From 34776b24c07c2b96dc9d71f902de8e75f6ace8c1 Mon Sep 17 00:00:00 2001 From: Andre Bernet Date: Thu, 16 Jan 2014 00:02:18 +0100 Subject: [PATCH 001/285] Mike's bootloader added --- radio/src/Makefile | 1 + radio/src/bootflashX.lbm | 1939 +++++++++++++++++ radio/src/loadboot.cpp | 168 ++ .../Source/Templates/system_stm32f2xx.c | 4 +- radio/src/targets/taranis/stm32_flash.ld | 15 +- 5 files changed, 2124 insertions(+), 3 deletions(-) create mode 100644 radio/src/bootflashX.lbm create mode 100644 radio/src/loadboot.cpp diff --git a/radio/src/Makefile b/radio/src/Makefile index 7e49bf5ab..c5bf64f12 100644 --- a/radio/src/Makefile +++ b/radio/src/Makefile @@ -614,6 +614,7 @@ ifeq ($(PCB), TARANIS) CPPSRC += audio_arm.cpp CPPSRC += targets/taranis/pwr_driver.cpp targets/taranis/pulses_driver.cpp targets/taranis/keys_driver.cpp targets/taranis/adc_driver.cpp targets/taranis/trainer_driver.cpp targets/taranis/audio_driver.cpp targets/taranis/delays.cpp targets/taranis/uart_driver.cpp targets/taranis/sport_driver.cpp CPPSRC += bmp.cpp gui/view_channels.cpp gui/view_about.cpp gui/view_text.cpp + CPPSRC += loadboot.cpp SRC += targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c SRC += targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/misc.c SRC += targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_gpio.c diff --git a/radio/src/bootflashX.lbm b/radio/src/bootflashX.lbm new file mode 100644 index 000000000..88ef5f552 --- /dev/null +++ b/radio/src/bootflashX.lbm @@ -0,0 +1,1939 @@ +0x00,0x00,0x02,0x20,0xe5,0x63,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, +0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x29,0x64,0x00,0x20, +0x29,0x64,0x00,0x20,0x00,0x00,0x00,0x00,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, +0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, +0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, +0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, +0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, +0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, +0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, +0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, +0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, +0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, +0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, +0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, +0x29,0x64,0x00,0x20,0x0d,0x5e,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, +0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, +0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, +0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, +0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, +0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x59,0x5d,0x00,0x20, +0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, +0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, +0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, +0x29,0x64,0x00,0x20,0x48,0x77,0x00,0x20,0x48,0x77,0x00,0x20,0x14,0x79,0x00,0x20, +0x14,0x79,0x00,0x20,0x38,0xb0,0x00,0x20,0x35,0x4b,0x82,0xb0,0x1a,0x68,0x42,0xf0, +0x01,0x02,0x1a,0x60,0x00,0x22,0x9a,0x60,0x19,0x68,0x21,0xf0,0x84,0x71,0x21,0xf4, +0x80,0x31,0x19,0x60,0x2f,0x49,0x59,0x60,0x19,0x68,0x21,0xf4,0x80,0x21,0x19,0x60, +0xda,0x60,0x00,0x92,0x01,0x92,0x1a,0x68,0x42,0xf4,0x80,0x32,0x1a,0x60,0x1a,0x68, +0x02,0xf4,0x00,0x32,0x01,0x92,0x00,0x9a,0x01,0x32,0x00,0x92,0x01,0x9a,0x1a,0xb9, +0x00,0x9a,0xb2,0xf5,0xa0,0x6f,0xf2,0xd1,0x21,0x4b,0x1b,0x68,0x13,0xf4,0x00,0x33, +0x18,0xbf,0x01,0x23,0x01,0x93,0x01,0x9b,0x01,0x2b,0x25,0xd1,0x1c,0x4b,0x9a,0x68, +0x9a,0x60,0x9a,0x68,0x42,0xf4,0x00,0x42,0x9a,0x60,0x9a,0x68,0x42,0xf4,0xa0,0x52, +0x9a,0x60,0x19,0x4a,0x5a,0x60,0x1a,0x68,0x42,0xf0,0x80,0x72,0x1a,0x60,0x19,0x68, +0x13,0x4a,0x89,0x01,0xfb,0xd5,0x15,0x4b,0x40,0xf2,0x03,0x71,0x19,0x60,0x93,0x68, +0x23,0xf0,0x03,0x03,0x93,0x60,0x93,0x68,0x43,0xf0,0x02,0x03,0x93,0x60,0x93,0x68, +0x03,0xf0,0x0c,0x03,0x08,0x2b,0xfa,0xd1,0x0d,0x4a,0x0e,0x4b,0x1a,0x60,0x0e,0x4a, +0x0e,0x4b,0x1a,0x60,0x0e,0x4a,0x0f,0x4b,0x1a,0x60,0x0f,0x4a,0x02,0x23,0x13,0x60, +0x0e,0x4a,0x13,0x60,0x0e,0x4b,0x0f,0x4a,0x9a,0x60,0x02,0xb0,0x70,0x47,0x00,0xbf, +0x00,0x38,0x02,0x40,0x10,0x30,0x00,0x24,0x0c,0x3c,0x41,0x05,0x00,0x3c,0x02,0x40, +0x00,0x87,0x93,0x03,0x6c,0x9f,0x00,0x20,0xc0,0xe1,0xe4,0x00,0x70,0x9f,0x00,0x20, +0x80,0xc3,0xc9,0x01,0x7c,0x9f,0x00,0x20,0x74,0x9f,0x00,0x20,0x78,0x9f,0x00,0x20, +0x00,0xed,0x00,0xe0,0x00,0x00,0x00,0x20,0x18,0x4b,0x19,0x4a,0x99,0x68,0x01,0xf0, +0x0c,0x01,0x04,0x29,0x08,0xbf,0x17,0x4b,0x1b,0xd0,0x08,0x29,0x18,0xbf,0x16,0x4b, +0x17,0xd1,0x59,0x68,0x5a,0x68,0x11,0xf4,0x80,0x0f,0x59,0x68,0x14,0xbf,0x11,0x4b, +0x11,0x4b,0x02,0xf0,0x3f,0x02,0xb3,0xfb,0xf2,0xf3,0x0c,0x4a,0xc1,0xf3,0x88,0x11, +0x52,0x68,0x4b,0x43,0xc2,0xf3,0x01,0x42,0x01,0x32,0x52,0x00,0xb3,0xfb,0xf2,0xf3, +0x07,0x4a,0x13,0x60,0x05,0x4b,0x9a,0x68,0x05,0x4b,0xc2,0xf3,0x03,0x12,0x9a,0x18, +0x12,0x79,0x19,0x68,0x31,0xfa,0x02,0xf2,0x1a,0x60,0x70,0x47,0x00,0x38,0x02,0x40, +0x48,0x77,0x00,0x20,0x00,0x1b,0xb7,0x00,0x00,0x24,0xf4,0x00,0x0a,0x4b,0x1a,0x68, +0x42,0xf0,0x01,0x02,0x1a,0x60,0x00,0x22,0x9a,0x60,0x19,0x68,0x21,0xf0,0x84,0x71, +0x21,0xf4,0x80,0x31,0x19,0x60,0x05,0x49,0x59,0x60,0x19,0x68,0x21,0xf4,0x80,0x21, +0x19,0x60,0xda,0x60,0x70,0x47,0x00,0xbf,0x00,0x38,0x02,0x40,0x10,0x30,0x00,0x24, +0x02,0x4b,0x00,0x22,0x1a,0x70,0x18,0x70,0x70,0x47,0x00,0xbf,0x02,0x38,0x02,0x40, +0x03,0x4b,0x1a,0x68,0x22,0xf0,0xf8,0x02,0x42,0xea,0xc0,0x00,0x18,0x60,0x70,0x47, +0x00,0x38,0x02,0x40,0x01,0x4b,0x18,0x60,0x70,0x47,0x00,0xbf,0x00,0x00,0x47,0x42, +0x06,0x4b,0x00,0x22,0x01,0x28,0x1a,0x70,0x1a,0x70,0x02,0xd0,0x04,0x28,0x04,0xd1, +0x01,0xe0,0x18,0x70,0x70,0x47,0x05,0x22,0x1a,0x70,0x70,0x47,0x70,0x38,0x02,0x40, +0x01,0x4b,0x18,0x60,0x70,0x47,0x00,0xbf,0x80,0x0e,0x47,0x42,0x01,0x43,0x41,0xea, +0x82,0x12,0x00,0x99,0x42,0xea,0x01,0x61,0x5a,0x08,0x01,0x3a,0x02,0x4b,0x41,0xea, +0x02,0x42,0x5a,0x60,0x70,0x47,0x00,0xbf,0x00,0x38,0x02,0x40,0x01,0x4b,0x18,0x60, +0x70,0x47,0x00,0xbf,0x60,0x00,0x47,0x42,0x80,0x01,0x03,0x4b,0x40,0xea,0x01,0x70, +0xc3,0xf8,0x84,0x00,0x70,0x47,0x00,0xbf,0x00,0x38,0x02,0x40,0x01,0x4b,0x18,0x60, +0x70,0x47,0x00,0xbf,0x68,0x00,0x47,0x42,0x01,0x4b,0x18,0x60,0x70,0x47,0x00,0xbf, +0x4c,0x00,0x47,0x42,0x03,0x4b,0x9a,0x68,0x22,0xf0,0xec,0x62,0x10,0x43,0x08,0x43, +0x98,0x60,0x70,0x47,0x00,0x38,0x02,0x40,0x03,0x4b,0x9a,0x68,0x22,0xf0,0x78,0x42, +0x10,0x43,0x08,0x43,0x98,0x60,0x70,0x47,0x00,0x38,0x02,0x40,0x03,0x4b,0x9a,0x68, +0x22,0xf0,0x03,0x02,0x10,0x43,0x98,0x60,0x70,0x47,0x00,0xbf,0x00,0x38,0x02,0x40, +0x02,0x4b,0x98,0x68,0x00,0xf0,0x0c,0x00,0x70,0x47,0x00,0xbf,0x00,0x38,0x02,0x40, +0x03,0x4b,0x9a,0x68,0x22,0xf0,0xf0,0x02,0x10,0x43,0x98,0x60,0x70,0x47,0x00,0xbf, +0x00,0x38,0x02,0x40,0x03,0x4b,0x9a,0x68,0x22,0xf4,0xe0,0x52,0x10,0x43,0x98,0x60, +0x70,0x47,0x00,0xbf,0x00,0x38,0x02,0x40,0x03,0x4b,0x9a,0x68,0x22,0xf4,0x60,0x42, +0x42,0xea,0xc0,0x00,0x98,0x60,0x70,0x47,0x00,0x38,0x02,0x40,0x10,0xb5,0x1e,0x4b, +0x9a,0x68,0x02,0xf0,0x0c,0x02,0x04,0x2a,0x08,0xbf,0x1c,0x4b,0x1a,0xd0,0x08,0x2a, +0x18,0xbf,0x1b,0x4b,0x16,0xd1,0x59,0x68,0x5a,0x68,0x11,0xf4,0x80,0x0f,0x59,0x68, +0x14,0xbf,0x16,0x4b,0x16,0x4b,0x02,0xf0,0x3f,0x02,0xb3,0xfb,0xf2,0xf3,0x12,0x4a, +0xc1,0xf3,0x88,0x11,0x52,0x68,0x4b,0x43,0xc2,0xf3,0x01,0x42,0x01,0x32,0x52,0x00, +0xb3,0xfb,0xf2,0xf3,0x0c,0x49,0x03,0x60,0x8b,0x68,0x0e,0x4a,0xc3,0xf3,0x03,0x13, +0xd3,0x5c,0x04,0x68,0x34,0xfa,0x03,0xf3,0x43,0x60,0x8c,0x68,0xc4,0xf3,0x82,0x24, +0x14,0x5d,0x33,0xfa,0x04,0xf4,0x84,0x60,0x89,0x68,0xc1,0xf3,0x42,0x31,0x52,0x5c, +0xd3,0x40,0xc3,0x60,0x10,0xbd,0x00,0xbf,0x00,0x38,0x02,0x40,0x00,0x1b,0xb7,0x00, +0x00,0x24,0xf4,0x00,0x5c,0x77,0x00,0x20,0x00,0xf4,0x40,0x73,0xb3,0xf5,0x40,0x7f, +0x08,0x4b,0x08,0xd1,0x99,0x68,0x20,0xf0,0x70,0x42,0x21,0xf4,0xf8,0x11,0x22,0xf4, +0x40,0x72,0x0a,0x43,0x9a,0x60,0x1a,0x6f,0x00,0x05,0x42,0xea,0x10,0x50,0x18,0x67, +0x70,0x47,0x00,0xbf,0x00,0x38,0x02,0x40,0x01,0x4b,0x18,0x60,0x70,0x47,0x00,0xbf, +0x3c,0x0e,0x47,0x42,0x01,0x4b,0x18,0x60,0x70,0x47,0x00,0xbf,0x40,0x0e,0x47,0x42, +0x01,0x4b,0x18,0x60,0x70,0x47,0x00,0xbf,0x5c,0x01,0x47,0x42,0x04,0x4b,0x1a,0x6b, +0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea,0x00,0x00,0x18,0x63,0x70,0x47,0x00,0xbf, +0x00,0x38,0x02,0x40,0x04,0x4b,0x5a,0x6b,0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea, +0x00,0x00,0x58,0x63,0x70,0x47,0x00,0xbf,0x00,0x38,0x02,0x40,0x04,0x4b,0x9a,0x6b, +0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea,0x00,0x00,0x98,0x63,0x70,0x47,0x00,0xbf, +0x00,0x38,0x02,0x40,0x04,0x4b,0x1a,0x6c,0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea, +0x00,0x00,0x18,0x64,0x70,0x47,0x00,0xbf,0x00,0x38,0x02,0x40,0x04,0x4b,0x5a,0x6c, +0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea,0x00,0x00,0x58,0x64,0x70,0x47,0x00,0xbf, +0x00,0x38,0x02,0x40,0x04,0x4b,0x1a,0x69,0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea, +0x00,0x00,0x18,0x61,0x70,0x47,0x00,0xbf,0x00,0x38,0x02,0x40,0x04,0x4b,0x5a,0x69, +0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea,0x00,0x00,0x58,0x61,0x70,0x47,0x00,0xbf, +0x00,0x38,0x02,0x40,0x04,0x4b,0x9a,0x69,0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea, +0x00,0x00,0x98,0x61,0x70,0x47,0x00,0xbf,0x00,0x38,0x02,0x40,0x04,0x4b,0x1a,0x6a, +0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea,0x00,0x00,0x18,0x62,0x70,0x47,0x00,0xbf, +0x00,0x38,0x02,0x40,0x04,0x4b,0x5a,0x6a,0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea, +0x00,0x00,0x58,0x62,0x70,0x47,0x00,0xbf,0x00,0x38,0x02,0x40,0x04,0x4b,0x1a,0x6d, +0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea,0x00,0x00,0x18,0x65,0x70,0x47,0x00,0xbf, +0x00,0x38,0x02,0x40,0x04,0x4b,0x5a,0x6d,0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea, +0x00,0x00,0x58,0x65,0x70,0x47,0x00,0xbf,0x00,0x38,0x02,0x40,0x04,0x4b,0x9a,0x6d, +0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea,0x00,0x00,0x98,0x65,0x70,0x47,0x00,0xbf, +0x00,0x38,0x02,0x40,0x04,0x4b,0x1a,0x6e,0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea, +0x00,0x00,0x18,0x66,0x70,0x47,0x00,0xbf,0x00,0x38,0x02,0x40,0x04,0x4b,0x5a,0x6e, +0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea,0x00,0x00,0x58,0x66,0x70,0x47,0x00,0xbf, +0x00,0x38,0x02,0x40,0x04,0x4b,0x1a,0x78,0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea, +0x00,0x00,0x18,0x70,0x70,0x47,0x00,0xbf,0x0d,0x38,0x02,0x40,0x43,0x09,0x08,0x4a, +0x01,0x2b,0x08,0xbf,0x13,0x68,0x03,0xd0,0x02,0x2b,0x0c,0xbf,0x13,0x6f,0x53,0x6f, +0x00,0xf0,0x1f,0x00,0x33,0xfa,0x00,0xf0,0x00,0xf0,0x01,0x00,0x70,0x47,0x00,0xbf, +0x00,0x38,0x02,0x40,0x07,0xb5,0x00,0x23,0x01,0x93,0x31,0x20,0xff,0xf7,0xe6,0xff, +0x01,0x9b,0x01,0x33,0x01,0x93,0x01,0x9b,0xb3,0xf5,0xa0,0x6f,0x01,0xd0,0x00,0x28, +0xf3,0xd0,0x31,0x20,0xff,0xf7,0xda,0xff,0x00,0x30,0x18,0xbf,0x01,0x20,0x0e,0xbd, +0x02,0x4b,0x5a,0x6f,0x42,0xf0,0x80,0x72,0x5a,0x67,0x70,0x47,0x00,0x38,0x02,0x40, +0x03,0x4b,0xdb,0x68,0x18,0x42,0x0c,0xbf,0x00,0x20,0x01,0x20,0x70,0x47,0x00,0xbf, +0x00,0x38,0x02,0x40,0x01,0x4b,0x18,0x70,0x70,0x47,0x00,0xbf,0x0e,0x38,0x02,0x40, +0x08,0xb5,0x2c,0x4b,0x98,0x42,0x05,0xd1,0x01,0x20,0x01,0x46,0xff,0xf7,0x32,0xff, +0x01,0x20,0x48,0xe0,0x28,0x4b,0x98,0x42,0x05,0xd1,0x02,0x20,0x01,0x21,0xff,0xf7, +0x29,0xff,0x02,0x20,0x3f,0xe0,0x25,0x4b,0x98,0x42,0x05,0xd1,0x04,0x20,0x01,0x21, +0xff,0xf7,0x20,0xff,0x04,0x20,0x36,0xe0,0x21,0x4b,0x98,0x42,0x05,0xd1,0x08,0x20, +0x01,0x21,0xff,0xf7,0x17,0xff,0x08,0x20,0x2d,0xe0,0x1e,0x4b,0x98,0x42,0x05,0xd1, +0x10,0x20,0x01,0x21,0xff,0xf7,0x0e,0xff,0x10,0x20,0x24,0xe0,0x1a,0x4b,0x98,0x42, +0x05,0xd1,0x20,0x20,0x01,0x21,0xff,0xf7,0x05,0xff,0x20,0x20,0x1b,0xe0,0x17,0x4b, +0x98,0x42,0x05,0xd1,0x40,0x20,0x01,0x21,0xff,0xf7,0xfc,0xfe,0x40,0x20,0x12,0xe0, +0x13,0x4b,0x98,0x42,0x05,0xd1,0x80,0x20,0x01,0x21,0xff,0xf7,0xf3,0xfe,0x80,0x20, +0x09,0xe0,0x10,0x4b,0x98,0x42,0x0b,0xd1,0x4f,0xf4,0x80,0x70,0x01,0x21,0xff,0xf7, +0xe9,0xfe,0x4f,0xf4,0x80,0x70,0x00,0x21,0xbd,0xe8,0x08,0x40,0xff,0xf7,0xe2,0xbe, +0x08,0xbd,0x00,0xbf,0x00,0x00,0x02,0x40,0x00,0x04,0x02,0x40,0x00,0x08,0x02,0x40, +0x00,0x0c,0x02,0x40,0x00,0x10,0x02,0x40,0x00,0x14,0x02,0x40,0x00,0x18,0x02,0x40, +0x00,0x1c,0x02,0x40,0x00,0x20,0x02,0x40,0x2d,0xe9,0xf0,0x47,0x00,0x23,0xd1,0xf8, +0x00,0x80,0x1a,0x46,0x4f,0xf0,0x01,0x0c,0x03,0x27,0x0c,0xfa,0x02,0xf4,0x04,0xea, +0x08,0x05,0xa5,0x42,0x2f,0xd1,0x17,0xfa,0x03,0xf4,0x06,0x68,0xe4,0x43,0x26,0x40, +0x06,0x60,0x0e,0x79,0xd0,0xf8,0x00,0x90,0x06,0xfa,0x03,0xfa,0x01,0x3e,0xf6,0xb2, +0x4a,0xea,0x09,0x09,0x01,0x2e,0xc0,0xf8,0x00,0x90,0x14,0xd8,0x91,0xf8,0x05,0x90, +0x86,0x68,0x09,0xfa,0x03,0xf9,0x26,0x40,0x86,0x60,0x86,0x68,0x49,0xea,0x06,0x06, +0x86,0x60,0x46,0x68,0x26,0xea,0x05,0x05,0x45,0x60,0x8d,0x79,0x46,0x68,0x95,0x40, +0xad,0xb2,0x35,0x43,0x45,0x60,0xc5,0x68,0x2c,0x40,0xc4,0x60,0xcc,0x79,0xc5,0x68, +0x9c,0x40,0x2c,0x43,0xc4,0x60,0x01,0x32,0x02,0x33,0x10,0x2a,0xc5,0xd1,0xbd,0xe8, +0xf0,0x87,0x4f,0xf6,0xff,0x73,0x03,0x60,0x00,0x23,0x03,0x71,0x43,0x71,0x83,0x71, +0xc3,0x71,0x70,0x47,0x82,0xb0,0x4f,0xf4,0x80,0x33,0x01,0x93,0x01,0x9b,0x0b,0x43, +0x01,0x93,0x01,0x9b,0xc3,0x61,0xc1,0x61,0x01,0x9b,0xc3,0x61,0xc3,0x69,0x01,0x93, +0xc3,0x69,0x01,0x93,0x02,0xb0,0x70,0x47,0x03,0x69,0x19,0x42,0x0c,0xbf,0x00,0x20, +0x01,0x20,0x70,0x47,0x00,0x69,0x80,0xb2,0x70,0x47,0x43,0x69,0x19,0x42,0x0c,0xbf, +0x00,0x20,0x01,0x20,0x70,0x47,0x40,0x69,0x80,0xb2,0x70,0x47,0x01,0x83,0x70,0x47, +0x41,0x83,0x70,0x47,0x0a,0xb1,0x01,0x83,0x70,0x47,0x41,0x83,0x70,0x47,0x41,0x61, +0x70,0x47,0x43,0x69,0x59,0x40,0x41,0x61,0x70,0x47,0x01,0xf0,0x07,0x03,0x30,0xb5, +0x9b,0x00,0x0f,0x24,0x9c,0x40,0x12,0xfa,0x03,0xf3,0xc9,0x08,0x08,0x31,0x50,0xf8, +0x21,0x50,0x25,0xea,0x04,0x04,0x40,0xf8,0x21,0x40,0x50,0xf8,0x21,0x40,0x23,0x43, +0x40,0xf8,0x21,0x30,0x30,0xbd,0x00,0xbf,0x08,0xb5,0x15,0x4b,0x98,0x42,0x0b,0xd1, +0x01,0x21,0x4f,0xf4,0x80,0x50,0xff,0xf7,0x5d,0xfe,0x4f,0xf4,0x80,0x50,0x00,0x21, +0xbd,0xe8,0x08,0x40,0xff,0xf7,0x56,0xbe,0x0e,0x4b,0x98,0x42,0x07,0xd1,0x4f,0xf4, +0x80,0x40,0x01,0x21,0xff,0xf7,0x42,0xfe,0x4f,0xf4,0x80,0x40,0x09,0xe0,0x0a,0x4b, +0x98,0x42,0x0b,0xd1,0x4f,0xf4,0x00,0x40,0x01,0x21,0xff,0xf7,0x37,0xfe,0x4f,0xf4, +0x00,0x40,0x00,0x21,0xbd,0xe8,0x08,0x40,0xff,0xf7,0x30,0xbe,0x08,0xbd,0x00,0xbf, +0x00,0x30,0x01,0x40,0x00,0x38,0x00,0x40,0x00,0x3c,0x00,0x40,0x0b,0x88,0x10,0xb5, +0x4c,0x88,0x02,0x88,0x23,0x43,0x8c,0x88,0x02,0xf4,0x41,0x52,0x23,0x43,0xcc,0x88, +0x23,0x43,0x0c,0x89,0x23,0x43,0x4c,0x89,0x23,0x43,0x8c,0x89,0x23,0x43,0xcc,0x89, +0x23,0x43,0x13,0x43,0x9b,0xb2,0x03,0x80,0x83,0x8b,0x23,0xf4,0x00,0x63,0x1b,0x04, +0x1b,0x0c,0x83,0x83,0x0b,0x8a,0x03,0x82,0x10,0xbd,0x83,0x8b,0xf0,0xb5,0x23,0xf4, +0x7a,0x63,0x23,0xf0,0x1f,0x03,0x1b,0x04,0x1b,0x0c,0x83,0x83,0x02,0x23,0x03,0x84, +0x8b,0x68,0x85,0x8b,0x00,0x22,0x02,0x2b,0xad,0xb2,0x38,0xd0,0x28,0x4a,0x8e,0x88, +0x94,0x68,0x00,0x2e,0x14,0xbf,0x02,0x26,0x01,0x26,0x24,0x02,0x48,0xbf,0x94,0x68, +0xdf,0xf8,0x90,0xc0,0x44,0xbf,0x24,0xf4,0x00,0x04,0x94,0x60,0xd2,0xf8,0x84,0x40, +0xd2,0xf8,0x84,0x70,0x52,0x68,0xc4,0xf3,0x88,0x14,0x02,0xf0,0x3f,0x02,0xbc,0xfb, +0xf2,0xf2,0x54,0x43,0xc7,0xf3,0x02,0x72,0xb4,0xfb,0xf2,0xf4,0xca,0x88,0xb2,0xf5, +0x00,0x7f,0x4f,0xf0,0x0a,0x02,0x01,0xd1,0x24,0x0a,0x02,0xe0,0x76,0x01,0xb4,0xfb, +0xf6,0xf4,0x62,0x43,0xb2,0xfb,0xf3,0xf3,0x05,0x33,0x0a,0x22,0x9b,0xb2,0xb3,0xfb, +0xf2,0xf3,0x03,0xf0,0x01,0x02,0x12,0x02,0xc3,0xf3,0x4f,0x03,0x92,0xb2,0x9c,0x1e, +0xa4,0xb2,0xfe,0x2c,0x28,0xbf,0x00,0x22,0xcc,0x88,0x28,0xbf,0x02,0x23,0x13,0x43, +0x23,0x43,0x9b,0xb2,0x03,0x84,0x0b,0x88,0x4a,0x88,0x2b,0x43,0x43,0xf4,0x00,0x63, +0x13,0x43,0x8a,0x88,0x13,0x43,0x8a,0x89,0x13,0x43,0x9b,0xb2,0x83,0x83,0xf0,0xbd, +0x00,0x38,0x02,0x40,0x00,0x1b,0xb7,0x00,0x00,0x23,0x03,0x80,0x43,0x80,0x83,0x80, +0xc3,0x80,0x03,0x81,0x43,0x81,0x83,0x81,0xc3,0x81,0x07,0x23,0x03,0x82,0x70,0x47, +0x00,0x23,0x02,0x22,0x03,0x80,0x43,0x80,0x83,0x80,0xc3,0x80,0x82,0x60,0x83,0x81, +0x70,0x47,0x03,0x88,0x19,0xb1,0x9b,0xb2,0x43,0xf0,0x40,0x03,0x03,0xe0,0x23,0xf0, +0x40,0x03,0x1b,0x04,0x1b,0x0c,0x03,0x80,0x70,0x47,0x83,0x8b,0x19,0xb1,0x9b,0xb2, +0x43,0xf4,0x80,0x63,0x03,0xe0,0x23,0xf4,0x80,0x63,0x1b,0x04,0x1b,0x0c,0x83,0x83, +0x70,0x47,0x03,0x88,0x23,0xf4,0x00,0x63,0x1b,0x04,0x1b,0x0c,0x03,0x80,0x03,0x88, +0x9b,0xb2,0x19,0x43,0x01,0x80,0x70,0x47,0x03,0x88,0xb1,0xf5,0x80,0x4f,0x04,0xbf, +0x9b,0xb2,0x43,0xf4,0x80,0x43,0x03,0xd0,0x23,0xf4,0x80,0x43,0x1b,0x04,0x1b,0x0c, +0x03,0x80,0x70,0x47,0x4f,0xf6,0xff,0x63,0x99,0x42,0x03,0x88,0x1c,0xbf,0x9b,0xb2, +0x43,0xf4,0x80,0x73,0x03,0xd1,0x23,0xf4,0x80,0x73,0x1b,0x04,0x1b,0x0c,0x03,0x80, +0x70,0x47,0x83,0x88,0x19,0xb1,0x9b,0xb2,0x43,0xf0,0x04,0x03,0x03,0xe0,0x23,0xf0, +0x04,0x03,0x1b,0x04,0x1b,0x0c,0x83,0x80,0x70,0x47,0x83,0x88,0x19,0xb1,0x9b,0xb2, +0x43,0xf0,0x10,0x03,0x03,0xe0,0x23,0xf0,0x10,0x03,0x1b,0x04,0x1b,0x0c,0x83,0x80, +0x70,0x47,0x80,0x89,0x80,0xb2,0x70,0x47,0x81,0x81,0x70,0x47,0x03,0x88,0x19,0xb1, +0x9b,0xb2,0x43,0xf4,0x00,0x53,0x03,0xe0,0x23,0xf4,0x00,0x53,0x1b,0x04,0x1b,0x0c, +0x03,0x80,0x70,0x47,0x03,0x88,0x9b,0xb2,0x43,0xf4,0x80,0x53,0x03,0x80,0x70,0x47, +0x01,0x29,0x15,0xbf,0x00,0x8b,0x80,0x8a,0x80,0xb2,0x80,0xb2,0x70,0x47,0x00,0x8a, +0x80,0xb2,0x70,0x47,0x83,0x88,0x9b,0xb2,0x0a,0xb1,0x19,0x43,0x01,0xe0,0x23,0xea, +0x01,0x01,0x81,0x80,0x70,0x47,0x01,0x23,0x09,0x09,0x13,0xfa,0x01,0xf1,0x83,0x88, +0x89,0xb2,0x9b,0xb2,0x0a,0xb1,0x19,0x43,0x01,0xe0,0x23,0xea,0x01,0x01,0x81,0x80, +0x70,0x47,0x03,0x89,0x19,0x42,0x0c,0xbf,0x00,0x20,0x01,0x20,0x70,0x47,0xc9,0x43, +0x89,0xb2,0x01,0x81,0x70,0x47,0x01,0x23,0x01,0xf0,0x0f,0x02,0x13,0xfa,0x02,0xf2, +0x10,0xb5,0x84,0x88,0x00,0x89,0xa4,0xb2,0x80,0xb2,0x10,0x40,0x05,0xd0,0x09,0x09, +0x8b,0x40,0x1c,0x42,0x0c,0xbf,0x00,0x20,0x01,0x20,0x10,0xbd,0x01,0xf0,0x0f,0x01, +0x01,0x23,0x8b,0x40,0xdb,0x43,0x9b,0xb2,0x03,0x81,0x70,0x47,0x40,0xf0,0xbe,0x60, +0x02,0x4b,0x40,0xf4,0x20,0x20,0xd8,0x60,0x70,0x47,0x00,0xbf,0x00,0xed,0x00,0xe0, +0xc3,0x78,0x10,0xb5,0xfb,0xb1,0x16,0x4b,0x42,0x78,0xdb,0x68,0x84,0x78,0xdb,0x43, +0xc3,0xf3,0x02,0x23,0xc3,0xf1,0x04,0x01,0xc9,0xb2,0x12,0xfa,0x01,0xf1,0x0f,0x22, +0x1a,0x41,0xc9,0xb2,0x22,0x40,0x0a,0x43,0x0e,0x4b,0x01,0x78,0x12,0x01,0xcb,0x18, +0xd2,0xb2,0x83,0xf8,0x00,0x23,0x03,0x78,0x01,0x22,0x59,0x09,0x03,0xf0,0x1f,0x03, +0x12,0xfa,0x03,0xf3,0x07,0xe0,0x03,0x78,0x01,0x22,0x59,0x09,0x03,0xf0,0x1f,0x03, +0x12,0xfa,0x03,0xf3,0x20,0x31,0x03,0x4a,0x42,0xf8,0x21,0x30,0x10,0xbd,0x00,0xbf, +0x00,0xed,0x00,0xe0,0x00,0xe1,0x00,0xe0,0x21,0xf0,0x60,0x41,0x21,0xf0,0x7f,0x01, +0x01,0x4b,0x08,0x43,0x98,0x60,0x70,0x47,0x00,0xed,0x00,0xe0,0x04,0x4b,0x1a,0x69, +0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea,0x00,0x00,0x18,0x61,0x70,0x47,0x00,0xbf, +0x00,0xed,0x00,0xe0,0x04,0x4b,0x04,0x28,0x1a,0x68,0x0c,0xbf,0x42,0xf0,0x04,0x02, +0x22,0xf0,0x04,0x02,0x1a,0x60,0x70,0x47,0x10,0xe0,0x00,0xe0,0x37,0xb5,0x00,0x23, +0x10,0x4c,0x05,0x46,0x01,0x93,0x03,0x20,0x02,0xf0,0xc2,0xf8,0x2b,0x68,0x01,0x3c, +0x1a,0x69,0x01,0x92,0x13,0xd0,0x01,0x9a,0x00,0x2a,0xf4,0xda,0x01,0x9a,0x42,0xf0, +0x01,0x02,0x01,0x92,0x01,0x9a,0x1a,0x61,0x06,0x4a,0x19,0x69,0x01,0x3a,0x01,0x91, +0x02,0xd0,0x01,0x99,0xc9,0x07,0xf8,0xd4,0x03,0x20,0x02,0xf0,0xa9,0xf8,0x00,0x20, +0x3e,0xbd,0x00,0xbf,0x41,0x0d,0x03,0x00,0x10,0xb5,0xc4,0x78,0x74,0xb9,0x00,0xeb, +0x82,0x00,0x03,0x33,0x9b,0x10,0xd0,0xf8,0xd0,0x00,0x22,0x46,0x03,0xe0,0x51,0xf8, +0x04,0x4c,0x01,0x32,0x04,0x60,0x04,0x31,0x9a,0x42,0xf8,0xd1,0x00,0x20,0x10,0xbd, +0x03,0x32,0x30,0xb5,0x92,0x10,0xd0,0xf8,0xd0,0x40,0x0b,0x46,0x00,0x20,0x03,0xe0, +0x25,0x68,0x01,0x30,0x43,0xf8,0x04,0x5c,0x04,0x33,0x90,0x42,0xf8,0xd1,0x01,0xeb, +0x80,0x00,0x30,0xbd,0x01,0x22,0xf0,0xb5,0x00,0x23,0x82,0x70,0x40,0x22,0x01,0x29, +0xc3,0x70,0x82,0x80,0x0c,0xd1,0x08,0x23,0x03,0x70,0x04,0x23,0x43,0x70,0x4f,0xf4, +0xa0,0x73,0xc3,0x80,0x02,0x23,0x03,0x72,0xc1,0x72,0x4f,0xf0,0xa0,0x43,0x09,0xe0, +0x41,0xb9,0x0c,0x23,0x03,0x70,0x06,0x23,0x43,0x70,0x4f,0xf4,0xa0,0x62,0x20,0x4b, +0xc1,0x72,0xc2,0x80,0x03,0xf5,0x00,0x62,0x02,0x61,0xc3,0x60,0x46,0x78,0x04,0x46, +0x01,0x46,0x1a,0x46,0x00,0x25,0x08,0xe0,0x02,0xf5,0x10,0x6c,0x02,0xf5,0x30,0x62, +0x0a,0x65,0xc1,0xf8,0x14,0xc0,0x01,0x35,0x3a,0x46,0x04,0x31,0xb5,0x42,0x02,0xf1, +0x20,0x07,0xf1,0xd3,0x03,0xf5,0x80,0x62,0x42,0x61,0x03,0xf5,0x88,0x62,0xc0,0xf8, +0xcc,0x20,0x06,0x78,0x03,0xf5,0xa0,0x65,0x01,0x46,0x00,0x22,0x03,0xe0,0xc1,0xf8, +0x8c,0x50,0x01,0x32,0x20,0x35,0x04,0x31,0xb2,0x42,0xf8,0xd3,0x19,0x46,0x00,0x22, +0x02,0xe0,0xc4,0xf8,0xcc,0x10,0x01,0x32,0x04,0x34,0xb2,0x42,0x01,0xf5,0x80,0x51, +0xf7,0xd3,0x03,0xf5,0x60,0x63,0xc0,0xf8,0x0c,0x31,0x00,0x20,0xf0,0xbd,0x00,0xbf, +0x00,0x00,0x04,0x40,0x38,0xb5,0x03,0x7a,0x00,0x25,0x01,0x2b,0x04,0x46,0xc2,0x68, +0x20,0xd1,0x93,0x6b,0x41,0x7a,0x65,0xf3,0x10,0x43,0x09,0xb1,0x43,0xf4,0x80,0x13, +0x93,0x63,0xd3,0x68,0x04,0xf1,0x0c,0x00,0x6f,0xf3,0x86,0x13,0x6f,0xf3,0x96,0x53, +0x6f,0xf3,0x51,0x43,0x6f,0xf3,0xd3,0x43,0xd3,0x60,0xff,0xf7,0x37,0xff,0xe3,0x78, +0x01,0x2b,0x1b,0xd1,0x05,0x23,0x63,0xf3,0x44,0x05,0xe3,0x68,0x45,0xf0,0x20,0x05, +0x9d,0x60,0x13,0xe0,0xd3,0x68,0x00,0xf1,0x0c,0x00,0x43,0xf0,0x40,0x03,0xd3,0x60, +0xff,0xf7,0x24,0xff,0x63,0x7a,0xe2,0x68,0x00,0x2b,0x0c,0xbf,0x4f,0xf4,0x50,0x23, +0x4f,0xf4,0xe8,0x13,0x93,0x63,0x14,0x20,0x01,0xf0,0xf2,0xff,0xe3,0x78,0x01,0x2b, +0x07,0xd1,0xe3,0x68,0x05,0x22,0x9d,0x68,0x62,0xf3,0x44,0x05,0x45,0xf0,0x20,0x05, +0x9d,0x60,0x00,0x20,0x38,0xbd,0xc3,0x68,0x00,0x20,0x9a,0x68,0x42,0xf0,0x01,0x02, +0x9a,0x60,0x70,0x47,0xc3,0x68,0x00,0x20,0x9a,0x68,0x22,0xf0,0x01,0x02,0x9a,0x60, +0x70,0x47,0x07,0xb5,0x00,0x23,0x01,0x93,0x01,0x9b,0x43,0xf0,0x20,0x03,0x01,0x93, +0x01,0x9b,0x61,0xf3,0x8a,0x13,0x01,0x93,0x01,0x9b,0xc2,0x68,0x13,0x61,0x06,0x4b, +0x11,0x69,0x01,0x3b,0x01,0x91,0x02,0xd0,0x01,0x99,0x88,0x06,0xf8,0xd4,0x03,0x20, +0x01,0xf0,0xae,0xff,0x00,0x20,0x0e,0xbd,0x41,0x0d,0x03,0x00,0x07,0xb5,0x00,0x23, +0x01,0x93,0x01,0x9b,0x43,0xf0,0x10,0x03,0x01,0x93,0x01,0x9b,0xc2,0x68,0x13,0x61, +0x06,0x4b,0x11,0x69,0x01,0x3b,0x01,0x91,0x02,0xd0,0x01,0x99,0xc9,0x06,0xf8,0xd4, +0x03,0x20,0x01,0xf0,0x95,0xff,0x00,0x20,0x0e,0xbd,0x00,0xbf,0x41,0x0d,0x03,0x00, +0x08,0xb5,0xc2,0x68,0x01,0x29,0xd3,0x68,0x6f,0xf3,0x5d,0x73,0x6f,0xf3,0x9e,0x73, +0x08,0xbf,0x43,0xf0,0x00,0x53,0x02,0xd0,0x09,0xb9,0x43,0xf0,0x80,0x43,0x32,0x20, +0xd3,0x60,0x01,0xf0,0x8d,0xff,0x00,0x20,0x08,0xbd,0xc3,0x68,0x58,0x69,0x00,0xf0, +0x01,0x00,0x70,0x47,0xc3,0x68,0x5b,0x69,0x13,0xf0,0x01,0x0f,0x14,0xbf,0x00,0x20, +0x01,0x20,0x70,0x47,0xc3,0x68,0x58,0x69,0x00,0xf0,0x01,0x00,0x70,0x47,0xc3,0x68, +0x5a,0x69,0x98,0x69,0x10,0x40,0x70,0x47,0xc3,0x68,0x58,0x68,0x70,0x47,0x03,0x69, +0x1a,0x68,0x61,0xf3,0x01,0x02,0x1a,0x60,0x70,0x47,0xc2,0x68,0x00,0x23,0x93,0x61, +0x4f,0xf0,0xff,0x31,0x6f,0xf0,0x80,0x43,0x53,0x61,0x51,0x60,0x53,0x61,0x0c,0x4b, +0x93,0x61,0xc3,0x78,0x91,0x69,0x00,0x2b,0x14,0xbf,0x4f,0xf4,0x00,0x63,0x4f,0xf4, +0x01,0x63,0x43,0xf0,0x80,0x43,0x43,0xf4,0x70,0x13,0x43,0xf4,0x40,0x53,0x43,0xf0, +0x0c,0x03,0x21,0xea,0x03,0x01,0x0b,0x43,0x93,0x61,0x00,0x20,0x70,0x47,0x00,0xbf, +0x00,0x08,0x00,0x80,0xf8,0xb5,0xd0,0xf8,0x0c,0x31,0x00,0x22,0x1a,0x60,0x03,0x69, +0x15,0x46,0x1a,0x68,0x04,0x46,0x65,0xf3,0xcc,0x22,0x1a,0x60,0xc3,0x7a,0x01,0x2b, +0x1b,0xd1,0x03,0x21,0xff,0xf7,0xc3,0xff,0xe3,0x68,0x80,0x21,0x4f,0xf4,0x80,0x02, +0x61,0xf3,0x0f,0x02,0x59,0x62,0x9a,0x62,0xc0,0x22,0x62,0xf3,0x0f,0x05,0x61,0xf3, +0x1f,0x45,0x4f,0xf4,0xa0,0x72,0xc3,0xf8,0x04,0x51,0x62,0xf3,0x0f,0x05,0x6f,0xf3, +0x1f,0x45,0xc3,0xf8,0x08,0x51,0xc3,0xf8,0x0c,0x51,0x10,0x21,0x20,0x46,0xff,0xf7, +0x40,0xff,0x20,0x46,0xff,0xf7,0x5a,0xff,0x22,0x69,0x00,0x23,0x4f,0xf0,0xff,0x31, +0x13,0x61,0x20,0x46,0x53,0x61,0x1e,0x46,0x91,0x61,0xff,0x25,0xd3,0x61,0x21,0x46, +0x10,0xe0,0x82,0x69,0x01,0x33,0x17,0x68,0x04,0x30,0xc7,0xf3,0x07,0x67,0x07,0xf0, +0x80,0x07,0xff,0xb2,0x00,0x2f,0x14,0xbf,0x4f,0xf0,0x90,0x47,0x00,0x27,0x17,0x60, +0x16,0x61,0x95,0x60,0x62,0x78,0x93,0x42,0xeb,0xd3,0x00,0x23,0x1d,0x46,0xff,0x20, +0x10,0xe0,0x4a,0x6d,0x01,0x33,0x16,0x68,0x04,0x31,0xc6,0xf3,0x07,0x66,0x06,0xf0, +0x80,0x06,0xf6,0xb2,0x00,0x2e,0x14,0xbf,0x4f,0xf0,0x90,0x46,0x00,0x26,0x16,0x60, +0x15,0x61,0x90,0x60,0x62,0x78,0x93,0x42,0xeb,0xd3,0x23,0x69,0x1a,0x69,0x42,0xf4, +0x80,0x72,0x1a,0x61,0xe2,0x78,0x01,0x2a,0x04,0xd1,0x05,0x4a,0x40,0x21,0x61,0xf3, +0x59,0x42,0x1a,0x63,0x20,0x46,0xff,0xf7,0x60,0xff,0x00,0x20,0xf8,0xbd,0x00,0xbf, +0x03,0x01,0x01,0x00,0x03,0x69,0x9b,0x68,0xc3,0xf3,0x41,0x03,0x5a,0x1e,0x02,0x2a, +0x9d,0xbf,0x03,0x4a,0xd3,0x18,0x13,0xf8,0x01,0x0c,0x03,0x20,0x70,0x47,0x00,0xbf, +0x6c,0x68,0x00,0x20,0x10,0xb5,0x03,0x69,0x81,0x69,0x9c,0x68,0x0a,0x68,0xc4,0xf3, +0x41,0x00,0x02,0x28,0x18,0xbf,0x6f,0xf3,0x0a,0x02,0x02,0xd1,0x03,0x20,0x60,0xf3, +0x0a,0x02,0x0a,0x60,0x5a,0x68,0x00,0x20,0x42,0xf4,0x80,0x72,0x5a,0x60,0x10,0xbd, +0x30,0xb5,0x4d,0x78,0x0b,0x78,0x00,0x22,0x01,0x2d,0x00,0xeb,0x83,0x04,0x05,0xd1, +0x15,0xfa,0x03,0xf3,0xa4,0x69,0x63,0xf3,0x0f,0x02,0x05,0xe0,0x01,0x25,0x15,0xfa, +0x03,0xf3,0x64,0x6d,0x63,0xf3,0x1f,0x42,0x23,0x68,0xc3,0xf3,0x07,0x25,0x05,0xf0, +0x80,0x05,0xed,0xb2,0x6d,0xb9,0x8d,0x68,0x65,0xf3,0x0a,0x03,0xcd,0x78,0xc9,0x88, +0x65,0xf3,0x93,0x43,0x61,0xf3,0x99,0x53,0x43,0xf0,0x80,0x53,0x43,0xf4,0x00,0x43, +0x23,0x60,0x03,0x69,0x00,0x20,0xd9,0x69,0x0a,0x43,0xda,0x61,0x30,0xbd,0x30,0xb5, +0x4d,0x78,0x0b,0x78,0x00,0x24,0x01,0x2d,0x22,0x46,0x00,0xeb,0x83,0x01,0x05,0xd1, +0x15,0xfa,0x03,0xf3,0x89,0x69,0x63,0xf3,0x0f,0x02,0x05,0xe0,0x01,0x25,0x15,0xfa, +0x03,0xf3,0x49,0x6d,0x63,0xf3,0x1f,0x42,0x03,0x69,0x6f,0xf3,0xcf,0x34,0x0c,0x60, +0xd9,0x69,0x00,0x20,0x21,0xea,0x02,0x02,0xda,0x61,0x30,0xbd,0xf8,0xb5,0x4f,0x78, +0x0b,0x78,0x01,0x2f,0x00,0xeb,0x83,0x03,0x49,0xd1,0x9e,0x69,0x4c,0x69,0x35,0x68, +0x33,0x69,0x2a,0x46,0x64,0xf3,0x12,0x03,0x14,0xb9,0x67,0xf3,0xdc,0x43,0x0b,0xe0, +0x8f,0x68,0xe4,0x19,0x01,0x3c,0xb4,0xfb,0xf7,0xf7,0xcc,0x78,0x67,0xf3,0xdc,0x43, +0x01,0x2c,0x08,0xbf,0x64,0xf3,0x5e,0x73,0x33,0x61,0xc3,0x78,0x01,0x2b,0x06,0xd1, +0x0b,0x78,0x0c,0x69,0x00,0xeb,0x83,0x03,0x9b,0x69,0x5c,0x61,0x0c,0xe0,0xcb,0x78, +0x01,0x2b,0x09,0xd0,0x4b,0x69,0x3b,0xb1,0x0c,0x78,0x01,0x27,0x17,0xfa,0x04,0xf4, +0x03,0x69,0x5e,0x6b,0x34,0x43,0x5c,0x63,0xcb,0x78,0x01,0x2b,0x07,0xd1,0x03,0x69, +0x9b,0x68,0xdb,0x05,0x54,0xbf,0x45,0xf0,0x00,0x52,0x45,0xf0,0x80,0x52,0x0b,0x78, +0x42,0xf0,0x04,0x42,0x00,0xeb,0x83,0x03,0x9b,0x69,0x1a,0x60,0xcb,0x78,0x01,0x2b, +0x38,0xd1,0x0a,0x78,0x8b,0x8a,0xc9,0x68,0xff,0xf7,0x4e,0xfd,0x32,0xe0,0x5e,0x6d, +0x4f,0x69,0x35,0x68,0x8c,0x68,0x2a,0x46,0x33,0x69,0x2f,0xb9,0x64,0xf3,0x12,0x03, +0x01,0x24,0x64,0xf3,0xdc,0x43,0x0a,0xe0,0x3f,0x19,0x01,0x3f,0xb7,0xfb,0xf4,0xf7, +0xbf,0x05,0xbf,0x0d,0x7c,0x43,0x67,0xf3,0xdc,0x43,0x64,0xf3,0x12,0x03,0x33,0x61, +0xc3,0x78,0x01,0x2b,0x01,0xbf,0x0b,0x78,0x0c,0x69,0x00,0xeb,0x83,0x03,0x5b,0x6d, +0x08,0xbf,0x5c,0x61,0xcb,0x78,0x01,0x2b,0x05,0xd1,0x4b,0x79,0x45,0xf0,0x00,0x52, +0x0b,0xb9,0x45,0xf0,0x80,0x52,0x0b,0x78,0x42,0xf0,0x04,0x42,0x00,0xeb,0x83,0x00, +0x43,0x6d,0x1a,0x60,0x00,0x20,0xf8,0xbd,0x73,0xb5,0x4d,0x78,0x01,0x2d,0x3e,0xd1, +0x83,0x69,0x4a,0x69,0x1e,0x68,0x1c,0x69,0x00,0x94,0xe4,0xb2,0x42,0xb9,0x62,0xf3, +0x06,0x04,0x8d,0xf8,0x00,0x40,0x9d,0xf8,0x02,0x40,0x65,0xf3,0xc4,0x04,0x0e,0xe0, +0x8d,0x68,0xaa,0x42,0x86,0xbf,0x4d,0x61,0x65,0xf3,0x06,0x04,0x62,0xf3,0x06,0x04, +0x8d,0xf8,0x00,0x40,0x9d,0xf8,0x02,0x40,0x01,0x22,0x62,0xf3,0xc4,0x04,0x8d,0xf8, +0x02,0x40,0x00,0x9a,0x1a,0x61,0xc2,0x78,0x01,0x2a,0x01,0xbf,0x0a,0x78,0x0c,0x69, +0x00,0xeb,0x82,0x02,0x92,0x69,0x08,0xbf,0x54,0x61,0x46,0xf0,0x04,0x42,0x1a,0x60, +0xc3,0x78,0x00,0x2b,0x35,0xd1,0x4b,0x69,0x00,0x2b,0x32,0xd0,0x0a,0x78,0x01,0x21, +0x11,0xfa,0x02,0xf2,0x03,0x69,0x58,0x6b,0x02,0x43,0x5a,0x63,0x29,0xe0,0x0b,0x78, +0x4e,0x69,0x00,0xeb,0x83,0x03,0x5b,0x6d,0x8c,0x68,0x1a,0x68,0x1d,0x69,0x00,0x95, +0xed,0xb2,0x06,0xb1,0x4c,0x61,0x64,0xf3,0x06,0x05,0x9d,0xf8,0x02,0x40,0x8d,0xf8, +0x00,0x50,0x01,0x25,0x65,0xf3,0xc4,0x04,0x8d,0xf8,0x02,0x40,0x00,0x9c,0x42,0xf0, +0x04,0x42,0x1c,0x61,0xc3,0x78,0x01,0x2b,0x01,0xbf,0x0b,0x78,0x0c,0x69,0x00,0xeb, +0x83,0x03,0x5b,0x6d,0x08,0xbf,0x5c,0x61,0x0b,0x78,0x00,0xeb,0x83,0x00,0x43,0x6d, +0x1a,0x60,0x00,0x20,0x7c,0xbd,0x4b,0x78,0x01,0x2b,0x0b,0x78,0x00,0xeb,0x83,0x00, +0x1c,0xbf,0x42,0x6d,0x13,0x68,0x09,0xd1,0x82,0x69,0x13,0x68,0xc3,0xf3,0x07,0x61, +0x01,0xf0,0x80,0x01,0xc9,0xb2,0x09,0xb1,0x43,0xf0,0x80,0x43,0x43,0xf4,0x00,0x13, +0x13,0x60,0x00,0x20,0x70,0x47,0x4b,0x78,0x01,0x2b,0x0b,0x78,0xc9,0x78,0x00,0xeb, +0x83,0x00,0x0c,0xbf,0x82,0x69,0x42,0x6d,0x02,0x39,0x13,0x68,0xc9,0xb2,0x6f,0xf3, +0x55,0x53,0x01,0x29,0x98,0xbf,0x43,0xf0,0x80,0x53,0x13,0x60,0x00,0x20,0x70,0x47, +0x03,0x69,0x9a,0x69,0xd8,0x69,0x10,0x40,0x00,0x0c,0x70,0x47,0x00,0xeb,0x81,0x01, +0x4b,0x6d,0x02,0x69,0x9b,0x68,0x50,0x69,0x18,0x40,0x70,0x47,0x03,0x69,0x98,0x69, +0xdb,0x69,0x18,0x40,0x80,0xb2,0x70,0x47,0x82,0xb0,0x00,0x23,0x00,0x93,0xc0,0x23, +0x8d,0xf8,0x03,0x30,0x01,0x22,0x00,0x23,0x62,0xf3,0xc4,0x03,0x8d,0xf8,0x02,0x30, +0x18,0x23,0x8d,0xf8,0x00,0x30,0x00,0x9a,0x43,0x6d,0x1a,0x61,0xc2,0x78,0x01,0x2a, +0x07,0xd1,0x00,0xf5,0xb8,0x60,0x0c,0x30,0x58,0x61,0x1a,0x68,0x4f,0xf0,0x80,0x22, +0x1a,0x60,0x02,0xb0,0x70,0x47,0xd0,0xf8,0x18,0x31,0x10,0xb5,0x04,0x46,0xd3,0xb1, +0x03,0x69,0x9a,0x68,0xd2,0x07,0x16,0xd5,0x82,0x7a,0x42,0xb1,0xd0,0xf8,0x0c,0x21, +0xd0,0xf8,0x0c,0x11,0x6f,0xf3,0x41,0x02,0x6f,0xf3,0x00,0x02,0x0a,0x60,0x5a,0x68, +0x05,0x20,0x42,0xf0,0x01,0x02,0x5a,0x60,0x01,0xf0,0xe2,0xfc,0x23,0x69,0x5a,0x68, +0x22,0xf0,0x01,0x02,0x5a,0x60,0x10,0xbd,0x83,0x7a,0x6b,0xb1,0x03,0x69,0x9b,0x68, +0xd9,0x07,0x41,0xbf,0xd0,0xf8,0x0c,0x31,0xd0,0xf8,0x0c,0x21,0x6f,0xf3,0x41,0x03, +0x6f,0xf3,0x00,0x03,0x48,0xbf,0x13,0x60,0x70,0x47,0x01,0x23,0x10,0xb5,0x00,0x22, +0x80,0xf8,0x12,0x31,0x04,0x46,0x03,0x46,0xff,0x21,0x04,0xe0,0x58,0x69,0x01,0x32, +0x81,0x60,0x18,0x6d,0x81,0x60,0x60,0x78,0x04,0x33,0x82,0x42,0xf6,0xd3,0x23,0x69, +0x00,0x22,0x1a,0x61,0x5a,0x61,0xda,0x61,0x4f,0xf0,0xff,0x32,0x9a,0x61,0x20,0x46, +0xff,0xf7,0xf4,0xfc,0x20,0x46,0x10,0x21,0xbd,0xe8,0x10,0x40,0xd1,0xe4,0x4b,0x78, +0x01,0x2b,0x0b,0x78,0x00,0xeb,0x83,0x00,0x0f,0xd1,0x83,0x69,0x18,0x68,0xc0,0xf3, +0x07,0x40,0x00,0xf0,0x20,0x03,0xdb,0xb2,0xcb,0xb9,0x00,0xf0,0x02,0x00,0xc0,0xb2, +0x00,0x28,0x0c,0xbf,0x30,0x20,0x20,0x20,0x70,0x47,0x43,0x6d,0x18,0x68,0xc0,0xf3, +0x07,0x40,0x00,0xf0,0x20,0x03,0xdb,0xb2,0x5b,0xb9,0x00,0xf0,0x02,0x00,0xc0,0xb2, +0x00,0x28,0x0c,0xbf,0x4f,0xf4,0x40,0x50,0x4f,0xf4,0x00,0x50,0x70,0x47,0x10,0x20, +0x70,0x47,0x4f,0xf4,0x80,0x50,0x70,0x47,0x4b,0x78,0x10,0xb5,0x01,0x2b,0x0b,0x78, +0x00,0xeb,0x83,0x03,0x0a,0xd1,0x9c,0x69,0x10,0x2a,0x23,0x68,0x02,0xd1,0xbd,0xe8, +0x10,0x40,0x10,0xe7,0x20,0x2a,0x0c,0xd0,0x30,0x2a,0x0f,0xe0,0x5c,0x6d,0xb2,0xf5, +0x80,0x5f,0x23,0x68,0x08,0xbf,0x43,0xf4,0x00,0x13,0x1a,0xd0,0xb2,0xf5,0x00,0x5f, +0x02,0xd1,0x43,0xf0,0x00,0x63,0x14,0xe0,0xb2,0xf5,0x40,0x5f,0x0e,0xd1,0xc3,0xf3, +0x07,0x42,0x02,0xf0,0x20,0x02,0x43,0xf0,0x80,0x63,0xd2,0xb2,0x43,0xf0,0x80,0x23, +0x3a,0xb1,0x00,0x23,0x4b,0x71,0xbd,0xe8,0x10,0x40,0x04,0xe7,0x0a,0xb9,0x62,0xf3, +0xcf,0x33,0x23,0x60,0x10,0xbd,0x00,0xbf,0xf8,0xb5,0x04,0x46,0xff,0xf7,0xb2,0xfb, +0x01,0x22,0x00,0x23,0x84,0xf8,0x12,0x21,0x84,0xf8,0x14,0x31,0x28,0x27,0x16,0x46, +0x19,0x46,0x40,0x25,0x10,0xe0,0x07,0xfb,0x03,0x40,0x80,0xf8,0x1c,0x31,0xa0,0xf8, +0x22,0x31,0x80,0xf8,0x1d,0x61,0x80,0xf8,0x1f,0x11,0xc0,0xf8,0x24,0x51,0xc0,0xf8, +0x28,0x11,0xc0,0xf8,0x30,0x11,0x01,0x33,0x62,0x78,0x93,0x42,0xeb,0xd3,0x00,0x23, +0x28,0x26,0x19,0x46,0x40,0x25,0x10,0xe0,0x06,0xfb,0x03,0x40,0x80,0xf8,0x74,0x33, +0xa0,0xf8,0x7a,0x33,0x80,0xf8,0x75,0x13,0x80,0xf8,0x77,0x13,0xc0,0xf8,0x7c,0x53, +0xc0,0xf8,0x80,0x13,0xc0,0xf8,0x88,0x13,0x01,0x33,0x62,0x78,0x93,0x42,0xeb,0xd3, +0x20,0x46,0xff,0xf7,0x27,0xfc,0x20,0x46,0xff,0xf7,0xd4,0xfb,0x00,0x21,0x20,0x46, +0xff,0xf7,0x5e,0xfc,0x20,0x46,0xff,0xf7,0xb5,0xfc,0x20,0x46,0xbd,0xe8,0xf8,0x40, +0xff,0xf7,0x11,0xbc,0x70,0xb5,0xcd,0xb2,0x0c,0x46,0x4f,0xf0,0x28,0x06,0x01,0xf0, +0x7f,0x01,0x06,0xfb,0x01,0x01,0x15,0xf0,0x80,0x0f,0x14,0xbf,0x01,0xf5,0x8e,0x71, +0x01,0xf5,0x5d,0x71,0x04,0xf0,0x7f,0x04,0xed,0x09,0x0c,0x70,0x4d,0x70,0x8a,0x60, +0xcb,0x70,0x05,0xb1,0xcc,0x80,0x02,0x2b,0x01,0xd1,0x00,0x23,0x0b,0x71,0xff,0xf7, +0x37,0xfd,0x00,0x20,0x70,0xbd,0x10,0xb5,0x01,0xf0,0x7f,0x03,0x4f,0xf0,0x28,0x04, +0x04,0xfb,0x03,0x03,0xca,0xb2,0x12,0xf0,0x80,0x0f,0x14,0xbf,0x03,0xf5,0x8e,0x73, +0x03,0xf5,0x5d,0x73,0x01,0xf0,0x7f,0x01,0xd2,0x09,0x19,0x70,0x5a,0x70,0x19,0x46, +0xff,0xf7,0x4d,0xfd,0x00,0x20,0x10,0xbd,0x38,0xb5,0x01,0xf0,0x7f,0x05,0x28,0x24, +0x04,0xfb,0x05,0x04,0x04,0xf5,0x5d,0x71,0x4b,0x61,0x00,0x23,0x8b,0x61,0x4b,0x70, +0xeb,0xb2,0xca,0x60,0x84,0xf8,0x74,0x33,0xc4,0x78,0x01,0x2c,0x08,0xbf,0x0a,0x61, +0x13,0xb9,0xff,0xf7,0xd9,0xfd,0x01,0xe0,0xff,0xf7,0x50,0xfd,0x00,0x20,0x38,0xbd, +0x70,0xb5,0x01,0xf0,0x7f,0x04,0x28,0x25,0x05,0xfb,0x04,0x05,0x05,0xf5,0x8e,0x71, +0x01,0x26,0xe4,0xb2,0xca,0x60,0x0a,0x61,0x00,0x22,0x85,0xf8,0x1c,0x41,0x4e,0x70, +0x05,0xf5,0x8c,0x75,0x8a,0x61,0x4b,0x61,0x14,0xb9,0xff,0xf7,0xbd,0xfd,0x01,0xe0, +0xff,0xf7,0x34,0xfd,0x00,0x20,0x70,0xbd,0xca,0xb2,0x12,0xf0,0x80,0x0f,0x4f,0xf0, +0x28,0x03,0x10,0xb5,0x15,0xbf,0x01,0xf0,0x7f,0x04,0x03,0xfb,0x01,0x03,0x03,0xfb, +0x04,0x03,0x03,0xf5,0x5d,0x73,0x18,0xbf,0x03,0xf5,0x8e,0x73,0x01,0xf0,0x7f,0x01, +0xd2,0x09,0x01,0x24,0x19,0x70,0x9c,0x70,0x5a,0x70,0x19,0x46,0xff,0xf7,0x0b,0xfe, +0x00,0x20,0x10,0xbd,0xca,0xb2,0x12,0xf0,0x80,0x0f,0x4f,0xf0,0x28,0x03,0x10,0xb5, +0x15,0xbf,0x01,0xf0,0x7f,0x04,0x03,0xfb,0x01,0x03,0x03,0xfb,0x04,0x03,0x03,0xf5, +0x5d,0x73,0x18,0xbf,0x03,0xf5,0x8e,0x73,0x01,0xf0,0x7f,0x01,0x00,0x24,0xd2,0x09, +0x19,0x70,0x9c,0x70,0x5a,0x70,0x19,0x46,0xff,0xf7,0x05,0xfe,0x20,0x46,0x10,0xbd, +0x08,0xb5,0x0b,0x06,0x04,0xd5,0x01,0xf0,0x7f,0x01,0xff,0xf7,0x6a,0xfb,0x01,0xe0, +0xff,0xf7,0x84,0xfb,0x00,0x20,0x08,0xbd,0x03,0x69,0x00,0x22,0x61,0xf3,0x0a,0x12, +0x19,0x68,0x0a,0x43,0x1a,0x60,0x70,0x47,0x03,0x69,0x03,0x20,0x5a,0x68,0x6f,0xf3, +0x41,0x02,0x5a,0x60,0x01,0xf0,0x2c,0xbb,0x03,0x69,0x03,0x20,0x5a,0x68,0x42,0xf0, +0x02,0x02,0x5a,0x60,0x01,0xf0,0x24,0xbb,0x11,0xf0,0x80,0x0f,0x4f,0xf0,0x28,0x03, +0x1b,0xbf,0x01,0xf0,0x7f,0x01,0x03,0xfb,0x01,0x01,0x03,0xfb,0x01,0x01,0x01,0xf5, +0x8e,0x71,0x08,0xbf,0x01,0xf5,0x5d,0x71,0xff,0xf7,0x69,0xbe,0x11,0xf0,0x80,0x0f, +0x4f,0xf0,0x28,0x03,0x1b,0xbf,0x01,0xf0,0x7f,0x01,0x03,0xfb,0x01,0x01,0x03,0xfb, +0x01,0x01,0x01,0xf5,0x8e,0x71,0x08,0xbf,0x01,0xf5,0x5d,0x71,0xff,0xf7,0x84,0xbe, +0x2d,0xe9,0xf0,0x4f,0x85,0xb0,0x04,0x46,0xff,0xf7,0x74,0xfb,0x00,0x28,0x00,0xf0, +0x5e,0x82,0x20,0x46,0xff,0xf7,0x7b,0xfb,0x05,0x46,0x00,0x2d,0x00,0xf0,0x57,0x82, +0xc5,0xf3,0x07,0x40,0x00,0xf0,0x08,0x00,0xc0,0xb2,0x00,0x28,0x5c,0xd0,0x20,0x46, +0xff,0xf7,0xb6,0xfd,0x27,0x46,0x82,0x46,0xa1,0x46,0x4f,0xf0,0x00,0x08,0xdf,0xf8, +0x6c,0xb3,0x2e,0x46,0x4b,0xe0,0x1a,0xf0,0x01,0x0f,0x41,0xd0,0x5f,0xfa,0x88,0xf2, +0x11,0x46,0x20,0x46,0x00,0x92,0xff,0xf7,0xa9,0xfd,0x10,0xf0,0x01,0x0f,0x05,0x46, +0x00,0x9a,0x22,0xd0,0x7b,0x6d,0x01,0x25,0x9d,0x60,0xe1,0x78,0x20,0x46,0xa9,0x42, +0x01,0xbf,0x1b,0x69,0xd9,0xf8,0x7c,0x13,0xc3,0xf3,0x12,0x03,0xc3,0xeb,0x01,0x03, +0x08,0xbf,0xc9,0xf8,0x8c,0x33,0xdb,0xf8,0x00,0x30,0x11,0x46,0x1b,0x68,0x98,0x47, +0xe3,0x78,0x01,0x2b,0x09,0xd1,0xb8,0xf1,0x00,0x0f,0x06,0xd1,0x94,0xf8,0x11,0x31, +0x05,0x2b,0x02,0xd1,0x20,0x46,0xff,0xf7,0x8f,0xfd,0x05,0xf0,0x02,0x03,0xdb,0xb2, +0x13,0xb1,0x7b,0x6d,0x02,0x25,0x9d,0x60,0x05,0xf0,0x08,0x05,0xed,0xb2,0x3d,0xb1, +0xdb,0xf8,0x00,0x30,0x20,0x46,0x9b,0x68,0x98,0x47,0x7b,0x6d,0x08,0x20,0x98,0x60, +0x08,0xf1,0x01,0x08,0x4f,0xea,0x5a,0x0a,0x04,0x37,0x09,0xf1,0x28,0x09,0xba,0xf1, +0x00,0x0f,0xb0,0xd1,0x35,0x46,0x01,0x20,0xc5,0xf3,0x07,0x43,0x03,0xf0,0x04,0x03, +0xdb,0xb2,0x00,0x2b,0x00,0xf0,0xa1,0x80,0x20,0x46,0xff,0xf7,0x5f,0xfd,0x27,0x46, +0x83,0x46,0x4f,0xf0,0x00,0x08,0x01,0x95,0x91,0xe0,0x1b,0xf0,0x01,0x0f,0x00,0xf0, +0x89,0x80,0x23,0x69,0x5f,0xfa,0x88,0xf9,0x19,0x69,0x5d,0x6b,0x04,0xeb,0x89,0x02, +0x25,0xfa,0x09,0xf5,0x92,0x69,0xed,0x01,0x92,0x68,0xed,0xb2,0x0d,0x43,0x15,0x40, +0xea,0x07,0x1c,0xd5,0x01,0x20,0x00,0xfa,0x08,0xf1,0x5a,0x6b,0x05,0x46,0x22,0xea, +0x01,0x02,0x5a,0x63,0xbb,0x69,0x99,0x4a,0x98,0x60,0x13,0x68,0x20,0x46,0x5b,0x68, +0x49,0x46,0x98,0x47,0xe3,0x78,0xab,0x42,0x09,0xd1,0xb8,0xf1,0x00,0x0f,0x06,0xd1, +0x94,0xf8,0x11,0x31,0x04,0x2b,0x02,0xd1,0x20,0x46,0xff,0xf7,0x2d,0xfd,0x05,0xf0, +0x08,0x03,0xdb,0xb2,0x13,0xb1,0xbb,0x69,0x08,0x25,0x9d,0x60,0x05,0xf0,0x10,0x03, +0xdb,0xb2,0x13,0xb1,0xbb,0x69,0x10,0x25,0x9d,0x60,0x05,0xf0,0x40,0x03,0xdb,0xb2, +0x13,0xb1,0xbb,0x69,0x40,0x25,0x9d,0x60,0x05,0xf0,0x02,0x03,0xdb,0xb2,0x13,0xb1, +0xbb,0x69,0x02,0x25,0x9d,0x60,0x25,0xf0,0x7f,0x05,0x15,0xf0,0xff,0x0f,0x39,0xd0, +0x28,0x25,0x05,0xfb,0x08,0x45,0x05,0xf5,0x8e,0x75,0xab,0x69,0x6a,0x69,0xc2,0x46, +0xc3,0xeb,0x02,0x0c,0xab,0x68,0xa0,0x46,0x9c,0x45,0x28,0xbf,0x9c,0x46,0x0c,0xf1, +0x03,0x0c,0xbb,0x69,0x4f,0xea,0x9c,0x0c,0x9b,0x69,0x66,0x46,0x14,0xe0,0xaa,0x68, +0x1c,0x1b,0x94,0x42,0x28,0xbf,0x14,0x46,0xa3,0xb2,0x40,0x46,0xe9,0x68,0x4a,0x46, +0xff,0xf7,0x52,0xf9,0xeb,0x68,0xe6,0x1c,0x1b,0x19,0xeb,0x60,0xab,0x69,0xb6,0x08, +0x1c,0x19,0xac,0x61,0xbb,0x69,0x9b,0x69,0x9b,0xb2,0xb3,0x42,0x05,0xd9,0xac,0x69, +0x6b,0x69,0x9c,0x42,0x01,0xd2,0x00,0x2b,0xe1,0xd1,0xbb,0x69,0x80,0x25,0x44,0x46, +0x9d,0x60,0xd0,0x46,0x08,0xf1,0x01,0x08,0x4f,0xea,0x5b,0x0b,0x04,0x37,0xbb,0xf1, +0x00,0x0f,0x7f,0xf4,0x6a,0xaf,0x01,0x9d,0x01,0x20,0x05,0xf0,0x02,0x03,0xdb,0xb2, +0x13,0xb1,0xe3,0x68,0x02,0x22,0x5a,0x61,0xc5,0xf3,0x07,0x63,0x03,0xf0,0x80,0x03, +0xdb,0xb2,0xcb,0xb1,0xa3,0x7a,0x43,0xb1,0xd4,0xf8,0x0c,0x31,0xd4,0xf8,0x0c,0x21, +0x6f,0xf3,0x41,0x03,0x6f,0xf3,0x00,0x03,0x13,0x60,0x23,0x69,0x20,0x46,0x5a,0x68, +0x22,0xf0,0x01,0x02,0x5a,0x60,0x4d,0x4b,0x1b,0x68,0x9b,0x69,0x98,0x47,0xe3,0x68, +0x4f,0xf0,0x00,0x42,0x5a,0x61,0x01,0x20,0xc5,0xf3,0x07,0x23,0x03,0xf0,0x08,0x03, +0xdb,0xb2,0x00,0x2b,0x2e,0xd0,0x00,0x23,0x8d,0xf8,0x0f,0x30,0x94,0xf8,0x12,0x31, +0x20,0x46,0x8d,0xf8,0x0f,0x30,0x41,0x4b,0x1b,0x68,0x5b,0x69,0x98,0x47,0x23,0x69, +0xe2,0x68,0x4f,0xf4,0x00,0x61,0x9b,0x68,0x51,0x61,0xa2,0x7a,0xca,0xb1,0xdb,0x07, +0x17,0xd5,0x94,0xf8,0x15,0x01,0x01,0x28,0x13,0xd1,0x9d,0xf8,0x0f,0x30,0x03,0x2b, +0x10,0xd1,0xd4,0xf8,0x0c,0x31,0x1a,0x68,0x42,0xf0,0x01,0x02,0x1a,0x60,0x1a,0x68, +0x42,0xf0,0x03,0x02,0x1a,0x60,0x32,0x4b,0x1a,0x69,0x42,0xf0,0x06,0x02,0x1a,0x61, +0x00,0xe0,0x01,0x20,0x05,0xf0,0x08,0x03,0xdb,0xb2,0x43,0xb1,0x2b,0x4b,0x20,0x46, +0x1b,0x68,0xdb,0x68,0x98,0x47,0xe3,0x68,0x08,0x22,0x5a,0x61,0x01,0x20,0x05,0xf0, +0x10,0x03,0xdb,0xb2,0x00,0x2b,0x34,0xd0,0xe3,0x68,0x28,0x26,0x9a,0x69,0x22,0xf0, +0x10,0x02,0x9a,0x61,0x1f,0x6a,0x07,0xf0,0x0f,0x03,0x06,0xfb,0x03,0x46,0xc7,0xf3, +0x43,0x43,0x02,0x2b,0x06,0xf5,0x5d,0x76,0x02,0xd0,0x06,0x2b,0x1b,0xd1,0x0e,0xe0, +0x47,0xf6,0xf0,0x73,0x3b,0x40,0xb3,0xb1,0xc7,0xf3,0x0a,0x17,0x20,0x46,0xf1,0x68, +0x3a,0x46,0xff,0xf7,0xb5,0xf8,0xf3,0x68,0xdb,0x19,0xf3,0x60,0x08,0xe0,0x04,0xf5, +0xb8,0x61,0x0c,0x31,0x20,0x46,0x08,0x22,0xff,0xf7,0xaa,0xf8,0xc7,0xf3,0x0a,0x17, +0xb3,0x69,0xdf,0x19,0xb7,0x61,0xe3,0x68,0x01,0x20,0x9a,0x69,0x42,0xf0,0x10,0x02, +0x9a,0x61,0xc5,0xf3,0x07,0x23,0x03,0xf0,0x10,0x03,0xdb,0xb2,0x00,0x2b,0x38,0xd0, +0x23,0x69,0x00,0x26,0x5a,0x68,0x31,0x46,0x22,0xf0,0x01,0x02,0x5a,0x60,0x20,0x46, +0xff,0xf7,0x57,0xf9,0x23,0x46,0x32,0x46,0xff,0x21,0x08,0xe0,0x6c,0x77,0x00,0x20, +0x00,0xed,0x00,0xe0,0x58,0x69,0x01,0x32,0x81,0x60,0x18,0x6d,0x81,0x60,0x60,0x78, +0x04,0x33,0x82,0x42,0xf6,0xd3,0x23,0x69,0x01,0x27,0x4f,0xf0,0xff,0x32,0x67,0xf3, +0x0f,0x06,0x9a,0x61,0x67,0xf3,0x1f,0x46,0x0b,0x22,0xde,0x61,0x5a,0x61,0x1a,0x61, +0x1a,0x68,0x20,0x46,0x6f,0xf3,0x0a,0x12,0x1a,0x60,0xff,0xf7,0xed,0xfb,0xe3,0x68, +0x4f,0xf4,0x80,0x52,0x5a,0x61,0x37,0x4b,0x20,0x46,0x1b,0x68,0x1b,0x69,0x98,0x47, +0x38,0x46,0xc5,0xf3,0x07,0x23,0x03,0xf0,0x20,0x03,0xdb,0xb2,0xeb,0xb1,0x20,0x46, +0xff,0xf7,0x40,0xfa,0xe3,0x68,0x20,0x46,0xde,0x68,0xff,0xf7,0x2b,0xfa,0x03,0x28, +0x06,0xd1,0x00,0x23,0xa3,0x70,0x4f,0xf4,0x00,0x73,0xa3,0x80,0x09,0x23,0x04,0xe0, +0x01,0x23,0x40,0x20,0xa3,0x70,0xa0,0x80,0x05,0x23,0x63,0xf3,0x8d,0x26,0xe3,0x68, +0x4f,0xf4,0x00,0x52,0xde,0x60,0x01,0x20,0x5a,0x61,0xc5,0xf3,0x07,0x43,0x03,0xf0, +0x10,0x03,0xdb,0xb2,0x4b,0xb1,0x1f,0x4b,0x20,0x46,0x1b,0x68,0xdb,0x69,0x98,0x47, +0xe3,0x68,0x4f,0xf4,0x80,0x12,0x5a,0x61,0x01,0x20,0xc5,0xf3,0x07,0x43,0x03,0xf0, +0x20,0x03,0xdb,0xb2,0x4b,0xb1,0x17,0x4b,0x20,0x46,0x1b,0x68,0x1b,0x6a,0x98,0x47, +0xe3,0x68,0x4f,0xf4,0x00,0x12,0x5a,0x61,0x01,0x20,0xc5,0xf3,0x07,0x63,0x03,0xf0, +0x40,0x03,0xdb,0xb2,0x4b,0xb1,0x0f,0x4b,0x20,0x46,0x1b,0x68,0x5b,0x6a,0x98,0x47, +0xe3,0x68,0x4f,0xf0,0x80,0x42,0x5a,0x61,0x01,0x20,0x05,0xf0,0x04,0x05,0xed,0xb2, +0x6d,0xb1,0xe3,0x68,0x5d,0x68,0x05,0xf0,0x04,0x03,0xdb,0xb2,0x23,0xb1,0x05,0x4b, +0x20,0x46,0x1b,0x68,0x9b,0x6a,0x98,0x47,0xe3,0x68,0x01,0x20,0x5d,0x60,0x05,0xb0, +0xbd,0xe8,0xf0,0x8f,0x6c,0x77,0x00,0x20,0xd0,0xf8,0xe8,0x35,0x10,0xb5,0x1b,0x69, +0x04,0x46,0x98,0x47,0x03,0x23,0x84,0xf8,0x12,0x31,0x00,0x20,0x10,0xbd,0x08,0xb5, +0x90,0xf8,0x12,0x31,0x80,0xf8,0x13,0x31,0x04,0x23,0x80,0xf8,0x12,0x31,0xd0,0xf8, +0xe8,0x35,0xdb,0x68,0x98,0x47,0x00,0x20,0x08,0xbd,0x08,0xb5,0xd0,0xf8,0xe4,0x35, +0xdb,0x69,0x03,0xb1,0x98,0x47,0x00,0x20,0x08,0xbd,0x08,0xb5,0xd0,0xf8,0xe4,0x35, +0x1b,0x6a,0x98,0x47,0x00,0x20,0x08,0xbd,0x08,0xb5,0xd0,0xf8,0xe4,0x35,0x5b,0x6a, +0x98,0x47,0x00,0x20,0x08,0xbd,0xd0,0xf8,0xe8,0x35,0x10,0xb5,0x5b,0x69,0x04,0x46, +0x98,0x47,0x01,0x23,0x84,0xf8,0x15,0x31,0x00,0x20,0x10,0xbd,0xd0,0xf8,0xe8,0x35, +0x10,0xb5,0x9b,0x69,0x04,0x46,0x98,0x47,0xd4,0xf8,0xe4,0x35,0x20,0x46,0x5b,0x68, +0x00,0x21,0x98,0x47,0x00,0x20,0x84,0xf8,0x15,0x01,0x10,0xbd,0x00,0x21,0x10,0xb5, +0x40,0x22,0x04,0x46,0x0b,0x46,0xff,0xf7,0x4d,0xfc,0x80,0x21,0x40,0x22,0x00,0x23, +0x20,0x46,0xff,0xf7,0x47,0xfc,0x01,0x23,0x84,0xf8,0x12,0x31,0xd4,0xf8,0xe8,0x35, +0xa0,0x78,0x5b,0x68,0x98,0x47,0x00,0x20,0x10,0xbd,0x13,0xb5,0x69,0x46,0x04,0x46, +0x00,0xf0,0x3c,0xf9,0x9d,0xf8,0x00,0x10,0x01,0xf0,0x1f,0x03,0x01,0x2b,0x07,0xd0, +0x02,0x2b,0x0a,0xd0,0x73,0xb9,0x20,0x46,0x69,0x46,0x00,0xf0,0xeb,0xf9,0x0f,0xe0, +0x20,0x46,0x69,0x46,0x00,0xf0,0xcc,0xf9,0x0a,0xe0,0x20,0x46,0x69,0x46,0x00,0xf0, +0x55,0xf9,0x05,0xe0,0x21,0xf0,0x7f,0x01,0xc9,0xb2,0x20,0x46,0xff,0xf7,0x8c,0xfc, +0x00,0x20,0x1c,0xbd,0x38,0xb5,0x04,0x46,0x00,0x29,0x48,0xd1,0x90,0xf8,0x11,0x31, +0x02,0x2b,0x38,0xd1,0xd0,0xf8,0x38,0x21,0xd0,0xf8,0x24,0x31,0x9a,0x42,0x11,0xd9, +0xc1,0x78,0xd2,0x1a,0x01,0x29,0x08,0xbf,0xd0,0xf8,0x28,0x11,0xc0,0xf8,0x38,0x21, +0x04,0xbf,0xcb,0x18,0xc0,0xf8,0x28,0x31,0x92,0xb2,0xd4,0xf8,0x28,0x11,0x00,0xf0, +0xb7,0xf8,0x20,0xe0,0xd0,0xf8,0x3c,0x21,0xb2,0xfb,0xf3,0xf5,0x03,0xfb,0x15,0x25, +0x65,0xb9,0x9a,0x42,0x0a,0xd3,0xd0,0xf8,0x40,0x31,0x9a,0x42,0x06,0xd2,0x29,0x46, +0x2a,0x46,0x00,0xf0,0xa5,0xf8,0xc4,0xf8,0x40,0x51,0x0c,0xe0,0xd4,0xf8,0xe4,0x35, +0xdb,0x68,0x2b,0xb1,0x94,0xf8,0x12,0x21,0x03,0x2a,0x01,0xd1,0x20,0x46,0x98,0x47, +0x20,0x46,0x00,0xf0,0xc6,0xf8,0x94,0xf8,0x16,0x31,0x01,0x2b,0x10,0xd1,0x09,0x4a, +0x23,0x69,0x12,0x68,0x5a,0x60,0x00,0x23,0x84,0xf8,0x16,0x31,0x08,0xe0,0xd0,0xf8, +0xe4,0x35,0x5b,0x69,0x23,0xb1,0x90,0xf8,0x12,0x21,0x03,0x2a,0x00,0xd1,0x98,0x47, +0x00,0x20,0x38,0xbd,0x80,0x9f,0x00,0x20,0x10,0xb5,0x04,0x46,0x59,0xbb,0x90,0xf8, +0x11,0x31,0x03,0x2b,0x30,0xd1,0xd0,0xf8,0x90,0x23,0xd0,0xf8,0x7c,0x33,0x9a,0x42, +0x14,0xd9,0xc1,0x78,0xd2,0x1a,0x01,0x29,0x08,0xbf,0xd0,0xf8,0x80,0x13,0xc0,0xf8, +0x90,0x23,0x04,0xbf,0xc9,0x18,0xc0,0xf8,0x80,0x13,0x9a,0x42,0x28,0xbf,0x1a,0x46, +0x92,0xb2,0xd0,0xf8,0x80,0x13,0x00,0xf0,0x74,0xf8,0x15,0xe0,0xd0,0xf8,0xe4,0x35, +0x1b,0x69,0x23,0xb1,0x90,0xf8,0x12,0x21,0x03,0x2a,0x00,0xd1,0x98,0x47,0x20,0x46, +0x00,0xf0,0x70,0xf8,0x08,0xe0,0xd0,0xf8,0xe4,0x35,0x9b,0x69,0x23,0xb1,0x90,0xf8, +0x12,0x21,0x03,0x2a,0x00,0xd1,0x98,0x47,0x00,0x20,0x10,0xbd,0x2d,0xe9,0xf0,0x41, +0x06,0x9f,0x04,0x46,0x16,0x46,0x98,0x46,0x0d,0x46,0x00,0xf0,0x0f,0xff,0x20,0x46, +0x29,0x46,0xc4,0xf8,0xe4,0x85,0xc4,0xf8,0xe8,0x75,0xc4,0xf8,0xec,0x65,0xff,0xf7, +0x23,0xfb,0xd4,0xf8,0xe8,0x35,0x1b,0x68,0x98,0x47,0x20,0x46,0xbd,0xe8,0xf0,0x41, +0x00,0xf0,0x3a,0xbf,0x00,0x20,0x70,0x47,0xd0,0xf8,0xe4,0x35,0x10,0xb5,0x1b,0x68, +0x04,0x46,0x98,0x47,0xd4,0xf8,0xe8,0x35,0x9b,0x68,0x98,0x47,0x00,0x20,0x10,0xbd, +0x08,0xb5,0xd0,0xf8,0xe4,0x35,0x5b,0x68,0x98,0x47,0x00,0x20,0x08,0xbd,0x00,0xbf, +0x10,0xb5,0x13,0x46,0x0c,0x46,0xc0,0xf8,0x3c,0x21,0xc0,0xf8,0x38,0x21,0x02,0x22, +0x80,0xf8,0x11,0x21,0x00,0x21,0x22,0x46,0xff,0xf7,0x9a,0xfb,0x00,0x20,0x10,0xbd, +0x10,0xb5,0x0c,0x46,0x13,0x46,0x00,0x21,0x22,0x46,0xff,0xf7,0x91,0xfb,0x00,0x20, +0x10,0xbd,0x10,0xb5,0x13,0x46,0x0c,0x46,0xc0,0xf8,0x94,0x23,0xc0,0xf8,0x90,0x23, +0x03,0x22,0x80,0xf8,0x11,0x21,0x00,0x21,0x22,0x46,0xff,0xf7,0x65,0xfb,0x00,0x20, +0x10,0xbd,0x10,0xb5,0x0c,0x46,0x13,0x46,0x00,0x21,0x22,0x46,0xff,0xf7,0x5c,0xfb, +0x00,0x20,0x10,0xbd,0x00,0x21,0x04,0x23,0x10,0xb5,0x0a,0x46,0x04,0x46,0x80,0xf8, +0x11,0x31,0x0b,0x46,0xff,0xf7,0x6c,0xfb,0x20,0x46,0xff,0xf7,0xed,0xf9,0x00,0x20, +0x10,0xbd,0x00,0x21,0x05,0x23,0x10,0xb5,0x0a,0x46,0x04,0x46,0x80,0xf8,0x11,0x31, +0x0b,0x46,0xff,0xf7,0x41,0xfb,0x20,0x46,0xff,0xf7,0xde,0xf9,0x00,0x20,0x10,0xbd, +0x28,0x23,0x03,0xfb,0x01,0x00,0xb0,0xf8,0x8c,0x03,0x70,0x47,0x90,0xf8,0xcc,0x35, +0x0b,0x70,0x90,0xf8,0xcd,0x35,0x4b,0x70,0x90,0xf8,0xcf,0x25,0x90,0xf8,0xce,0x35, +0x03,0xeb,0x02,0x23,0x4b,0x80,0x90,0xf8,0xd1,0x25,0x90,0xf8,0xd0,0x35,0x03,0xeb, +0x02,0x23,0x8b,0x80,0x90,0xf8,0xd3,0x25,0x90,0xf8,0xd2,0x35,0x03,0xeb,0x02,0x23, +0x9b,0xb2,0xcb,0x80,0xc0,0xf8,0x40,0x31,0x01,0x23,0x80,0xf8,0x11,0x31,0x70,0x47, +0x10,0xb5,0x80,0x21,0x04,0x46,0xff,0xf7,0x47,0xfb,0x20,0x46,0x00,0x21,0xff,0xf7, +0x43,0xfb,0x20,0x46,0xbd,0xe8,0x10,0x40,0xff,0xf7,0xa6,0xb9,0x38,0xb5,0x0d,0x46, +0x6b,0x78,0x04,0x46,0x01,0x2b,0x09,0x79,0x16,0xd0,0x33,0xd3,0x03,0x2b,0x63,0xd1, +0x90,0xf8,0x12,0x31,0x02,0x2b,0x34,0xd0,0x03,0x2b,0x59,0xd1,0x6b,0x88,0xfb,0xb9, +0x0b,0x1c,0x18,0xbf,0x01,0x23,0x80,0x29,0x0c,0xbf,0x00,0x23,0x03,0xf0,0x01,0x03, +0xb3,0xb1,0xff,0xf7,0x21,0xfb,0x13,0xe0,0x90,0xf8,0x12,0x31,0x02,0x2b,0x20,0xd0, +0x03,0x2b,0x45,0xd1,0x6b,0x88,0x00,0x2b,0x46,0xd1,0x0b,0x1c,0x18,0xbf,0x01,0x23, +0x80,0x29,0x0c,0xbf,0x00,0x23,0x03,0xf0,0x01,0x03,0x3b,0xb1,0xff,0xf7,0x2a,0xfb, +0xd4,0xf8,0xe4,0x35,0x20,0x46,0x9b,0x68,0x29,0x46,0x98,0x47,0x20,0x46,0xff,0xf7, +0x71,0xff,0x31,0xe0,0x90,0xf8,0x12,0x31,0x02,0x2b,0x02,0xd0,0x03,0x2b,0x27,0xd1, +0x0c,0xe0,0x0b,0x1c,0x18,0xbf,0x01,0x23,0x80,0x29,0x0c,0xbf,0x00,0x23,0x03,0xf0, +0x01,0x03,0x0b,0xb3,0x20,0x46,0xff,0xf7,0xef,0xfa,0x1d,0xe0,0x11,0xf0,0x80,0x0f, +0x4f,0xf0,0x28,0x03,0x1b,0xbf,0x01,0xf0,0x7f,0x01,0x03,0xfb,0x01,0x03,0x03,0xfb, +0x01,0x01,0x93,0xf8,0x1e,0x21,0x08,0xbf,0x91,0xf8,0x76,0x23,0x07,0x4b,0x02,0xb1, +0x01,0x22,0x1a,0x60,0x20,0x46,0x05,0x49,0x02,0x22,0xff,0xf7,0x11,0xff,0x03,0xe0, +0x20,0x46,0x29,0x46,0xff,0xf7,0x84,0xff,0x00,0x20,0x38,0xbd,0x14,0x79,0x00,0x20, +0x38,0xb5,0x90,0xf8,0x12,0x31,0x04,0x46,0x03,0x2b,0x0d,0x46,0x0c,0xd1,0x0b,0x79, +0x01,0x2b,0x09,0xd8,0xd0,0xf8,0xe4,0x35,0x9b,0x68,0x98,0x47,0xeb,0x88,0x3b,0xb9, +0x20,0x46,0xff,0xf7,0x27,0xff,0x03,0xe0,0x20,0x46,0x29,0x46,0xff,0xf7,0x68,0xff, +0x00,0x20,0x38,0xbd,0x73,0xb5,0x4b,0x78,0x04,0x46,0x0d,0x46,0x09,0x2b,0x00,0xf2, +0x1b,0x81,0xdf,0xe8,0x13,0xf0,0xcc,0x00,0x07,0x01,0x19,0x01,0xdf,0x00,0x19,0x01, +0x72,0x00,0x0a,0x00,0x19,0x01,0xbc,0x00,0x90,0x00,0x6b,0x88,0x1a,0x0a,0x01,0x3a, +0x06,0x2a,0x00,0xf2,0x09,0x81,0xdf,0xe8,0x12,0xf0,0x07,0x00,0x1a,0x00,0x27,0x00, +0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0xd0,0xf8,0xec,0x35,0x0d,0xf1,0x06,0x01, +0x1b,0x68,0x80,0x78,0x98,0x47,0xeb,0x88,0x01,0x46,0x40,0x2b,0x03,0xd0,0x94,0xf8, +0x12,0x31,0x01,0x2b,0x3a,0xd1,0x08,0x22,0xad,0xf8,0x06,0x20,0x36,0xe0,0xd0,0xf8, +0xe4,0x35,0x0d,0xf1,0x06,0x01,0x9b,0x6a,0x80,0x78,0x98,0x47,0x02,0x23,0x43,0x70, +0x01,0x46,0xc4,0xf8,0xf0,0x05,0x29,0xe0,0xdb,0xb2,0x05,0x2b,0x00,0xf2,0xdc,0x80, +0xdf,0xe8,0x03,0xf0,0x03,0x08,0x0d,0x12,0x17,0x1c,0xd0,0xf8,0xec,0x35,0x80,0x78, +0x5b,0x68,0x17,0xe0,0xd0,0xf8,0xec,0x35,0x80,0x78,0x9b,0x68,0x12,0xe0,0xd0,0xf8, +0xec,0x35,0x80,0x78,0xdb,0x68,0x0d,0xe0,0xd0,0xf8,0xec,0x35,0x80,0x78,0x1b,0x69, +0x08,0xe0,0xd0,0xf8,0xec,0x35,0x80,0x78,0x5b,0x69,0x03,0xe0,0xd0,0xf8,0xec,0x35, +0x80,0x78,0x9b,0x69,0x0d,0xf1,0x06,0x01,0x98,0x47,0x01,0x46,0xbd,0xf8,0x06,0x30, +0x00,0x2b,0x00,0xf0,0xb5,0x80,0xea,0x88,0x00,0x2a,0x00,0xf0,0xb1,0x80,0x9a,0x42, +0x28,0xbf,0x1a,0x46,0xad,0xf8,0x06,0x20,0x57,0xe0,0xab,0x88,0x00,0x2b,0x40,0xf0, +0xa3,0x80,0xeb,0x88,0x00,0x2b,0x40,0xf0,0x9f,0x80,0x90,0xf8,0x12,0x21,0x6b,0x88, +0x03,0x2a,0x00,0xf0,0x99,0x80,0x03,0xf0,0x7f,0x05,0x80,0xf8,0x14,0x51,0x29,0x46, +0xff,0xf7,0x6a,0xfa,0x20,0x46,0xff,0xf7,0x8d,0xfe,0x02,0x23,0x05,0xb9,0x01,0x23, +0x84,0xf8,0x12,0x31,0x8c,0xe0,0xa9,0x78,0x46,0x4e,0x01,0x29,0x31,0x71,0x00,0xf2, +0x83,0x80,0x90,0xf8,0x12,0x31,0x02,0x2b,0x02,0xd0,0x03,0x2b,0x7c,0xd1,0x08,0xe0, +0x00,0x29,0x63,0xd0,0x01,0x21,0x03,0x23,0x80,0xf8,0x10,0x11,0x80,0xf8,0x12,0x31, +0x11,0xe0,0x39,0xb9,0x02,0x23,0x80,0xf8,0x12,0x31,0x80,0xf8,0x10,0x11,0xff,0xf7, +0x2f,0xfe,0x53,0xe0,0x90,0xf8,0x10,0x11,0x01,0x29,0x50,0xd0,0xff,0xf7,0x28,0xfe, +0x31,0x79,0x84,0xf8,0x10,0x11,0x20,0x46,0xff,0xf7,0x16,0xfe,0x46,0xe0,0xea,0x88, +0x01,0x2a,0x59,0xd1,0x90,0xf8,0x12,0x31,0x02,0x2b,0x02,0xd0,0x03,0x2b,0x53,0xd1, +0x01,0xe0,0x2d,0x49,0x13,0xe0,0x00,0xf5,0x88,0x71,0x20,0x46,0x0f,0xe0,0x90,0xf8, +0x12,0x31,0x02,0x3b,0x01,0x2b,0x47,0xd8,0x26,0x4b,0x01,0x22,0xda,0x60,0xd0,0xf8, +0x18,0x21,0x0a,0xb1,0x03,0x22,0xda,0x60,0x24,0x49,0x20,0x46,0x02,0x22,0xff,0xf7, +0x07,0xfe,0x3d,0xe0,0x6b,0x88,0x01,0x2b,0x2d,0xd0,0x02,0x2b,0x38,0xd1,0xab,0x88, +0x13,0xf0,0xff,0x0f,0x34,0xd1,0x02,0x69,0x1b,0x0a,0x01,0x3b,0x52,0x68,0x04,0x2b, +0x0f,0xd8,0xdf,0xe8,0x03,0xf0,0x03,0x05,0x07,0x09,0x0b,0x00,0x01,0x23,0x06,0xe0, +0x02,0x23,0x04,0xe0,0x03,0x23,0x02,0xe0,0x04,0x23,0x00,0xe0,0x05,0x23,0x63,0xf3, +0x06,0x12,0x13,0x4b,0x1a,0x60,0x01,0x23,0x84,0xf8,0x16,0x31,0x20,0x46,0xff,0xf7, +0x11,0xfe,0x15,0xe0,0x90,0xf8,0x12,0x31,0x02,0x3b,0x01,0x2b,0x0c,0xd8,0x6b,0x88, +0x01,0x2b,0x0d,0xd1,0x00,0x23,0xc4,0xf8,0x18,0x31,0xd4,0xf8,0xe4,0x35,0x20,0x46, +0x9b,0x68,0x29,0x46,0x98,0x47,0xe9,0xe7,0x20,0x46,0x29,0x46,0xff,0xf7,0x40,0xfe, +0x00,0x20,0x7c,0xbd,0x14,0x79,0x00,0x20,0x1c,0x79,0x00,0x20,0x20,0x79,0x00,0x20, +0x80,0x9f,0x00,0x20,0x30,0xb5,0xc8,0xb1,0x00,0x23,0xdd,0xb2,0x01,0x33,0xc4,0x18, +0x14,0xf8,0x01,0x4c,0x00,0x2c,0xf8,0xd1,0x6b,0x1c,0x5b,0x00,0x13,0x80,0x0b,0x70, +0x03,0x23,0x4b,0x70,0x02,0x23,0x05,0xe0,0xca,0x54,0x5a,0x1c,0xd2,0xb2,0x02,0x33, +0x8c,0x54,0xdb,0xb2,0x10,0xf8,0x01,0x2b,0x00,0x2a,0xf5,0xd1,0x30,0xbd,0x00,0xbf, +0x10,0xb5,0x08,0x4b,0x08,0x4c,0x18,0x78,0x12,0x02,0x04,0xf8,0x30,0x10,0x04,0xeb, +0xc0,0x04,0x01,0x30,0xc0,0xb2,0x04,0x28,0x62,0x60,0x18,0x70,0x01,0xd1,0x00,0x22, +0x1a,0x70,0x10,0xbd,0xfc,0x9f,0x00,0x20,0xd4,0x9f,0x00,0x20,0xf8,0xb5,0x0d,0x4b, +0x0d,0x4d,0x1b,0x68,0x0e,0x46,0x17,0x46,0x5b,0x68,0x29,0x46,0x0b,0x4a,0x04,0x46, +0x98,0x47,0x18,0xb1,0x20,0x46,0x02,0x21,0x3a,0x22,0x06,0xe0,0x2b,0x68,0xbe,0x19, +0x9e,0x42,0x05,0xd9,0x20,0x46,0x05,0x21,0x21,0x22,0xff,0xf7,0xd1,0xff,0xff,0x20, +0x40,0xb2,0xf8,0xbd,0xec,0x78,0x00,0x20,0xc4,0x9f,0x00,0x20,0xc8,0x9f,0x00,0x20, +0x2d,0xe9,0xf7,0x43,0xdf,0xf8,0xc8,0x92,0x0c,0x46,0xc9,0xf8,0x00,0x00,0x13,0x78, +0x16,0x46,0x1e,0x2b,0x7a,0xd0,0x0d,0xd8,0x12,0x2b,0x5a,0xd0,0x04,0xd8,0xeb,0xb1, +0x03,0x2b,0x40,0xf0,0x1c,0x82,0x29,0xe0,0x1a,0x2b,0x73,0xd0,0x1b,0x2b,0x40,0xf0, +0x16,0x82,0x6b,0xe0,0x28,0x2b,0x00,0xf0,0xd2,0x80,0x06,0xd8,0x23,0x2b,0x00,0xf0, +0x83,0x80,0x25,0x2b,0x40,0xf0,0x0b,0x82,0xa7,0xe0,0x2f,0x2b,0x00,0xf0,0xf2,0x81, +0x5a,0x2b,0x6c,0xd0,0x2a,0x2b,0x40,0xf0,0x02,0x82,0x58,0xe1,0x8e,0x4b,0x9a,0x68, +0x00,0x2a,0x40,0xf0,0x5d,0x81,0x8d,0x4b,0x08,0x46,0x1b,0x68,0x9b,0x68,0x98,0x47, +0x00,0x28,0x40,0xf0,0x5d,0x81,0x8a,0x4b,0x18,0x80,0x8c,0xe0,0x00,0x22,0x89,0x48, +0x11,0x46,0x11,0x54,0x01,0x32,0x12,0x2a,0x86,0x4b,0xfa,0xd1,0x70,0x22,0x86,0x49, +0x86,0x48,0x1a,0x70,0x0c,0x22,0xda,0x71,0x00,0x78,0x0a,0x78,0x90,0x42,0x10,0xd0, +0x83,0x48,0x10,0xf8,0x32,0x40,0x00,0xeb,0xc2,0x00,0x9c,0x70,0x44,0x79,0x01,0x32, +0x1c,0x73,0xd2,0xb2,0x00,0x79,0x04,0x2a,0x58,0x73,0x0a,0x70,0x01,0xd1,0x00,0x23, +0x0b,0x70,0x77,0x4b,0x12,0x22,0x1a,0x80,0x32,0x79,0x12,0x2a,0x00,0xf2,0xcb,0x81, +0x1e,0xe0,0x53,0x78,0xdb,0x07,0x0c,0xd4,0x70,0x4b,0x24,0x22,0x1b,0x68,0xdb,0x69, +0x02,0xfb,0x01,0x34,0x25,0x79,0x33,0x79,0x05,0x35,0x9d,0x42,0x28,0xbf,0x1d,0x46, +0x01,0xe0,0x70,0x4c,0x07,0x25,0x6a,0x4b,0x1d,0x80,0x6a,0x4b,0x03,0xe0,0x01,0x3d, +0xad,0xb2,0x62,0x5d,0x5a,0x55,0x00,0x2d,0xf9,0xd1,0xaf,0xe1,0x64,0x4b,0x00,0x22, +0x1a,0x80,0xa8,0xe1,0x62,0x4b,0x08,0x22,0x1a,0x80,0x62,0x4a,0x66,0x4b,0x08,0x25, +0x01,0x3d,0xad,0xb2,0x59,0x5d,0x51,0x55,0x00,0x2d,0xf9,0xd1,0x9e,0xe1,0x5c,0x4b, +0x08,0x22,0x1a,0x80,0x5b,0x4a,0x61,0x4b,0x08,0x25,0x01,0x3d,0xad,0xb2,0x59,0x5d, +0x51,0x55,0x00,0x2d,0xf9,0xd1,0x91,0xe1,0x00,0x27,0x56,0x4a,0x3b,0x46,0xbb,0x54, +0x01,0x37,0x0c,0x2f,0x53,0x4e,0xfa,0xd1,0x50,0x4b,0x20,0x46,0x1b,0x68,0x01,0xa9, +0x5b,0x68,0x6a,0x46,0x98,0x47,0x00,0x28,0x40,0xf0,0xe2,0x80,0x08,0x23,0xf3,0x70, +0x01,0x9b,0x01,0x3b,0x1a,0x0e,0x32,0x71,0x1a,0x0c,0x72,0x71,0xf3,0x71,0x1a,0x0a, +0x02,0x23,0x33,0x72,0x00,0x9b,0xb2,0x71,0x1a,0x0c,0x72,0x72,0xf3,0x72,0x1a,0x0a, +0x43,0x4b,0xb2,0x72,0x1f,0x80,0x05,0x46,0x68,0xe1,0x40,0x4b,0x48,0x4f,0x1b,0x68, +0x48,0x4e,0x08,0x46,0x5b,0x68,0x39,0x46,0x32,0x46,0x98,0x47,0x00,0x28,0x40,0xf0, +0xbf,0x80,0x3a,0x68,0x3b,0x4b,0x01,0x3a,0x11,0x0e,0x19,0x70,0x11,0x0c,0x59,0x70, +0xda,0x70,0x11,0x0a,0x32,0x68,0x99,0x70,0x11,0x0e,0x19,0x71,0x11,0x0c,0x59,0x71, +0x11,0x0a,0xda,0x71,0x99,0x71,0x32,0x4b,0x08,0x22,0x1a,0x80,0xdb,0xe7,0xdf,0xf8, +0xf4,0x80,0x98,0xf8,0x00,0x30,0x00,0x2b,0x35,0xd1,0x2b,0x4d,0x95,0xf9,0x0c,0x30, +0x00,0x2b,0x2e,0xda,0x29,0x4b,0x08,0x46,0x1b,0x68,0x9b,0x68,0x98,0x47,0x00,0x28, +0x40,0xf0,0x96,0x80,0xf1,0x78,0xb3,0x78,0x09,0x04,0x41,0xea,0x03,0x61,0x73,0x79, +0xf2,0x79,0x19,0x43,0x33,0x79,0x2c,0x4f,0x41,0xea,0x03,0x21,0x33,0x7a,0x2b,0x4e, +0x43,0xea,0x02,0x22,0x32,0x60,0x39,0x60,0x92,0xb2,0x20,0x46,0xff,0xf7,0xc6,0xfe, +0x00,0x28,0xc0,0xf2,0x1a,0x81,0x02,0x23,0x88,0xf8,0x00,0x30,0x21,0x4b,0x3a,0x68, +0x1b,0x68,0x5a,0x43,0x3a,0x60,0x32,0x68,0x53,0x43,0xaa,0x68,0x33,0x60,0x9a,0x42, +0x01,0xd0,0x68,0x7b,0x04,0xe1,0x12,0x4b,0x1c,0x4d,0x4f,0xf4,0x80,0x52,0x1a,0x80, +0x2b,0x68,0x0e,0x4a,0xb3,0xf5,0x80,0x5f,0x34,0xbf,0x98,0x46,0x4f,0xf4,0x80,0x58, +0x15,0x4e,0x14,0x4b,0x11,0x68,0x1b,0x68,0x32,0x68,0x0f,0x69,0xb2,0xfb,0xf3,0xf2, +0xb8,0xfb,0xf3,0xf3,0x9b,0xb2,0x20,0x46,0x06,0x49,0xb8,0x47,0x00,0x28,0x23,0xda, +0x20,0x46,0x04,0x21,0x11,0x22,0xaa,0xe0,0x04,0xb0,0x00,0x20,0xec,0x78,0x00,0x20, +0x36,0xb0,0x00,0x20,0x00,0xa0,0x00,0x20,0xcc,0x9f,0x00,0x20,0xfc,0x9f,0x00,0x20, +0xd4,0x9f,0x00,0x20,0x7f,0x68,0x00,0x20,0x77,0x68,0x00,0x20,0x6f,0x68,0x00,0x20, +0xc4,0x9f,0x00,0x20,0xc8,0x9f,0x00,0x20,0xf4,0x9f,0x00,0x20,0xd0,0x9f,0x00,0x20, +0xf8,0x9f,0x00,0x20,0x34,0xb0,0x00,0x20,0x66,0x4b,0x81,0x21,0x18,0x68,0x66,0x4a, +0x43,0x46,0xfe,0xf7,0x9d,0xff,0x33,0x68,0x64,0x4a,0x43,0x44,0x91,0x68,0x33,0x60, +0x2b,0x68,0xc8,0xeb,0x01,0x01,0xc8,0xeb,0x03,0x03,0x2b,0x60,0x91,0x60,0x00,0x2b, +0x40,0xf0,0xb1,0x80,0x5e,0x4a,0x03,0x21,0x11,0x70,0x1d,0x46,0xae,0xe0,0x5c,0x4b, +0x1b,0x78,0x00,0x2b,0x4f,0xd1,0x5b,0x4b,0x93,0xf9,0x0c,0x20,0x00,0x2a,0x01,0xda, +0x58,0x7b,0x9d,0xe0,0x58,0x4d,0x08,0x46,0x2b,0x68,0x9b,0x68,0x98,0x47,0x18,0xb1, +0x20,0x46,0x02,0x21,0x3a,0x22,0x5a,0xe0,0x2b,0x68,0x20,0x46,0xdb,0x68,0x98,0x47, +0x05,0x46,0x02,0x21,0x20,0x46,0x27,0x22,0x00,0x2d,0x50,0xd1,0xf1,0x78,0xb3,0x78, +0x09,0x04,0x41,0xea,0x03,0x61,0x73,0x79,0xf2,0x79,0x19,0x43,0x33,0x79,0x4b,0x4f, +0x41,0xea,0x03,0x21,0x33,0x7a,0x4a,0x4e,0x43,0xea,0x02,0x22,0x32,0x60,0x39,0x60, +0x92,0xb2,0x20,0x46,0xff,0xf7,0x22,0xfe,0x00,0x28,0x76,0xdb,0x45,0x4b,0x3a,0x68, +0x1b,0x68,0x31,0x68,0x5a,0x43,0x59,0x43,0x3a,0x60,0x3e,0x4a,0x31,0x60,0x93,0x68, +0x8b,0x42,0x18,0xbf,0x50,0x7b,0x63,0xd1,0x39,0x4a,0x01,0x21,0x11,0x70,0x35,0x4a, +0xb3,0xf5,0x80,0x5f,0x28,0xbf,0x4f,0xf4,0x80,0x53,0x9b,0xb2,0x10,0x68,0x32,0x4a, +0xfe,0xf7,0x1a,0xff,0x5a,0xe0,0x36,0x4d,0x33,0x4a,0x2b,0x68,0x33,0x4e,0xb3,0xf5, +0x80,0x5f,0x34,0xbf,0x98,0x46,0x4f,0xf4,0x80,0x58,0x32,0x4b,0x11,0x68,0x1b,0x68, +0x32,0x68,0x4f,0x69,0xb2,0xfb,0xf3,0xf2,0xb8,0xfb,0xf3,0xf3,0x9b,0xb2,0x20,0x46, +0x25,0x49,0xb8,0x47,0x00,0x28,0x05,0xda,0x20,0x46,0x04,0x21,0x03,0x22,0xff,0xf7, +0xcf,0xfd,0x3a,0xe0,0x33,0x68,0x21,0x4a,0x43,0x44,0x91,0x68,0x33,0x60,0x2b,0x68, +0xc8,0xeb,0x01,0x01,0xc8,0xeb,0x03,0x03,0x2b,0x60,0x91,0x60,0x2b,0xb9,0xd9,0xf8, +0x00,0x00,0x00,0x21,0x00,0xf0,0x9e,0xf8,0x25,0xe0,0xb3,0xf5,0x80,0x5f,0x28,0xbf, +0x4f,0xf4,0x80,0x53,0x9b,0xb2,0xd9,0xf8,0x00,0x00,0x01,0x21,0x12,0x4a,0xfe,0xf7, +0xdb,0xfe,0x18,0xe0,0x55,0x78,0x15,0xf0,0x02,0x05,0x03,0xd0,0x08,0x46,0x24,0x22, +0x05,0x21,0xd4,0xe7,0x12,0x4b,0x08,0x46,0x1a,0x88,0x10,0x4b,0x19,0x68,0xff,0xf7, +0xb5,0xfd,0x00,0x28,0xa4,0xbf,0x10,0x4b,0x1d,0x80,0x07,0xda,0x05,0xe0,0x20,0x46, +0x05,0x21,0x20,0x22,0xc3,0xe7,0x00,0x25,0x00,0xe0,0xff,0x25,0x68,0xb2,0xbd,0xe8, +0xfe,0x83,0x00,0xbf,0xf8,0x9f,0x00,0x20,0x00,0xa0,0x00,0x20,0x24,0xb0,0x00,0x20, +0x34,0xb0,0x00,0x20,0x04,0xb0,0x00,0x20,0xec,0x78,0x00,0x20,0xf4,0x9f,0x00,0x20, +0xd0,0x9f,0x00,0x20,0xc8,0x9f,0x00,0x20,0x36,0xb0,0x00,0x20,0x70,0xb5,0x0e,0x4b, +0x04,0x46,0x1a,0x7b,0x0d,0x4d,0x32,0xb9,0x9b,0x68,0x23,0xb1,0x2b,0x78,0x13,0xb9, +0x01,0x21,0xfe,0xf7,0xd1,0xfe,0x81,0x21,0x20,0x46,0xfe,0xf7,0xcd,0xfe,0x2b,0x78, +0x02,0x2b,0x07,0xd1,0x04,0x4a,0x20,0x46,0x01,0x21,0x1f,0x23,0xbd,0xe8,0x70,0x40, +0xfe,0xf7,0x8a,0xbe,0x70,0xbd,0x00,0xbf,0x04,0xb0,0x00,0x20,0x00,0xb0,0x00,0x20, +0x0d,0x4b,0x10,0xb5,0x04,0x46,0x00,0x20,0x18,0x70,0x0c,0x4b,0x18,0x70,0x0c,0x4b, +0x1b,0x68,0x1b,0x68,0x98,0x47,0x01,0x21,0x20,0x46,0xfe,0xf7,0xe9,0xfe,0x81,0x21, +0x20,0x46,0xfe,0xf7,0xe5,0xfe,0x07,0x4a,0x20,0x46,0x01,0x21,0x1f,0x23,0xbd,0xe8, +0x10,0x40,0xfe,0xf7,0x69,0xbe,0x00,0xbf,0x34,0xb0,0x00,0x20,0x00,0xb0,0x00,0x20, +0xec,0x78,0x00,0x20,0x04,0xb0,0x00,0x20,0x04,0x4b,0x00,0x22,0x1a,0x70,0x04,0x4b, +0x01,0x21,0x04,0x4a,0x19,0x70,0x1f,0x23,0xfe,0xf7,0x56,0xbe,0x34,0xb0,0x00,0x20, +0x00,0xb0,0x00,0x20,0x04,0xb0,0x00,0x20,0x01,0x4b,0x00,0x22,0x1a,0x70,0x70,0x47, +0x34,0xb0,0x00,0x20,0x0a,0x4a,0x0b,0x4b,0x10,0xb5,0x13,0x60,0x0a,0x4b,0x11,0x73, +0x00,0x21,0x19,0x70,0x81,0x21,0x0d,0x23,0x04,0x46,0xfe,0xf7,0x59,0xfe,0x07,0x4a, +0x20,0x46,0x01,0x21,0x1f,0x23,0xbd,0xe8,0x10,0x40,0xfe,0xf7,0x35,0xbe,0x00,0xbf, +0x24,0xb0,0x00,0x20,0x55,0x53,0x42,0x53,0x34,0xb0,0x00,0x20,0x04,0xb0,0x00,0x20, +0x2d,0xe9,0xf0,0x41,0xdf,0xf8,0xd4,0x80,0x04,0x46,0x98,0xf8,0x00,0x70,0x17,0xb1, +0x01,0x2f,0x54,0xd1,0x47,0xe0,0x2b,0x4d,0x2b,0x4e,0x6b,0x68,0x01,0x21,0x73,0x60, +0xab,0x68,0xb3,0x60,0xff,0xf7,0xdc,0xfa,0x1f,0x28,0x2a,0x46,0x0a,0xd1,0x29,0x68, +0x26,0x4b,0x99,0x42,0x06,0xd1,0x69,0x7b,0x01,0x29,0x03,0xd8,0xab,0x7b,0x0b,0xb1, +0x10,0x2b,0x08,0xd9,0x50,0x7b,0x05,0x21,0x20,0x22,0xff,0xf7,0xd9,0xfc,0x20,0x4b, +0x02,0x22,0x1a,0x70,0x06,0xe0,0x20,0x46,0x05,0xf1,0x0f,0x02,0xff,0xf7,0x08,0xfd, +0x00,0x28,0x03,0xda,0x20,0x46,0xbd,0xe8,0xf0,0x41,0x4f,0xe7,0x98,0xf8,0x00,0x30, +0x01,0x3b,0xdb,0xb2,0x02,0x2b,0x22,0xd9,0x16,0x4b,0x20,0x46,0x19,0x88,0xd9,0xb1, +0xab,0x68,0xb2,0x68,0x99,0x42,0x38,0xbf,0x0b,0x46,0x9b,0xb2,0xd2,0x1a,0xb2,0x60, +0x04,0x22,0x88,0xf8,0x00,0x20,0x10,0x4a,0x20,0x46,0x81,0x21,0x37,0x73,0xbd,0xe8, +0xf0,0x41,0xfe,0xf7,0xf5,0xbd,0x07,0x4a,0x51,0x7b,0x0f,0x32,0xff,0xf7,0xe0,0xfc, +0x00,0x28,0x04,0xda,0x20,0x46,0x39,0x46,0xbd,0xe8,0xf0,0x41,0x82,0xe7,0xbd,0xe8, +0xf0,0x81,0x00,0xbf,0x04,0xb0,0x00,0x20,0x24,0xb0,0x00,0x20,0x55,0x53,0x42,0x43, +0x00,0xb0,0x00,0x20,0x36,0xb0,0x00,0x20,0x00,0xa0,0x00,0x20,0x34,0xb0,0x00,0x20, +0x10,0xb5,0x0c,0x4b,0x04,0x46,0x1b,0x78,0x02,0x2b,0x03,0xd0,0x10,0xd3,0x04,0x2b, +0x0e,0xd8,0x09,0xe0,0x08,0x4a,0x51,0x7b,0x0f,0x32,0xff,0xf7,0xb9,0xfc,0x00,0x28, +0x06,0xda,0x20,0x46,0x01,0x21,0x00,0xe0,0x00,0x21,0xbd,0xe8,0x10,0x40,0x59,0xe7, +0x10,0xbd,0x00,0xbf,0x34,0xb0,0x00,0x20,0x04,0xb0,0x00,0x20,0x10,0xb5,0x09,0x4c, +0x23,0x78,0x02,0x2b,0x05,0xd1,0x81,0x21,0xfe,0xf7,0xce,0xfd,0x00,0x23,0x23,0x70, +0x10,0xbd,0x0a,0x06,0x05,0xd5,0x01,0x2b,0x03,0xd0,0x01,0x21,0xbd,0xe8,0x10,0x40, +0x40,0xe7,0x10,0xbd,0x00,0xb0,0x00,0x20,0x20,0x23,0x0b,0x80,0x00,0x48,0x70,0x47, +0x9c,0x77,0x00,0x20,0x08,0xb5,0xff,0xf7,0x53,0xff,0x00,0x20,0x08,0xbd,0x08,0xb5, +0xff,0xf7,0xbe,0xff,0x00,0x20,0x08,0xbd,0xf8,0xb5,0x0b,0x78,0x05,0x46,0x13,0xf0, +0x60,0x06,0x0c,0x46,0x28,0xd0,0x20,0x2e,0x49,0xd1,0x4a,0x78,0xfe,0x2a,0x02,0xd0, +0xff,0x2a,0x1b,0xd1,0x11,0xe0,0x4e,0x88,0xc6,0xb9,0xcf,0x88,0x01,0x2f,0x15,0xd1, +0x1a,0x06,0x13,0xd5,0x1f,0x4b,0x1b,0x68,0x9b,0x69,0x98,0x47,0x1e,0x49,0xc0,0xb2, +0x08,0x70,0x58,0xb1,0x28,0x46,0x3a,0x46,0x18,0xe0,0x4a,0x88,0x32,0xb9,0xce,0x88, +0x26,0xb9,0x1b,0x06,0x02,0xd4,0xff,0xf7,0xef,0xfe,0x29,0xe0,0x28,0x46,0x21,0x46, +0xff,0xf7,0x36,0xfa,0x02,0x26,0x23,0xe0,0x4b,0x78,0x0a,0x2b,0x04,0xd0,0x0b,0x2b, +0x07,0xd0,0x01,0x2b,0x1c,0xd1,0x08,0xe0,0x10,0x49,0x01,0x22,0xff,0xf7,0xb0,0xf9, +0x16,0xe0,0x4a,0x88,0x0c,0x4b,0x5a,0x70,0x12,0xe0,0x09,0x79,0xfe,0xf7,0xa8,0xfd, +0x21,0x79,0x28,0x46,0xfe,0xf7,0x17,0xfd,0xa1,0x88,0x28,0x46,0xc9,0xb2,0x40,0x22, +0x02,0x23,0xfe,0xf7,0xef,0xfc,0x21,0x79,0x28,0x46,0xff,0xf7,0x87,0xff,0x00,0x26, +0x30,0x46,0xf8,0xbd,0xec,0x78,0x00,0x20,0x24,0x79,0x00,0x20,0x25,0x79,0x00,0x20, +0x10,0xb5,0x81,0x21,0x04,0x46,0xfe,0xf7,0xfe,0xfc,0x01,0x21,0x20,0x46,0xfe,0xf7, +0xfa,0xfc,0x20,0x46,0xff,0xf7,0xc0,0xfe,0x00,0x20,0x10,0xbd,0x10,0xb5,0x04,0x46, +0xff,0xf7,0xee,0xff,0x81,0x21,0x40,0x22,0x02,0x23,0x20,0x46,0xfe,0xf7,0xca,0xfc, +0x01,0x21,0x40,0x22,0x02,0x23,0x20,0x46,0xfe,0xf7,0xc4,0xfc,0x20,0x46,0xff,0xf7, +0x77,0xfe,0x00,0x20,0x10,0xbd,0x00,0xbf,0x12,0x23,0x0b,0x80,0x00,0x48,0x70,0x47, +0xe8,0x77,0x00,0x20,0x04,0x23,0x0b,0x80,0x00,0x48,0x70,0x47,0xfa,0x77,0x00,0x20, +0x10,0xb5,0x04,0x4c,0x0a,0x46,0x04,0x48,0x21,0x46,0xff,0xf7,0x9b,0xfb,0x20,0x46, +0x10,0xbd,0x00,0xbf,0x84,0x9f,0x00,0x20,0x58,0x76,0x00,0x20,0x10,0xb5,0x04,0x4c, +0x0a,0x46,0x04,0x48,0x21,0x46,0xff,0xf7,0x8d,0xfb,0x20,0x46,0x10,0xbd,0x00,0xbf, +0x84,0x9f,0x00,0x20,0x66,0x76,0x00,0x20,0x10,0xb5,0x04,0x4c,0x0a,0x46,0x04,0x48, +0x21,0x46,0xff,0xf7,0x7f,0xfb,0x20,0x46,0x10,0xbd,0x00,0xbf,0x84,0x9f,0x00,0x20, +0x71,0x76,0x00,0x20,0x10,0xb5,0x04,0x4c,0x0a,0x46,0x04,0x48,0x21,0x46,0xff,0xf7, +0x71,0xfb,0x20,0x46,0x10,0xbd,0x00,0xbf,0x84,0x9f,0x00,0x20,0x7e,0x76,0x00,0x20, +0x10,0xb5,0x04,0x4c,0x0a,0x46,0x04,0x48,0x21,0x46,0xff,0xf7,0x63,0xfb,0x20,0x46, +0x10,0xbd,0x00,0xbf,0x84,0x9f,0x00,0x20,0x84,0x76,0x00,0x20,0x73,0xb5,0x01,0x20, +0x1c,0x4c,0x01,0x46,0xfd,0xf7,0x9a,0xfb,0x4f,0xf4,0xc0,0x53,0x00,0x25,0x03,0x26, +0x00,0x93,0x20,0x46,0x02,0x23,0x69,0x46,0x8d,0xf8,0x04,0x30,0x8d,0xf8,0x05,0x60, +0x8d,0xf8,0x06,0x50,0x8d,0xf8,0x07,0x50,0xfd,0xf7,0xf6,0xfc,0x20,0x46,0x0b,0x21, +0x0a,0x22,0xfd,0xf7,0x72,0xfd,0x0a,0x22,0x20,0x46,0x0c,0x21,0xfd,0xf7,0x6d,0xfd, +0x4f,0xf4,0x00,0x73,0x8d,0xf8,0x05,0x60,0x20,0x46,0x01,0x26,0x69,0x46,0x00,0x93, +0x8d,0xf8,0x04,0x50,0x8d,0xf8,0x06,0x60,0x8d,0xf8,0x07,0x50,0xfd,0xf7,0xdc,0xfc, +0x31,0x46,0x4f,0xf4,0x80,0x40,0xfd,0xf7,0x99,0xfb,0x80,0x20,0x31,0x46,0xfd,0xf7, +0x71,0xfb,0x7c,0xbd,0x00,0x00,0x02,0x40,0x07,0xb5,0x4f,0xf4,0xc0,0x60,0xfd,0xf7, +0xe5,0xfe,0x43,0x23,0x8d,0xf8,0x04,0x30,0x03,0x22,0x01,0x23,0x01,0xa8,0x8d,0xf8, +0x05,0x30,0x8d,0xf8,0x06,0x20,0x8d,0xf8,0x07,0x30,0xfd,0xf7,0xe1,0xfe,0x0e,0xbd, +0x05,0x4b,0x1a,0x68,0x05,0x4b,0xb2,0xfb,0xf3,0xf3,0x58,0x43,0x00,0x23,0x01,0x33, +0x83,0x42,0xfc,0xd9,0x70,0x47,0x00,0xbf,0x48,0x77,0x00,0x20,0x40,0x42,0x0f,0x00, +0x4f,0xf4,0x7a,0x73,0x58,0x43,0xeb,0xe7,0xc9,0x08,0x2d,0xe9,0xf0,0x47,0x04,0x46, +0xd4,0x20,0x00,0xfb,0x01,0x41,0x55,0x48,0xa9,0x2c,0x01,0x44,0x88,0xbf,0xd4,0x39, +0x15,0x2a,0x09,0xd8,0x06,0x20,0x42,0x43,0x5b,0x07,0xd0,0xb2,0x40,0xf1,0x9b,0x80, +0x40,0x00,0xc0,0xb2,0xbd,0xe8,0xf0,0x87,0xa0,0x1d,0xbf,0x2a,0xc0,0xb2,0x4c,0x4d, +0x03,0xd8,0x05,0x26,0x06,0xfb,0x02,0x55,0xa0,0x3d,0xde,0x07,0x07,0xd4,0x13,0xf0, +0x02,0x06,0x05,0xd0,0x47,0x4e,0x36,0x78,0xc6,0xf3,0x80,0x16,0x00,0xe0,0x01,0x26, +0x5f,0x07,0x56,0xd5,0x2e,0x2a,0x44,0x4b,0x0e,0xd0,0x0c,0x34,0xbf,0x2a,0xe0,0xb2, +0x0e,0xd8,0x01,0x24,0x42,0x2a,0x08,0xd0,0x02,0x24,0x53,0x2a,0x05,0xd0,0x55,0x2a, +0x0c,0xbf,0x03,0x24,0x00,0x24,0x00,0xe0,0x00,0x24,0x14,0x25,0x05,0xfb,0x04,0x33, +0xdf,0xf8,0xe8,0x90,0x05,0x25,0xbf,0x2a,0x0e,0xd8,0x3d,0xb1,0x93,0xf8,0x00,0x80, +0x9f,0x7a,0x93,0xf8,0x01,0xc0,0xdc,0x7a,0x01,0x33,0x03,0xe0,0xac,0x46,0x2f,0x46, +0xa8,0x46,0x2c,0x46,0x01,0x33,0x0c,0xe0,0x3d,0xb1,0x93,0xf8,0x00,0x80,0x5f,0x78, +0x93,0xf8,0x02,0xc0,0xdc,0x78,0x04,0x33,0x03,0xe0,0x2c,0x46,0xac,0x46,0x2f,0x46, +0xa8,0x46,0x5e,0xb1,0x6f,0xea,0x08,0x08,0x6f,0xea,0x0c,0x0c,0xff,0x43,0xe4,0x43, +0x5f,0xfa,0x88,0xf8,0x5f,0xfa,0x8c,0xfc,0xff,0xb2,0xe4,0xb2,0x01,0xf1,0xd5,0x0a, +0xca,0x45,0x3f,0xbf,0x81,0xf8,0x00,0x80,0x81,0xf8,0x01,0xc0,0x81,0xf8,0xd4,0x70, +0x81,0xf8,0xd5,0x40,0x38,0xbf,0x02,0x31,0x15,0xf1,0xff,0x35,0xc3,0xd2,0xbd,0xe8, +0xf0,0x87,0x13,0xf0,0x08,0x03,0x08,0xd0,0x00,0x2e,0x14,0xbf,0xff,0x23,0x00,0x23, +0x05,0x34,0x01,0xf8,0x01,0x3b,0xe0,0xb2,0x01,0x23,0x14,0x4f,0x05,0x22,0x04,0x2a, +0x14,0xbf,0x4f,0xf0,0x00,0x0c,0x03,0xf0,0x01,0x0c,0x15,0xf8,0x01,0x4b,0xbc,0xf1, +0x00,0x0f,0x06,0xd1,0xb9,0x42,0x04,0xd2,0x0e,0xb1,0xe4,0x43,0xe4,0xb2,0x01,0xf8, +0x01,0x4b,0x01,0x3a,0xeb,0xd1,0x09,0x4b,0x99,0x42,0x04,0xd2,0x00,0x2e,0x14,0xbf, +0xff,0x26,0x00,0x26,0x0e,0x70,0xbd,0xe8,0xf0,0x87,0x00,0xbf,0x50,0x79,0x00,0x20, +0x86,0x68,0x00,0x20,0x46,0x82,0x00,0x20,0x70,0x6a,0x00,0x20,0xc6,0x7f,0x00,0x20, +0x00,0x23,0x41,0xe7,0xf8,0xb5,0x0f,0x46,0x1c,0x46,0x9d,0xf8,0x18,0x60,0x15,0x46, +0x08,0xe0,0x15,0xf8,0x01,0x2b,0x3a,0xb1,0x39,0x46,0x33,0x46,0xff,0xf7,0x34,0xff, +0x01,0x3c,0xe4,0xb2,0x00,0x2c,0xf4,0xd1,0xf8,0xbd,0x13,0xb5,0x00,0x24,0x00,0x94, +0xff,0xf7,0xe8,0xff,0x1c,0xbd,0x70,0xb5,0x0e,0x46,0x14,0x46,0x1d,0x46,0x14,0xf8, +0x01,0x2b,0x22,0xb1,0x31,0x46,0x2b,0x46,0xff,0xf7,0x1e,0xff,0xf7,0xe7,0x70,0xbd, +0x03,0x46,0x00,0x20,0x0a,0x46,0x19,0x46,0x03,0x46,0xec,0xe7,0x00,0x23,0xea,0xe7, +0xf8,0xb5,0x00,0xf1,0x14,0x04,0x06,0x46,0x0f,0x46,0x15,0x46,0xe4,0xb2,0x05,0xf0, +0x0f,0x02,0x05,0x3c,0x09,0x2a,0xe4,0xb2,0x02,0xd9,0x37,0x32,0x08,0x23,0x01,0xe0, +0x30,0x32,0x00,0x23,0x20,0x46,0x39,0x46,0xff,0xf7,0xfe,0xfe,0x2d,0x09,0xb4,0x42, +0xed,0xd1,0xf8,0xbd,0x07,0x4a,0x02,0xf5,0xd4,0x63,0x98,0x42,0x09,0xd2,0x92,0xf8, +0xa0,0x26,0x03,0x78,0x1a,0xb1,0x01,0x2a,0x43,0xea,0x01,0x03,0x00,0xd0,0x4b,0x40, +0x03,0x70,0x70,0x47,0x26,0x79,0x00,0x20,0xcb,0x08,0xd4,0x22,0x02,0xfb,0x03,0x00, +0x04,0x4b,0x01,0xf0,0x07,0x01,0xc0,0x18,0x01,0x23,0x13,0xfa,0x01,0xf1,0xc9,0xb2, +0xe0,0xe7,0x00,0xbf,0x50,0x79,0x00,0x20,0x00,0x2a,0x2d,0xe9,0xf0,0x41,0x14,0x46, +0x04,0xda,0xd4,0xb2,0x20,0x18,0x64,0x42,0xc0,0xb2,0x64,0xb2,0xca,0x08,0x4f,0xf0, +0x01,0x08,0x01,0xf0,0x07,0x01,0x08,0xfa,0x01,0xf8,0xd4,0x25,0x05,0xfb,0x02,0x05, +0x0e,0x4f,0x2a,0x35,0x7d,0x19,0x5f,0xfa,0x88,0xf8,0x07,0xf5,0xd4,0x67,0x11,0xe0, +0xbd,0x42,0x11,0xd2,0x13,0xf0,0x01,0x0f,0x4f,0xea,0x63,0x06,0x08,0xbf,0xf3,0xb2, +0x05,0xd0,0x28,0x46,0x41,0x46,0xff,0xf7,0xb5,0xff,0x46,0xf0,0x80,0x03,0x01,0x3c, +0x64,0xb2,0x01,0x35,0x00,0x2c,0xeb,0xd1,0xbd,0xe8,0xf0,0x81,0x26,0x79,0x00,0x20, +0x6b,0xb1,0x0c,0x4b,0x1b,0x78,0x5b,0x06,0x12,0xd4,0x08,0xe0,0x0b,0x78,0x01,0x30, +0xdb,0x43,0x01,0xf8,0x01,0x3b,0xc0,0xb2,0x90,0x42,0xf7,0xd3,0x70,0x47,0xd4,0x23, +0xc9,0x08,0x03,0xfb,0x01,0x01,0x04,0x4b,0x12,0x18,0xd2,0xb2,0xc9,0x18,0xf3,0xe7, +0x70,0x47,0x00,0xbf,0x46,0x82,0x00,0x20,0x50,0x79,0x00,0x20,0xff,0x23,0xab,0xe7, +0x00,0x2a,0x38,0xb5,0x14,0x46,0x04,0xda,0xd4,0xb2,0x61,0x18,0x64,0x42,0xc9,0xb2, +0x64,0xb2,0xcb,0x08,0xd4,0x25,0x05,0xfb,0x03,0x05,0x15,0x4b,0x11,0xf0,0x07,0x01, +0x1d,0x44,0x18,0xd0,0x01,0x22,0x12,0xfa,0x01,0xf3,0x0c,0x19,0x08,0x3c,0xdb,0xb2, +0x64,0xb2,0x59,0x42,0x00,0x2c,0x04,0xda,0x04,0xf1,0x08,0x01,0x12,0xfa,0x01,0xf1, +0xc9,0x1a,0xc9,0xb2,0x28,0x46,0x03,0xe0,0x08,0x3c,0x64,0xb2,0x28,0x46,0xff,0x21, +0xff,0xf7,0x60,0xff,0xd4,0x35,0x07,0x2c,0xf6,0xdc,0x00,0x2c,0x07,0xdd,0x01,0x21, +0xa1,0x40,0x01,0x39,0xc9,0xb2,0x28,0x46,0xbd,0xe8,0x38,0x40,0x52,0xe7,0x38,0xbd, +0x50,0x79,0x00,0x20,0x2d,0xe9,0xf0,0x4f,0x13,0xf0,0x20,0x07,0x85,0xb0,0x04,0x46, +0x8b,0x46,0x01,0x92,0x1e,0x46,0x9d,0xf9,0x38,0xa0,0x04,0xd0,0x13,0xf0,0x10,0x0f, +0x0c,0xbf,0x01,0x27,0x02,0x27,0x01,0x9d,0x00,0x23,0x00,0x2d,0xb8,0xbf,0x6d,0x42, +0xba,0xf1,0x00,0x0f,0xbe,0xbf,0xca,0xf1,0x00,0x0a,0x4f,0xfa,0x8a,0xfa,0x01,0x23, +0x71,0x06,0x02,0x93,0x25,0xd5,0x01,0x9b,0x00,0x2b,0x01,0xda,0x05,0x34,0xe4,0xb2, +0x42,0xf2,0x0f,0x73,0x9d,0x42,0x02,0xdd,0x05,0x34,0xe4,0xb2,0x02,0xe0,0xb5,0xf5, +0x7a,0x7f,0x02,0xdb,0x05,0x34,0xe4,0xb2,0x01,0xe0,0x63,0x2d,0x02,0xdd,0x05,0x34, +0xe4,0xb2,0x01,0xe0,0x09,0x2d,0x01,0xdd,0x05,0x34,0xe4,0xb2,0x5f,0xb1,0x02,0x2f, +0x03,0xd1,0x63,0x2d,0x07,0xdc,0x05,0x34,0xe4,0xb2,0x09,0x2d,0x03,0xdc,0x05,0x34, +0x00,0xe0,0x05,0x3c,0xe4,0xb2,0x31,0x4b,0xa2,0x1d,0x02,0x2f,0x83,0xf8,0xa1,0x26, +0x01,0xd1,0x10,0x3e,0xf6,0xb2,0x0b,0xf1,0x06,0x03,0xdb,0xb2,0x4f,0xf0,0x01,0x08, +0x03,0x93,0x3e,0xe0,0x0a,0x23,0x95,0xfb,0xf3,0xf2,0x03,0xfb,0x12,0x52,0x30,0x32, +0xd2,0xb2,0x20,0x46,0x59,0x46,0x33,0x46,0xff,0xf7,0xe6,0xfd,0x47,0x45,0x18,0xbf, +0xa1,0x46,0x14,0xd1,0xa4,0xf1,0x02,0x09,0x16,0xf0,0x01,0x0f,0x04,0xf1,0xff,0x34, +0x5f,0xfa,0x89,0xf9,0xe0,0xb2,0x04,0xd0,0x59,0x46,0x07,0x22,0xff,0xf7,0x50,0xff, +0x02,0xe0,0x03,0x99,0xff,0xf7,0xe8,0xfe,0x09,0x2d,0xc8,0xbf,0x00,0x27,0x0a,0x23, +0x95,0xfb,0xf3,0xf5,0x85,0xb9,0x4f,0xb1,0x02,0x2f,0x18,0xbf,0x2f,0x46,0x0b,0xd1, +0xb8,0xf1,0x01,0x0f,0x0c,0xbf,0x02,0x27,0x00,0x27,0x05,0xe0,0xf2,0x06,0x0b,0xd5, +0x02,0x9b,0x0b,0xb9,0x10,0x3e,0xf6,0xb2,0xa9,0xf1,0x05,0x04,0xe4,0xb2,0x08,0xf1, +0x01,0x08,0xd0,0x45,0xbe,0xdd,0xa1,0x46,0x01,0x9b,0x00,0x2b,0x0a,0xda,0xa9,0xf1, +0x05,0x09,0x5f,0xfa,0x89,0xf0,0x59,0x46,0x2d,0x22,0x33,0x46,0x05,0xb0,0xbd,0xe8, +0xf0,0x4f,0xa1,0xe5,0x05,0xb0,0xbd,0xe8,0xf0,0x8f,0x00,0xbf,0x26,0x79,0x00,0x20, +0x13,0xb5,0x05,0x24,0x00,0x94,0xff,0xf7,0x4d,0xff,0x1c,0xbd,0x00,0x23,0xf7,0xe7, +0x02,0x48,0x00,0x21,0x4f,0xf4,0xd4,0x62,0x02,0xf0,0x8a,0xbf,0x26,0x79,0x00,0x20, +0xf8,0xb5,0x03,0x69,0x0d,0x46,0x01,0xf1,0x09,0x01,0x00,0x2b,0x4f,0xd0,0x43,0x69, +0x0c,0x46,0x1f,0x7b,0x00,0x26,0x07,0xf0,0x08,0x0c,0x9a,0x5d,0x21,0x46,0x20,0x2a, +0x12,0xd0,0x05,0x2a,0x08,0xbf,0xe5,0x22,0xbc,0xf1,0x00,0x0f,0x06,0xd0,0xa2,0xf1, +0x41,0x01,0xc9,0xb2,0x19,0x29,0x01,0xd8,0x20,0x32,0xd2,0xb2,0x01,0x36,0x04,0xf8, +0x01,0x2b,0x08,0x2e,0x21,0x46,0xe8,0xd1,0x1a,0x7a,0x20,0x2a,0x18,0xd0,0x22,0x46, +0x2e,0x21,0x02,0xf8,0x01,0x1b,0x08,0x26,0x07,0xf0,0x10,0x07,0x9c,0x5d,0x11,0x46, +0x20,0x2c,0x0d,0xd0,0x37,0xb1,0xa4,0xf1,0x41,0x01,0xc9,0xb2,0x19,0x29,0x01,0xd8, +0x20,0x34,0xe4,0xb2,0x01,0x36,0x02,0xf8,0x01,0x4b,0x0b,0x2e,0x11,0x46,0xed,0xd1, +0xda,0x7a,0x2a,0x72,0x9a,0x7f,0xdc,0x7f,0x12,0x04,0x42,0xea,0x04,0x62,0x1c,0x7f, +0x22,0x43,0x5c,0x7f,0x42,0xea,0x04,0x22,0x2a,0x60,0x5c,0x7e,0x1a,0x7e,0x42,0xea, +0x04,0x22,0xaa,0x80,0xda,0x7d,0x9b,0x7d,0x43,0xea,0x02,0x23,0xeb,0x80,0x00,0x24, +0x0c,0x70,0xae,0x69,0x0e,0xb3,0xeb,0x69,0xfb,0xb1,0x03,0x69,0xb3,0xb1,0x02,0x8c, +0x4f,0xf6,0xff,0x73,0x9a,0x42,0x18,0xbf,0xc7,0x69,0x0a,0xd1,0x13,0xe0,0x00,0x21, +0x02,0xf0,0xfa,0xfa,0x60,0xb1,0xeb,0x69,0x01,0x3b,0x9c,0x42,0x0a,0xd2,0x30,0x55, +0x01,0x34,0x37,0xf8,0x02,0x0b,0x00,0x28,0xf1,0xd1,0x04,0xe0,0x1c,0x46,0x02,0xe0, +0x04,0x46,0x00,0xe0,0x00,0x24,0x00,0x23,0x33,0x55,0xf8,0xbd,0x08,0xb5,0x60,0xb1, +0x03,0x78,0x53,0xb1,0xc3,0x88,0x8b,0x42,0x09,0xd1,0x40,0x78,0x01,0xf0,0xfe,0xf9, +0x10,0xf0,0x01,0x00,0x18,0xbf,0x03,0x20,0x08,0xbd,0x09,0x20,0x08,0xbd,0x09,0x20, +0x08,0xbd,0x38,0xb5,0x43,0x6a,0x05,0x46,0x8b,0x42,0x0c,0x46,0x0c,0xd0,0x69,0xb1, +0x40,0x78,0x05,0xf1,0x28,0x01,0x22,0x46,0x01,0x23,0x01,0xf0,0x0f,0xfa,0x08,0xb9, +0x6c,0x62,0x38,0xbd,0x01,0x20,0x38,0xbd,0x00,0x20,0x38,0xbd,0x08,0x46,0x38,0xbd, +0x10,0xb5,0x04,0x46,0x0a,0x46,0x40,0x78,0x04,0xf1,0x28,0x01,0x01,0x23,0x01,0xf0, +0xfd,0xf9,0x80,0xbb,0x94,0xf8,0x26,0x32,0x94,0xf8,0x27,0x22,0x43,0xea,0x02,0x22, +0x17,0x4b,0x12,0xb2,0x9a,0x42,0x28,0xd1,0x94,0xf8,0x60,0x20,0x94,0xf8,0x61,0x30, +0x12,0x04,0x42,0xea,0x03,0x62,0x94,0xf8,0x5e,0x30,0x1a,0x43,0x94,0xf8,0x5f,0x30, +0x42,0xea,0x03,0x22,0x0f,0x4b,0x22,0xf0,0x7f,0x42,0x9a,0x42,0x16,0xd0,0x94,0xf8, +0x7c,0x00,0x94,0xf8,0x7d,0x20,0x00,0x04,0x40,0xea,0x02,0x60,0x94,0xf8,0x7a,0x20, +0x10,0x43,0x94,0xf8,0x7b,0x20,0x40,0xea,0x02,0x20,0x20,0xf0,0x7f,0x40,0xc0,0x1a, +0x18,0xbf,0x01,0x20,0x10,0xbd,0x03,0x20,0x10,0xbd,0x02,0x20,0x10,0xbd,0x00,0xbf, +0x55,0xaa,0xff,0xff,0x46,0x41,0x54,0x00,0x2d,0xe9,0xf0,0x41,0x03,0x68,0x1d,0x78, +0x30,0x3d,0x09,0x2d,0x05,0xd8,0x5a,0x78,0x3a,0x2a,0x02,0xd1,0x02,0x33,0x03,0x60, +0x01,0xe0,0x7f,0x4b,0x1d,0x78,0x00,0x2d,0x40,0xf0,0xe4,0x80,0x7c,0x4b,0x5c,0x68, +0x0c,0x60,0x00,0x2c,0x00,0xf0,0xe1,0x80,0x23,0x78,0x2b,0xb1,0x60,0x78,0x01,0xf0, +0x7d,0xf9,0xc2,0x07,0x40,0xf1,0xdc,0x80,0x00,0x20,0x20,0x70,0x60,0x70,0x01,0xf0, +0xdb,0xf8,0x10,0xf0,0x01,0x05,0x40,0xf0,0xd6,0x80,0x20,0x46,0x29,0x46,0xff,0xf7, +0x8f,0xff,0x01,0x28,0x16,0xd1,0x94,0xf8,0xea,0x31,0x00,0x2b,0x00,0xf0,0xd1,0x80, +0x94,0xf8,0xf0,0x51,0x94,0xf8,0xf1,0x31,0x2d,0x04,0x45,0xea,0x03,0x65,0x94,0xf8, +0xee,0x31,0x20,0x46,0x1d,0x43,0x94,0xf8,0xef,0x31,0x45,0xea,0x03,0x25,0x29,0x46, +0xff,0xf7,0x76,0xff,0x03,0x28,0x00,0xf0,0xb9,0x80,0x00,0x28,0x40,0xf0,0xb9,0x80, +0x94,0xf8,0x34,0x20,0x94,0xf8,0x33,0x30,0x43,0xea,0x02,0x23,0xb3,0xf5,0x00,0x7f, +0x40,0xf0,0xaf,0x80,0x94,0xf8,0x3f,0x60,0x94,0xf8,0x3e,0x30,0x53,0xea,0x06,0x26, +0x0d,0xd1,0x94,0xf8,0x4e,0x60,0x94,0xf8,0x4f,0x30,0x36,0x04,0x46,0xea,0x03,0x66, +0x94,0xf8,0x4c,0x30,0x1e,0x43,0x94,0xf8,0x4d,0x30,0x46,0xea,0x03,0x26,0x94,0xf8, +0x38,0x00,0x66,0x61,0x43,0x1e,0xdb,0xb2,0x01,0x2b,0xe0,0x70,0x00,0xf2,0x91,0x80, +0x94,0xf8,0x35,0x10,0xa1,0x70,0x00,0x29,0x00,0xf0,0x8b,0x80,0x4b,0x1e,0x0b,0x42, +0x40,0xf0,0x87,0x80,0x94,0xf8,0x39,0x30,0x94,0xf8,0x3a,0x20,0x43,0xea,0x02,0x22, +0x13,0x07,0x22,0x81,0x7d,0xd1,0x94,0xf8,0x3c,0x70,0x94,0xf8,0x3b,0x30,0x53,0xea, +0x07,0x23,0x0d,0xd1,0x94,0xf8,0x4a,0x30,0x94,0xf8,0x4b,0x70,0x1b,0x04,0x43,0xea, +0x07,0x63,0x94,0xf8,0x48,0x70,0x3b,0x43,0x94,0xf8,0x49,0x70,0x43,0xea,0x07,0x23, +0x94,0xf8,0x37,0xc0,0x94,0xf8,0x36,0x70,0x57,0xea,0x0c,0x2c,0x61,0xd0,0x00,0xfb, +0x06,0xf8,0x0c,0xeb,0x12,0x17,0x47,0x44,0xbb,0x42,0x5a,0xd3,0xdb,0x1b,0xb3,0xfb, +0xf1,0xf3,0x00,0x2b,0x55,0xd0,0x40,0xf6,0xf5,0x71,0x01,0x20,0x8b,0x42,0x05,0xd9, +0x4f,0xf6,0xf5,0x70,0x83,0x42,0x8c,0xbf,0x03,0x20,0x02,0x20,0x02,0x33,0x7f,0x19, +0x03,0x28,0x65,0x44,0x23,0x61,0x27,0x62,0xa5,0x61,0x12,0xd1,0x00,0x2a,0x40,0xd1, +0x94,0xf8,0x56,0x20,0x94,0xf8,0x57,0x10,0x12,0x04,0x42,0xea,0x01,0x62,0x94,0xf8, +0x54,0x10,0x9b,0x00,0x0a,0x43,0x94,0xf8,0x55,0x10,0x42,0xea,0x01,0x22,0xe2,0x61, +0x0d,0xe0,0x00,0x2a,0x2d,0xd0,0x45,0x44,0x02,0x28,0xe5,0x61,0x01,0xd1,0x5b,0x00, +0x05,0xe0,0x03,0x22,0x5a,0x43,0x03,0xf0,0x01,0x03,0x03,0xeb,0x52,0x03,0x03,0xf5, +0xfe,0x73,0x03,0x33,0xb6,0xeb,0x53,0x2f,0x1e,0xd3,0x11,0x4a,0x20,0x70,0x13,0x89, +0x00,0x20,0x01,0x33,0x9b,0xb2,0x13,0x81,0xe3,0x80,0x60,0x62,0x20,0x71,0xe0,0x60, +0xbd,0xe8,0xf0,0x81,0x0b,0x20,0xbd,0xe8,0xf0,0x81,0x0c,0x20,0xbd,0xe8,0xf0,0x81, +0x28,0x46,0xbd,0xe8,0xf0,0x81,0x03,0x20,0xbd,0xe8,0xf0,0x81,0x01,0x20,0xbd,0xe8, +0xf0,0x81,0x0d,0x20,0xbd,0xe8,0xf0,0x81,0x0d,0x20,0xbd,0xe8,0xf0,0x81,0x00,0xbf, +0xcc,0x7f,0x00,0x20,0x03,0x69,0x02,0x39,0x02,0x3b,0x99,0x42,0x3d,0xbf,0x82,0x78, +0x03,0x6a,0x02,0xfb,0x01,0x30,0x00,0x20,0x70,0x47,0x01,0x29,0xf8,0xb5,0x04,0x46, +0x0d,0x46,0x5b,0xd9,0x03,0x69,0x99,0x42,0x5a,0xd2,0x03,0x78,0x02,0x2b,0x28,0xd0, +0x03,0x2b,0x36,0xd0,0x01,0x2b,0x4e,0xd1,0x01,0xeb,0x51,0x06,0x81,0x69,0x01,0xeb, +0x56,0x21,0xff,0xf7,0x76,0xfe,0x00,0x28,0x45,0xd1,0xa1,0x69,0xf3,0x05,0x01,0x36, +0x04,0xeb,0xd3,0x53,0x01,0xeb,0x56,0x21,0x20,0x46,0x93,0xf8,0x28,0x70,0xff,0xf7, +0x68,0xfe,0x00,0x28,0x37,0xd1,0xf6,0x05,0x04,0xeb,0xd6,0x54,0x94,0xf8,0x28,0x00, +0xe9,0x07,0x47,0xea,0x00,0x20,0x01,0xd5,0x00,0x09,0xf8,0xbd,0x00,0x05,0x00,0x0d, +0xf8,0xbd,0x81,0x69,0x01,0xeb,0x15,0x21,0xff,0xf7,0x53,0xfe,0x18,0xbb,0x2d,0x06, +0x04,0xeb,0xd5,0x54,0x94,0xf8,0x29,0x00,0x94,0xf8,0x28,0x30,0x43,0xea,0x00,0x20, +0xf8,0xbd,0x81,0x69,0x01,0xeb,0xd5,0x11,0xff,0xf7,0x43,0xfe,0x98,0xb9,0x6d,0x06, +0x04,0xeb,0xd5,0x54,0x94,0xf8,0x2a,0x00,0x94,0xf8,0x2b,0x30,0x00,0x04,0x40,0xea, +0x03,0x60,0x94,0xf8,0x28,0x30,0x94,0xf8,0x29,0x70,0x18,0x43,0x40,0xea,0x07,0x20, +0x20,0xf0,0x70,0x40,0xf8,0xbd,0x4f,0xf0,0xff,0x30,0xf8,0xbd,0x01,0x20,0xf8,0xbd, +0x01,0x20,0xf8,0xbd,0x70,0xb5,0x04,0x46,0x0d,0x46,0xe1,0x80,0x81,0x68,0x01,0x29, +0x39,0xd0,0x03,0x68,0x1a,0x69,0x91,0x42,0x35,0xd2,0x79,0xb9,0x1a,0x78,0x03,0x2a, +0x01,0xd1,0xd9,0x69,0x51,0xb9,0x00,0x22,0xe2,0x60,0x1a,0x89,0xaa,0x42,0x82,0xbf, +0xdb,0x69,0x03,0xeb,0x15,0x13,0x23,0x61,0x25,0xd9,0x19,0xe0,0x9e,0x78,0x36,0x01, +0x0d,0xe0,0x20,0x68,0xff,0xf7,0x79,0xff,0x01,0x46,0x01,0x30,0x19,0xd0,0x01,0x29, +0x19,0xd9,0x23,0x68,0x1b,0x69,0x99,0x42,0x17,0xd2,0xad,0x1b,0xad,0xb2,0xb5,0x42, +0xef,0xd2,0xe1,0x60,0x20,0x68,0xff,0xf7,0x5d,0xff,0x00,0xeb,0x15,0x10,0x20,0x61, +0x23,0x68,0x05,0xf0,0x0f,0x05,0x28,0x33,0x03,0xeb,0x45,0x15,0x65,0x61,0x00,0x20, +0x70,0xbd,0x01,0x20,0x70,0xbd,0x02,0x20,0x70,0xbd,0x02,0x20,0x70,0xbd,0x70,0xb5, +0xc5,0x88,0x04,0x46,0x01,0x35,0xad,0xb2,0x00,0x2d,0x2a,0xd0,0x03,0x69,0x00,0x2b, +0x27,0xd0,0x15,0xf0,0x0f,0x06,0x1c,0xd1,0xc1,0x68,0x01,0x33,0x03,0x61,0x00,0x68, +0x19,0xb9,0x03,0x89,0xab,0x42,0x1c,0xd9,0x13,0xe0,0x83,0x78,0x01,0x3b,0x13,0xea, +0x15,0x13,0x0e,0xd1,0xff,0xf7,0x39,0xff,0x01,0x28,0x01,0x46,0x13,0xd9,0x43,0x1c, +0x13,0xd0,0x20,0x68,0x03,0x69,0x99,0x42,0x11,0xd2,0xe1,0x60,0xff,0xf7,0x22,0xff, +0x20,0x61,0x23,0x68,0xe5,0x80,0x28,0x33,0x03,0xeb,0x46,0x16,0x66,0x61,0x00,0x20, +0x70,0xbd,0x04,0x20,0x70,0xbd,0x02,0x20,0x70,0xbd,0x01,0x20,0x70,0xbd,0x04,0x20, +0x70,0xbd,0x2d,0xe9,0xf0,0x47,0xff,0x26,0x05,0x46,0x34,0x46,0x04,0x20,0xdf,0xf8, +0xf8,0x80,0x4f,0xf6,0xff,0x77,0x6a,0xe0,0x28,0x68,0xff,0xf7,0x9a,0xfd,0x00,0x28, +0x69,0xd1,0x6b,0x69,0x1a,0x78,0x00,0x2a,0x6c,0xd0,0xe5,0x2a,0xd9,0x7a,0x59,0xd0, +0x01,0xf0,0x3f,0x01,0xb1,0xf1,0x0f,0x0c,0x18,0xbf,0x4f,0xf0,0x01,0x0c,0x1c,0xea, +0xd1,0x0c,0x4f,0xd1,0x0f,0x29,0x39,0xd1,0x50,0x06,0x05,0xd5,0xe9,0x88,0x5e,0x7b, +0x02,0xf0,0xbf,0x04,0x29,0x84,0x01,0xe0,0xa2,0x42,0x43,0xd1,0x5a,0x7b,0xb2,0x42, +0x40,0xd1,0x1a,0x78,0x0d,0x21,0x02,0xf0,0x3f,0x02,0x01,0x3a,0xd5,0xf8,0x1c,0xe0, +0x4a,0x43,0x4f,0xf0,0x01,0x0c,0x00,0x21,0x11,0xf8,0x08,0x90,0x03,0xeb,0x09,0x00, +0x90,0xf8,0x01,0xa0,0x13,0xf8,0x09,0x00,0x40,0xea,0x0a,0x20,0xbc,0xf1,0x00,0x0f, +0x06,0xd0,0xfe,0x2a,0x26,0xd8,0x2e,0xf8,0x12,0x00,0x84,0x46,0x01,0x32,0x01,0xe0, +0xb8,0x42,0x1f,0xd1,0x01,0x31,0x0d,0x29,0xe6,0xd1,0x1b,0x78,0x59,0x06,0x26,0xd5, +0xfe,0x2a,0x17,0xd8,0x00,0x23,0x2e,0xf8,0x12,0x30,0x20,0xe0,0x6c,0xb9,0x01,0x46, +0x02,0x46,0x5c,0x5c,0x01,0x31,0x04,0xeb,0xc2,0x14,0x04,0xeb,0x52,0x02,0x0b,0x29, +0x02,0xf0,0xff,0x02,0xf5,0xd1,0x96,0x42,0x0f,0xd0,0x4f,0xf0,0xff,0x31,0x29,0x84, +0xbd,0xe8,0xf0,0x87,0xff,0x24,0x28,0x46,0xff,0xf7,0x51,0xff,0x18,0xb9,0x29,0x69, +0x00,0x29,0x91,0xd1,0x08,0xb1,0x00,0x23,0x2b,0x61,0xbd,0xe8,0xf0,0x87,0x01,0x3c, +0xe4,0xb2,0xf0,0xe7,0x04,0x20,0xf6,0xe7,0xc0,0x6a,0x00,0x20,0x2d,0xe9,0xf7,0x4f, +0x0b,0x78,0x04,0x46,0xa3,0xf1,0x2f,0x0c,0xdc,0xf1,0x00,0x02,0x42,0xeb,0x0c,0x02, +0x5c,0x2b,0x14,0xbf,0x13,0x46,0x42,0xf0,0x01,0x03,0x8a,0x46,0x1b,0xb1,0x01,0xf1, +0x01,0x0a,0x00,0x23,0x01,0xe0,0x03,0x68,0xdb,0x68,0xa3,0x60,0x9a,0xf8,0x00,0x30, +0x1f,0x2b,0x06,0xd8,0x20,0x46,0x00,0x21,0xff,0xf7,0xdc,0xfe,0x00,0x23,0x63,0x61, +0xd5,0xe1,0xd4,0xf8,0x1c,0x80,0x00,0x23,0x47,0x46,0x46,0x46,0x1a,0xf8,0x03,0x00, +0x03,0xf1,0x01,0x09,0x1f,0x28,0x8c,0xbf,0x00,0x22,0x01,0x22,0x2f,0x28,0x08,0xbf, +0x42,0xf0,0x01,0x02,0xba,0xb9,0x5c,0x28,0x15,0xd0,0xb9,0xf5,0x80,0x7f,0x00,0xf0, +0xbb,0x81,0x01,0x21,0x01,0xf0,0xb8,0xff,0x00,0x28,0x00,0xf0,0xb5,0x81,0x7f,0x28, +0x00,0xf2,0xb7,0x81,0xa5,0x4b,0x13,0xf8,0x01,0x2b,0x00,0x2a,0x00,0xf0,0xb1,0x81, +0x82,0x42,0xf8,0xd1,0xa8,0xe1,0x1f,0x28,0x94,0xbf,0x04,0x25,0x00,0x25,0x01,0x2b, +0x1e,0x46,0xca,0x44,0x0a,0xd0,0x02,0x2b,0x18,0xbf,0x1e,0x46,0x03,0xd1,0xb8,0xf8, +0x02,0x20,0x2e,0x2a,0x02,0xd0,0x08,0xeb,0x43,0x03,0x21,0xe0,0xb8,0xf8,0x00,0x20, +0x2e,0x2a,0xf8,0xd1,0x00,0x21,0x28,0xf8,0x13,0x10,0x00,0x22,0xa1,0x69,0x9a,0x42, +0x2c,0xbf,0x20,0x20,0x2e,0x20,0x88,0x54,0x01,0x32,0x0b,0x2a,0xf6,0xd1,0xa3,0x69, +0x45,0xf0,0x20,0x05,0xbf,0xe0,0x33,0xf8,0x02,0x2d,0xb2,0xf1,0x20,0x01,0x18,0xbf, +0x01,0x21,0x2e,0x2a,0x0c,0xbf,0x00,0x22,0x01,0xf0,0x01,0x02,0x1a,0xb9,0x01,0x3e, +0x00,0x2e,0xf0,0xd1,0x70,0xe1,0x00,0x22,0xa0,0x69,0x28,0xf8,0x16,0x20,0x08,0xeb, +0x46,0x01,0x00,0x23,0x20,0x22,0xc2,0x54,0x01,0x33,0x0b,0x2b,0xfb,0xd1,0x4f,0xf0, +0x00,0x09,0x01,0xe0,0x09,0xf1,0x01,0x09,0x37,0xf8,0x02,0x2b,0xa2,0xf1,0x20,0x0e, +0xde,0xf1,0x00,0x03,0x43,0xeb,0x0e,0x03,0x2e,0x2a,0x14,0xbf,0x1a,0x46,0x43,0xf0, +0x01,0x02,0x00,0x2a,0xee,0xd1,0xb9,0xf1,0x00,0x0f,0x01,0xd0,0x45,0xf0,0x03,0x05, +0x0b,0x46,0x33,0xf8,0x02,0x2d,0x2e,0x2a,0x00,0xf0,0x4f,0x81,0x01,0x3e,0x00,0xf0, +0x4c,0x81,0xf6,0xe7,0x38,0xf8,0x19,0x00,0x00,0x28,0x5b,0xd0,0x20,0x28,0x09,0xf1, +0x01,0x09,0x09,0xd0,0xb9,0xeb,0x06,0x02,0x18,0xbf,0x01,0x22,0x2e,0x28,0x14,0xbf, +0x00,0x21,0x02,0xf0,0x01,0x01,0x11,0xb1,0x45,0xf0,0x03,0x05,0xea,0xe7,0x9b,0x45, +0x34,0xbf,0x00,0x21,0x01,0x21,0xb1,0x45,0x08,0xbf,0x41,0xf0,0x01,0x01,0x81,0xb1, +0x0b,0x2b,0x02,0xd1,0x45,0xf0,0x03,0x05,0x3c,0xe0,0x1a,0xb1,0xb1,0x45,0x45,0xf0, +0x03,0x05,0x37,0xd8,0xbf,0x00,0xff,0xb2,0xb1,0x46,0x0b,0x23,0x4f,0xf0,0x08,0x0b, +0xd0,0xe7,0x7f,0x28,0x0b,0xd9,0x01,0x93,0x01,0xf0,0x0e,0xff,0x01,0x9b,0x18,0xb1, +0x53,0x49,0x08,0x18,0x10,0xf8,0x73,0x0c,0x45,0xf0,0x02,0x05,0x78,0xb1,0x51,0x4a, +0x12,0xf8,0x01,0x1b,0x11,0xb1,0x81,0x42,0xfa,0xd1,0x08,0xe0,0xa0,0xf1,0x41,0x02, +0x92,0xb2,0x19,0x2a,0x98,0xbf,0x47,0xf0,0x02,0x07,0x0d,0xd9,0x03,0xe0,0x45,0xf0, +0x03,0x05,0x5f,0x20,0x08,0xe0,0xa0,0xf1,0x61,0x02,0x92,0xb2,0x19,0x2a,0x03,0xd8, +0x20,0x38,0x47,0xf0,0x01,0x07,0x80,0xb2,0xa2,0x69,0x02,0xf8,0x0b,0x00,0x0b,0xf1, +0x01,0x0b,0x9f,0xe7,0xa2,0x69,0x11,0x78,0xe5,0x29,0x01,0xd1,0x05,0x21,0x11,0x70, +0x08,0x2b,0x01,0xd1,0xbf,0x00,0xff,0xb2,0x07,0xf0,0x0c,0x03,0x0c,0x2b,0x03,0xd0, +0x07,0xf0,0x03,0x02,0x03,0x2a,0x01,0xd1,0x45,0xf0,0x02,0x05,0xa8,0x07,0x09,0xd4, +0x07,0xf0,0x03,0x07,0x01,0x2f,0x08,0xbf,0x45,0xf0,0x10,0x05,0x04,0x2b,0x08,0xbf, +0x45,0xf0,0x08,0x05,0xa3,0x69,0xdd,0x72,0x20,0x46,0x00,0x21,0xff,0xf7,0xc2,0xfd, +0x00,0x28,0x00,0xf0,0xd4,0x80,0x8f,0xe0,0x20,0x68,0x21,0x69,0xff,0xf7,0xe1,0xfb, +0x00,0x28,0x40,0xf0,0x89,0x80,0x67,0x69,0x97,0xf8,0x00,0x80,0xb8,0xf1,0x00,0x0f, +0x00,0xf0,0x81,0x80,0xb8,0xf1,0xe5,0x0f,0xfb,0x7a,0x74,0xd0,0x03,0xf0,0x3f,0x03, +0xb3,0xf1,0x0f,0x02,0x18,0xbf,0x01,0x22,0x12,0xea,0xd3,0x02,0x6b,0xd1,0x0f,0x2b, +0x51,0xd1,0xd4,0xf8,0x1c,0xb0,0xbb,0xf1,0x00,0x0f,0x65,0xd0,0x18,0xf0,0x40,0x0f, +0x05,0xd0,0xe2,0x88,0x7e,0x7b,0x08,0xf0,0xbf,0x08,0x22,0x84,0x01,0xe0,0xa8,0x45, +0x59,0xd1,0x7b,0x7b,0xb3,0x42,0x56,0xd1,0x3d,0x78,0x0d,0x23,0x05,0xf0,0xbf,0x05, +0x01,0x3d,0x5d,0x43,0x4f,0xf0,0x01,0x09,0x00,0x23,0x0d,0x49,0x5a,0x5c,0xb9,0x18, +0x48,0x78,0xba,0x5c,0x42,0xea,0x00,0x20,0xb9,0xf1,0x00,0x0f,0x14,0xd0,0x01,0x93, +0x01,0xf0,0x90,0xfe,0xfe,0x2d,0x81,0x46,0x3d,0xd8,0x3b,0xf8,0x15,0x00,0x01,0xf0, +0x89,0xfe,0x81,0x45,0x01,0x9b,0x36,0xd1,0x01,0x35,0x09,0xe0,0x9f,0x76,0x00,0x20, +0xc0,0x6a,0x00,0x20,0xa8,0x76,0x00,0x20,0x4f,0xf6,0xff,0x72,0x90,0x42,0x2a,0xd1, +0x01,0x33,0x0d,0x2b,0xd9,0xd1,0x3b,0x78,0xc3,0xf3,0x80,0x13,0xb9,0xf1,0x00,0x0f, +0x0c,0xbf,0x00,0x23,0x03,0xf0,0x01,0x03,0x00,0x2b,0x5b,0xd0,0x3b,0xf8,0x15,0x30, +0x00,0x2b,0x57,0xd0,0x17,0xe0,0x00,0x2d,0x58,0xd1,0x02,0x46,0x03,0x46,0xb9,0x5c, +0x01,0x32,0x01,0xeb,0xc3,0x11,0x01,0xeb,0x53,0x03,0x0b,0x2a,0x03,0xf0,0xff,0x03, +0xf5,0xd1,0x9e,0x42,0x4a,0xd1,0x0f,0xe0,0x0b,0x2b,0x0d,0xd0,0xfd,0x5c,0xd1,0x5c, +0x01,0x33,0x8d,0x42,0xf8,0xd0,0xff,0x25,0x20,0x46,0xff,0xf7,0x78,0xfd,0x00,0x28, +0x3f,0xf4,0x72,0xaf,0x00,0xe0,0x04,0x20,0xa3,0x69,0xdb,0x7a,0x90,0xb1,0x04,0x28, +0x25,0xd1,0x13,0xf0,0x20,0x0f,0x03,0xf0,0x04,0x03,0x06,0xd0,0x00,0x20,0xa0,0x60, +0x60,0x61,0x00,0x2b,0x3f,0xf4,0x45,0xae,0x19,0xe0,0x00,0x2b,0x14,0xbf,0x04,0x20, +0x05,0x20,0x14,0xe0,0x59,0x07,0x12,0xd4,0x63,0x69,0xda,0x7a,0xd2,0x06,0x0d,0xd5, +0x59,0x7d,0x1a,0x7d,0x42,0xea,0x01,0x22,0xd9,0x7e,0x9b,0x7e,0x43,0xea,0x01,0x23, +0x43,0xea,0x02,0x43,0xa3,0x60,0x2c,0xe6,0x06,0x20,0x00,0xe0,0x05,0x20,0xbd,0xe8, +0xfe,0x8f,0x26,0xf8,0x02,0x0b,0x4b,0x46,0x28,0xe6,0x4f,0xf0,0x00,0x0b,0x08,0x23, +0x5f,0x46,0xaf,0xe6,0x08,0xf1,0xff,0x35,0xed,0xb2,0xbd,0xe7,0x4f,0xf0,0xff,0x33, +0xa2,0x69,0x23,0x84,0xd3,0x7a,0x13,0xf0,0x01,0x03,0xaf,0xd0,0xb3,0xe7,0xff,0x26, +0x35,0x46,0x29,0xe7,0x37,0xb5,0x00,0x24,0x0d,0x5d,0x05,0x55,0x01,0x34,0x0b,0x2c, +0xfa,0xd1,0x05,0x2b,0x0d,0xd9,0x00,0xe0,0x0a,0x46,0x11,0x46,0x31,0xf8,0x02,0x4b, +0x52,0x88,0x04,0xeb,0xc3,0x34,0xa4,0xb2,0x04,0xeb,0x53,0x03,0x9b,0xb2,0x00,0x2a, +0xf2,0xd1,0x07,0x22,0x03,0xf0,0x0f,0x04,0x04,0xf1,0x30,0x01,0x39,0x29,0x88,0xbf, +0x04,0xf1,0x37,0x01,0x0d,0xf8,0x02,0x10,0x01,0x3a,0x1b,0x09,0xf2,0xd1,0x02,0xac, +0xa1,0x18,0x7e,0x24,0x01,0xf8,0x08,0x4c,0x93,0x42,0x04,0xd0,0xc1,0x5c,0x20,0x29, +0x01,0xd0,0x01,0x33,0xf8,0xe7,0x20,0x21,0x07,0x2a,0x9f,0xbf,0x02,0xac,0xa1,0x18, +0x11,0xf8,0x08,0x1c,0x01,0x32,0xc1,0x54,0x01,0x33,0x07,0x2b,0xf3,0xd9,0x3e,0xbd, +0x48,0xb9,0x06,0x4a,0x53,0x68,0x03,0xb1,0x18,0x70,0x09,0xb1,0x00,0x23,0x0b,0x70, +0x51,0x60,0x00,0x20,0x70,0x47,0x0b,0x20,0x70,0x47,0x00,0xbf,0xcc,0x7f,0x00,0x20, +0x30,0xb5,0x00,0x23,0xad,0xf5,0x0f,0x7d,0x03,0x60,0x01,0x91,0x04,0x46,0x82,0xa9, +0x01,0xa8,0x15,0x46,0xff,0xf7,0x10,0xfb,0x8b,0xab,0x88,0x93,0x02,0xab,0x89,0x93, +0x18,0xb9,0x82,0xa8,0x01,0x99,0xff,0xf7,0x89,0xfd,0x87,0x9b,0x30,0xb9,0x23,0xb1, +0xda,0x7a,0xd2,0x06,0x05,0xd5,0x04,0x20,0x00,0xe0,0x06,0x20,0x0d,0xf5,0x0f,0x7d, +0x30,0xbd,0x05,0xf0,0x01,0x05,0xa5,0x71,0x1a,0x7d,0x59,0x7d,0xdd,0x7e,0x42,0xea, +0x01,0x21,0x9a,0x7e,0x42,0xea,0x05,0x22,0x42,0xea,0x01,0x42,0x22,0x61,0x9a,0x7f, +0xd9,0x7f,0x12,0x04,0x42,0xea,0x01,0x62,0x19,0x7f,0x5b,0x7f,0x0a,0x43,0x42,0xea, +0x03,0x23,0xe3,0x60,0x82,0x9b,0xa0,0x60,0x23,0x60,0xdb,0x88,0xa0,0x61,0xa3,0x80, +0xdc,0xe7,0x2d,0xe9,0xf8,0x4f,0x98,0x46,0x00,0x23,0x04,0x46,0x89,0x46,0xc8,0xf8, +0x00,0x30,0x81,0x88,0x00,0x68,0x17,0x46,0xff,0xf7,0x60,0xfa,0x05,0x46,0x00,0x28, +0x78,0xd1,0xa3,0x79,0x1a,0x06,0x72,0xd4,0xd8,0x07,0x72,0xd5,0xe6,0x68,0xa3,0x68, +0xf6,0x1a,0xb7,0x42,0x38,0xbf,0x3e,0x46,0x66,0xe0,0xa3,0x68,0xda,0x05,0x39,0xd1, +0x20,0x68,0x90,0xf8,0x02,0xa0,0x0a,0xf1,0xff,0x3a,0x0a,0xea,0x53,0x2a,0x5f,0xfa, +0x8a,0xfa,0xba,0xf1,0x00,0x0f,0x0a,0xd1,0x0b,0xb9,0x20,0x69,0x02,0xe0,0x61,0x69, +0xff,0xf7,0xc3,0xfb,0x01,0x28,0x09,0xd9,0x41,0x1c,0x29,0xd0,0x60,0x61,0xd4,0xf8, +0x00,0xb0,0x61,0x69,0x58,0x46,0xff,0xf7,0xad,0xfb,0x20,0xb9,0xa3,0x79,0x63,0xf0, +0x7f,0x03,0xa3,0x71,0x43,0xe0,0x00,0xeb,0x0a,0x02,0x77,0x0a,0x08,0xbf,0xa2,0x61, +0x10,0xd0,0x9b,0xf8,0x02,0x30,0x07,0xeb,0x0a,0x01,0x99,0x42,0x88,0xbf,0xca,0xeb, +0x03,0x07,0x9b,0xf8,0x01,0x00,0xfb,0xb2,0x49,0x46,0x00,0xf0,0x47,0xfc,0x38,0xb9, +0x7f,0x02,0x1f,0xe0,0x20,0x68,0xa1,0x69,0xa7,0x68,0xff,0xf7,0x22,0xfa,0x28,0xb1, +0xa3,0x79,0x01,0x25,0x63,0xf0,0x7f,0x03,0xa3,0x71,0x23,0xe0,0xa3,0x68,0xff,0x05, +0xdb,0x05,0xff,0x0d,0xdb,0x0d,0x22,0x68,0xc7,0xf5,0x00,0x77,0x28,0x33,0xbe,0x42, +0x38,0xbf,0x37,0x46,0xd3,0x18,0x03,0xe0,0x1a,0x5c,0x09,0xf8,0x00,0x20,0x01,0x30, +0xb8,0x42,0xf9,0xd1,0xa3,0x68,0xb9,0x44,0xdb,0x19,0xa3,0x60,0xd8,0xf8,0x00,0x30, +0xf6,0x1b,0xdb,0x19,0xc8,0xf8,0x00,0x30,0x00,0x2e,0x96,0xd1,0x02,0xe0,0x02,0x25, +0x00,0xe0,0x07,0x25,0x28,0x46,0xbd,0xe8,0xf8,0x8f,0x10,0xb5,0x81,0x88,0x04,0x46, +0x00,0x68,0xff,0xf7,0xdb,0xf9,0x00,0xb9,0x20,0x60,0x10,0xbd,0x10,0xb9,0x02,0x4b, +0x18,0x70,0x70,0x47,0x0b,0x20,0x70,0x47,0xcc,0x7f,0x00,0x20,0x00,0xb5,0xad,0xf5, +0x0f,0x7d,0x01,0x90,0x82,0xa9,0x01,0xa8,0xff,0xf7,0x36,0xfa,0xf0,0xb9,0x8b,0xab, +0x88,0x93,0x82,0xa8,0x02,0xab,0x01,0x99,0x89,0x93,0xff,0xf7,0xaf,0xfc,0x90,0xb9, +0x87,0x9b,0x84,0x9a,0x63,0xb1,0xda,0x7a,0xd1,0x06,0x12,0xd5,0x59,0x7d,0x1a,0x7d, +0x42,0xea,0x01,0x22,0xd9,0x7e,0x9b,0x7e,0x43,0xea,0x01,0x23,0x43,0xea,0x02,0x42, +0x82,0x9b,0xda,0x60,0x02,0xe0,0x04,0x28,0x08,0xbf,0x05,0x20,0x0d,0xf5,0x0f,0x7d, +0x00,0xbd,0x05,0x20,0xfa,0xe7,0x2d,0xe9,0xf0,0x43,0xad,0xf5,0x17,0x7d,0x01,0xaf, +0x00,0x23,0x82,0xae,0x38,0x60,0x88,0x46,0x03,0x70,0x31,0x46,0x38,0x46,0xff,0xf7, +0x03,0xfa,0x05,0x46,0x00,0x28,0x40,0xf0,0x8e,0x80,0x93,0xab,0x88,0x93,0x02,0xab, +0x89,0x93,0x82,0x9b,0x44,0x46,0xdb,0x68,0x84,0x93,0x5f,0xe0,0x30,0x46,0x01,0x21, +0xff,0xf7,0x70,0xfb,0x00,0x28,0x61,0xd1,0x30,0x46,0xff,0xf7,0xea,0xfb,0x01,0x46, +0x00,0x28,0x59,0xd1,0x87,0x9b,0x58,0x7d,0x1a,0x7d,0x42,0xea,0x00,0x22,0xd8,0x7e, +0x9b,0x7e,0x43,0xea,0x00,0x23,0x43,0xea,0x02,0x43,0x30,0x46,0x84,0x93,0xff,0xf7, +0x59,0xfb,0x00,0x28,0x4a,0xd1,0x30,0x46,0xff,0xf7,0xd3,0xfb,0x88,0xb9,0x87,0x9b, +0x59,0x7d,0x1a,0x7d,0x42,0xea,0x01,0x22,0xd9,0x7e,0x9b,0x7e,0x43,0xea,0x01,0x23, +0x43,0xea,0x02,0x43,0x99,0x45,0x09,0xd0,0x30,0x46,0xff,0xf7,0x88,0xfb,0x00,0x28, +0xe9,0xd0,0x04,0x28,0x14,0xbf,0x05,0x46,0x02,0x25,0x32,0xe0,0x3b,0x68,0x30,0x46, +0x8b,0xa9,0x91,0x93,0x92,0x94,0xff,0xf7,0xcb,0xf8,0x3a,0x68,0x13,0x78,0x13,0xb9, +0x8b,0xab,0x03,0xf1,0x09,0x02,0x00,0x23,0x00,0xe0,0x01,0x33,0xd1,0x5c,0x00,0x29, +0xfb,0xd1,0xd9,0x1c,0x8c,0x42,0x18,0x46,0x1a,0xd3,0x21,0x46,0x07,0xe0,0x01,0x3b, +0x12,0xf8,0x03,0x90,0xd7,0xf8,0x00,0xc0,0x01,0x39,0x0c,0xf8,0x01,0x90,0x00,0x2b, +0xf5,0xd1,0xc3,0x43,0xe4,0x18,0x3b,0x68,0x2f,0x22,0x1a,0x55,0xdd,0xf8,0x10,0x92, +0xb9,0xf1,0x00,0x0f,0x9a,0xd1,0x04,0xe0,0x05,0x46,0x02,0xe0,0x05,0x46,0x00,0xe0, +0x11,0x25,0x01,0xa9,0x0b,0x68,0xa5,0xb9,0x0d,0x4a,0x12,0x78,0x30,0x32,0x1a,0x70, +0x3a,0x22,0x5a,0x70,0x9a,0x1c,0x44,0x45,0x03,0xd1,0x2f,0x22,0x9a,0x70,0x03,0x33, +0x07,0xe0,0x0b,0x68,0x1b,0x5d,0x01,0x34,0x02,0xf8,0x01,0x3b,0x44,0x45,0x13,0x46, +0xf7,0xd3,0x00,0x22,0x1a,0x70,0x28,0x46,0x0d,0xf5,0x17,0x7d,0xbd,0xe8,0xf0,0x83, +0xcc,0x7f,0x00,0x20,0xf8,0xb5,0x04,0x46,0x0d,0x46,0x81,0x88,0x00,0x68,0xff,0xf7, +0xf5,0xf8,0x06,0x46,0x00,0x28,0x58,0xd1,0x94,0xf9,0x06,0x30,0x00,0x2b,0x53,0xdb, +0xe3,0x68,0x01,0x46,0x9d,0x42,0x28,0xbf,0x1d,0x46,0xa3,0x68,0xa0,0x60,0x00,0x2d, +0x42,0xd0,0x22,0x68,0x97,0x78,0x7f,0x02,0x6b,0xb1,0x01,0x3b,0x69,0x1e,0xb1,0xfb, +0xf7,0xf1,0xb3,0xfb,0xf7,0xf2,0x91,0x42,0x05,0xd3,0x7a,0x42,0x13,0x40,0xa3,0x60, +0xed,0x1a,0x61,0x69,0x01,0xe0,0x21,0x69,0x61,0x61,0x00,0x29,0x2c,0xd0,0x16,0xe0, +0x20,0x68,0xff,0xf7,0x52,0xfa,0x01,0x46,0x01,0x30,0x05,0xd1,0xa3,0x79,0x01,0x26, +0x63,0xf0,0x7f,0x03,0xa3,0x71,0x28,0xe0,0x01,0x29,0x14,0xd9,0x23,0x68,0x1b,0x69, +0x99,0x42,0x10,0xd2,0xa3,0x68,0x61,0x61,0xdb,0x19,0xa3,0x60,0xed,0x1b,0xbd,0x42, +0xe6,0xd8,0xa3,0x68,0x5b,0x19,0xa3,0x60,0xeb,0x05,0xda,0x0d,0x5b,0xb1,0x20,0x68, +0xff,0xf7,0x28,0xfa,0x20,0xb9,0xa3,0x79,0x63,0xf0,0x7f,0x03,0xa3,0x71,0x0b,0xe0, +0x00,0xeb,0x55,0x21,0x00,0xe0,0x11,0x46,0xa3,0x68,0xdb,0x05,0x05,0xd0,0xa3,0x69, +0x99,0x42,0x18,0xbf,0xa1,0x61,0x00,0xe0,0x02,0x26,0x30,0x46,0xf8,0xbd,0x10,0xb5, +0x04,0x46,0xad,0xf5,0x06,0x7d,0x01,0x91,0x01,0xa8,0x21,0x46,0xff,0xf7,0xfc,0xf8, +0x20,0xbb,0x83,0xab,0xa3,0x61,0x03,0xab,0xe3,0x61,0x20,0x46,0x01,0x99,0xff,0xf7, +0x75,0xfb,0xb0,0xb9,0x63,0x69,0x6b,0xb1,0xda,0x7a,0xd2,0x06,0x15,0xd5,0x59,0x7d, +0x1a,0x7d,0x42,0xea,0x01,0x22,0xd9,0x7e,0x9b,0x7e,0x43,0xea,0x01,0x23,0x43,0xea, +0x02,0x43,0xa3,0x60,0x23,0x68,0x20,0x46,0xdb,0x88,0x00,0x21,0xa3,0x80,0xff,0xf7, +0x59,0xfa,0x04,0x28,0x08,0xbf,0x05,0x20,0x00,0xe0,0x05,0x20,0x0d,0xf5,0x06,0x7d, +0x10,0xbd,0x70,0xb5,0x04,0x46,0xad,0xf5,0x04,0x7d,0x0e,0x46,0x81,0x88,0x00,0x68, +0xff,0xf7,0x5c,0xf8,0x05,0x46,0xf0,0xb9,0x26,0xb9,0x20,0x46,0x29,0x46,0xff,0xf7, +0x41,0xfa,0x17,0xe0,0x81,0xab,0xa3,0x61,0x01,0xab,0xe3,0x61,0x20,0x46,0xff,0xf7, +0xb8,0xfa,0x04,0x28,0x08,0xbf,0x25,0x61,0x00,0xd0,0x58,0xb9,0x20,0x46,0x31,0x46, +0xfe,0xf7,0xc6,0xff,0x20,0x46,0xff,0xf7,0x72,0xfa,0x04,0x28,0x02,0xd1,0x00,0x23, +0x23,0x61,0x00,0xe0,0x05,0x46,0x28,0x46,0x0d,0xf5,0x04,0x7d,0x70,0xbd,0x00,0xbf, +0x12,0x4b,0x4f,0xf4,0x00,0x51,0x59,0x83,0x4f,0xf4,0x00,0x62,0x4f,0xf4,0x80,0x41, +0x1a,0x83,0x59,0x83,0x09,0x22,0x0e,0xe0,0x4f,0xf4,0x00,0x61,0x59,0x83,0x10,0xf0, +0x80,0x0f,0x4f,0xf4,0x80,0x61,0x14,0xbf,0x19,0x83,0x59,0x83,0x40,0x00,0x4f,0xf4, +0x00,0x61,0xc0,0xb2,0x19,0x83,0x01,0x3a,0x04,0x49,0xed,0xd1,0x4f,0xf4,0x80,0x42, +0x4f,0xf4,0x00,0x53,0x0a,0x83,0x0b,0x83,0x70,0x47,0x00,0xbf,0x00,0x0c,0x02,0x40, +0x12,0x4b,0x4f,0xf4,0x00,0x61,0x19,0x83,0x4f,0xf4,0x00,0x52,0x4f,0xf4,0x80,0x41, +0x1a,0x83,0x59,0x83,0x09,0x22,0x0e,0xe0,0x10,0xf0,0x80,0x0f,0x4f,0xf4,0x80,0x61, +0x14,0xbf,0x19,0x83,0x59,0x83,0x40,0x00,0x4f,0xf4,0x00,0x61,0x59,0x83,0xc0,0xb2, +0x00,0xbf,0x19,0x83,0x00,0xbf,0x01,0x3a,0x04,0x49,0xed,0xd1,0x4f,0xf4,0x80,0x42, +0x4f,0xf4,0x00,0x53,0x0a,0x83,0x0b,0x83,0x70,0x47,0x00,0xbf,0x00,0x0c,0x02,0x40, +0xf0,0xb5,0x02,0x20,0x89,0xb0,0x01,0x21,0xfc,0xf7,0x28,0xf8,0x4f,0xf4,0x80,0x40, +0x01,0x21,0xfc,0xf7,0x47,0xf8,0x39,0x48,0x0d,0x21,0x05,0x22,0xfc,0xf7,0x0d,0xfa, +0x36,0x48,0x0e,0x21,0x05,0x22,0xfc,0xf7,0x08,0xfa,0x34,0x48,0x0f,0x21,0x05,0x22, +0xfc,0xf7,0x03,0xfa,0x32,0x4e,0x7d,0x24,0x4a,0xf6,0xaa,0x25,0x44,0xf6,0x20,0x60, +0x01,0xf0,0x8a,0xfc,0x01,0x3c,0x35,0x60,0xf8,0xd1,0x4f,0xf4,0x82,0x73,0xad,0xf8, +0x06,0x30,0x4f,0xf4,0x00,0x73,0xad,0xf8,0x0e,0x30,0x08,0x23,0xad,0xf8,0x10,0x30, +0x01,0xa9,0x07,0x23,0x27,0x48,0xad,0xf8,0x14,0x30,0xad,0xf8,0x04,0x40,0xad,0xf8, +0x08,0x40,0xad,0xf8,0x0a,0x40,0xad,0xf8,0x0c,0x40,0xad,0xf8,0x12,0x40,0xfc,0xf7, +0x25,0xfa,0x21,0x46,0x1f,0x48,0xfc,0xf7,0x19,0xfb,0x1c,0x4d,0x01,0x21,0x1d,0x48, +0xfc,0xf7,0xb7,0xfa,0x4f,0xf4,0x80,0x53,0x2b,0x83,0x26,0x46,0x01,0x27,0x8d,0xf8, +0x1e,0x40,0x8d,0xf8,0x1f,0x40,0x28,0x46,0x02,0x24,0x06,0xa9,0x06,0x93,0x8d,0xf8, +0x1c,0x70,0x8d,0xf8,0x1d,0x40,0xfc,0xf7,0x3f,0xf9,0x4f,0xf4,0x20,0x43,0x28,0x46, +0x06,0xa9,0x06,0x93,0x8d,0xf8,0x1d,0x40,0x8d,0xf8,0x1c,0x40,0x8d,0xf8,0x1e,0x60, +0x8d,0xf8,0x1f,0x70,0xfc,0xf7,0x30,0xf9,0x4f,0xf4,0x80,0x43,0x28,0x46,0x06,0xa9, +0x06,0x93,0x8d,0xf8,0x1d,0x40,0x8d,0xf8,0x1c,0x40,0x8d,0xf8,0x1e,0x60,0x8d,0xf8, +0x1f,0x70,0xfc,0xf7,0x21,0xf9,0x09,0xb0,0xf0,0xbd,0x00,0xbf,0x00,0x04,0x02,0x40, +0x00,0x30,0x00,0x40,0x00,0x38,0x00,0x40,0x01,0x46,0x08,0xb5,0x06,0x48,0xfc,0xf7, +0xd3,0xfa,0x05,0x48,0x01,0x21,0xfc,0xf7,0x04,0xfb,0x00,0x28,0xf9,0xd0,0x02,0x48, +0xfc,0xf7,0xc7,0xfa,0xc0,0xb2,0x08,0xbd,0x00,0x38,0x00,0x40,0xff,0x20,0xeb,0xe7, +0x10,0xb5,0x06,0x4c,0x32,0x23,0x23,0x60,0xff,0xf7,0xf8,0xff,0xff,0xf7,0xf6,0xff, +0xff,0x28,0x02,0xd0,0x23,0x68,0x00,0x2b,0xf8,0xd1,0x10,0xbd,0xd8,0x7f,0x00,0x20, +0x02,0x4b,0x4f,0xf4,0x80,0x52,0x1a,0x83,0xe8,0xe7,0x00,0xbf,0x00,0x04,0x02,0x40, +0x02,0x06,0x38,0xb5,0x04,0x46,0x0d,0x46,0x07,0xd5,0x77,0x20,0x00,0x21,0xff,0xf7, +0xf7,0xff,0x01,0x28,0x32,0xd8,0x04,0xf0,0x7f,0x04,0x19,0x4b,0x4f,0xf4,0x80,0x52, +0x5a,0x83,0xff,0xf7,0xd5,0xff,0xff,0x28,0x27,0xd1,0x20,0x46,0xff,0xf7,0xbc,0xff, +0x28,0x0e,0xff,0xf7,0xb9,0xff,0xc5,0xf3,0x07,0x40,0xff,0xf7,0xb5,0xff,0xc5,0xf3, +0x07,0x20,0xff,0xf7,0xb1,0xff,0xe8,0xb2,0xff,0xf7,0xae,0xff,0x95,0x20,0x40,0x2c, +0x03,0xd0,0x48,0x2c,0x0c,0xbf,0x87,0x20,0x01,0x20,0xff,0xf7,0xa5,0xff,0x4c,0x2c, +0x01,0xd1,0xff,0xf7,0xb3,0xff,0x0a,0x24,0xff,0xf7,0xb0,0xff,0x03,0x06,0x05,0xd5, +0x01,0x3c,0xe4,0xb2,0x00,0x2c,0xf7,0xd1,0x38,0xbd,0xff,0x20,0x38,0xbd,0x00,0xbf, +0x00,0x04,0x02,0x40,0x70,0xb5,0x15,0x4e,0x0a,0x23,0x04,0x46,0x0d,0x46,0x73,0x60, +0xff,0xf7,0x9c,0xff,0xff,0x28,0x03,0xd1,0x70,0x68,0x00,0x28,0xf8,0xd1,0x70,0xbd, +0xfe,0x28,0x18,0xd1,0xff,0x20,0xff,0xf7,0x7f,0xff,0x20,0x70,0xff,0x20,0xff,0xf7, +0x7b,0xff,0x60,0x70,0xff,0x20,0xff,0xf7,0x77,0xff,0xa0,0x70,0xff,0x20,0xff,0xf7, +0x73,0xff,0xe0,0x70,0x04,0x34,0x04,0x3d,0xec,0xd1,0xff,0xf7,0x7f,0xff,0xff,0xf7, +0x7d,0xff,0x01,0x20,0x70,0xbd,0x00,0x20,0x70,0xbd,0x00,0xbf,0xd8,0x7f,0x00,0x20, +0x38,0xb5,0x04,0x46,0x0d,0x46,0xff,0xf7,0x73,0xff,0xff,0x28,0x22,0xd1,0x28,0x46, +0xff,0xf7,0x5a,0xff,0xfd,0x2d,0x1b,0xd0,0x00,0x25,0x60,0x5d,0xff,0xf7,0x54,0xff, +0x63,0x19,0x58,0x78,0x02,0x35,0xff,0xf7,0x4f,0xff,0xb5,0xf5,0x00,0x7f,0xf4,0xd1, +0xff,0x20,0xff,0xf7,0x49,0xff,0xff,0x20,0xff,0xf7,0x46,0xff,0xff,0xf7,0x56,0xff, +0x00,0xf0,0x1f,0x00,0xa0,0xf1,0x05,0x01,0x48,0x42,0x40,0xeb,0x01,0x00,0x38,0xbd, +0x01,0x20,0x38,0xbd,0x00,0x20,0x38,0xbd,0x02,0x4b,0x18,0x69,0x00,0xf4,0x00,0x70, +0x70,0x47,0x00,0xbf,0x00,0x0c,0x02,0x40,0x73,0xb5,0x00,0x28,0x40,0xf0,0x84,0x80, +0x47,0x4b,0x1a,0x78,0x90,0x07,0x7d,0xd4,0xff,0xf7,0xa2,0xfe,0x45,0x4b,0x0a,0x24, +0x1a,0x88,0x92,0xb2,0x42,0xf0,0x30,0x02,0x1a,0x80,0x01,0x3c,0xe4,0xb2,0xff,0xf7, +0x2d,0xff,0x00,0x2c,0xf9,0xd1,0x40,0x20,0x21,0x46,0xff,0xf7,0x41,0xff,0x01,0x28, +0x55,0xd1,0x3d,0x4d,0x64,0x23,0x48,0x20,0x4f,0xf4,0xd5,0x71,0x6b,0x60,0xff,0xf7, +0x37,0xff,0x01,0x28,0x2f,0xd1,0xff,0xf7,0x19,0xff,0x01,0xab,0xe0,0x54,0x01,0x34, +0x04,0x2c,0xf8,0xd1,0x9d,0xf8,0x06,0x30,0x01,0x2b,0x3f,0xd1,0x9d,0xf8,0x07,0x30, +0xaa,0x2b,0x3b,0xd1,0x30,0x4c,0x63,0x68,0x00,0x2b,0x4f,0xd0,0xe9,0x20,0x4f,0xf0, +0x80,0x41,0xff,0xf7,0x1d,0xff,0x00,0x28,0xf5,0xd1,0x47,0xe0,0x7a,0x20,0x00,0x21, +0xff,0xf7,0x16,0xff,0x50,0xbb,0x04,0x46,0xff,0xf7,0xf8,0xfe,0x01,0xab,0xe0,0x54, +0x01,0x34,0x04,0x2c,0xf8,0xd1,0x9d,0xf8,0x04,0x30,0x13,0xf0,0x40,0x0f,0x0c,0xbf, +0x04,0x24,0x0c,0x24,0x1b,0xe0,0xe9,0x20,0x21,0x46,0xff,0xf7,0x01,0xff,0x01,0x28, +0x8c,0xbf,0x01,0x24,0x02,0x24,0x8c,0xbf,0x41,0x26,0xe9,0x26,0x6b,0x68,0x00,0x2b, +0x29,0xd0,0x30,0x46,0x00,0x21,0xff,0xf7,0xf3,0xfe,0x00,0x28,0xf6,0xd1,0x22,0xe0, +0x50,0x20,0x4f,0xf4,0x00,0x71,0xff,0xf7,0xeb,0xfe,0x00,0xb1,0x00,0x24,0x12,0x4b, +0x1c,0x72,0xff,0xf7,0xdd,0xfe,0x64,0xb1,0x0d,0x4b,0x1a,0x78,0x02,0xf0,0xfe,0x02, +0x1a,0x70,0x0c,0x4b,0x1a,0x88,0x92,0xb2,0x22,0xf0,0x38,0x02,0x42,0xf0,0x08,0x02, +0x1a,0x80,0x07,0x4b,0x18,0x78,0x00,0xe0,0x01,0x20,0x7c,0xbd,0x06,0x4b,0x5b,0x68, +0x00,0x2b,0xe3,0xd0,0xb2,0xe7,0x04,0x4b,0x5b,0x68,0x00,0x2b,0xde,0xd0,0xd7,0xe7, +0xce,0x78,0x00,0x20,0x00,0x38,0x00,0x40,0xd8,0x7f,0x00,0x20,0x10,0xb9,0x02,0x4b, +0x18,0x78,0x70,0x47,0x01,0x20,0x70,0x47,0xce,0x78,0x00,0x20,0x38,0xb5,0x0e,0x4b, +0x04,0x46,0x1b,0x7a,0x15,0x46,0x1b,0x07,0x58,0xbf,0x49,0x02,0x52,0x20,0xff,0xf7, +0xaf,0xfe,0x68,0xb9,0x20,0x46,0x4f,0xf4,0x00,0x71,0xff,0xf7,0xeb,0xfe,0x18,0xb1, +0x01,0x3d,0x04,0xf5,0x00,0x74,0xf5,0xd1,0x4c,0x20,0x00,0x21,0xff,0xf7,0xa0,0xfe, +0xff,0xf7,0x96,0xfe,0x00,0x20,0x38,0xbd,0xd8,0x7f,0x00,0x20,0x00,0x30,0x18,0xbf, +0x01,0x20,0x00,0x2b,0x08,0xbf,0x40,0xf0,0x01,0x00,0x38,0xb5,0x0c,0x46,0x1d,0x46, +0x11,0x46,0x00,0x28,0x32,0xd1,0x1b,0x4b,0x1b,0x78,0xd8,0x07,0x30,0xd4,0x1a,0x4b, +0x1b,0x7a,0x1a,0x07,0x58,0xbf,0x49,0x02,0x01,0x2d,0x0d,0xd1,0x51,0x20,0xff,0xf7, +0x7f,0xfe,0xe8,0xb9,0x20,0x46,0x4f,0xf4,0x00,0x71,0xff,0xf7,0xbb,0xfe,0xd0,0xf1, +0x01,0x05,0x38,0xbf,0x00,0x25,0x13,0xe0,0x52,0x20,0xff,0xf7,0x71,0xfe,0x78,0xb9, +0x20,0x46,0x4f,0xf4,0x00,0x71,0xff,0xf7,0xad,0xfe,0x28,0xb1,0x01,0x3d,0xed,0xb2, +0x04,0xf5,0x00,0x74,0x00,0x2d,0xf3,0xd1,0x4c,0x20,0x00,0x21,0xff,0xf7,0x60,0xfe, +0xff,0xf7,0x56,0xfe,0x28,0x1c,0x18,0xbf,0x01,0x20,0x38,0xbd,0x04,0x20,0x38,0xbd, +0x03,0x20,0x38,0xbd,0xce,0x78,0x00,0x20,0xd8,0x7f,0x00,0x20,0x70,0xb5,0x12,0x4b, +0x16,0x46,0x1b,0x7a,0x0c,0x46,0x1a,0x07,0x58,0xbf,0x4c,0x02,0x13,0xf0,0x06,0x0f, +0x05,0x46,0x03,0xd0,0xd7,0x20,0x31,0x46,0xff,0xf7,0x42,0xfe,0x59,0x20,0x21,0x46, +0xff,0xf7,0x3e,0xfe,0x60,0xb9,0x28,0x46,0xfc,0x21,0xff,0xf7,0xa9,0xfe,0x18,0xb1, +0x01,0x3e,0x05,0xf5,0x00,0x75,0xf6,0xd1,0x00,0x20,0xfd,0x21,0xff,0xf7,0xa0,0xfe, +0xff,0xf7,0x26,0xfe,0x00,0x20,0x70,0xbd,0xd8,0x7f,0x00,0x20,0x00,0x30,0x18,0xbf, +0x01,0x20,0x00,0x2b,0x08,0xbf,0x40,0xf0,0x01,0x00,0x70,0xb5,0x0c,0x46,0x15,0x46, +0x1e,0x46,0x00,0x28,0x3f,0xd1,0x23,0x4b,0x1a,0x78,0xd2,0x07,0x3d,0xd4,0x1b,0x78, +0x58,0x07,0x3c,0xd4,0x20,0x4b,0x1b,0x7a,0x19,0x07,0x58,0xbf,0x6d,0x02,0x01,0x2e, +0x0d,0xd1,0x58,0x20,0x29,0x46,0xff,0xf7,0x0b,0xfe,0x30,0xbb,0xfe,0x21,0x20,0x46, +0xff,0xf7,0x76,0xfe,0xd0,0xf1,0x01,0x06,0x38,0xbf,0x00,0x26,0x1d,0xe0,0x13,0xf0, +0x06,0x0f,0x03,0xd0,0xd7,0x20,0x31,0x46,0xff,0xf7,0xfa,0xfd,0x59,0x20,0x29,0x46, +0xff,0xf7,0xf6,0xfd,0x88,0xb9,0x20,0x46,0xfc,0x21,0xff,0xf7,0x61,0xfe,0x28,0xb1, +0x01,0x3e,0xf6,0xb2,0x04,0xf5,0x00,0x74,0x00,0x2e,0xf4,0xd1,0x00,0x20,0xfd,0x21, +0xff,0xf7,0x56,0xfe,0x00,0x28,0x08,0xbf,0x01,0x26,0xff,0xf7,0xd9,0xfd,0x30,0x1c, +0x18,0xbf,0x01,0x20,0x70,0xbd,0x04,0x20,0x70,0xbd,0x03,0x20,0x70,0xbd,0x02,0x20, +0x70,0xbd,0x00,0xbf,0xce,0x78,0x00,0x20,0xd8,0x7f,0x00,0x20,0x70,0xb5,0x05,0x46, +0x86,0xb0,0x14,0x46,0x00,0x28,0x40,0xf0,0x27,0x81,0x05,0x29,0x3a,0xd1,0x13,0x78, +0x01,0x2b,0x31,0xd0,0x03,0xd3,0x02,0x2b,0x40,0xf0,0x1e,0x81,0x2f,0xe0,0x90,0x4b, +0x1b,0x78,0xdd,0x07,0x07,0xd4,0x8f,0x4b,0x4f,0xf4,0x80,0x52,0x5a,0x83,0xff,0xf7, +0x9f,0xfd,0xff,0xf7,0xad,0xfd,0x8c,0x48,0xfb,0xf7,0x36,0xff,0x8a,0x48,0x00,0x21, +0xfb,0xf7,0xff,0xff,0x4f,0xf4,0x80,0x40,0x00,0x21,0xfb,0xf7,0x4b,0xfd,0x4f,0xf4, +0x60,0x43,0x04,0x93,0x00,0x25,0x02,0x23,0x82,0x48,0x04,0xa9,0x8d,0xf8,0x17,0x30, +0x8d,0xf8,0x14,0x50,0x8d,0xf8,0x16,0x50,0xfb,0xf7,0x86,0xfe,0x7c,0x4b,0x1a,0x78, +0x42,0xf0,0x01,0x02,0x1a,0x70,0xf0,0xe0,0xff,0xf7,0xe2,0xfc,0xed,0xe0,0x01,0x23, +0x53,0x70,0xea,0xe0,0x76,0x4b,0x03,0x25,0x1b,0x78,0xd8,0x07,0x00,0xf1,0xe5,0x80, +0x0e,0x29,0x00,0xf2,0xdb,0x80,0xdf,0xe8,0x11,0xf0,0x0f,0x00,0x1a,0x00,0x56,0x00, +0x5a,0x00,0xd9,0x00,0xd9,0x00,0xd9,0x00,0xd9,0x00,0xd9,0x00,0xd9,0x00,0xa9,0x00, +0xad,0x00,0xaf,0x00,0xbb,0x00,0xc9,0x00,0x6a,0x4b,0x4f,0xf4,0x80,0x52,0x5a,0x83, +0xff,0xf7,0x56,0xfd,0xb0,0xf1,0xff,0x05,0x18,0xbf,0x01,0x25,0xc1,0xe0,0x49,0x20, +0x00,0x21,0xff,0xf7,0x65,0xfd,0x05,0x46,0x00,0x28,0x40,0xf0,0xb9,0x80,0x68,0x46, +0x10,0x21,0xff,0xf7,0x9f,0xfd,0x00,0x28,0x00,0xf0,0xb2,0x80,0x9d,0xf8,0x00,0x30, +0x9b,0x11,0x01,0x2b,0x9d,0xf8,0x08,0x30,0x07,0xd1,0x9d,0xf8,0x09,0x20,0x01,0x32, +0x02,0xeb,0x03,0x23,0x9b,0xb2,0x9b,0x02,0x1b,0xe0,0x9d,0xf8,0x07,0x20,0x9d,0xf8, +0x05,0x10,0x92,0x00,0x01,0x32,0x02,0xeb,0x93,0x13,0x9d,0xf8,0x06,0x20,0x01,0xf0, +0x0f,0x01,0x02,0xf0,0x03,0x02,0x03,0xeb,0x82,0x23,0x9d,0xf8,0x0a,0x20,0x01,0xeb, +0xd2,0x11,0x9d,0xf8,0x09,0x20,0x02,0xf0,0x03,0x02,0x01,0xeb,0x42,0x02,0x07,0x3a, +0x93,0x40,0x23,0x60,0x85,0xe0,0x4f,0xf4,0x00,0x73,0x13,0x80,0x6c,0xe0,0x47,0x4d, +0x29,0x7a,0x11,0xf0,0x04,0x01,0x1b,0xd0,0xcd,0x20,0x00,0x21,0xff,0xf7,0x20,0xfd, +0x00,0x28,0x75,0xd1,0xff,0xf7,0x02,0xfd,0x68,0x46,0x10,0x21,0xff,0xf7,0x5a,0xfd, +0x00,0x28,0x6d,0xd0,0x30,0x25,0x01,0x3d,0xed,0xb2,0xff,0xf7,0xf7,0xfc,0x00,0x2d, +0xf9,0xd1,0x9d,0xf8,0x0a,0x30,0x10,0x22,0x1b,0x11,0x12,0xfa,0x03,0xf3,0xd8,0xe7, +0x49,0x20,0xff,0xf7,0x05,0xfd,0x06,0x46,0x00,0x28,0x59,0xd1,0x68,0x46,0x10,0x21, +0xff,0xf7,0x40,0xfd,0x00,0x28,0x53,0xd0,0x2d,0x7a,0x9d,0xf8,0x0a,0x20,0x15,0xf0, +0x02,0x05,0x9d,0xf8,0x0b,0x30,0x0d,0xd0,0x9d,0xf8,0x0d,0x10,0x02,0xf0,0x3f,0x02, +0xdb,0x09,0x03,0xeb,0x42,0x03,0x89,0x11,0x01,0x33,0x01,0x39,0x8b,0x40,0x35,0x46, +0x23,0x60,0x3e,0xe0,0xc2,0xf3,0x84,0x02,0x51,0x1c,0x03,0xf0,0x03,0x02,0x5b,0x09, +0x03,0xeb,0xc2,0x02,0x01,0x32,0x4a,0x43,0x22,0x60,0x32,0xe0,0x1f,0x4b,0x1b,0x7a, +0x13,0x70,0x19,0xe0,0x49,0x20,0x00,0xe0,0x4a,0x20,0x00,0x21,0xff,0xf7,0xd0,0xfc, +0x05,0x46,0x28,0xbb,0x20,0x46,0x10,0x21,0xff,0xf7,0x0c,0xfd,0x08,0xbb,0x1f,0xe0, +0x7a,0x20,0x00,0x21,0xff,0xf7,0xc4,0xfc,0xd0,0xb9,0x05,0x46,0xff,0xf7,0xa6,0xfc, +0x60,0x55,0x01,0x35,0x04,0x2d,0xf9,0xd1,0x00,0x25,0x12,0xe0,0xcd,0x20,0x00,0x21, +0xff,0xf7,0xb6,0xfc,0x60,0xb9,0xff,0xf7,0x99,0xfc,0x40,0x21,0x20,0x46,0xff,0xf7, +0xf1,0xfc,0xd0,0xf1,0x01,0x05,0x38,0xbf,0x00,0x25,0x02,0xe0,0x04,0x25,0x00,0xe0, +0x01,0x25,0xff,0xf7,0x9d,0xfc,0x00,0xe0,0x04,0x25,0x28,0x46,0x06,0xb0,0x70,0xbd, +0xce,0x78,0x00,0x20,0x00,0x04,0x02,0x40,0x00,0x38,0x00,0x40,0xd8,0x7f,0x00,0x20, +0x0e,0x4b,0x5a,0x68,0xd2,0xb2,0x12,0xb1,0x01,0x3a,0xd2,0xb2,0x5a,0x60,0x1b,0x68, +0xdb,0xb2,0x1b,0xb1,0x01,0x3b,0x09,0x4a,0xdb,0xb2,0x13,0x60,0x08,0x4b,0x07,0x4a, +0x1b,0x69,0xd1,0x68,0x03,0xf4,0x00,0x73,0x99,0x42,0xd3,0x60,0x01,0xbf,0x05,0x4b, +0x1a,0x78,0x02,0xf0,0xf9,0x02,0x1a,0x70,0x70,0x47,0x00,0xbf,0xd8,0x7f,0x00,0x20, +0x00,0x0c,0x02,0x40,0xce,0x78,0x00,0x20,0x10,0xb5,0x05,0x4c,0x00,0x20,0x04,0xf1, +0x10,0x01,0xff,0xf7,0xe5,0xf8,0x10,0xb9,0x64,0x23,0xc4,0xf8,0x38,0x32,0x10,0xbd, +0xd8,0x7f,0x00,0x20,0x04,0x4b,0xd3,0xf8,0x38,0x02,0xa0,0xf1,0x64,0x0c,0xdc,0xf1, +0x00,0x00,0x40,0xeb,0x0c,0x00,0x70,0x47,0xd8,0x7f,0x00,0x20,0x70,0x47,0x04,0x4b, +0xd3,0xf8,0x38,0x02,0xa0,0xf1,0x64,0x03,0x58,0x42,0x40,0xeb,0x03,0x00,0x70,0x47, +0xd8,0x7f,0x00,0x20,0x84,0xb0,0x01,0x90,0x00,0x23,0x1c,0xe0,0x8d,0xf8,0x0f,0x30, +0x05,0xe0,0x9d,0xf8,0x0f,0x20,0x01,0x32,0xd2,0xb2,0x8d,0xf8,0x0f,0x20,0x9d,0xf8, +0x0f,0x20,0xf9,0x2a,0xf5,0xd9,0x8d,0xf8,0x0f,0x30,0x05,0xe0,0x9d,0xf8,0x0f,0x20, +0x01,0x32,0xd2,0xb2,0x8d,0xf8,0x0f,0x20,0x9d,0xf8,0x0f,0x20,0x4a,0x2a,0xf5,0xd9, +0x01,0x9a,0x01,0x3a,0x01,0x92,0x01,0x9a,0x00,0x2a,0xdf,0xd1,0x04,0xb0,0x70,0x47, +0x37,0xb5,0x02,0x20,0x01,0x21,0x1c,0x4d,0xfb,0xf7,0xa0,0xfb,0x4f,0xf4,0x80,0x73, +0x00,0x24,0x00,0x93,0x28,0x46,0x02,0x23,0x69,0x46,0x8d,0xf8,0x04,0x30,0x8d,0xf8, +0x05,0x30,0x8d,0xf8,0x06,0x40,0x8d,0xf8,0x07,0x40,0xfb,0xf7,0xfd,0xfc,0x28,0x46, +0x08,0x21,0x03,0x22,0xfb,0xf7,0x79,0xfd,0x10,0x4b,0x11,0x49,0x5a,0x6c,0x11,0x48, +0x42,0xf4,0x00,0x32,0x5a,0x64,0xa3,0xf5,0x74,0x43,0x64,0x22,0xda,0x62,0x0e,0x4a, +0x09,0x68,0x12,0x68,0x4a,0x43,0x42,0xf2,0x10,0x71,0xb2,0xfb,0xf1,0xf2,0x01,0x3a, +0x92,0xb2,0x1a,0x85,0x60,0x22,0x1a,0x83,0x50,0x21,0x01,0x22,0x1a,0x84,0x01,0x80, +0x59,0x63,0x9c,0x82,0x1a,0x80,0x3e,0xbd,0x00,0x04,0x02,0x40,0x00,0x38,0x02,0x40, +0x7c,0x9f,0x00,0x20,0x14,0x82,0x00,0x20,0x78,0x9f,0x00,0x20,0x38,0xb5,0x04,0x46, +0x24,0x11,0x00,0xf0,0x0f,0x00,0x0d,0x46,0xff,0xf7,0xda,0xfa,0x44,0xf0,0x10,0x00, +0xff,0xf7,0xd6,0xfa,0x05,0xf0,0x0f,0x00,0x40,0xf0,0x60,0x00,0xff,0xf7,0xd0,0xfa, +0x2d,0x09,0x45,0xf0,0x70,0x00,0xbd,0xe8,0x38,0x40,0xff,0xf7,0xc9,0xba,0x2d,0xe9, +0xf0,0x41,0x48,0x4c,0x00,0x25,0x26,0x46,0x47,0x4b,0xea,0x08,0x4f,0xf0,0xd4,0x08, +0x08,0xfb,0x02,0x38,0x01,0x27,0x05,0xf0,0x07,0x03,0x9f,0x40,0xe9,0xb2,0x00,0x20, +0xff,0xf7,0xd4,0xff,0xaf,0x20,0xff,0xf7,0xb3,0xfa,0x4f,0xf4,0x00,0x60,0x20,0x83, +0x4f,0xf4,0x00,0x53,0x4f,0xf4,0x80,0x40,0x3c,0x4a,0x23,0x83,0xff,0xb2,0x60,0x83, +0x00,0x21,0x18,0xf8,0x01,0x30,0x08,0xeb,0x01,0x00,0x40,0x78,0x3b,0x40,0x18,0xbf, +0xf0,0x23,0x07,0x42,0x18,0xbf,0x0f,0x33,0x13,0xf0,0x80,0x0f,0x4f,0xf4,0x80,0x60, +0x14,0xbf,0x20,0x83,0x60,0x83,0x4f,0xf4,0x00,0x60,0x60,0x83,0x58,0x06,0x46,0xbf, +0x4f,0xf4,0x40,0x60,0x20,0x83,0xa2,0x61,0x00,0xbf,0x4f,0xf4,0x00,0x60,0x60,0x83, +0x98,0x06,0x46,0xbf,0x4f,0xf4,0x40,0x60,0x20,0x83,0xa2,0x61,0x00,0xbf,0x4f,0xf4, +0x00,0x60,0x70,0x83,0xd8,0x06,0x46,0xbf,0x4f,0xf4,0x40,0x60,0x20,0x83,0xa2,0x61, +0x00,0xbf,0x4f,0xf4,0x00,0x60,0x60,0x83,0x18,0x07,0x46,0xbf,0x4f,0xf4,0x40,0x60, +0x20,0x83,0xa2,0x61,0x00,0xbf,0x4f,0xf4,0x00,0x60,0x70,0x83,0x58,0x07,0x46,0xbf, +0x4f,0xf4,0x40,0x60,0x20,0x83,0xa2,0x61,0x00,0xbf,0x4f,0xf4,0x00,0x60,0x60,0x83, +0x98,0x07,0x46,0xbf,0x4f,0xf4,0x40,0x60,0x20,0x83,0xa2,0x61,0x00,0xbf,0xdb,0x07, +0x4f,0xf4,0x00,0x60,0x48,0xbf,0x4f,0xf4,0x40,0x63,0x70,0x83,0x4c,0xbf,0x23,0x83, +0xa2,0x61,0x00,0xbf,0x4f,0xf4,0x00,0x60,0x60,0x83,0x00,0xbf,0x02,0x31,0xd4,0x29, +0x20,0x83,0x9e,0xd1,0x4f,0xf4,0x80,0x40,0x4f,0xf4,0x00,0x53,0x30,0x83,0x01,0x35, +0x00,0x20,0x33,0x83,0xff,0xf7,0x64,0xfa,0x40,0x2d,0x7f,0xf4,0x75,0xaf,0xbd,0xe8, +0xf0,0x81,0x00,0xbf,0x00,0x0c,0x02,0x40,0x26,0x79,0x00,0x20,0x00,0x08,0x00,0x04, +0x03,0x4b,0x1a,0x88,0x03,0x4b,0xc2,0xf1,0x64,0x02,0x5a,0x63,0x70,0x47,0x00,0xbf, +0x14,0x82,0x00,0x20,0x00,0x44,0x01,0x40,0x01,0x4b,0x00,0x22,0x5a,0x63,0x70,0x47, +0x00,0x44,0x01,0x40,0x03,0x4b,0x18,0x80,0x03,0x4b,0xc0,0xf1,0x64,0x00,0x58,0x63, +0x70,0x47,0x00,0xbf,0x14,0x82,0x00,0x20,0x00,0x44,0x01,0x40,0x73,0xb5,0xff,0xf7, +0xe7,0xfe,0x49,0x4d,0x08,0x20,0x01,0x21,0xfb,0xf7,0x88,0xfa,0x4f,0xf4,0x30,0x53, +0x00,0x24,0x01,0x26,0x00,0x93,0x28,0x46,0x02,0x23,0x69,0x46,0x8d,0xf8,0x04,0x60, +0x8d,0xf8,0x05,0x30,0x8d,0xf8,0x06,0x40,0x8d,0xf8,0x07,0x40,0xfb,0xf7,0xe4,0xfb, +0x4f,0xf4,0xa0,0x43,0x69,0x46,0x8d,0xf8,0x04,0x60,0x8d,0xf8,0x07,0x60,0x28,0x46, +0x4f,0xf4,0x80,0x56,0x00,0x93,0x8d,0xf8,0x06,0x40,0x8d,0xf8,0x05,0x40,0xfb,0xf7, +0xd3,0xfb,0x2e,0x83,0x05,0x20,0xff,0xf7,0x95,0xfe,0x6e,0x83,0x78,0x20,0xff,0xf7, +0x91,0xfe,0x2e,0x83,0x40,0xf6,0xc4,0x15,0x28,0x46,0xff,0xf7,0x8b,0xfe,0xe2,0x20, +0xff,0xf7,0xd6,0xf9,0x28,0x46,0xff,0xf7,0x85,0xfe,0xff,0xf7,0xa9,0xfe,0x25,0x20, +0xff,0xf7,0xce,0xf9,0x2b,0x20,0xff,0xf7,0xcb,0xf9,0xea,0x20,0xff,0xf7,0xc8,0xf9, +0x81,0x20,0xff,0xf7,0xc5,0xf9,0x1e,0x20,0xff,0xf7,0xc2,0xf9,0xa6,0x20,0xff,0xf7, +0xbf,0xf9,0xd1,0x20,0xff,0xf7,0xbc,0xf9,0xd5,0x20,0xff,0xf7,0xb9,0xf9,0xa0,0x20, +0xff,0xf7,0xb6,0xf9,0xc8,0x20,0xff,0xf7,0xb3,0xf9,0x1d,0x20,0xff,0xf7,0xb0,0xf9, +0xf1,0x20,0xff,0xf7,0xad,0xf9,0x3f,0x20,0xff,0xf7,0xaa,0xf9,0x84,0x20,0xff,0xf7, +0xa7,0xf9,0xc4,0x20,0xff,0xf7,0xa4,0xf9,0x89,0x20,0xff,0xf7,0xa1,0xf9,0xf8,0x20, +0xff,0xf7,0x9e,0xf9,0xf4,0x20,0xff,0xf7,0x9b,0xf9,0x20,0x46,0xff,0xf7,0x98,0xf9, +0xf5,0x20,0xff,0xf7,0x95,0xf9,0x60,0x20,0xff,0xf7,0x92,0xf9,0xf6,0x20,0xff,0xf7, +0x8f,0xf9,0x47,0x20,0xff,0xf7,0x8c,0xf9,0xf7,0x20,0xff,0xf7,0x89,0xf9,0x9f,0x20, +0xff,0xf7,0x86,0xf9,0xaf,0x20,0xff,0xf7,0x83,0xf9,0x78,0x20,0xff,0xf7,0x32,0xfe, +0xaf,0x20,0xff,0xf7,0x7d,0xf9,0x7c,0xbd,0x00,0x0c,0x02,0x40,0x10,0xb5,0x04,0x46, +0x81,0x20,0xff,0xf7,0x75,0xf9,0x05,0x34,0xe0,0xb2,0xbd,0xe8,0x10,0x40,0xff,0xf7, +0x6f,0xb9,0x00,0xbf,0x70,0xb5,0x0a,0x4c,0x80,0x26,0x32,0x20,0x40,0x25,0x26,0x83, +0x00,0xf0,0x62,0xfe,0x32,0x20,0x25,0x83,0x00,0xf0,0x5e,0xfe,0x32,0x20,0x66,0x83, +0x00,0xf0,0x5a,0xfe,0x32,0x20,0x65,0x83,0x00,0xf0,0x56,0xfe,0x01,0x20,0x70,0xbd, +0x00,0x04,0x02,0x40,0x70,0xb5,0x0a,0x4c,0x40,0x26,0x32,0x20,0x80,0x25,0x66,0x83, +0x00,0xf0,0x4a,0xfe,0x32,0x20,0x65,0x83,0x00,0xf0,0x46,0xfe,0x32,0x20,0x26,0x83, +0x00,0xf0,0x42,0xfe,0x32,0x20,0x25,0x83,0xbd,0xe8,0x70,0x40,0x00,0xf0,0x3c,0xbe, +0x00,0x04,0x02,0x40,0x38,0xb5,0x0a,0x4c,0x40,0x25,0x32,0x20,0x65,0x83,0x00,0xf0, +0x33,0xfe,0x80,0x23,0x63,0x83,0x32,0x20,0x00,0xf0,0x2e,0xfe,0x32,0x20,0x25,0x83, +0x00,0xf0,0x2a,0xfe,0x32,0x20,0x65,0x83,0xbd,0xe8,0x38,0x40,0x00,0xf0,0x24,0xbe, +0x00,0x04,0x02,0x40,0x38,0xb5,0x0a,0x4c,0x40,0x25,0x32,0x20,0x65,0x83,0x00,0xf0, +0x1b,0xfe,0x80,0x23,0x23,0x83,0x32,0x20,0x00,0xf0,0x16,0xfe,0x32,0x20,0x25,0x83, +0x00,0xf0,0x12,0xfe,0x32,0x20,0x65,0x83,0xbd,0xe8,0x38,0x40,0x00,0xf0,0x0c,0xbe, +0x00,0x04,0x02,0x40,0x38,0xb5,0x12,0x4d,0x40,0x22,0x6a,0x83,0x32,0x20,0x00,0xf0, +0x03,0xfe,0x80,0x23,0x2b,0x83,0x32,0x20,0x00,0xf0,0xfe,0xfd,0x40,0x22,0x2a,0x83, +0x32,0x20,0x00,0xf0,0xf9,0xfd,0x32,0x24,0x2b,0x69,0x1b,0x06,0x07,0xd5,0x01,0x3c, +0x32,0x20,0xa4,0xb2,0x00,0xf0,0xf0,0xfd,0x00,0x2c,0xf5,0xd1,0x00,0xe0,0x02,0x24, +0x03,0x4b,0x40,0x22,0x32,0x20,0x5a,0x83,0x00,0xf0,0xe6,0xfd,0x20,0xb2,0x38,0xbd, +0x00,0x04,0x02,0x40,0x70,0xb5,0x06,0x46,0x09,0x25,0x10,0x4c,0x12,0xe0,0x40,0x22, +0x62,0x83,0x32,0x06,0x02,0xd5,0x80,0x23,0x23,0x83,0x01,0xe0,0x80,0x22,0x62,0x83, +0x32,0x20,0x00,0xf0,0xd1,0xfd,0x40,0x23,0x76,0x00,0x23,0x83,0x32,0x20,0xf6,0xb2, +0x00,0xf0,0xca,0xfd,0x01,0x3d,0xad,0xb2,0x00,0x2d,0xe8,0xd1,0x03,0x4b,0x40,0x22, +0x32,0x20,0x5a,0x83,0xbd,0xe8,0x70,0x40,0x00,0xf0,0xbe,0xbd,0x00,0x04,0x02,0x40, +0x70,0xb5,0x10,0x4d,0x80,0x22,0x2a,0x83,0x09,0x26,0x00,0x24,0x10,0xe0,0x40,0x23, +0x6b,0x83,0x32,0x20,0x00,0xf0,0xb0,0xfd,0x40,0x22,0x32,0x20,0x2a,0x83,0x00,0xf0, +0xab,0xfd,0x2b,0x69,0x64,0x00,0xe4,0xb2,0x19,0x06,0x48,0xbf,0x44,0xf0,0x01,0x04, +0x01,0x3e,0xb6,0xb2,0x00,0x2e,0xea,0xd1,0x02,0x4b,0x40,0x22,0x5a,0x83,0x20,0x46, +0x70,0xbd,0x00,0xbf,0x00,0x04,0x02,0x40,0x38,0xb5,0x02,0x20,0x01,0x21,0xfb,0xf7, +0x15,0xf9,0x0e,0x4b,0x0e,0x4c,0x1a,0x6b,0x4f,0xf4,0x00,0x75,0x42,0xf0,0x02,0x02, +0x1a,0x63,0x1a,0x6b,0x28,0x46,0x42,0xf0,0x10,0x02,0x1a,0x63,0x44,0xf2,0x01,0x11, +0x65,0x83,0x00,0xf0,0x01,0xfa,0xc0,0x20,0x4c,0xf2,0x05,0x11,0x00,0xf0,0xfc,0xf9, +0x80,0x23,0x23,0x83,0x40,0x23,0x23,0x83,0x65,0x83,0x38,0xbd,0x00,0x38,0x02,0x40, +0x00,0x04,0x02,0x40,0x10,0xb5,0x04,0x46,0xff,0xf7,0x04,0xff,0x5c,0x20,0xff,0xf7, +0x89,0xff,0xff,0xf7,0x5f,0xff,0x00,0x20,0xff,0xf7,0x84,0xff,0xff,0xf7,0x5a,0xff, +0x20,0x46,0xff,0xf7,0x7f,0xff,0xff,0xf7,0x55,0xff,0xbd,0xe8,0x10,0x40,0x09,0xe7, +0x10,0xb5,0xff,0xf7,0xef,0xfe,0x5c,0x20,0xff,0xf7,0x74,0xff,0xff,0xf7,0x4a,0xff, +0x00,0x20,0xff,0xf7,0x6f,0xff,0xff,0xf7,0x45,0xff,0xff,0xf7,0xe3,0xfe,0x5d,0x20, +0xff,0xf7,0x68,0xff,0xff,0xf7,0x3e,0xff,0xff,0xf7,0x8a,0xff,0x04,0x46,0xff,0xf7, +0x21,0xff,0xff,0xf7,0xef,0xfe,0x20,0x46,0x10,0xbd,0x38,0xb5,0x0d,0x46,0x04,0x46, +0xff,0xf7,0xd0,0xfe,0xa2,0x20,0xff,0xf7,0x55,0xff,0xff,0xf7,0x2b,0xff,0x28,0x0a, +0xff,0xf7,0x50,0xff,0xff,0xf7,0x26,0xff,0xe8,0xb2,0xff,0xf7,0x4b,0xff,0xff,0xf7, +0x21,0xff,0x20,0x78,0xff,0xf7,0x46,0xff,0xff,0xf7,0x1c,0xff,0xbd,0xe8,0x38,0x40, +0xd0,0xe6,0x70,0xb5,0x0d,0x46,0x16,0x46,0x04,0x46,0xff,0xf7,0xb3,0xfe,0xa2,0x20, +0xff,0xf7,0x38,0xff,0xff,0xf7,0x0e,0xff,0x28,0x0a,0xff,0xf7,0x33,0xff,0xff,0xf7, +0x09,0xff,0xe8,0xb2,0xff,0xf7,0x2e,0xff,0xff,0xf7,0x04,0xff,0xff,0xf7,0xa2,0xfe, +0xa3,0x20,0xff,0xf7,0x27,0xff,0xff,0xf7,0xfd,0xfe,0x11,0xe0,0x01,0x2e,0x07,0xd1, +0xff,0xf7,0x46,0xff,0x20,0x70,0xff,0xf7,0xdd,0xfe,0xff,0xf7,0xab,0xfe,0x05,0xe0, +0xff,0xf7,0x3e,0xff,0x04,0xf8,0x01,0x0b,0xff,0xf7,0xbc,0xfe,0x01,0x3e,0xb6,0xb2, +0x00,0x2e,0xeb,0xd1,0x70,0xbd,0x70,0xb5,0x0d,0x46,0x16,0x46,0x04,0x46,0xff,0xf7, +0x81,0xfe,0xa2,0x20,0xff,0xf7,0x06,0xff,0xff,0xf7,0xdc,0xfe,0x28,0x0a,0xff,0xf7, +0x01,0xff,0xff,0xf7,0xd7,0xfe,0xe8,0xb2,0xff,0xf7,0xfc,0xfe,0xff,0xf7,0xd2,0xfe, +0x07,0xe0,0x14,0xf8,0x01,0x0b,0xff,0xf7,0xf5,0xfe,0xff,0xf7,0xcb,0xfe,0x01,0x3e, +0xf6,0xb2,0x00,0x2e,0xf5,0xd1,0xbd,0xe8,0x70,0x40,0x7b,0xe6,0x08,0xb5,0xff,0xf7, +0x61,0xfe,0xa2,0x20,0xff,0xf7,0xe6,0xfe,0xff,0xf7,0xbc,0xfe,0x00,0x28,0xf6,0xd0, +0xbd,0xe8,0x08,0x40,0x6e,0xe6,0x2d,0xe9,0xf8,0x43,0x5f,0xfa,0x82,0xf9,0x11,0xf0, +0x3f,0x05,0x06,0x46,0x0c,0x46,0xc2,0xf3,0x87,0x18,0x09,0xf0,0x3f,0x07,0x17,0xd1, +0xb8,0xf1,0x00,0x0f,0x4b,0xd0,0x01,0xeb,0x88,0x19,0x1f,0xfa,0x89,0xf9,0x05,0x46, +0x09,0xe0,0x28,0x46,0x21,0x46,0x40,0x22,0xff,0xf7,0xb5,0xff,0xff,0xf7,0xd6,0xff, +0x40,0x34,0xa4,0xb2,0x40,0x35,0x4c,0x45,0xf3,0xd1,0x06,0xeb,0x88,0x10,0x35,0xe0, +0xc5,0xf1,0x40,0x05,0xed,0xb2,0xb8,0xf1,0x00,0x0f,0x0d,0xd1,0xaa,0x42,0x2f,0xd9, +0x2a,0x46,0xff,0xf7,0xa0,0xff,0x2c,0x19,0xff,0xf7,0xc0,0xff,0x70,0x19,0xc5,0xeb, +0x09,0x05,0xa1,0xb2,0xea,0xb2,0x24,0xe0,0x57,0x1b,0xbf,0xb2,0x2c,0x19,0xc7,0xf3, +0x87,0x18,0xa4,0xb2,0x2a,0x46,0x75,0x19,0x04,0xeb,0x88,0x16,0xff,0xf7,0x8b,0xff, +0x07,0xf0,0x3f,0x07,0xff,0xf7,0xaa,0xff,0xb6,0xb2,0xa9,0x46,0x0a,0xe0,0x48,0x46, +0x21,0x46,0x40,0x22,0xff,0xf7,0x7f,0xff,0xff,0xf7,0xa0,0xff,0x40,0x34,0xa4,0xb2, +0x09,0xf1,0x40,0x09,0xb4,0x42,0xf2,0xd1,0x05,0xeb,0x88,0x10,0x37,0xb1,0x21,0x46, +0x3a,0x46,0xff,0xf7,0x70,0xff,0xbd,0xe8,0xf8,0x43,0x8f,0xe7,0xbd,0xe8,0xf8,0x83, +0x01,0x4b,0x18,0x70,0x70,0x47,0x00,0xbf,0x18,0x82,0x00,0x20,0x02,0x4b,0x00,0x22, +0x18,0x78,0x1a,0x70,0x70,0x47,0x00,0xbf,0x18,0x82,0x00,0x20,0x30,0xb5,0x04,0x78, +0x63,0x00,0x03,0xf0,0x0e,0x03,0x63,0xf3,0x03,0x04,0x04,0x70,0x29,0xb1,0x43,0xf0, +0x01,0x01,0xe3,0xb2,0x61,0xf3,0x03,0x03,0x03,0x70,0x41,0x78,0x83,0x78,0x01,0x31, +0xc9,0xb2,0x41,0x70,0xa3,0xb1,0x04,0x78,0x14,0xf0,0x0f,0x0f,0x10,0xd1,0x63,0x2b, +0x0b,0xd0,0x33,0x4c,0x42,0xf0,0x20,0x05,0x10,0x2b,0x25,0x70,0x01,0xd1,0x0f,0x29, +0x03,0xd9,0x03,0x78,0x6f,0xf3,0x05,0x13,0x03,0x70,0x00,0x23,0x43,0x70,0x83,0x70, +0x83,0x78,0x08,0x2b,0x3a,0xd0,0x06,0xd8,0x01,0x2b,0x3e,0xd0,0x0e,0xd3,0x02,0x2b, +0x34,0xd0,0x04,0x2b,0x03,0xe0,0x5f,0x2b,0x23,0xd0,0x02,0xd8,0x10,0x2b,0x45,0xd1, +0x2c,0xe0,0x61,0x2b,0x10,0xd0,0x62,0x2b,0x40,0xd1,0x38,0xe0,0x03,0x78,0x03,0xf0, +0x0f,0x02,0x0f,0x2a,0x3a,0xd1,0x61,0x22,0x82,0x70,0x42,0x78,0x10,0x2a,0x84,0xbf, +0x6f,0xf3,0x05,0x13,0x03,0x70,0x16,0xe0,0x19,0x4b,0x42,0xf0,0x60,0x02,0x1a,0x70, +0x03,0x78,0xc3,0xf3,0x01,0x12,0x01,0x32,0x62,0xf3,0x05,0x13,0x03,0x70,0x5f,0x23, +0x08,0xe0,0x43,0x78,0x20,0x2b,0x08,0xbf,0x62,0xf0,0x7f,0x02,0x14,0xd0,0x28,0x2b, +0x1c,0xd1,0x10,0x23,0x83,0x70,0x00,0x23,0x43,0x70,0x30,0xbd,0x41,0x78,0x2f,0x29, +0x03,0xd9,0x5b,0x10,0x83,0x70,0x00,0x23,0x43,0x70,0x81,0x78,0x43,0x78,0x01,0x39, +0x19,0x42,0x0b,0xd1,0x42,0xf0,0x40,0x02,0x05,0x4b,0x1a,0x70,0x30,0xbd,0x43,0x78, +0x3f,0x2b,0x03,0xd9,0x08,0x23,0x83,0x70,0x00,0x23,0x43,0x70,0x30,0xbd,0x00,0xbf, +0x18,0x82,0x00,0x20,0x00,0xf0,0x0f,0x03,0x0f,0x2b,0x07,0xd0,0x04,0x4a,0x03,0x20, +0x00,0xfb,0x03,0x20,0x62,0x23,0x83,0x70,0x00,0x23,0x43,0x70,0x70,0x47,0x00,0xbf, +0x19,0x82,0x00,0x20,0x00,0xf0,0x0f,0x00,0x0f,0x28,0x09,0xd0,0x03,0x22,0x50,0x43, +0x04,0x4b,0x63,0x21,0x1a,0x18,0x91,0x70,0x1a,0x5c,0x6f,0xf3,0x05,0x12,0x1a,0x54, +0x70,0x47,0x00,0xbf,0x19,0x82,0x00,0x20,0x2d,0xe9,0xf0,0x41,0x11,0x4f,0x03,0x26, +0x97,0xf8,0x2e,0x30,0x01,0x25,0x01,0x33,0xdb,0xb2,0x87,0xf8,0x2e,0x30,0x00,0xf0, +0xc3,0xf8,0x6f,0xea,0x00,0x08,0x5f,0xfa,0x88,0xf8,0x00,0x22,0x01,0x37,0x00,0xe0, +0x22,0x46,0x54,0x1c,0x15,0xfa,0x04,0xf3,0x13,0xea,0x08,0x0f,0x06,0xfb,0x02,0x70, +0x0c,0xbf,0x00,0x21,0x01,0x21,0xd2,0xb2,0xff,0xf7,0x38,0xff,0x06,0x2c,0xef,0xd1, +0xbd,0xe8,0xf0,0x81,0x18,0x82,0x00,0x20,0x2d,0xe9,0xf0,0x4f,0xc1,0xf3,0x02,0x23, +0x03,0x27,0x01,0xea,0x07,0x06,0x9b,0x02,0x85,0xb0,0xc1,0xf3,0x03,0x12,0x75,0x1e, +0x03,0xf1,0x80,0x43,0xc1,0xf3,0x41,0x38,0xc1,0xf3,0x81,0x0b,0x01,0x24,0x09,0xb2, +0x01,0x92,0x02,0x95,0x03,0xf5,0x00,0x33,0x00,0x22,0x25,0x46,0x03,0x91,0x00,0x90, +0xdd,0xf8,0x00,0xa0,0x14,0xea,0x0a,0x0f,0x6b,0xd0,0x51,0x00,0x07,0xfa,0x01,0xf9, +0xd3,0xf8,0x00,0xc0,0x2c,0xea,0x09,0x0c,0x06,0xfa,0x01,0xf9,0xc3,0xf8,0x00,0xc0, +0xd3,0xf8,0x00,0xc0,0x49,0xea,0x0c,0x0c,0xc3,0xf8,0x00,0xc0,0xdd,0xf8,0x08,0xc0, +0xbc,0xf1,0x01,0x0f,0x29,0xd8,0x6f,0xf0,0x03,0x00,0x00,0xfa,0x01,0xf9,0xd3,0xf8, +0x08,0xc0,0xdd,0xf8,0x0c,0xa0,0x09,0xea,0x0c,0x0c,0x08,0xfa,0x01,0xf9,0xc3,0xf8, +0x08,0xc0,0xd3,0xf8,0x08,0xc0,0xba,0xf1,0x00,0x0f,0x49,0xea,0x0c,0x0c,0x1f,0xfa, +0x82,0xf9,0x05,0xfa,0x09,0xf9,0xc3,0xf8,0x08,0xc0,0xd3,0xf8,0x04,0xc0,0x2c,0xea, +0x09,0x0c,0xb8,0xbf,0x05,0xfa,0x02,0xf9,0xc3,0xf8,0x04,0xc0,0xbe,0xbf,0xd3,0xf8, +0x04,0xc0,0x49,0xea,0x0c,0x0c,0xc3,0xf8,0x04,0xc0,0x1f,0xfa,0x82,0xf9,0x4f,0xea, +0x49,0x09,0x07,0xfa,0x09,0xf9,0x0b,0xfa,0x01,0xf1,0xd3,0xf8,0x0c,0xc0,0x0f,0x20, +0x2c,0xea,0x09,0x0c,0xc3,0xf8,0x0c,0xc0,0xd3,0xf8,0x0c,0xc0,0x41,0xea,0x0c,0x01, +0x02,0xf0,0x07,0x0c,0x4f,0xea,0x8c,0x0c,0x00,0xfa,0x0c,0xf9,0xd9,0x60,0xd1,0x08, +0x08,0x31,0x53,0xf8,0x21,0xa0,0x2a,0xea,0x09,0x09,0xdd,0xf8,0x04,0xa0,0x43,0xf8, +0x21,0x90,0x0a,0xfa,0x0c,0xfc,0x53,0xf8,0x21,0x90,0x4c,0xea,0x09,0x0c,0x43,0xf8, +0x21,0xc0,0x01,0x32,0x64,0x00,0x10,0x2a,0x8a,0xd1,0x05,0xb0,0xbd,0xe8,0xf0,0x8f, +0x08,0xb5,0x08,0x4b,0x4f,0xf4,0xe0,0x50,0x1a,0x6b,0x40,0xf2,0x04,0x41,0x42,0xf0, +0x10,0x02,0x1a,0x63,0xff,0xf7,0x60,0xff,0x8c,0x20,0x4f,0xf4,0x41,0x71,0xbd,0xe8, +0x08,0x40,0x59,0xe7,0x00,0x38,0x02,0x40,0x0e,0x4b,0x1b,0x69,0x13,0xf0,0x80,0x00, +0x18,0xbf,0x10,0x20,0x1a,0x07,0x48,0xbf,0x40,0xf0,0x40,0x00,0x5b,0x07,0x0a,0x4b, +0x48,0xbf,0x40,0xf0,0x08,0x00,0x1b,0x69,0x59,0x05,0x48,0xbf,0x40,0xf0,0x02,0x00, +0x1a,0x05,0x48,0xbf,0x40,0xf0,0x20,0x00,0xdb,0x04,0x48,0xbf,0x40,0xf0,0x04,0x00, +0x70,0x47,0x00,0xbf,0x00,0x0c,0x02,0x40,0x00,0x10,0x02,0x40,0x08,0xb5,0x0e,0x4b, +0x20,0x20,0x1a,0x6b,0x04,0x21,0x42,0xf0,0x01,0x02,0x1a,0x63,0x1a,0x6b,0x42,0xf0, +0x02,0x02,0x1a,0x63,0x1a,0x6b,0x42,0xf0,0x10,0x02,0x1a,0x63,0xff,0xf7,0x24,0xff, +0x3a,0x20,0x4f,0xf4,0x82,0x71,0xff,0xf7,0x1f,0xff,0x4e,0xf2,0x07,0x30,0x40,0xf2, +0x04,0x41,0xbd,0xe8,0x08,0x40,0x17,0xe7,0x00,0x38,0x02,0x40,0x10,0xb5,0x46,0x4b, +0x0e,0x28,0x19,0x69,0xd3,0xf8,0x10,0x24,0x03,0xf5,0x80,0x53,0x1b,0x69,0x0b,0xd8, +0x03,0x23,0x58,0x43,0x41,0x4b,0xc0,0x5c,0x00,0xf0,0x0f,0x00,0xa0,0xf1,0x0f,0x01, +0x48,0x42,0x40,0xeb,0x01,0x00,0x10,0xbd,0x0f,0x38,0x15,0x28,0x71,0xd8,0xdf,0xe8, +0x00,0xf0,0x0b,0x10,0x17,0x19,0x1d,0x24,0x26,0x2a,0x33,0x37,0x3b,0x42,0x46,0x4a, +0x4e,0x52,0x55,0x59,0x5d,0x62,0x66,0x69,0x03,0xf0,0x01,0x00,0x80,0xf0,0x01,0x00, +0x5b,0xe0,0x02,0xf0,0x20,0x00,0x03,0xf0,0x01,0x03,0x18,0x43,0x21,0x28,0x08,0xe0, +0xd0,0x43,0x0d,0xe0,0xd8,0x43,0x00,0xf0,0x04,0x00,0x4e,0xe0,0x03,0xf0,0x06,0x00, +0x06,0x28,0x14,0xbf,0x00,0x20,0x01,0x20,0x47,0xe0,0xd8,0x43,0x11,0xe0,0xc8,0x43, +0x00,0xf0,0x20,0x00,0x41,0xe0,0x03,0xf4,0x00,0x40,0x01,0xf0,0x20,0x01,0x08,0x43, +0x48,0xf2,0x20,0x02,0x90,0x42,0xec,0xe7,0xd8,0x43,0x00,0xf4,0x00,0x40,0x34,0xe0, +0xd0,0x43,0x00,0xf0,0x02,0x00,0x30,0xe0,0x03,0xf0,0x80,0x00,0x02,0xf0,0x02,0x02, +0x10,0x43,0x82,0x28,0xdd,0xe7,0xd8,0x43,0x00,0xf0,0x80,0x00,0x25,0xe0,0xd0,0x43, +0x00,0xf0,0x10,0x00,0x21,0xe0,0x02,0xf0,0x18,0x00,0x18,0x28,0xd1,0xe7,0xd0,0x43, +0x00,0xf0,0x08,0x00,0x19,0xe0,0x03,0xf4,0x80,0x40,0x16,0xe0,0xd8,0x43,0x00,0xf4, +0x80,0x40,0x12,0xe0,0xd8,0x43,0x00,0xf4,0x00,0x70,0x0e,0xe0,0x03,0xf4,0x40,0x70, +0xb0,0xf5,0x40,0x7f,0xbd,0xe7,0xd8,0x43,0x00,0xf4,0x80,0x70,0x05,0xe0,0x03,0xf4, +0x00,0x50,0x02,0xe0,0xd8,0x43,0x00,0xf4,0x00,0x50,0x00,0x30,0x18,0xbf,0x01,0x20, +0x10,0xbd,0x00,0x20,0x10,0xbd,0x00,0xbf,0x00,0x00,0x02,0x40,0x19,0x82,0x00,0x20, +0x03,0x23,0x58,0x43,0x10,0xb5,0x00,0xf1,0x0f,0x04,0x1e,0x2c,0x88,0xbf,0x00,0xf1, +0x0e,0x04,0xe0,0xb2,0xff,0xf7,0x62,0xff,0x90,0xb9,0x01,0x34,0xe0,0xb2,0xff,0xf7, +0x5d,0xff,0x78,0xb1,0xb4,0xf1,0x1f,0x00,0x18,0xbf,0x01,0x20,0x24,0x2c,0x0c,0xbf, +0x00,0x24,0x00,0xf0,0x01,0x04,0x00,0x2c,0x14,0xbf,0x01,0x20,0x02,0x20,0x10,0xbd, +0x00,0x20,0x10,0xbd,0x02,0x20,0x10,0xbd,0x7f,0x28,0x15,0xd9,0x0b,0x4b,0x31,0xb1, +0xff,0x28,0x10,0xd8,0x0a,0x4b,0x80,0x38,0x33,0xf8,0x10,0x00,0x70,0x47,0x33,0xf8, +0x02,0x2f,0x82,0x42,0x03,0xd0,0x01,0x31,0x89,0xb2,0x80,0x29,0xf7,0xd1,0x01,0xf1, +0x80,0x00,0xc0,0xb2,0x70,0x47,0x00,0x20,0x70,0x47,0x00,0xbf,0x4c,0x6b,0x00,0x20, +0x4e,0x6b,0x00,0x20,0x07,0x4a,0x00,0x23,0x32,0xf8,0x02,0x1f,0x49,0xb1,0x88,0x42, +0x05,0xd1,0x05,0x4a,0x02,0xeb,0x43,0x03,0xb3,0xf8,0xe0,0x02,0x70,0x47,0x01,0x33, +0xf2,0xe7,0x70,0x47,0x4c,0x6c,0x00,0x20,0x4e,0x6b,0x00,0x20,0x70,0x47,0x70,0x47, +0x70,0x47,0x70,0x47,0x70,0x47,0x70,0x47,0x70,0x47,0x00,0x00,0x00,0x20,0x70,0x47, +0x01,0x20,0x70,0x47,0x13,0xb5,0x31,0x23,0x00,0x24,0x8d,0xf8,0x04,0x30,0x01,0xa8, +0x01,0x23,0x8d,0xf8,0x05,0x40,0x8d,0xf8,0x06,0x40,0x8d,0xf8,0x07,0x30,0xfb,0xf7, +0xa7,0xf8,0x20,0x46,0x1c,0xbd,0x01,0x28,0x08,0xb5,0x06,0xd0,0xfe,0xf7,0x2c,0xfe, +0x00,0x28,0x14,0xbf,0xff,0x20,0x00,0x20,0x00,0xe0,0x00,0x20,0x40,0xb2,0x08,0xbd, +0x01,0x28,0xf8,0xb5,0x0e,0x46,0x14,0x46,0x05,0xd1,0x4f,0xf4,0x00,0x73,0x13,0x60, +0x40,0xf2,0x43,0x43,0x12,0xe0,0xfe,0xf7,0x17,0xfe,0x90,0xb9,0x4f,0xf4,0x00,0x73, +0x23,0x60,0x09,0x4c,0x25,0x68,0x27,0x46,0x3d,0xb9,0x28,0x46,0x01,0x21,0x22,0x46, +0xfe,0xf7,0x9c,0xff,0x08,0xb1,0x25,0x60,0x03,0xe0,0x3b,0x68,0x33,0x60,0x00,0x20, +0x00,0xe0,0xff,0x20,0x40,0xb2,0xf8,0xbd,0x4c,0x82,0x00,0x20,0xf8,0xb5,0x05,0x46, +0x0c,0x46,0x16,0x46,0x40,0xf2,0x82,0x47,0x27,0xe0,0x28,0x46,0x15,0x49,0xd4,0xb1, +0x01,0x2c,0x04,0xbf,0x28,0x46,0x14,0x49,0x15,0xd0,0x02,0x2c,0x04,0xbf,0x28,0x46, +0x12,0x49,0x10,0xd0,0x42,0x2c,0x08,0xd8,0xe1,0x1e,0x49,0x02,0x89,0xb2,0x28,0x46, +0x4f,0xf4,0x00,0x72,0xff,0xf7,0x1d,0xfc,0x09,0xe0,0xbc,0x42,0x07,0xd8,0x0c,0x49, +0x63,0x02,0x59,0x18,0x28,0x46,0x4f,0xf4,0x00,0x72,0x00,0xf0,0x37,0xfb,0x01,0x34, +0x01,0x3e,0x05,0xf5,0x00,0x75,0xa4,0xb2,0xb6,0xb2,0x00,0x2e,0xd5,0xd1,0x30,0x46, +0xf8,0xbd,0x00,0xbf,0x10,0x70,0x00,0x20,0x10,0x72,0x00,0x20,0x10,0x74,0x00,0x20, +0x00,0x7a,0xff,0x07,0x10,0xb5,0x04,0x46,0x01,0x2c,0x08,0x46,0x04,0xd1,0x91,0xb2, +0x1a,0x46,0xff,0xf7,0xbb,0xff,0x03,0xe0,0x11,0x46,0x1a,0x46,0xfe,0xf7,0x5e,0xfe, +0x00,0x28,0x14,0xbf,0xff,0x20,0x00,0x20,0x40,0xb2,0x10,0xbd,0x02,0x29,0x2d,0xe9, +0xf0,0x47,0x05,0x46,0x0c,0x46,0x16,0x46,0x5f,0xd9,0x42,0x29,0x35,0xd8,0x2d,0xe0, +0x7b,0x68,0xd3,0xf1,0x01,0x03,0x38,0xbf,0x00,0x23,0x03,0x2c,0x14,0xbf,0x00,0x23, +0x03,0xf0,0x01,0x03,0x3b,0xb1,0x6b,0x78,0x80,0x2b,0x04,0xd1,0xeb,0x78,0x80,0x2b, +0x08,0xbf,0xc7,0xf8,0x04,0x80,0xd9,0xf8,0x04,0x10,0x59,0xb1,0x8c,0x42,0x09,0xdb, +0x61,0x1a,0x3f,0x29,0x06,0xdc,0x49,0x02,0x89,0xb2,0x28,0x46,0x4f,0xf4,0x00,0x72, +0xff,0xf7,0x21,0xfc,0x01,0x34,0x7b,0x68,0xa4,0xb2,0xe3,0x1a,0x01,0x3e,0x3f,0x2b, +0x05,0xf5,0x00,0x75,0x06,0xdd,0x00,0x23,0x7b,0x60,0x03,0xe0,0x18,0x4f,0x4f,0xf0, +0x03,0x08,0xb9,0x46,0x00,0x2e,0xcb,0xd1,0x27,0xe0,0x40,0xf2,0x82,0x43,0x99,0x42, +0x23,0xd8,0x14,0x4f,0x4c,0x02,0xdf,0xf8,0x50,0x90,0xe7,0x19,0xdf,0xf8,0x4c,0x80, +0x07,0xf5,0x80,0x74,0xca,0x46,0xc6,0xb1,0x4f,0x45,0x05,0xd9,0x47,0x45,0x03,0xd8, +0x38,0x46,0x29,0x46,0x00,0xf0,0x06,0xf9,0x54,0x45,0x06,0xd9,0x44,0x45,0x04,0xd8, +0x05,0xf5,0x80,0x71,0x20,0x46,0x00,0xf0,0xfd,0xf8,0x07,0xf5,0x00,0x77,0x05,0xf5, +0x00,0x75,0x01,0x3e,0x04,0xf5,0x00,0x74,0xe5,0xe7,0x00,0x20,0xbd,0xe8,0xf0,0x87, +0x4c,0x82,0x00,0x20,0x00,0x7a,0xff,0x07,0xff,0x7f,0x00,0x08,0xff,0xfe,0x07,0x08, +0x10,0xb5,0x04,0x46,0x01,0x2c,0x08,0x46,0x04,0xd1,0x91,0xb2,0x1a,0x46,0xff,0xf7, +0x85,0xff,0x03,0xe0,0x11,0x46,0x1a,0x46,0xfe,0xf7,0x40,0xfe,0x00,0x28,0x14,0xbf, +0xff,0x20,0x00,0x20,0x40,0xb2,0x10,0xbd,0x01,0x48,0xfb,0xf7,0xc9,0xbd,0x00,0xbf, +0x58,0x82,0x00,0x20,0x03,0x68,0x9b,0x0c,0x9b,0x04,0xb3,0xf1,0x00,0x5f,0x0e,0xd1, +0x43,0x68,0x1b,0x0d,0x1b,0x05,0xb3,0xf1,0x00,0x6f,0x0a,0xd1,0x80,0x68,0x00,0x0d, +0x00,0x05,0xa0,0xf1,0x00,0x63,0x58,0x42,0x40,0xeb,0x03,0x00,0x70,0x47,0x00,0x20, +0x70,0x47,0x00,0x20,0x70,0x47,0x04,0x4b,0x93,0xf8,0xf4,0x25,0x42,0xf0,0x01,0x02, +0x83,0xf8,0xf4,0x25,0xff,0xf7,0xb8,0xbc,0x58,0x82,0x00,0x20,0x12,0x4b,0x13,0x49, +0x1a,0x6c,0x42,0xf4,0x80,0x72,0x1a,0x64,0xa3,0xf5,0x06,0x33,0x42,0xf2,0x0f,0x72, +0xda,0x62,0x0f,0x4a,0x09,0x68,0x12,0x68,0x4a,0x43,0x0e,0x49,0xb2,0xfb,0xf1,0xf2, +0x01,0x3a,0x92,0xb2,0x1a,0x85,0x00,0x22,0x1a,0x84,0x1a,0x83,0x9a,0x82,0x05,0x22, +0x1a,0x80,0x9a,0x89,0x92,0xb2,0x42,0xf0,0x01,0x02,0x9a,0x81,0x06,0x4b,0x4f,0xf4, +0x00,0x52,0x5a,0x60,0x70,0x47,0x00,0xbf,0x00,0x38,0x02,0x40,0x70,0x9f,0x00,0x20, +0x74,0x9f,0x00,0x20,0x40,0x42,0x0f,0x00,0x00,0xe1,0x00,0xe0,0x03,0x4a,0x13,0x8a, +0x23,0xf0,0x01,0x03,0x1b,0x04,0x1b,0x0c,0x13,0x82,0xbc,0xe7,0x00,0x20,0x00,0x40, +0x0d,0x4b,0x0e,0x49,0x1a,0x6c,0x42,0xf0,0x80,0x02,0x1a,0x64,0xa3,0xf5,0x07,0x33, +0x4f,0xf6,0xff,0x72,0xda,0x62,0x0a,0x4a,0x09,0x68,0x12,0x68,0x4a,0x43,0x09,0x49, +0xb2,0xfb,0xf1,0xf2,0x01,0x3a,0x92,0xb2,0x1a,0x85,0x00,0x22,0x1a,0x84,0x1a,0x83, +0x9a,0x82,0x01,0x22,0x1a,0x80,0x70,0x47,0x00,0x38,0x02,0x40,0x70,0x9f,0x00,0x20, +0x74,0x9f,0x00,0x20,0x80,0x96,0x98,0x00,0x04,0x4b,0x00,0x22,0x5a,0x62,0x01,0x22, +0x9a,0x82,0x5a,0x6a,0x82,0x42,0xfc,0xd3,0x70,0x47,0x00,0xbf,0x00,0x1c,0x00,0x40, +0x03,0x4b,0x04,0x4a,0x5a,0x60,0x02,0xf1,0x88,0x32,0x5a,0x60,0x70,0x47,0x00,0xbf, +0x00,0x3c,0x02,0x40,0x23,0x01,0x67,0x45,0x04,0x49,0x05,0x4a,0x4a,0xf6,0xaa,0x23, +0x00,0xe0,0x13,0x60,0xc8,0x68,0xc0,0x03,0xfb,0xd4,0x70,0x47,0x00,0x3c,0x02,0x40, +0x00,0x30,0x00,0x40,0x38,0xb5,0x12,0x4c,0x05,0x46,0xff,0xf7,0xed,0xff,0x23,0x69, +0x23,0xf4,0x40,0x73,0x23,0x61,0x23,0x69,0x43,0xf4,0x00,0x73,0x23,0x61,0x23,0x69, +0x23,0xf0,0xf8,0x03,0x23,0x61,0x23,0x69,0x43,0xf0,0x02,0x03,0x43,0xea,0xc5,0x05, +0x25,0x61,0x23,0x69,0x43,0xf4,0x80,0x33,0x23,0x61,0xff,0xf7,0xd5,0xff,0x23,0x69, +0x23,0xf0,0x02,0x03,0x23,0x61,0x23,0x69,0x23,0xf0,0xf8,0x03,0x23,0x61,0x38,0xbd, +0x00,0x3c,0x02,0x40,0xf8,0xb5,0x2d,0x4b,0x04,0x46,0x98,0x42,0x0d,0x46,0x07,0xd1, +0x08,0x46,0xff,0xf7,0x27,0xff,0x2a,0x4b,0x00,0x22,0x00,0xb9,0x01,0x22,0x1a,0x60, +0x27,0x4b,0x1b,0x68,0x00,0x2b,0x44,0xd1,0x24,0x4b,0x9c,0x42,0x03,0xd1,0x02,0x20, +0xff,0xf7,0xc0,0xff,0x0d,0xe0,0x23,0x4b,0x9c,0x42,0x03,0xd1,0x03,0x20,0xff,0xf7, +0xb9,0xff,0x0a,0xe0,0x20,0x4b,0x9c,0x42,0x03,0xd1,0x04,0x20,0xff,0xf7,0xb2,0xff, +0x07,0xe0,0x1e,0x4b,0x05,0x20,0x9c,0x42,0x07,0xd0,0x1d,0x4b,0x06,0x20,0x9c,0x42, +0x03,0xd0,0x1c,0x4b,0x9c,0x42,0x02,0xd1,0x07,0x20,0xff,0xf7,0xa3,0xff,0x1a,0x4e, +0x00,0x27,0xff,0xf7,0x91,0xff,0x33,0x69,0x23,0xf4,0x40,0x73,0x33,0x61,0x33,0x69, +0x43,0xf4,0x00,0x73,0x33,0x61,0x33,0x69,0x43,0xf0,0x01,0x03,0x33,0x61,0xeb,0x59, +0xe3,0x51,0xff,0xf7,0x81,0xff,0x33,0x69,0x23,0xf0,0x01,0x03,0x33,0x61,0xe2,0x59, +0xeb,0x59,0x9a,0x42,0x07,0xd1,0x04,0x37,0xb7,0xf5,0x80,0x7f,0xe1,0xd1,0x00,0x20, +0xf8,0xbd,0x01,0x20,0xf8,0xbd,0x02,0x20,0xf8,0xbd,0x00,0xbf,0x00,0x80,0x00,0x08, +0x10,0x79,0x00,0x20,0x00,0xc0,0x00,0x08,0x00,0x00,0x01,0x08,0x00,0x00,0x02,0x08, +0x00,0x00,0x04,0x08,0x00,0x00,0x06,0x08,0x00,0x3c,0x02,0x40,0x00,0xe0,0x18,0x46, +0x11,0xf8,0x01,0x2b,0x03,0x46,0x03,0xf8,0x01,0x2b,0x00,0x2a,0xf7,0xd1,0x70,0x47, +0x2d,0xe9,0xf0,0x41,0x07,0x46,0x0c,0x46,0x01,0xf1,0x09,0x06,0x38,0x46,0x21,0x46, +0xfe,0xf7,0x07,0xfa,0x05,0x46,0x00,0x28,0x40,0xd1,0x63,0x7a,0x00,0x2b,0x3d,0xd0, +0xa0,0x69,0x03,0x78,0x13,0xb9,0x31,0x46,0xff,0xf7,0xe0,0xff,0xd4,0xf8,0x18,0x80, +0x40,0x46,0x00,0xf0,0xaf,0xf9,0x03,0x1f,0x18,0xf8,0x03,0x20,0x80,0x44,0xdb,0x0f, +0x2e,0x2a,0x18,0xf8,0x03,0x2c,0x18,0xbf,0x01,0x23,0xb2,0xf1,0x62,0x01,0x18,0xbf, +0x01,0x21,0x42,0x2a,0x0c,0xbf,0x00,0x22,0x01,0xf0,0x01,0x02,0x00,0x2a,0x18,0xbf, +0x01,0x23,0x18,0xf8,0x02,0x2c,0xb2,0xf1,0x69,0x01,0x18,0xbf,0x01,0x21,0x49,0x2a, +0x0c,0xbf,0x00,0x22,0x01,0xf0,0x01,0x02,0x00,0x2a,0x18,0xbf,0x01,0x23,0x18,0xf8, +0x01,0x2c,0xb2,0xf1,0x6e,0x01,0x18,0xbf,0x01,0x21,0x4e,0x2a,0x0c,0xbf,0x00,0x22, +0x01,0xf0,0x01,0x02,0x00,0x2a,0xb9,0xd1,0x00,0x2b,0xb7,0xd1,0x28,0x46,0xbd,0xe8, +0xf0,0x81,0x2d,0xe9,0xf0,0x41,0x24,0x4c,0x00,0x21,0x04,0xf5,0xc3,0x63,0xc4,0xf8, +0x10,0x36,0x30,0x23,0xc4,0xf8,0x14,0x36,0x06,0x46,0x04,0xf5,0x20,0x60,0xfe,0xf7, +0xb0,0xf9,0x04,0xf5,0xbf,0x61,0x04,0xf5,0x20,0x60,0xfe,0xf7,0xaa,0xf9,0x04,0xf5, +0x20,0x60,0x04,0xf5,0xbf,0x61,0xfe,0xf7,0xa4,0xf9,0x00,0x25,0x17,0x48,0xa0,0xf5, +0x81,0x61,0xff,0xf7,0x8d,0xff,0xd4,0xf8,0xf8,0x35,0x04,0x28,0xc4,0xf8,0x24,0x3a, +0x1d,0xd0,0x01,0x35,0xb5,0x42,0xf1,0xd9,0x0f,0x4d,0x11,0x4e,0x01,0x24,0x05,0xf5, +0xc3,0x68,0x32,0x27,0x07,0xfb,0x04,0x83,0x0c,0x48,0xc5,0xf8,0x10,0x36,0xa0,0xf5, +0x81,0x61,0xff,0xf7,0x75,0xff,0xd5,0xf8,0xf8,0x35,0x46,0xf8,0x04,0x3f,0x38,0xb9, +0x95,0xf8,0x01,0x36,0x23,0xb1,0x01,0x34,0x07,0x2c,0xeb,0xd1,0x00,0xe0,0x00,0x24, +0x20,0x46,0xbd,0xe8,0xf0,0x81,0x00,0xbf,0x58,0x82,0x00,0x20,0x58,0x8c,0x00,0x20, +0x7c,0x8c,0x00,0x20,0x70,0xb5,0x12,0x4d,0x12,0x4c,0x06,0x46,0x12,0x49,0x28,0x46, +0xff,0xf7,0x4c,0xff,0x04,0xf5,0xc3,0x63,0x32,0x21,0x01,0xfb,0x06,0x31,0x04,0xf5, +0x2b,0x64,0xff,0xf7,0x43,0xff,0x01,0x22,0x29,0x46,0x20,0x46,0xfd,0xf7,0x10,0xff, +0x20,0x46,0x4f,0xf4,0x00,0x41,0xfe,0xf7,0xbd,0xf8,0x08,0x4b,0x20,0x46,0x04,0xf1, +0x1c,0x01,0x4f,0xf4,0x80,0x52,0xbd,0xe8,0x70,0x40,0xfd,0xf7,0x42,0xbf,0x00,0xbf, +0xcc,0x8c,0x00,0x20,0x58,0x82,0x00,0x20,0xaf,0x76,0x00,0x20,0x24,0x9d,0x00,0x20, +0x70,0xb5,0x2d,0x4d,0x04,0x46,0xfd,0xf7,0x1b,0xf9,0x00,0x20,0x2b,0x49,0xfc,0xf7, +0x8f,0xff,0xd5,0xf8,0xd8,0x39,0x7b,0xb9,0x20,0x46,0xff,0xf7,0xc3,0xff,0x28,0x48, +0xfd,0xf7,0xb3,0xff,0x01,0x23,0x27,0x48,0xc5,0xf8,0xd8,0x39,0xff,0xf7,0xd2,0xfd, +0x10,0xb9,0x02,0x23,0xc5,0xf8,0xd8,0x39,0x1f,0x4d,0xd5,0xf8,0xd8,0x39,0x02,0x2b, +0x0e,0xd1,0x18,0x20,0x20,0x49,0xfc,0xf7,0x73,0xff,0x30,0x20,0x1f,0x49,0xfc,0xf7, +0x6f,0xff,0xff,0xf7,0xeb,0xf9,0x82,0x28,0x14,0xbf,0x04,0x20,0x03,0x20,0x70,0xbd, +0x1b,0x4e,0x32,0x22,0x06,0xf5,0xc3,0x63,0x02,0xfb,0x04,0x32,0x00,0x20,0x15,0x23, +0x10,0x21,0xfc,0xf7,0x4a,0xff,0x28,0x20,0x16,0x49,0xfc,0xf7,0x59,0xff,0x30,0x20, +0x15,0x49,0xfc,0xf7,0x55,0xff,0xff,0xf7,0xd1,0xf9,0x83,0x28,0x0d,0xd1,0x20,0x46, +0xff,0xf7,0x88,0xff,0x06,0xeb,0x84,0x04,0xd4,0xf8,0x24,0x3a,0x00,0x28,0x0c,0xbf, +0x02,0x20,0x04,0x20,0xc5,0xf8,0xdc,0x39,0x70,0xbd,0xa0,0xf1,0x82,0x0c,0xdc,0xf1, +0x00,0x00,0x40,0xeb,0x0c,0x00,0x70,0xbd,0x50,0x93,0x00,0x20,0xba,0x76,0x00,0x20, +0x08,0x8d,0x00,0x20,0x24,0x8d,0x00,0x20,0xc6,0x76,0x00,0x20,0xdb,0x76,0x00,0x20, +0x58,0x82,0x00,0x20,0xe3,0x76,0x00,0x20,0xeb,0x76,0x00,0x20,0x0f,0x2a,0xf0,0xb4, +0x98,0xbf,0x03,0x46,0x31,0xd9,0x41,0xea,0x00,0x03,0x9b,0x07,0x36,0xd1,0x0c,0x46, +0x03,0x46,0x15,0x46,0x26,0x68,0x10,0x3d,0x1e,0x60,0x66,0x68,0x5e,0x60,0xa6,0x68, +0x9e,0x60,0xe6,0x68,0x10,0x34,0xde,0x60,0x10,0x33,0x0f,0x2d,0xf2,0xd8,0xa2,0xf1, +0x10,0x04,0x02,0xf0,0x0f,0x02,0x24,0xf0,0x0f,0x04,0x10,0x34,0x03,0x2a,0x00,0xeb, +0x04,0x03,0x21,0x44,0x11,0xd9,0x0e,0x46,0x1d,0x46,0x14,0x46,0x56,0xf8,0x04,0x7b, +0x04,0x3c,0x03,0x2c,0x45,0xf8,0x04,0x7b,0xf8,0xd8,0x14,0x1f,0x02,0xf0,0x03,0x02, +0x24,0xf0,0x03,0x04,0x04,0x34,0x09,0x19,0x1b,0x19,0x2a,0xb1,0x11,0xf8,0x01,0x4b, +0x01,0x3a,0x03,0xf8,0x01,0x4b,0xf9,0xd1,0xf0,0xbc,0x70,0x47,0x03,0x46,0xf5,0xe7, +0x10,0xf0,0x03,0x0f,0x03,0x46,0x70,0xb4,0x41,0xd0,0x00,0x2a,0x3d,0xd0,0xce,0xb2, +0x01,0xe0,0x00,0x2a,0x39,0xd0,0x03,0xf8,0x01,0x6b,0x54,0x1e,0x13,0xf0,0x03,0x0f, +0x22,0x46,0x1d,0x46,0xf5,0xd1,0x03,0x2c,0x29,0xd9,0xca,0xb2,0x0f,0x2c,0x84,0xbf, +0x2b,0x46,0x26,0x46,0x42,0xea,0x02,0x22,0x42,0xea,0x02,0x42,0x11,0xd9,0x10,0x3e, +0x1a,0x60,0x5a,0x60,0x9a,0x60,0xda,0x60,0x10,0x33,0x0f,0x2e,0xf7,0xd8,0xa4,0xf1, +0x10,0x03,0x04,0xf0,0x0f,0x04,0x23,0xf0,0x0f,0x03,0x10,0x33,0x03,0x2c,0x1d,0x44, +0x0d,0xd9,0x2e,0x46,0x23,0x46,0x04,0x3b,0x46,0xf8,0x04,0x2b,0x03,0x2b,0xfa,0xd8, +0x23,0x1f,0x04,0xf0,0x03,0x04,0x23,0xf0,0x03,0x03,0x04,0x33,0xed,0x18,0xc9,0xb2, +0x1c,0xb1,0x01,0x3c,0x05,0xf8,0x01,0x1b,0xfb,0xd1,0x70,0xbc,0x70,0x47,0x05,0x46, +0x14,0x46,0xc8,0xe7,0x20,0xf0,0x03,0x01,0x10,0xf0,0x03,0x00,0xc0,0xf1,0x00,0x00, +0x51,0xf8,0x04,0x3b,0x00,0xf1,0x04,0x0c,0x4f,0xea,0xcc,0x0c,0x6f,0xf0,0x00,0x02, +0x1c,0xbf,0x22,0xfa,0x0c,0xf2,0x13,0x43,0x4f,0xf0,0x01,0x0c,0x4c,0xea,0x0c,0x2c, +0x4c,0xea,0x0c,0x4c,0xa3,0xeb,0x0c,0x02,0x22,0xea,0x03,0x02,0x12,0xea,0xcc,0x12, +0x04,0xbf,0x51,0xf8,0x04,0x3b,0x04,0x30,0xf4,0xd0,0x13,0xf0,0xff,0x0f,0x1f,0xbf, +0x01,0x30,0x13,0xf4,0x7f,0x4f,0x01,0x30,0x13,0xf4,0x7f,0x0f,0x18,0xbf,0x01,0x30, +0x70,0x47,0x00,0xbf,0x00,0x21,0x03,0xe0,0x0a,0x4b,0x5b,0x58,0x43,0x50,0x04,0x31, +0x09,0x48,0x0a,0x4b,0x42,0x18,0x9a,0x42,0xf6,0xd3,0x09,0x4a,0x02,0xe0,0x00,0x23, +0x42,0xf8,0x04,0x3b,0x07,0x4b,0x9a,0x42,0xf9,0xd3,0xf9,0xf7,0xc5,0xfe,0x00,0xf0, +0x0d,0xf8,0x70,0x47,0x48,0x77,0x00,0x20,0x48,0x77,0x00,0x20,0x14,0x79,0x00,0x20, +0x14,0x79,0x00,0x20,0x38,0xb0,0x00,0x20,0xfe,0xe7,0x00,0x00,0x2d,0xe9,0xf0,0x4f, +0xb2,0x4c,0x89,0xb0,0x4a,0xf6,0xaa,0x25,0xfe,0xf7,0x08,0xfe,0x25,0x60,0xfc,0xf7, +0xc7,0xff,0x00,0x20,0xae,0x49,0xfc,0xf7,0x3b,0xfe,0xfe,0xf7,0x48,0xfd,0xad,0x4b, +0x25,0x60,0x1a,0x6b,0x42,0xf0,0x01,0x02,0x1a,0x63,0xff,0xf7,0x19,0xfa,0xfe,0xf7, +0x6b,0xff,0xff,0xf7,0xdd,0xfc,0x62,0xb6,0xff,0xf7,0xa0,0xfc,0xa6,0x4b,0x4f,0xf4, +0x00,0x70,0xc3,0xf8,0xe0,0x09,0x4f,0xf4,0x41,0x71,0xff,0xf7,0x75,0xf9,0x00,0x20, +0xfe,0xf7,0x9a,0xf9,0xfe,0xf7,0x80,0xfc,0xff,0xf7,0xfa,0xfc,0x9f,0x48,0xfc,0xf7, +0xcd,0xfc,0x9f,0x4b,0x9f,0x4a,0x00,0x93,0x9c,0x48,0x9f,0x4b,0x01,0x21,0x00,0x26, +0xfb,0xf7,0xac,0xfd,0x4f,0xf4,0x80,0x02,0x02,0x23,0x05,0x92,0x35,0x46,0x37,0x46, +0xb2,0x46,0x34,0x46,0x06,0x93,0xb0,0x46,0x90,0x4a,0x4a,0xf6,0xaa,0x21,0x93,0x4b, +0x11,0x60,0x93,0xf8,0xf4,0x05,0x00,0x28,0xf6,0xd0,0x11,0x60,0x8e,0x4a,0x92,0xf8, +0xe4,0x19,0x11,0xb1,0x01,0x39,0x82,0xf8,0xe4,0x19,0x4f,0xf0,0x00,0x09,0x83,0xf8, +0xf4,0x95,0xfc,0xf7,0x75,0xff,0x48,0x46,0x85,0x49,0xfc,0xf7,0xe9,0xfd,0xfe,0xf7, +0x66,0xfc,0x00,0x28,0x00,0xf0,0x8d,0x81,0x48,0x46,0xdf,0xf8,0x48,0x92,0x87,0x49, +0xfc,0xf7,0xde,0xfd,0xd9,0xf8,0x10,0x30,0x9b,0x05,0x01,0xd4,0x0a,0x2c,0x09,0xd1, +0x18,0x20,0x83,0x49,0xfc,0xf7,0xd4,0xfd,0xd9,0xf8,0x10,0x30,0x9c,0x05,0x04,0xd5, +0x0a,0x24,0x76,0xe1,0x00,0x2c,0x40,0xf0,0x8a,0x81,0x00,0x20,0x7d,0x49,0xfd,0xf7, +0x17,0xfd,0x00,0x24,0x00,0x28,0x40,0xf0,0x6c,0x81,0x7b,0x48,0xfd,0xf7,0xfe,0xfd, +0x18,0xb1,0x80,0xe1,0x02,0x2c,0x10,0xd1,0x00,0xe0,0x80,0x46,0x77,0x48,0x78,0x49, +0xfd,0xf7,0x2d,0xff,0x04,0x46,0x00,0x28,0x40,0xf0,0x7b,0x81,0xff,0xf7,0x99,0xfd, +0x25,0x46,0x82,0x46,0x27,0x46,0xa0,0x46,0x02,0xe0,0x03,0x2c,0x40,0xf0,0x98,0x80, +0xba,0xf1,0x06,0x0f,0x34,0xbf,0x52,0x46,0x06,0x22,0x4f,0xf0,0x00,0x09,0x07,0x92, +0x4f,0xf0,0x10,0x0b,0x4c,0x46,0x23,0xe0,0x6a,0x4a,0x32,0x23,0x03,0xfb,0x04,0x20, +0xff,0xf7,0xf8,0xfe,0x48,0x45,0x88,0xbf,0x5f,0xfa,0x80,0xf9,0x15,0x28,0x07,0xd9, +0x05,0xf1,0x15,0x03,0x83,0x42,0x98,0xbf,0x28,0x46,0x02,0xd9,0x15,0x38,0x00,0xe0, +0x00,0x20,0x32,0x23,0x03,0xfb,0x04,0x00,0x5e,0x4b,0x59,0x46,0x1a,0x18,0x00,0x20, +0x15,0x23,0xfc,0xf7,0x6a,0xfd,0x0b,0xf1,0x08,0x0b,0x01,0x34,0x5f,0xfa,0x8b,0xfb, +0x07,0x9a,0x94,0x42,0xd8,0xd1,0xfe,0xf7,0xf1,0xff,0x83,0x46,0xa0,0xf1,0x44,0x00, +0x43,0x42,0x43,0xeb,0x00,0x03,0xbb,0xf1,0x64,0x0f,0x08,0xbf,0x43,0xf0,0x01,0x03, +0x73,0xb1,0x63,0x1e,0x9f,0x42,0x01,0xd2,0x01,0x37,0x09,0xe0,0xa2,0x45,0x07,0xd9, +0x08,0xf1,0x01,0x08,0x5f,0xfa,0x88,0xf8,0x40,0x46,0xff,0xf7,0x42,0xfd,0x82,0x46, +0xab,0xf1,0x40,0x01,0x4b,0x42,0x43,0xeb,0x01,0x03,0xbb,0xf1,0x60,0x0f,0x08,0xbf, +0x43,0xf0,0x01,0x03,0x6b,0xb1,0x0f,0xb1,0x01,0x3f,0x0a,0xe0,0xb8,0xf1,0x00,0x0f, +0x07,0xd0,0x08,0xf1,0xff,0x38,0x5f,0xfa,0x88,0xf8,0x40,0x46,0xff,0xf7,0x29,0xfd, +0x82,0x46,0xab,0xf1,0x41,0x02,0x53,0x42,0x43,0xeb,0x02,0x03,0xbb,0xf1,0x61,0x0f, +0x08,0xbf,0x43,0xf0,0x01,0x03,0x23,0xb1,0x05,0xf1,0x15,0x03,0x4b,0x45,0x38,0xbf, +0x01,0x35,0xab,0xf1,0x45,0x09,0xd9,0xf1,0x00,0x03,0x43,0xeb,0x09,0x03,0xbb,0xf1, +0x65,0x0f,0x08,0xbf,0x43,0xf0,0x01,0x03,0x0b,0xb1,0x05,0xb1,0x01,0x3d,0x03,0x24, +0xbb,0xf1,0x83,0x0f,0x04,0xd1,0x20,0x4b,0x00,0x22,0xc3,0xf8,0xd8,0x29,0x04,0x24, +0xb9,0x1c,0xc9,0x00,0x00,0x20,0xc9,0xb2,0x7e,0x22,0x03,0x46,0xfc,0xf7,0x88,0xfd, +0x04,0x2c,0x17,0xd1,0x38,0x46,0xff,0xf7,0x73,0xfd,0x18,0x4b,0x03,0x24,0x03,0xeb, +0x87,0x03,0xd3,0xf8,0x24,0x2a,0x14,0x4b,0xa2,0xf5,0x00,0x42,0x01,0x28,0xc3,0xf8, +0xdc,0x29,0x00,0xf0,0xa6,0x80,0x02,0x28,0x08,0xd0,0x03,0x28,0x14,0xbf,0x04,0x24, +0x03,0x24,0x9e,0xe0,0x05,0x2c,0x40,0xf0,0x8f,0x80,0x02,0xe0,0x16,0x4b,0x00,0x26, +0x05,0x93,0x18,0x20,0x15,0x49,0x00,0x24,0xfc,0xf7,0xea,0xfc,0xdf,0xf8,0x18,0xb0, +0x13,0x4b,0x22,0x46,0xdd,0xf8,0x14,0x90,0x3e,0xe0,0x00,0xbf,0x00,0x30,0x00,0x40, +0xfa,0x76,0x00,0x20,0x00,0x38,0x02,0x40,0x50,0x93,0x00,0x20,0x58,0x82,0x00,0x20, +0xd0,0x78,0x00,0x20,0x08,0x78,0x00,0x20,0xbc,0x77,0x00,0x20,0x06,0x77,0x00,0x20, +0x0d,0x77,0x00,0x20,0x38,0x9d,0x00,0x20,0x13,0x77,0x00,0x20,0x58,0x8c,0x00,0x20, +0x1d,0x77,0x00,0x20,0x70,0x88,0x00,0x20,0x00,0x80,0x00,0x08,0x1f,0x77,0x00,0x20, +0x24,0x8d,0x00,0x20,0x00,0x00,0x02,0x40,0x03,0xeb,0x84,0x01,0x48,0x46,0x03,0x92, +0x04,0x93,0xff,0xf7,0xd7,0xfb,0xdb,0xf8,0xd4,0x19,0x03,0x9a,0x40,0x34,0xb1,0xf5, +0x80,0x7f,0x88,0xbf,0xa1,0xf5,0x80,0x71,0x04,0x9b,0x09,0xf5,0x80,0x79,0x8c,0xbf, +0xcb,0xf8,0xd4,0x19,0xcb,0xf8,0xd4,0x29,0xdb,0xf8,0xd4,0x19,0x00,0x29,0xe3,0xd1, +0x35,0x4b,0xcd,0xf8,0x14,0x90,0xd3,0xf8,0xdc,0x39,0x89,0x46,0xc3,0xf3,0x07,0x3b, +0x0b,0xf1,0x01,0x04,0x64,0xb2,0x08,0x46,0x22,0x46,0x27,0x21,0xfc,0xf7,0x26,0xfd, +0x48,0x46,0x30,0x21,0x22,0x46,0xfc,0xf7,0x21,0xfd,0x58,0x46,0x28,0x21,0x08,0x22, +0x01,0x36,0xfc,0xf7,0x1d,0xfd,0x07,0xe0,0x5f,0xfa,0x89,0xf0,0x28,0x21,0x08,0x22, +0xfc,0xf7,0x16,0xfd,0x09,0xf1,0x01,0x09,0xb1,0x45,0xf5,0xd3,0x23,0x48,0xdf,0xf8, +0x88,0x90,0x23,0x4b,0x00,0xf1,0x1c,0x01,0x4f,0xf4,0x80,0x52,0xfd,0xf7,0x11,0xfc, +0xd9,0xf8,0xe0,0x39,0xd9,0xf8,0xd4,0x49,0x9b,0x08,0x09,0x3b,0x00,0x2c,0x0c,0xbf, +0x06,0x24,0x05,0x24,0x9e,0x42,0x01,0xd8,0x06,0x2c,0x0a,0xd1,0xfe,0xf7,0xde,0xfe, +0x18,0x49,0x04,0x46,0x18,0x20,0xfc,0xf7,0x5b,0xfc,0x82,0x2c,0x0c,0xbf,0x03,0x24, +0x06,0x24,0x06,0x9a,0x01,0x2a,0x04,0xd1,0xfe,0xf7,0x61,0xfb,0x02,0x23,0x06,0x93, +0x01,0xe0,0x01,0x22,0x06,0x92,0x0c,0x4b,0xd3,0xf8,0x10,0x2c,0x13,0x2a,0x03,0xd8, +0x01,0x32,0xc3,0xf8,0x10,0x2c,0x3f,0xe6,0xfe,0xf7,0x82,0xfa,0x3c,0xe6,0x01,0x2c, +0x7f,0xf4,0x80,0xae,0x79,0xe6,0x10,0x20,0x07,0x49,0xfc,0xf7,0x39,0xfc,0x01,0x24, +0xdf,0xe7,0x02,0x24,0xdd,0xe7,0x00,0xbf,0x50,0x93,0x00,0x20,0x08,0x8d,0x00,0x20, +0x24,0x9d,0x00,0x20,0x28,0x77,0x00,0x20,0x3a,0x77,0x00,0x20,0x02,0x01,0x02,0x00, +0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x03,0x00,0x80,0x83,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x6f,0x00, +0x00,0x07,0x00,0x07,0x00,0x14,0x7f,0x14,0x7f,0x14,0x24,0x2a,0x7f,0x2a,0x12,0x23, +0x13,0x08,0x64,0x62,0x36,0x49,0x55,0x22,0x50,0x00,0x05,0x03,0x00,0x00,0x00,0x1c, +0x22,0x41,0x00,0x00,0x41,0x22,0x1c,0x00,0x14,0x08,0x3e,0x08,0x14,0x08,0x08,0x3e, +0x08,0x08,0x00,0x50,0x30,0x00,0x00,0x08,0x08,0x08,0x08,0x08,0x00,0x60,0x60,0x00, +0x00,0x20,0x10,0x08,0x04,0x02,0x00,0x3e,0x49,0x45,0x3e,0x00,0x00,0x42,0x7f,0x40, +0x00,0x62,0x51,0x49,0x46,0x00,0x41,0x49,0x49,0x36,0x00,0x18,0x14,0x12,0x7f,0x00, +0x27,0x45,0x45,0x39,0x00,0x3e,0x49,0x49,0x32,0x00,0x01,0x79,0x05,0x03,0x00,0x36, +0x49,0x49,0x36,0x00,0x06,0x49,0x29,0x1e,0x00,0x00,0x36,0x36,0x00,0x00,0x00,0x56, +0x36,0x00,0x00,0x08,0x14,0x22,0x41,0x14,0x14,0x14,0x14,0x14,0x41,0x22,0x14,0x08, +0x00,0x02,0x01,0x51,0x09,0x06,0x00,0x06,0x09,0x09,0x06,0x7e,0x09,0x09,0x09,0x7e, +0x7f,0x49,0x49,0x49,0x36,0x3e,0x41,0x41,0x41,0x22,0x7f,0x41,0x41,0x22,0x1c,0x7f, +0x49,0x49,0x49,0x41,0x7f,0x09,0x09,0x09,0x01,0x3e,0x41,0x49,0x49,0x7a,0x7f,0x08, +0x08,0x08,0x7f,0x00,0x41,0x7f,0x41,0x00,0x20,0x40,0x41,0x3f,0x01,0x7f,0x08,0x14, +0x22,0x41,0x7f,0x40,0x40,0x40,0x40,0x7f,0x02,0x0c,0x02,0x7f,0x7f,0x04,0x08,0x10, +0x7f,0x3e,0x41,0x41,0x41,0x3e,0x7f,0x09,0x09,0x09,0x06,0x3e,0x41,0x51,0x21,0x5e, +0x7f,0x09,0x19,0x29,0x46,0x26,0x49,0x49,0x49,0x32,0x01,0x01,0x7f,0x01,0x01,0x3f, +0x40,0x40,0x40,0x3f,0x1f,0x20,0x40,0x20,0x1f,0x3f,0x40,0x30,0x40,0x3f,0x63,0x14, +0x08,0x14,0x63,0x07,0x08,0x70,0x08,0x07,0x61,0x51,0x49,0x45,0x43,0x00,0x7f,0x41, +0x41,0x00,0x02,0x04,0x08,0x10,0x20,0x00,0x41,0x41,0x7f,0x00,0x04,0x02,0x01,0x02, +0x04,0x40,0x40,0x40,0x40,0x40,0x00,0x01,0x02,0x04,0x00,0x20,0x54,0x54,0x54,0x78, +0x7f,0x48,0x44,0x44,0x38,0x38,0x44,0x44,0x44,0x20,0x38,0x44,0x44,0x48,0x7f,0x38, +0x54,0x54,0x54,0x18,0x08,0x7e,0x09,0x01,0x02,0x0c,0x52,0x52,0x52,0x3e,0x7f,0x08, +0x04,0x04,0x78,0x00,0x44,0x7d,0x40,0x00,0x20,0x40,0x44,0x3d,0x00,0x7f,0x10,0x28, +0x44,0x00,0x00,0x41,0x7f,0x40,0x00,0x7c,0x04,0x18,0x04,0x78,0x7c,0x08,0x04,0x04, +0x78,0x38,0x44,0x44,0x44,0x38,0x7c,0x14,0x14,0x14,0x08,0x08,0x14,0x14,0x18,0x7c, +0x7c,0x08,0x04,0x04,0x08,0x48,0x54,0x54,0x54,0x20,0x04,0x3f,0x44,0x40,0x20,0x3c, +0x40,0x40,0x20,0x7c,0x1c,0x20,0x40,0x20,0x1c,0x3c,0x40,0x20,0x40,0x3c,0x44,0x28, +0x10,0x28,0x44,0x0c,0x50,0x50,0x50,0x3c,0x44,0x64,0x54,0x4c,0x44,0x00,0x08,0x36, +0x41,0x00,0x00,0x00,0x7f,0x00,0x00,0x00,0x41,0x36,0x08,0x00,0x08,0x08,0x22,0x1c, +0x08,0x08,0x1c,0x22,0x08,0x08,0x04,0x02,0x7f,0x02,0x04,0x10,0x20,0x7f,0x20,0x10, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0xff,0xff,0xc3,0xc3,0xc3,0xc3,0xc3,0xe7,0xfe,0x3c,0x3f,0x3f, +0x30,0x30,0x30,0x30,0x30,0x39,0x1f,0x0f,0x3c,0x7e,0xe7,0xc3,0xc3,0xc3,0xc3,0xc7, +0x8e,0x0c,0x0c,0x1c,0x38,0x30,0x30,0x30,0x30,0x39,0x1f,0x0f,0xff,0xff,0x00,0x00, +0x00,0x00,0x00,0x00,0xff,0xff,0x0f,0x1f,0x38,0x30,0x30,0x30,0x30,0x38,0x1f,0x0f, +0x01,0x03,0x05,0x07,0x09,0x0e,0x10,0x12,0x14,0x16,0x18,0x1c,0x1e,0x80,0x9a,0x90, +0x41,0x8e,0x41,0x8f,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8e,0x8f,0x90,0x92,0x92, +0x4f,0x99,0x4f,0x55,0x55,0x59,0x99,0x9a,0x9b,0x9c,0x9d,0x9e,0x9f,0x41,0x49,0x4f, +0x55,0xa5,0xa5,0xa6,0xa7,0xa8,0xa9,0xaa,0xab,0xac,0x21,0xae,0xaf,0xb0,0xb1,0xb2, +0xb3,0xb4,0xb5,0xb6,0xb7,0xb8,0xb9,0xba,0xbb,0xbc,0xbd,0xbe,0xbf,0xc0,0xc1,0xc2, +0xc3,0xc4,0xc5,0xc6,0xc7,0xc8,0xc9,0xca,0xcb,0xcc,0xcd,0xce,0xcf,0xd0,0xd1,0xd2, +0xd3,0xd4,0xd5,0xd6,0xd7,0xd8,0xd9,0xda,0xdb,0xdc,0xdd,0xde,0xdf,0xe0,0xe1,0xe2, +0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,0xea,0xeb,0xec,0xed,0xee,0xef,0xf0,0xf1,0xf2, +0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,0xfe,0xff,0x00,0xc7,0x00, +0xfc,0x00,0xe9,0x00,0xe2,0x00,0xe4,0x00,0xe0,0x00,0xe5,0x00,0xe7,0x00,0xea,0x00, +0xeb,0x00,0xe8,0x00,0xef,0x00,0xee,0x00,0xec,0x00,0xc4,0x00,0xc5,0x00,0xc9,0x00, +0xe6,0x00,0xc6,0x00,0xf4,0x00,0xf6,0x00,0xf2,0x00,0xfb,0x00,0xf9,0x00,0xff,0x00, +0xd6,0x00,0xdc,0x00,0xa2,0x00,0xa3,0x00,0xa5,0x00,0xa7,0x20,0x92,0x01,0xe1,0x00, +0xed,0x00,0xf3,0x00,0xfa,0x00,0xf1,0x00,0xd1,0x00,0xaa,0x00,0xba,0x00,0xbf,0x00, +0x10,0x23,0xac,0x00,0xbd,0x00,0xbc,0x00,0xa1,0x00,0xab,0x00,0xbb,0x00,0x91,0x25, +0x92,0x25,0x93,0x25,0x02,0x25,0x24,0x25,0x61,0x25,0x62,0x25,0x56,0x25,0x55,0x25, +0x63,0x25,0x51,0x25,0x57,0x25,0x5d,0x25,0x5c,0x25,0x5b,0x25,0x10,0x25,0x14,0x25, +0x34,0x25,0x2c,0x25,0x1c,0x25,0x00,0x25,0x3c,0x25,0x5e,0x25,0x5f,0x25,0x5a,0x25, +0x54,0x25,0x69,0x25,0x66,0x25,0x60,0x25,0x50,0x25,0x6c,0x25,0x67,0x25,0x68,0x25, +0x64,0x25,0x65,0x25,0x59,0x25,0x58,0x25,0x52,0x25,0x53,0x25,0x6b,0x25,0x6a,0x25, +0x18,0x25,0x0c,0x25,0x88,0x25,0x84,0x25,0x8c,0x25,0x90,0x25,0x80,0x25,0xb1,0x03, +0xdf,0x00,0x93,0x03,0xc0,0x03,0xa3,0x03,0xc3,0x03,0xb5,0x00,0xc4,0x03,0xa6,0x03, +0x98,0x03,0xa9,0x03,0xb4,0x03,0x1e,0x22,0xc6,0x03,0xb5,0x03,0x29,0x22,0x61,0x22, +0xb1,0x00,0x65,0x22,0x64,0x22,0x20,0x23,0x21,0x23,0xf7,0x00,0x48,0x22,0xb0,0x00, +0x19,0x22,0xb7,0x00,0x1a,0x22,0x7f,0x20,0xb2,0x00,0xa0,0x25,0xa0,0x00,0x61,0x00, +0x62,0x00,0x63,0x00,0x64,0x00,0x65,0x00,0x66,0x00,0x67,0x00,0x68,0x00,0x69,0x00, +0x6a,0x00,0x6b,0x00,0x6c,0x00,0x6d,0x00,0x6e,0x00,0x6f,0x00,0x70,0x00,0x71,0x00, +0x72,0x00,0x73,0x00,0x74,0x00,0x75,0x00,0x76,0x00,0x77,0x00,0x78,0x00,0x79,0x00, +0x7a,0x00,0xa1,0x00,0xa2,0x00,0xa3,0x00,0xa5,0x00,0xac,0x00,0xaf,0x00,0xe0,0x00, +0xe1,0x00,0xe2,0x00,0xe3,0x00,0xe4,0x00,0xe5,0x00,0xe6,0x00,0xe7,0x00,0xe8,0x00, +0xe9,0x00,0xea,0x00,0xeb,0x00,0xec,0x00,0xed,0x00,0xee,0x00,0xef,0x00,0xf0,0x00, +0xf1,0x00,0xf2,0x00,0xf3,0x00,0xf4,0x00,0xf5,0x00,0xf6,0x00,0xf8,0x00,0xf9,0x00, +0xfa,0x00,0xfb,0x00,0xfc,0x00,0xfd,0x00,0xfe,0x00,0xff,0x00,0x01,0x01,0x03,0x01, +0x05,0x01,0x07,0x01,0x09,0x01,0x0b,0x01,0x0d,0x01,0x0f,0x01,0x11,0x01,0x13,0x01, +0x15,0x01,0x17,0x01,0x19,0x01,0x1b,0x01,0x1d,0x01,0x1f,0x01,0x21,0x01,0x23,0x01, +0x25,0x01,0x27,0x01,0x29,0x01,0x2b,0x01,0x2d,0x01,0x2f,0x01,0x31,0x01,0x33,0x01, +0x35,0x01,0x37,0x01,0x3a,0x01,0x3c,0x01,0x3e,0x01,0x40,0x01,0x42,0x01,0x44,0x01, +0x46,0x01,0x48,0x01,0x4b,0x01,0x4d,0x01,0x4f,0x01,0x51,0x01,0x53,0x01,0x55,0x01, +0x57,0x01,0x59,0x01,0x5b,0x01,0x5d,0x01,0x5f,0x01,0x61,0x01,0x63,0x01,0x65,0x01, +0x67,0x01,0x69,0x01,0x6b,0x01,0x6d,0x01,0x6f,0x01,0x71,0x01,0x73,0x01,0x75,0x01, +0x77,0x01,0x7a,0x01,0x7c,0x01,0x7e,0x01,0x92,0x01,0xb1,0x03,0xb2,0x03,0xb3,0x03, +0xb4,0x03,0xb5,0x03,0xb6,0x03,0xb7,0x03,0xb8,0x03,0xb9,0x03,0xba,0x03,0xbb,0x03, +0xbc,0x03,0xbd,0x03,0xbe,0x03,0xbf,0x03,0xc0,0x03,0xc1,0x03,0xc3,0x03,0xc4,0x03, +0xc5,0x03,0xc6,0x03,0xc7,0x03,0xc8,0x03,0xc9,0x03,0xca,0x03,0x30,0x04,0x31,0x04, +0x32,0x04,0x33,0x04,0x34,0x04,0x35,0x04,0x36,0x04,0x37,0x04,0x38,0x04,0x39,0x04, +0x3a,0x04,0x3b,0x04,0x3c,0x04,0x3d,0x04,0x3e,0x04,0x3f,0x04,0x40,0x04,0x41,0x04, +0x42,0x04,0x43,0x04,0x44,0x04,0x45,0x04,0x46,0x04,0x47,0x04,0x48,0x04,0x49,0x04, +0x4a,0x04,0x4b,0x04,0x4c,0x04,0x4d,0x04,0x4e,0x04,0x4f,0x04,0x51,0x04,0x52,0x04, +0x53,0x04,0x54,0x04,0x55,0x04,0x56,0x04,0x57,0x04,0x58,0x04,0x59,0x04,0x5a,0x04, +0x5b,0x04,0x5c,0x04,0x5e,0x04,0x5f,0x04,0x70,0x21,0x71,0x21,0x72,0x21,0x73,0x21, +0x74,0x21,0x75,0x21,0x76,0x21,0x77,0x21,0x78,0x21,0x79,0x21,0x7a,0x21,0x7b,0x21, +0x7c,0x21,0x7d,0x21,0x7e,0x21,0x7f,0x21,0x41,0xff,0x42,0xff,0x43,0xff,0x44,0xff, +0x45,0xff,0x46,0xff,0x47,0xff,0x48,0xff,0x49,0xff,0x4a,0xff,0x4b,0xff,0x4c,0xff, +0x4d,0xff,0x4e,0xff,0x4f,0xff,0x50,0xff,0x51,0xff,0x52,0xff,0x53,0xff,0x54,0xff, +0x55,0xff,0x56,0xff,0x57,0xff,0x58,0xff,0x59,0xff,0x5a,0xff,0x00,0x00,0x41,0x00, +0x42,0x00,0x43,0x00,0x44,0x00,0x45,0x00,0x46,0x00,0x47,0x00,0x48,0x00,0x49,0x00, +0x4a,0x00,0x4b,0x00,0x4c,0x00,0x4d,0x00,0x4e,0x00,0x4f,0x00,0x50,0x00,0x51,0x00, +0x52,0x00,0x53,0x00,0x54,0x00,0x55,0x00,0x56,0x00,0x57,0x00,0x58,0x00,0x59,0x00, +0x5a,0x00,0x21,0x00,0xe0,0xff,0xe1,0xff,0xe5,0xff,0xe2,0xff,0xe3,0xff,0xc0,0x00, +0xc1,0x00,0xc2,0x00,0xc3,0x00,0xc4,0x00,0xc5,0x00,0xc6,0x00,0xc7,0x00,0xc8,0x00, +0xc9,0x00,0xca,0x00,0xcb,0x00,0xcc,0x00,0xcd,0x00,0xce,0x00,0xcf,0x00,0xd0,0x00, +0xd1,0x00,0xd2,0x00,0xd3,0x00,0xd4,0x00,0xd5,0x00,0xd6,0x00,0xd8,0x00,0xd9,0x00, +0xda,0x00,0xdb,0x00,0xdc,0x00,0xdd,0x00,0xde,0x00,0x78,0x01,0x00,0x01,0x02,0x01, +0x04,0x01,0x06,0x01,0x08,0x01,0x0a,0x01,0x0c,0x01,0x0e,0x01,0x10,0x01,0x12,0x01, +0x14,0x01,0x16,0x01,0x18,0x01,0x1a,0x01,0x1c,0x01,0x1e,0x01,0x20,0x01,0x22,0x01, +0x24,0x01,0x26,0x01,0x28,0x01,0x2a,0x01,0x2c,0x01,0x2e,0x01,0x30,0x01,0x32,0x01, +0x34,0x01,0x36,0x01,0x39,0x01,0x3b,0x01,0x3d,0x01,0x3f,0x01,0x41,0x01,0x43,0x01, +0x45,0x01,0x47,0x01,0x4a,0x01,0x4c,0x01,0x4e,0x01,0x50,0x01,0x52,0x01,0x54,0x01, +0x56,0x01,0x58,0x01,0x5a,0x01,0x5c,0x01,0x5e,0x01,0x60,0x01,0x62,0x01,0x64,0x01, +0x66,0x01,0x68,0x01,0x6a,0x01,0x6c,0x01,0x6e,0x01,0x70,0x01,0x72,0x01,0x74,0x01, +0x76,0x01,0x79,0x01,0x7b,0x01,0x7d,0x01,0x91,0x01,0x91,0x03,0x92,0x03,0x93,0x03, +0x94,0x03,0x95,0x03,0x96,0x03,0x97,0x03,0x98,0x03,0x99,0x03,0x9a,0x03,0x9b,0x03, +0x9c,0x03,0x9d,0x03,0x9e,0x03,0x9f,0x03,0xa0,0x03,0xa1,0x03,0xa3,0x03,0xa4,0x03, +0xa5,0x03,0xa6,0x03,0xa7,0x03,0xa8,0x03,0xa9,0x03,0xaa,0x03,0x10,0x04,0x11,0x04, +0x12,0x04,0x13,0x04,0x14,0x04,0x15,0x04,0x16,0x04,0x17,0x04,0x18,0x04,0x19,0x04, +0x1a,0x04,0x1b,0x04,0x1c,0x04,0x1d,0x04,0x1e,0x04,0x1f,0x04,0x20,0x04,0x21,0x04, +0x22,0x04,0x23,0x04,0x24,0x04,0x25,0x04,0x26,0x04,0x27,0x04,0x28,0x04,0x29,0x04, +0x2a,0x04,0x2b,0x04,0x2c,0x04,0x2d,0x04,0x2e,0x04,0x2f,0x04,0x01,0x04,0x02,0x04, +0x03,0x04,0x04,0x04,0x05,0x04,0x06,0x04,0x07,0x04,0x08,0x04,0x09,0x04,0x0a,0x04, +0x0b,0x04,0x0c,0x04,0x0e,0x04,0x0f,0x04,0x60,0x21,0x61,0x21,0x62,0x21,0x63,0x21, +0x64,0x21,0x65,0x21,0x66,0x21,0x67,0x21,0x68,0x21,0x69,0x21,0x6a,0x21,0x6b,0x21, +0x6c,0x21,0x6d,0x21,0x6e,0x21,0x6f,0x21,0x21,0xff,0x22,0xff,0x23,0xff,0x24,0xff, +0x25,0xff,0x26,0xff,0x27,0xff,0x28,0xff,0x29,0xff,0x2a,0xff,0x2b,0xff,0x2c,0xff, +0x2d,0xff,0x2e,0xff,0x2f,0xff,0x30,0xff,0x31,0xff,0x32,0xff,0x33,0xff,0x34,0xff, +0x35,0xff,0x36,0xff,0x37,0xff,0x38,0xff,0x39,0xff,0x3a,0xff,0x00,0x00,0x00,0x00, +0xeb,0x3c,0x90,0x39,0x58,0x20,0x54,0x45,0x41,0x4d,0x00,0x00,0x02,0x08,0x01,0x00, +0x01,0x10,0x00,0x43,0x04,0xf8,0x01,0x00,0x20,0x00,0x40,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x29,0xce,0xfa,0x5c,0xd1,0x56,0x49,0x52,0x54,0x46, +0x53,0x20,0x20,0x20,0x20,0x20,0x46,0x41,0x54,0x31,0x32,0x20,0x20,0x20,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x55,0xaa, +0xf8,0xff,0xff,0x03,0x40,0x00,0x05,0x60,0x00,0x07,0x80,0x00,0x09,0xf0,0xff,0x0b, +0xc0,0x00,0x0d,0xe0,0x00,0x0f,0x00,0x01,0x11,0x20,0x01,0x13,0x40,0x01,0x15,0x60, +0x01,0x17,0x80,0x01,0x19,0xa0,0x01,0x1b,0xc0,0x01,0x1d,0xe0,0x01,0x1f,0x00,0x02, +0x21,0x20,0x02,0x23,0x40,0x02,0x25,0x60,0x02,0x27,0x80,0x02,0x29,0xa0,0x02,0x2b, +0xc0,0x02,0x2d,0xe0,0x02,0x2f,0x00,0x03,0x31,0x20,0x03,0x33,0x40,0x03,0x35,0x60, +0x03,0x37,0x80,0x03,0x39,0xa0,0x03,0x3b,0xc0,0x03,0x3d,0xe0,0x03,0x3f,0x00,0x04, +0x41,0x20,0x04,0x43,0x40,0x04,0x45,0x60,0x04,0x47,0x80,0x04,0x49,0xa0,0x04,0x4b, +0xc0,0x04,0x4d,0xe0,0x04,0x4f,0x00,0x05,0x51,0x20,0x05,0x53,0x40,0x05,0x55,0x60, +0x05,0x57,0x80,0x05,0x59,0xa0,0x05,0x5b,0xc0,0x05,0x5d,0xe0,0x05,0x5f,0x00,0x06, +0x61,0x20,0x06,0x63,0x40,0x06,0x65,0x60,0x06,0x67,0x80,0x06,0x69,0xa0,0x06,0x6b, +0xc0,0x06,0x6d,0xe0,0x06,0x6f,0x00,0x07,0x71,0x20,0x07,0x73,0x40,0x07,0x75,0x60, +0x07,0x77,0x80,0x07,0x79,0xa0,0x07,0x7b,0xc0,0x07,0x7d,0xe0,0x07,0x7f,0x00,0x08, +0x81,0x20,0x08,0x83,0x40,0x08,0x85,0x60,0x08,0x87,0x80,0x08,0x89,0xf0,0xff,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x45,0x52,0x53,0x4b,0x59,0x5f,0x39,0x58,0x20,0x20,0x20,0x08,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x54,0x41,0x52,0x41,0x4e,0x49,0x53,0x20,0x42,0x49,0x4e,0x24,0x00,0x3e,0x01,0xa3, +0x55,0x3d,0x55,0x3d,0x00,0x00,0x02,0xa3,0x55,0x3d,0x02,0x00,0x00,0x80,0x00,0x00, +0x46,0x49,0x52,0x4d,0x57,0x41,0x52,0x45,0x42,0x49,0x4e,0x24,0x00,0x3e,0x01,0xa3, +0x55,0x3d,0x55,0x3d,0x00,0x00,0x02,0xa3,0x55,0x3d,0x0a,0x00,0x00,0x00,0x08,0x00, +0x00,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x80,0x02,0x02,0x1f,0x00,0x00,0x00,0x46,0x72,0x53,0x6b,0x79,0x20,0x20,0x20, +0x54,0x61,0x72,0x61,0x6e,0x69,0x73,0x20,0x52,0x61,0x64,0x69,0x6f,0x20,0x20,0x20, +0x31,0x2e,0x30,0x30,0x00,0x80,0x02,0x02,0x1f,0x00,0x00,0x00,0x46,0x72,0x53,0x6b, +0x79,0x20,0x20,0x20,0x54,0x61,0x72,0x61,0x6e,0x69,0x73,0x20,0x52,0x61,0x64,0x69, +0x6f,0x20,0x20,0x20,0x31,0x2e,0x30,0x30,0x4d,0x53,0x43,0x20,0x49,0x6e,0x74,0x65, +0x72,0x66,0x61,0x63,0x65,0x00,0x4d,0x53,0x43,0x20,0x43,0x6f,0x6e,0x66,0x69,0x67, +0x00,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x31,0x42,0x00,0x46,0x72, +0x53,0x6b,0x79,0x00,0x46,0x72,0x53,0x6b,0x79,0x20,0x54,0x61,0x72,0x61,0x6e,0x69, +0x73,0x20,0x4d,0x61,0x73,0x73,0x20,0x53,0x74,0x6f,0x72,0x61,0x67,0x65,0x00,0x22, +0x2a,0x3a,0x3c,0x3e,0x3f,0x7c,0x7f,0x00,0x2b,0x2c,0x3b,0x3d,0x5b,0x5d,0x00,0x5c, +0x66,0x69,0x72,0x6d,0x77,0x61,0x72,0x65,0x5c,0x00,0x05,0x46,0x6c,0x61,0x73,0x68, +0x20,0x46,0x69,0x6c,0x65,0x00,0x4e,0x4f,0x54,0x20,0x41,0x20,0x56,0x41,0x4c,0x49, +0x44,0x20,0x46,0x49,0x52,0x4d,0x57,0x41,0x52,0x45,0x00,0x07,0x5b,0x45,0x58,0x49, +0x54,0x5d,0x00,0x03,0x59,0x45,0x53,0x0b,0x4e,0x4f,0x00,0x03,0x5b,0x4d,0x45,0x4e, +0x55,0x5d,0x0b,0x5b,0x45,0x58,0x49,0x54,0x5d,0x00,0x42,0x6f,0x6f,0x74,0x20,0x4c, +0x6f,0x61,0x64,0x65,0x72,0x00,0x0c,0x52,0x65,0x61,0x64,0x79,0x00,0x08,0x42,0x55, +0x53,0x59,0x00,0x5c,0x66,0x69,0x72,0x6d,0x77,0x61,0x72,0x65,0x00,0x2e,0x00,0x46, +0x6c,0x61,0x73,0x68,0x69,0x6e,0x67,0x00,0x46,0x6c,0x61,0x73,0x68,0x69,0x6e,0x67, +0x20,0x43,0x6f,0x6d,0x70,0x6c,0x65,0x74,0x65,0x00,0x05,0x4e,0x6f,0x20,0x46,0x69, +0x72,0x6d,0x77,0x61,0x72,0x65,0x00,0x00,0x00,0x87,0x93,0x03,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04,0x06,0x07,0x08,0x09,0x00,0x00,0x00,0x00, +0x01,0x02,0x03,0x04,0x01,0x02,0x03,0x04,0x06,0x07,0x08,0x09,0x70,0x77,0x00,0x20, +0x89,0x1f,0x00,0x20,0xd5,0x1e,0x00,0x20,0x8b,0x1e,0x00,0x20,0xfb,0x1d,0x00,0x20, +0x5d,0x1e,0x00,0x20,0xdf,0x1d,0x00,0x20,0xc9,0x1d,0x00,0x20,0x0b,0x1e,0x00,0x20, +0x19,0x1e,0x00,0x20,0x27,0x1e,0x00,0x20,0x3d,0x1e,0x00,0x20,0x09,0x02,0x20,0x00, +0x01,0x01,0x04,0xc0,0x32,0x09,0x04,0x00,0x00,0x02,0x08,0x06,0x50,0x05,0x07,0x05, +0x81,0x02,0x40,0x00,0x00,0x07,0x05,0x01,0x02,0x40,0x00,0x00,0x5d,0x2d,0x00,0x20, +0x41,0x2d,0x00,0x20,0x89,0x2c,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x7f,0x2c,0x00,0x20,0x75,0x2c,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x69,0x2c,0x00,0x20,0x12,0x01,0x00,0x02,0x00,0x00,0x00,0x40, +0x83,0x04,0x20,0x57,0x00,0x02,0x01,0x02,0x03,0x01,0x04,0x03,0x09,0x04,0x0a,0x06, +0x00,0x02,0x00,0x00,0x00,0x40,0x01,0x00,0x89,0x2d,0x00,0x20,0x95,0x2d,0x00,0x20, +0xf5,0x2d,0x00,0x20,0x11,0x2e,0x00,0x20,0xd9,0x2d,0x00,0x20,0xbd,0x2d,0x00,0x20, +0xa1,0x2d,0x00,0x20,0x04,0x08,0x00,0x38,0x38,0x7c,0xfe,0x0a,0x40,0x50,0xff,0xf7, +0xf3,0xf9,0x00,0x00,0xf9,0xf3,0xf7,0xff,0xff,0xff,0xff,0xff,0xfc,0xfc,0xff,0xff, +0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xcf,0x87,0x03, +0x49,0xcf,0xcf,0xcf,0xcf,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xff, +0xff,0xff,0xff,0xff,0x3f,0x3f,0xff,0xff,0xff,0xff,0xff,0xef,0xcf,0x9f,0x00,0x00, +0x9f,0xcf,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, +0x3f,0x7f,0xff,0x3f,0x8f,0xe3,0xf8,0xff,0xff,0xff,0xff,0xfe,0xfc,0xfe,0xff,0xff, +0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xcf,0xcf,0xcf, +0xcf,0x49,0x03,0x87,0xcf,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff, +0xff,0x7f,0x7f,0xff,0xff,0xff,0xff,0x7f,0x7f,0xff,0xff,0x9e,0x8c,0xc0,0xe1,0xe1, +0xc0,0x8c,0x9e,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x01,0x00, +0x0d,0x5b,0x00,0x20,0x0f,0x5b,0x00,0x20,0x11,0x5b,0x00,0x20,0x13,0x5b,0x00,0x20, +0x15,0x5b,0x00,0x20,0x17,0x5b,0x00,0x20,0x19,0x5b,0x00,0x20,0xf0,0x78,0x00,0x20, +0x25,0x5b,0x00,0x20,0x61,0x5b,0x00,0x20,0x47,0x5b,0x00,0x20,0x1d,0x5b,0x00,0x20, +0x25,0x5c,0x00,0x20,0x31,0x5d,0x00,0x20,0x21,0x5b,0x00,0x20,0x10,0x76,0x00,0x20, +0x01,0x00,0x00,0x00, + diff --git a/radio/src/loadboot.cpp b/radio/src/loadboot.cpp new file mode 100644 index 000000000..f69ab8d19 --- /dev/null +++ b/radio/src/loadboot.cpp @@ -0,0 +1,168 @@ +/**************************************************************************** +* Copyright (c) 2014 by Michael Blandford. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. Neither the name of the author nor the names of its contributors may +* be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +* SUCH DAMAGE. +* +**************************************************************************** +* Other Authors: + * - Andre Bernet + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer +* +****************************************************************************/ + + +#include +//#include "lcd.h" +#ifdef PCBSKY +#include "AT91SAM3S4.h" +#endif + +#ifdef PCBTARANIS +#include "stm32f2xx.h" +#include "stm32f2xx_gpio.h" + +void bwdt_reset() +{ + IWDG->KR = 0xAAAA ; // reload +} +#endif + +#ifdef PCBTARANIS +//#include "lcd.h" + +__attribute__ ((section(".bootrodata"), used)) +void _bootStart( void ) ; + + +__attribute__ ((section(".isr_boot_vector"), used)) +const uint32_t BootVectors[] = { + (uint32_t)&_estack, + (uint32_t)(void (*)(void))((unsigned long)&_bootStart) +} ; +#endif + +#ifdef PCBTARANIS +__attribute__ ((section(".bootrodata.*"), used)) +#endif + +#ifdef PCBSKY +__attribute__ ((section(".bootrodata"), used)) +#endif + +const uint8_t BootCode[] = { +#ifdef PCBTARANIS +#include "bootflashX.lbm" +#else + #ifdef REVX + #include "bootflash8.lbm" + #else + #include "bootflash4.lbm" + #endif +#endif +} ; + + +#ifdef PCBTARANIS + +__attribute__ ((section(".bootrodata"), used)) +static void run_application( void ) ; + +static void run_application() +{ + asm(" mov.w r1, #134217728"); // 0x8000000 + asm(" add.w r1, #32768"); // 0x8000 + + asm(" movw r0, #60680"); // 0xED08 + asm(" movt r0, #57344"); // 0xE000 + asm(" str r1, [r0, #0]"); // Set the VTOR + + asm("ldr r0, [r1, #0]"); // Stack pointer value + asm("msr msp, r0"); // Set it + asm("ldr r0, [r1, #4]"); // Reset address + asm("mov.w r1, #1"); + asm("orr r0, r1"); // Set lsbit + asm("bx r0"); // Execute application +} + +void _bootStart() +{ + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN ; // Enable portC clock + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOEEN ; // Enable portE clock + + GPIOC->PUPDR = 0x00000004 ; + GPIOE->PUPDR = 0x00000040 ; + + uint32_t i ; + for ( i = 0 ; i < 50000 ; i += 1 ) + { + bwdt_reset() ; + } + + if ( (GPIOE->IDR & 0x00000008 ) == 0 ) + { + if ( (GPIOC->IDR & 0x00000002 ) == 0 ) + { + // Bootloader needed + const uint8_t *src ; + uint8_t *dest ; + uint32_t size ; + + bwdt_reset() ; + size = sizeof(BootCode) ; + src = BootCode ; + dest = (uint8_t *)0x20000000 ; + + for ( ; size ; size -= 1 ) + { + *dest++ = *src++ ; + } + // Could check for a valid copy to RAM here + // Go execute bootloader + bwdt_reset() ; + + uint32_t address = *(uint32_t *)0x20000004 ; + + ((void (*)(void)) (address))() ; // Go execute the loaded application + + } + } + run_application() ; +} +#endif + + diff --git a/radio/src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c b/radio/src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c index e1d39a223..95a58c955 100644 --- a/radio/src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c +++ b/radio/src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c @@ -232,7 +232,9 @@ void SystemInit(void) #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +// SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +extern uint32_t g_pfnVectors ; + SCB->VTOR = (uint32_t) &g_pfnVectors ; /* Vector Table Relocation in Internal FLASH */ #endif } diff --git a/radio/src/targets/taranis/stm32_flash.ld b/radio/src/targets/taranis/stm32_flash.ld index a3279e20a..b478c181b 100644 --- a/radio/src/targets/taranis/stm32_flash.ld +++ b/radio/src/targets/taranis/stm32_flash.ld @@ -32,6 +32,9 @@ /* Entry Point */ ENTRY(Reset_Handler) +/* Highest address of the user mode stack */ +_estack = 0x20020000; /* end of 128K SRAM */ + /* Generate a link error if heap and stack don't fit into RAM */ _Min_Heap_Size = 0; /* required amount of heap */ _Min_Stack_Size = 0x200; /* required amount of stack */ @@ -52,6 +55,16 @@ SECTIONS /* The program code and other data goes into FLASH */ .text : { + FILL(0xFFFF) + + CREATE_OBJECT_SYMBOLS + + KEEP(*(.isr_boot_vector)) /* Startup code */ + *(.bootrodata) + *(.bootrodata.*) + + . = ALIGN(32768); /* Align the start of the main program */ + _stext = .; /* Provide the name for the start of this section */ . = ALIGN(4); KEEP(*(.isr_vector)) /* Startup code */ *(.text) /* .text sections (code) */ @@ -141,8 +154,6 @@ SECTIONS . = ALIGN(4); } >RAM - PROVIDE ( _estack = ORIGIN(RAM) + LENGTH(RAM) ); - /* MEMORY_bank1 section, code must be located here explicitly */ /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */ .memory_b1_text : From 229dfc19385647e61fc1b8ab8f898d9991049b9b Mon Sep 17 00:00:00 2001 From: Andre Bernet Date: Sat, 18 Jan 2014 20:00:31 +0100 Subject: [PATCH 002/285] Mike's bootloader sources + added as option, for Taranis only for now (not as clean as it could be, bootloader is always built even if not selected - didn't find how to nest ifs in makefile :\ ) (Issue #546) --- radio/bootloader/Fat12.cpp | 562 ++ radio/bootloader/MEDSdcard.c | 558 ++ radio/bootloader/aspi.cpp | 136 + radio/bootloader/board_lowlevel.c | 273 + radio/bootloader/boot.cpp | 1164 +++ radio/bootloader/bootsamEeprom.cpp | 604 ++ radio/bootloader/ccsbcs.c | 540 ++ radio/bootloader/core_cm3.c | 880 ++ radio/bootloader/crt.c | 147 + radio/bootloader/diskio.cpp | 1195 +++ radio/bootloader/driversboot.cpp | 206 + radio/bootloader/ff.cpp | 3822 +++++++++ radio/bootloader/ff_lfn.cpp | 113 + radio/bootloader/font.lbm | 8 + radio/bootloader/font_dblsize.lbm | 16 + radio/bootloader/i2c_ee.cpp | 416 + radio/bootloader/include/AT91SAM3S4.h | 7102 +++++++++++++++++ radio/bootloader/include/MSD.h | 233 + radio/bootloader/include/MSDDriver.h | 75 + radio/bootloader/include/MSDLun.h | 161 + radio/bootloader/include/Media.h | 288 + radio/bootloader/include/SBC.h | 653 ++ radio/bootloader/include/aspi.h | 37 + radio/bootloader/include/board.h | 714 ++ radio/bootloader/include/chip.h | 130 + radio/bootloader/include/core_cm3.h | 1818 +++++ radio/bootloader/include/debug.h | 25 + radio/bootloader/include/diskio.h | 179 + radio/bootloader/include/drivers.h | 74 + radio/bootloader/include/eeprom_rlc.h | 48 + radio/bootloader/include/ersky9x.h | 758 ++ radio/bootloader/include/ff.h | 575 ++ radio/bootloader/include/ffconf.h | 231 + radio/bootloader/include/file.h | 116 + radio/bootloader/include/gtime.h | 63 + radio/bootloader/include/hal.h | 254 + radio/bootloader/include/i2c_ee.h | 52 + radio/bootloader/include/integer.h | 70 + radio/bootloader/include/lcd.h | 122 + radio/bootloader/include/logicio.h | 123 + radio/bootloader/include/misc.h | 178 + radio/bootloader/include/myeeprom.h | 527 ++ radio/bootloader/include/radio.h | 64 + radio/bootloader/include/rtc.h | 71 + radio/bootloader/include/stm32f2xx.h | 6966 ++++++++++++++++ radio/bootloader/include/stm32f2xx_flash.h | 340 + radio/bootloader/include/stm32f2xx_gpio.h | 411 + radio/bootloader/include/stm32f2xx_rcc.h | 515 ++ radio/bootloader/include/stm32f2xx_rtc.h | 650 ++ radio/bootloader/include/stm32f2xx_spi.h | 526 ++ radio/bootloader/include/system_stm32f2xx.h | 105 + radio/bootloader/include/timers.h | 45 + radio/bootloader/include/usb_bsp.h | 102 + radio/bootloader/include/usb_conf.h | 175 + radio/bootloader/include/usb_core.h | 417 + radio/bootloader/include/usb_dcd.h | 163 + radio/bootloader/include/usb_dcd_int.h | 127 + radio/bootloader/include/usb_defines.h | 249 + radio/bootloader/include/usb_regs.h | 1188 +++ radio/bootloader/include/usbd_conf.h | 54 + radio/bootloader/include/usbd_core.h | 120 + radio/bootloader/include/usbd_def.h | 156 + radio/bootloader/include/usbd_desc.h | 120 + radio/bootloader/include/usbd_ioreq.h | 121 + radio/bootloader/include/usbd_msc_bot.h | 153 + radio/bootloader/include/usbd_msc_core.h | 77 + radio/bootloader/include/usbd_msc_data.h | 104 + radio/bootloader/include/usbd_msc_mem.h | 112 + radio/bootloader/include/usbd_msc_scsi.h | 195 + radio/bootloader/include/usbd_req.h | 108 + radio/bootloader/include/usbd_usr.h | 141 + radio/bootloader/lcd_driver.cpp | 314 + radio/bootloader/lcdboot.cpp | 618 ++ radio/bootloader/logicioboot.cpp | 457 ++ radio/bootloader/makefile | 378 + radio/bootloader/massstorage.cpp | 233 + radio/bootloader/misc.c | 249 + radio/bootloader/power.cpp | 117 + radio/bootloader/sam3s4c_boot.ld | 144 + radio/bootloader/sam3s8c_boot.ld | 144 + radio/bootloader/sdcard_driver.cpp | 71 + radio/bootloader/startup_stm32f2xx.s | 512 ++ radio/bootloader/stm32_ramBoot.ld | 153 + radio/bootloader/stm32f2xx_gpio.c | 566 ++ radio/bootloader/stm32f2xx_rcc.c | 1817 +++++ radio/bootloader/stm32f2xx_spi.c | 1185 +++ radio/bootloader/system_stm32f2xx.c | 559 ++ .../common/core/USBConfigurationDescriptor.c | 162 + .../common/core/USBConfigurationDescriptor.h | 150 + .../usb/common/core/USBDeviceDescriptor.h | 125 + .../core/USBDeviceQualifierDescriptor.h | 89 + .../usb/common/core/USBEndpointDescriptor.c | 109 + .../usb/common/core/USBEndpointDescriptor.h | 224 + .../usb/common/core/USBFeatureRequest.c | 70 + .../usb/common/core/USBFeatureRequest.h | 146 + .../usb/common/core/USBGenericDescriptor.c | 80 + .../usb/common/core/USBGenericDescriptor.h | 133 + .../usb/common/core/USBGenericRequest.c | 138 + .../usb/common/core/USBGenericRequest.h | 244 + .../usb/common/core/USBGetDescriptorRequest.c | 72 + .../usb/common/core/USBGetDescriptorRequest.h | 67 + .../core/USBInterfaceAssociationDescriptor.h | 86 + .../usb/common/core/USBInterfaceDescriptor.h | 87 + .../usb/common/core/USBInterfaceRequest.c | 69 + .../usb/common/core/USBInterfaceRequest.h | 68 + .../usb/common/core/USBIrqHandler.c | 62 + .../usb/common/core/USBIrqHandler.h | 52 + .../usb/common/core/USBSetAddressRequest.c | 56 + .../usb/common/core/USBSetAddressRequest.h | 60 + .../common/core/USBSetConfigurationRequest.c | 58 + .../common/core/USBSetConfigurationRequest.h | 61 + .../usb/common/core/USBStringDescriptor.h | 74 + .../common/massstorage/MSDeviceDescriptor.h | 73 + .../massstorage/MSInterfaceDescriptor.h | 75 + radio/bootloader/usb/device/core/USBD.h | 275 + .../usb/device/core/USBDCallbacks.c | 81 + .../usb/device/core/USBDCallbacks.h | 65 + radio/bootloader/usb/device/core/USBDDriver.c | 753 ++ radio/bootloader/usb/device/core/USBDDriver.h | 101 + .../usb/device/core/USBDDriverCallbacks.h | 61 + .../usb/device/core/USBDDriverDescriptors.h | 86 + radio/bootloader/usb/device/core/USBD_UDP.c | 1734 ++++ radio/bootloader/usb/device/massstorage/MSD.h | 233 + .../usb/device/massstorage/MSDDStateMachine.c | 609 ++ .../usb/device/massstorage/MSDDStateMachine.h | 264 + .../usb/device/massstorage/MSDDriver.c | 343 + .../usb/device/massstorage/MSDDriver.h | 75 + .../device/massstorage/MSDDriverDescriptors.c | 395 + .../device/massstorage/MSDDriverDescriptors.h | 83 + .../usb/device/massstorage/MSDIOFifo.h | 135 + .../usb/device/massstorage/MSDLun.c | 368 + .../usb/device/massstorage/MSDLun.h | 161 + radio/bootloader/usb/device/massstorage/SBC.h | 653 ++ .../usb/device/massstorage/SBCMethods.c | 1624 ++++ .../usb/device/massstorage/SBCMethods.h | 111 + radio/bootloader/usb/usb_bsp.c | 135 + radio/bootloader/usb/usb_core.c | 2162 +++++ radio/bootloader/usb/usb_dcd.c | 478 ++ radio/bootloader/usb/usb_dcd_int.c | 869 ++ radio/bootloader/usb/usbd_core.c | 506 ++ radio/bootloader/usb/usbd_desc.c | 223 + radio/bootloader/usb/usbd_ioreq.c | 244 + radio/bootloader/usb/usbd_msc_bot.c | 400 + radio/bootloader/usb/usbd_msc_core.c | 496 ++ radio/bootloader/usb/usbd_msc_data.c | 134 + radio/bootloader/usb/usbd_msc_scsi.c | 734 ++ radio/bootloader/usb/usbd_req.c | 868 ++ radio/bootloader/usbd_storage_msd.cpp | 817 ++ radio/bootloader/usbd_usr.cpp | 126 + radio/bootloader/vectors_sam3s.c | 198 + radio/bootloader/x9ddiskio.cpp | 1008 +++ radio/src/Makefile | 27 +- radio/src/bootflashX.lbm | 1939 ----- radio/src/loadboot.cpp | 63 +- radio/src/targets/sky9x/sam3s4c_flash.ld | 15 +- .../Source/Templates/system_stm32f2xx.c | 9 +- radio/src/targets/taranis/stm32_flash.ld | 15 +- radio/src/targets/taranis/stm32_flash_bl.ld | 176 + radio/util/bin2lbm.py | 23 + 159 files changed, 66903 insertions(+), 2000 deletions(-) create mode 100644 radio/bootloader/Fat12.cpp create mode 100644 radio/bootloader/MEDSdcard.c create mode 100644 radio/bootloader/aspi.cpp create mode 100644 radio/bootloader/board_lowlevel.c create mode 100644 radio/bootloader/boot.cpp create mode 100644 radio/bootloader/bootsamEeprom.cpp create mode 100644 radio/bootloader/ccsbcs.c create mode 100644 radio/bootloader/core_cm3.c create mode 100644 radio/bootloader/crt.c create mode 100644 radio/bootloader/diskio.cpp create mode 100644 radio/bootloader/driversboot.cpp create mode 100644 radio/bootloader/ff.cpp create mode 100644 radio/bootloader/ff_lfn.cpp create mode 100644 radio/bootloader/font.lbm create mode 100644 radio/bootloader/font_dblsize.lbm create mode 100644 radio/bootloader/i2c_ee.cpp create mode 100644 radio/bootloader/include/AT91SAM3S4.h create mode 100644 radio/bootloader/include/MSD.h create mode 100644 radio/bootloader/include/MSDDriver.h create mode 100644 radio/bootloader/include/MSDLun.h create mode 100644 radio/bootloader/include/Media.h create mode 100644 radio/bootloader/include/SBC.h create mode 100644 radio/bootloader/include/aspi.h create mode 100644 radio/bootloader/include/board.h create mode 100644 radio/bootloader/include/chip.h create mode 100644 radio/bootloader/include/core_cm3.h create mode 100644 radio/bootloader/include/debug.h create mode 100644 radio/bootloader/include/diskio.h create mode 100644 radio/bootloader/include/drivers.h create mode 100644 radio/bootloader/include/eeprom_rlc.h create mode 100644 radio/bootloader/include/ersky9x.h create mode 100644 radio/bootloader/include/ff.h create mode 100644 radio/bootloader/include/ffconf.h create mode 100644 radio/bootloader/include/file.h create mode 100644 radio/bootloader/include/gtime.h create mode 100644 radio/bootloader/include/hal.h create mode 100644 radio/bootloader/include/i2c_ee.h create mode 100644 radio/bootloader/include/integer.h create mode 100644 radio/bootloader/include/lcd.h create mode 100644 radio/bootloader/include/logicio.h create mode 100644 radio/bootloader/include/misc.h create mode 100644 radio/bootloader/include/myeeprom.h create mode 100644 radio/bootloader/include/radio.h create mode 100644 radio/bootloader/include/rtc.h create mode 100644 radio/bootloader/include/stm32f2xx.h create mode 100644 radio/bootloader/include/stm32f2xx_flash.h create mode 100644 radio/bootloader/include/stm32f2xx_gpio.h create mode 100644 radio/bootloader/include/stm32f2xx_rcc.h create mode 100644 radio/bootloader/include/stm32f2xx_rtc.h create mode 100644 radio/bootloader/include/stm32f2xx_spi.h create mode 100644 radio/bootloader/include/system_stm32f2xx.h create mode 100644 radio/bootloader/include/timers.h create mode 100644 radio/bootloader/include/usb_bsp.h create mode 100644 radio/bootloader/include/usb_conf.h create mode 100644 radio/bootloader/include/usb_core.h create mode 100644 radio/bootloader/include/usb_dcd.h create mode 100644 radio/bootloader/include/usb_dcd_int.h create mode 100644 radio/bootloader/include/usb_defines.h create mode 100644 radio/bootloader/include/usb_regs.h create mode 100644 radio/bootloader/include/usbd_conf.h create mode 100644 radio/bootloader/include/usbd_core.h create mode 100644 radio/bootloader/include/usbd_def.h create mode 100644 radio/bootloader/include/usbd_desc.h create mode 100644 radio/bootloader/include/usbd_ioreq.h create mode 100644 radio/bootloader/include/usbd_msc_bot.h create mode 100644 radio/bootloader/include/usbd_msc_core.h create mode 100644 radio/bootloader/include/usbd_msc_data.h create mode 100644 radio/bootloader/include/usbd_msc_mem.h create mode 100644 radio/bootloader/include/usbd_msc_scsi.h create mode 100644 radio/bootloader/include/usbd_req.h create mode 100644 radio/bootloader/include/usbd_usr.h create mode 100644 radio/bootloader/lcd_driver.cpp create mode 100644 radio/bootloader/lcdboot.cpp create mode 100644 radio/bootloader/logicioboot.cpp create mode 100644 radio/bootloader/makefile create mode 100644 radio/bootloader/massstorage.cpp create mode 100644 radio/bootloader/misc.c create mode 100644 radio/bootloader/power.cpp create mode 100644 radio/bootloader/sam3s4c_boot.ld create mode 100644 radio/bootloader/sam3s8c_boot.ld create mode 100644 radio/bootloader/sdcard_driver.cpp create mode 100644 radio/bootloader/startup_stm32f2xx.s create mode 100644 radio/bootloader/stm32_ramBoot.ld create mode 100644 radio/bootloader/stm32f2xx_gpio.c create mode 100644 radio/bootloader/stm32f2xx_rcc.c create mode 100644 radio/bootloader/stm32f2xx_spi.c create mode 100644 radio/bootloader/system_stm32f2xx.c create mode 100644 radio/bootloader/usb/common/core/USBConfigurationDescriptor.c create mode 100644 radio/bootloader/usb/common/core/USBConfigurationDescriptor.h create mode 100644 radio/bootloader/usb/common/core/USBDeviceDescriptor.h create mode 100644 radio/bootloader/usb/common/core/USBDeviceQualifierDescriptor.h create mode 100644 radio/bootloader/usb/common/core/USBEndpointDescriptor.c create mode 100644 radio/bootloader/usb/common/core/USBEndpointDescriptor.h create mode 100644 radio/bootloader/usb/common/core/USBFeatureRequest.c create mode 100644 radio/bootloader/usb/common/core/USBFeatureRequest.h create mode 100644 radio/bootloader/usb/common/core/USBGenericDescriptor.c create mode 100644 radio/bootloader/usb/common/core/USBGenericDescriptor.h create mode 100644 radio/bootloader/usb/common/core/USBGenericRequest.c create mode 100644 radio/bootloader/usb/common/core/USBGenericRequest.h create mode 100644 radio/bootloader/usb/common/core/USBGetDescriptorRequest.c create mode 100644 radio/bootloader/usb/common/core/USBGetDescriptorRequest.h create mode 100644 radio/bootloader/usb/common/core/USBInterfaceAssociationDescriptor.h create mode 100644 radio/bootloader/usb/common/core/USBInterfaceDescriptor.h create mode 100644 radio/bootloader/usb/common/core/USBInterfaceRequest.c create mode 100644 radio/bootloader/usb/common/core/USBInterfaceRequest.h create mode 100644 radio/bootloader/usb/common/core/USBIrqHandler.c create mode 100644 radio/bootloader/usb/common/core/USBIrqHandler.h create mode 100644 radio/bootloader/usb/common/core/USBSetAddressRequest.c create mode 100644 radio/bootloader/usb/common/core/USBSetAddressRequest.h create mode 100644 radio/bootloader/usb/common/core/USBSetConfigurationRequest.c create mode 100644 radio/bootloader/usb/common/core/USBSetConfigurationRequest.h create mode 100644 radio/bootloader/usb/common/core/USBStringDescriptor.h create mode 100644 radio/bootloader/usb/common/massstorage/MSDeviceDescriptor.h create mode 100644 radio/bootloader/usb/common/massstorage/MSInterfaceDescriptor.h create mode 100644 radio/bootloader/usb/device/core/USBD.h create mode 100644 radio/bootloader/usb/device/core/USBDCallbacks.c create mode 100644 radio/bootloader/usb/device/core/USBDCallbacks.h create mode 100644 radio/bootloader/usb/device/core/USBDDriver.c create mode 100644 radio/bootloader/usb/device/core/USBDDriver.h create mode 100644 radio/bootloader/usb/device/core/USBDDriverCallbacks.h create mode 100644 radio/bootloader/usb/device/core/USBDDriverDescriptors.h create mode 100644 radio/bootloader/usb/device/core/USBD_UDP.c create mode 100644 radio/bootloader/usb/device/massstorage/MSD.h create mode 100644 radio/bootloader/usb/device/massstorage/MSDDStateMachine.c create mode 100644 radio/bootloader/usb/device/massstorage/MSDDStateMachine.h create mode 100644 radio/bootloader/usb/device/massstorage/MSDDriver.c create mode 100644 radio/bootloader/usb/device/massstorage/MSDDriver.h create mode 100644 radio/bootloader/usb/device/massstorage/MSDDriverDescriptors.c create mode 100644 radio/bootloader/usb/device/massstorage/MSDDriverDescriptors.h create mode 100644 radio/bootloader/usb/device/massstorage/MSDIOFifo.h create mode 100644 radio/bootloader/usb/device/massstorage/MSDLun.c create mode 100644 radio/bootloader/usb/device/massstorage/MSDLun.h create mode 100644 radio/bootloader/usb/device/massstorage/SBC.h create mode 100644 radio/bootloader/usb/device/massstorage/SBCMethods.c create mode 100644 radio/bootloader/usb/device/massstorage/SBCMethods.h create mode 100644 radio/bootloader/usb/usb_bsp.c create mode 100644 radio/bootloader/usb/usb_core.c create mode 100644 radio/bootloader/usb/usb_dcd.c create mode 100644 radio/bootloader/usb/usb_dcd_int.c create mode 100644 radio/bootloader/usb/usbd_core.c create mode 100644 radio/bootloader/usb/usbd_desc.c create mode 100644 radio/bootloader/usb/usbd_ioreq.c create mode 100644 radio/bootloader/usb/usbd_msc_bot.c create mode 100644 radio/bootloader/usb/usbd_msc_core.c create mode 100644 radio/bootloader/usb/usbd_msc_data.c create mode 100644 radio/bootloader/usb/usbd_msc_scsi.c create mode 100644 radio/bootloader/usb/usbd_req.c create mode 100644 radio/bootloader/usbd_storage_msd.cpp create mode 100644 radio/bootloader/usbd_usr.cpp create mode 100644 radio/bootloader/vectors_sam3s.c create mode 100644 radio/bootloader/x9ddiskio.cpp delete mode 100644 radio/src/bootflashX.lbm create mode 100644 radio/src/targets/taranis/stm32_flash_bl.ld create mode 100644 radio/util/bin2lbm.py diff --git a/radio/bootloader/Fat12.cpp b/radio/bootloader/Fat12.cpp new file mode 100644 index 000000000..44d9b2e34 --- /dev/null +++ b/radio/bootloader/Fat12.cpp @@ -0,0 +1,562 @@ +/**************************************************************************** +* Copyright (c) 2013 by Michael Blandford. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* Original source of this code: Primoz Beltram +* http://sourceforge.net/projects/fat12ctrlface/files/ +* + * Other Authors (alphabetical order) + * - Andre Bernet + * - Andreas Weitl + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Gabriel Birkus + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer +* +****************************************************************************/ + + + +#include +#include "string.h" +//#include "myeeprom.h" +#include "file.h" + +#define BLOCKSIZE 512 + +//------------------------------------------------------------------------------ +/** + * FAT12 boot sector partition. + */ +const char g_FATboot[BLOCKSIZE] = { + // See http://en.wikipedia.org/wiki/FAT12#Boot_Sector + 0xeb, 0x3c, 0x90, // Jump instruction. + 0x39, 0x58, 0x20, 0x54, 0x45, 0x41, 0x4D, 0x00, // OEM Name + 0x00, 0x02, // Bytes per sector + 0x08, // Sectors per FS cluster. + 0x01, 0x00, // Reserved sector count + + 0x01, // Number of FATs + 0x10, 0x00, // Number of root directory entries +#ifdef REVX + 0x03, 0x08, // Total sectors = 2051 +#else + 0x03, 0x06, // Total sectors = 1539 +#endif + 0xf8, // Media descriptor + 0x01, 0x00, // Sectors per FAT table + 0x08, 0x00, // Sectors per track + 0x40, 0x00, // Number of heads + 0x00, 0x00, 0x00, 0x00, // Number of hidden sectors + + 0x00, 0x00, 0x00, 0x00, // Large number of sectors. + 0x00, // Physical drive number + 0x00, // Reserved + 0x29, // Extended boot signature + 0xCE, 0xFA, 0x5C, 0xD1, // Disk ID (serial number) + 0x56, 0x49, 0x52, 0x54, 0x46, 0x53, 0x20, 0x20, 0x20, 0x20, 0x20, // Volume label + 0x46, 0x41, 0x54, 0x31, 0x32, 0x20, 0x20, 0x20, // FAT file system type + 0x00, 0x00, // OS boot code + + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0xaa +}; + +const char g_FAT[BLOCKSIZE] = +{ +#ifdef REVX + 0xF8, 0xFF, 0xFF, 0x03, 0x40, 0x00, 0x05, 0x60, 0x00, 0x07, 0x80, 0x00, 0x09, 0xA0, 0x00, 0x0B, + 0xC0, 0x00, 0x0D, 0xE0, 0x00, 0x0F, 0x00, 0x01, 0x11, 0x20, 0x01, 0x13, 0x40, 0x01, 0x15, 0x60, + 0x01, 0x17, 0x80, 0x01, 0x19, 0xA0, 0x01, 0x1B, 0xC0, 0x01, 0x1D, 0xE0, 0x01, 0x1F, 0x00, 0x02, + 0x21, 0x20, 0x02, 0x23, 0x40, 0x02, 0x25, 0x60, 0x02, 0x27, 0x80, 0x02, 0x29, 0xA0, 0x02, 0x2B, + 0xC0, 0x02, 0x2D, 0xE0, 0x02, 0x2F, 0x00, 0x03, 0x31, 0x20, 0x03, 0x33, 0x40, 0x03, 0x35, 0x60, + 0x03, 0x37, 0x80, 0x03, 0x39, 0xA0, 0x03, 0x3B, 0xC0, 0x03, 0x3D, 0xE0, 0x03, 0x3F, 0x00, 0x04, + 0x41, 0x20, 0x04, 0x43, 0x40, 0x04, 0x45, 0x60, 0x04, 0x47, 0x80, 0x04, 0x49, 0xA0, 0x04, 0x4B, + 0xC0, 0x04, 0x4D, 0xE0, 0x04, 0x4F, 0x00, 0x05, 0x51, 0x20, 0x05, 0x53, 0x40, 0x05, 0x55, 0x60, + 0x05, 0x57, 0x80, 0x05, 0x59, 0xA0, 0x05, 0x5B, 0xC0, 0x05, 0x5D, 0xE0, 0x05, 0x5F, 0x00, 0x06, + 0x61, 0x20, 0x06, 0x63, 0x40, 0x06, 0x65, 0x60, 0x06, 0x67, 0x80, 0x06, 0x69, 0xA0, 0x06, 0x6B, + 0xC0, 0x06, 0x6D, 0xE0, 0x06, 0x6F, 0x00, 0x07, 0x71, 0x20, 0x07, 0x73, 0x40, 0x07, 0x75, 0x60, + 0x07, 0x77, 0x80, 0x07, 0x79, 0xA0, 0x07, 0x7B, 0xC0, 0x07, 0x7D, 0xE0, 0x07, 0x7F, 0x00, 0x08, + 0x81, 0xF0, 0xFF, 0x83, 0x40, 0x08, 0x85, 0x60, 0x08, 0x87, 0x80, 0x08, 0x89, 0xA0, 0x08, 0x8B, + 0xC0, 0x08, 0x8D, 0xE0, 0x08, 0x8F, 0x00, 0x09, 0x91, 0x20, 0x09, 0x93, 0x40, 0x09, 0x95, 0x60, + 0x09, 0x97, 0x80, 0x09, 0x99, 0xA0, 0x09, 0x9B, 0xC0, 0x09, 0x9D, 0xE0, 0x09, 0x9F, 0x00, 0x0A, + 0xA1, 0x20, 0x0A, 0xA3, 0x40, 0x0A, 0xA5, 0x60, 0x0A, 0xA7, 0x80, 0x0A, 0xA9, 0xA0, 0x0A, 0xAB, + 0xC0, 0x0A, 0xAD, 0xE0, 0x0A, 0xAF, 0x00, 0x0B, 0xB1, 0x20, 0x0B, 0xB3, 0x40, 0x0B, 0xB5, 0x60, + 0x0B, 0xB7, 0x80, 0x0B, 0xB9, 0xA0, 0x0B, 0xBB, 0xC0, 0x0B, 0xBD, 0xE0, 0x0B, 0xBF, 0x00, 0x0C, + 0xC1, 0x20, 0x0C, 0xC3, 0x40, 0x0C, 0xC5, 0x60, 0x0C, 0xC7, 0x80, 0x0C, 0xC9, 0xA0, 0x0C, 0xCB, + 0xC0, 0x0C, 0xCD, 0xE0, 0x0C, 0xCF, 0x00, 0x0D, 0xD1, 0x20, 0x0D, 0xD3, 0x40, 0x0D, 0xD5, 0x60, + 0x0D, 0xD7, 0x80, 0x0D, 0xD9, 0xA0, 0x0D, 0xDB, 0xC0, 0x0D, 0xDD, 0xE0, 0x0D, 0xDF, 0x00, 0x0E, + 0xE1, 0x20, 0x0E, 0xE3, 0x40, 0x0E, 0xE5, 0x60, 0x0E, 0xE7, 0x80, 0x0E, 0xE9, 0xA0, 0x0E, 0xEB, + 0xC0, 0x0E, 0xED, 0xE0, 0x0E, 0xEF, 0x00, 0x0F, 0xF1, 0x20, 0x0F, 0xF3, 0x40, 0x0F, 0xF5, 0x60, + 0x0F, 0xF7, 0x80, 0x0F, 0xF9, 0xA0, 0x0F, 0xFB, 0xC0, 0x0F, 0xFD, 0xE0, 0x0F, 0xFF, 0x00, 0x10, + 0x01, 0xF1, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +#else + 0xF8, 0xFF, 0xFF, 0x03, 0x40, 0x00, 0x05, 0x60, 0x00, 0x07, 0x80, 0x00, 0x09, 0xA0, 0x00, 0x0B, + 0xC0, 0x00, 0x0D, 0xE0, 0x00, 0x0F, 0x00, 0x01, 0x11, 0x20, 0x01, 0x13, 0x40, 0x01, 0x15, 0x60, + 0x01, 0x17, 0x80, 0x01, 0x19, 0xA0, 0x01, 0x1B, 0xC0, 0x01, 0x1D, 0xE0, 0x01, 0x1F, 0x00, 0x02, + 0x21, 0x20, 0x02, 0x23, 0x40, 0x02, 0x25, 0x60, 0x02, 0x27, 0x80, 0x02, 0x29, 0xA0, 0x02, 0x2B, + 0xC0, 0x02, 0x2D, 0xE0, 0x02, 0x2F, 0x00, 0x03, 0x31, 0x20, 0x03, 0x33, 0x40, 0x03, 0x35, 0x60, + 0x03, 0x37, 0x80, 0x03, 0x39, 0xA0, 0x03, 0x3B, 0xC0, 0x03, 0x3D, 0xE0, 0x03, 0x3F, 0x00, 0x04, + 0x41, 0x20, 0x04, 0x43, 0x40, 0x04, 0x45, 0x60, 0x04, 0x47, 0x80, 0x04, 0x49, 0xA0, 0x04, 0x4B, + 0xC0, 0x04, 0x4D, 0xE0, 0x04, 0x4F, 0x00, 0x05, 0x51, 0x20, 0x05, 0x53, 0x40, 0x05, 0x55, 0x60, + 0x05, 0x57, 0x80, 0x05, 0x59, 0xA0, 0x05, 0x5B, 0xC0, 0x05, 0x5D, 0xE0, 0x05, 0x5F, 0x00, 0x06, + 0x61, 0x20, 0x06, 0x63, 0x40, 0x06, 0x65, 0x60, 0x06, 0x67, 0x80, 0x06, 0x69, 0xA0, 0x06, 0x6B, + 0xC0, 0x06, 0x6D, 0xE0, 0x06, 0x6F, 0x00, 0x07, 0x71, 0x20, 0x07, 0x73, 0x40, 0x07, 0x75, 0x60, + 0x07, 0x77, 0x80, 0x07, 0x79, 0xA0, 0x07, 0x7B, 0xC0, 0x07, 0x7D, 0xE0, 0x07, 0x7F, 0x00, 0x08, + 0x81, 0xF0, 0xFF, 0x83, 0x40, 0x08, 0x85, 0x60, 0x08, 0x87, 0x80, 0x08, 0x89, 0xA0, 0x08, 0x8B, + 0xC0, 0x08, 0x8D, 0xE0, 0x08, 0x8F, 0x00, 0x09, 0x91, 0x20, 0x09, 0x93, 0x40, 0x09, 0x95, 0x60, + 0x09, 0x97, 0x80, 0x09, 0x99, 0xA0, 0x09, 0x9B, 0xC0, 0x09, 0x9D, 0xE0, 0x09, 0x9F, 0x00, 0x0A, + 0xA1, 0x20, 0x0A, 0xA3, 0x40, 0x0A, 0xA5, 0x60, 0x0A, 0xA7, 0x80, 0x0A, 0xA9, 0xA0, 0x0A, 0xAB, + 0xC0, 0x0A, 0xAD, 0xE0, 0x0A, 0xAF, 0x00, 0x0B, 0xB1, 0x20, 0x0B, 0xB3, 0x40, 0x0B, 0xB5, 0x60, + 0x0B, 0xB7, 0x80, 0x0B, 0xB9, 0xA0, 0x0B, 0xBB, 0xC0, 0x0B, 0xBD, 0xE0, 0x0B, 0xBF, 0x00, 0x0C, + 0xC1, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +#endif +}; + + +// File Attributes +// 0 0x01 Read Only. +// 1 0x02 Hidden. +// 2 0x04 System. +// 3 0x08 Volume Label. +// 4 0x10 Subdirectory. +// 5 0x20 Archive. +// 6 0x40 Device. +// 7 0x80 Reserved. + +typedef struct +{ + uint8_t name[8]; + uint8_t ext[3]; + uint8_t attribute; + uint8_t reserved; + uint8_t create_time_ms; + uint16_t create_time; + uint16_t create_date; + uint16_t access_date; + uint16_t ea_index; + uint16_t modify_time; + uint16_t modify_date; + uint16_t start_cluster; + uint32_t file_size; +} FATDirEntry_t; + +// First 16 FAT root directory entries (1 sector) +const FATDirEntry_t g_DIRroot[16] = +{ + { + { 'E', 'R', 'S', 'K', 'Y', '_', '9', 'X'}, + { ' ', ' ', ' '}, + 0x08, // Volume + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + }, + { + { 'E', 'R', 'S', 'K', 'Y', '9', 'X', ' '}, + { 'B', 'I', 'N'}, + 0x26, // Archive, hidden, system, read-only + 0x00, + 0x3E, + 0xA301, + 0x3D55, + 0x3D55, + 0x0000, + 0xA302, + 0x3D55, + 0x0002, + 0x00080000 + }, + { + { 'F', 'I', 'R', 'M', 'W', 'A', 'R', 'E'}, + { 'B', 'I', 'N'}, + 0x26, + 0x00, + 0x3E, + 0xA301, + 0x3D55, + 0x3D55, + 0x0000, + 0xA302, + 0x3D55, + 0x0082, +#ifdef REVX + 0x00080000 +#else + 0x00040000 +#endif + }, + { + { 'A', '2', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x27, + 0x00, + 0x3E, + 0xA301, + 0x3D55, + 0x3D55, + 0x0000, + 0xA302, + 0x3D55, + 0x0000, + 0x00000000 + }, + { + { 'A', '3', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x27, + 0x00, + 0x3E, + 0xA301, + 0x3D55, + 0x3D55, + 0x0000, + 0xA302, + 0x3D55, + 0x0000, + 0x00000000 + }, + { + { 'A', '4', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x27, + 0x00, + 0x3E, + 0xA301, + 0x3D55, + 0x3D55, + 0x0000, + 0xA302, + 0x3D55, + 0x0000, + 0x00000000 + }, + { + { 'A', '5', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x27, + 0x00, + 0x3E, + 0xA301, + 0x3D55, + 0x3D55, + 0x0000, + 0xA302, + 0x3D55, + 0x0000, + 0x00000000 + }, + { + { 'A', '6', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x27, + 0x00, + 0x3E, + 0xA301, + 0x3D55, + 0x3D55, + 0x0000, + 0xA302, + 0x3D55, + 0x0000, + 0x00000000 + }, + { + { 'A', '7', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x27, + 0x00, + 0x3E, + 0xA301, + 0x3D55, + 0x3D55, + 0x0000, + 0xA302, + 0x3D55, + 0x0000, + 0x00000000 + }, + { + { 'A', '8', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x27, + 0x00, + 0x3E, + 0xA301, + 0x3D55, + 0x3D55, + 0x0000, + 0xA302, + 0x3D55, + 0x0000, + 0x00000000 + }, + { + { 'A', '9', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x27, + 0x00, + 0x3E, + 0xA301, + 0x3D55, + 0x3D55, + 0x0000, + 0xA302, + 0x3D55, + 0x0000, + 0x00000000 + }, + { + { 'A', 'A', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x27, + 0x00, + 0x3E, + 0xA301, + 0x3D55, + 0x3D55, + 0x0000, + 0xA302, + 0x3D55, + 0x0000, + 0x00000000 + }, + { + { 'A', 'B', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x27, + 0x00, + 0x3E, + 0xA301, + 0x3D55, + 0x3D55, + 0x0000, + 0xA302, + 0x3D55, + 0x0000, + 0x00000000 + }, + { + { 'A', 'C', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x27, + 0x00, + 0x3E, + 0xA301, + 0x3D55, + 0x3D55, + 0x0000, + 0xA302, + 0x3D55, + 0x0000, + 0x00000000 + }, + { + { '\0', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x00, + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + }, +// { +// { 'A', 'E', ' ', ' ', ' ', ' ', ' ', ' '}, +// { ' ', ' ', ' '}, +// 0x27, +// 0x00, +// 0x3E, +// 0xA301, +// 0x3D55, +// 0x3D55, +// 0x0000, +// 0xA302, +// 0x3D55, +// 0x0000, +// 0x00000000 +// } + { + { '\0', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x00, + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + } +}; + + +int fat12Read( uint8_t *buffer, uint16_t sector ) +{ + if (sector == 0) + { + memcpy( buffer, g_FATboot, BLOCKSIZE ) ; + return TRUE; + } + else if ( sector == 1/*Reserved sector count*/) + { + // FAT table. + memcpy( buffer, g_FAT, BLOCKSIZE); + return TRUE; + } + else if ( sector == 2) + { + // Directory + memcpy( buffer, g_DIRroot, BLOCKSIZE ) ; + return TRUE; + } + + sector -= 3 ; + if ( sector < 1024 ) + { + ee32_read_512( sector, buffer ) ; + } +#ifdef REVX + else if ( sector < 2048 ) +#else + else if ( sector < 1536 ) +#endif + { + uint32_t address ; + address = sector - 1024 ; + address *= 512 ; + address += 0x00400000 ; + memcpy( buffer, (uint8_t *)address, BLOCKSIZE ) ; + } + else + { + memset( buffer, 0, BLOCKSIZE ) ; + } + return TRUE; +} + + +uint32_t program( uint32_t *address, uint32_t *buffer ) ; // size is 256 bytes +uint32_t ee32_write( const uint8_t *buffer, uint32_t sector, uint32_t count ) ; + +int fat12Write( const uint8_t *buffer, uint16_t sector, uint32_t count ) +{ + // TO DO, actually write to the EEPROM + if ( sector >= 3 ) + { + sector -= 3 ; + // Look for a 4K block boundary, writing 4K+ + if ( sector < 1024 ) + { + ee32_write( buffer, sector, count ) ; + } +#ifdef REVX + else if ( sector < 2048 ) +#else + else if ( sector < 1536 ) +#endif + { + // FIRMWARE + uint32_t address ; + address = sector - 1024 ; + address *= 512 ; + address += 0x00400000 ; + // Write to flash + uint32_t i ; + while ( count ) + { + for ( i = 0 ; i < 2 ; i += 1 ) + { + if ( address >= 0x00408000 ) // Protect bootloader + { + program( (uint32_t *)address, (uint32_t *) buffer ) ; // size is 256 bytes + } + address += 256 ; + buffer += 256 ; + } + count -= 1 ; + } + } + } + return TRUE; +} + + diff --git a/radio/bootloader/MEDSdcard.c b/radio/bootloader/MEDSdcard.c new file mode 100644 index 000000000..e030b5571 --- /dev/null +++ b/radio/bootloader/MEDSdcard.c @@ -0,0 +1,558 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include +#include "Media.h" +#include "debug.h" +#include "board.h" +#include "diskio.h" + +//------------------------------------------------------------------------------ +// Constants +//------------------------------------------------------------------------------ + +/// Number of SD Slots +#define NUM_SD_SLOTS 1 +#define SD_BLOCK_SIZE 512 + +//------------------------------------------------------------------------------ +/// Checks if the device is write protected. +/// \return 1 if protected. +//------------------------------------------------------------------------------ +#if 0 +static unsigned char CardIsProtected(unsigned char slot) +{ + if (slot == 0) { + #ifdef BOARD_SD_PIN_WP + PIO_Configure(&pinMciWriteProtect, 1); + return (PIO_Get(&pinMciWriteProtect) != 0); + #else + return 0; + #endif + } + + if (slot == 1) { + #ifdef BOARD_SD_MCI1_PIN_WP + PIO_Configure(&pinMciWriteProtect1, 1); + return (PIO_Get(&pinMciWriteProtect1) != 0); + #else + return 0; + #endif + } + + return 0; +} +#endif + +//------------------------------------------------------------------------------ +/// Configure the PIO for SD +//------------------------------------------------------------------------------ +#if 0 +static void ConfigurePIO(unsigned char mciID) +{ + #ifdef BOARD_SD_PINS + const Pin pinSd0[] = {BOARD_SD_PINS}; + #endif + + #ifdef BOARD_SD_MCI1_PINS + const Pin pinSd1[] = {BOARD_SD_MCI1_PINS}; + #endif + + if(mciID == 0) { + #ifdef BOARD_SD_PINS + PIO_Configure(pinSd0, PIO_LISTSIZE(pinSd0)); + #endif + } else { + #ifdef BOARD_SD_MCI1_PINS + PIO_Configure(pinSd1, PIO_LISTSIZE(pinSd1)); + #endif + } +} +#endif + +//------------------------------------------------------------------------------ +//! \brief Reads a specified amount of data from a SDCARD memory +//! \param media Pointer to a Media instance +//! \param address Address of the data to read +//! \param data Pointer to the buffer in which to store the retrieved +//! data +//! \param length Length of the buffer +//! \param callback Optional pointer to a callback function to invoke when +//! the operation is finished +//! \param argument Optional pointer to an argument for the callback +//! \return Operation result code +//------------------------------------------------------------------------------ +static unsigned char MEDSdcard_Read(Media *media, + unsigned int address, + void *data, + unsigned int length, + MediaCallback callback, + void *argument) +{ + TRACE_DEBUG("MEDSdcard_Read(address=%d length=%d)\n\r", address, length); + + // Check that the media is ready + if (media->state != MED_STATE_READY) { + + TRACE_INFO("Media busy\n\r"); + return MED_STATUS_BUSY; + } + + // Check that the data to read is not too big + if ((length + address) > media->size) { + + TRACE_WARNING("MEDSdcard_Read: Data too big: %d, %d\n\r", + (int)length, (int)address); + return MED_STATUS_ERROR; + } + + // Enter Busy state + media->state = MED_STATE_BUSY; + + disk_read (0, data, address, length); + + // Leave the Busy state + media->state = MED_STATE_READY; + + // Invoke callback + if (callback != 0) { + + callback(argument, MED_STATUS_SUCCESS, 0, 0); + } + + return MED_STATUS_SUCCESS; +} + +static unsigned char Eeprom_Read(Media *media, + unsigned int address, + void *data, + unsigned int length, + MediaCallback callback, + void *argument) +{ + if (media->state != MED_STATE_READY) { + + TRACE_INFO("Media busy\n\r"); + return MED_STATUS_BUSY; + } + // Check that the data to read is not too big + if ((length + address) > media->size) { + + TRACE_WARNING("Eeprom_Read: Data too big: %d, %d\n\r", + (int)length, (int)address); + return MED_STATUS_ERROR; + } + + // Enter Busy state + media->state = MED_STATE_BUSY; + + disk_read (1, data, address, length); + + // Leave the Busy state + media->state = MED_STATE_READY; + + // Invoke callback + if (callback != 0) { + + callback(argument, MED_STATUS_SUCCESS, 0, 0); + } + + return MED_STATUS_SUCCESS; + +} +//------------------------------------------------------------------------------ +//! \brief Writes data on a SDRAM media +//! \param media Pointer to a Media instance +//! \param address Address at which to write +//! \param data Pointer to the data to write +//! \param length Size of the data buffer +//! \param callback Optional pointer to a callback function to invoke when +//! the write operation terminates +//! \param argument Optional argument for the callback function +//! \return Operation result code +//! \see Media +//! \see MediaCallback +//------------------------------------------------------------------------------ +static unsigned char MEDSdcard_Write(Media *media, + unsigned int address, + void *data, + unsigned int length, + MediaCallback callback, + void *argument) +{ + + TRACE_DEBUG("MEDSdcard_Write(address=%d length=%d)\n\r", address, length); + + // Check that the media if ready + if (media->state != MED_STATE_READY) { + + TRACE_WARNING("MEDSdcard_Write: Media is busy\n\r"); + return MED_STATUS_BUSY; + } + + // Check that the data to write is not too big + if ((length + address) > media->size) { + + TRACE_WARNING("MEDSdcard_Write: Data too big\n\r"); + return MED_STATUS_ERROR; + } + + // Put the media in Busy state + media->state = MED_STATE_BUSY; + + disk_write(0, data, address, length); + + // Leave the Busy state + media->state = MED_STATE_READY; + + // Invoke the callback if it exists + if (callback != 0) { + + callback(argument, MED_STATUS_SUCCESS, 0, 0); + } + + return MED_STATUS_SUCCESS; +} + +static unsigned char Eeprom_Write(Media *media, + unsigned int address, + void *data, + unsigned int length, + MediaCallback callback, + void *argument) +{ + + TRACE_DEBUG("Eeprom_Write(address=%d length=%d)\n\r", address, length); + + // Check that the media if ready + if (media->state != MED_STATE_READY) { + + TRACE_WARNING("Eeprom_Write: Media is busy\n\r"); + return MED_STATUS_BUSY; + } + + // Check that the data to write is not too big + if ((length + address) > media->size) { + + TRACE_WARNING("Eeprom_Write: Data too big\n\r"); + return MED_STATUS_ERROR; + } + + // Put the media in Busy state + media->state = MED_STATE_BUSY; + + disk_write(1, data, address, length); + + // Leave the Busy state + media->state = MED_STATE_READY; + + // Invoke the callback if it exists + if (callback != 0) { + + callback(argument, MED_STATUS_SUCCESS, 0, 0); + } + + return MED_STATUS_SUCCESS; +} + +//------------------------------------------------------------------------------ +/// Initializes a Media instance and the associated physical interface +/// \param media Pointer to the Media instance to initialize +/// \return 1 if success. +//------------------------------------------------------------------------------ + +unsigned char MEDSdcard_Initialize(Media *media, unsigned char mciID) +{ + TRACE_INFO("MEDSdcard init\n\r"); + + // Initialize SDcard + //-------------------------------------------------------------------------- + + if ( !CardIsConnected( ) ) + { + return 0; + } + + // Configure SDcard pins + // ConfigurePIO(mciID); + +#if defined(MCI2_INTERFACE) + // DMAD_Initialize(BOARD_MCI_DMA_CHANNEL, DMAD_NO_DEFAULT_IT); +#endif + +#if 0 + // Initialize the MCI driver + if ( mciID == 0 ) + { + IRQ_ConfigureIT(BOARD_SD_MCI_ID, 1, MCI0_IrqHandler); + MCI_Init(mciDrv, BOARD_SD_MCI_BASE, BOARD_SD_MCI_ID, BOARD_SD_SLOT, BOARD_MCK ); + IRQ_EnableIT(BOARD_SD_MCI_ID); + } + else + { + #ifdef BOARD_SD_MCI1_ID + IRQ_ConfigureIT(BOARD_SD_MCI1_ID, 1, MCI0_IrqHandler); + MCI_Init(mciDrv, BOARD_SD_MCI1_BASE, BOARD_SD_MCI1_ID, BOARD_SD_MCI1_SLOT, BOARD_MCK ); + IRQ_EnableIT(BOARD_SD_MCI1_ID); + #else + TRACE_ERROR("SD/MMC card initialization failed (MCI1 not supported)\n\r"); + #endif + } +#if MCI_BUSY_CHECK_FIX && defined(BOARD_SD_DAT0) + MCI_SetBusyFix(mciDrv, &pinSdDAT0); +#endif + + // Initialize the SD card driver + if (SD_Init(sdDrv, (SdDriver *)mciDrv)) + { + TRACE_ERROR("SD/MMC card initialization failed\n\r"); + return 0; + } + else + { + //SD_DisplayRegisterCSD(&sdDrv); + TRACE_INFO("SD/MMC card initialization successful\n\r"); + TRACE_INFO("Card size: %d MB\n\r", (int)(MMC_GetTotalSizeKB(sdDrv)/1024)); + } + MCI_SetSpeed(mciDrv, sdDrv->transSpeed, sdDrv->transSpeed, BOARD_MCK); +#endif + + + media->write = MEDSdcard_Write; + media->read = MEDSdcard_Read; + media->lock = 0; + media->unlock = 0; + media->handler = 0; + media->flush = 0; + + media->blockSize = SD_BLOCK_SIZE; + media->baseAddress = 0; + + media->size = SD_GET_BLOCKNR(); + + media->mappedRD = 0; + media->mappedWR = 0; + media->protected = 0; // TODO BSS CardIsProtected(mciID); + media->removable = 1; + + media->state = MED_STATE_READY; + + media->transfer.data = 0; + media->transfer.address = 0; + media->transfer.length = 0; + media->transfer.callback = 0; + media->transfer.argument = 0; + + return 1; +} + +unsigned char EEPROM_Initialize(Media *media, unsigned char mciID) +{ + media->write = Eeprom_Write; + media->read = Eeprom_Read; + media->lock = 0; + media->unlock = 0; + media->handler = 0; + media->flush = 0; + + media->blockSize = 512 ; + media->baseAddress = 0; + +#ifdef REVX + media->size = 2051 ; +#else + media->size = 1539 ; +#endif + + media->mappedRD = 0; + media->mappedWR = 0; + media->protected = 0; // TODO BSS CardIsProtected(mciID); + media->removable = 1; + + media->state = MED_STATE_READY; + + media->transfer.data = 0; + media->transfer.address = 0; + media->transfer.length = 0; + media->transfer.callback = 0; + media->transfer.argument = 0; + + return 1; + +} + +#if 0 +//------------------------------------------------------------------------------ +/// Initializes a Media instance and the associated physical interface +/// \param media Pointer to the Media instance to initialize +/// \return 1 if success. +//------------------------------------------------------------------------------ +unsigned char MEDSdusb_Initialize(Media *media, unsigned char mciID) +{ + TRACE_INFO("MEDSdusb init\n\r"); + + // Initialize SDcard + //-------------------------------------------------------------------------- + + if (!CardIsConnected()) return 0; +#if 0 + // Configure SDcard pins + ConfigurePIO(mciID); + +#if defined(MCI2_INTERFACE) + DMAD_Initialize(BOARD_MCI_DMA_CHANNEL, DMAD_NO_DEFAULT_IT); +#endif + // Initialize the MCI driver + if ( mciID == 0 ) + { + IRQ_ConfigureIT(BOARD_SD_MCI_ID, 1, MCI0_IrqHandler); + MCI_Init(mciDrv, BOARD_SD_MCI_BASE, BOARD_SD_MCI_ID, BOARD_SD_SLOT, BOARD_MCK ); + IRQ_EnableIT(BOARD_SD_MCI_ID); + } + else + { +#ifdef BOARD_SD_MCI1_ID + IRQ_ConfigureIT(BOARD_SD_MCI1_ID, 1, MCI0_IrqHandler); + MCI_Init(mciDrv, BOARD_SD_MCI1_BASE, BOARD_SD_MCI1_ID, BOARD_SD_SLOT, BOARD_MCK ); + IRQ_EnableIT(BOARD_SD_MCI1_ID); +#else + TRACE_ERROR("SD/MMC card initialization failed (MCI1 not supported)\n\r"); +#endif + } +#if MCI_BUSY_CHECK_FIX && defined(BOARD_SD_DAT0) + MCI_SetBusyFix(mciDrv, &pinSdDAT0); +#endif + + // Initialize the SD card driver + if (SD_Init(sdDrv, (SdDriver *)mciDrv)) + { + TRACE_ERROR("SD/MMC card initialization failed\n\r"); + return 0; + } + else + { + TRACE_INFO("SD/MMC card initialization successful\n\r"); + TRACE_INFO("Card size: %d MB\n\r", (int)(MMC_GetTotalSizeKB(sdDrv)/1024)); + } + MCI_SetSpeed(mciDrv, sdDrv->transSpeed, sdDrv->transSpeed, BOARD_MCK); +#endif + // Initialize media fields + //-------------------------------------------------------------------------- + //media->interface = sdDrv; + media->write = MEDSdusb_Write; + media->read = MEDSdusb_Read; + media->lock = 0; + media->unlock = 0; + media->handler = 0; + media->flush = 0; + + media->blockSize = SD_BLOCK_SIZE; + media->baseAddress = 0; + media->size = 1024*1024; // TODO BSS SD_TOTAL_BLOCK(sdDrv); + + media->mappedRD = 0; + media->mappedWR = 0; + media->protectedd = false; // TODO BSS CardIsProtected(mciID); + media->removable = 1; + + media->state = MED_STATE_READY; + + media->transfer.data = 0; + media->transfer.address = 0; + media->transfer.length = 0; + media->transfer.callback = 0; + media->transfer.argument = 0; + + return 1; +} +#endif + +#if 0 +//------------------------------------------------------------------------------ +/// erase all the Sdcard +/// \param media Pointer to the Media instance to initialize +//------------------------------------------------------------------------------ +void MEDSdcard_EraseAll(Media *media) +{ + unsigned char buffer[SD_BLOCK_SIZE]; + unsigned int block; + unsigned int multiBlock = 1; // change buffer size for multiblocks + unsigned char error; + + TRACE_INFO("MEDSdcard Erase All ...\n\r"); + + // Clear the block buffer + memset(buffer, 0, media->blockSize * multiBlock); + + for (block=0; + block < (SD_TOTAL_BLOCK((SdCard*)media->interface)-multiBlock); + block += multiBlock) + { + // TODO BSS error = SD_WriteBlock((SdCard*)media->interface, block, multiBlock, buffer); + assert( !error ); /* "\n\r-F- Failed to write block (%d) #%u\n\r", error, block */ + } +} +#endif + +//------------------------------------------------------------------------------ +/// erase block +/// \param media Pointer to the Media instance to initialize +/// \param block to erase +//------------------------------------------------------------------------------ +#if 0 +void MEDSdcard_EraseBlock(Media *media, unsigned int block) +{ + unsigned char buffer[SD_BLOCK_SIZE]; + unsigned char error; + + // Clear the block buffer + memset(buffer, 0, media->blockSize); + + // TODO BSS error = SD_WriteBlock((SdCard*)media->interface, block, 1, buffer); + assert( !error ) ; /* "\n\r-F- Failed to write block (%d) #%u\n\r", error, block */ +} +#endif +//------------------------------------------------------------------------------ +/// Get driver pointer +//------------------------------------------------------------------------------ +#if 0 +SdCard* MEDSdcard_GetDriver( unsigned int slot ) +{ + if (slot >= NUM_SD_SLOTS) + { + return 0; + } + + return &sdDrv[slot]; +} +#endif diff --git a/radio/bootloader/aspi.cpp b/radio/bootloader/aspi.cpp new file mode 100644 index 000000000..8de383af0 --- /dev/null +++ b/radio/bootloader/aspi.cpp @@ -0,0 +1,136 @@ +/** + ****************************************************************************** + * @file Project/spi/spi.c + * @author X9D Application Team + * @Hardware version V0.2 + * @date 11-July-2012 + * @brief This file provides spi Init(Analog spi),read and write. + driver for LCD. + * * + ****************************************************************************** +*/ + +#include "radio.h" +#include "stm32f2xx.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_rcc.h" +#include "hal.h" +#include "aspi.h" + +#define __no_operation __NOP + +/** +**********send command to lcd************** +*/ +//hardware spi +/*u16 spiCmd(u8 addr) +{ + u8 readValue; + + SPI_RS_LOW(); + SPI_NCS_LOW(); + + SPI_WRITE_BYTE(addr); + SPI_WAIT_DONE(); + + readValue=SPI_READ_BYTE(); + SPI_NCS_HIGH(); + return readValue; +}*/ + +//Anolog spi +void AspiCmd(uint8_t Command_Byte) +{ + int i=8; + LCD_A0_LOW(); + + LCD_CLK_HIGH(); + LCD_NCS_LOW(); + + while (i--) + { + LCD_CLK_LOW(); + if(Command_Byte&0x80) + { + LCD_MOSI_HIGH(); + } + else LCD_MOSI_LOW(); + + Command_Byte=Command_Byte<<1; + LCD_CLK_HIGH(); + } + LCD_NCS_HIGH(); + LCD_A0_HIGH(); +} + +/** + +********send data to lcd************** + +*/ + +//hardware spi +/* +u16 spiData(u8 addr) +{ + u16 readValue; + OLED_RS_HIGH(); + SPI_NCS_LOW(); + + SPI_WRITE_BYTE(addr); + SPI_WAIT_DONE(); + + readValue=SPI_READ_BYTE(); + SPI_NCS_HIGH(); + return readValue; +} +*/ + +//Anolog spi +void AspiData(uint8_t Para_data) +{ + int i=8; + LCD_CLK_HIGH(); + LCD_A0_HIGH(); + LCD_NCS_LOW(); + while (i--) + { + if(Para_data&0x80) + { + LCD_MOSI_HIGH(); + }else LCD_MOSI_LOW(); + Para_data<<=1; + LCD_CLK_LOW(); + __no_operation(); + LCD_CLK_HIGH(); + __no_operation(); + } + LCD_NCS_HIGH(); + LCD_A0_HIGH(); +} + +/*** +**********read one byte in a register******* +*/ + +/* +u16 spiRegAccess(u8 addrByte, u8 writeValue) +{ + u8 readValue; + + SPI_NCS_LOW(); + + SPI_WRITE_BYTE(addrByte); + SPI_WAIT_DONE(); + + SPI_WRITE_BYTE(writeValue); + SPI_WAIT_DONE(); + + readValue=SPI_READ_BYTE(); + SPI_NCS_HIGH(); + return readValue; +} + +*/ + + diff --git a/radio/bootloader/board_lowlevel.c b/radio/bootloader/board_lowlevel.c new file mode 100644 index 000000000..8bb63be1f --- /dev/null +++ b/radio/bootloader/board_lowlevel.c @@ -0,0 +1,273 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \par Purpose + * + * Provides the low-level initialization function that gets called on chip startup. + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +/*---------------------------------------------------------------------------- + * Local definitions + *----------------------------------------------------------------------------*/ +/** Define clock timeout */ +#define CLOCK_TIMEOUT 5000 +/** Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.*/ +#define PMC_PLLA_SET_BIT29 (0x1 << 29) +/** Specifies the number of Slow Clock cycles x8 before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.*/ +#define PMC_PLLA_COUNT (0xBF << 8) +/** The PLLA Clock frequency is the PLLA input frequency multiplied by 8*/ +#define PMC_PLLA_MULTIPIER (0x07 << 16) +/** PLLA Divider is bypassed.*/ +#define PMC_PLLA_DIV (0x01) + +void revert_osc( void ) ; + + +/*---------------------------------------------------------------------------- + * Local functions + * returns master_frequency + *----------------------------------------------------------------------------*/ + +// *** WARNING, this is called BEFORE .data and .bss have been initialised +// *** GLOBAL variables are NOT useable + +static uint32_t BOARD_ConfigurePmc(void) +{ +/* TODO: configurate PLL in new way */ +//#if 0 +// uint32_t timeout = 0; +// /** 1: Checking the Main Oscillator Frequency (Optional) and Initialize main oscillator */ +// /** 1.1 Initialize main oscillator */ +// // TODO: + +// /** 2. Setting PLL and Divider*/ +// /** 2.1 Initialize PLLA*/ +// PMC->CKGR_PLLAR = ( PMC_PLLA_SET_BIT29 | +// PMC_PLLA_MULTIPIER | +// PMC_PLLA_COUNT | +// PMC_PLLA_DIV +// ); +// timeout = 0; +// /** 2.2 Wait for the LOCKA bit to be set by polling the status register.*/ +// while (!(PMC->PMC_SR & PMC_SR_LOCKA) && (timeout++ < CLOCK_TIMEOUT)); +// /** 2.3 wait for the MCKRDY bit to be set by polling the status register*/ +// timeout = 0; +// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); + +// /** 3. Selection of Master Clock and Processor Clock*/ +// PMC->PMC_MCKR |= PMC_MCKR_PRES_CLK_2; + +// /** 3.1 wait for the MCKRDY bit to be set by polling the status register*/ +// timeout = 0; +// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); + +// /** 3.2 PLLA Clock is selected */ +// PMC->PMC_MCKR = PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK; + +// /** 3.3 wait for the MCKRDY bit to be set by polling the status register*/ +// timeout = 0; +// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); +//#endif + +#if 1 // old as sam3u +#define AT91C_CKGR_MUL_SHIFT 16 +//#define AT91C_CKGR_OUT_SHIFT 14 +#define AT91C_CKGR_PLLCOUNT_SHIFT 8 +#define AT91C_CKGR_DIV_SHIFT 0 + +// Settings at 72MHz/2 = 36MHz +#define BOARD_OSCOUNT (CKGR_MOR_MOSCXTST & (0x8 << 8)) +#define BOARD_PLLR ((1 << 29) | (0x5 << AT91C_CKGR_MUL_SHIFT) \ + | (0x1 << AT91C_CKGR_PLLCOUNT_SHIFT) | (0x2 << AT91C_CKGR_DIV_SHIFT)) +#define BOARD_MCKR (PMC_MCKR_CSS_PLLA_CLK) + +// Define clock timeout +#undef CLOCK_TIMEOUT +#define CLOCK_TIMEOUT 0xFFFFFFFF + + register uint32_t timeout = 0 ; + register Pmc *pmcptr ; + + pmcptr = PMC ; + + /* Enable NRST reset + ************************************/ + //AT91C_BASE_RSTC->RSTC_RMR |= AT91C_RSTC_URSTEN; + + /* Select external slow clock + ****************************/ + + +// if ((SUPC->SUPC_SR & SUPC_SR_OSCSEL) != SUPC_SR_OSCSEL_CRYST) { +// SUPC->SUPC_CR = SUPC_CR_XTALSEL_CRYSTAL_SEL | ((uint32_t)0xA5 << 24); +// timeout = 0; +// while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL_CRYST) ); +// } + + + /* Initialize main oscillator + ****************************/ + if(!(pmcptr->CKGR_MOR & CKGR_MOR_MOSCSEL)) + { + + pmcptr->CKGR_MOR = (0x37 << 16) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN; + timeout = 0; + while (!(pmcptr->PMC_SR & PMC_SR_MOSCXTS) && (++timeout < CLOCK_TIMEOUT)); + + } + + /* Switch to 3-20MHz Xtal oscillator */ + pmcptr->CKGR_MOR = (0x37 << 16) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL; + timeout = 0; + while (!(pmcptr->PMC_SR & PMC_SR_MOSCSELS) && (++timeout < CLOCK_TIMEOUT)); + + pmcptr->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS) | PMC_MCKR_CSS_MAIN_CLK; + timeout = 0; + while (!(pmcptr->PMC_SR & PMC_SR_MCKRDY) && (++timeout < CLOCK_TIMEOUT)); + + /* Initialize PLLA 72 MHz */ + pmcptr->CKGR_PLLAR = BOARD_PLLR; + timeout = 0; + while (!(pmcptr->PMC_SR & PMC_SR_LOCKA) && (++timeout < CLOCK_TIMEOUT)); + + + /* Initialize UTMI for USB usage, can be disabled if not using USB for the sake of saving power*/ + //AT91C_BASE_CKGR->CKGR_UCKR |= (AT91C_CKGR_UPLLCOUNT & (3 << 20)) | AT91C_CKGR_UPLLEN; + //timeout = 0; + //while (!(PMC->PMC_SR & AT91C_PMC_LOCKU) && (timeout++ < CLOCK_TIMEOUT)); + + /* Switch to fast clock + **********************/ +// PMC->PMC_MCKR = (BOARD_MCKR & ~PMC_MCKR_CSS) | PMC_MCKR_CSS_MAIN_CLK; +// timeout = 0; +// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); + + // Switch to PLLA as main clock 36MHz + PMC->PMC_MCKR = BOARD_MCKR; + timeout = 0; + while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); + +#endif + return 36000000L ; // Master_frequency +} + +#ifndef BOOT +void revert_osc() +{ + register uint32_t timeout = 0 ; + register Pmc *pmcptr ; + + pmcptr = PMC ; + + + // Switch back to the internal oscillator + pmcptr->CKGR_MOR = (0x37 << 16) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN ; + timeout = 0; + while (!(pmcptr->PMC_SR & PMC_SR_MOSCSELS) && (++timeout < CLOCK_TIMEOUT)); + + pmcptr->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS) | PMC_MCKR_CSS_SLOW_CLK; + timeout = 0; + while (!(pmcptr->PMC_SR & PMC_SR_MCKRDY) && (++timeout < CLOCK_TIMEOUT)); + + + pmcptr->CKGR_PLLAR = 1 << 29 ; // Stop PLLA + +} +#endif + +#ifdef BOOT + +extern void sam_bootx( void ) ; +extern void dispUSB( void ) ; +extern uint32_t initReadTrims( void ) ; +extern void run_application( void ) ; + +static void lowLevelUsbCheck( void ) +{ + PMC->PMC_PCER0 = (1<PIO_PER = PIO_PC25 ; // Enable bit C25 (USB-detect) + + uint32_t i ; + for ( i = 0 ; i < 50 ; i += 1 ) + { + __asm("nop") ; + } + + for ( i = 0 ; i < 10 ; i += 1 ) + { + if ( PIOC->PIO_PDSR & 0x02000000 ) + { + PMC->PMC_PCDR0 = (1<EEFC_FMR = (1 << 8) ; + + /** Configure PMC */ + return BOARD_ConfigurePmc(); +} + + diff --git a/radio/bootloader/boot.cpp b/radio/bootloader/boot.cpp new file mode 100644 index 000000000..01a1dbdca --- /dev/null +++ b/radio/bootloader/boot.cpp @@ -0,0 +1,1164 @@ +/**************************************************************************** +* Copyright (c) 2014 by Michael Blandford. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. Neither the name of the author nor the names of its contributors may +* be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +* SUCH DAMAGE. +* +**************************************************************************** +* Other Authors: + * - Andre Bernet + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer +* +****************************************************************************/ + + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include +#include +#include +#ifdef PCBSKY +#include "AT91SAM3S4.h" +#include "core_cm3.h" +#endif + +#ifdef PCBX9D +#include "stm32f2xx.h" +#include "stm32f2xx_flash.h" +#include "i2c_ee.h" +#include "hal.h" +#include "timers.h" + +extern "C" { +#include "usb_dcd_int.h" +#include "usb_bsp.h" +#include "usbd_desc.h" +#include "usbd_msc_core.h" +#include "usbd_usr.h" +} + +#endif + +#include "radio.h" +#include "lcd.h" +#include "ff.h" +#include "diskio.h" +#include "drivers.h" +#include "logicio.h" + +#ifdef PCBSKY +extern void usbMassStorage( void ) ; +#endif + +#ifdef PCBSKY +#define BOOT_KEY_UP KEY_UP +#define BOOT_KEY_DOWN KEY_DOWN +#define BOOT_KEY_LEFT KEY_LEFT +#define BOOT_KEY_RIGHT KEY_RIGHT +#define BOOT_KEY_MENU KEY_MENU +#define BOOT_KEY_EXIT KEY_EXIT +#define DISPLAY_CHAR_WIDTH 21 +#endif + +#ifdef PCBX9D +#define BOOT_KEY_UP KEY_PLUS +#define BOOT_KEY_DOWN KEY_MINUS +#define BOOT_KEY_LEFT KEY_MENU +#define BOOT_KEY_RIGHT KEY_PAGE +#define BOOT_KEY_MENU KEY_ENTER +#define BOOT_KEY_EXIT KEY_EXIT +#define DISPLAY_CHAR_WIDTH 35 +#endif + +// states +#define ST_START 0 +#define ST_DIR_CHECK 1 +#define ST_OPEN_DIR 2 +#define ST_FILE_LIST 3 +#define ST_FLASH_CHECK 4 +#define ST_FLASHING 5 +#define ST_FLASH_DONE 6 +#define ST_USB 10 +#define ST_REBOOT 11 + + + + + + +/*---------------------------------------------------------------------------- + * Local variables + *----------------------------------------------------------------------------*/ + +uint32_t FirmwareSize ; + +uint32_t Master_frequency ; +volatile uint8_t Tenms ; +uint8_t EE_timer ; + +extern uint32_t sd_card_ready( void ) ; + +TCHAR FlashFilename[60] ; +FATFS g_FATFS ; +FIL FlashFile ; +DIR Dj ; +FILINFO Finfo ; + +TCHAR Filenames[20][50] ; +uint32_t FileSize[20] ; +uint32_t FnStartIndex ; +uint32_t Valid ; + +uint32_t FlashSize ; + + +uint32_t FlashBlocked = 1 ; +uint32_t LockBits ; + +uint32_t Block_buffer[1024] ; +UINT BlockCount ; + +#ifdef PCBSKY +extern int32_t EblockAddress ; +#endif +extern uint32_t EepromBlocked ; + +extern void init_spi( void ) ; +extern void writeBlock( void ) ; + + +/*---------------------------------------------------------------------------- + * Global functions + *----------------------------------------------------------------------------*/ + +#ifdef PCBSKY +// Starts TIMER0 at full speed (MCK/2) for delay timing +// @ 36MHz this is 18MHz +// This was 6 MHz, we may need to slow it to TIMER_CLOCK2 (MCK/8=4.5 MHz) +void start_timer0() +{ + register Tc *ptc ; + + PMC->PMC_PCER0 |= 0x00800000L ; // Enable peripheral clock to TC0 + + ptc = TC0 ; // Tc block 0 (TC0-2) + ptc->TC_BCR = 0 ; // No sync + ptc->TC_BMR = 2 ; + ptc->TC_CHANNEL[0].TC_CMR = 0x00008001 ; // Waveform mode MCK/8 for 36MHz osc.(Upset be write below) + ptc->TC_CHANNEL[0].TC_RC = 0xFFF0 ; + ptc->TC_CHANNEL[0].TC_RA = 0 ; + ptc->TC_CHANNEL[0].TC_CMR = 0x00008040 ; // 0000 0000 0000 0000 1000 0000 0100 0000, stop at regC, 18MHz + ptc->TC_CHANNEL[0].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) +} + +void stop_timer0( void ) +{ + TC0->TC_CHANNEL[0].TC_CCR = TC_CCR0_CLKDIS ; // Disable clock +} + +void delay2ms() +{ + TC0->TC_CHANNEL[0].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) + while ( TC0->TC_CHANNEL[0].TC_CV < 36000 ) // 2mS, Value depends on MCK/2 (used 18MHz) + { + // Wait + } +} +#endif + +static bool usbPlugged(void) +{ +#ifdef PCBSKY + return PIOC->PIO_PDSR & 0x02000000 ; +#endif + +#ifdef PCBX9D + return GPIOA->IDR & 0x0200 ; +#endif +} + +#ifdef PCBX9D + +extern "C" { +USB_OTG_CORE_HANDLE USB_OTG_dev; + +void OTG_FS_IRQHandler(void) +{ + USBD_OTG_ISR_Handler (&USB_OTG_dev); +} +} + +static void usbInit() +{ + USB_OTG_BSP_Init(&USB_OTG_dev); +} + +static void usbStart() +{ + USBD_Init(&USB_OTG_dev, USB_OTG_FS_CORE_ID, &USR_desc, &USBD_MSC_cb, &USR_cb); +} + +uint32_t isFirmwareStart( uint32_t *block ) +{ + if ( ( block[0] & 0xFFFC0000 ) != 0x20000000 ) + { + return 0 ; + } + if ( ( block[1] & 0xFFF00000 ) != 0x08000000 ) + { + return 0 ; + } + if ( ( block[2] & 0xFFF00000 ) != 0x08000000 ) + { + return 0 ; + } + return 1 ; +} +#endif + +#ifdef PCBSKY +uint32_t isFirmwareStart( uint32_t *block ) +{ + if ( ( block[0] & 0xFFFE3000 ) != 0x20000000 ) + { + return 0 ; + } + if ( ( block[1] & 0xFFF80000 ) != 0x00400000 ) + { + return 0 ; + } + if ( ( block[2] & 0xFFF80000 ) != 0x00400000 ) + { + return 0 ; + } + return 1 ; +} +#endif + + +#ifdef PCBSKY + +uint32_t (*IAP_Function)(uint32_t, uint32_t) ; + + +uint32_t program( uint32_t *address, uint32_t *buffer ) // size is 256 bytes +{ + uint32_t FlashSectorNum ; + uint32_t flash_cmd = 0 ; + uint32_t i ; +// uint32_t flash_status = 0; + // uint32_t EFCIndex = 0; // 0:EEFC0, 1: EEFC1 + /* Initialize the function pointer (retrieve function address from NMI vector) */ + + if ( (uint32_t) address == 0x00408000 ) + { + if ( isFirmwareStart( buffer) ) + { + FlashBlocked = 0 ; + } + else + { + FlashBlocked = 1 ; + } + } + + if ( FlashBlocked ) + { + return 1 ; + } + // Always initialise this here, setting a default doesn't seem to work + IAP_Function = (uint32_t (*)(uint32_t, uint32_t)) *(( uint32_t *)0x00800008) ; + FlashSectorNum = (uint32_t) address ; + FlashSectorNum >>= 8 ; // page size is 256 bytes + FlashSectorNum &= 2047 ; // max page number + + /* Send data to the sector here */ + for ( i = 0 ; i < 64 ; i += 1 ) + { + *address++ = *buffer++ ; + } + + /* build the command to send to EEFC */ + flash_cmd = (0x5A << 24) | (FlashSectorNum << 8) | 0x03 ; //AT91C_MC_FCMD_EWP ; + + __disable_irq() ; + /* Call the IAP function with appropriate command */ + i = IAP_Function( 0, flash_cmd ) ; + __enable_irq() ; + return i ; +} + + +uint32_t readLockBits() +{ + // Always initialise this here, setting a default doesn't seem to work + IAP_Function = (uint32_t (*)(uint32_t, uint32_t)) *(( uint32_t *)0x00800008) ; + + uint32_t flash_cmd = (0x5A << 24) | 0x0A ; //AT91C_MC_FCMD_GLB ; + __disable_irq() ; + (void) IAP_Function( 0, flash_cmd ) ; + __enable_irq() ; + return EFC->EEFC_FRR ; +} + + +void clearLockBits() +{ + uint32_t i ; + uint32_t flash_cmd = 0 ; + + // Always initialise this here, setting a default doesn't seem to work + IAP_Function = (uint32_t (*)(uint32_t, uint32_t)) *(( uint32_t *)0x00800008) ; + for ( i = 0 ; i < 16 ; i += 1 ) + { + flash_cmd = (0x5A << 24) | ((128*i) << 8) | 0x09 ; //AT91C_MC_FCMD_CLB ; + __disable_irq() ; + /* Call the IAP function with appropriate command */ + (void) IAP_Function( 0, flash_cmd ) ; + __enable_irq() ; + } +} +#endif + +void interrupt10ms() +{ + Tenms |= 1 ; // 10 mS has passed + per10ms() ; +} + +#ifdef PCBSKY +void init10msTimer() +{ + register Tc *ptc ; + register uint32_t timer ; + + PMC->PMC_PCER0 |= 0x02000000L ; // Enable peripheral clock to TC2 + + timer = Master_frequency / 12800 ; // MCK/128 and 100 Hz + + ptc = TC0 ; // Tc block 0 (TC0-2) + ptc->TC_BCR = 0 ; // No sync + ptc->TC_BMR = 0 ; + ptc->TC_CHANNEL[2].TC_CMR = 0x00008000 ; // Waveform mode + ptc->TC_CHANNEL[2].TC_RC = timer ; // 10 Hz + ptc->TC_CHANNEL[2].TC_RA = timer >> 1 ; + ptc->TC_CHANNEL[2].TC_CMR = 0x0009C003 ; // 0000 0000 0000 1001 1100 0000 0000 0011 + // MCK/128, set @ RA, Clear @ RC waveform + ptc->TC_CHANNEL[2].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) + + NVIC_EnableIRQ(TC2_IRQn) ; + TC0->TC_CHANNEL[2].TC_IER = TC_IER0_CPCS ; +} + +extern "C" void TC2_IRQHandler() +{ + register uint32_t dummy; + + /* Clear status bit to acknowledge interrupt */ + dummy = TC0->TC_CHANNEL[2].TC_SR; + (void) dummy ; // Discard value - prevents compiler warning + + interrupt10ms() ; + +} +#endif + +#ifdef PCBX9D +void init10msTimer() +{ + // Timer14 + RCC->APB1ENR |= RCC_APB1ENR_TIM14EN ; // Enable clock + TIM14->ARR = 9999 ; // 10mS + TIM14->PSC = (Peri1_frequency*Timer_mult1) / 1000000 - 1 ; // 1uS from 12MHz + TIM14->CCER = 0 ; + TIM14->CCMR1 = 0 ; + TIM14->EGR = 0 ; + TIM14->CR1 = 5 ; + TIM14->DIER |= 1 ; + NVIC_EnableIRQ(TIM8_TRG_COM_TIM14_IRQn) ; +} + +extern "C" void TIM8_TRG_COM_TIM14_IRQHandler() +{ + TIM14->SR &= ~TIM_SR_UIF ; + interrupt10ms() ; +} + +void init_hw_timer() +{ + // Timer13 + RCC->APB1ENR |= RCC_APB1ENR_TIM13EN ; // Enable clock + TIM13->ARR = 65535 ; + TIM13->PSC = (Peri1_frequency*Timer_mult1) / 10000000 - 1 ; // 0.1uS from 12MHz + TIM13->CCER = 0 ; + TIM13->CCMR1 = 0 ; + TIM13->EGR = 0 ; + TIM13->CR1 = 1 ; +} + + +// delay in units of 0.1 uS up to 6.5535 mS +void hw_delay( uint16_t time ) +{ + TIM13->CNT = 0 ; + TIM13->EGR = 1 ; // Re-start counter + while ( TIM13->CNT < time ) + { + // wait + } +} + +//After reset, write is not allowed in the Flash control register (FLASH_CR) to protect the +//Flash memory against possible unwanted operations due, for example, to electric +//disturbances. The following sequence is used to unlock this register: +//1. Write KEY1 = 0x45670123 in the Flash key register (FLASH_KEYR) +//2. Write KEY2 = 0xCDEF89AB in the Flash key register (FLASH_KEYR) +//Any wrong sequence will return a bus error and lock up the FLASH_CR register until the +//next reset. +//The FLASH_CR register can be locked again by software by setting the LOCK bit in the +//FLASH_CR register. +void unlockFlash() +{ + FLASH->KEYR = 0x45670123 ; + FLASH->KEYR = 0xCDEF89AB ; +} + +void waitFlashIdle() +{ + while (FLASH->SR & FLASH_FLAG_BSY) + { + wdt_reset() ; + } +} + +#define SECTOR_MASK ((uint32_t)0xFFFFFF07) + +void eraseSector( uint32_t sector ) +{ + waitFlashIdle() ; + + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= FLASH_PSIZE_WORD ; + FLASH->CR &= SECTOR_MASK; + FLASH->CR |= FLASH_CR_SER | (sector<<3) ; + FLASH->CR |= FLASH_CR_STRT; + + /* Wait for operation to be completed */ + waitFlashIdle() ; + + /* if the erase operation is completed, disable the SER Bit */ + FLASH->CR &= (~FLASH_CR_SER); + FLASH->CR &= SECTOR_MASK; +} + +uint32_t program( uint32_t *address, uint32_t *buffer ) // size is 256 bytes +{ + uint32_t i ; + + if ( (uint32_t) address == 0x08008000 ) + { + if ( isFirmwareStart( buffer) ) + { + FlashBlocked = 0 ; + } + else + { + FlashBlocked = 1 ; + } + } + + if ( FlashBlocked ) + { + return 1 ; + } + + if ( (uint32_t) address == 0x08008000 ) + { + eraseSector( 2 ) ; + } + if ( (uint32_t) address == 0x0800C000 ) + { + eraseSector( 3 ) ; + } + if ( (uint32_t) address == 0x08010000 ) + { + eraseSector( 4 ) ; + } + if ( (uint32_t) address == 0x08020000 ) + { + eraseSector( 5 ) ; + } + if ( (uint32_t) address == 0x08040000 ) + { + eraseSector( 6 ) ; + } + if ( (uint32_t) address == 0x08060000 ) + { + eraseSector( 7 ) ; + } + + // Now program the 256 bytes + + for (i = 0 ; i < 64 ; i += 1 ) + { + /* Device voltage range supposed to be [2.7V to 3.6V], the operation will + be done by word */ + + // Wait for last operation to be completed + waitFlashIdle() ; + + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= FLASH_PSIZE_WORD; + FLASH->CR |= FLASH_CR_PG; + + *address = *buffer ; + + /* Wait for operation to be completed */ + waitFlashIdle() ; + FLASH->CR &= (~FLASH_CR_PG); + + /* Check the written value */ + if ( *address != *buffer ) + { + /* Flash content doesn't match SRAM content */ + return 2 ; + } + /* Increment FLASH destination address */ + address += 1 ; + buffer += 1 ; + } + return 0 ; +} + +#endif + + +uint8_t *cpystr( uint8_t *dest, uint8_t *source ) +{ + while ( (*dest++ = *source++) ) + ; + return dest - 1 ; +} + + +FRESULT readBinDir( DIR *dj, FILINFO *fno ) +{ + FRESULT fr ; + uint32_t loop ; + do + { + loop = 0 ; + fr = f_readdir ( dj, fno ) ; // First entry + + if ( fr != FR_OK || fno->fname[0] == 0 ) + { + break ; + } + if ( *fno->lfname == 0 ) + { + cpystr( (uint8_t *)fno->lfname, (uint8_t *)fno->fname ) ; // Copy 8.3 name + } + int32_t len = strlen(fno->lfname) - 4 ; + if ( len < 0 ) + { + loop = 1 ; + } + if ( fno->lfname[len] != '.' ) + { + loop = 1 ; + } + if ( ( fno->lfname[len+1] != 'b' ) && ( fno->lfname[len+1] != 'B' ) ) + { + loop = 1 ; + } + if ( ( fno->lfname[len+2] != 'i' ) && ( fno->lfname[len+2] != 'I' ) ) + { + loop = 1 ; + } + if ( ( fno->lfname[len+3] != 'n' ) && ( fno->lfname[len+3] != 'N' ) ) + { + loop = 1 ; + } + + } while ( loop ) ; + return fr ; +} + + +uint32_t fillNames( uint32_t index ) +{ + uint32_t i ; + FRESULT fr ; + Finfo.lfname = Filenames[0] ; + Finfo.lfsize = 48 ; + fr = f_readdir ( &Dj, 0 ) ; // rewind + fr = f_readdir ( &Dj, &Finfo ) ; // Skip . + fr = f_readdir ( &Dj, &Finfo ) ; // Skip .. + i = 0 ; + while ( i <= index ) + { + fr = readBinDir( &Dj, &Finfo ) ; // First entry + FileSize[0] = Finfo.fsize ; + i += 1 ; + if ( fr == FR_NO_FILE) + { + return 0 ; + } + } + for ( i = 1 ; i < 7 ; i += 1 ) + { + Finfo.lfname = Filenames[i] ; + fr = readBinDir( &Dj, &Finfo ) ; // First entry + FileSize[i] = Finfo.fsize ; + if ( fr != FR_OK || Finfo.fname[0] == 0 ) + { + break ; + } + } + return i ; +} + +FRESULT openFirmwareFile( uint32_t index ) +{ + cpystr( cpystr( (uint8_t *)FlashFilename, (uint8_t *)"\\firmware\\" ), (uint8_t *)Filenames[index] ) ; + f_open( &FlashFile, FlashFilename, FA_READ ) ; + f_lseek ( &FlashFile, 32768 ) ; + return f_read( &FlashFile, (BYTE *)Block_buffer, 4096, &BlockCount ) ; +} + + + +uint8_t flashFile( uint32_t index ) +{ + FRESULT fr ; + + lcd_clear() ; + lcd_puts_Pleft( 0, "\005Flash File" ) ; + if ( Valid == 0 ) + { + // Validate file here + // return 3 if invalid + fr = openFirmwareFile( index ) ; + fr = f_close( &FlashFile ) ; + + Valid = 1 ; + if ( isFirmwareStart( Block_buffer ) == 0 ) + { + Valid = 2 ; + } + } + if ( Valid == 2 ) + { + lcd_puts_Pleft( 3*FH,"NOT A VALID FIRMWARE") ; +#ifdef PCBX9D + lcd_puts_Pleft( 6*FH,"\015[EXIT]") ; +#else + lcd_puts_Pleft( 6*FH,"\007[EXIT]") ; +#endif + uint8_t event = getEvent() ; + if ( event == EVT_KEY_FIRST(BOOT_KEY_EXIT) ) + { + return 3 ; + } + return 4 ; // + } + lcd_putsn_P( 0, 2*FH, Filenames[index], DISPLAY_CHAR_WIDTH ) ; + +#ifdef PCBX9D + lcd_puts_Pleft( 6*FH,"\010[ENTER]\021[EXIT]") ; + lcd_puts_Pleft( 5*FH,"\010YES\021NO") ; +#else + lcd_puts_Pleft( 6*FH,"\003[MENU]\013[EXIT]") ; + lcd_puts_Pleft( 5*FH,"\003YES\013NO") ; +#endif + + uint8_t event = getEvent() ; + + if ( event == EVT_KEY_FIRST(BOOT_KEY_MENU) ) + { + fr = openFirmwareFile( index ) ; + FirmwareSize = FileSize[index] ; + if ( fr != FR_OK ) + { + return 4 ; // File open error + } + return 2 ; + } + if ( event == EVT_KEY_FIRST(BOOT_KEY_EXIT) ) + { + return 1 ; + } + return 0 ; +} + + +extern Key keys[] ; + +static uint32_t PowerUpDelay ; + +int main() +{ + uint32_t i ; + uint8_t index = 0 ; +#ifdef PCBX9D + uint8_t TenCount = 2 ; +#endif + uint8_t maxhsize = DISPLAY_CHAR_WIDTH ; + FRESULT fr ; + uint32_t state = ST_START ; + uint32_t nameCount = 0 ; + uint32_t vpos = 0 ; + uint32_t hpos = 0 ; +#ifdef PCBX9D + uint32_t firmwareAddress = 0x08000000 ; +#endif +#ifdef PCBSKY + uint32_t firmwareAddress = 0x00400000 ; +#endif + uint32_t firmwareWritten = 0 ; + +#ifdef PCBX9D + wdt_reset() ; + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ; // Enable portA clock +#endif + + init_soft_power() ; + +#ifdef PCBSKY + MATRIX->CCFG_SYSIO |= 0x000000F0L ; // Disable syspins, enable B4,5,6,7 +#endif + +#ifdef PCBSKY + init_SDcard() ; + PIOC->PIO_PER = PIO_PC25 ; // Enable bit C25 (USB-detect) + start_timer0() ; +#endif + + lcd_init() ; +#ifdef PCBSKY +extern uint8_t OptrexDisplay ; + OptrexDisplay = 1 ; +#endif + lcd_clear() ; +#ifdef PCBX9D + lcd_puts_Pleft( 0, "\006Boot Loader" ) ; +#endif + refreshDisplay() ; +#ifdef PCBSKY + OptrexDisplay = 0 ; + refreshDisplay() ; +#endif + +#ifdef PCBX9D + init_keys() ; + I2C_EE_Init() ; + init_hw_timer() ; +#endif + + __enable_irq() ; + init10msTimer() ; + +#ifdef PCBSKY + EblockAddress = -1 ; + init_spi() ; +#endif + +#ifdef PCBSKY + uint32_t chip_id = CHIPID->CHIPID_CIDR ; + + FlashSize = ( (chip_id >> 8 ) & 0x000F ) == 9 ? 256 : 512 ; +#endif + +#ifdef PCBX9D + FlashSize = 512 ; +#endif + +#ifdef PCBSKY + LockBits = readLockBits() ; + if ( LockBits ) + { + clearLockBits() ; + } +#endif + +#ifdef PCBX9D + // SD card detect pin + configure_pins( GPIO_Pin_CP, PIN_PORTD | PIN_INPUT | PIN_PULLUP ) ; + disk_initialize( 0 ) ; + sdInit() ; + unlockFlash() ; + + usbInit() ; + usbStart() ; +#endif + + for(;;) + { +#ifdef PCBSKY + usbMassStorage() ; +#endif + + wdt_reset() ; + + if ( Tenms ) + { + wdt_reset() ; // Retrigger hardware watchdog + + if ( EE_timer ) + { + if ( --EE_timer == 0) + { +#ifdef PCBSKY + writeBlock() ; +#endif + } + } + + Tenms = 0 ; + lcd_clear() ; +#ifdef PCBSKY + lcd_puts_Pleft( 0, "Boot Loader" ) ; +#endif +#ifdef PCBX9D + lcd_puts_Pleft( 0, "\006Boot Loader" ) ; +#endif + + if ( sd_card_ready() ) + { +#ifdef PCBSKY + lcd_puts_Pleft( 0, "\014Ready" ) ; +#endif +#ifdef PCBX9D + lcd_puts_Pleft( 0, "\022Ready" ) ; +#endif + + if ( usbPlugged() ) + { + state = ST_USB ; + } + + if ( state == ST_USB ) + { +#ifdef PCBSKY + lcd_puts_Pleft( 3*FH, "\010BUSY" ) ; +#endif +#ifdef PCBX9D + lcd_puts_Pleft( 3*FH, "\016BUSY" ) ; +#endif + if ( usbPlugged() == 0 ) + { + state = ST_START ; + } +#ifdef PCBSKY + lcd_putc( 0, 6*FH, 'F' ) ; + lcd_putc( 6, 6*FH, '0' + FlashBlocked ) ; + lcd_putc( 0, 7*FH, 'E' ) ; + lcd_putc( 6, 7*FH, '0' + EepromBlocked ) ; +#endif + } + + if ( state == ST_START ) + { + fr = f_mount(0, &g_FATFS) ; + } + else + { + fr = FR_OK ; + } + + if ( fr == FR_OK) + { + if ( state == ST_START ) + { + state = ST_DIR_CHECK ; + } + } + if ( state == ST_DIR_CHECK ) + { + fr = f_chdir( (TCHAR *)"\\firmware" ) ; + if ( fr == FR_OK ) + { + state = ST_OPEN_DIR ; + index = 0 ; + } + } + if ( state == ST_DIR_CHECK ) + { +#ifdef PCBSKY + lcd_puts_Pleft( 16, "\005No Firmware" ) ; +#endif +#ifdef PCBX9D + lcd_puts_Pleft( 16, "\013No Firmware" ) ; +#endif + } + if ( state == ST_OPEN_DIR ) + { + fr = f_opendir( &Dj, (TCHAR *) "." ) ; + if ( fr == FR_OK ) + { + state = ST_FILE_LIST ; + index = 0 ; + nameCount = fillNames( 0 ) ; + hpos = 0 ; + vpos = 0 ; + } + } + if ( state == ST_FILE_LIST ) + { + uint32_t limit = 6 ; + if ( nameCount < limit ) + { + limit = nameCount ; + } + maxhsize = 0 ; + for ( i = 0 ; i < limit ; i += 1 ) + { + uint32_t x ; + x = strlen( Filenames[i] ) ; + if ( x > maxhsize ) + { + maxhsize = x ; + } + if ( x > DISPLAY_CHAR_WIDTH ) + { + if ( ( hpos + DISPLAY_CHAR_WIDTH ) > x ) + { + x = x - DISPLAY_CHAR_WIDTH ; + } + else + { + x = hpos ; + } + } + else + { + x = 0 ; + } + lcd_putsn_P( 0, 16+FH*i, &Filenames[i][x], DISPLAY_CHAR_WIDTH ) ; + } + { + uint8_t event = getEvent() ; + + if ( ( event == EVT_KEY_REPT(BOOT_KEY_DOWN) ) || event == EVT_KEY_FIRST(BOOT_KEY_DOWN) ) + { + if ( vpos < limit-1 ) + { + vpos += 1 ; + } + else + { + if ( nameCount > limit ) + { + index += 1 ; + nameCount = fillNames( index ) ; + } + } + } + if ( ( event == EVT_KEY_REPT(BOOT_KEY_UP)) || ( event == EVT_KEY_FIRST(BOOT_KEY_UP) ) ) + { + if ( vpos > 0 ) + { + vpos -= 1 ; + } + else + { + if ( index ) + { + index -= 1 ; + nameCount = fillNames( index ) ; + } + } + } + if ( ( event == EVT_KEY_REPT(BOOT_KEY_RIGHT)) || ( event == EVT_KEY_FIRST(BOOT_KEY_RIGHT) ) ) + { + if ( hpos + DISPLAY_CHAR_WIDTH < maxhsize ) + { + hpos += 1 ; + } + } + if ( ( event == EVT_KEY_REPT(BOOT_KEY_LEFT)) || ( event == EVT_KEY_FIRST(BOOT_KEY_LEFT) ) ) + { + if ( hpos ) + { + hpos -= 1 ; + } + } + if ( event == EVT_KEY_LONG(BOOT_KEY_MENU) ) + { + // Select file to flash + state = ST_FLASH_CHECK ; + Valid = 0 ; + } + if ( event == EVT_KEY_LONG(BOOT_KEY_EXIT) ) + { + state = ST_REBOOT ; + } + } + lcd_char_inverse( 0, 2*FH+FH*vpos, DISPLAY_CHAR_WIDTH*FW, 0 ) ; + } + if ( state == ST_FLASH_CHECK ) + { + i = flashFile( vpos ) ; + FirmwareSize = FileSize[vpos] - 32768 ; + if ( i == 1 ) + { + state = ST_FILE_LIST ; // Canceled + } + if ( i == 2 ) + { +#ifdef PCBSKY + firmwareAddress = 0x00408000 ; +#endif +#ifdef PCBX9D + firmwareAddress = 0x08008000 ; +#endif + firmwareWritten = 0 ; + state = ST_FLASHING ; // confirmed + } + if ( i == 3 ) + { + // Invalid file + state = ST_FILE_LIST ; // Canceled + } + } + if ( state == ST_FLASHING ) + { + // Commit to flashing + uint32_t blockOffset = 0 ; + lcd_puts_Pleft( 3*FH, "Flashing" ) ; + while ( BlockCount ) + { + program( (uint32_t *)firmwareAddress, &Block_buffer[blockOffset] ) ; // size is 256 bytes + blockOffset += 64 ; // 32-bit words (256 bytes) + firmwareAddress += 256 ; + if ( BlockCount > 256 ) + { + BlockCount -= 256 ; + } + else + { + BlockCount = 0 ; + } + } + firmwareWritten += 1 ; + uint32_t width = FirmwareSize / 4096 ; + lcd_hline( 0, 5*FH-1, width+1 ) ; + lcd_hline( 0, 6*FH, width+1 ) ; + lcd_vline( width, 5*FH, 8 ) ; + for ( i = 0 ; i < firmwareWritten ; i += 1 ) + { + lcd_vline( i, 5*FH, 8 ) ; + } + fr = f_read( &FlashFile, (BYTE *)Block_buffer, 4096, &BlockCount ) ; + if ( BlockCount == 0 ) + { + state = ST_FLASH_DONE ; + } + if ( firmwareWritten > FlashSize/4 - 9 ) // (127-8, or 63-8) 4K blocks + { + state = ST_FLASH_DONE ; // Backstop + } + } + if ( state == ST_FLASH_DONE ) + { + uint8_t event = getEvent() ; + lcd_puts_Pleft( 3*FH, "Flashing Complete" ) ; + if ( event == EVT_KEY_FIRST(BOOT_KEY_EXIT) ) + { + state = ST_FILE_LIST ; + } + } + } + +#ifdef PCBX9D + if ( --TenCount == 0 ) + { + TenCount = 2 ; +#endif + refreshDisplay() ; +#ifdef PCBX9D + } +#endif + if ( PowerUpDelay < 20 ) // 200 mS + { + PowerUpDelay += 1 ; + } + else + { +#ifdef PCBSKY + sd_poll_10mS() ; +#endif +#ifdef PCBX9D + sdPoll10ms() ; +#endif + } + } + if ((state < ST_FLASH_CHECK) || (state == ST_FLASH_DONE)) + { + if ( check_soft_power() == POWER_OFF ) + { + soft_power_off() ; + for(;;) + { + // Wait for power to go off + } + } + } + if ( state < ST_FILE_LIST ) + { + if ( getEvent() == EVT_KEY_LONG(BOOT_KEY_EXIT) ) + { + state = ST_REBOOT ; + } + } + if ( state == ST_REBOOT ) + { + if ( (~read_keys() & 0x7E) == 0 ) + { + NVIC_SystemReset() ; + } + } + + } +// stop_timer0() ; + + return 0; +} + + diff --git a/radio/bootloader/bootsamEeprom.cpp b/radio/bootloader/bootsamEeprom.cpp new file mode 100644 index 000000000..a3803793d --- /dev/null +++ b/radio/bootloader/bootsamEeprom.cpp @@ -0,0 +1,604 @@ +/**************************************************************************** +* Copyright (c) 2014 by Michael Blandford. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. Neither the name of the author nor the names of its contributors may +* be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +* SUCH DAMAGE. +* +**************************************************************************** +* Other Authors: + * - Andre Bernet + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer +* +****************************************************************************/ + + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include +#include +#include +#include "AT91SAM3S4.h" + + +uint8_t Eblock_buffer[4096] ; +uint8_t Eblock_current[4096] ; // For erased checking +int32_t EblockAddress ; + +uint8_t Spi_tx_buf[24] ; +uint8_t Spi_rx_buf[24] ; +uint32_t Spi_init_done = 0 ; + +uint32_t EepromBlocked = 1 ; +extern uint8_t EE_timer ; + +// Test for EEPROM file +uint32_t isEepromStart( uint8_t *p ) +{ + uint32_t csum ; + uint32_t size = 7 ; + + csum = 0 ; + while( size ) + { + csum += *p++ ; + size -= 1 ; + } + if ( csum == *p ) + { + return 1 ; + } + return 0 ; +} + + +uint32_t eeprom_write_one( uint8_t byte, uint8_t count ) ; +uint32_t eeprom_read_status( void ) ; +void eeprom_write_enable( void ) ; +void eeprom_wait_busy( void ) ; +uint32_t spi_operation( register uint8_t *tx, register uint8_t *rx, register uint32_t count ) ; +void init_spi( void ) ; +uint32_t unprotect_eeprom( void ) ; +uint32_t spi_PDC_action( register uint8_t *command, register uint8_t *tx, register uint8_t *rx, register uint32_t comlen, register uint32_t count ) ; +void AT25D_Read( uint8_t *BufferAddr, uint32_t size, uint32_t memoryOffset) ; +void AT25D_Write( uint8_t *BufferAddr, uint32_t size, uint32_t memoryOffset ) ; +uint32_t AT25D_EraseBlock( uint32_t memoryOffset ) ; +void writeBlock( void ) ; + + +uint32_t eeprom_write_one( uint8_t byte, uint8_t count ) +{ + register Spi *spiptr ; + register uint32_t result ; + + spiptr = SPI ; + spiptr->SPI_CR = 1 ; // Enable + (void) spiptr->SPI_RDR ; // Dump any rx data + + spiptr->SPI_TDR = byte ; + + result = 0 ; + while( ( spiptr->SPI_SR & SPI_SR_RDRF ) == 0 ) + { + // wait for received + if ( ++result > 10000 ) + { + break ; + } + } + if ( count == 0 ) + { + spiptr->SPI_CR = 2 ; // Disable + return spiptr->SPI_RDR ; + } + (void) spiptr->SPI_RDR ; // Dump the rx data + spiptr->SPI_TDR = 0 ; + result = 0 ; + while( ( spiptr->SPI_SR & SPI_SR_RDRF ) == 0 ) + { + // wait for received + if ( ++result > 10000 ) + { + break ; + } + } + spiptr->SPI_CR = 2 ; // Disable + return spiptr->SPI_RDR ; +} + + +uint32_t eeprom_read_status() +{ + return eeprom_write_one( 5, 1 ) ; +} + + +void eeprom_write_enable() +{ + eeprom_write_one( 6, 0 ) ; +} + +void eeprom_wait_busy() +{ + register uint32_t x ; + register uint32_t y ; + + y = 0 ; + do + { + y += 1 ; + if ( y > 1000000 ) + { + break ; + } + x = eeprom_read_status() ; + } while ( x & 1 ) ; + +} + +uint32_t spi_operation( register uint8_t *tx, register uint8_t *rx, register uint32_t count ) +{ + register Spi *spiptr ; + register uint32_t result ; + +// PMC->PMC_PCER0 |= 0x00200000L ; // Enable peripheral clock to SPI + + result = 0 ; + spiptr = SPI ; + spiptr->SPI_CR = 1 ; // Enable + (void) spiptr->SPI_RDR ; // Dump any rx data + while( count ) + { + result = 0 ; + while( ( spiptr->SPI_SR & SPI_SR_TXEMPTY ) == 0 ) + { + // wait + if ( ++result > 10000 ) + { + result = 0xFFFF ; + break ; + } + } + if ( result > 10000 ) + { + break ; + } +// if ( count == 1 ) +// { +// spiptr->SPI_CR = SPI_CR_LASTXFER ; // LastXfer bit +// } + spiptr->SPI_TDR = *tx++ ; + result = 0 ; + while( ( spiptr->SPI_SR & SPI_SR_RDRF ) == 0 ) + { + // wait for received + if ( ++result > 10000 ) + { + result = 0x2FFFF ; + break ; + } + } + if ( result > 10000 ) + { + break ; + } + *rx++ = spiptr->SPI_RDR ; + count -= 1 ; + } + if ( result <= 10000 ) + { + result = 0 ; + } + spiptr->SPI_CR = 2 ; // Disable + +// Power save +// PMC->PMC_PCER0 &= ~0x00200000L ; // Disable peripheral clock to SPI + + return result ; +} + +uint32_t spi_PDC_action( register uint8_t *command, register uint8_t *tx, register uint8_t *rx, register uint32_t comlen, register uint32_t count ) +{ + register Spi *spiptr ; +// register uint32_t result ; + register uint32_t condition ; + static uint8_t discard_rx_command[4] ; + +// PMC->PMC_PCER0 |= 0x00200000L ; // Enable peripheral clock to SPI + +// Spi_complete = 0 ; + if ( comlen > 4 ) + { +// Spi_complete = 1 ; + return 0x4FFFF ; + } + condition = SPI_SR_TXEMPTY ; + spiptr = SPI ; + spiptr->SPI_CR = 1 ; // Enable + (void) spiptr->SPI_RDR ; // Dump any rx data + (void) spiptr->SPI_SR ; // Clear error flags + spiptr->SPI_RPR = (uint32_t)discard_rx_command ; + spiptr->SPI_RCR = comlen ; + if ( rx ) + { + spiptr->SPI_RNPR = (uint32_t)rx ; + spiptr->SPI_RNCR = count ; + condition = SPI_SR_RXBUFF ; + } + spiptr->SPI_TPR = (uint32_t)command ; + spiptr->SPI_TCR = comlen ; + if ( tx ) + { + spiptr->SPI_TNPR = (uint32_t)tx ; + } + else + { + spiptr->SPI_TNPR = (uint32_t)rx ; + } + spiptr->SPI_TNCR = count ; + + spiptr->SPI_PTCR = SPI_PTCR_RXTEN | SPI_PTCR_TXTEN ; // Start transfers + + // Wait for things to get started, avoids early interrupt + for ( count = 0 ; count < 1000 ; count += 1 ) + { + if ( ( spiptr->SPI_SR & SPI_SR_TXEMPTY ) == 0 ) + { + break ; + } + } + + count = 0 ; + while( ( spiptr->SPI_SR & condition ) == 0 ) + { + if ( ++count > 1000000 ) + { + break ; + } + } + + spiptr->SPI_CR = 2 ; // Disable + (void) spiptr->SPI_RDR ; // Dump any rx data + (void) spiptr->SPI_SR ; // Clear error flags + spiptr->SPI_PTCR = SPI_PTCR_RXTDIS | SPI_PTCR_TXTDIS ; // Stop tramsfers + + if ( count > 1000000 ) + { + return 1 ; + } + return 0 ; +} + + +uint32_t unprotect_eeprom() +{ + register uint8_t *p ; + + eeprom_write_enable() ; + + p = Spi_tx_buf ; + *p = 0x39 ; // Unprotect sector command + *(p+1) = 0 ; + *(p+2) = 0 ; + *(p+3) = 0 ; // 3 bytes address + + return spi_operation( p, Spi_rx_buf, 4 ) ; +} + + + + + + +void init_spi() +{ + register Pio *pioptr ; + register Spi *spiptr ; + register uint32_t timer ; + register uint8_t *p ; + uint8_t spi_buf[4] ; + + if ( !Spi_init_done) + { + PMC->PMC_PCER0 |= 0x00200000L ; // Enable peripheral clock to SPI + /* Configure PIO */ + pioptr = PIOA ; + pioptr->PIO_ABCDSR[0] &= ~0x00007800 ; // Peripheral A bits 14,13,12,11 + pioptr->PIO_ABCDSR[1] &= ~0x00007800 ; // Peripheral A + pioptr->PIO_PDR = 0x00007800 ; // Assign to peripheral + + spiptr = SPI ; + timer = ( 64000000 / 3000000 ) << 8 ; + spiptr->SPI_MR = 0x14000011 ; // 0001 0100 0000 0000 0000 0000 0001 0001 Master + spiptr->SPI_CSR[0] = 0x01180009 | timer ; // 0000 0001 0001 1000 xxxx xxxx 0000 1001 + // NVIC_EnableIRQ(SPI_IRQn) ; + + p = spi_buf ; + + // *p = 0x39 ; // Unprotect sector command + // *(p+1) = 0 ; + // *(p+2) = 0 ; + // *(p+3) = 0 ; // 3 bytes address + + // spi_operation( p, spi_buf, 4 ) ; + + eeprom_write_enable() ; + + *p = 1 ; // Write status register command + *(p+1) = 0 ; + spi_operation( p, spi_buf, 2 ) ; + Spi_init_done = 1 ; + } + +} + + +void AT25D_Read( uint8_t *BufferAddr, uint32_t size, uint32_t memoryOffset) +{ + register uint8_t *p ; + + p = Spi_tx_buf ; + *p = 3 ; // Read command + *(p+1) = memoryOffset >> 16 ; + *(p+2) = memoryOffset >> 8 ; + *(p+3) = memoryOffset ; // 3 bytes address + + spi_PDC_action( p, 0, BufferAddr, 4, size ) ; +} + + +uint32_t ee32_read_512( uint32_t sector, uint8_t *buffer ) +{ + AT25D_Read( buffer, 512, sector * 512 ) ; + return 1 ; +} + +void AT25D_Write( uint8_t *BufferAddr, uint32_t size, uint32_t memoryOffset ) +{ + register uint8_t *p ; + + eeprom_write_enable() ; + + p = Spi_tx_buf ; + *p = 2 ; // Write command + *(p+1) = memoryOffset >> 16 ; + *(p+2) = memoryOffset >> 8 ; + *(p+3) = memoryOffset ; // 3 bytes address + + spi_PDC_action( p, BufferAddr, 0, 4, size ) ; + + eeprom_wait_busy() ; + +} + +uint32_t eeprom_block_erased( register uint8_t *p) +{ + register uint32_t x ; + register uint32_t result ; + + result = 1 ; + + for ( x = 0 ; x < 4096 ; x += 1 ) + { + if ( *p++ != 0xFF ) + { + result = 0 ; + break ; + } + } + return result ; +} + +uint32_t eeprom_page_erased( register uint8_t *p) +{ + register uint32_t x ; + register uint32_t result ; + + result = 1 ; + + for ( x = 0 ; x < 256 ; x += 1 ) + { + if ( *p++ != 0xFF ) + { + result = 0 ; + break ; + } + } + return result ; +} + +void writeBlock() +{ + uint32_t x ; + uint32_t address ; + uint32_t i ; + uint8_t *s ; + + x = eeprom_block_erased( Eblock_current ) ; // EEPROM block blanked? + if ( x == 0 ) + { + AT25D_EraseBlock( EblockAddress ) ; + memset( Eblock_current, 0xFF, 4096 ) ; // Now erased + } + + s = Eblock_buffer ; + address = EblockAddress ; + for ( i = 0 ; i < 16 ; i += 1 ) // pages in block + { + x = eeprom_page_erased( s ) ; + if ( x == 0 ) // Not blank + { +//EeWriteCount += 1 ; + AT25D_Write( s, 256, address ) ; + } + s += 256 ; + address += 256 ; + } + EblockAddress = -1 ; + EE_timer = 0 ; +} + + +void readBlock( uint32_t block_address ) +{ + AT25D_Read( Eblock_buffer, 4096, block_address ) ; // read block to write to + memcpy( Eblock_current, Eblock_buffer, 4096 ) ; // Copy for erase checking + + EblockAddress = block_address ; +} + +uint32_t ee32_write( const uint8_t *buffer, uint32_t sector, uint32_t count ) +{ + // EEPROM write + uint32_t startMemoryOffset ; + uint32_t memoryOffset ; + uint32_t bytesToWrite ; + uint8_t *pBuffer ; + int32_t block_address ; + + if ( sector == 0 ) + { + if ( isEepromStart( (uint8_t *) buffer ) ) + { + EepromBlocked = 0 ; + } + else + { + EepromBlocked = 1 ; + } + } + + if ( EepromBlocked ) + { + return 1 ; + } + + startMemoryOffset = sector ; + startMemoryOffset *= 512 ; // Byte address into EEPROM + memoryOffset = startMemoryOffset; + + bytesToWrite = count * 512 ; + + unprotect_eeprom() ; + + pBuffer = (uint8_t *) buffer ; + + block_address = memoryOffset &0xFFFFF000 ; // 4k boundary + + if ( EblockAddress != -1 ) + { + // Ram copy is dirty + if ( EblockAddress != block_address ) + { + // flush buffer + writeBlock() ; + } + } + + // Now check for pre-read + if ( EblockAddress != block_address ) + { + readBlock( block_address ) ; + +// // Check to see if it is blank +// x = eeprom_block_erased( Eblock_buffer ) ; +// if ( x == 0 ) +// { +// AT25D_EraseBlock( block_address ) ; +// } + } + + while (bytesToWrite) + { + uint32_t bytes_to_copy ; + uint32_t i ; + uint8_t *s ; + uint8_t *dest ; + + if ( EblockAddress != block_address ) + { + readBlock( block_address ) ; + } + + dest = Eblock_buffer + (memoryOffset & 0x0FFF ) ; + s = pBuffer ; + bytes_to_copy = 4096 - ( memoryOffset - block_address ) ; + if ( bytes_to_copy > bytesToWrite ) + { + bytes_to_copy = bytesToWrite ; + } + for ( i = 0 ; i < bytes_to_copy ; i += 1 ) + { + *dest++ = *s++ ; + } + memoryOffset += bytes_to_copy ; + bytesToWrite -= bytes_to_copy ; + + if ( dest > &Eblock_buffer[4095] ) + { + // copied data past end + writeBlock() ; + } + else + { + EE_timer = 30 ; // Write dirty block in 0.3 secs + } + } + return 1 ; +} + +uint32_t AT25D_EraseBlock( uint32_t memoryOffset ) +{ + register uint8_t *p ; + register uint32_t x ; + +// EeEraseCount += 1 ; + + eeprom_write_enable() ; + p = Spi_tx_buf ; + *p = 0x20 ; // Block Erase command + *(p+1) = memoryOffset >> 16 ; + *(p+2) = memoryOffset >> 8 ; + *(p+3) = memoryOffset ; // 3 bytes address + x = spi_operation( p, Spi_rx_buf, 4 ) ; + + eeprom_wait_busy() ; + return x ; +} + + diff --git a/radio/bootloader/ccsbcs.c b/radio/bootloader/ccsbcs.c new file mode 100644 index 000000000..e5634173b --- /dev/null +++ b/radio/bootloader/ccsbcs.c @@ -0,0 +1,540 @@ +/*------------------------------------------------------------------------*/ +/* Unicode - Local code bidirectional converter (C)ChaN, 2012 */ +/* (SBCS code pages) */ +/*------------------------------------------------------------------------*/ +/* 437 U.S. (OEM) +/ 720 Arabic (OEM) +/ 1256 Arabic (Windows) +/ 737 Greek (OEM) +/ 1253 Greek (Windows) +/ 1250 Central Europe (Windows) +/ 775 Baltic (OEM) +/ 1257 Baltic (Windows) +/ 850 Multilingual Latin 1 (OEM) +/ 852 Latin 2 (OEM) +/ 1252 Latin 1 (Windows) +/ 855 Cyrillic (OEM) +/ 1251 Cyrillic (Windows) +/ 866 Russian (OEM) +/ 857 Turkish (OEM) +/ 1254 Turkish (Windows) +/ 858 Multilingual Latin 1 + Euro (OEM) +/ 862 Hebrew (OEM) +/ 1255 Hebrew (Windows) +/ 874 Thai (OEM, Windows) +/ 1258 Vietnam (OEM, Windows) +*/ + +#include "ff.h" + + +#if _CODE_PAGE == 437 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP437(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, + 0x00FF, 0x00D6, 0x00DC, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, + 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, + 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 720 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP720(0x80-0xFF) to Unicode conversion table */ + 0x0000, 0x0000, 0x00E9, 0x00E2, 0x0000, 0x00E0, 0x0000, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0651, 0x0652, 0x00F4, 0x00A4, 0x0640, 0x00FB, 0x00F9, + 0x0621, 0x0622, 0x0623, 0x0624, 0x00A3, 0x0625, 0x0626, 0x0627, + 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, + 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x0636, 0x0637, 0x0638, 0x0639, 0x063A, 0x0641, 0x00B5, 0x0642, + 0x0643, 0x0644, 0x0645, 0x0646, 0x0647, 0x0648, 0x0649, 0x064A, + 0x2261, 0x064B, 0x064C, 0x064D, 0x064E, 0x064F, 0x0650, 0x2248, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 737 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP737(0x80-0xFF) to Unicode conversion table */ + 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x0398, + 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, 0x03A0, + 0x03A1, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, + 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, 0x03B8, + 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, + 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x03C5, 0x03C6, 0x03C7, 0x03C8, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03C9, 0x03AC, 0x03AD, 0x03AE, 0x03CA, 0x03AF, 0x03CC, 0x03CD, + 0x03CB, 0x03CE, 0x0386, 0x0388, 0x0389, 0x038A, 0x038C, 0x038E, + 0x038F, 0x00B1, 0x2265, 0x2264, 0x03AA, 0x03AB, 0x00F7, 0x2248, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 775 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP775(0x80-0xFF) to Unicode conversion table */ + 0x0106, 0x00FC, 0x00E9, 0x0101, 0x00E4, 0x0123, 0x00E5, 0x0107, + 0x0142, 0x0113, 0x0156, 0x0157, 0x012B, 0x0179, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x014D, 0x00F6, 0x0122, 0x00A2, 0x015A, + 0x015B, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x00A4, + 0x0100, 0x012A, 0x00F3, 0x017B, 0x017C, 0x017A, 0x201D, 0x00A6, + 0x00A9, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x0141, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0104, 0x010C, 0x0118, + 0x0116, 0x2563, 0x2551, 0x2557, 0x255D, 0x012E, 0x0160, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0172, 0x016A, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x017D, + 0x0105, 0x010D, 0x0119, 0x0117, 0x012F, 0x0161, 0x0173, 0x016B, + 0x017E, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x00D3, 0x00DF, 0x014C, 0x0143, 0x00F5, 0x00D5, 0x00B5, 0x0144, + 0x0136, 0x0137, 0x013B, 0x013C, 0x0146, 0x0112, 0x0145, 0x2019, + 0x00AD, 0x00B1, 0x201C, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x201E, + 0x00B0, 0x2219, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 850 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP850(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, + 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, + 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, + 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x0131, 0x00CD, 0x00CE, + 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, + 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4, + 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, + 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 852 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP852(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x016F, 0x0107, 0x00E7, + 0x0142, 0x00EB, 0x0150, 0x0151, 0x00EE, 0x0179, 0x00C4, 0x0106, + 0x00C9, 0x0139, 0x013A, 0x00F4, 0x00F6, 0x013D, 0x013E, 0x015A, + 0x015B, 0x00D6, 0x00DC, 0x0164, 0x0165, 0x0141, 0x00D7, 0x010D, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x0104, 0x0105, 0x017D, 0x017E, + 0x0118, 0x0119, 0x00AC, 0x017A, 0x010C, 0x015F, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x011A, + 0x015E, 0x2563, 0x2551, 0x2557, 0x255D, 0x017B, 0x017C, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0102, 0x0103, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x0111, 0x0110, 0x010E, 0x00CB, 0x010F, 0x0147, 0x00CD, 0x00CE, + 0x011B, 0x2518, 0x250C, 0x2588, 0x2584, 0x0162, 0x016E, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x0143, 0x0144, 0x0148, 0x0160, 0x0161, + 0x0154, 0x00DA, 0x0155, 0x0170, 0x00FD, 0x00DD, 0x0163, 0x00B4, + 0x00AD, 0x02DD, 0x02DB, 0x02C7, 0x02D8, 0x00A7, 0x00F7, 0x00B8, + 0x00B0, 0x00A8, 0x02D9, 0x0171, 0x0158, 0x0159, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 855 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP855(0x80-0xFF) to Unicode conversion table */ + 0x0452, 0x0402, 0x0453, 0x0403, 0x0451, 0x0401, 0x0454, 0x0404, + 0x0455, 0x0405, 0x0456, 0x0406, 0x0457, 0x0407, 0x0458, 0x0408, + 0x0459, 0x0409, 0x045A, 0x040A, 0x045B, 0x040B, 0x045C, 0x040C, + 0x045E, 0x040E, 0x045F, 0x040F, 0x044E, 0x042E, 0x044A, 0x042A, + 0x0430, 0x0410, 0x0431, 0x0411, 0x0446, 0x0426, 0x0434, 0x0414, + 0x0435, 0x0415, 0x0444, 0x0424, 0x0433, 0x0413, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0445, 0x0425, 0x0438, + 0x0418, 0x2563, 0x2551, 0x2557, 0x255D, 0x0439, 0x0419, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x043A, 0x041A, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x043B, 0x041B, 0x043C, 0x041C, 0x043D, 0x041D, 0x043E, 0x041E, + 0x043F, 0x2518, 0x250C, 0x2588, 0x2584, 0x041F, 0x044F, 0x2580, + 0x042F, 0x0440, 0x0420, 0x0441, 0x0421, 0x0442, 0x0422, 0x0443, + 0x0423, 0x0436, 0x0416, 0x0432, 0x0412, 0x044C, 0x042C, 0x2116, + 0x00AD, 0x044B, 0x042B, 0x0437, 0x0417, 0x0448, 0x0428, 0x044D, + 0x042D, 0x0449, 0x0429, 0x0447, 0x0427, 0x00A7, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 857 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP857(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0131, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, + 0x0130, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x015E, 0x015F, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x011E, 0x011F, + 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, + 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x00BA, 0x00AA, 0x00CA, 0x00CB, 0x00C8, 0x0000, 0x00CD, 0x00CE, + 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x0000, + 0x00D7, 0x00DA, 0x00DB, 0x00D9, 0x00EC, 0x00FF, 0x00AF, 0x00B4, + 0x00AD, 0x00B1, 0x0000, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, + 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 858 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP858(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, + 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, + 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, + 0x00A9, 0x2563, 0x2551, 0x2557, 0x2550, 0x00A2, 0x00A5, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x20AC, 0x00CD, 0x00CE, + 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00C6, 0x00CC, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, + 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4, + 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, + 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 862 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP862(0x80-0xFF) to Unicode conversion table */ + 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, + 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF, + 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, + 0x05E8, 0x05E9, 0x05EA, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, + 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, + 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 866 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP866(0x80-0xFF) to Unicode conversion table */ + 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, + 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, + 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, + 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, + 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, + 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, + 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F, + 0x0401, 0x0451, 0x0404, 0x0454, 0x0407, 0x0457, 0x040E, 0x045E, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x2116, 0x00A4, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 874 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP874(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x0000, 0x0000, 0x0000, 0x2026, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x00A0, 0x0E01, 0x0E02, 0x0E03, 0x0E04, 0x0E05, 0x0E06, 0x0E07, + 0x0E08, 0x0E09, 0x0E0A, 0x0E0B, 0x0E0C, 0x0E0D, 0x0E0E, 0x0E0F, + 0x0E10, 0x0E11, 0x0E12, 0x0E13, 0x0E14, 0x0E15, 0x0E16, 0x0E17, + 0x0E18, 0x0E19, 0x0E1A, 0x0E1B, 0x0E1C, 0x0E1D, 0x0E1E, 0x0E1F, + 0x0E20, 0x0E21, 0x0E22, 0x0E23, 0x0E24, 0x0E25, 0x0E26, 0x0E27, + 0x0E28, 0x0E29, 0x0E2A, 0x0E2B, 0x0E2C, 0x0E2D, 0x0E2E, 0x0E2F, + 0x0E30, 0x0E31, 0x0E32, 0x0E33, 0x0E34, 0x0E35, 0x0E36, 0x0E37, + 0x0E38, 0x0E39, 0x0E3A, 0x0000, 0x0000, 0x0000, 0x0000, 0x0E3F, + 0x0E40, 0x0E41, 0x0E42, 0x0E43, 0x0E44, 0x0E45, 0x0E46, 0x0E47, + 0x0E48, 0x0E49, 0x0E4A, 0x0E4B, 0x0E4C, 0x0E4D, 0x0E4E, 0x0E4F, + 0x0E50, 0x0E51, 0x0E52, 0x0E53, 0x0E54, 0x0E55, 0x0E56, 0x0E57, + 0x0E58, 0x0E59, 0x0E5A, 0x0E5B, 0x0000, 0x0000, 0x0000, 0x0000 +}; + +#elif _CODE_PAGE == 1250 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1250(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021, + 0x0000, 0x2030, 0x0160, 0x2039, 0x015A, 0x0164, 0x017D, 0x0179, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x0000, 0x2122, 0x0161, 0x203A, 0x015B, 0x0165, 0x017E, 0x017A, + 0x00A0, 0x02C7, 0x02D8, 0x0141, 0x00A4, 0x0104, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x015E, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x017B, + 0x00B0, 0x00B1, 0x02DB, 0x0142, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x0105, 0x015F, 0x00BB, 0x013D, 0x02DD, 0x013E, 0x017C, + 0x0154, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x0139, 0x0106, 0x00C7, + 0x010C, 0x00C9, 0x0118, 0x00CB, 0x011A, 0x00CD, 0x00CE, 0x010E, + 0x0110, 0x0143, 0x0147, 0x00D3, 0x00D4, 0x0150, 0x00D6, 0x00D7, + 0x0158, 0x016E, 0x00DA, 0x0170, 0x00DC, 0x00DD, 0x0162, 0x00DF, + 0x0155, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x013A, 0x0107, 0x00E7, + 0x010D, 0x00E9, 0x0119, 0x00EB, 0x011B, 0x00ED, 0x00EE, 0x010F, + 0x0111, 0x0144, 0x0148, 0x00F3, 0x00F4, 0x0151, 0x00F6, 0x00F7, + 0x0159, 0x016F, 0x00FA, 0x0171, 0x00FC, 0x00FD, 0x0163, 0x02D9 +}; + +#elif _CODE_PAGE == 1251 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1251(0x80-0xFF) to Unicode conversion table */ + 0x0402, 0x0403, 0x201A, 0x0453, 0x201E, 0x2026, 0x2020, 0x2021, + 0x20AC, 0x2030, 0x0409, 0x2039, 0x040A, 0x040C, 0x040B, 0x040F, + 0x0452, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x0000, 0x2111, 0x0459, 0x203A, 0x045A, 0x045C, 0x045B, 0x045F, + 0x00A0, 0x040E, 0x045E, 0x0408, 0x00A4, 0x0490, 0x00A6, 0x00A7, + 0x0401, 0x00A9, 0x0404, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x0407, + 0x00B0, 0x00B1, 0x0406, 0x0456, 0x0491, 0x00B5, 0x00B6, 0x00B7, + 0x0451, 0x2116, 0x0454, 0x00BB, 0x0458, 0x0405, 0x0455, 0x0457, + 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, + 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, + 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, + 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, + 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, + 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, + 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, + 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F +}; + +#elif _CODE_PAGE == 1252 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1252(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x017D, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x017E, 0x0178, + 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, + 0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7, + 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF, + 0x00D0, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7, + 0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x00DD, 0x00DE, 0x00DF, + 0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7, + 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF, + 0x00F0, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7, + 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x00FD, 0x00FE, 0x00FF +}; + +#elif _CODE_PAGE == 1253 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1253(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x0000, 0x2030, 0x0000, 0x2039, 0x000C, 0x0000, 0x0000, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000, + 0x00A0, 0x0385, 0x0386, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x0000, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x2015, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x0384, 0x00B5, 0x00B6, 0x00B7, + 0x0388, 0x0389, 0x038A, 0x00BB, 0x038C, 0x00BD, 0x038E, 0x038F, + 0x0390, 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, + 0x0398, 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, + 0x03A0, 0x03A1, 0x0000, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, + 0x03A8, 0x03A9, 0x03AA, 0x03AD, 0x03AC, 0x03AD, 0x03AE, 0x03AF, + 0x03B0, 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, + 0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, + 0x03C0, 0x03C1, 0x03C2, 0x03C3, 0x03C4, 0x03C5, 0x03C6, 0x03C7, + 0x03C8, 0x03C9, 0x03CA, 0x03CB, 0x03CC, 0x03CD, 0x03CE, 0x0000 +}; + +#elif _CODE_PAGE == 1254 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1254(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x210A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178, + 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, + 0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7, + 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF, + 0x011E, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7, + 0x00D8, 0x00D9, 0x00DA, 0x00BD, 0x00DC, 0x0130, 0x015E, 0x00DF, + 0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7, + 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF, + 0x011F, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7, + 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x0131, 0x015F, 0x00FF +}; + +#elif _CODE_PAGE == 1255 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1255(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x02C6, 0x2030, 0x0000, 0x2039, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x02DC, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000, + 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x00D7, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x00F7, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, + 0x05B0, 0x05B1, 0x05B2, 0x05B3, 0x05B4, 0x05B5, 0x05B6, 0x05B7, + 0x05B8, 0x05B9, 0x0000, 0x05BB, 0x05BC, 0x05BD, 0x05BE, 0x05BF, + 0x05C0, 0x05C1, 0x05C2, 0x05C3, 0x05F0, 0x05F1, 0x05F2, 0x05F3, + 0x05F4, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, + 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF, + 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, + 0x05E8, 0x05E9, 0x05EA, 0x0000, 0x0000, 0x200E, 0x200F, 0x0000 +}; + +#elif _CODE_PAGE == 1256 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1256(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x067E, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x02C6, 0x2030, 0x0679, 0x2039, 0x0152, 0x0686, 0x0698, 0x0688, + 0x06AF, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x06A9, 0x2122, 0x0691, 0x203A, 0x0153, 0x200C, 0x200D, 0x06BA, + 0x00A0, 0x060C, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x06BE, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x061B, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x061F, + 0x06C1, 0x0621, 0x0622, 0x0623, 0x0624, 0x0625, 0x0626, 0x0627, + 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, + 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x0636, 0x00D7, + 0x0637, 0x0638, 0x0639, 0x063A, 0x0640, 0x0640, 0x0642, 0x0643, + 0x00E0, 0x0644, 0x00E2, 0x0645, 0x0646, 0x0647, 0x0648, 0x00E7, + 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0649, 0x064A, 0x00EE, 0x00EF, + 0x064B, 0x064C, 0x064D, 0x064E, 0x00F4, 0x064F, 0x0650, 0x00F7, + 0x0651, 0x00F9, 0x0652, 0x00FB, 0x00FC, 0x200E, 0x200F, 0x06D2 +} + +#elif _CODE_PAGE == 1257 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1257(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021, + 0x0000, 0x2030, 0x0000, 0x2039, 0x0000, 0x00A8, 0x02C7, 0x00B8, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x00AF, 0x02DB, 0x0000, + 0x00A0, 0x0000, 0x00A2, 0x00A3, 0x00A4, 0x0000, 0x00A6, 0x00A7, + 0x00D8, 0x00A9, 0x0156, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x0157, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00E6, + 0x0104, 0x012E, 0x0100, 0x0106, 0x00C4, 0x00C5, 0x0118, 0x0112, + 0x010C, 0x00C9, 0x0179, 0x0116, 0x0122, 0x0136, 0x012A, 0x013B, + 0x0160, 0x0143, 0x0145, 0x00D3, 0x014C, 0x00D5, 0x00D6, 0x00D7, + 0x0172, 0x0141, 0x015A, 0x016A, 0x00DC, 0x017B, 0x017D, 0x00DF, + 0x0105, 0x012F, 0x0101, 0x0107, 0x00E4, 0x00E5, 0x0119, 0x0113, + 0x010D, 0x00E9, 0x017A, 0x0117, 0x0123, 0x0137, 0x012B, 0x013C, + 0x0161, 0x0144, 0x0146, 0x00F3, 0x014D, 0x00F5, 0x00F6, 0x00F7, + 0x0173, 0x014E, 0x015B, 0x016B, 0x00FC, 0x017C, 0x017E, 0x02D9 +}; + +#elif _CODE_PAGE == 1258 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1258(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x02C6, 0x2030, 0x0000, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x02DC, 0x2122, 0x0000, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178, + 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, + 0x00C0, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x00C5, 0x00C6, 0x00C7, + 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x0300, 0x00CD, 0x00CE, 0x00CF, + 0x0110, 0x00D1, 0x0309, 0x00D3, 0x00D4, 0x01A0, 0x00D6, 0x00D7, + 0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x01AF, 0x0303, 0x00DF, + 0x00E0, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x00E5, 0x00E6, 0x00E7, + 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0301, 0x00ED, 0x00EE, 0x00EF, + 0x0111, 0x00F1, 0x0323, 0x00F3, 0x00F4, 0x01A1, 0x00F6, 0x00F7, + 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x01B0, 0x20AB, 0x00FF +}; + +#endif + + +#if !_TBLDEF || !_USE_LFN +#error This file is not needed in current configuration. Remove from the project. +#endif + + +WCHAR ff_convert ( /* Converted character, Returns zero on error */ + WCHAR chr, /* Character code to be converted */ + UINT dir /* 0: Unicode to OEMCP, 1: OEMCP to Unicode */ +) +{ + WCHAR c; + + + if (chr < 0x80) { /* ASCII */ + c = chr; + + } else { + if (dir) { /* OEMCP to Unicode */ + c = (chr >= 0x100) ? 0 : Tbl[chr - 0x80]; + + } else { /* Unicode to OEMCP */ + for (c = 0; c < 0x80; c++) { + if (chr == Tbl[c]) break; + } + c = (c + 0x80) & 0xFF; + } + } + + return c; +} + + +WCHAR ff_wtoupper ( /* Upper converted character */ + WCHAR chr /* Input character */ +) +{ + static const WCHAR tbl_lower[] = { 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0xA1, 0x00A2, 0x00A3, 0x00A5, 0x00AC, 0x00AF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0x0FF, 0x101, 0x103, 0x105, 0x107, 0x109, 0x10B, 0x10D, 0x10F, 0x111, 0x113, 0x115, 0x117, 0x119, 0x11B, 0x11D, 0x11F, 0x121, 0x123, 0x125, 0x127, 0x129, 0x12B, 0x12D, 0x12F, 0x131, 0x133, 0x135, 0x137, 0x13A, 0x13C, 0x13E, 0x140, 0x142, 0x144, 0x146, 0x148, 0x14B, 0x14D, 0x14F, 0x151, 0x153, 0x155, 0x157, 0x159, 0x15B, 0x15D, 0x15F, 0x161, 0x163, 0x165, 0x167, 0x169, 0x16B, 0x16D, 0x16F, 0x171, 0x173, 0x175, 0x177, 0x17A, 0x17C, 0x17E, 0x192, 0x3B1, 0x3B2, 0x3B3, 0x3B4, 0x3B5, 0x3B6, 0x3B7, 0x3B8, 0x3B9, 0x3BA, 0x3BB, 0x3BC, 0x3BD, 0x3BE, 0x3BF, 0x3C0, 0x3C1, 0x3C3, 0x3C4, 0x3C5, 0x3C6, 0x3C7, 0x3C8, 0x3C9, 0x3CA, 0x430, 0x431, 0x432, 0x433, 0x434, 0x435, 0x436, 0x437, 0x438, 0x439, 0x43A, 0x43B, 0x43C, 0x43D, 0x43E, 0x43F, 0x440, 0x441, 0x442, 0x443, 0x444, 0x445, 0x446, 0x447, 0x448, 0x449, 0x44A, 0x44B, 0x44C, 0x44D, 0x44E, 0x44F, 0x451, 0x452, 0x453, 0x454, 0x455, 0x456, 0x457, 0x458, 0x459, 0x45A, 0x45B, 0x45C, 0x45E, 0x45F, 0x2170, 0x2171, 0x2172, 0x2173, 0x2174, 0x2175, 0x2176, 0x2177, 0x2178, 0x2179, 0x217A, 0x217B, 0x217C, 0x217D, 0x217E, 0x217F, 0xFF41, 0xFF42, 0xFF43, 0xFF44, 0xFF45, 0xFF46, 0xFF47, 0xFF48, 0xFF49, 0xFF4A, 0xFF4B, 0xFF4C, 0xFF4D, 0xFF4E, 0xFF4F, 0xFF50, 0xFF51, 0xFF52, 0xFF53, 0xFF54, 0xFF55, 0xFF56, 0xFF57, 0xFF58, 0xFF59, 0xFF5A, 0 }; + static const WCHAR tbl_upper[] = { 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x21, 0xFFE0, 0xFFE1, 0xFFE5, 0xFFE2, 0xFFE3, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0x178, 0x100, 0x102, 0x104, 0x106, 0x108, 0x10A, 0x10C, 0x10E, 0x110, 0x112, 0x114, 0x116, 0x118, 0x11A, 0x11C, 0x11E, 0x120, 0x122, 0x124, 0x126, 0x128, 0x12A, 0x12C, 0x12E, 0x130, 0x132, 0x134, 0x136, 0x139, 0x13B, 0x13D, 0x13F, 0x141, 0x143, 0x145, 0x147, 0x14A, 0x14C, 0x14E, 0x150, 0x152, 0x154, 0x156, 0x158, 0x15A, 0x15C, 0x15E, 0x160, 0x162, 0x164, 0x166, 0x168, 0x16A, 0x16C, 0x16E, 0x170, 0x172, 0x174, 0x176, 0x179, 0x17B, 0x17D, 0x191, 0x391, 0x392, 0x393, 0x394, 0x395, 0x396, 0x397, 0x398, 0x399, 0x39A, 0x39B, 0x39C, 0x39D, 0x39E, 0x39F, 0x3A0, 0x3A1, 0x3A3, 0x3A4, 0x3A5, 0x3A6, 0x3A7, 0x3A8, 0x3A9, 0x3AA, 0x410, 0x411, 0x412, 0x413, 0x414, 0x415, 0x416, 0x417, 0x418, 0x419, 0x41A, 0x41B, 0x41C, 0x41D, 0x41E, 0x41F, 0x420, 0x421, 0x422, 0x423, 0x424, 0x425, 0x426, 0x427, 0x428, 0x429, 0x42A, 0x42B, 0x42C, 0x42D, 0x42E, 0x42F, 0x401, 0x402, 0x403, 0x404, 0x405, 0x406, 0x407, 0x408, 0x409, 0x40A, 0x40B, 0x40C, 0x40E, 0x40F, 0x2160, 0x2161, 0x2162, 0x2163, 0x2164, 0x2165, 0x2166, 0x2167, 0x2168, 0x2169, 0x216A, 0x216B, 0x216C, 0x216D, 0x216E, 0x216F, 0xFF21, 0xFF22, 0xFF23, 0xFF24, 0xFF25, 0xFF26, 0xFF27, 0xFF28, 0xFF29, 0xFF2A, 0xFF2B, 0xFF2C, 0xFF2D, 0xFF2E, 0xFF2F, 0xFF30, 0xFF31, 0xFF32, 0xFF33, 0xFF34, 0xFF35, 0xFF36, 0xFF37, 0xFF38, 0xFF39, 0xFF3A, 0 }; + int i; + + + for (i = 0; tbl_lower[i] && chr != tbl_lower[i]; i++) ; + + return tbl_lower[i] ? tbl_upper[i] : chr; +} diff --git a/radio/bootloader/core_cm3.c b/radio/bootloader/core_cm3.c new file mode 100644 index 000000000..6f4106433 --- /dev/null +++ b/radio/bootloader/core_cm3.c @@ -0,0 +1,880 @@ +/**************************************************************************//** + * @file core_cm3.c + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File + * @version V1.30 + * @date 30. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + +uint32_t __get_PSP(void) ; +void __set_PSP(uint32_t topOfProcStack) ; +uint32_t __get_MSP(void) ; +void __set_MSP(uint32_t mainStackPointer) ; +uint32_t __REV16(uint16_t value) ; +int32_t __REVSH(int16_t value) ; +uint32_t __RBIT(uint32_t value) ; +uint8_t __LDREXB(uint8_t *addr) ; +uint16_t __LDREXH(uint16_t *addr) ; +uint32_t __LDREXW(uint32_t *addr) ; +uint32_t __STREXB(uint8_t value, uint8_t *addr) ; +uint32_t __STREXH(uint16_t value, uint16_t *addr) ; +uint32_t __STREXW(uint32_t value, uint32_t *addr) ; + +uint32_t __get_BASEPRI(void) ; +void __set_BASEPRI(uint32_t basePri) ; +uint32_t __get_PRIMASK(void) ; +void __set_PRIMASK(uint32_t priMask) ; +uint32_t __get_FAULTMASK(void) ; +void __set_FAULTMASK(uint32_t faultMask) ; +uint32_t __get_CONTROL(void) ; +void __set_CONTROL(uint32_t control) ; +uint32_t __REV(uint32_t value) ; + +void revert_osc( void ) ; +void sam_boot( void ) ; +void sam_bootx( void ) ; +void run_application( void ) ; + + +/* ################### Compiler specific Intrinsics ########################### */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +__ASM uint32_t __get_PSP(void) +{ + mrs r0, psp + bx lr +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +__ASM void __set_PSP(uint32_t topOfProcStack) +{ + msr psp, r0 + bx lr +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +__ASM uint32_t __get_MSP(void) +{ + mrs r0, msp + bx lr +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +__ASM void __set_MSP(uint32_t mainStackPointer) +{ + msr msp, r0 + bx lr +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +__ASM uint32_t __REV16(uint16_t value) +{ + rev16 r0, r0 + bx lr +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +__ASM int32_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} + + +#if (__ARMCC_VERSION < 400000) + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +__ASM void __CLREX(void) +{ + clrex +} + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +__ASM uint32_t __get_BASEPRI(void) +{ + mrs r0, basepri + bx lr +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +__ASM void __set_BASEPRI(uint32_t basePri) +{ + msr basepri, r0 + bx lr +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +__ASM uint32_t __get_PRIMASK(void) +{ + mrs r0, primask + bx lr +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +__ASM void __set_PRIMASK(uint32_t priMask) +{ + msr primask, r0 + bx lr +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +__ASM uint32_t __get_FAULTMASK(void) +{ + mrs r0, faultmask + bx lr +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +__ASM void __set_FAULTMASK(uint32_t faultMask) +{ + msr faultmask, r0 + bx lr +} + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +__ASM uint32_t __get_CONTROL(void) +{ + mrs r0, control + bx lr +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +__ASM void __set_CONTROL(uint32_t control) +{ + msr control, r0 + bx lr +} + +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#pragma diag_suppress=Pe940 + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +uint32_t __get_PSP(void) +{ + __ASM("mrs r0, psp"); + __ASM("bx lr"); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM("msr psp, r0"); + __ASM("bx lr"); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +uint32_t __get_MSP(void) +{ + __ASM("mrs r0, msp"); + __ASM("bx lr"); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM("msr msp, r0"); + __ASM("bx lr"); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + __ASM("rev16 r0, r0"); + __ASM("bx lr"); +} + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +uint32_t __RBIT(uint32_t value) +{ + __ASM("rbit r0, r0"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit values) + */ +uint8_t __LDREXB(uint8_t *addr) +{ + __ASM("ldrexb r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +uint16_t __LDREXH(uint16_t *addr) +{ + __ASM("ldrexh r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +uint32_t __LDREXW(uint32_t *addr) +{ + __ASM("ldrex r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + __ASM("strexb r0, r0, [r1]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + __ASM("strexh r0, r0, [r1]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + __ASM("strex r0, r0, [r1]"); + __ASM("bx lr"); +} + +#pragma diag_default=Pe940 + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +#ifndef BOOT +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +/*extern uint32_t __get_PSP(void) __attribute__( ( naked ) ); */ +uint32_t __get_PSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, psp\n\t" + "MOV r0, %0 \n\t" + "BX lr \n\t" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +/*void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); */ +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n\t" + "BX lr \n\t" : : "r" (topOfProcStack) ); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +/*uint32_t __get_MSP(void) __attribute__( ( naked ) ); */ +uint32_t __get_MSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, msp\n\t" + "MOV r0, %0 \n\t" + "BX lr \n\t" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +/*void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); */ +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n\t" + "BX lr \n\t" : : "r" (topOfMainStack) ); +} + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +uint32_t __get_BASEPRI(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +uint32_t __get_PRIMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +uint32_t __get_FAULTMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +uint32_t __get_CONTROL(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + +#endif + +/** + * @brief Reverse byte order in integer value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +uint32_t __REV(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#ifndef BOOT +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +int32_t __REVSH(int16_t value) +{ + uint32_t result=0; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +uint32_t __RBIT(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +uint8_t __LDREXB(uint8_t *addr) +{ + uint8_t result=0; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +uint16_t __LDREXH(uint16_t *addr) +{ + uint16_t result=0; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +uint32_t __LDREXW(uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} +#endif + +#ifdef BOOT +void run_application() +{ + __ASM(" mov.w r1, #4227072"); // 0x408000 + __ASM(" movw r0, #60680"); // 0xED08 + __ASM(" movt r0, #57344"); // 0xE000 + __ASM(" str r1, [r0, #0]"); // Set the VTOR + +// __ASM("mov.w r3, #0"); // 0x0000 +// __ASM("movt r3, #128"); // 0x0080 + __ASM("ldr r0, [r1, #0]"); // Stack pointer value + __ASM("msr msp, r0"); // Set it + __ASM("ldr r0, [r1, #4]"); // Reset address + __ASM("mov.w r1, #1"); + __ASM("orr r0, r1"); // Set lsbit + __ASM("bx r0"); // Execute application +} + +#endif + +#ifndef BOOT + +void sam_boot() +{ + revert_osc() ; + + __ASM(" mov.w r1, #8388608"); + __ASM(" movw r0, #60680"); + __ASM(" movt r0, #57344"); + __ASM(" str r1, [r0, #0]"); // Set the VTOR + + __ASM("mov.w r3, #0"); + __ASM("movt r3, #128"); + __ASM("ldr r0, [r3, #0]"); + __ASM("msr msp, r0"); + __ASM("ldr r0, [r3, #4]"); + __ASM("mov.w r3, #1"); + __ASM("orr r0, r3"); + __ASM("bx r0"); +} +#endif + +#ifdef BOOT + +void sam_bootx() +{ + __ASM(" mov.w r1, #8388608"); + __ASM(" movw r0, #60680"); + __ASM(" movt r0, #57344"); + __ASM(" str r1, [r0, #0]"); // Set the VTOR + + __ASM("mov.w r3, #0"); + __ASM("movt r3, #128"); + __ASM("ldr r0, [r3, #0]"); + __ASM("msr msp, r0"); + __ASM("ldr r0, [r3, #4]"); + __ASM("mov.w r3, #1"); + __ASM("orr r0, r3"); + __ASM("bx r0"); +} + +#endif + + +#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif diff --git a/radio/bootloader/crt.c b/radio/bootloader/crt.c new file mode 100644 index 000000000..158c5a27a --- /dev/null +++ b/radio/bootloader/crt.c @@ -0,0 +1,147 @@ +/**************************************************************************** +* Copyright (c) 2011 by Michael Fischer. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. Neither the name of the author nor the names of its contributors may +* be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +* SUCH DAMAGE. +* +**************************************************************************** +* History: +* +* 09.04.2011 mifi First Version +* 29.04.2011 mifi Call SystemInit, and set the Vector Table Offset +* before copy of data and bss segment. +****************************************************************************/ +#define __CRT_C__ + +#include + +/*=========================================================================*/ +/* DEFINE: All extern Data */ +/*=========================================================================*/ +/* + * The next data are defined by the linker script. + */ +extern unsigned long _stext; +extern unsigned long _etext; +extern unsigned long _sdata; +extern unsigned long _edata; +extern unsigned long _sbss; +extern unsigned long _ebss; +extern unsigned long _estack; + +/* This is the main */ +extern int main (void); + +/*=========================================================================*/ +/* DEFINE: Prototypes */ +/*=========================================================================*/ +extern uint32_t SystemInit (void) ; // __attribute__((weak)); + +/*=========================================================================*/ +/* DEFINE: All code exported */ +/*=========================================================================*/ + +/***************************************************************************/ +/* SystemInit */ +/* */ +/* SystemInit is a function which is provided by the CMSIS interface. */ +/* If this function is not available, we need a function here to prevent */ +/* an error of the linker. Therefore this function is declared as weak. */ +/***************************************************************************/ +//uint32_t SystemInit (void) +//{ + +//} /* SystemInit */ + +extern uint32_t Master_frequency ; + +/***************************************************************************/ +/* ResetHandler */ +/* */ +/* This function is used for the C runtime initialisation, */ +/* for handling the .data and .bss segments. */ +/***************************************************************************/ +void ResetHandler (void) +{ + { + register uint32_t *pSrc; + register uint32_t *pDest; + register uint32_t m_freq ; + + /* + * Call the SystemInit code from CMSIS interface if available. + * SystemInit is a week function which can be override + * by an external function. + */ + m_freq = SystemInit(); + + /* + * Set the "Vector Table Offset Register". From the ARM + * documentation, we got the following information: + * + * Use the Vector Table Offset Register to determine: + * - if the vector table is in RAM or code memory + * - the vector table offset. + */ + *((uint32_t*)0xE000ED08) = (uint32_t)&_stext; + + /* + * Copy the initialized data of the ".data" segment + * from the flash to the are in the ram. + */ + pSrc = &_etext; + pDest = &_sdata; + while(pDest < &_edata) + { + *pDest++ = *pSrc++; + } + + /* + * Clear the ".bss" segment. + */ + pDest = &_sbss; + while(pDest < &_ebss) + { + *pDest++ = 0; + } + Master_frequency = m_freq ; + } + + /* + * And now the main function can be called. + * Scotty, energie... + */ + main(); + + /* + * In case there are problems with the + * "warp drive", stop here. + */ + while(1) {}; + +} /* ResetHandler */ + +/*** EOF ***/ diff --git a/radio/bootloader/diskio.cpp b/radio/bootloader/diskio.cpp new file mode 100644 index 000000000..2db16ad0b --- /dev/null +++ b/radio/bootloader/diskio.cpp @@ -0,0 +1,1195 @@ +/* + * Authors (alphabetical order) + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * open9x is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +/*-----------------------------------------------------------------------*/ +/* MMCv3/SDv1/SDv2 (in SPI mode) control module (C)ChaN, 2010 */ +/*-----------------------------------------------------------------------*/ +/* Only rcvr_spi(), xmit_spi(), disk_timerproc() and some macros */ +/* are platform dependent. */ +/*-----------------------------------------------------------------------*/ + +#include "radio.h" +//extern unsigned long Master_frequency ; +extern void delay2ms() ; +#ifdef BOOT +#define TRUE 1 +#endif + + +#ifndef BOOT +//#if !defined(SIMU) +//#include "CoOS.h" +//#endif +#endif + +#include "diskio.h" +#include "board.h" +#ifndef BOOT +#include "debug.h" +#endif +// States for initialising card +#define SD_ST_EMPTY 0 +#define SD_ST_INIT1 1 +#define SD_ST_INIT2 2 +#define SD_ST_IDLE 3 +#define SD_ST_READY 4 +#define SD_ST_IDENT 5 +#define SD_ST_STBY 6 +#define SD_ST_TRAN 7 +#define SD_ST_DATA 8 + +// Bits in status register of Sd card +#define STATUS_READY_FOR_DATA (1UL << 8) +#define STATUS_TRAN (4UL << 9) +#define STATUS_STATE (0xFUL << 9) + + + +uint32_t Card_ID[4] ; +uint32_t Card_SCR[2] ; +uint32_t Card_CSD[4] ; +uint32_t Card_state = SD_ST_EMPTY ; +uint32_t Sd_128_resp[4] ; +uint32_t Sd_rca ; +uint32_t Sd_status13 ; +uint32_t Cmd_A41_resp ; +uint32_t SpeedAllowed ; + +uint32_t Sd_retries ; + +/** + * Configure the MCI SDCBUS in the MCI_SDCR register. Only two modes available + * + * \param busWidth MCI bus width mode. 00: 1-bit, 10: 4-bit. + */ +uint32_t SD_SetBusWidth( uint32_t busWidth) +{ + uint32_t mciSdcr; + + if( (busWidth != HSMCI_SDCR_SDCBUS_1) && (busWidth != HSMCI_SDCR_SDCBUS_4) ) + { + return (uint32_t)-1; + } + + busWidth &= HSMCI_SDCR_SDCBUS_Msk ; + + mciSdcr = (HSMCI->HSMCI_SDCR & ~(uint32_t)(HSMCI_SDCR_SDCBUS_Msk)); + HSMCI->HSMCI_SDCR = mciSdcr | busWidth; + + return 0; +} + +#if 0 +/** + * Configure the MCI_CFG to enable the HS mode + * \param hsEnable 1 to enable, 0 to disable HS mode. + */ +void SD_EnableHsMode( uint8_t hsEnable) +{ + uint32_t cfgr; + + cfgr = HSMCI->HSMCI_CFG; + if (hsEnable) + { + cfgr |= HSMCI_CFG_HSMODE; + } + else + { + cfgr &= ~(uint32_t)HSMCI_CFG_HSMODE; + } + + HSMCI->HSMCI_CFG = cfgr; +} +#endif + +/** + * Configure the MCI CLKDIV in the MCI_MR register. The max. for MCI clock is + * MCK/2 and corresponds to CLKDIV = 0 + * \param mciSpeed MCI clock speed in Hz, 0 will not change current speed. + * \return The actual speed used, 0 for fail. + */ +uint32_t SD_SetSpeed( uint32_t mciSpeed ) +{ + uint32_t mciMr; + uint32_t clkdiv, divLimit; + + mciMr = HSMCI->HSMCI_MR & (~(uint32_t)HSMCI_MR_CLKDIV_Msk); + /* Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK) + * divided by (2*(CLKDIV+1)) + * mciSpeed = MCK / (2*(CLKDIV+1)) */ + if (mciSpeed > 0) + { + + divLimit = (Master_frequency / 2 / mciSpeed); + if ((Master_frequency / 2) % mciSpeed) divLimit ++; + + clkdiv = (Master_frequency / 2 / mciSpeed); + if (mciSpeed && clkdiv < divLimit) + clkdiv = divLimit; + if (clkdiv > 0) + clkdiv -= 1; + +// clkdiv = (Master_frequency / 2 / mciSpeed); +// /* Speed should not bigger than expired one */ +// if (mciSpeed < Master_frequency/2/clkdiv) +// { +// clkdiv++; +// } + +// if ( clkdiv > 0 ) +// { +// clkdiv -= 1; +// } + } + else + { + clkdiv = 0 ; + } + + /* Actual MCI speed */ + mciSpeed = Master_frequency / 2 / (clkdiv + 1); + /* Modify MR */ + HSMCI->HSMCI_MR = mciMr | clkdiv; + + return (mciSpeed); +} + +#if 0 +void SD_SetBlklen( uint32_t blklen ) +{ + uint32_t mciMr; + uint32_t clkdiv; + + mciMr = HSMCI->HSMCI_MR & (~(uint32_t)HSMCI_MR_BLKLEN); + /* Modify MR */ + HSMCI->HSMCI_MR = mciMr | blklen << 16 ; +} +#endif + +#if 0 +/** + * Reset MCI HW interface and disable it. + * \param keepSettings Keep old register settings, including + * _MR, _SDCR, _DTOR, _CSTOR, _DMA and _CFG. + */ +void SD_Reset( uint8_t keepSettings) +{ + Hsmci *pMciHw = HSMCI ; + + if (keepSettings) + { + uint32_t mr, sdcr, dtor, cstor; + uint32_t cfg; + mr = pMciHw->HSMCI_MR; + sdcr = pMciHw->HSMCI_SDCR; + dtor = pMciHw->HSMCI_DTOR; + cstor = pMciHw->HSMCI_CSTOR; + cfg = pMciHw->HSMCI_CFG; + pMciHw->HSMCI_CR = HSMCI_CR_SWRST ; // Reset + pMciHw->HSMCI_CR = HSMCI_CR_MCIDIS; // Disable + pMciHw->HSMCI_MR = mr; + pMciHw->HSMCI_SDCR = sdcr; + pMciHw->HSMCI_DTOR = dtor; + pMciHw->HSMCI_CSTOR = cstor; + pMciHw->HSMCI_CFG = cfg; + } + else + { + pMciHw->HSMCI_CR = HSMCI_CR_SWRST ; // Reset + pMciHw->HSMCI_CR = HSMCI_CR_MCIDIS; // Disable + } +} +#endif + + +uint32_t sdCommand(uint32_t cmd, uint32_t arg) +{ + uint32_t i; + Hsmci *phsmci = HSMCI; + + if (CardIsConnected()) + { + phsmci->HSMCI_ARGR = arg; + phsmci->HSMCI_CMDR = cmd; + + for (i = 0; i < 50000; i += 1) + { + if (phsmci->HSMCI_SR & HSMCI_SR_CMDRDY) + { + return 0; + } + } + return 1 ; // No response + } + else + { + return 1 ; // No Sdcard + } +} + + +#define SDMMC_APP_CMD (55| HSMCI_CMDR_SPCMD_STD \ + | HSMCI_CMDR_RSPTYP_48_BIT \ + | HSMCI_CMDR_TRCMD_NO_DATA \ + | HSMCI_CMDR_MAXLAT) + +uint32_t sd_cmd55() +{ + return sdCommand( SDMMC_APP_CMD, Sd_rca ) ; +} + +#define SDMMC_GO_IDLE_STATE (0 | HSMCI_CMDR_TRCMD_NO_DATA \ + | HSMCI_CMDR_SPCMD_STD ) + +// returns 0 = OK, non-zero = fail +uint32_t sd_cmd0() +{ + return sdCommand( SDMMC_GO_IDLE_STATE, 0 ) ; +} +#define SD_SEND_IF_COND (8 | HSMCI_CMDR_TRCMD_NO_DATA \ + | HSMCI_CMDR_SPCMD_STD \ + | HSMCI_CMDR_RSPTYP_48_BIT \ + | HSMCI_CMDR_OPDCMD /* BSS difference */ \ + | HSMCI_CMDR_MAXLAT ) + +#define SDMMC_SEND_STATUS_CMD (13 | HSMCI_CMDR_TRCMD_NO_DATA \ + | HSMCI_CMDR_SPCMD_STD \ + | HSMCI_CMDR_RSPTYP_48_BIT \ + | HSMCI_CMDR_MAXLAT ) + +// returns 0 = OK, non-zero = fail +uint32_t sd_cmd13(uint32_t *status) +{ + uint32_t result = sdCommand( SDMMC_SEND_STATUS_CMD, Sd_rca ) ; + if (result) + return result; + Sd_status13 = *status = HSMCI->HSMCI_RSPR[0]; + return 0 ; +} + +// returns 0 = OK, non-zero = fail +uint32_t sd_cmd8() +{ + return sdCommand( SD_SEND_IF_COND, 0X000001AA ) ; +} + +uint32_t sd_acmd41() +{ + uint32_t i; + Hsmci *phsmci = HSMCI; + + if (CardIsConnected()) { + sd_cmd55(); + phsmci->HSMCI_ARGR = 0x403F8000; + phsmci->HSMCI_CMDR = 0x00001069; + + for (i = 0; i < 30000; i += 1) { + if (phsmci->HSMCI_SR & HSMCI_SR_CMDRDY) { + break; + } + } + return Cmd_A41_resp = phsmci->HSMCI_RSPR[0] ; + } + else { + return 0; + } +} + +// Get Card ID +// returns 0 = OK, non-zero = fail +uint32_t sd_cmd2() +{ + uint32_t result = sdCommand( 0x00001082, 0 ) ; + if (result) + return result; + + Hsmci *phsmci = HSMCI ; + Card_ID[0] = phsmci->HSMCI_RSPR[0] ; + Card_ID[1] = phsmci->HSMCI_RSPR[1] ; + Card_ID[2] = phsmci->HSMCI_RSPR[2] ; + Card_ID[3] = phsmci->HSMCI_RSPR[3] ; + return 0 ; +} + +// Get new RCA +// returns 0 = OK, non-zero = fail +uint32_t sd_cmd3() +{ + uint32_t result = sdCommand( 0x00001043, 0 ) ; + if (result) + return result; + + Sd_rca = HSMCI->HSMCI_RSPR[0]; + return 0 ; +} + +// Get CSD +uint32_t sd_cmd9() +{ + uint32_t result = sdCommand( 0x00001089, Sd_rca ) ; + if (result) + return result; + + Hsmci *phsmci = HSMCI ; + + Card_CSD[0] = phsmci->HSMCI_RSPR[0] ; + Card_CSD[1] = phsmci->HSMCI_RSPR[1] ; + Card_CSD[2] = phsmci->HSMCI_RSPR[2] ; + Card_CSD[3] = phsmci->HSMCI_RSPR[3] ; + return 0 ; +} + +/** Cmd7 MCI, ac, R1/R1b */ +#define SDMMC_SELECT_CARD (7 | HSMCI_CMDR_TRCMD_NO_DATA \ + | HSMCI_CMDR_SPCMD_STD \ + | HSMCI_CMDR_RSPTYP_R1B \ + | HSMCI_CMDR_MAXLAT /* TODO not the same */ ) + +// Select Card +uint32_t sd_cmd7() +{ + return sdCommand( SDMMC_SELECT_CARD, Sd_rca ) ; +} + +#define SD_SEND_SCR (51 | HSMCI_CMDR_SPCMD_STD | HSMCI_CMDR_RSPTYP_48_BIT \ + | HSMCI_CMDR_TRCMD_START_DATA | HSMCI_CMDR_TRDIR_READ \ + | HSMCI_CMDR_TRTYP_SINGLE | HSMCI_CMDR_MAXLAT) + +#define SDMMC_SET_BLOCKLEN (16 | HSMCI_CMDR_TRCMD_NO_DATA \ + | HSMCI_CMDR_SPCMD_STD \ + | HSMCI_CMDR_RSPTYP_48_BIT \ + | HSMCI_CMDR_MAXLAT_64 ) + +#define SD_READ_SINGLE_BLOCK (17 | HSMCI_CMDR_SPCMD_STD | HSMCI_CMDR_RSPTYP_48_BIT \ + | HSMCI_CMDR_TRCMD_START_DATA | HSMCI_CMDR_TRDIR_READ \ + | HSMCI_CMDR_TRTYP_SINGLE | HSMCI_CMDR_MAXLAT) + +#define SD_WRITE_SINGLE_BLOCK (24 | HSMCI_CMDR_SPCMD_STD \ + | HSMCI_CMDR_RSPTYP_48_BIT \ + | HSMCI_CMDR_TRCMD_START_DATA \ + | HSMCI_CMDR_TRDIR_WRITE \ + | HSMCI_CMDR_TRTYP_SINGLE \ + | HSMCI_CMDR_MAXLAT) + +// Get SCR +uint32_t sd_acmd51( uint32_t *presult ) +{ + uint32_t i ; + uint32_t j = 0 ; + Hsmci *phsmci = HSMCI ; + + if ( CardIsConnected() ) + { + sd_cmd55() ; + // Block size = 64/ 8, nblocks = 1 + phsmci->HSMCI_BLKR = ( ( 64 / 8 ) << 16 ) | 1 ; + phsmci->HSMCI_ARGR = 0 ; + phsmci->HSMCI_CMDR = SD_SEND_SCR ; + + for ( i = 0 ; i < 50000 ; i += 1 ) + { + if ( phsmci->HSMCI_SR & HSMCI_SR_RXRDY ) + { + *presult++ = __REV(phsmci->HSMCI_RDR) ; + j += 0x10000000 ; + } + if ( ( phsmci->HSMCI_SR & ( HSMCI_SR_CMDRDY | HSMCI_SR_XFRDONE ) ) == ( HSMCI_SR_CMDRDY | HSMCI_SR_XFRDONE ) ) + { + break ; + } + + } + if ( i >= 50000 ) + { + *presult = phsmci->HSMCI_SR ; + } + return i | j ; //phsmci->HSMCI_RSPR[0] ; + } + else + { + return 0 ; + } +} + +#define SD_SET_BUS_WIDTH (6 | HSMCI_CMDR_SPCMD_STD | HSMCI_CMDR_RSPTYP_48_BIT \ + | HSMCI_CMDR_MAXLAT) + +// Set bus width to 4 bits, set speed to 9 MHz +uint32_t sd_acmd6() +{ + uint32_t i ; + Hsmci *phsmci = HSMCI ; + + if ( CardIsConnected() ) + { + sd_cmd55() ; + phsmci->HSMCI_ARGR = 2 ; // Bus width 4 bits + phsmci->HSMCI_CMDR = SD_SET_BUS_WIDTH ; + + for ( i = 0 ; i < 300000 ; i += 1 ) + { + if ( phsmci->HSMCI_SR & HSMCI_SR_CMDRDY ) + { + break ; + } + } + if ( i >= 300000 ) + { + return 0 ; + } + SD_SetBusWidth( HSMCI_SDCR_SDCBUS_4 ) ; + uint32_t j ; + j = SpeedAllowed ; + if ( j > 9000000 ) + { + j = 9000000 ; + } + + SD_SetSpeed( j ) ; + if (Cmd_A41_resp & 0x40000000 ) // OCR_SD_CCS) + sd_cmd16(); + return i ; //phsmci->HSMCI_RSPR[0] ; + } + else + { + return 0 ; + } +} + +const uint8_t SpeedTable[] = { 1, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80 } ; + +// This routine is called every 10 mS, and checks for card +// insertion and removal. +// When a card is inserted, it initialises it ready for read/write access. +void sd_poll_10mS() +{ + uint32_t i ; + + if ( !CardIsConnected() ) + { + Card_state = SD_ST_EMPTY ; + Sd_rca = 0 ; + + } + + switch ( Card_state ) + { + case SD_ST_EMPTY : + if ( CardIsConnected() ) { + Card_state = SD_ST_INIT1 ; + } + break ; + + case SD_ST_INIT1 : + i = sd_cmd0() ; // Keep a 10mS delay after this before sd_cmd8() + if ( i == 0 ) + { + Card_state = SD_ST_INIT2 ; + } + break ; + + case SD_ST_INIT2 : + i = sd_cmd8() ; + if ( i == 0 ) + { + Card_state = SD_ST_IDLE ; + } + break ; + + case SD_ST_IDLE : + i = sd_acmd41() ; + if ( i & 0x80000000 ) { + Card_state = SD_ST_READY ; + } + break ; + + case SD_ST_READY : + i = sd_cmd2() ; + if ( i == 0 ) + { + Card_state = SD_ST_IDENT ; + } + break ; + + case SD_ST_IDENT : + i = sd_cmd3() ; // Get new RCA + if ( i == 0 ) + { + Card_state = SD_ST_STBY ; + } + break ; + + case SD_ST_STBY : + i = sd_cmd9() ; + // Calc transmission speed + i = Card_CSD[0] & 0x0000007F ; + { + uint32_t j ; + j = i >> 3 ; + j = SpeedTable[j] ; + j *= 10000 ; + i &= 7 ; + if ( i-- ) + { + j *= 10 ; + } + if ( i-- ) + { + j *= 10 ; + } + if ( i ) + { + j *= 10 ; + } + SpeedAllowed = j ; + } + i = sd_cmd7() ; // Select Card + Card_state = SD_ST_TRAN ; + Sd_retries = 5 ; + break ; + + case SD_ST_TRAN : + i = sd_acmd51( Sd_128_resp ) ; + if ( i != 0 ) + { + if ( --Sd_retries > 0 ) + { + break ; + } + } + Card_SCR[0] = Sd_128_resp[0] ; + Card_SCR[1] = Sd_128_resp[1] ; + Card_state = SD_ST_DATA ; + i = sd_acmd6() ; // Set bus width to 4 bits, and speed to 9 MHz + // Should check the card can do this **** + break ; + } +} + +// Checks for card ready for read/write +// returns 1 for YES, 0 for NO +uint32_t sd_card_ready( void ) +{ + if ( CardIsConnected() ) + { + if ( Card_state == SD_ST_DATA ) + { + return 1 ; + } + } + return 0 ; +} + +uint32_t sd_cmd16() +{ +// @Mike: there is something wrong here, where could I have find infos??? +//#if 0 + Hsmci *phsmci = HSMCI; + + if (CardIsConnected()) + { + phsmci->HSMCI_BLKR = ( ( 512 ) << 16 ) | 1 ; + phsmci->HSMCI_ARGR = 512; + phsmci->HSMCI_CMDR = SDMMC_SET_BLOCKLEN; + + while(1) { + if (phsmci->HSMCI_SR & HSMCI_SR_CMDRDY) { + break; + } + } + return phsmci->HSMCI_RSPR[0]; + } + else + { + return 0; + } +//#else +// return 0; +//#endif +} + +uint32_t sd_read_block(uint32_t block_no, uint32_t *data) +{ + uint32_t result = 0; + Hsmci *phsmci = HSMCI; + uint32_t status = 0; + + if (sd_card_ready()) + { +// sd_cmd16(); + + // Wait for card to be ready for data transfers + do { + sd_cmd13(&status); + } while (((status & STATUS_READY_FOR_DATA) == 0) + || ((status & STATUS_STATE) != STATUS_TRAN) ); + + // Block size = 512, nblocks = 1 + phsmci->HSMCI_BLKR = ((512) << 16) | 1; + phsmci->HSMCI_MR = (phsmci->HSMCI_MR & (~(HSMCI_MR_BLKLEN_Msk|HSMCI_MR_FBYTE))) | (HSMCI_MR_PDCMODE|HSMCI_MR_WRPROOF|HSMCI_MR_RDPROOF) | (512 << 16); + phsmci->HSMCI_ARGR = Cmd_A41_resp & 0x40000000 ? block_no : block_no << 9; + phsmci->HSMCI_RPR = CONVERT_PTR(data); + phsmci->HSMCI_RCR = 512 / 4; + phsmci->HSMCI_PTCR = HSMCI_PTCR_RXTEN; + phsmci->HSMCI_CMDR = SD_READ_SINGLE_BLOCK; + + uint8_t retry = 100; + while (retry-- > 0) + { +#ifndef BOOT + CoTickDelay(1); // 2ms +#else + delay2ms() ; +#endif + if (phsmci->HSMCI_SR & HSMCI_SR_ENDRX) + { +// phsmci->HSMCI_PTCR = HSMCI_PTCR_RXTDIS; + result = 1; + break; + } + } + } + phsmci->HSMCI_PTCR = HSMCI_PTCR_RXTDIS; + phsmci->HSMCI_MR &= ~HSMCI_MR_PDCMODE; + return result; +} + +uint32_t sd_write_block( uint32_t block_no, uint32_t *data ) +{ + uint32_t result = 0; + Hsmci *phsmci = HSMCI; + uint32_t status = 0; + + if (sd_card_ready()) + { +// sd_cmd16(); + // Wait for card to be ready for data transfers + do { + sd_cmd13(&status); + } while (((status & STATUS_READY_FOR_DATA) == 0) + || ((status & STATUS_STATE) != STATUS_TRAN) ); + + // Block size = 512, nblocks = 1 + phsmci->HSMCI_BLKR = ((512) << 16) | 1; + phsmci->HSMCI_MR = (phsmci->HSMCI_MR & (~(HSMCI_MR_BLKLEN_Msk|HSMCI_MR_FBYTE))) | (HSMCI_MR_PDCMODE|HSMCI_MR_WRPROOF|HSMCI_MR_RDPROOF) | (512 << 16); + phsmci->HSMCI_ARGR = Cmd_A41_resp & 0x40000000 ? block_no : block_no << 9; + phsmci->HSMCI_TPR = CONVERT_PTR(data); + phsmci->HSMCI_TCR = 512 / 4; + phsmci->HSMCI_CMDR = SD_WRITE_SINGLE_BLOCK; + phsmci->HSMCI_PTCR = HSMCI_PTCR_TXTEN; + + uint8_t retry = 100; + while (retry-- > 0) { +#ifndef BOOT + CoTickDelay(1); // 2ms +#else + delay2ms() ; +#endif + if (phsmci->HSMCI_SR & HSMCI_SR_NOTBUSY) + { +// phsmci->HSMCI_PTCR = HSMCI_PTCR_TXTDIS; + result = 1; + break; + } + } + } + + phsmci->HSMCI_PTCR = HSMCI_PTCR_TXTDIS; + phsmci->HSMCI_MR &= ~HSMCI_MR_PDCMODE; + return result; +} + +/* + Notes on SD card: + +1) CMD8 fails and CMD58 fails: must be MMC, thus initialize using CMD1 +2) CMD8 fails and CMD58 passes: must be Ver1.x Standard Capacity SD Memory Card +3) CMD8 passes and CMD58 passes (CCS = 0): must be Ver2.00 or later Standard Capacity SD Memory Card +4) CMD8 passes and CMD58 passes (CCS = 1): must be Ver2.00 or later High Capacity SD Memory Card +5) CMD8 passes and CMD58 passes but indicates non compatible voltage range: unusable card + +On card present +1. Send CMD 55 (resp 48bit) + followed by ACMD41 (resp48bit) + until bit 31 of response is '1' + +2. Send CMD 2 (resp 136bit) - card ID + +3. Send CMD 3 (resp 48 bit) - new RCA returned + +4. Send CMD 9 (resp 136) - CSD + +5. Send CMD 7 (resp 48) - + +6. Send CMD 55 (resp 48bit) + followed by ACMD51 (resp48bit) - SCR stored as 2 32 bit values + +Now decide what the card can do! + +7. Set block length + +8. Set bus width + +9. Read block 0 + +*/ + + +#include "ff.h" +#include "diskio.h" + +/* FAT sub-type boundaries */ +/* Note that the FAT spec by Microsoft says 4085 but Windows works with 4087! */ +#define MIN_FAT16 4086 /* Minimum number of clusters for FAT16 */ +#define MIN_FAT32 65526 /* Minimum number of clusters for FAT32 */ + + +/* FatFs refers the members in the FAT structures as byte array instead of +/ structure member because there are incompatibility of the packing option +/ between compilers. */ + +#define BS_jmpBoot 0 +#define BS_OEMName 3 +#define BPB_BytsPerSec 11 +#define BPB_SecPerClus 13 +#define BPB_RsvdSecCnt 14 +#define BPB_NumFATs 16 +#define BPB_RootEntCnt 17 +#define BPB_TotSec16 19 +#define BPB_Media 21 +#define BPB_FATSz16 22 +#define BPB_SecPerTrk 24 +#define BPB_NumHeads 26 +#define BPB_HiddSec 28 +#define BPB_TotSec32 32 +#define BS_DrvNum 36 +#define BS_BootSig 38 +#define BS_VolID 39 +#define BS_VolLab 43 +#define BS_FilSysType 54 +#define BPB_FATSz32 36 +#define BPB_ExtFlags 40 +#define BPB_FSVer 42 +#define BPB_RootClus 44 +#define BPB_FSInfo 48 +#define BPB_BkBootSec 50 +#define BS_DrvNum32 64 +#define BS_BootSig32 66 +#define BS_VolID32 67 +#define BS_VolLab32 71 +#define BS_FilSysType32 82 +#define FSI_LeadSig 0 +#define FSI_StrucSig 484 +#define FSI_Free_Count 488 +#define FSI_Nxt_Free 492 +#define MBR_Table 446 +#define BS_55AA 510 + +#define DIR_Name 0 +#define DIR_Attr 11 +#define DIR_NTres 12 +#define DIR_CrtTime 14 +#define DIR_CrtDate 16 +#define DIR_FstClusHI 20 +#define DIR_WrtTime 22 +#define DIR_WrtDate 24 +#define DIR_FstClusLO 26 +#define DIR_FileSize 28 +#define LDIR_Ord 0 +#define LDIR_Attr 11 +#define LDIR_Type 12 +#define LDIR_Chksum 13 +#define LDIR_FstClusLO 26 + +#ifdef BOOT +#if !defined(SIMU) +#include "Fat12.cpp" +#endif +#endif + +/*-----------------------------------------------------------------------*/ +/* Initialize Disk Drive */ +/*-----------------------------------------------------------------------*/ + +DSTATUS disk_initialize ( + BYTE drv /* Physical drive nmuber (0) */ + ) +{ +#ifdef BOOT + if (drv==1) return RES_OK ; /* EEPROM */ +#endif + if (drv) return STA_NOINIT; /* Supports only single drive */ + if ( sd_card_ready() == 0 ) return RES_NOTRDY; + return RES_OK; + +#if 0 + BYTE n, cmd, ty, ocr[4]; + + + if (drv) return STA_NOINIT; /* Supports only single drive */ + + if (Stat & STA_NODISK) return Stat; /* No card in the socket */ + + power_on(); /* Force socket power on */ + FCLK_SLOW(); + for (n = 10; n; n--) rcvr_spi(); /* 80 dummy clocks */ + + ty = 0; + if (send_cmd(CMD0, 0) == 1) { /* Enter Idle state */ + Timer1 = 100; /* Initialization timeout of 1000 msec */ + if (send_cmd(CMD8, 0x1AA) == 1) { /* SDv2? */ + for (n = 0; n < 4; n++) ocr[n] = rcvr_spi(); /* Get trailing return value of R7 resp */ + if (ocr[2] == 0x01 && ocr[3] == 0xAA) { /* The card can work at vdd range of 2.7-3.6V */ + while (Timer1 && send_cmd(ACMD41, 1UL << 30)); /* Wait for leaving idle state (ACMD41 with HCS bit) */ + if (Timer1 && send_cmd(CMD58, 0) == 0) { /* Check CCS bit in the OCR */ + for (n = 0; n < 4; n++) ocr[n] = rcvr_spi(); + ty = (ocr[0] & 0x40) ? CT_SD2 | CT_BLOCK : CT_SD2; /* SDv2 */ + } + } + } else { /* SDv1 or MMCv3 */ + if (send_cmd(ACMD41, 0) <= 1) { + ty = CT_SD1; cmd = ACMD41; /* SDv1 */ + } else { + ty = CT_MMC; cmd = CMD1; /* MMCv3 */ + } + while (Timer1 && send_cmd(cmd, 0)); /* Wait for leaving idle state */ + if (!Timer1 || send_cmd(CMD16, 512) != 0) /* Set R/W block length to 512 */ + ty = 0; + } + } + CardType = ty; + deselect(); + + if (ty) { /* Initialization succeded */ + Stat &= ~STA_NOINIT; /* Clear STA_NOINIT */ + FCLK_FAST(); + } else { /* Initialization failed */ + power_off(); + } + + return Stat; +#endif +} + +/*-----------------------------------------------------------------------*/ +/* Get Disk Status */ +/*-----------------------------------------------------------------------*/ + +DSTATUS disk_status ( BYTE drv /* Physical drive number (0) */ ) +{ + + if (drv==1) return RES_OK ; /* EEPROM */ + if (drv) return STA_NOINIT; /* Supports only single drive */ + if ( sd_card_ready() == 0 ) return RES_NOTRDY; + return RES_OK; +} + +#if !defined(SIMU) + +/*-----------------------------------------------------------------------*/ +/* Read Sector(s) */ +/*-----------------------------------------------------------------------*/ + +DRESULT disk_read ( + BYTE drv, /* Physical drive nmuber (0) */ + BYTE *buff, /* Pointer to the data buffer to store read data */ + DWORD sector, /* Start sector number (LBA) */ + BYTE count /* Sector count (1..255) */ + ) +{ + uint32_t result ; + if ( !count) return RES_PARERR ; + +#ifdef BOOT + if (drv==1) /* EEPROM */ + { + + do + { + result = fat12Read( buff, sector ) ; + if (result) + { + sector += 1 ; + buff += 512 ; + count -= 1 ; + } + else + { + count = 1 ; // Flag error + break ; + } + } while ( count ) ; + } + else +#endif + { + if (drv ) return RES_PARERR; + + if ( sd_card_ready() == 0 ) return RES_NOTRDY; + + do { + result = sd_read_block( sector, ( uint32_t *)buff ) ; + if (result) { + sector += 1 ; + buff += 512 ; + count -= 1 ; + } + else { + count = 1 ; // Flag error + break ; + } + } while ( count ) ; + } + return count ? RES_ERROR : RES_OK; +} + + +/*-----------------------------------------------------------------------*/ +/* Write Sector(s) */ +/*-----------------------------------------------------------------------*/ + +DRESULT disk_write ( + BYTE drv, /* Physical drive nmuber (0) */ + const BYTE *buff, /* Pointer to the data to be written */ + DWORD sector, /* Start sector number (LBA) */ + BYTE count /* Sector count (1..255) */ + ) +{ + uint32_t result ; + + if ( !count) return RES_PARERR ; + +#ifdef BOOT + if (drv==1) /* EEPROM */ + { + count = fat12Write( buff, sector, count ) ; + } + else +#endif + { + if (drv ) return RES_PARERR; + + if ( sd_card_ready() == 0 ) return RES_NOTRDY; + + // TODO if (Stat & STA_PROTECT) return RES_WRPRT; + + do { + result = sd_write_block( sector, ( uint32_t *)buff ) ; + if (result) { + sector += 1 ; + buff += 512 ; + count -= 1 ; + } + else { + count = 1 ; // Flag error + break ; + } + } while ( count ) ; + } + return count ? RES_ERROR : RES_OK; +} + +#endif + +/*-----------------------------------------------------------------------*/ +/* Miscellaneous Functions */ +/*-----------------------------------------------------------------------*/ + +DRESULT disk_ioctl ( + BYTE drv, /* Physical drive nmuber (0) */ + BYTE ctrl, /* Control code */ + BYTE *buff /* Buffer to send/receive control data */ + ) +{ + DRESULT res; + BYTE *csd = (BYTE*)&Card_CSD[0]; + BYTE n; // csd[16], *ptr = buff; + WORD csize; + + res = RES_ERROR; +#ifdef BOOT + if (drv==1) + { + switch (ctrl) + { + case CTRL_SYNC : /* Make sure that no pending write process. Do not remove this or written sector might not left updated. */ + /* BSS if (select()) { + deselect(); */ + res = RES_OK; + // } + break ; + + case GET_SECTOR_COUNT : /* Get number of sectors on the disk (DWORD) */ +#ifdef REVX + *(DWORD*)buff = (DWORD)2051 ; +#else + *(DWORD*)buff = (DWORD)1539 ; +#endif + res = RES_OK; + break; + + case GET_SECTOR_SIZE : /* Get R/W sector size (WORD) */ + *(WORD*)buff = 512; + res = RES_OK; + break; + + } + return res ; + } +#endif + + if (drv) return RES_PARERR; + + res = RES_ERROR; + + if (ctrl == CTRL_POWER) { +#if 0 + switch (ptr[0]) { + case 0: /* Sub control code (POWER_OFF) */ + power_off(); /* Power off */ + res = RES_OK; + break; + case 1: /* Sub control code (POWER_GET) */ + ptr[1] = (BYTE)power_status(); + res = RES_OK; + break; + default : + res = RES_PARERR; + } +#endif + } + else { + switch (ctrl) { + case CTRL_SYNC : /* Make sure that no pending write process. Do not remove this or written sector might not left updated. */ + /* BSS if (select()) { + deselect(); */ + res = RES_OK; + // } + break; + + case GET_SECTOR_COUNT : /* Get number of sectors on the disk (DWORD) */ + // if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { + if ((csd[0] >> 6) == 1) { /* SDC ver 2.00 */ + csize = csd[9] + ((WORD)csd[8] << 8) + 1; + *(DWORD*)buff = (DWORD)csize << 10; + } else { /* SDC ver 1.XX or MMC*/ + n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + ((csd[9] & 3) << 1) + 2; + csize = (csd[8] >> 6) + ((WORD)csd[7] << 2) + ((WORD)(csd[6] & 3) << 10) + 1; + *(DWORD*)buff = (DWORD)csize << (n - 9); + } + res = RES_OK; + // } + break; + + case GET_SECTOR_SIZE : /* Get R/W sector size (WORD) */ + *(WORD*)buff = 512; + res = RES_OK; + break; + + case GET_BLOCK_SIZE : /* Get erase block size in unit of sector (DWORD) */ + // only used in f_mkfs +#if 0 + if (CardType & CT_SD2) { /* SDv2? */ + if (send_cmd(ACMD13, 0) == 0) { /* Read SD status */ + rcvr_spi(); + if (rcvr_datablock(csd, 16)) { /* Read partial block */ + for (n = 64 - 16; n; n--) rcvr_spi(); /* Purge trailing data */ + *(DWORD*)buff = 16UL << (csd[10] >> 4); + res = RES_OK; + } + } + } else { /* SDv1 or MMCv3 */ + if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { /* Read CSD */ + if (CardType & CT_SD1) { /* SDv1 */ + *(DWORD*)buff = (((csd[10] & 63) << 1) + ((WORD)(csd[11] & 128) >> 7) + 1) << ((csd[13] >> 6) - 1); + } else { /* MMCv3 */ + *(DWORD*)buff = ((WORD)((csd[10] & 124) >> 2) + 1) * (((csd[11] & 3) << 3) + ((csd[11] & 224) >> 5) + 1); + } + res = RES_OK; + } + } +#endif + break; + +#if 0 + case MMC_GET_TYPE : /* Get card type flags (1 byte) */ + *ptr = CardType; + res = RES_OK; + break; + + case MMC_GET_CSD : /* Receive CSD as a data block (16 bytes) */ + if (send_cmd(CMD9, 0) == 0 /* READ_CSD */ + && rcvr_datablock(ptr, 16)) + res = RES_OK; + break; + + case MMC_GET_CID : /* Receive CID as a data block (16 bytes) */ + if (send_cmd(CMD10, 0) == 0 /* READ_CID */ + && rcvr_datablock(ptr, 16)) + res = RES_OK; + break; + + case MMC_GET_OCR : /* Receive OCR as an R3 resp (4 bytes) */ + if (send_cmd(CMD58, 0) == 0) { /* READ_OCR */ + for (n = 4; n; n--) *ptr++ = rcvr_spi(); + res = RES_OK; + } + break; + + case MMC_GET_SDSTAT : /* Receive SD statsu as a data block (64 bytes) */ + if (send_cmd(ACMD13, 0) == 0) { /* SD_STATUS */ + rcvr_spi(); + if (rcvr_datablock(ptr, 64)) + res = RES_OK; + } + break; +#endif + default: + res = RES_PARERR; + } + + // BSS deselect(); + } + + return res; +} + + + + + + + + + + diff --git a/radio/bootloader/driversboot.cpp b/radio/bootloader/driversboot.cpp new file mode 100644 index 000000000..a848981b0 --- /dev/null +++ b/radio/bootloader/driversboot.cpp @@ -0,0 +1,206 @@ +/* + * Author - Mike Blandford + * + * Based on er9x by Erez Raviv + * + * Based on th9x -> http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + + + +#include +#include + +#ifdef PCBSKY +#include "radio.h" +#include "drivers.h" +#endif + + +#ifdef PCBX9D +#include "radio.h" +#include "hal.h" +#include "stm32f2xx.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_rcc.h" +#endif +#include "drivers.h" +#include "logicio.h" + +#ifdef EVT_KEY_MASK +#undef EVT_KEY_MASK +#endif + +#define EVT_KEY_MASK 0x0f + + +void b_putEvent( register uint8_t evt) ; +void per10ms( void ) ; +uint8_t getEvent( void ) ; +void pauseEvents(uint8_t event) ; +void killEvents(uint8_t event) ; + +uint8_t s_evt; +void b_putEvent( uint8_t evt) +{ + s_evt = evt; +} + + +uint8_t getEvent() +{ + register uint8_t evt = s_evt; + s_evt=0; + return evt; +} + +Key keys[NUM_KEYS] ; + +void Key::input(bool val, EnumKeys enuk) +{ + // uint8_t old=m_vals; + m_vals <<= 1; if(val) m_vals |= 1; //portbit einschieben + m_cnt++; + + if(m_state && m_vals==0){ //gerade eben sprung auf 0 + if(m_state!=KSTATE_KILLED) { + b_putEvent(EVT_KEY_BREAK(enuk)); + } + m_cnt = 0; + m_state = KSTATE_OFF; + } + switch(m_state){ + case KSTATE_OFF: + if(m_vals==FFVAL){ //gerade eben sprung auf ff + m_state = KSTATE_START; + m_cnt = 0; + } + break; + //fallthrough + case KSTATE_START: + b_putEvent(EVT_KEY_FIRST(enuk)); +#ifdef KSTATE_RPTDELAY + m_state = KSTATE_RPTDELAY; +#else + m_state = 16; +#endif + m_cnt = 0; + break; +#ifdef KSTATE_RPTDELAY + case KSTATE_RPTDELAY: // gruvin: longer delay before first key repeat + if(m_cnt == 32) b_putEvent(EVT_KEY_LONG(enuk)); // need to catch this inside RPTDELAY time + if (m_cnt == 40) { + m_state = 16; + m_cnt = 0; + } + break; +#endif + case 16: +#ifndef KSTATE_RPTDELAY + if(m_cnt == 32) b_putEvent(EVT_KEY_LONG(enuk)); + //fallthrough +#endif + case 8: + case 4: + case 2: + if(m_cnt >= 48) { //3 6 12 24 48 pulses in every 480ms + m_state >>= 1; + m_cnt = 0; + } + //fallthrough + case 1: + if( (m_cnt & (m_state-1)) == 0) b_putEvent(EVT_KEY_REPT(enuk)); + break; + + case KSTATE_PAUSE: //pause + if(m_cnt >= 64) { + m_state = 8; + m_cnt = 0; + } + break; + + case KSTATE_KILLED: //killed + break; + } +} + +void b_pauseEvents(uint8_t event) +{ + event=event & EVT_KEY_MASK; + if(event < (int)DIM(keys)) keys[event].pauseEvents(); +} + +void killEvents(uint8_t event) +{ + event=event & EVT_KEY_MASK; + if(event < (int)DIM(keys)) keys[event].killEvents(); +} + +void per10ms() +{ + register uint32_t i ; + + uint8_t enuk = KEY_MENU; + uint8_t in = ~read_keys() ; + // Bits 3-6 are down, up, right and left + // Try to only allow one at a +#ifdef REVX + static uint8_t current ; + uint8_t dir_keys ; + uint8_t lcurrent ; + + dir_keys = in & 0x78 ; // Mask to direction keys + if ( ( lcurrent = current ) ) + { // Something already pressed + if ( ( lcurrent & dir_keys ) == 0 ) + { + lcurrent = 0 ; // No longer pressed + } + else + { + in &= lcurrent | 0x06 ; // current or MENU or EXIT allowed + } + } + if ( lcurrent == 0 ) + { // look for a key + if ( dir_keys & 0x20 ) // right + { + lcurrent = 0x60 ; // Allow L and R for 9X + } + else if ( dir_keys & 0x40 ) // left + { + lcurrent = 0x60 ; // Allow L and R for 9X + } + else if ( dir_keys & 0x08 ) // down + { + lcurrent = 0x08 ; + } + else if ( dir_keys & 0x10 ) // up + { + lcurrent = 0x10 ; + } + in &= lcurrent | 0x06 ; // current or MENU or EXIT allowed + } + current = lcurrent ; +#endif + + for( i=1; i<7; i++) + { + uint8_t value = in & (1< + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * open9x is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +/*----------------------------------------------------------------------------/ +/ FatFs - FAT file system module R0.08a (C)ChaN, 2010 +/-----------------------------------------------------------------------------/ +/ FatFs module is a generic FAT file system module for small embedded systems. +/ This is a free software that opened for education, research and commercial +/ developments under license policy of following terms. +/ +/ Copyright (C) 2010, ChaN, all right reserved. +/ +/ * The FatFs module is a free software and there is NO WARRANTY. +/ * No restriction on use. You can use, modify and redistribute it for +/ personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY. +/ * Redistributions of source code must retain the above copyright notice. +/ +/-----------------------------------------------------------------------------/ +/ Feb 26,'06 R0.00 Prototype. +/ +/ Apr 29,'06 R0.01 First stable version. +/ +/ Jun 01,'06 R0.02 Added FAT12 support. +/ Removed unbuffered mode. +/ Fixed a problem on small (<32M) partition. +/ Jun 10,'06 R0.02a Added a configuration option (_FS_MINIMUM). +/ +/ Sep 22,'06 R0.03 Added f_rename(). +/ Changed option _FS_MINIMUM to _FS_MINIMIZE. +/ Dec 11,'06 R0.03a Improved cluster scan algorithm to write files fast. +/ Fixed f_mkdir() creates incorrect directory on FAT32. +/ +/ Feb 04,'07 R0.04 Supported multiple drive system. +/ Changed some interfaces for multiple drive system. +/ Changed f_mountdrv() to f_mount(). +/ Added f_mkfs(). +/ Apr 01,'07 R0.04a Supported multiple partitions on a physical drive. +/ Added a capability of extending file size to f_lseek(). +/ Added minimization level 3. +/ Fixed an endian sensitive code in f_mkfs(). +/ May 05,'07 R0.04b Added a configuration option _USE_NTFLAG. +/ Added FSInfo support. +/ Fixed DBCS name can result FR_INVALID_NAME. +/ Fixed short seek (<= csize) collapses the file object. +/ +/ Aug 25,'07 R0.05 Changed arguments of f_read(), f_write() and f_mkfs(). +/ Fixed f_mkfs() on FAT32 creates incorrect FSInfo. +/ Fixed f_mkdir() on FAT32 creates incorrect directory. +/ Feb 03,'08 R0.05a Added f_truncate() and f_utime(). +/ Fixed off by one error at FAT sub-type determination. +/ Fixed btr in f_read() can be mistruncated. +/ Fixed cached sector is not flushed when create and close without write. +/ +/ Apr 01,'08 R0.06 Added fputc(), fputs(), fprintf() and fgets(). +/ Improved performance of f_lseek() on moving to the same or following cluster. +/ +/ Apr 01,'09 R0.07 Merged Tiny-FatFs as a buffer configuration option. (_FS_TINY) +/ Added long file name support. +/ Added multiple code page support. +/ Added re-entrancy for multitask operation. +/ Added auto cluster size selection to f_mkfs(). +/ Added rewind option to f_readdir(). +/ Changed result code of critical errors. +/ Renamed string functions to avoid name collision. +/ Apr 14,'09 R0.07a Separated out OS dependent code on reentrant cfg. +/ Added multiple sector size support. +/ Jun 21,'09 R0.07c Fixed f_unlink() can return FR_OK on error. +/ Fixed wrong cache control in f_lseek(). +/ Added relative path feature. +/ Added f_chdir() and f_chdrive(). +/ Added proper case conversion to extended char. +/ Nov 03,'09 R0.07e Separated out configuration options from ff.h to ffconf.h. +/ Fixed f_unlink() fails to remove a sub-dir on _FS_RPATH. +/ Fixed name matching error on the 13 char boundary. +/ Added a configuration option, _LFN_UNICODE. +/ Changed f_readdir() to return the SFN with always upper case on non-LFN cfg. +/ +/ May 15,'10 R0.08 Added a memory configuration option. (_USE_LFN = 3) +/ Added file lock feature. (_FS_SHARE) +/ Added fast seek feature. (_USE_FASTSEEK) +/ Changed some types on the API, XCHAR->TCHAR. +/ Changed fname member in the FILINFO structure on Unicode cfg. +/ String functions support UTF-8 encoding files on Unicode cfg. +/ Aug 16,'10 R0.08a Added f_getcwd(). (_FS_RPATH = 2) +/ Added sector erase feature. (_USE_ERASE) +/ Moved file lock semaphore table from fs object to the bss. +/ Fixed a wrong directory entry is created on non-LFN cfg when the given name contains ';'. +/ Fixed f_mkfs() creates wrong FAT32 volume. +/---------------------------------------------------------------------------*/ + +#include "ff.h" /* FatFs configurations and declarations */ +#include "diskio.h" /* Declarations of low level disk I/O functions */ +#include "gtime.h" + +/*-------------------------------------------------------------------------- + + Module Private Definitions + +---------------------------------------------------------------------------*/ + +#if _FATFS != 8255 +#error Wrong include file (ff.h). +#endif + + +/* Definitions on sector size */ +#if _MAX_SS != 512 && _MAX_SS != 1024 && _MAX_SS != 2048 && _MAX_SS != 4096 +#error Wrong sector size. +#endif +#if _MAX_SS != 512 +#define SS(fs) ((fs)->ssize) /* Multiple sector size */ +#else +#define SS(fs) 512U /* Fixed sector size */ +#endif + + +/* Reentrancy related */ +#if _FS_REENTRANT +#if _USE_LFN == 1 +#error Static LFN work area must not be used in re-entrant configuration. +#endif +#define ENTER_FF(fs) { if (!lock_fs(fs)) return FR_TIMEOUT; } +#define LEAVE_FF(fs, res) { unlock_fs(fs, res); return res; } +#else +#define ENTER_FF(fs) +#define LEAVE_FF(fs, res) return res +#endif + +#define ABORT(fs, res) { fp->flag |= FA__ERROR; LEAVE_FF(fs, res); } + + +/* File shareing feature */ +#if _FS_SHARE +#if _FS_READONLY +#error _FS_SHARE must be 0 on read-only cfg. +#endif +typedef struct { + FATFS *fs; /* File ID 1, volume (NULL:blank entry) */ + DWORD clu; /* File ID 2, directory */ + WORD idx; /* File ID 3, directory index */ + WORD ctr; /* File open counter, 0:none, 0x01..0xFF:read open count, 0x100:write mode */ +} FILESEM; +#endif + + +/* Misc definitions */ +#define LD_CLUST(dir) (((DWORD)LD_WORD(dir+DIR_FstClusHI)<<16) | LD_WORD(dir+DIR_FstClusLO)) +#define ST_CLUST(dir,cl) {ST_WORD(dir+DIR_FstClusLO, cl); ST_WORD(dir+DIR_FstClusHI, (DWORD)cl>>16);} + + +/* Character code support macros */ +#define IsUpper(c) (((c)>='A')&&((c)<='Z')) +#define IsLower(c) (((c)>='a')&&((c)<='z')) +#define IsDigit(c) (((c)>='0')&&((c)<='9')) + +#if _DF1S /* Code page is DBCS */ + +#ifdef _DF2S /* Two 1st byte areas */ +#define IsDBCS1(c) (((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E)) +#else /* One 1st byte area */ +#define IsDBCS1(c) ((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) +#endif + +#ifdef _DS3S /* Three 2nd byte areas */ +#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E)) +#else /* Two 2nd byte areas */ +#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E)) +#endif + +#else /* Code page is SBCS */ + +#define IsDBCS1(c) 0 +#define IsDBCS2(c) 0 + +#endif /* _DF1S */ + + +/* Name status flags */ +#define NS 11 /* Offset of name status byte */ +#define NS_LOSS 0x01 /* Out of 8.3 format */ +#define NS_LFN 0x02 /* Force to create LFN entry */ +#define NS_LAST 0x04 /* Last segment */ +#define NS_BODY 0x08 /* Lower case flag (body) */ +#define NS_EXT 0x10 /* Lower case flag (ext) */ +#define NS_DOT 0x20 /* Dot entry */ + + +/* FAT sub-type boundaries */ +/* Note that the FAT spec by Microsoft says 4085 but Windows works with 4087! */ +#define MIN_FAT16 4086 /* Minimum number of clusters for FAT16 */ +#define MIN_FAT32 65526 /* Minimum number of clusters for FAT32 */ + + +/* FatFs refers the members in the FAT structures as byte array instead of +/ structure member because there are incompatibility of the packing option +/ between compilers. */ + +#define BS_jmpBoot 0 +#define BS_OEMName 3 +#define BPB_BytsPerSec 11 +#define BPB_SecPerClus 13 +#define BPB_RsvdSecCnt 14 +#define BPB_NumFATs 16 +#define BPB_RootEntCnt 17 +#define BPB_TotSec16 19 +#define BPB_Media 21 +#define BPB_FATSz16 22 +#define BPB_SecPerTrk 24 +#define BPB_NumHeads 26 +#define BPB_HiddSec 28 +#define BPB_TotSec32 32 +#define BS_DrvNum 36 +#define BS_BootSig 38 +#define BS_VolID 39 +#define BS_VolLab 43 +#define BS_FilSysType 54 +#define BPB_FATSz32 36 +#define BPB_ExtFlags 40 +#define BPB_FSVer 42 +#define BPB_RootClus 44 +#define BPB_FSInfo 48 +#define BPB_BkBootSec 50 +#define BS_DrvNum32 64 +#define BS_BootSig32 66 +#define BS_VolID32 67 +#define BS_VolLab32 71 +#define BS_FilSysType32 82 +#define FSI_LeadSig 0 +#define FSI_StrucSig 484 +#define FSI_Free_Count 488 +#define FSI_Nxt_Free 492 +#define MBR_Table 446 +#define BS_55AA 510 + +#define DIR_Name 0 +#define DIR_Attr 11 +#define DIR_NTres 12 +#define DIR_CrtTime 14 +#define DIR_CrtDate 16 +#define DIR_FstClusHI 20 +#define DIR_WrtTime 22 +#define DIR_WrtDate 24 +#define DIR_FstClusLO 26 +#define DIR_FileSize 28 +#define LDIR_Ord 0 +#define LDIR_Attr 11 +#define LDIR_Type 12 +#define LDIR_Chksum 13 +#define LDIR_FstClusLO 26 + + + +/*------------------------------------------------------------*/ +/* Work area */ + +#if _VOLUMES +static +FATFS *FatFs[_VOLUMES]; /* Pointer to the file system objects (logical drives) */ +#else +#error Number of drives must not be 0. +#endif + +static +WORD Fsid; /* File system mount ID */ + +#if _FS_RPATH +static +BYTE CurrVol; /* Current drive */ +#endif + +#if _FS_SHARE +static +FILESEM Files[_FS_SHARE]; /* File lock semaphores */ +#endif + +#if _USE_LFN == 0 /* No LFN */ +#define DEF_NAMEBUF BYTE sfn[12] +#define INIT_BUF(dobj) (dobj).fn = sfn +#define FREE_BUF() + +#elif _USE_LFN == 1 /* LFN with static LFN working buffer */ +static WCHAR LfnBuf[_MAX_LFN+1]; +#define DEF_NAMEBUF BYTE sfn[12] +#define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = LfnBuf; } +#define FREE_BUF() + +#elif _USE_LFN == 2 /* LFN with dynamic LFN working buffer on the stack */ +#define DEF_NAMEBUF BYTE sfn[12]; WCHAR lbuf[_MAX_LFN+1] +#define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = lbuf; } +#define FREE_BUF() + +#elif _USE_LFN == 3 /* LFN with dynamic LFN working buffer on the heap */ +#define DEF_NAMEBUF BYTE sfn[12]; WCHAR *lfn +#define INIT_BUF(dobj) { lfn = ff_memalloc((_MAX_LFN + 1) * 2); \ + if (!lfn) LEAVE_FF((dobj).fs, FR_NOT_ENOUGH_CORE); \ + (dobj).lfn = lfn; (dobj).fn = sfn; } +#define FREE_BUF() ff_memfree(lfn) + +#else +#error Wrong LFN configuration. +#endif + + + + +/*-------------------------------------------------------------------------- + + Module Private Functions + +---------------------------------------------------------------------------*/ + + +/*-----------------------------------------------------------------------*/ +/* String functions */ +/*-----------------------------------------------------------------------*/ + +/* Copy memory to memory */ +static +void mem_cpy (void* dst, const void* src, UINT cnt) { + BYTE *d = (BYTE*)dst; + const BYTE *s = (const BYTE*)src; + +#if _WORD_ACCESS == 1 + while (cnt >= sizeof(int)) { + *(int*)d = *(int*)s; + d += sizeof(int); s += sizeof(int); + cnt -= sizeof(int); + } +#endif + while (cnt--) + *d++ = *s++; +} + +/* Fill memory */ +static +void mem_set (void* dst, int val, UINT cnt) { + BYTE *d = (BYTE*)dst; + + while (cnt--) + *d++ = (BYTE)val; +} + +/* Compare memory to memory */ +static +int mem_cmp (const void* dst, const void* src, UINT cnt) { + const BYTE *d = (const BYTE *)dst, *s = (const BYTE *)src; + int r = 0; + + while (cnt-- && (r = *d++ - *s++) == 0) ; + return r; +} + +/* Check if chr is contained in the string */ +static +int chk_chr (const char* str, int chr) { + while (*str && *str != chr) str++; + return *str; +} + + + +/*-----------------------------------------------------------------------*/ +/* Request/Release grant to access the volume */ +/*-----------------------------------------------------------------------*/ +#if _FS_REENTRANT + +static +int lock_fs ( + FATFS *fs /* File system object */ +) +{ + return ff_req_grant(fs->sobj); +} + + +static +void unlock_fs ( + FATFS *fs, /* File system object */ + FRESULT res /* Result code to be returned */ +) +{ + if (fs && + res != FR_NOT_ENABLED && + res != FR_INVALID_DRIVE && + res != FR_INVALID_OBJECT && + res != FR_TIMEOUT) { + ff_rel_grant(fs->sobj); + } +} +#endif + + + +/*-----------------------------------------------------------------------*/ +/* File shareing control functions */ +/*-----------------------------------------------------------------------*/ +#if _FS_SHARE + +static +FRESULT chk_lock ( /* Check if the file can be accessed */ + DIR* dj, /* Directory object pointing the file to be checked */ + int acc /* Desired access (0:Read, 1:Write, 2:Delete/Rename) */ +) +{ + UINT i, be; + + /* Search file semaphore table */ + for (i = be = 0; i < _FS_SHARE; i++) { + if (Files[i].fs) { /* Existing entry */ + if (Files[i].fs == dj->fs && /* Check if the file matched with an open file */ + Files[i].clu == dj->sclust && + Files[i].idx == dj->index) break; + } else { /* Blank entry */ + be++; + } + } + if (i == _FS_SHARE) /* The file is not opened */ + return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES; /* Is there a blank entry for new file? */ + + /* The file has been opened. Reject any open against writing file and all write mode open */ + return (acc || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK; +} + + +static +int enq_lock ( /* Check if an entry is available for a new file */ + FATFS* fs /* File system object */ +) +{ + UINT i; + + for (i = 0; i < _FS_SHARE && Files[i].fs; i++) ; + return (i == _FS_SHARE) ? 0 : 1; +} + + +static +UINT inc_lock ( /* Increment file open counter and returns its index (0:int error) */ + DIR* dj, /* Directory object pointing the file to register or increment */ + int acc /* Desired access mode (0:Read, !0:Write) */ +) +{ + UINT i; + + + for (i = 0; i < _FS_SHARE; i++) { /* Find the file */ + if (Files[i].fs == dj->fs && + Files[i].clu == dj->sclust && + Files[i].idx == dj->index) break; + } + + if (i == _FS_SHARE) { /* Not opened. Register it as new. */ + for (i = 0; i < _FS_SHARE && Files[i].fs; i++) ; + if (i == _FS_SHARE) return 0; /* No space to register (int err) */ + Files[i].fs = dj->fs; + Files[i].clu = dj->sclust; + Files[i].idx = dj->index; + Files[i].ctr = 0; + } + + if (acc && Files[i].ctr) return 0; /* Access violation (int err) */ + + Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1; /* Set semaphore value */ + + return i + 1; +} + + +static +FRESULT dec_lock ( /* Decrement file open counter */ + UINT i /* Semaphore index */ +) +{ + WORD n; + FRESULT res; + + + if (--i < _FS_SHARE) { + n = Files[i].ctr; + if (n == 0x100) n = 0; + if (n) n--; + Files[i].ctr = n; + if (!n) Files[i].fs = 0; + res = FR_OK; + } else { + res = FR_INT_ERR; + } + return res; +} + + +static +void clear_lock ( /* Clear lock entries of the volume */ + FATFS *fs +) +{ + UINT i; + + for (i = 0; i < _FS_SHARE; i++) { + if (Files[i].fs == fs) Files[i].fs = 0; + } +} +#endif + + + +/*-----------------------------------------------------------------------*/ +/* Change window offset */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT move_window ( + FATFS *fs, /* File system object */ + DWORD sector /* Sector number to make appearance in the fs->win[] */ +) /* Move to zero only writes back dirty window */ +{ + DWORD wsect; + + + wsect = fs->winsect; + if (wsect != sector) { /* Changed current window */ +#if !_FS_READONLY + if (fs->wflag) { /* Write back dirty window if needed */ + if (disk_write(fs->drv, fs->win, wsect, 1) != RES_OK) + return FR_DISK_ERR; + fs->wflag = 0; + if (wsect < (fs->fatbase + fs->fsize)) { /* In FAT area */ + BYTE nf; + for (nf = fs->n_fats; nf > 1; nf--) { /* Reflect the change to all FAT copies */ + wsect += fs->fsize; + disk_write(fs->drv, fs->win, wsect, 1); + } + } + } +#endif + if (sector) { + if (disk_read(fs->drv, fs->win, sector, 1) != RES_OK) + return FR_DISK_ERR; + fs->winsect = sector; + } + } + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Clean-up cached data */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +FRESULT sync ( /* FR_OK: successful, FR_DISK_ERR: failed */ + FATFS *fs /* File system object */ +) +{ + FRESULT res; + + + res = move_window(fs, 0); + if (res == FR_OK) { + /* Update FSInfo sector if needed */ + if (fs->fs_type == FS_FAT32 && fs->fsi_flag) { + fs->winsect = 0; + mem_set(fs->win, 0, 512); + ST_WORD(fs->win+BS_55AA, 0xAA55); + ST_DWORD(fs->win+FSI_LeadSig, 0x41615252); + ST_DWORD(fs->win+FSI_StrucSig, 0x61417272); + ST_DWORD(fs->win+FSI_Free_Count, fs->free_clust); + ST_DWORD(fs->win+FSI_Nxt_Free, fs->last_clust); + disk_write(fs->drv, fs->win, fs->fsi_sector, 1); + fs->fsi_flag = 0; + } + /* Make sure that no pending write process in the physical drive */ + if (disk_ioctl(fs->drv, CTRL_SYNC, (BYTE*)0) != RES_OK) + res = FR_DISK_ERR; + } + + return res; +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* Get sector# from cluster# */ +/*-----------------------------------------------------------------------*/ + + +DWORD clust2sect ( /* !=0: Sector number, 0: Failed - invalid cluster# */ + FATFS *fs, /* File system object */ + DWORD clst /* Cluster# to be converted */ +) +{ + clst -= 2; + if (clst >= (fs->n_fatent - 2)) return 0; /* Invalid cluster# */ + return clst * fs->csize + fs->database; +} + + + + +/*-----------------------------------------------------------------------*/ +/* FAT access - Read value of a FAT entry */ +/*-----------------------------------------------------------------------*/ + + +DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, Else:Cluster status */ + FATFS *fs, /* File system object */ + DWORD clst /* Cluster# to get the link information */ +) +{ + UINT wc, bc; + BYTE *p; + + + if (clst < 2 || clst >= fs->n_fatent) /* Check range */ + return 1; + + switch (fs->fs_type) { + case FS_FAT12 : + bc = (UINT)clst; bc += bc / 2; + if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break; + wc = fs->win[bc % SS(fs)]; bc++; + if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break; + wc |= fs->win[bc % SS(fs)] << 8; + return (clst & 1) ? (wc >> 4) : (wc & 0xFFF); + + case FS_FAT16 : + if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)))) break; + p = &fs->win[clst * 2 % SS(fs)]; + return LD_WORD(p); + + case FS_FAT32 : + if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)))) break; + p = &fs->win[clst * 4 % SS(fs)]; + return LD_DWORD(p) & 0x0FFFFFFF; + } + + return 0xFFFFFFFF; /* An error occurred at the disk I/O layer */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* FAT access - Change value of a FAT entry */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY + +FRESULT put_fat ( + FATFS *fs, /* File system object */ + DWORD clst, /* Cluster# to be changed in range of 2 to fs->n_fatent - 1 */ + DWORD val /* New value to mark the cluster */ +) +{ + UINT bc; + BYTE *p; + FRESULT res; + + + if (clst < 2 || clst >= fs->n_fatent) { /* Check range */ + res = FR_INT_ERR; + + } else { + switch (fs->fs_type) { + case FS_FAT12 : + bc = clst; bc += bc / 2; + res = move_window(fs, fs->fatbase + (bc / SS(fs))); + if (res != FR_OK) break; + p = &fs->win[bc % SS(fs)]; + *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; + bc++; + fs->wflag = 1; + res = move_window(fs, fs->fatbase + (bc / SS(fs))); + if (res != FR_OK) break; + p = &fs->win[bc % SS(fs)]; + *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F)); + break; + + case FS_FAT16 : + res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))); + if (res != FR_OK) break; + p = &fs->win[clst * 2 % SS(fs)]; + ST_WORD(p, (WORD)val); + break; + + case FS_FAT32 : + res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))); + if (res != FR_OK) break; + p = &fs->win[clst * 4 % SS(fs)]; + val |= LD_DWORD(p) & 0xF0000000; + ST_DWORD(p, val); + break; + + default : + res = FR_INT_ERR; + } + fs->wflag = 1; + } + + return res; +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* FAT handling - Remove a cluster chain */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +FRESULT remove_chain ( + FATFS *fs, /* File system object */ + DWORD clst /* Cluster# to remove a chain from */ +) +{ + FRESULT res; + DWORD nxt; +#if _USE_ERASE + DWORD scl = clst, ecl = clst, resion[2]; +#endif + + if (clst < 2 || clst >= fs->n_fatent) { /* Check range */ + res = FR_INT_ERR; + + } else { + res = FR_OK; + while (clst < fs->n_fatent) { /* Not a last link? */ + nxt = get_fat(fs, clst); /* Get cluster status */ + if (nxt == 0) break; /* Empty cluster? */ + if (nxt == 1) { res = FR_INT_ERR; break; } /* Internal error? */ + if (nxt == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } /* Disk error? */ + res = put_fat(fs, clst, 0); /* Mark the cluster "empty" */ + if (res != FR_OK) break; + if (fs->free_clust != 0xFFFFFFFF) { /* Update FSInfo */ + fs->free_clust++; + fs->fsi_flag = 1; + } +#if _USE_ERASE + if (ecl + 1 == nxt) { /* Next cluster is contiguous */ + ecl = nxt; + } else { /* End of contiguous clusters */ + resion[0] = clust2sect(fs, scl); /* Start sector */ + resion[1] = clust2sect(fs, ecl) + fs->csize - 1; /* End sector */ + disk_ioctl(fs->drv, CTRL_ERASE_SECTOR, resion); /* Erase the block */ + scl = ecl = nxt; + } +#endif + clst = nxt; /* Next cluster */ + } + } + + return res; +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* FAT handling - Stretch or Create a cluster chain */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */ + FATFS *fs, /* File system object */ + DWORD clst /* Cluster# to stretch. 0 means create a new chain. */ +) +{ + DWORD cs, ncl, scl; + FRESULT res; + + + if (clst == 0) { /* Create a new chain */ + scl = fs->last_clust; /* Get suggested start point */ + if (!scl || scl >= fs->n_fatent) scl = 1; + } + else { /* Stretch the current chain */ + cs = get_fat(fs, clst); /* Check the cluster status */ + if (cs < 2) return 1; /* It is an invalid cluster */ + if (cs < fs->n_fatent) return cs; /* It is already followed by next cluster */ + scl = clst; + } + + ncl = scl; /* Start cluster */ + for (;;) { + ncl++; /* Next cluster */ + if (ncl >= fs->n_fatent) { /* Wrap around */ + ncl = 2; + if (ncl > scl) return 0; /* No free cluster */ + } + cs = get_fat(fs, ncl); /* Get the cluster status */ + if (cs == 0) break; /* Found a free cluster */ + if (cs == 0xFFFFFFFF || cs == 1)/* An error occurred */ + return cs; + if (ncl == scl) return 0; /* No free cluster */ + } + + res = put_fat(fs, ncl, 0x0FFFFFFF); /* Mark the new cluster "last link" */ + if (res == FR_OK && clst != 0) { + res = put_fat(fs, clst, ncl); /* Link it to the previous one if needed */ + } + if (res == FR_OK) { + fs->last_clust = ncl; /* Update FSINFO */ + if (fs->free_clust != 0xFFFFFFFF) { + fs->free_clust--; + fs->fsi_flag = 1; + } + } else { + ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1; + } + + return ncl; /* Return new cluster number or error code */ +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Set directory index */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT dir_sdi ( + DIR *dj, /* Pointer to directory object */ + WORD idx /* Directory index number */ +) +{ + DWORD clst; + WORD ic; + + + dj->index = idx; + clst = dj->sclust; + if (clst == 1 || clst >= dj->fs->n_fatent) /* Check start cluster range */ + return FR_INT_ERR; + if (!clst && dj->fs->fs_type == FS_FAT32) /* Replace cluster# 0 with root cluster# if in FAT32 */ + clst = dj->fs->dirbase; + + if (clst == 0) { /* Static table (root-dir in FAT12/16) */ + dj->clust = clst; + if (idx >= dj->fs->n_rootdir) /* Index is out of range */ + return FR_INT_ERR; + dj->sect = dj->fs->dirbase + idx / (SS(dj->fs) / 32); /* Sector# */ + } + else { /* Dynamic table (sub-dirs or root-dir in FAT32) */ + ic = SS(dj->fs) / 32 * dj->fs->csize; /* Entries per cluster */ + while (idx >= ic) { /* Follow cluster chain */ + clst = get_fat(dj->fs, clst); /* Get next cluster */ + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ + if (clst < 2 || clst >= dj->fs->n_fatent) /* Reached to end of table or int error */ + return FR_INT_ERR; + idx -= ic; + } + dj->clust = clst; + dj->sect = clust2sect(dj->fs, clst) + idx / (SS(dj->fs) / 32); /* Sector# */ + } + + dj->dir = dj->fs->win + (idx % (SS(dj->fs) / 32)) * 32; /* Ptr to the entry in the sector */ + + return FR_OK; /* Seek succeeded */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Move directory index next */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT dir_next ( /* FR_OK:Succeeded, FR_NO_FILE:End of table, FR_DENIED:EOT and could not stretch */ + DIR *dj, /* Pointer to directory object */ + int stretch /* 0: Do not stretch table, 1: Stretch table if needed */ +) +{ + DWORD clst; + WORD i; + + + i = dj->index + 1; + if (!i || !dj->sect) /* Report EOT when index has reached 65535 */ + return FR_NO_FILE; + + if (!(i % (SS(dj->fs) / 32))) { /* Sector changed? */ + dj->sect++; /* Next sector */ + + if (dj->clust == 0) { /* Static table */ + if (i >= dj->fs->n_rootdir) /* Report EOT when end of table */ + return FR_NO_FILE; + } + else { /* Dynamic table */ + if (((i / (SS(dj->fs) / 32)) & (dj->fs->csize - 1)) == 0) { /* Cluster changed? */ + clst = get_fat(dj->fs, dj->clust); /* Get next cluster */ + if (clst <= 1) return FR_INT_ERR; + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; + if (clst >= dj->fs->n_fatent) { /* When it reached end of dynamic table */ +#if !_FS_READONLY + BYTE c; + if (!stretch) return FR_NO_FILE; /* When do not stretch, report EOT */ + clst = create_chain(dj->fs, dj->clust); /* Stretch cluster chain */ + if (clst == 0) return FR_DENIED; /* No free cluster */ + if (clst == 1) return FR_INT_ERR; + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; + /* Clean-up stretched table */ + if (move_window(dj->fs, 0)) return FR_DISK_ERR; /* Flush active window */ + mem_set(dj->fs->win, 0, SS(dj->fs)); /* Clear window buffer */ + dj->fs->winsect = clust2sect(dj->fs, clst); /* Cluster start sector */ + for (c = 0; c < dj->fs->csize; c++) { /* Fill the new cluster with 0 */ + dj->fs->wflag = 1; + if (move_window(dj->fs, 0)) return FR_DISK_ERR; + dj->fs->winsect++; + } + dj->fs->winsect -= c; /* Rewind window address */ +#else + return FR_NO_FILE; /* Report EOT */ +#endif + } + dj->clust = clst; /* Initialize data for new cluster */ + dj->sect = clust2sect(dj->fs, clst); + } + } + } + + dj->index = i; + dj->dir = dj->fs->win + (i % (SS(dj->fs) / 32)) * 32; + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* LFN handling - Test/Pick/Fit an LFN segment from/to directory entry */ +/*-----------------------------------------------------------------------*/ +#if _USE_LFN +static +const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30}; /* Offset of LFN chars in the directory entry */ + + +static +int cmp_lfn ( /* 1:Matched, 0:Not matched */ + WCHAR *lfnbuf, /* Pointer to the LFN to be compared */ + BYTE *dir /* Pointer to the directory entry containing a part of LFN */ +) +{ + UINT i, s; + WCHAR wc, uc; + + + i = ((dir[LDIR_Ord] & 0xBF) - 1) * 13; /* Get offset in the LFN buffer */ + s = 0; wc = 1; + do { + uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */ + if (wc) { /* Last char has not been processed */ + wc = ff_wtoupper(uc); /* Convert it to upper case */ + if (i >= _MAX_LFN || wc != ff_wtoupper(lfnbuf[i++])) /* Compare it */ + return 0; /* Not matched */ + } else { + if (uc != 0xFFFF) return 0; /* Check filler */ + } + } while (++s < 13); /* Repeat until all chars in the entry are checked */ + + if ((dir[LDIR_Ord] & 0x40) && wc && lfnbuf[i]) /* Last segment matched but different length */ + return 0; + + return 1; /* The part of LFN matched */ +} + + + +static +int pick_lfn ( /* 1:Succeeded, 0:Buffer overflow */ + WCHAR *lfnbuf, /* Pointer to the Unicode-LFN buffer */ + BYTE *dir /* Pointer to the directory entry */ +) +{ + UINT i, s; + WCHAR wc, uc; + + + i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13; /* Offset in the LFN buffer */ + + s = 0; wc = 1; + do { + uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */ + if (wc) { /* Last char has not been processed */ + if (i >= _MAX_LFN) return 0; /* Buffer overflow? */ + lfnbuf[i++] = wc = uc; /* Store it */ + } else { + if (uc != 0xFFFF) return 0; /* Check filler */ + } + } while (++s < 13); /* Read all character in the entry */ + + if (dir[LDIR_Ord] & 0x40) { /* Put terminator if it is the last LFN part */ + if (i >= _MAX_LFN) return 0; /* Buffer overflow? */ + lfnbuf[i] = 0; + } + + return 1; +} + + +#if !_FS_READONLY +static +void fit_lfn ( + const WCHAR *lfnbuf, /* Pointer to the LFN buffer */ + BYTE *dir, /* Pointer to the directory entry */ + BYTE ord, /* LFN order (1-20) */ + BYTE sum /* SFN sum */ +) +{ + UINT i, s; + WCHAR wc; + + + dir[LDIR_Chksum] = sum; /* Set check sum */ + dir[LDIR_Attr] = AM_LFN; /* Set attribute. LFN entry */ + dir[LDIR_Type] = 0; + ST_WORD(dir+LDIR_FstClusLO, 0); + + i = (ord - 1) * 13; /* Get offset in the LFN buffer */ + s = wc = 0; + do { + if (wc != 0xFFFF) wc = lfnbuf[i++]; /* Get an effective char */ + ST_WORD(dir+LfnOfs[s], wc); /* Put it */ + if (!wc) wc = 0xFFFF; /* Padding chars following last char */ + } while (++s < 13); + if (wc == 0xFFFF || !lfnbuf[i]) ord |= 0x40; /* Bottom LFN part is the start of LFN sequence */ + dir[LDIR_Ord] = ord; /* Set the LFN order */ +} + +#endif +#endif + + + +/*-----------------------------------------------------------------------*/ +/* Create numbered name */ +/*-----------------------------------------------------------------------*/ +#if _USE_LFN +void gen_numname ( + BYTE *dst, /* Pointer to generated SFN */ + const BYTE *src, /* Pointer to source SFN to be modified */ + const WCHAR *lfn, /* Pointer to LFN */ + WORD seq /* Sequence number */ +) +{ + BYTE ns[8], c; + UINT i, j; + + + mem_cpy(dst, src, 11); + + if (seq > 5) { /* On many collisions, generate a hash number instead of sequential number */ + do seq = (seq >> 1) + (seq << 15) + (WORD)*lfn++; while (*lfn); + } + + /* itoa */ + i = 7; + do { + c = (seq % 16) + '0'; + if (c > '9') c += 7; + ns[i--] = c; + seq /= 16; + } while (seq); + ns[i] = '~'; + + /* Append the number */ + for (j = 0; j < i && dst[j] != ' '; j++) { + if (IsDBCS1(dst[j])) { + if (j == i - 1) break; + j++; + } + } + do { + dst[j++] = (i < 8) ? ns[i++] : ' '; + } while (j < 8); +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* Calculate sum of an SFN */ +/*-----------------------------------------------------------------------*/ +#if _USE_LFN +static +BYTE sum_sfn ( + const BYTE *dir /* Ptr to directory entry */ +) +{ + BYTE sum = 0; + UINT n = 11; + + do sum = (sum >> 1) + (sum << 7) + *dir++; while (--n); + return sum; +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Find an object in the directory */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT dir_find ( + DIR *dj /* Pointer to the directory object linked to the file name */ +) +{ + FRESULT res; + BYTE c, *dir; +#if _USE_LFN + BYTE a, ord, sum; +#endif + + res = dir_sdi(dj, 0); /* Rewind directory object */ + if (res != FR_OK) return res; + +#if _USE_LFN + ord = sum = 0xFF; +#endif + do { + res = move_window(dj->fs, dj->sect); + if (res != FR_OK) break; + dir = dj->dir; /* Ptr to the directory entry of current index */ + c = dir[DIR_Name]; + if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ +#if _USE_LFN /* LFN configuration */ + a = dir[DIR_Attr] & AM_MASK; + if (c == 0xE5 || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */ + ord = 0xFF; + } else { + if (a == AM_LFN) { /* An LFN entry is found */ + if (dj->lfn) { + if (c & 0x40) { /* Is it start of LFN sequence? */ + sum = dir[LDIR_Chksum]; + c &= 0xBF; ord = c; /* LFN start order */ + dj->lfn_idx = dj->index; + } + /* Check validity of the LFN entry and compare it with given name */ + ord = (c == ord && sum == dir[LDIR_Chksum] && cmp_lfn(dj->lfn, dir)) ? ord - 1 : 0xFF; + } + } else { /* An SFN entry is found */ + if (!ord && sum == sum_sfn(dir)) break; /* LFN matched? */ + ord = 0xFF; dj->lfn_idx = 0xFFFF; /* Reset LFN sequence */ + if (!(dj->fn[NS] & NS_LOSS) && !mem_cmp(dir, dj->fn, 11)) break; /* SFN matched? */ + } + } +#else /* Non LFN configuration */ + if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dj->fn, 11)) /* Is it a valid entry? */ + break; +#endif + res = dir_next(dj, 0); /* Next entry */ + } while (res == FR_OK); + + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read an object from the directory */ +/*-----------------------------------------------------------------------*/ +#if _FS_MINIMIZE <= 1 +static +FRESULT dir_read ( + DIR *dj /* Pointer to the directory object that pointing the entry to be read */ +) +{ + FRESULT res; + BYTE c, *dir; +#if _USE_LFN + BYTE a, ord = 0xFF, sum = 0xFF; +#endif + + res = FR_NO_FILE; + while (dj->sect) { + res = move_window(dj->fs, dj->sect); + if (res != FR_OK) break; + dir = dj->dir; /* Ptr to the directory entry of current index */ + c = dir[DIR_Name]; + if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ +#if _USE_LFN /* LFN configuration */ + a = dir[DIR_Attr] & AM_MASK; + if (c == 0xE5 || (!_FS_RPATH && c == '.') || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */ + ord = 0xFF; + } else { + if (a == AM_LFN) { /* An LFN entry is found */ + if (c & 0x40) { /* Is it start of LFN sequence? */ + sum = dir[LDIR_Chksum]; + c &= 0xBF; ord = c; + dj->lfn_idx = dj->index; + } + /* Check LFN validity and capture it */ + ord = (c == ord && sum == dir[LDIR_Chksum] && pick_lfn(dj->lfn, dir)) ? ord - 1 : 0xFF; + } else { /* An SFN entry is found */ + if (ord || sum != sum_sfn(dir)) /* Is there a valid LFN? */ + dj->lfn_idx = 0xFFFF; /* It has no LFN. */ + break; + } + } +#else /* Non LFN configuration */ + if (c != 0xE5 && (_FS_RPATH || c != '.') && !(dir[DIR_Attr] & AM_VOL)) /* Is it a valid entry? */ + break; +#endif + res = dir_next(dj, 0); /* Next entry */ + if (res != FR_OK) break; + } + + if (res != FR_OK) dj->sect = 0; + + return res; +} +#endif + + + +/*-----------------------------------------------------------------------*/ +/* Register an object to the directory */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +FRESULT dir_register ( /* FR_OK:Successful, FR_DENIED:No free entry or too many SFN collision, FR_DISK_ERR:Disk error */ + DIR *dj /* Target directory with object name to be created */ +) +{ + FRESULT res; + BYTE c, *dir; +#if _USE_LFN /* LFN configuration */ + WORD n, ne, is; + BYTE sn[12], *fn, sum; + WCHAR *lfn; + + + fn = dj->fn; lfn = dj->lfn; + mem_cpy(sn, fn, 12); + + if (_FS_RPATH && (sn[NS] & NS_DOT)) /* Cannot create dot entry */ + return FR_INVALID_NAME; + + if (sn[NS] & NS_LOSS) { /* When LFN is out of 8.3 format, generate a numbered name */ + fn[NS] = 0; dj->lfn = 0; /* Find only SFN */ + for (n = 1; n < 100; n++) { + gen_numname(fn, sn, lfn, n); /* Generate a numbered name */ + res = dir_find(dj); /* Check if the name collides with existing SFN */ + if (res != FR_OK) break; + } + if (n == 100) return FR_DENIED; /* Abort if too many collisions */ + if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */ + fn[NS] = sn[NS]; dj->lfn = lfn; + } + + if (sn[NS] & NS_LFN) { /* When LFN is to be created, reserve an SFN + LFN entries. */ + for (ne = 0; lfn[ne]; ne++) ; + ne = (ne + 25) / 13; + } else { /* Otherwise reserve only an SFN entry. */ + ne = 1; + } + + /* Reserve contiguous entries */ + res = dir_sdi(dj, 0); + if (res != FR_OK) return res; + n = is = 0; + do { + res = move_window(dj->fs, dj->sect); + if (res != FR_OK) break; + c = *dj->dir; /* Check the entry status */ + if (c == 0xE5 || c == 0) { /* Is it a blank entry? */ + if (n == 0) is = dj->index; /* First index of the contiguous entry */ + if (++n == ne) break; /* A contiguous entry that required count is found */ + } else { + n = 0; /* Not a blank entry. Restart to search */ + } + res = dir_next(dj, 1); /* Next entry with table stretch */ + } while (res == FR_OK); + + if (res == FR_OK && ne > 1) { /* Initialize LFN entry if needed */ + res = dir_sdi(dj, is); + if (res == FR_OK) { + sum = sum_sfn(dj->fn); /* Sum of the SFN tied to the LFN */ + ne--; + do { /* Store LFN entries in bottom first */ + res = move_window(dj->fs, dj->sect); + if (res != FR_OK) break; + fit_lfn(dj->lfn, dj->dir, (BYTE)ne, sum); + dj->fs->wflag = 1; + res = dir_next(dj, 0); /* Next entry */ + } while (res == FR_OK && --ne); + } + } + +#else /* Non LFN configuration */ + res = dir_sdi(dj, 0); + if (res == FR_OK) { + do { /* Find a blank entry for the SFN */ + res = move_window(dj->fs, dj->sect); + if (res != FR_OK) break; + c = *dj->dir; + if (c == 0xE5 || c == 0) break; /* Is it a blank entry? */ + res = dir_next(dj, 1); /* Next entry with table stretch */ + } while (res == FR_OK); + } +#endif + + if (res == FR_OK) { /* Initialize the SFN entry */ + res = move_window(dj->fs, dj->sect); + if (res == FR_OK) { + dir = dj->dir; + mem_set(dir, 0, 32); /* Clean the entry */ + mem_cpy(dir, dj->fn, 11); /* Put SFN */ +#if _USE_LFN + dir[DIR_NTres] = *(dj->fn+NS) & (NS_BODY | NS_EXT); /* Put NT flag */ +#endif + dj->fs->wflag = 1; + } + } + + return res; +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Remove an object from the directory */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY && !_FS_MINIMIZE +static +FRESULT dir_remove ( /* FR_OK: Successful, FR_DISK_ERR: A disk error */ + DIR *dj /* Directory object pointing the entry to be removed */ +) +{ + FRESULT res; +#if _USE_LFN /* LFN configuration */ + WORD i; + + i = dj->index; /* SFN index */ + res = dir_sdi(dj, (WORD)((dj->lfn_idx == 0xFFFF) ? i : dj->lfn_idx)); /* Goto the SFN or top of the LFN entries */ + if (res == FR_OK) { + do { + res = move_window(dj->fs, dj->sect); + if (res != FR_OK) break; + *dj->dir = 0xE5; /* Mark the entry "deleted" */ + dj->fs->wflag = 1; + if (dj->index >= i) break; /* When reached SFN, all entries of the object has been deleted. */ + res = dir_next(dj, 0); /* Next entry */ + } while (res == FR_OK); + if (res == FR_NO_FILE) res = FR_INT_ERR; + } + +#else /* Non LFN configuration */ + res = dir_sdi(dj, dj->index); + if (res == FR_OK) { + res = move_window(dj->fs, dj->sect); + if (res == FR_OK) { + *dj->dir = 0xE5; /* Mark the entry "deleted" */ + dj->fs->wflag = 1; + } + } +#endif + + return res; +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Pick a segment and create the object name in directory form */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT create_name ( + DIR *dj, /* Pointer to the directory object */ + const TCHAR **path /* Pointer to pointer to the segment in the path string */ +) +{ +#ifdef _EXCVT + static const BYTE excvt[] = _EXCVT; /* Upper conversion table for extended chars */ +#endif + +#if _USE_LFN /* LFN configuration */ + BYTE b, cf; + WCHAR w, *lfn; + UINT i, ni, si, di; + const TCHAR *p; + + /* Create LFN in Unicode */ + si = di = 0; + p = *path; + lfn = dj->lfn; + for (;;) { + w = p[si++]; /* Get a character */ + if (w < ' ' || w == '/' || w == '\\') break; /* Break on end of segment */ + if (di >= _MAX_LFN) /* Reject too long name */ + return FR_INVALID_NAME; +#if !_LFN_UNICODE + w &= 0xFF; + if (IsDBCS1(w)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */ + b = (BYTE)p[si++]; /* Get 2nd byte */ + if (!IsDBCS2(b)) + return FR_INVALID_NAME; /* Reject invalid sequence */ + w = (w << 8) + b; /* Create a DBC */ + } + w = ff_convert(w, 1); /* Convert ANSI/OEM to Unicode */ + if (!w) return FR_INVALID_NAME; /* Reject invalid code */ +#endif + if (w < 0x80 && chk_chr("\"*:<>\?|\x7F", w)) /* Reject illegal chars for LFN */ + return FR_INVALID_NAME; + lfn[di++] = w; /* Store the Unicode char */ + } + *path = &p[si]; /* Return pointer to the next segment */ + cf = (w < ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */ +#if _FS_RPATH + if ((di == 1 && lfn[di-1] == '.') || /* Is this a dot entry? */ + (di == 2 && lfn[di-1] == '.' && lfn[di-2] == '.')) { + lfn[di] = 0; + for (i = 0; i < 11; i++) + dj->fn[i] = (i < di) ? '.' : ' '; + dj->fn[i] = cf | NS_DOT; /* This is a dot entry */ + return FR_OK; + } +#endif + while (di) { /* Strip trailing spaces and dots */ + w = lfn[di-1]; + if (w != ' ' && w != '.') break; + di--; + } + if (!di) return FR_INVALID_NAME; /* Reject nul string */ + + lfn[di] = 0; /* LFN is created */ + + /* Create SFN in directory form */ + mem_set(dj->fn, ' ', 11); + for (si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++) ; /* Strip leading spaces and dots */ + if (si) cf |= NS_LOSS | NS_LFN; + while (di && lfn[di - 1] != '.') di--; /* Find extension (di<=si: no extension) */ + + b = i = 0; ni = 8; + for (;;) { + w = lfn[si++]; /* Get an LFN char */ + if (!w) break; /* Break on end of the LFN */ + if (w == ' ' || (w == '.' && si != di)) { /* Remove spaces and dots */ + cf |= NS_LOSS | NS_LFN; continue; + } + + if (i >= ni || si == di) { /* Extension or end of SFN */ + if (ni == 11) { /* Long extension */ + cf |= NS_LOSS | NS_LFN; break; + } + if (si != di) cf |= NS_LOSS | NS_LFN; /* Out of 8.3 format */ + if (si > di) break; /* No extension */ + si = di; i = 8; ni = 11; /* Enter extension section */ + b <<= 2; continue; + } + + if (w >= 0x80) { /* Non ASCII char */ +#ifdef _EXCVT + w = ff_convert(w, 0); /* Unicode -> OEM code */ + if (w) w = excvt[w - 0x80]; /* Convert extended char to upper (SBCS) */ +#else + w = ff_convert(ff_wtoupper(w), 0); /* Upper converted Unicode -> OEM code */ +#endif + cf |= NS_LFN; /* Force create LFN entry */ + } + + if (_DF1S && w >= 0x100) { /* Double byte char (always false on SBCS cfg) */ + if (i >= ni - 1) { + cf |= NS_LOSS | NS_LFN; i = ni; continue; + } + dj->fn[i++] = (BYTE)(w >> 8); + } else { /* Single byte char */ + if (!w || chk_chr("+,;=[]", w)) { /* Replace illegal chars for SFN */ + w = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */ + } else { + if (IsUpper(w)) { /* ASCII large capital */ + b |= 2; + } else { + if (IsLower(w)) { /* ASCII small capital */ + b |= 1; w -= 0x20; + } + } + } + } + dj->fn[i++] = (BYTE)w; + } + + if (dj->fn[0] == 0xE5) dj->fn[0] = 0x05; /* If the first char collides with deleted mark, replace it with 0x05 */ + + if (ni == 8) b <<= 2; + if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) /* Create LFN entry when there are composite capitals */ + cf |= NS_LFN; + if (!(cf & NS_LFN)) { /* When LFN is in 8.3 format without extended char, NT flags are created */ + if ((b & 0x03) == 0x01) cf |= NS_EXT; /* NT flag (Extension has only small capital) */ + if ((b & 0x0C) == 0x04) cf |= NS_BODY; /* NT flag (Filename has only small capital) */ + } + + dj->fn[NS] = cf; /* SFN is created */ + + return FR_OK; + + +#else /* Non-LFN configuration */ + BYTE b, c, d, *sfn; + UINT ni, si, i; + const char *p; + + /* Create file name in directory form */ + sfn = dj->fn; + mem_set(sfn, ' ', 11); + si = i = b = 0; ni = 8; + p = *path; +#if _FS_RPATH + if (p[si] == '.') { /* Is this a dot entry? */ + for (;;) { + c = (BYTE)p[si++]; + if (c != '.' || si >= 3) break; + sfn[i++] = c; + } + if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME; + *path = &p[si]; /* Return pointer to the next segment */ + sfn[NS] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT; /* Set last segment flag if end of path */ + return FR_OK; + } +#endif + for (;;) { + c = (BYTE)p[si++]; + if (c <= ' ' || c == '/' || c == '\\') break; /* Break on end of segment */ + if (c == '.' || i >= ni) { + if (ni != 8 || c != '.') return FR_INVALID_NAME; + i = 8; ni = 11; + b <<= 2; continue; + } + if (c >= 0x80) { /* Extended char? */ + b |= 3; /* Eliminate NT flag */ +#ifdef _EXCVT + c = excvt[c-0x80]; /* Upper conversion (SBCS) */ +#else +#if !_DF1S /* ASCII only cfg */ + return FR_INVALID_NAME; +#endif +#endif + } + if (IsDBCS1(c)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */ + d = (BYTE)p[si++]; /* Get 2nd byte */ + if (!IsDBCS2(d) || i >= ni - 1) /* Reject invalid DBC */ + return FR_INVALID_NAME; + sfn[i++] = c; + sfn[i++] = d; + } else { /* Single byte code */ + if (chk_chr("\"*+,:;<=>\?[]|\x7F", c)) /* Reject illegal chrs for SFN */ + return FR_INVALID_NAME; + if (IsUpper(c)) { /* ASCII large capital? */ + b |= 2; + } else { + if (IsLower(c)) { /* ASCII small capital? */ + b |= 1; c -= 0x20; + } + } + sfn[i++] = c; + } + } + *path = &p[si]; /* Return pointer to the next segment */ + c = (c <= ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */ + + if (!i) return FR_INVALID_NAME; /* Reject nul string */ + if (sfn[0] == 0xE5) sfn[0] = 0x05; /* When first char collides with 0xE5, replace it with 0x05 */ + + if (ni == 8) b <<= 2; + if ((b & 0x03) == 0x01) c |= NS_EXT; /* NT flag (Name extension has only small capital) */ + if ((b & 0x0C) == 0x04) c |= NS_BODY; /* NT flag (Name body has only small capital) */ + + sfn[NS] = c; /* Store NT flag, File name is created */ + + return FR_OK; +#endif +} + + + + +/*-----------------------------------------------------------------------*/ +/* Get file information from directory entry */ +/*-----------------------------------------------------------------------*/ +#if _FS_MINIMIZE <= 1 +static +void get_fileinfo ( /* No return code */ + DIR *dj, /* Pointer to the directory object */ + FILINFO *fno /* Pointer to the file information to be filled */ +) +{ + UINT i; + BYTE nt, *dir; + TCHAR *p, c; + + + p = fno->fname; + if (dj->sect) { + dir = dj->dir; + nt = dir[DIR_NTres]; /* NT flag */ + for (i = 0; i < 8; i++) { /* Copy name body */ + c = dir[i]; + if (c == ' ') break; + if (c == 0x05) c = (TCHAR)0xE5; + if (_USE_LFN && (nt & NS_BODY) && IsUpper(c)) c += 0x20; +#if _LFN_UNICODE + if (IsDBCS1(c) && i < 7 && IsDBCS2(dir[i+1])) + c = (c << 8) | dir[++i]; + c = ff_convert(c, 1); + if (!c) c = '?'; +#endif + *p++ = c; + } + if (dir[8] != ' ') { /* Copy name extension */ + *p++ = '.'; + for (i = 8; i < 11; i++) { + c = dir[i]; + if (c == ' ') break; + if (_USE_LFN && (nt & NS_EXT) && IsUpper(c)) c += 0x20; +#if _LFN_UNICODE + if (IsDBCS1(c) && i < 10 && IsDBCS2(dir[i+1])) + c = (c << 8) | dir[++i]; + c = ff_convert(c, 1); + if (!c) c = '?'; +#endif + *p++ = c; + } + } + fno->fattrib = dir[DIR_Attr]; /* Attribute */ + fno->fsize = LD_DWORD(dir+DIR_FileSize); /* Size */ + fno->fdate = LD_WORD(dir+DIR_WrtDate); /* Date */ + fno->ftime = LD_WORD(dir+DIR_WrtTime); /* Time */ + } + *p = 0; /* Terminate SFN str by a \0 */ + +#if _USE_LFN + if (fno->lfname && fno->lfsize) { + TCHAR *tp = fno->lfname; + WCHAR w, *lfn; + + i = 0; + if (dj->sect && dj->lfn_idx != 0xFFFF) {/* Get LFN if available */ + lfn = dj->lfn; + while ((w = *lfn++) != 0) { /* Get an LFN char */ +#if !_LFN_UNICODE + w = ff_convert(w, 0); /* Unicode -> OEM conversion */ + if (!w) { i = 0; break; } /* Could not convert, no LFN */ + if (_DF1S && w >= 0x100) /* Put 1st byte if it is a DBC (always false on SBCS cfg) */ + tp[i++] = (TCHAR)(w >> 8); +#endif + if (i >= fno->lfsize - 1) { i = 0; break; } /* Buffer overflow, no LFN */ + tp[i++] = (TCHAR)w; + } + } + tp[i] = 0; /* Terminate the LFN str by a \0 */ + } +#endif +} +#endif /* _FS_MINIMIZE <= 1 */ + + + + +/*-----------------------------------------------------------------------*/ +/* Follow a file path */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */ + DIR *dj, /* Directory object to return last directory and found object */ + const TCHAR *path /* Full-path string to find a file or directory */ +) +{ + FRESULT res; + BYTE *dir, ns; + + +#if _FS_RPATH + if (*path == '/' || *path == '\\') { /* There is a heading separator */ + path++; dj->sclust = 0; /* Strip it and start from the root dir */ + } else { /* No heading separator */ + dj->sclust = dj->fs->cdir; /* Start from the current dir */ + } +#else + if (*path == '/' || *path == '\\') /* Strip heading separator if exist */ + path++; + dj->sclust = 0; /* Start from the root dir */ +#endif + + if ((UINT)*path < ' ') { /* Nul path means the start directory itself */ + res = dir_sdi(dj, 0); + dj->dir = 0; + + } else { /* Follow path */ + for (;;) { + res = create_name(dj, &path); /* Get a segment */ + if (res != FR_OK) break; + res = dir_find(dj); /* Find it */ + ns = *(dj->fn+NS); + if (res != FR_OK) { /* Failed to find the object */ + if (res != FR_NO_FILE) break; /* Abort if any hard error occured */ + /* Object not found */ + if (_FS_RPATH && (ns & NS_DOT)) { /* If dot entry is not exit */ + dj->sclust = 0; dj->dir = 0; /* It is the root dir */ + res = FR_OK; + if (!(ns & NS_LAST)) continue; + } else { /* Could not find the object */ + if (!(ns & NS_LAST)) res = FR_NO_PATH; + } + break; + } + if (ns & NS_LAST) break; /* Last segment match. Function completed. */ + dir = dj->dir; /* There is next segment. Follow the sub directory */ + if (!(dir[DIR_Attr] & AM_DIR)) { /* Cannot follow because it is a file */ + res = FR_NO_PATH; break; + } + dj->sclust = LD_CLUST(dir); + } + } + + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Load boot record and check if it is an FAT boot record */ +/*-----------------------------------------------------------------------*/ + +static +BYTE check_fs ( /* 0:The FAT BR, 1:Valid BR but not an FAT, 2:Not a BR, 3:Disk error */ + FATFS *fs, /* File system object */ + DWORD sect /* Sector# (lba) to check if it is an FAT boot record or not */ +) +{ + if (disk_read(fs->drv, fs->win, sect, 1) != RES_OK) /* Load boot record */ + return 3; + if (LD_WORD(&fs->win[BS_55AA]) != 0xAA55) /* Check record signature (always placed at offset 510 even if the sector size is >512) */ + return 2; + + if ((LD_DWORD(&fs->win[BS_FilSysType]) & 0xFFFFFF) == 0x544146) /* Check "FAT" string */ + return 0; + if ((LD_DWORD(&fs->win[BS_FilSysType32]) & 0xFFFFFF) == 0x544146) + return 0; + + return 1; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Check if the file system object is valid or not */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT chk_mounted ( /* FR_OK(0): successful, !=0: any error occurred */ + const TCHAR **path, /* Pointer to pointer to the path name (drive number) */ + FATFS **rfs, /* Pointer to pointer to the found file system object */ + BYTE chk_wp /* !=0: Check media write protection for write access */ +) +{ + BYTE fmt, b, *tbl; + UINT vol; + DSTATUS stat; + DWORD bsect, fasize, tsect, sysect, nclst, szbfat; + WORD nrsv; + const TCHAR *p = *path; + FATFS *fs; + + /* Get logical drive number from the path name */ + vol = p[0] - '0'; /* Is there a drive number? */ + if (vol <= 9 && p[1] == ':') { /* Found a drive number, get and strip it */ + p += 2; *path = p; /* Return pointer to the path name */ + } else { /* No drive number is given */ +#if _FS_RPATH + vol = CurrVol; /* Use current drive */ +#else + vol = 0; /* Use drive 0 */ +#endif + } + + /* Check if the logical drive is valid or not */ + if (vol >= _VOLUMES) /* Is the drive number valid? */ + return FR_INVALID_DRIVE; + *rfs = fs = FatFs[vol]; /* Return pointer to the corresponding file system object */ + if (!fs) return FR_NOT_ENABLED; /* Is the file system object available? */ + + ENTER_FF(fs); /* Lock file system */ + + if (fs->fs_type) { /* If the logical drive has been mounted */ + stat = disk_status(fs->drv); + if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized (has not been changed), */ +#if !_FS_READONLY + if (chk_wp && (stat & STA_PROTECT)) /* Check write protection if needed */ + return FR_WRITE_PROTECTED; +#endif + return FR_OK; /* The file system object is valid */ + } + } + + /* The logical drive must be mounted. */ + /* Following code attempts to mount a volume. (analyze BPB and initialize the fs object) */ + + fs->fs_type = 0; /* Clear the file system object */ + fs->drv = (BYTE)LD2PD(vol); /* Bind the logical drive and a physical drive */ + stat = disk_initialize(fs->drv); /* Initialize low level disk I/O layer */ + if (stat & STA_NOINIT) /* Check if the initialization succeeded */ + return FR_NOT_READY; /* Failed to initialize due to no media or hard error */ +#if _MAX_SS != 512 /* Get disk sector size (variable sector size cfg only) */ + if (disk_ioctl(fs->drv, GET_SECTOR_SIZE, &fs->ssize) != RES_OK) + return FR_DISK_ERR; +#endif +#if !_FS_READONLY + if (chk_wp && (stat & STA_PROTECT)) /* Check disk write protection if needed */ + return FR_WRITE_PROTECTED; +#endif + /* Search FAT partition on the drive. Supports only generic partitionings, FDISK and SFD. */ + fmt = check_fs(fs, bsect = 0); /* Check sector 0 if it is a VBR */ + if (fmt == 1) { /* Not an FAT-VBR, the disk may be partitioned */ + /* Check the partition listed in top of the partition table */ + tbl = &fs->win[MBR_Table + LD2PT(vol) * 16]; /* Partition table */ + if (tbl[4]) { /* Is the partition existing? */ + bsect = LD_DWORD(&tbl[8]); /* Partition offset in LBA */ + fmt = check_fs(fs, bsect); /* Check the partition */ + } + } + if (fmt == 3) return FR_DISK_ERR; + if (fmt) return FR_NO_FILESYSTEM; /* No FAT volume is found */ + + /* Following code initializes the file system object */ + + if (LD_WORD(fs->win+BPB_BytsPerSec) != SS(fs)) /* (BPB_BytsPerSec must be equal to the physical sector size) */ + return FR_NO_FILESYSTEM; + + fasize = LD_WORD(fs->win+BPB_FATSz16); /* Number of sectors per FAT */ + if (!fasize) fasize = LD_DWORD(fs->win+BPB_FATSz32); + fs->fsize = fasize; + + fs->n_fats = b = fs->win[BPB_NumFATs]; /* Number of FAT copies */ + if (b != 1 && b != 2) return FR_NO_FILESYSTEM; /* (Must be 1 or 2) */ + fasize *= b; /* Number of sectors for FAT area */ + + fs->csize = b = fs->win[BPB_SecPerClus]; /* Number of sectors per cluster */ + if (!b || (b & (b - 1))) return FR_NO_FILESYSTEM; /* (Must be power of 2) */ + + fs->n_rootdir = LD_WORD(fs->win+BPB_RootEntCnt); /* Number of root directory entries */ + if (fs->n_rootdir % (SS(fs) / 32)) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be sector aligned) */ + + tsect = LD_WORD(fs->win+BPB_TotSec16); /* Number of sectors on the volume */ + if (!tsect) tsect = LD_DWORD(fs->win+BPB_TotSec32); + + nrsv = LD_WORD(fs->win+BPB_RsvdSecCnt); /* Number of reserved sectors */ + if (!nrsv) return FR_NO_FILESYSTEM; /* (BPB_RsvdSecCnt must not be 0) */ + + /* Determine the FAT sub type */ + sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / 32); /* RSV+FAT+DIR */ + if (tsect < sysect) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ + nclst = (tsect - sysect) / fs->csize; /* Number of clusters */ + if (!nclst) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ + fmt = FS_FAT12; + if (nclst >= MIN_FAT16) fmt = FS_FAT16; + if (nclst >= MIN_FAT32) fmt = FS_FAT32; + + /* Boundaries and Limits */ + fs->n_fatent = nclst + 2; /* Number of FAT entries */ + fs->database = bsect + sysect; /* Data start sector */ + fs->fatbase = bsect + nrsv; /* FAT start sector */ + if (fmt == FS_FAT32) { + if (fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */ + fs->dirbase = LD_DWORD(fs->win+BPB_RootClus); /* Root directory start cluster */ + szbfat = fs->n_fatent * 4; /* (Required FAT size) */ + } else { + if (!fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must not be 0) */ + fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */ + szbfat = (fmt == FS_FAT16) ? /* (Required FAT size) */ + fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1); + } + if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) /* (FAT size must not be less than FAT sectors */ + return FR_NO_FILESYSTEM; + +#if !_FS_READONLY + /* Initialize cluster allocation information */ + fs->free_clust = 0xFFFFFFFF; + fs->last_clust = 0; + + /* Get fsinfo if available */ + if (fmt == FS_FAT32) { + fs->fsi_flag = 0; + fs->fsi_sector = bsect + LD_WORD(fs->win+BPB_FSInfo); + if (disk_read(fs->drv, fs->win, fs->fsi_sector, 1) == RES_OK && + LD_WORD(fs->win+BS_55AA) == 0xAA55 && + LD_DWORD(fs->win+FSI_LeadSig) == 0x41615252 && + LD_DWORD(fs->win+FSI_StrucSig) == 0x61417272) { + fs->last_clust = LD_DWORD(fs->win+FSI_Nxt_Free); + fs->free_clust = LD_DWORD(fs->win+FSI_Free_Count); + } + } +#endif + fs->fs_type = fmt; /* FAT sub-type */ + fs->id = ++Fsid; /* File system mount ID */ + fs->winsect = 0; /* Invalidate sector cache */ + fs->wflag = 0; +#if _FS_RPATH + fs->cdir = 0; /* Current directory (root dir) */ +#endif +#if _FS_SHARE /* Clear file lock semaphores */ + clear_lock(fs); +#endif + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Check if the file/dir object is valid or not */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT validate ( /* FR_OK(0): The object is valid, !=0: Invalid */ + FATFS *fs, /* Pointer to the file system object */ + WORD id /* Member id of the target object to be checked */ +) +{ + if (!fs || !fs->fs_type || fs->id != id) + return FR_INVALID_OBJECT; + + ENTER_FF(fs); /* Lock file system */ + + if (disk_status(fs->drv) & STA_NOINIT) + return FR_NOT_READY; + + return FR_OK; +} + + + + +/*-------------------------------------------------------------------------- + + Public Functions + +--------------------------------------------------------------------------*/ + + + +/*-----------------------------------------------------------------------*/ +/* Mount/Unmount a Logical Drive */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_mount ( + BYTE vol, /* Logical drive number to be mounted/unmounted */ + FATFS *fs /* Pointer to new file system object (NULL for unmount)*/ +) +{ + FATFS *rfs; + + + if (vol >= _VOLUMES) /* Check if the drive number is valid */ + return FR_INVALID_DRIVE; + rfs = FatFs[vol]; /* Get current fs object */ + + if (rfs) { +#if _FS_SHARE + clear_lock(rfs); +#endif +#if _FS_REENTRANT /* Discard sync object of the current volume */ + if (!ff_del_syncobj(rfs->sobj)) return FR_INT_ERR; +#endif + rfs->fs_type = 0; /* Clear old fs object */ + } + + if (fs) { + fs->fs_type = 0; /* Clear new fs object */ +#if _FS_REENTRANT /* Create sync object for the new volume */ + if (!ff_cre_syncobj(vol, &fs->sobj)) return FR_INT_ERR; +#endif + } + FatFs[vol] = fs; /* Register new fs object */ + + return FR_OK; +} + + +#ifndef BOOT +/*---------------------------------------------------------*/ +/* User Provided Date/Time Function for FatFs module */ +/*---------------------------------------------------------*/ +/* This is a real time clock service to be called from */ +/* FatFs module. Any valid time must be returned even if */ +/* the system does not support a real time clock. */ +/* This is not required in read-only configuration. */ + +gtime_t g_unixTime; // Global date/time register, incremented each second in per10ms() + +uint32_t o9x_get_fattime(void) +{ + struct gtm t; + filltm(&g_unixTime, &t); // create a struct tm date/time structure from global unix time stamp + + /* Pack date and time into a DWORD variable */ + return ((DWORD)(t.tm_year - 80) << 25) + | ((uint32_t)(t.tm_mon+1) << 21) + | ((uint32_t)t.tm_mday << 16) + | ((uint32_t)t.tm_hour << 11) + | ((uint32_t)t.tm_min << 5) + | ((uint32_t)t.tm_sec >> 1); +} +#endif + +/*-----------------------------------------------------------------------*/ +/* Open or Create a File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_open ( + FIL *fp, /* Pointer to the blank file object */ + const TCHAR *path, /* Pointer to the file name */ + BYTE mode /* Access mode and file open mode flags */ +) +{ + FRESULT res; + DIR dj; + BYTE *dir; + DEF_NAMEBUF; + + + fp->fs = 0; /* Clear file object */ + +#if !_FS_READONLY + mode &= FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW; + res = chk_mounted(&path, &dj.fs, (BYTE)(mode & ~FA_READ)); +#else + mode &= FA_READ; + res = chk_mounted(&path, &dj.fs, 0); +#endif + INIT_BUF(dj); + if (res == FR_OK) + res = follow_path(&dj, path); /* Follow the file path */ + dir = dj.dir; + +#if !_FS_READONLY /* R/W configuration */ + if (res == FR_OK) { + if (!dir) /* Current dir itself */ + res = FR_INVALID_NAME; +#if _FS_SHARE + else + res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0); +#endif + } + /* Create or Open a file */ + if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) { + DWORD dw, cl; + + if (res != FR_OK) { /* No file, create new */ + if (res == FR_NO_FILE) /* There is no file to open, create a new entry */ +#if _FS_SHARE + res = enq_lock(dj.fs) ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES; +#else + res = dir_register(&dj); +#endif + mode |= FA_CREATE_ALWAYS; /* File is created */ + dir = dj.dir; /* New entry */ + } + else { /* Any object is already existing */ + if (mode & FA_CREATE_NEW) { /* Cannot create new */ + res = FR_EXIST; + } else { + if (dir[DIR_Attr] & (AM_RDO | AM_DIR)) /* Cannot overwrite it (R/O or DIR) */ + res = FR_DENIED; + } + } + if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) { /* Truncate it if overwrite mode */ + dw = o9x_get_fattime(); /* Created time */ + ST_DWORD(dir+DIR_CrtTime, dw); + dir[DIR_Attr] = 0; /* Reset attribute */ + ST_DWORD(dir+DIR_FileSize, 0); /* size = 0 */ + cl = LD_CLUST(dir); /* Get start cluster */ + ST_CLUST(dir, 0); /* cluster = 0 */ + dj.fs->wflag = 1; + if (cl) { /* Remove the cluster chain if exist */ + dw = dj.fs->winsect; + res = remove_chain(dj.fs, cl); + if (res == FR_OK) { + dj.fs->last_clust = cl - 1; /* Reuse the cluster hole */ + res = move_window(dj.fs, dw); + } + } + } + } + else { /* Open an existing file */ + if (res == FR_OK) { /* Follow succeeded */ + if (dir[DIR_Attr] & AM_DIR) { /* It is a directory */ + res = FR_NO_FILE; + } else { + if ((mode & FA_WRITE) && (dir[DIR_Attr] & AM_RDO)) /* R/O violation */ + res = FR_DENIED; + } + } + } + if (res == FR_OK) { + if (mode & FA_CREATE_ALWAYS) /* Set file change flag if created or overwritten */ + mode |= FA__WRITTEN; + fp->dir_sect = dj.fs->winsect; /* Pointer to the directory entry */ + fp->dir_ptr = dir; +#if _FS_SHARE + fp->lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0); + if (!fp->lockid) res = FR_INT_ERR; +#endif + } + +#else /* R/O configuration */ + if (res == FR_OK) { /* Follow succeeded */ + if (!dir) { /* Current dir itself */ + res = FR_INVALID_NAME; + } else { + if (dir[DIR_Attr] & AM_DIR) /* It is a directory */ + res = FR_NO_FILE; + } + } +#endif + FREE_BUF(); + + if (res == FR_OK) { + fp->flag = mode; /* File access mode */ + fp->org_clust = LD_CLUST(dir); /* File start cluster */ + fp->fsize = LD_DWORD(dir+DIR_FileSize); /* File size */ + fp->fptr = 0; /* File pointer */ + fp->dsect = 0; +#if _USE_FASTSEEK + fp->cltbl = 0; /* No cluster link map table */ +#endif + fp->fs = dj.fs; fp->id = dj.fs->id; /* Validate file object */ + } + + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_read ( + FIL *fp, /* Pointer to the file object */ + BYTE *buff, /* Pointer to data buffer */ + UINT btr, /* Number of bytes to read */ + UINT *br /* Pointer to number of bytes read */ +) +{ + FRESULT res; + DWORD clst, sect, remain; + UINT rcnt, cc; + BYTE csect, *rbuff = buff; + + + *br = 0; /* Initialize byte counter */ + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res != FR_OK) LEAVE_FF(fp->fs, res); + if (fp->flag & FA__ERROR) /* Check abort flag */ + LEAVE_FF(fp->fs, FR_INT_ERR); + if (!(fp->flag & FA_READ)) /* Check access mode */ + LEAVE_FF(fp->fs, FR_DENIED); + remain = fp->fsize - fp->fptr; + if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ + + for ( ; btr; /* Repeat until all data transferred */ + rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) { + if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ + csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ + if (!csect) { /* On the cluster boundary? */ + clst = (fp->fptr == 0) ? /* On the top of the file? */ + fp->org_clust : get_fat(fp->fs, fp->curr_clust); + if (clst <= 1) ABORT(fp->fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + fp->curr_clust = clst; /* Update current cluster */ + } + sect = clust2sect(fp->fs, fp->curr_clust); /* Get current sector */ + if (!sect) ABORT(fp->fs, FR_INT_ERR); + sect += csect; + cc = btr / SS(fp->fs); /* When remaining bytes >= sector size, */ + if (cc) { /* Read maximum contiguous sectors directly */ + if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */ + cc = fp->fs->csize - csect; + if (disk_read(fp->fs->drv, rbuff, sect, (BYTE)cc) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); +#if !_FS_READONLY && _FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it contains a dirty sector */ +#if _FS_TINY + if (fp->fs->wflag && fp->fs->winsect - sect < cc) + mem_cpy(rbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), fp->fs->win, SS(fp->fs)); +#else + if ((fp->flag & FA__DIRTY) && fp->dsect - sect < cc) + mem_cpy(rbuff + ((fp->dsect - sect) * SS(fp->fs)), fp->buf, SS(fp->fs)); +#endif +#endif + rcnt = SS(fp->fs) * cc; /* Number of bytes transferred */ + continue; + } +#if !_FS_TINY +#if !_FS_READONLY + if (fp->flag & FA__DIRTY) { /* Write sector I/O buffer if needed */ + if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + if (fp->dsect != sect) { /* Fill sector buffer with file data */ + if (disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); + } +#endif + fp->dsect = sect; + } + rcnt = SS(fp->fs) - (fp->fptr % SS(fp->fs)); /* Get partial sector data from sector buffer */ + if (rcnt > btr) rcnt = btr; +#if _FS_TINY + if (move_window(fp->fs, fp->dsect)) /* Move sector window */ + ABORT(fp->fs, FR_DISK_ERR); + mem_cpy(rbuff, &fp->fs->win[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */ +#else + mem_cpy(rbuff, &fp->buf[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */ +#endif + } + + LEAVE_FF(fp->fs, FR_OK); +} + + + + +#if !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Write File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_write ( + FIL *fp, /* Pointer to the file object */ + const BYTE *buff, /* Pointer to the data to be written */ + UINT btw, /* Number of bytes to write */ + UINT *bw /* Pointer to number of bytes written */ +) +{ + FRESULT res; + DWORD clst, sect; + UINT wcnt, cc; + const BYTE *wbuff = buff; + BYTE csect; + + + *bw = 0; /* Initialize byte counter */ + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res != FR_OK) LEAVE_FF(fp->fs, res); + if (fp->flag & FA__ERROR) /* Check abort flag */ + LEAVE_FF(fp->fs, FR_INT_ERR); + if (!(fp->flag & FA_WRITE)) /* Check access mode */ + LEAVE_FF(fp->fs, FR_DENIED); + if (fp->fsize + btw < fp->fsize) btw = 0; /* File size cannot reach 4GB */ + + for ( ; btw; /* Repeat until all data transferred */ + wbuff += wcnt, fp->fptr += wcnt, *bw += wcnt, btw -= wcnt) { + if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ + csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ + if (!csect) { /* On the cluster boundary? */ + if (fp->fptr == 0) { /* On the top of the file? */ + clst = fp->org_clust; /* Follow from the origin */ + if (clst == 0) /* When there is no cluster chain, */ + fp->org_clust = clst = create_chain(fp->fs, 0); /* Create a new cluster chain */ + } else { /* Middle or end of the file */ + clst = create_chain(fp->fs, fp->curr_clust); /* Follow or stretch cluster chain */ + } + if (clst == 0) break; /* Could not allocate a new cluster (disk full) */ + if (clst == 1) ABORT(fp->fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + fp->curr_clust = clst; /* Update current cluster */ + } +#if _FS_TINY + if (fp->fs->winsect == fp->dsect && move_window(fp->fs, 0)) /* Write back data buffer prior to following direct transfer */ + ABORT(fp->fs, FR_DISK_ERR); +#else + if (fp->flag & FA__DIRTY) { /* Write back data buffer prior to following direct transfer */ + if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + sect = clust2sect(fp->fs, fp->curr_clust); /* Get current sector */ + if (!sect) ABORT(fp->fs, FR_INT_ERR); + sect += csect; + cc = btw / SS(fp->fs); /* When remaining bytes >= sector size, */ + if (cc) { /* Write maximum contiguous sectors directly */ + if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */ + cc = fp->fs->csize - csect; + if (disk_write(fp->fs->drv, wbuff, sect, (BYTE)cc) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); +#if _FS_TINY + if (fp->fs->winsect - sect < cc) { /* Refill sector cache if it gets dirty by the direct write */ + mem_cpy(fp->fs->win, wbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), SS(fp->fs)); + fp->fs->wflag = 0; + } +#else + if (fp->dsect - sect < cc) { /* Refill sector cache if it gets dirty by the direct write */ + mem_cpy(fp->buf, wbuff + ((fp->dsect - sect) * SS(fp->fs)), SS(fp->fs)); + fp->flag &= ~FA__DIRTY; + } +#endif + wcnt = SS(fp->fs) * cc; /* Number of bytes transferred */ + continue; + } +#if _FS_TINY + if (fp->fptr >= fp->fsize) { /* Avoid silly buffer filling at growing edge */ + if (move_window(fp->fs, 0)) ABORT(fp->fs, FR_DISK_ERR); + fp->fs->winsect = sect; + } +#else + if (fp->dsect != sect) { /* Fill sector buffer with file data */ + if (fp->fptr < fp->fsize && + disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); + } +#endif + fp->dsect = sect; + } + wcnt = SS(fp->fs) - (fp->fptr % SS(fp->fs));/* Put partial sector into file I/O buffer */ + if (wcnt > btw) wcnt = btw; +#if _FS_TINY + if (move_window(fp->fs, fp->dsect)) /* Move sector window */ + ABORT(fp->fs, FR_DISK_ERR); + mem_cpy(&fp->fs->win[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */ + fp->fs->wflag = 1; +#else + mem_cpy(&fp->buf[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */ + fp->flag |= FA__DIRTY; +#endif + } + + if (fp->fptr > fp->fsize) fp->fsize = fp->fptr; /* Update file size if needed */ + fp->flag |= FA__WRITTEN; /* Set file change flag */ + + LEAVE_FF(fp->fs, FR_OK); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Synchronize the File Object */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_sync ( + FIL *fp /* Pointer to the file object */ +) +{ + FRESULT res; + DWORD tim; + BYTE *dir; + + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res == FR_OK) { + if (fp->flag & FA__WRITTEN) { /* Has the file been written? */ +#if !_FS_TINY /* Write-back dirty buffer */ + if (fp->flag & FA__DIRTY) { + if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) + LEAVE_FF(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + /* Update the directory entry */ + res = move_window(fp->fs, fp->dir_sect); + if (res == FR_OK) { + dir = fp->dir_ptr; + dir[DIR_Attr] |= AM_ARC; /* Set archive bit */ + ST_DWORD(dir+DIR_FileSize, fp->fsize); /* Update file size */ + ST_CLUST(dir, fp->org_clust); /* Update start cluster */ + tim = o9x_get_fattime(); /* Update updated time */ + ST_DWORD(dir+DIR_WrtTime, tim); + fp->flag &= ~FA__WRITTEN; + fp->fs->wflag = 1; + res = sync(fp->fs); + } + } + } + + LEAVE_FF(fp->fs, res); +} + +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Close File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_close ( + FIL *fp /* Pointer to the file object to be closed */ +) +{ + FRESULT res; + +#if _FS_READONLY + FATFS *fs = fp->fs; + res = validate(fs, fp->id); + if (res == FR_OK) fp->fs = 0; /* Discard file object */ + LEAVE_FF(fs, res); + +#else + res = f_sync(fp); /* Flush cached data */ +#if _FS_SHARE + if (res == FR_OK) { /* Decrement open counter */ +#if _FS_REENTRANT + res = validate(fp->fs, fp->id); + if (res == FR_OK) { + res = dec_lock(fp->lockid); + unlock_fs(fp->fs, FR_OK); + } +#else + res = dec_lock(fp->lockid); +#endif + } +#endif + if (res == FR_OK) fp->fs = 0; /* Discard file object */ + return res; +#endif +} + + + + +/*-----------------------------------------------------------------------*/ +/* Current Drive/Directory Handlings */ +/*-----------------------------------------------------------------------*/ + +#if _FS_RPATH >= 1 + +FRESULT f_chdrive ( + BYTE drv /* Drive number */ +) +{ + if (drv >= _VOLUMES) return FR_INVALID_DRIVE; + + CurrVol = drv; + + return FR_OK; +} + + + +FRESULT f_chdir ( + const TCHAR *path /* Pointer to the directory path */ +) +{ + FRESULT res; + DIR dj; + DEF_NAMEBUF; + + + res = chk_mounted(&path, &dj.fs, 0); + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the path */ + FREE_BUF(); + if (res == FR_OK) { /* Follow completed */ + if (!dj.dir) { + dj.fs->cdir = dj.sclust; /* Start directory itself */ + } else { + if (dj.dir[DIR_Attr] & AM_DIR) /* Reached to the directory */ + dj.fs->cdir = LD_CLUST(dj.dir); + else + res = FR_NO_PATH; /* Reached but a file */ + } + } + if (res == FR_NO_FILE) res = FR_NO_PATH; + } + + LEAVE_FF(dj.fs, res); +} + + +#if _FS_RPATH >= 2 +FRESULT f_getcwd ( + TCHAR *path, /* Pointer to the directory path */ + UINT sz_path /* Size of path */ +) +{ + FRESULT res; + DIR dj; + UINT i, n; + DWORD ccl; + TCHAR *tp; + FILINFO fno; + DEF_NAMEBUF; + + + *path = 0; + res = chk_mounted((const TCHAR**)&path, &dj.fs, 0); /* Get current volume */ + if (res == FR_OK) { + INIT_BUF(dj); + i = sz_path; /* Bottom of buffer (dir stack base) */ + dj.sclust = dj.fs->cdir; /* Start to follow upper dir from current dir */ + while ((ccl = dj.sclust) != 0) { /* Repeat while current dir is a sub-dir */ + res = dir_sdi(&dj, 1); /* Get parent dir */ + if (res != FR_OK) break; + res = dir_read(&dj); + if (res != FR_OK) break; + dj.sclust = LD_CLUST(dj.dir); /* Goto parent dir */ + res = dir_sdi(&dj, 0); + if (res != FR_OK) break; + do { /* Find the entry links to the child dir */ + res = dir_read(&dj); + if (res != FR_OK) break; + if (ccl == LD_CLUST(dj.dir)) break; /* Found the entry */ + res = dir_next(&dj, 0); + } while (res == FR_OK); + if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */ + if (res != FR_OK) break; +#if _USE_LFN + fno.lfname = path; + fno.lfsize = i; +#endif + get_fileinfo(&dj, &fno); /* Get the dir name and push it to the buffer */ + tp = fno.fname; + if (_USE_LFN && *path) tp = path; + for (n = 0; tp[n]; n++) ; + if (i < n + 3) { + res = FR_NOT_ENOUGH_CORE; break; + } + while (n) path[--i] = tp[--n]; + path[--i] = '/'; + } + tp = path; + if (res == FR_OK) { + *tp++ = '0' + CurrVol; /* Put drive number */ + *tp++ = ':'; + if (i == sz_path) { /* Root-dir */ + *tp++ = '/'; + } else { /* Sub-dir */ + do /* Add stacked path str */ + *tp++ = path[i++]; + while (i < sz_path); + } + } + *tp = 0; + FREE_BUF(); + } + + LEAVE_FF(dj.fs, res); +} +#endif /* _FS_RPATH >= 2 */ +#endif /* _FS_RPATH >= 1 */ + + + +#if _FS_MINIMIZE <= 2 +/*-----------------------------------------------------------------------*/ +/* Seek File R/W Pointer */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_lseek ( + FIL *fp, /* Pointer to the file object */ + DWORD ofs /* File pointer from top of file */ +) +{ + FRESULT res; + + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res != FR_OK) LEAVE_FF(fp->fs, res); + if (fp->flag & FA__ERROR) /* Check abort flag */ + LEAVE_FF(fp->fs, FR_INT_ERR); + +#if _USE_FASTSEEK + if (fp->cltbl) { /* Fast seek */ + DWORD cl, pcl, ncl, tcl, dsc, tlen, *tbl = fp->cltbl; + BYTE csc; + + tlen = *tbl++; + if (ofs == CREATE_LINKMAP) { /* Create link map table */ + cl = fp->org_clust; + if (cl) { + do { + if (tlen < 4) { /* Not enough table items */ + res = FR_NOT_ENOUGH_CORE; break; + } + tcl = cl; ncl = 0; + do { /* Get a fragment and store the top and length */ + pcl = cl; ncl++; + cl = get_fat(fp->fs, cl); + if (cl <= 1) ABORT(fp->fs, FR_INT_ERR); + if (cl == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + } while (cl == pcl + 1); + *tbl++ = ncl; *tbl++ = tcl; + tlen -= 2; + } while (cl < fp->fs->n_fatent); + } + *tbl = 0; /* Terminate table */ + + } else { /* Fast seek */ + if (ofs > fp->fsize) /* Clip offset at the file size */ + ofs = fp->fsize; + fp->fptr = ofs; /* Set file pointer */ + if (ofs) { + dsc = (ofs - 1) / SS(fp->fs); + cl = dsc / fp->fs->csize; + for (;;) { + ncl = *tbl++; + if (!ncl) ABORT(fp->fs, FR_INT_ERR); + if (cl < ncl) break; + cl -= ncl; tbl++; + } + fp->curr_clust = cl + *tbl; + csc = (BYTE)(dsc & (fp->fs->csize - 1)); + dsc = clust2sect(fp->fs, fp->curr_clust); + if (!dsc) ABORT(fp->fs, FR_INT_ERR); + dsc += csc; + if (fp->fptr % SS(fp->fs) && dsc != fp->dsect) { +#if !_FS_TINY +#if !_FS_READONLY + if (fp->flag & FA__DIRTY) { /* Flush dirty buffer if needed */ + if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + if (disk_read(fp->fs->drv, fp->buf, dsc, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); +#endif + fp->dsect = dsc; + } + } + } + } else +#endif + + /* Normal Seek */ + { + DWORD clst, bcs, nsect, ifptr; + + if (ofs > fp->fsize /* In read-only mode, clip offset with the file size */ +#if !_FS_READONLY + && !(fp->flag & FA_WRITE) +#endif + ) ofs = fp->fsize; + + ifptr = fp->fptr; + fp->fptr = nsect = 0; + if (ofs) { + bcs = (DWORD)fp->fs->csize * SS(fp->fs); /* Cluster size (byte) */ + if (ifptr > 0 && + (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */ + fp->fptr = (ifptr - 1) & ~(bcs - 1); /* start from the current cluster */ + ofs -= fp->fptr; + clst = fp->curr_clust; + } else { /* When seek to back cluster, */ + clst = fp->org_clust; /* start from the first cluster */ +#if !_FS_READONLY + if (clst == 0) { /* If no cluster chain, create a new chain */ + clst = create_chain(fp->fs, 0); + if (clst == 1) ABORT(fp->fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + fp->org_clust = clst; + } +#endif + fp->curr_clust = clst; + } + if (clst != 0) { + while (ofs > bcs) { /* Cluster following loop */ +#if !_FS_READONLY + if (fp->flag & FA_WRITE) { /* Check if in write mode or not */ + clst = create_chain(fp->fs, clst); /* Force stretch if in write mode */ + if (clst == 0) { /* When disk gets full, clip file size */ + ofs = bcs; break; + } + } else +#endif + clst = get_fat(fp->fs, clst); /* Follow cluster chain if not in write mode */ + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + if (clst <= 1 || clst >= fp->fs->n_fatent) ABORT(fp->fs, FR_INT_ERR); + fp->curr_clust = clst; + fp->fptr += bcs; + ofs -= bcs; + } + fp->fptr += ofs; + if (ofs % SS(fp->fs)) { + nsect = clust2sect(fp->fs, clst); /* Current sector */ + if (!nsect) ABORT(fp->fs, FR_INT_ERR); + nsect += ofs / SS(fp->fs); + } + } + } + if (fp->fptr % SS(fp->fs) && nsect != fp->dsect) { +#if !_FS_TINY +#if !_FS_READONLY + if (fp->flag & FA__DIRTY) { /* Flush dirty buffer if needed */ + if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + if (disk_read(fp->fs->drv, fp->buf, nsect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); +#endif + fp->dsect = nsect; + } +#if !_FS_READONLY + if (fp->fptr > fp->fsize) { /* Set change flag if the file size is extended */ + fp->fsize = fp->fptr; + fp->flag |= FA__WRITTEN; + } +#endif + } + + LEAVE_FF(fp->fs, res); +} + + + +#if _FS_MINIMIZE <= 1 +/*-----------------------------------------------------------------------*/ +/* Create a Directroy Object */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_opendir ( + DIR *dj, /* Pointer to directory object to create */ + const TCHAR *path /* Pointer to the directory path */ +) +{ + FRESULT res; + DEF_NAMEBUF; + + + res = chk_mounted(&path, &dj->fs, 0); + if (res == FR_OK) { + INIT_BUF(*dj); + res = follow_path(dj, path); /* Follow the path to the directory */ + FREE_BUF(); + if (res == FR_OK) { /* Follow completed */ + if (dj->dir) { /* It is not the root dir */ + if (dj->dir[DIR_Attr] & AM_DIR) { /* The object is a directory */ + dj->sclust = LD_CLUST(dj->dir); + } else { /* The object is not a directory */ + res = FR_NO_PATH; + } + } + if (res == FR_OK) { + dj->id = dj->fs->id; + res = dir_sdi(dj, 0); /* Rewind dir */ + } + } + if (res == FR_NO_FILE) res = FR_NO_PATH; + } + + LEAVE_FF(dj->fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read Directory Entry in Sequense */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_readdir ( + DIR *dj, /* Pointer to the open directory object */ + FILINFO *fno /* Pointer to file information to return */ +) +{ + FRESULT res; + DEF_NAMEBUF; + + + res = validate(dj->fs, dj->id); /* Check validity of the object */ + if (res == FR_OK) { + if (!fno) { + res = dir_sdi(dj, 0); /* Rewind the directory object */ + } else { + INIT_BUF(*dj); + res = dir_read(dj); /* Read an directory item */ + if (res == FR_NO_FILE) { /* Reached end of dir */ + dj->sect = 0; + res = FR_OK; + } + if (res == FR_OK) { /* A valid entry is found */ + get_fileinfo(dj, fno); /* Get the object information */ + res = dir_next(dj, 0); /* Increment index for next */ + if (res == FR_NO_FILE) { + dj->sect = 0; + res = FR_OK; + } + } + FREE_BUF(); + } + } + + LEAVE_FF(dj->fs, res); +} + + + +#if _FS_MINIMIZE == 0 +/*-----------------------------------------------------------------------*/ +/* Get File Status */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_stat ( + const TCHAR *path, /* Pointer to the file path */ + FILINFO *fno /* Pointer to file information to return */ +) +{ + FRESULT res; + DIR dj; + DEF_NAMEBUF; + + + res = chk_mounted(&path, &dj.fs, 0); + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK) { /* Follow completed */ + if (dj.dir) /* Found an object */ + get_fileinfo(&dj, fno); + else /* It is root dir */ + res = FR_INVALID_NAME; + } + FREE_BUF(); + } + + LEAVE_FF(dj.fs, res); +} + + + +#if !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Get Number of Free Clusters */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_getfree ( + const TCHAR *path, /* Pointer to the logical drive number (root dir) */ + DWORD *nclst, /* Pointer to the variable to return number of free clusters */ + FATFS **fatfs /* Pointer to pointer to corresponding file system object to return */ +) +{ + FRESULT res; + DWORD n, clst, sect, stat; + UINT i; + BYTE fat, *p; + + + /* Get drive number */ + res = chk_mounted(&path, fatfs, 0); + if (res == FR_OK) { + /* If free_clust is valid, return it without full cluster scan */ + if ((*fatfs)->free_clust <= (*fatfs)->n_fatent - 2) { + *nclst = (*fatfs)->free_clust; + } else { + /* Get number of free clusters */ + fat = (*fatfs)->fs_type; + n = 0; + if (fat == FS_FAT12) { + clst = 2; + do { + stat = get_fat(*fatfs, clst); + if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } + if (stat == 1) { res = FR_INT_ERR; break; } + if (stat == 0) n++; + } while (++clst < (*fatfs)->n_fatent); + } else { + clst = (*fatfs)->n_fatent; + sect = (*fatfs)->fatbase; + i = 0; p = 0; + do { + if (!i) { + res = move_window(*fatfs, sect++); + if (res != FR_OK) break; + p = (*fatfs)->win; + i = SS(*fatfs); + } + if (fat == FS_FAT16) { + if (LD_WORD(p) == 0) n++; + p += 2; i -= 2; + } else { + if ((LD_DWORD(p) & 0x0FFFFFFF) == 0) n++; + p += 4; i -= 4; + } + } while (--clst); + } + (*fatfs)->free_clust = n; + if (fat == FS_FAT32) (*fatfs)->fsi_flag = 1; + *nclst = n; + } + } + LEAVE_FF(*fatfs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Truncate File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_truncate ( + FIL *fp /* Pointer to the file object */ +) +{ + FRESULT res; + DWORD ncl; + + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res == FR_OK) { + if (fp->flag & FA__ERROR) { /* Check abort flag */ + res = FR_INT_ERR; + } else { + if (!(fp->flag & FA_WRITE)) /* Check access mode */ + res = FR_DENIED; + } + } + if (res == FR_OK) { + if (fp->fsize > fp->fptr) { + fp->fsize = fp->fptr; /* Set file size to current R/W point */ + fp->flag |= FA__WRITTEN; + if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */ + res = remove_chain(fp->fs, fp->org_clust); + fp->org_clust = 0; + } else { /* When truncate a part of the file, remove remaining clusters */ + ncl = get_fat(fp->fs, fp->curr_clust); + res = FR_OK; + if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR; + if (ncl == 1) res = FR_INT_ERR; + if (res == FR_OK && ncl < fp->fs->n_fatent) { + res = put_fat(fp->fs, fp->curr_clust, 0x0FFFFFFF); + if (res == FR_OK) res = remove_chain(fp->fs, ncl); + } + } + } + if (res != FR_OK) fp->flag |= FA__ERROR; + } + + LEAVE_FF(fp->fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Delete a File or Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_unlink ( + const TCHAR *path /* Pointer to the file or directory path */ +) +{ + FRESULT res; + DIR dj, sdj; + BYTE *dir; + DWORD dclst; + DEF_NAMEBUF; + + + res = chk_mounted(&path, &dj.fs, 1); + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the file path */ + if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; /* Cannot remove dot entry */ +#if _FS_SHARE + if (res == FR_OK) res = chk_lock(&dj, 2); /* Cannot remove open file */ +#endif + if (res == FR_OK) { /* The object is accessible */ + dir = dj.dir; + if (!dir) { + res = FR_INVALID_NAME; /* Cannot remove the start directory */ + } else { + if (dir[DIR_Attr] & AM_RDO) + res = FR_DENIED; /* Cannot remove R/O object */ + } + dclst = LD_CLUST(dir); + if (res == FR_OK && (dir[DIR_Attr] & AM_DIR)) { /* Is it a sub-dir? */ + if (dclst < 2) { + res = FR_INT_ERR; + } else { + mem_cpy(&sdj, &dj, sizeof(DIR)); /* Check if the sub-dir is empty or not */ + sdj.sclust = dclst; + res = dir_sdi(&sdj, 2); /* Exclude dot entries */ + if (res == FR_OK) { + res = dir_read(&sdj); + if (res == FR_OK /* Not empty dir */ +#if _FS_RPATH + || dclst == sdj.fs->cdir /* Current dir */ +#endif + ) res = FR_DENIED; + if (res == FR_NO_FILE) res = FR_OK; /* Empty */ + } + } + } + if (res == FR_OK) { + res = dir_remove(&dj); /* Remove the directory entry */ + if (res == FR_OK) { + if (dclst) /* Remove the cluster chain if exist */ + res = remove_chain(dj.fs, dclst); + if (res == FR_OK) res = sync(dj.fs); + } + } + } + FREE_BUF(); + } + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Create a Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_mkdir ( + const TCHAR *path /* Pointer to the directory path */ +) +{ + FRESULT res; + DIR dj; + BYTE *dir, n; + DWORD dsc, dcl, pcl, tim = o9x_get_fattime(); + DEF_NAMEBUF; + + + res = chk_mounted(&path, &dj.fs, 1); + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK) res = FR_EXIST; /* Any object with same name is already existing */ + if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; + if (res == FR_NO_FILE) { /* Can create a new directory */ + dcl = create_chain(dj.fs, 0); /* Allocate a cluster for the new directory table */ + res = FR_OK; + if (dcl == 0) res = FR_DENIED; /* No space to allocate a new cluster */ + if (dcl == 1) res = FR_INT_ERR; + if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR; + if (res == FR_OK) /* Flush FAT */ + res = move_window(dj.fs, 0); + if (res == FR_OK) { /* Initialize the new directory table */ + dsc = clust2sect(dj.fs, dcl); + dir = dj.fs->win; + mem_set(dir, 0, SS(dj.fs)); + mem_set(dir+DIR_Name, ' ', 8+3); /* Create "." entry */ + dir[DIR_Name] = '.'; + dir[DIR_Attr] = AM_DIR; + ST_DWORD(dir+DIR_WrtTime, tim); + ST_CLUST(dir, dcl); + mem_cpy(dir+32, dir, 32); /* Create ".." entry */ + dir[33] = '.'; pcl = dj.sclust; + if (dj.fs->fs_type == FS_FAT32 && pcl == dj.fs->dirbase) + pcl = 0; + ST_CLUST(dir+32, pcl); + for (n = dj.fs->csize; n; n--) { /* Write dot entries and clear following sectors */ + dj.fs->winsect = dsc++; + dj.fs->wflag = 1; + res = move_window(dj.fs, 0); + if (res != FR_OK) break; + mem_set(dir, 0, SS(dj.fs)); + } + } + if (res == FR_OK) res = dir_register(&dj); /* Register the object to the directoy */ + if (res != FR_OK) { + remove_chain(dj.fs, dcl); /* Could not register, remove cluster chain */ + } else { + dir = dj.dir; + dir[DIR_Attr] = AM_DIR; /* Attribute */ + ST_DWORD(dir+DIR_WrtTime, tim); /* Created time */ + ST_CLUST(dir, dcl); /* Table start cluster */ + dj.fs->wflag = 1; + res = sync(dj.fs); + } + } + FREE_BUF(); + } + + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Change Attribute */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_chmod ( + const TCHAR *path, /* Pointer to the file path */ + BYTE value, /* Attribute bits */ + BYTE mask /* Attribute mask to change */ +) +{ + FRESULT res; + DIR dj; + BYTE *dir; + DEF_NAMEBUF; + + + res = chk_mounted(&path, &dj.fs, 1); + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the file path */ + FREE_BUF(); + if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; + if (res == FR_OK) { + dir = dj.dir; + if (!dir) { /* Is it a root directory? */ + res = FR_INVALID_NAME; + } else { /* File or sub directory */ + mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC; /* Valid attribute mask */ + dir[DIR_Attr] = (value & mask) | (dir[DIR_Attr] & (BYTE)~mask); /* Apply attribute change */ + dj.fs->wflag = 1; + res = sync(dj.fs); + } + } + } + + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Change Timestamp */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_utime ( + const TCHAR *path, /* Pointer to the file/directory name */ + const FILINFO *fno /* Pointer to the time stamp to be set */ +) +{ + FRESULT res; + DIR dj; + BYTE *dir; + DEF_NAMEBUF; + + + res = chk_mounted(&path, &dj.fs, 1); + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the file path */ + FREE_BUF(); + if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; + if (res == FR_OK) { + dir = dj.dir; + if (!dir) { /* Root directory */ + res = FR_INVALID_NAME; + } else { /* File or sub-directory */ + ST_WORD(dir+DIR_WrtTime, fno->ftime); + ST_WORD(dir+DIR_WrtDate, fno->fdate); + dj.fs->wflag = 1; + res = sync(dj.fs); + } + } + } + + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Rename File/Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_rename ( + const TCHAR *path_old, /* Pointer to the old name */ + const TCHAR *path_new /* Pointer to the new name */ +) +{ + FRESULT res; + DIR djo, djn; + BYTE buf[21], *dir; + DWORD dw; + DEF_NAMEBUF; + + + res = chk_mounted(&path_old, &djo.fs, 1); + if (res == FR_OK) { + djn.fs = djo.fs; + INIT_BUF(djo); + res = follow_path(&djo, path_old); /* Check old object */ + if (_FS_RPATH && res == FR_OK && (djo.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; +#if _FS_SHARE + if (res == FR_OK) res = chk_lock(&djo, 2); +#endif + if (res == FR_OK) { /* Old object is found */ + if (!djo.dir) { /* Is root dir? */ + res = FR_NO_FILE; + } else { + mem_cpy(buf, djo.dir+DIR_Attr, 21); /* Save the object information except for name */ + mem_cpy(&djn, &djo, sizeof(DIR)); /* Check new object */ + res = follow_path(&djn, path_new); + if (res == FR_OK) res = FR_EXIST; /* The new object name is already existing */ + if (res == FR_NO_FILE) { /* Is it a valid path and no name collision? */ +/* Start critical section that any interruption or error can cause cross-link */ + res = dir_register(&djn); /* Register the new entry */ + if (res == FR_OK) { + dir = djn.dir; /* Copy object information except for name */ + mem_cpy(dir+13, buf+2, 19); + dir[DIR_Attr] = buf[0] | AM_ARC; + djo.fs->wflag = 1; + if (djo.sclust != djn.sclust && (dir[DIR_Attr] & AM_DIR)) { /* Update .. entry in the directory if needed */ + dw = clust2sect(djn.fs, LD_CLUST(dir)); + if (!dw) { + res = FR_INT_ERR; + } else { + res = move_window(djn.fs, dw); + dir = djn.fs->win+32; /* .. entry */ + if (res == FR_OK && dir[1] == '.') { + dw = (djn.fs->fs_type == FS_FAT32 && djn.sclust == djn.fs->dirbase) ? 0 : djn.sclust; + ST_CLUST(dir, dw); + djn.fs->wflag = 1; + } + } + } + if (res == FR_OK) { + res = dir_remove(&djo); /* Remove old entry */ + if (res == FR_OK) + res = sync(djo.fs); + } + } +/* End critical section */ + } + } + } + FREE_BUF(); + } + LEAVE_FF(djo.fs, res); +} + +#endif /* !_FS_READONLY */ +#endif /* _FS_MINIMIZE == 0 */ +#endif /* _FS_MINIMIZE <= 1 */ +#endif /* _FS_MINIMIZE <= 2 */ + + + +/*-----------------------------------------------------------------------*/ +/* Forward data to the stream directly (available on only tiny cfg) */ +/*-----------------------------------------------------------------------*/ +#if _USE_FORWARD && _FS_TINY + +FRESULT f_forward ( + FIL *fp, /* Pointer to the file object */ + UINT (*func)(const BYTE*,UINT), /* Pointer to the streaming function */ + UINT btr, /* Number of bytes to forward */ + UINT *bf /* Pointer to number of bytes forwarded */ +) +{ + FRESULT res; + DWORD remain, clst, sect; + UINT rcnt; + BYTE csect; + + + *bf = 0; /* Initialize byte counter */ + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res != FR_OK) LEAVE_FF(fp->fs, res); + if (fp->flag & FA__ERROR) /* Check error flag */ + LEAVE_FF(fp->fs, FR_INT_ERR); + if (!(fp->flag & FA_READ)) /* Check access mode */ + LEAVE_FF(fp->fs, FR_DENIED); + + remain = fp->fsize - fp->fptr; + if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ + + for ( ; btr && (*func)(0, 0); /* Repeat until all data transferred or stream becomes busy */ + fp->fptr += rcnt, *bf += rcnt, btr -= rcnt) { + csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ + if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ + if (!csect) { /* On the cluster boundary? */ + clst = (fp->fptr == 0) ? /* On the top of the file? */ + fp->org_clust : get_fat(fp->fs, fp->curr_clust); + if (clst <= 1) ABORT(fp->fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + fp->curr_clust = clst; /* Update current cluster */ + } + } + sect = clust2sect(fp->fs, fp->curr_clust); /* Get current data sector */ + if (!sect) ABORT(fp->fs, FR_INT_ERR); + sect += csect; + if (move_window(fp->fs, sect)) /* Move sector window */ + ABORT(fp->fs, FR_DISK_ERR); + fp->dsect = sect; + rcnt = SS(fp->fs) - (WORD)(fp->fptr % SS(fp->fs)); /* Forward data from sector window */ + if (rcnt > btr) rcnt = btr; + rcnt = (*func)(&fp->fs->win[(WORD)fp->fptr % SS(fp->fs)], rcnt); + if (!rcnt) ABORT(fp->fs, FR_INT_ERR); + } + + LEAVE_FF(fp->fs, FR_OK); +} +#endif /* _USE_FORWARD */ + + + +#if _USE_MKFS && !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Create File System on the Drive */ +/*-----------------------------------------------------------------------*/ +#define N_ROOTDIR 512 /* Multiple of 32 */ +#define N_FATS 1 /* 1 or 2 */ + + +FRESULT f_mkfs ( + BYTE drv, /* Logical drive number */ + BYTE sfd, /* Partitioning rule 0:FDISK, 1:SFD */ + UINT au /* Allocation unit size [bytes] */ +) +{ + static const WORD vst[] = { 1024, 512, 256, 128, 64, 32, 16, 8, 4, 2, 0}; + static const WORD cst[] = {32768, 16384, 8192, 4096, 2048, 16384, 8192, 4096, 2048, 1024, 512}; + BYTE fmt, md, *tbl; + DWORD n_clst, vs, n, wsect; + UINT i; + DWORD b_vol, b_fat, b_dir, b_data; /* Offset (LBA) */ + DWORD n_vol, n_rsv, n_fat, n_dir; /* Size */ + FATFS *fs; + DSTATUS stat; + + + /* Check mounted drive and clear work area */ + if (drv >= _VOLUMES) return FR_INVALID_DRIVE; + fs = FatFs[drv]; + if (!fs) return FR_NOT_ENABLED; + fs->fs_type = 0; + drv = LD2PD(drv); + + /* Get disk statics */ + stat = disk_initialize(drv); + if (stat & STA_NOINIT) return FR_NOT_READY; + if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; +#if _MAX_SS != 512 /* Get disk sector size */ + if (disk_ioctl(drv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK) + return FR_DISK_ERR; +#endif + if (disk_ioctl(drv, GET_SECTOR_COUNT, (BYTE*)&n_vol) != RES_OK || n_vol < 128) + return FR_DISK_ERR; + b_vol = (sfd) ? 0 : 63; /* Volume start sector */ + n_vol -= b_vol; + if (au & (au - 1)) au = 0; /* Check validity of the allocation unit size */ + if (!au) { /* AU auto selection */ + vs = n_vol / (2000 / (SS(fs) / 512)); + for (i = 0; vs < vst[i]; i++) ; + au = cst[i]; + } + au /= SS(fs); /* Number of sectors per cluster */ + if (au == 0) au = 1; + if (au > 128) au = 128; + + /* Pre-compute number of clusters and FAT syb-type */ + n_clst = n_vol / au; + fmt = FS_FAT12; + if (n_clst >= MIN_FAT16) fmt = FS_FAT16; + if (n_clst >= MIN_FAT32) fmt = FS_FAT32; + + /* Determine offset and size of FAT structure */ + if (fmt == FS_FAT32) { + n_fat = ((n_clst * 4) + 8 + SS(fs) - 1) / SS(fs); + n_rsv = 32; + n_dir = 0; + } else { + n_fat = (fmt == FS_FAT12) ? (n_clst * 3 + 1) / 2 + 3 : (n_clst * 2) + 4; + n_fat = (n_fat + SS(fs) - 1) / SS(fs); + n_rsv = 1; + n_dir = N_ROOTDIR * 32UL / SS(fs); + } + b_fat = b_vol + n_rsv; /* FAT area start sector */ + b_dir = b_fat + n_fat * N_FATS; /* Directory area start sector */ + b_data = b_dir + n_dir; /* Data area start sector */ + if (n_vol < b_data + au) return FR_MKFS_ABORTED; /* Too small volume */ + + /* Align data start sector to erase block boundary (for flash memory media) */ + if (disk_ioctl(drv, GET_BLOCK_SIZE, (BYTE*)&n) != RES_OK || !n || n > 32768) n = 1; + n = (b_data + n - 1) & ~(n - 1); /* Next nearest erase block from current data start */ + n = (n - b_data) / N_FATS; + if (fmt == FS_FAT32) { /* FAT32: Move FAT offset */ + n_rsv += n; + b_fat += n; + } else { /* FAT12/16: Expand FAT size */ + n_fat += n; + } + + /* Determine number of cluster and final check of validity of the FAT sub-type */ + n_clst = (n_vol - n_rsv - n_fat * N_FATS - n_dir) / au; + if ( (fmt == FS_FAT16 && n_clst < MIN_FAT16) + || (fmt == FS_FAT32 && n_clst < MIN_FAT32)) + return FR_MKFS_ABORTED; + + /* Create partition table if required */ + if (sfd) { + md = 0xF0; + } else { + DWORD n_disk = b_vol + n_vol; + + mem_set(fs->win, 0, SS(fs)); + tbl = fs->win+MBR_Table; + ST_DWORD(tbl, 0x00010180); /* Partition start in CHS */ + if (n_disk < 63UL * 255 * 1024) { /* Partition end in CHS */ + n_disk = n_disk / 63 / 255; + tbl[7] = (BYTE)n_disk; + tbl[6] = (BYTE)((n_disk >> 2) | 63); + } else { + ST_WORD(&tbl[6], 0xFFFF); + } + tbl[5] = 254; + if (fmt != FS_FAT32) /* System ID */ + tbl[4] = (n_vol < 0x10000) ? 0x04 : 0x06; + else + tbl[4] = 0x0c; + ST_DWORD(tbl+8, 63); /* Partition start in LBA */ + ST_DWORD(tbl+12, n_vol); /* Partition size in LBA */ + ST_WORD(tbl+64, 0xAA55); /* Signature */ + if (disk_write(drv, fs->win, 0, 1) != RES_OK) + return FR_DISK_ERR; + md = 0xF8; + } + + /* Create volume boot record */ + tbl = fs->win; /* Clear sector */ + mem_set(tbl, 0, SS(fs)); + mem_cpy(tbl, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot code, OEM name */ + i = SS(fs); /* Sector size */ + ST_WORD(tbl+BPB_BytsPerSec, i); + tbl[BPB_SecPerClus] = (BYTE)au; /* Sectors per cluster */ + ST_WORD(tbl+BPB_RsvdSecCnt, n_rsv); /* Reserved sectors */ + tbl[BPB_NumFATs] = N_FATS; /* Number of FATs */ + i = (fmt == FS_FAT32) ? 0 : N_ROOTDIR; /* Number of rootdir entries */ + ST_WORD(tbl+BPB_RootEntCnt, i); + if (n_vol < 0x10000) { /* Number of total sectors */ + ST_WORD(tbl+BPB_TotSec16, n_vol); + } else { + ST_DWORD(tbl+BPB_TotSec32, n_vol); + } + tbl[BPB_Media] = md; /* Media descriptor */ + ST_WORD(tbl+BPB_SecPerTrk, 63); /* Number of sectors per track */ + ST_WORD(tbl+BPB_NumHeads, 255); /* Number of heads */ + ST_DWORD(tbl+BPB_HiddSec, b_vol); /* Hidden sectors */ + n = o9x_get_fattime(); /* Use current time as VSN */ + if (fmt == FS_FAT32) { + ST_DWORD(tbl+BS_VolID32, n); /* VSN */ + ST_DWORD(tbl+BPB_FATSz32, n_fat); /* Number of sectors per FAT */ + ST_DWORD(tbl+BPB_RootClus, 2); /* Root directory start cluster (2) */ + ST_WORD(tbl+BPB_FSInfo, 1); /* FSInfo record offset (VBR+1) */ + ST_WORD(tbl+BPB_BkBootSec, 6); /* Backup boot record offset (VBR+6) */ + tbl[BS_DrvNum32] = 0x80; /* Drive number */ + tbl[BS_BootSig32] = 0x29; /* Extended boot signature */ + mem_cpy(tbl+BS_VolLab32, "NO NAME " "FAT32 ", 19); /* Volume label, FAT signature */ + } else { + ST_DWORD(tbl+BS_VolID, n); /* VSN */ + ST_WORD(tbl+BPB_FATSz16, n_fat); /* Number of sectors per FAT */ + tbl[BS_DrvNum] = 0x80; /* Drive number */ + tbl[BS_BootSig] = 0x29; /* Extended boot signature */ + mem_cpy(tbl+BS_VolLab, "NO NAME " "FAT ", 19); /* Volume label, FAT signature */ + } + ST_WORD(tbl+BS_55AA, 0xAA55); /* Signature (Offset is fixed here regardless of sector size) */ + if (disk_write(drv, tbl, b_vol, 1) != RES_OK)/* Write original (VBR) */ + return FR_DISK_ERR; + if (fmt == FS_FAT32) /* Write backup (VBR+6) */ + disk_write(drv, tbl, b_vol + 6, 1); + + /* Initialize FAT area */ + wsect = b_fat; + for (i = 0; i < N_FATS; i++) { + mem_set(tbl, 0, SS(fs)); /* 1st sector of the FAT */ + n = md; /* Media descriptor byte */ + if (fmt != FS_FAT32) { + n |= (fmt == FS_FAT12) ? 0x00FFFF00 : 0xFFFFFF00; + ST_DWORD(tbl+0, n); /* Reserve cluster #0-1 (FAT12/16) */ + } else { + n |= 0xFFFFFF00; + ST_DWORD(tbl+0, n); /* Reserve cluster #0-1 (FAT32) */ + ST_DWORD(tbl+4, 0xFFFFFFFF); + ST_DWORD(tbl+8, 0x0FFFFFFF); /* Reserve cluster #2 for root dir */ + } + if (disk_write(drv, tbl, wsect++, 1) != RES_OK) + return FR_DISK_ERR; + mem_set(tbl, 0, SS(fs)); /* Fill following FAT entries with zero */ + for (n = 1; n < n_fat; n++) { /* This loop may take a time on FAT32 volume due to many single sector write */ + if (disk_write(drv, tbl, wsect++, 1) != RES_OK) + return FR_DISK_ERR; + } + } + + /* Initialize root directory */ + i = (fmt == FS_FAT32) ? au : n_dir; + do { + if (disk_write(drv, tbl, wsect++, 1) != RES_OK) + return FR_DISK_ERR; + } while (--i); + +#if _USE_ERASE /* Erase data area if needed */ + { + DWORD eb[2]; + + eb[0] = wsect; eb[1] = wsect + n_clst * au - 1; + disk_ioctl(drv, CTRL_ERASE_SECTOR, eb); + } +#endif + + /* Create FSInfo if needed */ + if (fmt == FS_FAT32) { + ST_WORD(tbl+BS_55AA, 0xAA55); + ST_DWORD(tbl+FSI_LeadSig, 0x41615252); + ST_DWORD(tbl+FSI_StrucSig, 0x61417272); + ST_DWORD(tbl+FSI_Free_Count, n_clst - 1); + ST_DWORD(tbl+FSI_Nxt_Free, 0xFFFFFFFF); + disk_write(drv, tbl, b_vol + 1, 1); /* Write original (VBR+1) */ + disk_write(drv, tbl, b_vol + 7, 1); /* Write backup (VBR+7) */ + } + + return (disk_ioctl(drv, CTRL_SYNC, (BYTE*)0) == RES_OK) ? FR_OK : FR_DISK_ERR; +} + +#endif /* _USE_MKFS && !_FS_READONLY */ + +#if _USE_LFN == 3 /* LFN with a working buffer on the heap */ +/*------------------------------------------------------------------------*/ +/* Allocate a memory block */ +/*------------------------------------------------------------------------*/ +/* If a NULL is returned, the file function fails with FR_NOT_ENOUGH_CORE. + */ + +void* ff_memalloc ( /* Returns pointer to the allocated memory block */ + UINT size /* Number of bytes to allocate */ + ) +{ + return malloc(size); +} + + +/*------------------------------------------------------------------------*/ +/* Free a memory block */ +/*------------------------------------------------------------------------*/ + +void ff_memfree( + void* mblock /* Pointer to the memory block to free */ + ) +{ + free(mblock); +} + +#endif + + + + +#if _USE_STRFUNC +/*-----------------------------------------------------------------------*/ +/* Get a string from the file */ +/*-----------------------------------------------------------------------*/ +TCHAR* f_gets ( + TCHAR* buff, /* Pointer to the string buffer to read */ + int len, /* Size of string buffer (characters) */ + FIL* fil /* Pointer to the file object */ +) +{ + int n = 0; + TCHAR c, *p = buff; + BYTE s[2]; + UINT rc; + + + while (n < len - 1) { /* Read bytes until buffer gets filled */ + f_read(fil, s, 1, &rc); + if (rc != 1) break; /* Break on EOF or error */ + c = s[0]; +#if _LFN_UNICODE /* Read a character in UTF-8 encoding */ + if (c >= 0x80) { + if (c < 0xC0) continue; /* Skip stray trailer */ + if (c < 0xE0) { /* Two-byte sequense */ + f_read(fil, s, 1, &rc); + if (rc != 1) break; + c = ((c & 0x1F) << 6) | (s[0] & 0x3F); + if (c < 0x80) c = '?'; + } else { + if (c < 0xF0) { /* Three-byte sequense */ + f_read(fil, s, 2, &rc); + if (rc != 2) break; + c = (c << 12) | ((s[0] & 0x3F) << 6) | (s[1] & 0x3F); + if (c < 0x800) c = '?'; + } else { /* Reject four-byte sequense */ + c = '?'; + } + } + } +#endif +#if _USE_STRFUNC >= 2 + if (c == '\r') continue; /* Strip '\r' */ +#endif + *p++ = c; + n++; + if (c == '\n') break; /* Break on EOL */ + } + *p = 0; + return n ? buff : 0; /* When no data read (eof or error), return with error. */ +} + + + +#if !_FS_READONLY +#include +/*-----------------------------------------------------------------------*/ +/* Put a character to the file */ +/*-----------------------------------------------------------------------*/ +int f_putc ( + TCHAR c, /* A character to be output */ + FIL* fil /* Pointer to the file object */ +) +{ + UINT bw, btw; + BYTE s[3]; + + +#if _USE_STRFUNC >= 2 + if (c == '\n') f_putc ('\r', fil); /* LF -> CRLF conversion */ +#endif + +#if _LFN_UNICODE /* Write the character in UTF-8 encoding */ + if (c < 0x80) { /* 7-bit */ + s[0] = (BYTE)c; + btw = 1; + } else { + if (c < 0x800) { /* 11-bit */ + s[0] = (BYTE)(0xC0 | (c >> 6)); + s[1] = (BYTE)(0x80 | (c & 0x3F)); + btw = 2; + } else { /* 16-bit */ + s[0] = (BYTE)(0xE0 | (c >> 12)); + s[1] = (BYTE)(0x80 | ((c >> 6) & 0x3F)); + s[2] = (BYTE)(0x80 | (c & 0x3F)); + btw = 3; + } + } +#else /* Write the character without conversion */ + s[0] = (BYTE)c; + btw = 1; +#endif + f_write(fil, s, btw, &bw); /* Write the char to the file */ + return (bw == btw) ? 1 : EOF; /* Return the result */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* Put a string to the file */ +/*-----------------------------------------------------------------------*/ +int f_puts ( + const TCHAR* str, /* Pointer to the string to be output */ + FIL* fil /* Pointer to the file object */ +) +{ + int n; + + + for (n = 0; *str; str++, n++) { + if (f_putc(*str, fil) == EOF) return EOF; + } + return n; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Put a formatted string to the file */ +/*-----------------------------------------------------------------------*/ +int f_printf ( + FIL* fil, /* Pointer to the file object */ + const TCHAR* str, /* Pointer to the format string */ + ... /* Optional arguments... */ +) +{ + va_list arp; + BYTE f, r; + UINT i, w; + ULONG val; + TCHAR c, d, s[16]; + int res, cc; + + + va_start(arp, str); + + for (cc = res = 0; cc != EOF; res += cc) { + c = *str++; + if (c == 0) break; /* End of string */ + if (c != '%') { /* Non escape character */ + cc = f_putc(c, fil); + if (cc != EOF) cc = 1; + continue; + } + w = f = 0; + c = *str++; + if (c == '0') { /* Flag: '0' padding */ + f = 1; c = *str++; + } + while (IsDigit(c)) { /* Precision */ + w = w * 10 + c - '0'; + c = *str++; + } + if (c == 'l' || c == 'L') { /* Prefix: Size is long int */ + f |= 2; c = *str++; + } + if (!c) break; + d = c; + if (IsLower(d)) d -= 0x20; + switch (d) { /* Type is... */ + case 'S' : /* String */ + cc = f_puts(va_arg(arp, TCHAR*), fil); continue; + case 'C' : /* Character */ + cc = f_putc((TCHAR)va_arg(arp, int), fil); continue; + case 'B' : /* Binary */ + r = 2; break; + case 'O' : /* Octal */ + r = 8; break; + case 'D' : /* Signed decimal */ + case 'U' : /* Unsigned decimal */ + r = 10; break; + case 'X' : /* Hexdecimal */ + r = 16; break; + default: /* Unknown */ + cc = f_putc(c, fil); continue; + } + + /* Get an argument */ + val = (f & 2) ? va_arg(arp, long) : ((d == 'D') ? (long)va_arg(arp, int) : va_arg(arp, unsigned int)); + if (d == 'D' && (val & 0x80000000)) { + val = 0 - val; + f |= 4; + } + /* Put it in numeral string */ + i = 0; + do { + d = (TCHAR)(val % r); val /= r; + if (d > 9) { + d += 7; + if (c == 'x') d += 0x20; + } + s[i++] = d + '0'; + } while (val && i < sizeof(s) / sizeof(s[0])); + if (f & 4) s[i++] = '-'; + cc = 0; + while (i < w-- && cc != EOF) { + cc = f_putc((TCHAR)((f & 1) ? '0' : ' '), fil); + res++; + } + do { + cc = f_putc(s[--i], fil); + res++; + } while (i && cc != EOF); + if (cc != EOF) cc = 0; + } + + va_end(arp); + return (cc == EOF) ? cc : res; +} + +#endif /* !_FS_READONLY */ +#endif /* _USE_STRFUNC */ diff --git a/radio/bootloader/ff_lfn.cpp b/radio/bootloader/ff_lfn.cpp new file mode 100644 index 000000000..377cc8ce3 --- /dev/null +++ b/radio/bootloader/ff_lfn.cpp @@ -0,0 +1,113 @@ +/**************************************************************************** +* Copyright (c) 2014 by Michael Blandford. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. Neither the name of the author nor the names of its contributors may +* be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +* SUCH DAMAGE. +* +**************************************************************************** +* Other Authors: + * - Andre Bernet + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer +* +****************************************************************************/ + +#include "ff.h" + +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP437(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, + 0x00FF, 0x00D6, 0x00DC, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, + 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, + 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + + +WCHAR ff_convert ( /* Converted character, Returns zero on error */ + WCHAR chr, /* Character code to be converted */ + UINT dir /* 0: Unicode to OEMCP, 1: OEMCP to Unicode */ +) +{ + WCHAR c; + + + if (chr < 0x80) { /* ASCII */ + c = chr; + + } else { + if (dir) { /* OEMCP to Unicode */ + c = (chr >= 0x100) ? 0 : Tbl[chr - 0x80]; + + } else { /* Unicode to OEMCP */ + for (c = 0; c < 0x80; c++) { + if (chr == Tbl[c]) break; + } + c = (c + 0x80) & 0xFF; + } + } + + return c; +} + + +WCHAR ff_wtoupper ( /* Upper converted character */ + WCHAR chr /* Input character */ +) +{ + static const WCHAR tbl_lower[] = { 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0xA1, 0x00A2, 0x00A3, 0x00A5, 0x00AC, 0x00AF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0x0FF, 0x101, 0x103, 0x105, 0x107, 0x109, 0x10B, 0x10D, 0x10F, 0x111, 0x113, 0x115, 0x117, 0x119, 0x11B, 0x11D, 0x11F, 0x121, 0x123, 0x125, 0x127, 0x129, 0x12B, 0x12D, 0x12F, 0x131, 0x133, 0x135, 0x137, 0x13A, 0x13C, 0x13E, 0x140, 0x142, 0x144, 0x146, 0x148, 0x14B, 0x14D, 0x14F, 0x151, 0x153, 0x155, 0x157, 0x159, 0x15B, 0x15D, 0x15F, 0x161, 0x163, 0x165, 0x167, 0x169, 0x16B, 0x16D, 0x16F, 0x171, 0x173, 0x175, 0x177, 0x17A, 0x17C, 0x17E, 0x192, 0x3B1, 0x3B2, 0x3B3, 0x3B4, 0x3B5, 0x3B6, 0x3B7, 0x3B8, 0x3B9, 0x3BA, 0x3BB, 0x3BC, 0x3BD, 0x3BE, 0x3BF, 0x3C0, 0x3C1, 0x3C3, 0x3C4, 0x3C5, 0x3C6, 0x3C7, 0x3C8, 0x3C9, 0x3CA, 0x430, 0x431, 0x432, 0x433, 0x434, 0x435, 0x436, 0x437, 0x438, 0x439, 0x43A, 0x43B, 0x43C, 0x43D, 0x43E, 0x43F, 0x440, 0x441, 0x442, 0x443, 0x444, 0x445, 0x446, 0x447, 0x448, 0x449, 0x44A, 0x44B, 0x44C, 0x44D, 0x44E, 0x44F, 0x451, 0x452, 0x453, 0x454, 0x455, 0x456, 0x457, 0x458, 0x459, 0x45A, 0x45B, 0x45C, 0x45E, 0x45F, 0x2170, 0x2171, 0x2172, 0x2173, 0x2174, 0x2175, 0x2176, 0x2177, 0x2178, 0x2179, 0x217A, 0x217B, 0x217C, 0x217D, 0x217E, 0x217F, 0xFF41, 0xFF42, 0xFF43, 0xFF44, 0xFF45, 0xFF46, 0xFF47, 0xFF48, 0xFF49, 0xFF4A, 0xFF4B, 0xFF4C, 0xFF4D, 0xFF4E, 0xFF4F, 0xFF50, 0xFF51, 0xFF52, 0xFF53, 0xFF54, 0xFF55, 0xFF56, 0xFF57, 0xFF58, 0xFF59, 0xFF5A, 0 }; + static const WCHAR tbl_upper[] = { 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x21, 0xFFE0, 0xFFE1, 0xFFE5, 0xFFE2, 0xFFE3, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0x178, 0x100, 0x102, 0x104, 0x106, 0x108, 0x10A, 0x10C, 0x10E, 0x110, 0x112, 0x114, 0x116, 0x118, 0x11A, 0x11C, 0x11E, 0x120, 0x122, 0x124, 0x126, 0x128, 0x12A, 0x12C, 0x12E, 0x130, 0x132, 0x134, 0x136, 0x139, 0x13B, 0x13D, 0x13F, 0x141, 0x143, 0x145, 0x147, 0x14A, 0x14C, 0x14E, 0x150, 0x152, 0x154, 0x156, 0x158, 0x15A, 0x15C, 0x15E, 0x160, 0x162, 0x164, 0x166, 0x168, 0x16A, 0x16C, 0x16E, 0x170, 0x172, 0x174, 0x176, 0x179, 0x17B, 0x17D, 0x191, 0x391, 0x392, 0x393, 0x394, 0x395, 0x396, 0x397, 0x398, 0x399, 0x39A, 0x39B, 0x39C, 0x39D, 0x39E, 0x39F, 0x3A0, 0x3A1, 0x3A3, 0x3A4, 0x3A5, 0x3A6, 0x3A7, 0x3A8, 0x3A9, 0x3AA, 0x410, 0x411, 0x412, 0x413, 0x414, 0x415, 0x416, 0x417, 0x418, 0x419, 0x41A, 0x41B, 0x41C, 0x41D, 0x41E, 0x41F, 0x420, 0x421, 0x422, 0x423, 0x424, 0x425, 0x426, 0x427, 0x428, 0x429, 0x42A, 0x42B, 0x42C, 0x42D, 0x42E, 0x42F, 0x401, 0x402, 0x403, 0x404, 0x405, 0x406, 0x407, 0x408, 0x409, 0x40A, 0x40B, 0x40C, 0x40E, 0x40F, 0x2160, 0x2161, 0x2162, 0x2163, 0x2164, 0x2165, 0x2166, 0x2167, 0x2168, 0x2169, 0x216A, 0x216B, 0x216C, 0x216D, 0x216E, 0x216F, 0xFF21, 0xFF22, 0xFF23, 0xFF24, 0xFF25, 0xFF26, 0xFF27, 0xFF28, 0xFF29, 0xFF2A, 0xFF2B, 0xFF2C, 0xFF2D, 0xFF2E, 0xFF2F, 0xFF30, 0xFF31, 0xFF32, 0xFF33, 0xFF34, 0xFF35, 0xFF36, 0xFF37, 0xFF38, 0xFF39, 0xFF3A, 0 }; + int i; + + + for (i = 0; tbl_lower[i] && chr != tbl_lower[i]; i++) ; + + return tbl_lower[i] ? tbl_upper[i] : chr; +} + + diff --git a/radio/bootloader/font.lbm b/radio/bootloader/font.lbm new file mode 100644 index 000000000..e95bed6c6 --- /dev/null +++ b/radio/bootloader/font.lbm @@ -0,0 +1,8 @@ +const uint8_t font[] = { +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x6f,0x00,0x00,0x07,0x00,0x07,0x00,0x14,0x7f,0x14,0x7f,0x14,0x24,0x2a,0x7f,0x2a,0x12,0x23,0x13,0x08,0x64,0x62,0x36,0x49,0x55,0x22,0x50,0x00,0x05,0x03,0x00,0x00,0x00,0x1c,0x22,0x41,0x00,0x00,0x41,0x22,0x1c,0x00,0x14,0x08,0x3e,0x08,0x14,0x08,0x08,0x3e,0x08,0x08,0x00,0x50,0x30,0x00,0x00,0x08,0x08,0x08,0x08,0x08,0x00,0x60,0x60,0x00,0x00,0x20,0x10,0x08,0x04,0x02, +0x00,0x3e,0x49,0x45,0x3e,0x00,0x00,0x42,0x7f,0x40,0x00,0x62,0x51,0x49,0x46,0x00,0x41,0x49,0x49,0x36,0x00,0x18,0x14,0x12,0x7f,0x00,0x27,0x45,0x45,0x39,0x00,0x3e,0x49,0x49,0x32,0x00,0x01,0x79,0x05,0x03,0x00,0x36,0x49,0x49,0x36,0x00,0x06,0x49,0x29,0x1e,0x00,0x00,0x36,0x36,0x00,0x00,0x00,0x56,0x36,0x00,0x00,0x08,0x14,0x22,0x41,0x14,0x14,0x14,0x14,0x14,0x41,0x22,0x14,0x08,0x00,0x02,0x01,0x51,0x09,0x06, +0x00,0x06,0x09,0x09,0x06,0x7e,0x09,0x09,0x09,0x7e,0x7f,0x49,0x49,0x49,0x36,0x3e,0x41,0x41,0x41,0x22,0x7f,0x41,0x41,0x22,0x1c,0x7f,0x49,0x49,0x49,0x41,0x7f,0x09,0x09,0x09,0x01,0x3e,0x41,0x49,0x49,0x7a,0x7f,0x08,0x08,0x08,0x7f,0x00,0x41,0x7f,0x41,0x00,0x20,0x40,0x41,0x3f,0x01,0x7f,0x08,0x14,0x22,0x41,0x7f,0x40,0x40,0x40,0x40,0x7f,0x02,0x0c,0x02,0x7f,0x7f,0x04,0x08,0x10,0x7f,0x3e,0x41,0x41,0x41,0x3e, +0x7f,0x09,0x09,0x09,0x06,0x3e,0x41,0x51,0x21,0x5e,0x7f,0x09,0x19,0x29,0x46,0x26,0x49,0x49,0x49,0x32,0x01,0x01,0x7f,0x01,0x01,0x3f,0x40,0x40,0x40,0x3f,0x1f,0x20,0x40,0x20,0x1f,0x3f,0x40,0x30,0x40,0x3f,0x63,0x14,0x08,0x14,0x63,0x07,0x08,0x70,0x08,0x07,0x61,0x51,0x49,0x45,0x43,0x00,0x7f,0x41,0x41,0x00,0x02,0x04,0x08,0x10,0x20,0x00,0x41,0x41,0x7f,0x00,0x04,0x02,0x01,0x02,0x04,0x40,0x40,0x40,0x40,0x40, +0x00,0x01,0x02,0x04,0x00,0x20,0x54,0x54,0x54,0x78,0x7f,0x48,0x44,0x44,0x38,0x38,0x44,0x44,0x44,0x20,0x38,0x44,0x44,0x48,0x7f,0x38,0x54,0x54,0x54,0x18,0x08,0x7e,0x09,0x01,0x02,0x0c,0x52,0x52,0x52,0x3e,0x7f,0x08,0x04,0x04,0x78,0x00,0x44,0x7d,0x40,0x00,0x20,0x40,0x44,0x3d,0x00,0x7f,0x10,0x28,0x44,0x00,0x00,0x41,0x7f,0x40,0x00,0x7c,0x04,0x18,0x04,0x78,0x7c,0x08,0x04,0x04,0x78,0x38,0x44,0x44,0x44,0x38, +0x7c,0x14,0x14,0x14,0x08,0x08,0x14,0x14,0x18,0x7c,0x7c,0x08,0x04,0x04,0x08,0x48,0x54,0x54,0x54,0x20,0x04,0x3f,0x44,0x40,0x20,0x3c,0x40,0x40,0x20,0x7c,0x1c,0x20,0x40,0x20,0x1c,0x3c,0x40,0x20,0x40,0x3c,0x44,0x28,0x10,0x28,0x44,0x0c,0x50,0x50,0x50,0x3c,0x44,0x64,0x54,0x4c,0x44,0x00,0x08,0x36,0x41,0x00,0x00,0x00,0x7f,0x00,0x00,0x00,0x41,0x36,0x08,0x00,0x08,0x08,0x22,0x1c,0x08,0x08,0x1c,0x22,0x08,0x08, +}; diff --git a/radio/bootloader/font_dblsize.lbm b/radio/bootloader/font_dblsize.lbm new file mode 100644 index 000000000..f8533a669 --- /dev/null +++ b/radio/bootloader/font_dblsize.lbm @@ -0,0 +1,16 @@ +const uint8_t font_dblsize[] = { + +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, //' ' +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + +0xff,0xff,0xc3,0xc3,0xc3,0xc3,0xc3,0xe7,0xfe,0x3c, //'B' +0x3f,0x3f,0x30,0x30,0x30,0x30,0x30,0x39,0x1f,0x0f, + + +0x3c,0x7e,0xe7,0xc3,0xc3,0xc3,0xc3,0xc7,0x8e,0x0c, //'S' +0x0c,0x1c,0x38,0x30,0x30,0x30,0x30,0x39,0x1f,0x0f, + +0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0xff,0xff, //'U' +0x0f,0x1f,0x38,0x30,0x30,0x30,0x30,0x38,0x1f,0x0f, + +}; diff --git a/radio/bootloader/i2c_ee.cpp b/radio/bootloader/i2c_ee.cpp new file mode 100644 index 000000000..def61280a --- /dev/null +++ b/radio/bootloader/i2c_ee.cpp @@ -0,0 +1,416 @@ +/** + ****************************************************************************** + * @file Project/ee_drivers/i2c_ee.c + * @author X9D Application Team + * @version V 0.2 + * @date 12-JULY-2012 + * @brief This file provides a set of functions needed to manage the + * communication between I2C peripheral and I2C M24CXX EEPROM. + CAT5137 added,share the I2C. + ****************************************************************************** +*/ + + +#include "radio.h" +#include "stm32f2xx.h" +#include "logicio.h" +#include "stm32f2xx_rcc.h" +#include "hal.h" +#include "i2c_ee.h" +#include "timers.h" + + +#define I2C_delay() hw_delay( 100 ) + +/** + * @brief Configure the used I/O ports pin + * @param None + * @retval None + */ +static void I2C_GPIO_Configuration(void) +{ + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN ; // Enable portB clock + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOEEN ; // Enable portE clock + +// GPIO_InitTypeDef GPIO_InitStructure; + + GPIOB->BSRRH =I2C_EE_WP; //PB9 + configure_pins( I2C_EE_WP, PIN_OUTPUT | PIN_OS50 | PIN_PORTB | PIN_PUSHPULL | PIN_NO_PULL ) ; + +// GPIO_InitStructure.GPIO_Pin = I2C_EE_WP; +// GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; +// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; +// GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; +// GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; +// GPIO_Init(I2C_EE_WP_GPIO, &GPIO_InitStructure); + + /* Configure I2C_EE pins: SCL and SDA */ + configure_pins( I2C_EE_SCL | I2C_EE_SDA, PIN_OUTPUT | PIN_OS50 | PIN_PORTB | PIN_ODRAIN | PIN_PULLUP ) ; +// GPIO_InitStructure.GPIO_Pin = I2C_EE_SCL | I2C_EE_SDA;//PE0,PE1 +// GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; +// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; +// GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; +// GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; +// GPIO_Init(I2C_EE_GPIO, &GPIO_InitStructure); + + //Set Idle levels + SDA_H; + SCL_H; + WP_L ; +} + +short I2C_START() +{ + SDA_H; + I2C_delay(); + SCL_H; + I2C_delay(); + // if (!SDA_read) return 0; + SDA_L; + I2C_delay(); + // if (SDA_read) return 0; + SCL_L; + I2C_delay(); + return 1; +} + +void I2C_STOP() +{ + SCL_L; + I2C_delay(); + SDA_L; + I2C_delay(); + SCL_H; + I2C_delay(); + SDA_H; + I2C_delay(); +} + +void I2C_ACK() +{ + SCL_L; + I2C_delay(); + SDA_L; + I2C_delay(); + SCL_H; + I2C_delay(); + SCL_L; + I2C_delay(); +} +void I2C_NO_ACK() +{ + SCL_L; + I2C_delay(); + SDA_H; + I2C_delay(); + SCL_H; + I2C_delay(); + SCL_L; + I2C_delay(); +} + +short I2C_WAIT_ACK() +{ + short i=50; + SCL_L; + I2C_delay(); + SDA_H; + I2C_delay(); + SCL_H; + I2C_delay(); + while(i) { + if(SDA_read) { + I2C_delay(); + i--; + } + else { + i=2; + break; + } + } + SCL_L; + I2C_delay(); + + return i; +} + +void I2C_SEND_DATA(char SendByte) +{ + short i=8; + while (i--) { + SCL_L; +// I2C_delay(); + if (SendByte & 0x80) + SDA_H; + else + SDA_L; + SendByte <<= 1; + I2C_delay(); + SCL_H; + I2C_delay(); + } + SCL_L; + I2C_delay(); +} + +char I2C_READ() +{ + short i=8; + char ReceiveByte=0; + + SDA_H; + while (i--) { + ReceiveByte <<= 1; + SCL_L; + I2C_delay(); + SCL_H; + I2C_delay(); + if (SDA_read) { + ReceiveByte|=0x01; + } + } + SCL_L; + return ReceiveByte; +} + +void I2C_EE_Init() +{ + /* GPIO Periph clock enable */ + RCC_AHB1PeriphClockCmd(I2C_EE_GPIO_CLK, ENABLE); + + /* GPIO configuration */ + I2C_GPIO_Configuration(); +} + +void I2C_set_volume( register uint8_t volume ) +{ + I2C_START(); + I2C_SEND_DATA(I2C_CAT5137_ADDRESS|EE_CMD_WRITE); + I2C_WAIT_ACK(); + I2C_SEND_DATA(0); + I2C_WAIT_ACK(); + I2C_SEND_DATA(volume); + I2C_WAIT_ACK(); + I2C_STOP(); +} + +uint8_t I2C_read_volume() +{ + uint8_t volume ; + I2C_START(); + I2C_SEND_DATA(I2C_CAT5137_ADDRESS|EE_CMD_WRITE); + I2C_WAIT_ACK(); + I2C_SEND_DATA(0); + I2C_WAIT_ACK(); + I2C_START(); + I2C_SEND_DATA(I2C_CAT5137_ADDRESS|EE_CMD_READ); + I2C_WAIT_ACK(); + volume = I2C_READ(); + I2C_NO_ACK(); + I2C_STOP(); + return volume ; +} + +/** + * @brief Writes one byte to the I2C EEPROM. + * @param pBuffer : pointer to the buffer containing the data to be + * written to the EEPROM. + * @param WriteAddr : EEPROM's internal address to write to. + * @retval None + */ +void I2C_EE_ByteWrite(uint8_t* pBuffer, uint16_t WriteAddr) +{ + I2C_START(); + I2C_SEND_DATA(I2C_EEPROM_ADDRESS|EE_CMD_WRITE); + I2C_WAIT_ACK(); +#ifdef EE_M24C08 + I2C_SEND_DATA(WriteAddr); + I2C_WAIT_ACK(); +#else + I2C_SEND_DATA((uint8_t)((WriteAddr&0xFF00)>>8) ); + I2C_WAIT_ACK(); + I2C_SEND_DATA((uint8_t)(WriteAddr&0xFF)); + I2C_WAIT_ACK(); +#endif + I2C_SEND_DATA(*pBuffer); + I2C_WAIT_ACK(); + I2C_STOP(); +} + +/** + * @brief Reads a block of data from the EEPROM. + * @param pBuffer : pointer to the buffer that receives the data read + * from the EEPROM. + * @param ReadAddr : EEPROM's internal address to read from. + * @param NumByteToRead : number of bytes to read from the EEPROM. + * @retval None + */ +void I2C_EE_BufferRead(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t NumByteToRead) +{ + I2C_START(); + I2C_SEND_DATA(I2C_EEPROM_ADDRESS|EE_CMD_WRITE); + I2C_WAIT_ACK(); +#ifdef EE_M24C08 + I2C_SEND_DATA(ReadAddr); + I2C_WAIT_ACK(); +#else + I2C_SEND_DATA((uint8_t)((ReadAddr & 0xFF00) >> 8)); + I2C_WAIT_ACK(); + I2C_SEND_DATA((uint8_t)(ReadAddr & 0x00FF)); + I2C_WAIT_ACK(); +#endif + + I2C_START(); + I2C_SEND_DATA(I2C_EEPROM_ADDRESS|EE_CMD_READ); + I2C_WAIT_ACK(); + while (NumByteToRead) { + if (NumByteToRead == 1) { + *pBuffer =I2C_READ(); + I2C_NO_ACK(); + I2C_STOP(); + } + else { + *pBuffer =I2C_READ(); + I2C_ACK(); + pBuffer++; + } + NumByteToRead--; + } +} + +/** + * @brief Writes buffer of data to the I2C EEPROM. + * @param pBuffer : pointer to the buffer containing the data to be + * written to the EEPROM. + * @param WriteAddr : EEPROM's internal address to write to. + * @param NumByteToWrite : number of bytes to write to the EEPROM. + * @retval None + */ +void I2C_EE_BufferWrite(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite) +{ + uint8_t NumOfPage = 0, NumOfSingle = 0, count = 0; + uint16_t Addr = 0; + + Addr = WriteAddr % I2C_FLASH_PAGESIZE; + count = I2C_FLASH_PAGESIZE - Addr; + NumOfPage = NumByteToWrite / I2C_FLASH_PAGESIZE; + NumOfSingle = NumByteToWrite % I2C_FLASH_PAGESIZE; + + /* If WriteAddr is I2C_FLASH_PAGESIZE aligned */ + if (Addr == 0) { + /* If NumByteToWrite < I2C_FLASH_PAGESIZE */ + if (NumOfPage == 0) { + I2C_EE_PageWrite(pBuffer, WriteAddr, NumOfSingle); + + I2C_EE_WaitEepromStandbyState(); + } + /* If NumByteToWrite > I2C_FLASH_PAGESIZE */ + else { + while (NumOfPage--) { + I2C_EE_PageWrite(pBuffer, WriteAddr, I2C_FLASH_PAGESIZE); + I2C_EE_WaitEepromStandbyState(); + WriteAddr += I2C_FLASH_PAGESIZE; + pBuffer += I2C_FLASH_PAGESIZE; + } + + if (NumOfSingle != 0) { + I2C_EE_PageWrite(pBuffer, WriteAddr, NumOfSingle); + I2C_EE_WaitEepromStandbyState(); + } + } + } + /* If WriteAddr is not I2C_FLASH_PAGESIZE aligned */ + else { + /* If NumByteToWrite < I2C_FLASH_PAGESIZE */ + if (NumOfPage== 0) { + /* If the number of data to be written is more than the remaining space + in the current page: */ + if (NumByteToWrite > count) { + /* Write the data conained in same page */ + I2C_EE_PageWrite(pBuffer, WriteAddr, count); + I2C_EE_WaitEepromStandbyState(); + + /* Write the remaining data in the following page */ + I2C_EE_PageWrite((uint8_t*)(pBuffer + count), (WriteAddr + count), (NumByteToWrite - count)); + I2C_EE_WaitEepromStandbyState(); + } + else { + I2C_EE_PageWrite(pBuffer, WriteAddr, NumOfSingle); + I2C_EE_WaitEepromStandbyState(); + } + } + /* If NumByteToWrite > I2C_FLASH_PAGESIZE */ + else { + NumByteToWrite -= count; + NumOfPage = NumByteToWrite / I2C_FLASH_PAGESIZE; + NumOfSingle = NumByteToWrite % I2C_FLASH_PAGESIZE; + + if (count != 0) { + I2C_EE_PageWrite(pBuffer, WriteAddr, count); + I2C_EE_WaitEepromStandbyState(); + WriteAddr += count; + pBuffer += count; + } + + while (NumOfPage--) { + I2C_EE_PageWrite(pBuffer, WriteAddr, I2C_FLASH_PAGESIZE); + I2C_EE_WaitEepromStandbyState(); + WriteAddr += I2C_FLASH_PAGESIZE; + pBuffer += I2C_FLASH_PAGESIZE; + } + if (NumOfSingle != 0) { + I2C_EE_PageWrite(pBuffer, WriteAddr, NumOfSingle); + I2C_EE_WaitEepromStandbyState(); + } + } + } +} + +/** + * @brief Writes more than one byte to the EEPROM with a single WRITE cycle. + * @note The number of byte can't exceed the EEPROM page size. + * @param pBuffer : pointer to the buffer containing the data to be + * written to the EEPROM. + * @param WriteAddr : EEPROM's internal address to write to. + * @param NumByteToWrite : number of bytes to write to the EEPROM. + * @retval None + */ +void I2C_EE_PageWrite(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t NumByteToWrite) +{ + I2C_START(); + I2C_SEND_DATA(I2C_EEPROM_ADDRESS|EE_CMD_WRITE); + I2C_WAIT_ACK(); + +#ifdef EE_M24C08 + I2C_SEND_DATA(WriteAddr); + I2C_WAIT_ACK(); +#else + I2C_SEND_DATA((uint8_t)((WriteAddr & 0xFF00) >> 8)); + I2C_WAIT_ACK(); + I2C_SEND_DATA((uint8_t)(WriteAddr & 0x00FF)); + I2C_WAIT_ACK(); +#endif /* EE_M24C08 */ + + /* While there is data to be written */ + while (NumByteToWrite--) { + I2C_SEND_DATA(*pBuffer); + I2C_WAIT_ACK(); + pBuffer++; + } + I2C_STOP(); +} + +/** + * @brief Wait for EEPROM Standby state + * @param None + * @retval None + */ +void I2C_EE_WaitEepromStandbyState(void) +{ + do { + I2C_START(); + I2C_SEND_DATA(I2C_EEPROM_ADDRESS|EE_CMD_WRITE); + } while (0 == I2C_WAIT_ACK()); + + I2C_STOP(); +} diff --git a/radio/bootloader/include/AT91SAM3S4.h b/radio/bootloader/include/AT91SAM3S4.h new file mode 100644 index 000000000..1e6914308 --- /dev/null +++ b/radio/bootloader/include/AT91SAM3S4.h @@ -0,0 +1,7102 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2009, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ +/* */ +/* File Name : AT91SAM3S.h */ +/* Object : AT91SAM3S definitions */ +/* Generated by : AT91 SW Application Group */ +/* Generated on : 2009-10-26 */ + +#ifndef AT91SAM3S_H +#define AT91SAM3S_H + +/** \addtogroup AT91SAM3S_definitions AT91SAM3S definitions + This file defines all structures and symbols for AT91SAM3S: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __ASSEMBLY__ +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +#define CAST(type, value) ((type *) value) +#define REG_ACCESS(type, address) (*(type*)address) /**< C code: Register value */ +#else +#define CAST(type, value) (value) +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif + +/* ***************************************************************************** */ +/* CMSIS DEFINITIONS FOR AT91SAM3S */ +/* ***************************************************************************** */ +/** \addtogroup AT91SAM3S_cmsis CMSIS Definitions */ + +/*@{*/ + +/** + * \brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ +#define __MPU_PRESENT 0 /**< AT91SAM3S does not provide a MPU present or not */ +#define __NVIC_PRIO_BITS 4 /**< AT91SAM3S uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ +/****** AT91SAM3S specific Interrupt Numbers *****************************************/ + + SUPC_IRQn = 0, /**< 0 AT91SAM3S Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 AT91SAM3S Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 AT91SAM3S Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 AT91SAM3S Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 AT91SAM3S Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 AT91SAM3S Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 AT91SAM3S Enhanced Flash Controller (EFC) */ + UART0_IRQn = 8, /**< 8 AT91SAM3S UART 0 (UART0) */ + UART1_IRQn = 9, /**< 9 AT91SAM3S UART 1 (UART1) */ + SMC_IRQn = 10, /**< 10 AT91SAM3S Static Memory Controller (SMC) */ + PIOA_IRQn = 11, /**< 11 AT91SAM3S Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 12, /**< 12 AT91SAM3S Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 13, /**< 13 AT91SAM3S Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 14, /**< 14 AT91SAM3S USART 0 (USART0) */ + USART1_IRQn = 15, /**< 15 AT91SAM3S USART 1 (USART1) */ + HSMCI_IRQn = 18, /**< 18 AT91SAM3S Multimedia Card Interface (HSMCI) */ + TWI0_IRQn = 19, /**< 19 AT91SAM3S Two Wire Interface 0 (TWI0) */ + TWI1_IRQn = 20, /**< 20 AT91SAM3S Two Wire Interface 1 (TWI1) */ + SPI_IRQn = 21, /**< 21 AT91SAM3S Serial Peripheral Interface (SPI) */ + SSC_IRQn = 22, /**< 22 AT91SAM3S Synchronous Serial Controler (SSC) */ + TC0_IRQn = 23, /**< 23 AT91SAM3S Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 AT91SAM3S Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 AT91SAM3S Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 AT91SAM3S Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 AT91SAM3S Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 AT91SAM3S Timer/Counter 5 (TC5) */ + ADC_IRQn = 29, /**< 29 AT91SAM3S Analog To Digital Converter (ADC) */ + DACC_IRQn = 30, /**< 30 AT91SAM3S Digital To Analog Converter (DACC) */ + PWM_IRQn = 31, /**< 31 AT91SAM3S Pulse Width Modulation (PWM) */ + CRCCU_IRQn = 32, /**< 32 AT91SAM3S CRC Calculation Unit (CRCCU) */ + ACC_IRQn = 33, /**< 33 AT91SAM3S Analog Comparator (ACC) */ + UDP_IRQn = 34 /**< 34 AT91SAM3S USB Device Port (UDP) */ +} IRQn_Type; +/*@}*/ + +/* ***************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR AT91SAM3S */ +/* ***************************************************************************** */ +/** \addtogroup AT91SAM3S_api Peripheral Software API */ +/*@{*/ +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_ACC Analog Comparator Controller */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Acc hardware registers */ +typedef struct { + WoReg ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */ + RwReg ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */ + RwReg Reserved1[7]; + WoReg ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */ + WoReg ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */ + RoReg ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */ + RoReg ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */ + RwReg Reserved2[24]; + RwReg ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */ + RwReg Reserved3[19]; + RwReg ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protect Mode Register */ + RoReg ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protect Status Register */ +} Acc; +#endif /* __ASSEMBLY__ */ +/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */ +#define ACC_CR_SWRST (0x1 << 0) /**< \brief (ACC_CR) SoftWare ReSeT */ +/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */ +#define ACC_MR_SELPLUS (0x7 << 0) /**< \brief (ACC_MR) SELection for PLUS comparator input */ +#define ACC_MR_SELMINUS (0x7 << 4) /**< \brief (ACC_MR) SELection for MINUS comparator input */ +#define ACC_MR_ACEN (0x1 << 8) /**< \brief (ACC_MR) Analog Comparator ENable */ +#define ACC_MR_ACEN_EN (0x1 << 8) /**< \brief (ACC_MR) Analog Comparator ENable */ +#define ACC_MR_ACEN_DIS (0x0 << 8) /**< \brief (ACC_MR) Analog Comparator Disable */ +#define ACC_MR_EDGETYP (0x3 << 9) /**< \brief (ACC_MR) EDGE TYPe */ +#define ACC_MR_EDGETYP_RISING (0x0 << 9) /**< \brief (ACC_MR) EDGE TYPe ,RISING edge*/ +#define ACC_MR_EDGETYP_FALLING (0x1 << 9) /**< \brief (ACC_MR) EDGE TYPe,falling edge */ +#define ACC_MR_EDGETYP_ANY (0x2 << 9) /**< \brief (ACC_MR) EDGE TYPe,any edge */ +#define ACC_MR_INV (0x1 << 12) /**< \brief (ACC_MR) INVert comparator output */ +#define ACC_MR_INV_EN (0x1 << 12) /**< \brief (ACC_MR) INVert comparator output */ +#define ACC_MR_INV_DIS (0x0 << 12) /**< \brief (ACC_MR) DIRECTLY */ +#define ACC_MR_SELFS (0x1 << 13) /**< \brief (ACC_MR) SELection of Fault Source */ +#define ACC_MR_SELFS_CF (0x0 << 13) /**< \brief (ACC_MR) SELection of Fault Source */ +#define ACC_MR_SELFS_OUTPUT (0x1 << 13) /**< \brief (ACC_MR) SELection of Fault Source */ +#define ACC_MR_FE (0x1 << 14) /**< \brief (ACC_MR) Fault Enable */ +#define ACC_MR_FE_EN (0x1 << 14) /**< \brief (ACC_MR) Fault Enable */ +#define ACC_MR_FE_DIS (0x0 << 14) /**< \brief (ACC_MR) Fault Enable */ +/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */ +#define ACC_IER_CE (0x1 << 0) /**< \brief (ACC_IER) Comparison Edge */ +/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */ +#define ACC_IDR_CE (0x1 << 0) /**< \brief (ACC_IDR) Comparison Edge */ +/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define ACC_IMR_CE (0x1 << 0) /**< \brief (ACC_IMR) Comparison Edge */ +/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */ +#define ACC_ISR_CE (0x1 << 0) /**< \brief (ACC_ISR) Comparison Edge */ +#define ACC_ISR_SCO (0x1 << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */ +#define ACC_ISR_MASK (0x1 << 31) /**< \brief (ACC_ISR) */ +/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */ +#define ACC_ACR_ISEL (0x1 << 0) /**< \brief (ACC_ACR) Current SELection */ +#define ACC_ACR_HYST (0x3 << 1) /**< \brief (ACC_ACR) HYSTeresis selection */ +/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protect Mode Register -------- */ +#define ACC_WPMR_WPEN (0x1 << 0) /**< \brief (ACC_WPMR) Write Protect Enable */ +#define ACC_WPMR_WPKEY (0xffffff << 8) /**< \brief (ACC_WPMR) Write Protect KEY */ +/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protect Status Register -------- */ +#define ACC_WPSR_WPROTERR (0x1 << 0) /**< \brief (ACC_WPSR) Write PROTection ERRor */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog-to-digital Converter */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_ADC Analog-to-digital Converter */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Adc hardware registers */ +typedef struct { + WoReg ADC_CR; /**< \brief (Adc Offset: 0x00) Control Register */ + RwReg ADC_MR; /**< \brief (Adc Offset: 0x04) Mode Register */ + RwReg ADC_SEQR1; /**< \brief (Adc Offset: 0x08) Channel Sequence 1Register */ + RwReg ADC_SEQR2; /**< \brief (Adc Offset: 0x0C) Channel Sequence 2 Register */ + WoReg ADC_CHER; /**< \brief (Adc Offset: 0x10) Channel Enable Register */ + WoReg ADC_CHDR; /**< \brief (Adc Offset: 0x14) Channel Disable Register */ + RoReg ADC_CHSR; /**< \brief (Adc Offset: 0x18) Channel Status Register */ + RwReg Reserved1[1]; + RoReg ADC_LCDR; /**< \brief (Adc Offset: 0x20) Last Converted Data Register */ + WoReg ADC_IER; /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */ + WoReg ADC_IDR; /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */ + RoReg ADC_IMR; /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */ + RoReg ADC_ISR; /**< \brief (Adc Offset: 0x30) Interrupt Status Register */ + RwReg Reserved2[2]; + RoReg ADC_OVER; /**< \brief (Adc Offset: 0x3C) Overrun Status Register */ + RwReg ADC_EMR; /**< \brief (Adc Offset: 0x40) Extended Mode Register */ + RwReg ADC_CWR; /**< \brief (Adc Offset: 0x44) Compare Window Register */ + RwReg ADC_CGR; /**< \brief (Adc Offset: 0x48) Channel Gain Register */ + RwReg ADC_COR; /**< \brief (Adc Offset: 0x4C) Channel Offset Register */ + RoReg ADC_CDR0; /**< \brief (Adc Offset: 0x50) Channel Data Register 0 */ + RoReg ADC_CDR1; /**< \brief (Adc Offset: 0x54) Channel Data Register 1 */ + RoReg ADC_CDR2; /**< \brief (Adc Offset: 0x58) Channel Data Register 2 */ + RoReg ADC_CDR3; /**< \brief (Adc Offset: 0x5C) Channel Data Register 3 */ + RoReg ADC_CDR4; /**< \brief (Adc Offset: 0x60) Channel Data Register 4 */ + RoReg ADC_CDR5; /**< \brief (Adc Offset: 0x64) Channel Data Register 5 */ + RoReg ADC_CDR6; /**< \brief (Adc Offset: 0x68) Channel Data Register 6 */ + RoReg ADC_CDR7; /**< \brief (Adc Offset: 0x6C) Channel Data Register 7 */ + RoReg ADC_CDR8; /**< \brief (Adc Offset: 0x70) Channel Data Register 8 */ + RoReg ADC_CDR9; /**< \brief (Adc Offset: 0x74) Channel Data Register 9 */ + RoReg ADC_CDR10; /**< \brief (Adc Offset: 0x78) Channel Data Register 10 */ + RoReg ADC_CDR11; /**< \brief (Adc Offset: 0x7C) Channel Data Register 11 */ + RoReg ADC_CDR12; /**< \brief (Adc Offset: 0x80) Channel Data Register 12 */ + RoReg ADC_CDR13; /**< \brief (Adc Offset: 0x84) Channel Data Register 13 */ + RoReg ADC_CDR14; /**< \brief (Adc Offset: 0x88) Channel Data Register 14 */ + RoReg ADC_CDR15; /**< \brief (Adc Offset: 0x8C) Channel Data Register 15 */ + RwReg Reserved3[1]; + RwReg ADC_ACR; /**< \brief (Adc Offset: 0x94) Analog Control Register */ + RwReg Reserved4[19]; + RwReg ADC_WPMR; /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */ + RoReg ADC_WPSR; /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */ + RwReg Reserved5[5]; + RwReg ADC_RPR; /**< \brief (Adc Offset: 0x100) Receive Pointer Register */ + RwReg ADC_RCR; /**< \brief (Adc Offset: 0x104) Receive Counter Register */ + RwReg ADC_TPR; /**< \brief (Adc Offset: 0x108) Transmit Pointer Register */ + RwReg ADC_TCR; /**< \brief (Adc Offset: 0x10C) Transmit Counter Register */ + RwReg ADC_RNPR; /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */ + RwReg ADC_RNCR; /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */ + RwReg ADC_TNPR; /**< \brief (Adc Offset: 0x118) Transmit Next Pointer Register */ + RwReg ADC_TNCR; /**< \brief (Adc Offset: 0x11C) Transmit Next Counter Register */ + WoReg ADC_PTCR; /**< \brief (Adc Offset: 0x120) Transfer Control Register */ + RoReg ADC_PTSR; /**< \brief (Adc Offset: 0x124) Transfer Status Register */ +} Adc; +#endif /* __ASSEMBLY__ */ +/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */ +#define ADC_CR_SWRST (0x1 << 0) /**< \brief (ADC_CR) Software Reset */ +#define ADC_CR_START (0x1 << 1) /**< \brief (ADC_CR) Start Conversion */ +/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */ +#define ADC_MR_TRGEN (0x1 << 0) /**< \brief (ADC_MR) Trigger Enable */ +#define ADC_MR_TRGEN_DIS (0x0 << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software.*/ +#define ADC_MR_TRGEN_EN (0x1) /**< (ADC) Hardware trigger selected by TRGSEL field is enabled.*/ +#define ADC_MR_TRGSEL (0x7 << 1) /**< \brief (ADC_MR) Trigger Selection */ +#define ADC_MR_TRGSEL_EXT (0x0 << 1) /**< \brief (ADC_MR) Selected TRGSEL = External Trigger*/ +#define ADC_MR_TRGSEL_TIOA0 (0x1 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO0*/ +#define ADC_MR_TRGSEL_TIOA1 (0x2 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO1*/ +#define ADC_MR_TRGSEL_TIOA2 (0x3 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO2*/ +#define ADC_MR_TRGSEL_PWM0_TRIG (0x4 << 1) /**< \brief (ADC_MR) Selected TRGSEL = PWM trigger*/ +#define ADC_MR_TRGSEL_PWM1_TRIG (0x5 << 1) /**< \brief (ADC_MR) Selected TRGSEL = PWM Trigger*/ +#define ADC_MR_TRGSEL_RESERVED (0x6 << 1) /**< \brief (ADC_MR) Selected TRGSEL = Reserved*/ +#define ADC_MR_LOWRES (0x1 << 4) /**< \brief (ADC_MR) Resolution */ +#define ADC_MR_LOWRES_12_BIT (0x0 << 4) /**< \brief (ADC_MR) 12-bit resolution*/ +#define ADC_MR_LOWRES_10_BIT (0x1 << 4) /**< \brief (ADC_MR) 10-bit resolution*/ +#define ADC_MR_SLEEP (0x1 << 5) /**< \brief (ADC_MR) Sleep Mode */ +#define ADC_MR_SLEEP_NORMAL (0x0 << 5) /**< \brief (ADC12B) Normal Mode*/ +#define ADC_MR_FWUP (0x1 << 6) /**< \brief (ADC_MR) Fast Wake Up */ +#define ADC_MR_FREERUN (0x1 << 7) /**< \brief (ADC_MR) Free Run Mode */ +#define ADC_MR_PRESCAL (0xff << 8) /**< \brief (ADC_MR) Prescaler Rate Selection */ +#define ADC_MR_STARTUP (0xf << 16) /**< \brief (ADC_MR) Start Up Time */ +#define ADC_MR_SETTLING (0x3 << 20) /**< \brief (ADC_MR) Analog Settling Time */ +#define ADC_MR_ANACH (0x1 << 23) /**< \brief (ADC_MR) Analog Change */ +#define ADC_MR_TRACKTIM (0xf << 24) /**< \brief (ADC_MR) Tracking Time */ +#define ADC_MR_TRANSFER (0x3 << 28) /**< \brief (ADC_MR) */ +#define ADC_MR_USEQ (0x1 << 31) /**< \brief (ADC_MR) User Sequence Enable */ +/* -------- ADC_SEQ1R : (ADC Offset: 0x08) Channel Sequence 1Register -------- */ +#define ADC_SEQ1R_USCH1 (0x7 << 0) /**< \brief (ADC_SEQ1R) User Sequence Number 1 */ +#define ADC_SEQ1R_USCH2 (0x7 << 4) /**< \brief (ADC_SEQ1R) User Sequence Number 2 */ +#define ADC_SEQ1R_USCH3 (0x7 << 8) /**< \brief (ADC_SEQ1R) User Sequence Number 3 */ +#define ADC_SEQ1R_USCH4 (0x7 << 12) /**< \brief (ADC_SEQ1R) User Sequence Number 4 */ +#define ADC_SEQ1R_USCH5 (0x7 << 16) /**< \brief (ADC_SEQ1R) User Sequence Number 5 */ +#define ADC_SEQ1R_USCH6 (0x7 << 20) /**< \brief (ADC_SEQ1R) User Sequence Number 6 */ +#define ADC_SEQ1R_USCH7 (0x7 << 24) /**< \brief (ADC_SEQ1R) User Sequence Number 7 */ +#define ADC_SEQ1R_USCH8 (0x7 << 28) /**< \brief (ADC_SEQ1R) User Sequence Number 8 */ +/* -------- ADC_SEQ2R : (ADC Offset: 0x0C) Channel Sequence 2 Register -------- */ +#define ADC_SEQ2R_USCH9 (0x7 << 0) /**< \brief (ADC_SEQ2R) User Sequence Number 9 */ +#define ADC_SEQ2R_USCH10 (0x7 << 4) /**< \brief (ADC_SEQ2R) User Sequence Number 10 */ +#define ADC_SEQ2R_USCH11 (0x7 << 8) /**< \brief (ADC_SEQ2R) User Sequence Number 11 */ +#define ADC_SEQ2R_USCH12 (0x7 << 12) /**< \brief (ADC_SEQ2R) User Sequence Number 12 */ +#define ADC_SEQ2R_USCH13 (0x7 << 16) /**< \brief (ADC_SEQ2R) User Sequence Number 13 */ +#define ADC_SEQ2R_USCH14 (0x7 << 20) /**< \brief (ADC_SEQ2R) User Sequence Number 14 */ +#define ADC_SEQ2R_USCH15 (0x7 << 24) /**< \brief (ADC_SEQ2R) User Sequence Number 15 */ +#define ADC_SEQ2R_USCH16 (0x7 << 28) /**< \brief (ADC_SEQ2R) User Sequence Number 16 */ +/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */ +#define ADC_CHER_CH0 (0x1 << 0) /**< \brief (ADC_CHER) Channel 0 Enable */ +#define ADC_CHER_CH1 (0x1 << 1) /**< \brief (ADC_CHER) Channel 1 Enable */ +#define ADC_CHER_CH2 (0x1 << 2) /**< \brief (ADC_CHER) Channel 2 Enable */ +#define ADC_CHER_CH3 (0x1 << 3) /**< \brief (ADC_CHER) Channel 3 Enable */ +#define ADC_CHER_CH4 (0x1 << 4) /**< \brief (ADC_CHER) Channel 4 Enable */ +#define ADC_CHER_CH5 (0x1 << 5) /**< \brief (ADC_CHER) Channel 5 Enable */ +#define ADC_CHER_CH6 (0x1 << 6) /**< \brief (ADC_CHER) Channel 6 Enable */ +#define ADC_CHER_CH7 (0x1 << 7) /**< \brief (ADC_CHER) Channel 7 Enable */ +#define ADC_CHER_CH8 (0x1 << 8) /**< \brief (ADC_CHER) Channel 8 Enable */ +#define ADC_CHER_CH9 (0x1 << 9) /**< \brief (ADC_CHER) Channel 9 Enable */ +#define ADC_CHER_CH10 (0x1 << 10) /**< \brief (ADC_CHER) Channel 10 Enable */ +#define ADC_CHER_CH11 (0x1 << 11) /**< \brief (ADC_CHER) Channel 11 Enable */ +#define ADC_CHER_CH12 (0x1 << 12) /**< \brief (ADC_CHER) Channel 12 Enable */ +#define ADC_CHER_CH13 (0x1 << 13) /**< \brief (ADC_CHER) Channel 13 Enable */ +#define ADC_CHER_CH14 (0x1 << 14) /**< \brief (ADC_CHER) Channel 14 Enable */ +#define ADC_CHER_CH15 (0x1 << 15) /**< \brief (ADC_CHER) Channel 15 Enable */ +/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */ +#define ADC_CHDR_CH0 (0x1 << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */ +#define ADC_CHDR_CH1 (0x1 << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */ +#define ADC_CHDR_CH2 (0x1 << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */ +#define ADC_CHDR_CH3 (0x1 << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */ +#define ADC_CHDR_CH4 (0x1 << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */ +#define ADC_CHDR_CH5 (0x1 << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */ +#define ADC_CHDR_CH6 (0x1 << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */ +#define ADC_CHDR_CH7 (0x1 << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */ +#define ADC_CHDR_CH8 (0x1 << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */ +#define ADC_CHDR_CH9 (0x1 << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */ +#define ADC_CHDR_CH10 (0x1 << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */ +#define ADC_CHDR_CH11 (0x1 << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */ +#define ADC_CHDR_CH12 (0x1 << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */ +#define ADC_CHDR_CH13 (0x1 << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */ +#define ADC_CHDR_CH14 (0x1 << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */ +#define ADC_CHDR_CH15 (0x1 << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */ +/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */ +#define ADC_CHSR_CH0 (0x1 << 0) /**< \brief (ADC_CHSR) Channel 0 Status */ +#define ADC_CHSR_CH1 (0x1 << 1) /**< \brief (ADC_CHSR) Channel 1 Status */ +#define ADC_CHSR_CH2 (0x1 << 2) /**< \brief (ADC_CHSR) Channel 2 Status */ +#define ADC_CHSR_CH3 (0x1 << 3) /**< \brief (ADC_CHSR) Channel 3 Status */ +#define ADC_CHSR_CH4 (0x1 << 4) /**< \brief (ADC_CHSR) Channel 4 Status */ +#define ADC_CHSR_CH5 (0x1 << 5) /**< \brief (ADC_CHSR) Channel 5 Status */ +#define ADC_CHSR_CH6 (0x1 << 6) /**< \brief (ADC_CHSR) Channel 6 Status */ +#define ADC_CHSR_CH7 (0x1 << 7) /**< \brief (ADC_CHSR) Channel 7 Status */ +#define ADC_CHSR_CH8 (0x1 << 8) /**< \brief (ADC_CHSR) Channel 8 Status */ +#define ADC_CHSR_CH9 (0x1 << 9) /**< \brief (ADC_CHSR) Channel 9 Status */ +#define ADC_CHSR_CH10 (0x1 << 10) /**< \brief (ADC_CHSR) Channel 10 Status */ +#define ADC_CHSR_CH11 (0x1 << 11) /**< \brief (ADC_CHSR) Channel 11 Status */ +#define ADC_CHSR_CH12 (0x1 << 12) /**< \brief (ADC_CHSR) Channel 12 Status */ +#define ADC_CHSR_CH13 (0x1 << 13) /**< \brief (ADC_CHSR) Channel 13 Status */ +#define ADC_CHSR_CH14 (0x1 << 14) /**< \brief (ADC_CHSR) Channel 14 Status */ +#define ADC_CHSR_CH15 (0x1 << 15) /**< \brief (ADC_CHSR) Channel 15 Status */ +/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */ +#define ADC_LCDR_LDATA (0xfff << 0) /**< \brief (ADC_LCDR) Last Data Converted */ +#define ADC_LCDR_CHNB (0xf << 12) /**< \brief (ADC_LCDR) Channel Number */ +/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */ +#define ADC_IER_EOC0 (0x1 << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */ +#define ADC_IER_EOC1 (0x1 << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */ +#define ADC_IER_EOC2 (0x1 << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */ +#define ADC_IER_EOC3 (0x1 << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */ +#define ADC_IER_EOC4 (0x1 << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */ +#define ADC_IER_EOC5 (0x1 << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */ +#define ADC_IER_EOC6 (0x1 << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */ +#define ADC_IER_EOC7 (0x1 << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */ +#define ADC_IER_EOC8 (0x1 << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */ +#define ADC_IER_EOC9 (0x1 << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */ +#define ADC_IER_EOC10 (0x1 << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */ +#define ADC_IER_EOC11 (0x1 << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */ +#define ADC_IER_EOC12 (0x1 << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */ +#define ADC_IER_EOC13 (0x1 << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */ +#define ADC_IER_EOC14 (0x1 << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */ +#define ADC_IER_EOC15 (0x1 << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */ +#define ADC_IER_DRDY (0x1 << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */ +#define ADC_IER_GOVRE (0x1 << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */ +#define ADC_IER_COMPE (0x1 << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */ +#define ADC_IER_ENDRX (0x1 << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */ +#define ADC_IER_RXBUFF (0x1 << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */ +/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */ +#define ADC_IDR_EOC0 (0x1 << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */ +#define ADC_IDR_EOC1 (0x1 << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */ +#define ADC_IDR_EOC2 (0x1 << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */ +#define ADC_IDR_EOC3 (0x1 << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */ +#define ADC_IDR_EOC4 (0x1 << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */ +#define ADC_IDR_EOC5 (0x1 << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */ +#define ADC_IDR_EOC6 (0x1 << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */ +#define ADC_IDR_EOC7 (0x1 << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */ +#define ADC_IDR_EOC8 (0x1 << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */ +#define ADC_IDR_EOC9 (0x1 << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */ +#define ADC_IDR_EOC10 (0x1 << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */ +#define ADC_IDR_EOC11 (0x1 << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */ +#define ADC_IDR_EOC12 (0x1 << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */ +#define ADC_IDR_EOC13 (0x1 << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */ +#define ADC_IDR_EOC14 (0x1 << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */ +#define ADC_IDR_EOC15 (0x1 << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */ +#define ADC_IDR_DRDY (0x1 << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */ +#define ADC_IDR_GOVRE (0x1 << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */ +#define ADC_IDR_COMPE (0x1 << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */ +#define ADC_IDR_ENDRX (0x1 << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */ +#define ADC_IDR_RXBUFF (0x1 << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */ +/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */ +#define ADC_IMR_EOC0 (0x1 << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */ +#define ADC_IMR_EOC1 (0x1 << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */ +#define ADC_IMR_EOC2 (0x1 << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */ +#define ADC_IMR_EOC3 (0x1 << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */ +#define ADC_IMR_EOC4 (0x1 << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */ +#define ADC_IMR_EOC5 (0x1 << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */ +#define ADC_IMR_EOC6 (0x1 << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */ +#define ADC_IMR_EOC7 (0x1 << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */ +#define ADC_IMR_EOC8 (0x1 << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */ +#define ADC_IMR_EOC9 (0x1 << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */ +#define ADC_IMR_EOC10 (0x1 << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */ +#define ADC_IMR_EOC11 (0x1 << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */ +#define ADC_IMR_EOC12 (0x1 << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */ +#define ADC_IMR_EOC13 (0x1 << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */ +#define ADC_IMR_EOC14 (0x1 << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */ +#define ADC_IMR_EOC15 (0x1 << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */ +#define ADC_IMR_DRDY (0x1 << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */ +#define ADC_IMR_GOVRE (0x1 << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */ +#define ADC_IMR_COMPE (0x1 << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */ +#define ADC_IMR_ENDRX (0x1 << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */ +#define ADC_IMR_RXBUFF (0x1 << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */ +/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */ +#define ADC_ISR_EOC0 (0x1 << 0) /**< \brief (ADC_ISR) End of Conversion 0 */ +#define ADC_ISR_EOC1 (0x1 << 1) /**< \brief (ADC_ISR) End of Conversion 1 */ +#define ADC_ISR_EOC2 (0x1 << 2) /**< \brief (ADC_ISR) End of Conversion 2 */ +#define ADC_ISR_EOC3 (0x1 << 3) /**< \brief (ADC_ISR) End of Conversion 3 */ +#define ADC_ISR_EOC4 (0x1 << 4) /**< \brief (ADC_ISR) End of Conversion 4 */ +#define ADC_ISR_EOC5 (0x1 << 5) /**< \brief (ADC_ISR) End of Conversion 5 */ +#define ADC_ISR_EOC6 (0x1 << 6) /**< \brief (ADC_ISR) End of Conversion 6 */ +#define ADC_ISR_EOC7 (0x1 << 7) /**< \brief (ADC_ISR) End of Conversion 7 */ +#define ADC_ISR_EOC8 (0x1 << 8) /**< \brief (ADC_ISR) End of Conversion 8 */ +#define ADC_ISR_EOC9 (0x1 << 9) /**< \brief (ADC_ISR) End of Conversion 9 */ +#define ADC_ISR_EOC10 (0x1 << 10) /**< \brief (ADC_ISR) End of Conversion 10 */ +#define ADC_ISR_EOC11 (0x1 << 11) /**< \brief (ADC_ISR) End of Conversion 11 */ +#define ADC_ISR_EOC12 (0x1 << 12) /**< \brief (ADC_ISR) End of Conversion 12 */ +#define ADC_ISR_EOC13 (0x1 << 13) /**< \brief (ADC_ISR) End of Conversion 13 */ +#define ADC_ISR_EOC14 (0x1 << 14) /**< \brief (ADC_ISR) End of Conversion 14 */ +#define ADC_ISR_EOC15 (0x1 << 15) /**< \brief (ADC_ISR) End of Conversion 15 */ +#define ADC_ISR_DRDY (0x1 << 24) /**< \brief (ADC_ISR) Data Ready */ +#define ADC_ISR_GOVRE (0x1 << 25) /**< \brief (ADC_ISR) General Overrun Error */ +#define ADC_ISR_COMPE (0x1 << 26) /**< \brief (ADC_ISR) Comparison Error */ +#define ADC_ISR_ENDRX (0x1 << 27) /**< \brief (ADC_ISR) End of RX Buffer */ +#define ADC_ISR_RXBUFF (0x1 << 28) /**< \brief (ADC_ISR) RX Buffer Full */ +/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */ +#define ADC_OVER_OVRE0 (0x1 << 0) /**< \brief (ADC_OVER) Overrun Error 0 */ +#define ADC_OVER_OVRE1 (0x1 << 1) /**< \brief (ADC_OVER) Overrun Error 1 */ +#define ADC_OVER_OVRE2 (0x1 << 2) /**< \brief (ADC_OVER) Overrun Error 2 */ +#define ADC_OVER_OVRE3 (0x1 << 3) /**< \brief (ADC_OVER) Overrun Error 3 */ +#define ADC_OVER_OVRE4 (0x1 << 4) /**< \brief (ADC_OVER) Overrun Error 4 */ +#define ADC_OVER_OVRE5 (0x1 << 5) /**< \brief (ADC_OVER) Overrun Error 5 */ +#define ADC_OVER_OVRE6 (0x1 << 6) /**< \brief (ADC_OVER) Overrun Error 6 */ +#define ADC_OVER_OVRE7 (0x1 << 7) /**< \brief (ADC_OVER) Overrun Error 7 */ +#define ADC_OVER_OVRE8 (0x1 << 8) /**< \brief (ADC_OVER) Overrun Error 8 */ +#define ADC_OVER_OVRE9 (0x1 << 9) /**< \brief (ADC_OVER) Overrun Error 9 */ +#define ADC_OVER_OVRE10 (0x1 << 10) /**< \brief (ADC_OVER) Overrun Error 10 */ +#define ADC_OVER_OVRE11 (0x1 << 11) /**< \brief (ADC_OVER) Overrun Error 11 */ +#define ADC_OVER_OVRE12 (0x1 << 12) /**< \brief (ADC_OVER) Overrun Error 12 */ +#define ADC_OVER_OVRE13 (0x1 << 13) /**< \brief (ADC_OVER) Overrun Error 13 */ +#define ADC_OVER_OVRE14 (0x1 << 14) /**< \brief (ADC_OVER) Overrun Error 14 */ +#define ADC_OVER_OVRE15 (0x1 << 15) /**< \brief (ADC_OVER) Overrun Error 15 */ +/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */ +#define ADC_EMR_CMPMODE (0x3 << 0) /**< \brief (ADC_EMR) Comparison Mode */ +#define ADC_EMR_CMPMODE_LOW (0x0 << 0) /**< \brief (ADC_EMR) Comparison Mode,lower than low threshold */ +#define ADC_EMR_CMPMODE_HIGH (0x1 << 0) /**< \brief (ADC_EMR) Comparison Mode,higher than high threshold */ +#define ADC_EMR_CMPMODE_IN (0x2 << 0) /**< \brief (ADC_EMR) Comparison Mode, in the comparison window */ +#define ADC_EMR_CMPMODE_OUT (0x3 << 0) /**< \brief (ADC_EMR) Comparison Mode, out of the comparison window */ +#define ADC_EMR_CMPSEL (0xf << 4) /**< \brief (ADC_EMR) Comparison Selected Channel */ +#define ADC_EMR_CMPALL (0x1 << 9) /**< \brief (ADC_EMR) Compare All Channels */ +#define ADC_EMR_TAG (0x1 << 24) /**< \brief (ADC_EMR) TAG of ADC_LDCR register */ +/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */ +#define ADC_CWR_LOWTHRES (0xfff << 0) /**< \brief (ADC_CWR) Low Threshold */ +#define ADC_CWR_HIGHTHRES (0xfff << 16) /**< \brief (ADC_CWR) High Threshold */ +/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */ +#define ADC_CGR_GAIN0 (0x3 << 0) /**< \brief (ADC_CGR) Gain for channel 0 */ +#define ADC_CGR_GAIN1 (0x3 << 2) /**< \brief (ADC_CGR) Gain for channel 1 */ +#define ADC_CGR_GAIN2 (0x3 << 4) /**< \brief (ADC_CGR) Gain for channel 2 */ +#define ADC_CGR_GAIN3 (0x3 << 6) /**< \brief (ADC_CGR) Gain for channel 3 */ +#define ADC_CGR_GAIN4 (0x3 << 8) /**< \brief (ADC_CGR) Gain for channel 4 */ +#define ADC_CGR_GAIN5 (0x3 << 10) /**< \brief (ADC_CGR) Gain for channel 5 */ +#define ADC_CGR_GAIN6 (0x3 << 12) /**< \brief (ADC_CGR) Gain for channel 6 */ +#define ADC_CGR_GAIN7 (0x3 << 14) /**< \brief (ADC_CGR) Gain for channel 7 */ +#define ADC_CGR_GAIN8 (0x3 << 16) /**< \brief (ADC_CGR) Gain for channel 8 */ +#define ADC_CGR_GAIN9 (0x3 << 18) /**< \brief (ADC_CGR) Gain for channel 9 */ +#define ADC_CGR_GAIN10 (0x3 << 20) /**< \brief (ADC_CGR) Gain for channel 10 */ +#define ADC_CGR_GAIN11 (0x3 << 22) /**< \brief (ADC_CGR) Gain for channel 11 */ +#define ADC_CGR_GAIN12 (0x3 << 24) /**< \brief (ADC_CGR) Gain for channel 12 */ +#define ADC_CGR_GAIN13 (0x3 << 26) /**< \brief (ADC_CGR) Gain for channel 13 */ +#define ADC_CGR_GAIN14 (0x3 << 28) /**< \brief (ADC_CGR) Gain for channel 14 */ +#define ADC_CGR_GAIN15 (0x3 << 30) /**< \brief (ADC_CGR) Gain for channel 15 */ +/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */ +#define ADC_COR_OFF0 (0x1 << 0) /**< \brief (ADC_COR) Offset for channel 0 */ +#define ADC_COR_OFF1 (0x1 << 1) /**< \brief (ADC_COR) Offset for channel 1 */ +#define ADC_COR_OFF2 (0x1 << 2) /**< \brief (ADC_COR) Offset for channel 2 */ +#define ADC_COR_OFF3 (0x1 << 3) /**< \brief (ADC_COR) Offset for channel 3 */ +#define ADC_COR_OFF4 (0x1 << 4) /**< \brief (ADC_COR) Offset for channel 4 */ +#define ADC_COR_OFF5 (0x1 << 5) /**< \brief (ADC_COR) Offset for channel 5 */ +#define ADC_COR_OFF6 (0x1 << 6) /**< \brief (ADC_COR) Offset for channel 6 */ +#define ADC_COR_OFF7 (0x1 << 7) /**< \brief (ADC_COR) Offset for channel 7 */ +#define ADC_COR_OFF8 (0x1 << 8) /**< \brief (ADC_COR) Offset for channel 8 */ +#define ADC_COR_OFF9 (0x1 << 9) /**< \brief (ADC_COR) Offset for channel 9 */ +#define ADC_COR_OFF10 (0x1 << 10) /**< \brief (ADC_COR) Offset for channel 10 */ +#define ADC_COR_OFF11 (0x1 << 11) /**< \brief (ADC_COR) Offset for channel 11 */ +#define ADC_COR_OFF12 (0x1 << 12) /**< \brief (ADC_COR) Offset for channel 12 */ +#define ADC_COR_OFF13 (0x1 << 13) /**< \brief (ADC_COR) Offset for channel 13 */ +#define ADC_COR_OFF14 (0x1 << 14) /**< \brief (ADC_COR) Offset for channel 14 */ +#define ADC_COR_OFF15 (0x1 << 15) /**< \brief (ADC_COR) Offset for channel 15 */ +#define ADC_COR_DIFF0 (0x1 << 16) /**< \brief (ADC_COR) Differential inputs for channel 0 */ +#define ADC_COR_DIFF1 (0x1 << 17) /**< \brief (ADC_COR) Differential inputs for channel 1 */ +#define ADC_COR_DIFF2 (0x1 << 18) /**< \brief (ADC_COR) Differential inputs for channel 2 */ +#define ADC_COR_DIFF3 (0x1 << 19) /**< \brief (ADC_COR) Differential inputs for channel 3 */ +#define ADC_COR_DIFF4 (0x1 << 20) /**< \brief (ADC_COR) Differential inputs for channel 4 */ +#define ADC_COR_DIFF5 (0x1 << 21) /**< \brief (ADC_COR) Differential inputs for channel 5 */ +#define ADC_COR_DIFF6 (0x1 << 22) /**< \brief (ADC_COR) Differential inputs for channel 6 */ +#define ADC_COR_DIFF7 (0x1 << 23) /**< \brief (ADC_COR) Differential inputs for channel 7 */ +#define ADC_COR_DIFF8 (0x1 << 24) /**< \brief (ADC_COR) Differential inputs for channel 8 */ +#define ADC_COR_DIFF9 (0x1 << 25) /**< \brief (ADC_COR) Differential inputs for channel 9 */ +#define ADC_COR_DIFF10 (0x1 << 26) /**< \brief (ADC_COR) Differential inputs for channel 10 */ +#define ADC_COR_DIFF11 (0x1 << 27) /**< \brief (ADC_COR) Differential inputs for channel 11 */ +#define ADC_COR_DIFF12 (0x1 << 28) /**< \brief (ADC_COR) Differential inputs for channel 12 */ +#define ADC_COR_DIFF13 (0x1 << 29) /**< \brief (ADC_COR) Differential inputs for channel 13 */ +#define ADC_COR_DIFF14 (0x1 << 30) /**< \brief (ADC_COR) Differential inputs for channel 14 */ +#define ADC_COR_DIFF15 (0x1 << 31) /**< \brief (ADC_COR) Differential inputs for channel 15 */ +/* -------- ADC_CDR0 : (ADC Offset: 0x50) Channel Data Register 0 -------- */ +#define ADC_CDR0_DATA (0x3ff << 0) /**< \brief (ADC_CDR0) Converted Data */ +/* -------- ADC_CDR1 : (ADC Offset: 0x54) Channel Data Register 1 -------- */ +#define ADC_CDR1_DATA (0x3ff << 0) /**< \brief (ADC_CDR1) Converted Data */ +/* -------- ADC_CDR2 : (ADC Offset: 0x58) Channel Data Register 2 -------- */ +#define ADC_CDR2_DATA (0x3ff << 0) /**< \brief (ADC_CDR2) Converted Data */ +/* -------- ADC_CDR3 : (ADC Offset: 0x5C) Channel Data Register 3 -------- */ +#define ADC_CDR3_DATA (0x3ff << 0) /**< \brief (ADC_CDR3) Converted Data */ +/* -------- ADC_CDR4 : (ADC Offset: 0x60) Channel Data Register 4 -------- */ +#define ADC_CDR4_DATA (0x3ff << 0) /**< \brief (ADC_CDR4) Converted Data */ +/* -------- ADC_CDR5 : (ADC Offset: 0x64) Channel Data Register 5 -------- */ +#define ADC_CDR5_DATA (0x3ff << 0) /**< \brief (ADC_CDR5) Converted Data */ +/* -------- ADC_CDR6 : (ADC Offset: 0x68) Channel Data Register 6 -------- */ +#define ADC_CDR6_DATA (0x3ff << 0) /**< \brief (ADC_CDR6) Converted Data */ +/* -------- ADC_CDR15 : (ADC Offset: 0x6C) Channel Data Register 15 -------- */ +#define ADC_CDR15_DATA (0x3ff << 0) /**< \brief (ADC_CDR15) Converted Data */ +/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */ +#define ADC_ACR_TSON (0x1 << 4) /**< \brief (ADC_ACR) Temperature Sensor On */ +#define ADC_ACR_IBCTL (0x3 << 8) /**< \brief (ADC_ACR) ADC Bias Current Control */ +/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */ +#define ADC_WPMR_WPEN (0x1 << 0) /**< \brief (ADC_WPMR) Write Protect Enable */ +#define ADC_WPMR_WPKEY (0xffffff << 8) /**< \brief (ADC_WPMR) Write Protect KEY */ +/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */ +#define ADC_WPSR_WPVS (0x1 << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */ +#define ADC_WPSR_WPVSRC (0xffff << 8) /**< \brief (ADC_WPSR) Write Protect Violation Source */ +/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */ +#define ADC_RPR_RXPTR (0xffffffff << 0) /**< \brief (ADC_RPR) Receive Pointer Register */ +/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */ +#define ADC_RCR_RXCTR (0xffff << 0) /**< \brief (ADC_RCR) Receive Counter Register */ +/* -------- ADC_TPR : (ADC Offset: 0x108) Transmit Pointer Register -------- */ +#define ADC_TPR_TXPTR (0xffffffff << 0) /**< \brief (ADC_TPR) Transmit Counter Register */ +/* -------- ADC_TCR : (ADC Offset: 0x10C) Transmit Counter Register -------- */ +#define ADC_TCR_TXCTR (0xffff << 0) /**< \brief (ADC_TCR) Transmit Counter Register */ +/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */ +#define ADC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (ADC_RNPR) Receive Next Pointer */ +/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */ +#define ADC_RNCR_RXNCTR (0xffff << 0) /**< \brief (ADC_RNCR) Receive Next Counter */ +/* -------- ADC_TNPR : (ADC Offset: 0x118) Transmit Next Pointer Register -------- */ +#define ADC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (ADC_TNPR) Transmit Next Pointer */ +/* -------- ADC_TNCR : (ADC Offset: 0x11C) Transmit Next Counter Register -------- */ +#define ADC_TNCR_TXNCTR (0xffff << 0) /**< \brief (ADC_TNCR) Transmit Counter Next */ +/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */ +#define ADC_PTCR_RXTEN (0x1 << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */ +#define ADC_PTCR_RXTDIS (0x1 << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */ +#define ADC_PTCR_TXTEN (0x1 << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */ +#define ADC_PTCR_TXTDIS (0x1 << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */ +/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */ +#define ADC_PTSR_RXTEN (0x1 << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */ +#define ADC_PTSR_TXTEN (0x1 << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Chip Identifier */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_CHIPID Chip Identifier */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Chipid hardware registers */ +typedef struct { + RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */ + RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */ +} Chipid; +#endif /* __ASSEMBLY__ */ +/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */ +#define CHIPID_CIDR_VERSION (0x1f << 0) /**< \brief (CHIPID_CIDR) Version of the Device */ +#define CHIPID_CIDR_EPROC (0x7 << 5) /**< \brief (CHIPID_CIDR) Embedded Processor */ +#define CHIPID_CIDR_NVPSIZ (0xf << 8) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ2 (0xf << 12) /**< \brief (CHIPID_CIDR) */ +#define CHIPID_CIDR_SRAMSIZ (0xf << 16) /**< \brief (CHIPID_CIDR) Internal SRAM Size */ +#define CHIPID_CIDR_ARCH (0xff << 20) /**< \brief (CHIPID_CIDR) Architecture Identifier */ +#define CHIPID_CIDR_NVPTYP (0x7 << 28) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */ +#define CHIPID_CIDR_EXT (0x1 << 31) /**< \brief (CHIPID_CIDR) Extension Flag */ +/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */ +#define CHIPID_EXID_EXID (0xffffffff << 0) /**< \brief (CHIPID_EXID) Chip ID Extension */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Cyclic Redundancy Check Calculation Unit */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_CRCCU Cyclic Redundancy Check Calculation Unit */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Crccu hardware registers */ +typedef struct { + RwReg CRCCU_DSCR; /**< \brief (Crccu Offset: 0x00000000) CRCCU Descriptor Base Register */ + RwReg Reserved1[1]; + WoReg CRCCU_DMA_EN; /**< \brief (Crccu Offset: 0x00000008) CRCCU DMA Enable Register */ + WoReg CRCCU_DMA_DIS; /**< \brief (Crccu Offset: 0x0000000C) CRCCU DMA Disable Register */ + RoReg CRCCU_DMA_SR; /**< \brief (Crccu Offset: 0x00000010) CRCCU DMA Status Register */ + WoReg CRCCU_DMA_IER; /**< \brief (Crccu Offset: 0x00000014) CRCCU DMA Interrupt Enable Register */ + WoReg CRCCU_DMA_IDR; /**< \brief (Crccu Offset: 0x00000018) CRCCU DMA Interrupt Disable Register */ + RoReg CRCCU_DMA_IMR; /**< \brief (Crccu Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register */ + RoReg CRCCU_DMA_ISR; /**< \brief (Crccu Offset: 0x00000020) CRCCU DMA Interrupt Status Register */ + RwReg Reserved2[4]; + WoReg CRCCU_CR; /**< \brief (Crccu Offset: 0x00000034) CRCCU Control Register */ + RwReg CRCCU_MR; /**< \brief (Crccu Offset: 0x00000038) CRCCU Mode Register */ + RoReg CRCCU_SR; /**< \brief (Crccu Offset: 0x0000003C) CRCCU Status Register */ + WoReg CRCCU_IER; /**< \brief (Crccu Offset: 0x00000040) CRCCU Interrupt Enable Register */ + WoReg CRCCU_IDR; /**< \brief (Crccu Offset: 0x00000044) CRCCU Interrupt Disable Register */ + RoReg CRCCU_IMR; /**< \brief (Crccu Offset: 0x00000048) CRCCU Interrupt Mask Register */ + RoReg CRCCU_ISR; /**< \brief (Crccu Offset: 0x0000004C) CRCCU Interrupt Status Register */ +} Crccu; +#endif /* __ASSEMBLY__ */ +/* -------- CRCCU_DSCR : (CRCCU Offset: 0x00000000) CRCCU Descriptor Base Register -------- */ +#define CRCCU_DSCR_DSCR (0x7fffff << 9) /**< \brief (CRCCU_DSCR) Descriptor Base Address */ +/* -------- CRCCU_DMA_EN : (CRCCU Offset: 0x00000008) CRCCU DMA Enable Register -------- */ +#define CRCCU_DMA_EN_DMAEN (0x1 << 0) /**< \brief (CRCCU_DMA_EN) DMA Enable Register */ +/* -------- CRCCU_DMA_DIS : (CRCCU Offset: 0x0000000C) CRCCU DMA Disable Register -------- */ +#define CRCCU_DMA_DIS_DMADIS (0x1 << 0) /**< \brief (CRCCU_DMA_DIS) DMA Disable Register */ +/* -------- CRCCU_DMA_SR : (CRCCU Offset: 0x00000010) CRCCU DMA Status Register -------- */ +#define CRCCU_DMA_SR_DMASR (0x1 << 0) /**< \brief (CRCCU_DMA_SR) DMA Status Register */ +/* -------- CRCCU_DMA_IER : (CRCCU Offset: 0x00000014) CRCCU DMA Interrupt Enable Register -------- */ +#define CRCCU_DMA_IER_DMAIER (0x1 << 0) /**< \brief (CRCCU_DMA_IER) Interrupt Enable register */ +/* -------- CRCCU_DMA_IDR : (CRCCU Offset: 0x00000018) CRCCU DMA Interrupt Disable Register -------- */ +#define CRCCU_DMA_IDR_DMAIDR (0x1 << 0) /**< \brief (CRCCU_DMA_IDR) Interrupt Disable register */ +/* -------- CRCCU_DMA_IMR : (CRCCU Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register -------- */ +#define CRCCU_DMA_IMR_DMAIMR (0x1 << 0) /**< \brief (CRCCU_DMA_IMR) Interrupt Mask Register */ +/* -------- CRCCU_DMA_ISR : (CRCCU Offset: 0x00000020) CRCCU DMA Interrupt Status Register -------- */ +#define CRCCU_DMA_ISR_DMAISR (0x1 << 0) /**< \brief (CRCCU_DMA_ISR) Interrupt Status register */ +/* -------- CRCCU_CR : (CRCCU Offset: 0x00000034) CRCCU Control Register -------- */ +#define CRCCU_CR_RESET (0x1 << 0) /**< \brief (CRCCU_CR) CRC Computation Reset */ +/* -------- CRCCU_MR : (CRCCU Offset: 0x00000038) CRCCU Mode Register -------- */ +#define CRCCU_MR_ENABLE (0x1 << 0) /**< \brief (CRCCU_MR) CRC Enable */ +#define CRCCU_MR_COMPARE (0x1 << 1) /**< \brief (CRCCU_MR) CRC Compare */ +#define CRCCU_MR_PTYPE (0x3 << 2) /**< \brief (CRCCU_MR) Primitive Polynomial */ +#define CRCCU_MR_PTYPE_CCIT8023 (0x0 << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */ +#define CRCCU_MR_PTYPE_CASTAGNOLI (0x1 << 2) /**< \brief (CRCCU_MR) Polynom 0x1EDC6F41 */ +#define CRCCU_MR_PTYPE_CCIT16 (0x2 << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */ +#define CRCCU_MR_DIVIDER (0xf << 4) /**< \brief (CRCCU_MR) Request Divider */ +/* -------- CRCCU_SR : (CRCCU Offset: 0x0000003C) CRCCU Status Register -------- */ +#define CRCCU_SR_CRC (0xffffffff << 0) /**< \brief (CRCCU_SR) Cyclic Redundancy Check Value */ +/* -------- CRCCU_IER : (CRCCU Offset: 0x00000040) CRCCU Interrupt Enable Register -------- */ +#define CRCCU_IER_ERRIER (0x1 << 0) /**< \brief (CRCCU_IER) CRC Error Interrupt Enable */ +/* -------- CRCCU_IDR : (CRCCU Offset: 0x00000044) CRCCU Interrupt Disable Register -------- */ +#define CRCCU_IDR_ERRIDR (0x1 << 0) /**< \brief (CRCCU_IDR) CRC Error Interrupt Disable */ +/* -------- CRCCU_IMR : (CRCCU Offset: 0x00000048) CRCCU Interrupt Mask Register -------- */ +#define CRCCU_IMR_ERRIMR (0x1 << 0) /**< \brief (CRCCU_IMR) CRC Error Interrupt Mask */ +/* -------- CRCCU_ISR : (CRCCU Offset: 0x0000004C) CRCCU Interrupt Status Register -------- */ +#define CRCCU_ISR_ERRISR (0x1 << 0) /**< \brief (CRCCU_ISR) CRC Error Interrupt Status */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_DACC Digital-to-Analog Converter Controller */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Dacc hardware registers */ +typedef struct { + WoReg DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */ + RwReg DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */ + RwReg Reserved1[2]; + WoReg DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */ + WoReg DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */ + RoReg DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */ + RwReg Reserved2[1]; + WoReg DACC_CDR; /**< \brief (Dacc Offset: 0x20) Conversion Data Register */ + WoReg DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */ + WoReg DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */ + RoReg DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */ + RoReg DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */ + RwReg Reserved3[24]; + RwReg DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */ + RwReg Reserved4[19]; + RwReg DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protect Mode register */ + RoReg DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protect Status register */ + RwReg Reserved5[5]; + RwReg DACC_RPR; /**< \brief (Dacc Offset: 0x100) Receive Pointer Register */ + RwReg DACC_RCR; /**< \brief (Dacc Offset: 0x104) Receive Counter Register */ + RwReg DACC_TPR; /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */ + RwReg DACC_TCR; /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */ + RwReg DACC_RNPR; /**< \brief (Dacc Offset: 0x110) Receive Next Pointer Register */ + RwReg DACC_RNCR; /**< \brief (Dacc Offset: 0x114) Receive Next Counter Register */ + RwReg DACC_TNPR; /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */ + RwReg DACC_TNCR; /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */ + WoReg DACC_PTCR; /**< \brief (Dacc Offset: 0x120) Transfer Control Register */ + RoReg DACC_PTSR; /**< \brief (Dacc Offset: 0x124) Transfer Status Register */ +} Dacc; +#endif /* __ASSEMBLY__ */ +/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */ +#define DACC_CR_SWRST (0x1 << 0) /**< \brief (DACC_CR) Software Reset */ +/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */ +#define DACC_MR_TRGEN (0x1 << 0) /**< \brief (DACC_MR) Trigger Enable */ +#define DACC_MR_TRGEN_DIS (0x0 << 0) // (DACC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. +#define DACC_MR_TRGEN_EN (0x1 << 0) // (DACC_MR) Hardware trigger selected by TRGSEL field is enabled. + +#define DACC_MR_TRGSEL (0x7 << 1) /**< \brief (DACC_MR) Trigger Selection */ +#define DACC_MR_TRGSEL_EXT_TRIG (0x0 << 1) // (DACC_MR) External trigger +#define DACC_MR_TRGSEL_TIOA_0 (0x1 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 0 +#define DACC_MR_TRGSEL_TIOA_1 (0x2 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 1 +#define DACC_MR_TRGSEL_TIOA_2 (0x3 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 2 +#define DACC_MR_TRGSEL_PWM_0 (0x4 << 1) // (DACC_MR) PWM Event Line 0 +#define DACC_MR_TRGSEL_PWM_1 (0x5 << 1) // (DACC_MR) PWM Event Line 1 +#define DACC_MR_WORD (0x1 << 4) /**< \brief (DACC_MR) Word Transfer */ +#define DACC_MR_WORD_HALF (0x0 << 4) /**< \brief (DACC_MR) Half-Word Transfer */ +#define DACC_MR_WORD_WORLD (0x1 << 4) /**< \brief (DACC_MR) Word Transfer */ +#define DACC_MR_SLEEP (0x1 << 5) /**< \brief (DACC_MR) Sleep Mode */ +#define DACC_MR_SLEEP_NORMAL (0x0 << 5) // (DACC_MR) Normal Mode +#define DACC_MR_SLEEP_SLEEP (0x1 << 5) // (DACC_MR) Sleep Modes +#define DACC_MR_FASTWKUP (0x1 << 6) /**< \brief (DACC_MR) Fast Wake up Mode */ +#define DACC_MR_REFRESH (0xff << 8) /**< \brief (DACC_MR) Refresh Period */ +#define DACC_MR_USER_SEL (0x3 << 16) /**< \brief (DACC_MR) User Channel Selection */ +#define DACC_MR_USER_SEL_0 (0x0 << 16) /**< \brief (DACC_MR) User Channel Selection */ +#define DACC_MR_USER_SEL_1 (0x1 << 16) /**< \brief (DACC_MR) User Channel Selection */ +#define DACC_MR_TAG (0x1 << 20) /**< \brief (DACC_MR) Tag Selection Mode */ +#define DACC_MR_MAXS (0x1 << 21) /**< \brief (DACC_MR) Max Speed Mode */ +#define DACC_MR_STARTUP (0x3f << 24) /**< \brief (DACC_MR) Startup Time Selection */ +/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */ +#define DACC_CHER_CH0 (0x1 << 0) /**< \brief (DACC_CHER) Channel 0 Enable */ +#define DACC_CHER_CH1 (0x1 << 1) /**< \brief (DACC_CHER) Channel 1 Enable */ +#define DACC_CHER_CH2 (0x1 << 2) /**< \brief (DACC_CHER) Channel 2 Enable */ +/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */ +#define DACC_CHDR_CH0 (0x1 << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */ +#define DACC_CHDR_CH1 (0x1 << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */ +#define DACC_CHDR_CH2 (0x1 << 2) /**< \brief (DACC_CHDR) Channel 2 Disable */ +/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */ +#define DACC_CHSR_CH0 (0x1 << 0) /**< \brief (DACC_CHSR) Channel 0 Status */ +#define DACC_CHSR_CH1 (0x1 << 1) /**< \brief (DACC_CHSR) Channel 1 Status */ +#define DACC_CHSR_CH2 (0x1 << 2) /**< \brief (DACC_CHSR) Channel 2 Status */ +/* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */ +#define DACC_CDR_DATA (0xffffffff << 0) /**< \brief (DACC_CDR) Data to Convert */ +/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */ +#define DACC_IER_TXRDY (0x1 << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */ +#define DACC_IER_EOC (0x1 << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */ +#define DACC_IER_ENDTX (0x1 << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */ +#define DACC_IER_TXBUFE (0x1 << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */ +/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */ +#define DACC_IDR_TXRDY (0x1 << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */ +#define DACC_IDR_EOC (0x1 << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */ +#define DACC_IDR_ENDTX (0x1 << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */ +#define DACC_IDR_TXBUFE (0x1 << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */ +/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define DACC_IMR_TXRDY (0x1 << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */ +#define DACC_IMR_EOC (0x1 << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */ +#define DACC_IMR_ENDTX (0x1 << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */ +#define DACC_IMR_TXBUFE (0x1 << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */ +/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */ +#define DACC_ISR_TXRDY (0x1 << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */ +#define DACC_ISR_EOC (0x1 << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */ +#define DACC_ISR_ENDTX (0x1 << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */ +#define DACC_ISR_TXBUFE (0x1 << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */ +/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */ +#define DACC_ACR_IBCTLCH0 (0x3 << 0) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLCH1 (0x3 << 2) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLDACCORE (0x3 << 8) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */ +/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */ +#define DACC_WPMR_WPEN (0x1 << 0) /**< \brief (DACC_WPMR) Write Protect Enable */ +#define DACC_WPMR_WPKEY (0xffffff << 8) /**< \brief (DACC_WPMR) Write Protect KEY */ +/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */ +#define DACC_WPSR_WPROTERR (0x1 << 0) /**< \brief (DACC_WPSR) Write protection error */ +#define DACC_WPSR_WPROTADDR (0xff << 8) /**< \brief (DACC_WPSR) Write protection error address */ +/* -------- DACC_RPR : (DACC Offset: 0x100) Receive Pointer Register -------- */ +#define DACC_RPR_RXPTR (0xffffffff << 0) /**< \brief (DACC_RPR) Receive Pointer Register */ +/* -------- DACC_RCR : (DACC Offset: 0x104) Receive Counter Register -------- */ +#define DACC_RCR_RXCTR (0xffff << 0) /**< \brief (DACC_RCR) Receive Counter Register */ +/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */ +#define DACC_TPR_TXPTR (0xffffffff << 0) /**< \brief (DACC_TPR) Transmit Counter Register */ +/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */ +#define DACC_TCR_TXCTR (0xffff << 0) /**< \brief (DACC_TCR) Transmit Counter Register */ +/* -------- DACC_RNPR : (DACC Offset: 0x110) Receive Next Pointer Register -------- */ +#define DACC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (DACC_RNPR) Receive Next Pointer */ +/* -------- DACC_RNCR : (DACC Offset: 0x114) Receive Next Counter Register -------- */ +#define DACC_RNCR_RXNCTR (0xffff << 0) /**< \brief (DACC_RNCR) Receive Next Counter */ +/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */ +#define DACC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (DACC_TNPR) Transmit Next Pointer */ +/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */ +#define DACC_TNCR_TXNCTR (0xffff << 0) /**< \brief (DACC_TNCR) Transmit Counter Next */ +/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */ +#define DACC_PTCR_RXTEN (0x1 << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */ +#define DACC_PTCR_RXTDIS (0x1 << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */ +#define DACC_PTCR_TXTEN (0x1 << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */ +#define DACC_PTCR_TXTDIS (0x1 << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */ +/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */ +#define DACC_PTSR_RXTEN (0x1 << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */ +#define DACC_PTSR_TXTEN (0x1 << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_EFC Embedded Flash Controller */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Efc hardware registers */ +typedef struct { + RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */ + WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */ + RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */ + RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */ +} Efc; +#endif /* __ASSEMBLY__ */ +/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */ +#define EEFC_FMR_FRDY (0x1 << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */ +#define EEFC_FMR_FWS (0xf << 8) /**< \brief (EEFC_FMR) Flash Wait State */ +#define EEFC_FMR_FAM (0x1 << 24) /**< \brief (EEFC_FMR) Flash Access Mode */ +/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */ +#define EEFC_FCR_FCMD (0xff << 0) /**< \brief (EEFC_FCR) Flash Command */ +#define EEFC_FCR_FARG (0xffff << 8) /**< \brief (EEFC_FCR) Flash Command Argument */ +#define EEFC_FCR_FKEY (0xff << 24) /**< \brief (EEFC_FCR) Flash Writing Protection Key */ +/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */ +#define EEFC_FSR_FRDY (0x1 << 0) /**< \brief (EEFC_FSR) Flash Ready Status */ +#define EEFC_FSR_FCMDE (0x1 << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */ +#define EEFC_FSR_FLOCKE (0x1 << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */ +/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */ +#define EEFC_FRR_FVALUE (0xffffffff << 0) /**< \brief (EEFC_FRR) Flash Result Value */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR General Purpose Backup Register */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_GPBR General Purpose Backup Register */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Gpbr hardware registers */ +typedef struct { + RwReg SYS_GPBR0; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register 0 */ + RwReg SYS_GPBR1; /**< \brief (Gpbr Offset: 0x4) General Purpose Backup Register 1 */ + RwReg SYS_GPBR2; /**< \brief (Gpbr Offset: 0x8) General Purpose Backup Register 2 */ + RwReg SYS_GPBR3; /**< \brief (Gpbr Offset: 0xC) General Purpose Backup Register 3 */ +} Gpbr; +#endif /* __ASSEMBLY__ */ +/* -------- SYS_GPBR0 : (GPBR Offset: 0x0) General Purpose Backup Register 0 -------- */ +#define SYS_GPBR0_GPBR_VALUE0 (0xffffffff << 0) /**< \brief (SYS_GPBR0) Value of GPBR x */ +/* -------- SYS_GPBR1 : (GPBR Offset: 0x4) General Purpose Backup Register 1 -------- */ +#define SYS_GPBR1_GPBR_VALUE1 (0xffffffff << 0) /**< \brief (SYS_GPBR1) Value of GPBR x */ +/* -------- SYS_GPBR2 : (GPBR Offset: 0x8) General Purpose Backup Register 2 -------- */ +#define SYS_GPBR2_GPBR_VALUE2 (0xffffffff << 0) /**< \brief (SYS_GPBR2) Value of GPBR x */ +/* -------- SYS_GPBR3 : (GPBR Offset: 0xC) General Purpose Backup Register 3 -------- */ +#define SYS_GPBR3_GPBR_VALUE3 (0xffffffff << 0) /**< \brief (SYS_GPBR3) Value of GPBR x */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_HSMCI High Speed MultiMedia Card Interface */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Hsmci hardware registers */ +typedef struct { + WoReg HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */ + RwReg HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */ + RwReg HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */ + RwReg HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */ + RwReg HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */ + WoReg HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */ + RwReg HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */ + RwReg HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */ + RoReg HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */ + RoReg HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */ + WoReg HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */ + RwReg Reserved1[2]; + RoReg HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */ + WoReg HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */ + WoReg HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */ + RoReg HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */ + RwReg Reserved2[1]; + RwReg HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */ + RwReg Reserved3[35]; + RwReg HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */ + RoReg HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */ + RwReg Reserved4[5]; + RwReg HSMCI_RPR; /**< \brief (Hsmci Offset: 0x100) Receive Pointer Register */ + RwReg HSMCI_RCR; /**< \brief (Hsmci Offset: 0x104) Receive Counter Register */ + RwReg HSMCI_TPR; /**< \brief (Hsmci Offset: 0x108) Transmit Pointer Register */ + RwReg HSMCI_TCR; /**< \brief (Hsmci Offset: 0x10C) Transmit Counter Register */ + RwReg HSMCI_RNPR; /**< \brief (Hsmci Offset: 0x110) Receive Next Pointer Register */ + RwReg HSMCI_RNCR; /**< \brief (Hsmci Offset: 0x114) Receive Next Counter Register */ + RwReg HSMCI_TNPR; /**< \brief (Hsmci Offset: 0x118) Transmit Next Pointer Register */ + RwReg HSMCI_TNCR; /**< \brief (Hsmci Offset: 0x11C) Transmit Next Counter Register */ + WoReg HSMCI_PTCR; /**< \brief (Hsmci Offset: 0x120) Transfer Control Register */ + RoReg HSMCI_PTSR; /**< \brief (Hsmci Offset: 0x124) Transfer Status Register */ +} Hsmci; +#endif /* __ASSEMBLY__ */ +/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */ +#define HSMCI_CR_MCIEN (0x1 << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */ +#define HSMCI_CR_MCIDIS (0x1 << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */ +#define HSMCI_CR_PWSEN (0x1 << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */ +#define HSMCI_CR_PWSDIS (0x1 << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */ +#define HSMCI_CR_SWRST (0x1 << 7) /**< \brief (HSMCI_CR) Software Reset */ +/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */ +#define HSMCI_MR_CLKDIV_Pos 0 +#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */ +#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos))) +#define HSMCI_MR_PWSDIV_Pos 8 +#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */ +#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos))) +#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) */ +#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) */ +#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ +#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */ +#define HSMCI_MR_PDCMODE (0x1u << 15) /**< \brief (HSMCI_MR) PDC-oriented Mode */ +#define HSMCI_MR_BLKLEN_Pos 16 +#define HSMCI_MR_BLKLEN_Msk (0xffffu << HSMCI_MR_BLKLEN_Pos) /**< \brief (HSMCI_MR) Data Block Length */ +#define HSMCI_MR_BLKLEN(value) ((HSMCI_MR_BLKLEN_Msk & ((value) << HSMCI_MR_BLKLEN_Pos))) +/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ +#define HSMCI_DTOR_DTOCYC_Pos 0 +#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ +#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos))) +#define HSMCI_DTOR_DTOMUL_Pos 4 +#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */ +#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */ +#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */ +#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */ +#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */ +#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */ +#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */ +#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */ +#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */ +/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */ +#define HSMCI_SDCR_SDCSEL_Pos 0 +#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */ +#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */ +#define HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) /**< \brief (HSMCI_SDCR) - */ +#define HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) /**< \brief (HSMCI_SDCR) - */ +#define HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) /**< \brief (HSMCI_SDCR) - */ +#define HSMCI_SDCR_SDCBUS_Pos 6 +#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */ +#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */ +#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */ +#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */ +/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */ +#define HSMCI_ARGR_ARG (0xffffffff << 0) /**< \brief (HSMCI_ARGR) Command Argument */ +/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */ +#define HSMCI_CMDR_CMDNB_Pos 0 +#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */ +#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos))) +#define HSMCI_CMDR_RSPTYP_Pos 6 +#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */ +#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */ +#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */ +#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */ +#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */ +#define HSMCI_CMDR_SPCMD_Pos 8 +#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */ +#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */ +#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD:74 clock cycles for initialization sequence. */ +#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD:Wait for the end of the current data block transfer before sending the pending command. */ +#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command.The host cancels the ability for the device to return a command completion signal on the command line. */ +#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command:Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response:Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request.Start a boot operation mode, the host processor can read boot data from the MMC device directly. */ +#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation.This command allows the host processor to terminate the boot operation mode. */ +#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */ +#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */ +#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */ +#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */ +#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */ +#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */ +#define HSMCI_CMDR_TRCMD_Pos 16 +#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */ +#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */ +#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */ +#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */ +#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */ +#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */ +#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */ +#define HSMCI_CMDR_TRTYP_Pos 19 +#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */ +#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Single Block */ +#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Multiple Block */ +#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */ +#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */ +#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */ +#define HSMCI_CMDR_IOSPCMD_Pos 24 +#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */ +#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */ +#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */ +#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */ +#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */ +#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */ +/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */ +#define HSMCI_BLKR_BCNT_Pos 0 +#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */ +#define HSMCI_BLKR_BCNT_MULTIPLE (0x0u << 0) /**< \brief (HSMCI_BLKR) MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. */ +#define HSMCI_BLKR_BCNT_BYTE (0x4u << 0) /**< \brief (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. */ +#define HSMCI_BLKR_BCNT_BLOCK (0x5u << 0) /**< \brief (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. */ +#define HSMCI_BLKR_BLKLEN_Pos 16 +#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */ +#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos))) +/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */ +#define HSMCI_CSTOR_CSTOCYC_Pos 0 +#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */ +#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos))) +#define HSMCI_CSTOR_CSTOMUL_Pos 4 +#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */ +#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */ +#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */ +#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */ +#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */ +#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */ +#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */ +#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */ +#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */ +/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */ +#define HSMCI_RSPR_RSP (0xffffffff << 0) /**< \brief (HSMCI_RSPR[4]) Response */ +/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */ +#define HSMCI_RDR_DATA (0xffffffff << 0) /**< \brief (HSMCI_RDR) Data to Read */ +/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */ +#define HSMCI_TDR_DATA (0xffffffff << 0) /**< \brief (HSMCI_TDR) Data to Write */ +/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */ +#define HSMCI_SR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_SR) Command Ready */ +#define HSMCI_SR_RXRDY (0x1 << 1) /**< \brief (HSMCI_SR) Receiver Ready */ +#define HSMCI_SR_TXRDY (0x1 << 2) /**< \brief (HSMCI_SR) Transmit Ready */ +#define HSMCI_SR_BLKE (0x1 << 3) /**< \brief (HSMCI_SR) Data Block Ended */ +#define HSMCI_SR_DTIP (0x1 << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */ +#define HSMCI_SR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */ +#define HSMCI_SR_ENDRX (0x1 << 6) /**< \brief (HSMCI_SR) End of RX Buffer */ +#define HSMCI_SR_ENDTX (0x1 << 7) /**< \brief (HSMCI_SR) End of TX Buffer */ +#define HSMCI_SR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A */ +#define HSMCI_SR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */ +#define HSMCI_SR_CSRCV (0x1 << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */ +#define HSMCI_SR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_SR) RX Buffer Full */ +#define HSMCI_SR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_SR) TX Buffer Empty */ +#define HSMCI_SR_RINDE (0x1 << 16) /**< \brief (HSMCI_SR) Response Index Error */ +#define HSMCI_SR_RDIRE (0x1 << 17) /**< \brief (HSMCI_SR) Response Direction Error */ +#define HSMCI_SR_RCRCE (0x1 << 18) /**< \brief (HSMCI_SR) Response CRC Error */ +#define HSMCI_SR_RENDE (0x1 << 19) /**< \brief (HSMCI_SR) Response End Bit Error */ +#define HSMCI_SR_RTOE (0x1 << 20) /**< \brief (HSMCI_SR) Response Time-out Error */ +#define HSMCI_SR_DCRCE (0x1 << 21) /**< \brief (HSMCI_SR) Data CRC Error */ +#define HSMCI_SR_DTOE (0x1 << 22) /**< \brief (HSMCI_SR) Data Time-out Error */ +#define HSMCI_SR_CSTOE (0x1 << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */ +#define HSMCI_SR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_SR) FIFO empty flag */ +#define HSMCI_SR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_SR) Transfer Done flag */ +#define HSMCI_SR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */ +#define HSMCI_SR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */ +#define HSMCI_SR_OVRE (0x1 << 30) /**< \brief (HSMCI_SR) Overrun */ +#define HSMCI_SR_UNRE (0x1 << 31) /**< \brief (HSMCI_SR) Underrun */ +/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */ +#define HSMCI_IER_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */ +#define HSMCI_IER_RXRDY (0x1 << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */ +#define HSMCI_IER_TXRDY (0x1 << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */ +#define HSMCI_IER_BLKE (0x1 << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */ +#define HSMCI_IER_DTIP (0x1 << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */ +#define HSMCI_IER_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */ +#define HSMCI_IER_ENDRX (0x1 << 6) /**< \brief (HSMCI_IER) End of Receive Buffer Interrupt Enable */ +#define HSMCI_IER_ENDTX (0x1 << 7) /**< \brief (HSMCI_IER) End of Transmit Buffer Interrupt Enable */ +#define HSMCI_IER_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */ +#define HSMCI_IER_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */ +#define HSMCI_IER_CSRCV (0x1 << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */ +#define HSMCI_IER_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IER) Receive Buffer Full Interrupt Enable */ +#define HSMCI_IER_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IER) Transmit Buffer Empty Interrupt Enable */ +#define HSMCI_IER_RINDE (0x1 << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */ +#define HSMCI_IER_RDIRE (0x1 << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */ +#define HSMCI_IER_RCRCE (0x1 << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */ +#define HSMCI_IER_RENDE (0x1 << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */ +#define HSMCI_IER_RTOE (0x1 << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */ +#define HSMCI_IER_DCRCE (0x1 << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */ +#define HSMCI_IER_DTOE (0x1 << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */ +#define HSMCI_IER_CSTOE (0x1 << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */ +#define HSMCI_IER_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */ +#define HSMCI_IER_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */ +#define HSMCI_IER_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */ +#define HSMCI_IER_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */ +#define HSMCI_IER_OVRE (0x1 << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */ +#define HSMCI_IER_UNRE (0x1 << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */ +/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */ +#define HSMCI_IDR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */ +#define HSMCI_IDR_RXRDY (0x1 << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */ +#define HSMCI_IDR_TXRDY (0x1 << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */ +#define HSMCI_IDR_BLKE (0x1 << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */ +#define HSMCI_IDR_DTIP (0x1 << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */ +#define HSMCI_IDR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */ +#define HSMCI_IDR_ENDRX (0x1 << 6) /**< \brief (HSMCI_IDR) End of Receive Buffer Interrupt Disable */ +#define HSMCI_IDR_ENDTX (0x1 << 7) /**< \brief (HSMCI_IDR) End of Transmit Buffer Interrupt Disable */ +#define HSMCI_IDR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */ +#define HSMCI_IDR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */ +#define HSMCI_IDR_CSRCV (0x1 << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */ +#define HSMCI_IDR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IDR) Receive Buffer Full Interrupt Disable */ +#define HSMCI_IDR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IDR) Transmit Buffer Empty Interrupt Disable */ +#define HSMCI_IDR_RINDE (0x1 << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */ +#define HSMCI_IDR_RDIRE (0x1 << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */ +#define HSMCI_IDR_RCRCE (0x1 << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */ +#define HSMCI_IDR_RENDE (0x1 << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */ +#define HSMCI_IDR_RTOE (0x1 << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */ +#define HSMCI_IDR_DCRCE (0x1 << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */ +#define HSMCI_IDR_DTOE (0x1 << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */ +#define HSMCI_IDR_CSTOE (0x1 << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */ +#define HSMCI_IDR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */ +#define HSMCI_IDR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */ +#define HSMCI_IDR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */ +#define HSMCI_IDR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */ +#define HSMCI_IDR_OVRE (0x1 << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */ +#define HSMCI_IDR_UNRE (0x1 << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */ +/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */ +#define HSMCI_IMR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */ +#define HSMCI_IMR_RXRDY (0x1 << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */ +#define HSMCI_IMR_TXRDY (0x1 << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */ +#define HSMCI_IMR_BLKE (0x1 << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */ +#define HSMCI_IMR_DTIP (0x1 << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */ +#define HSMCI_IMR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */ +#define HSMCI_IMR_ENDRX (0x1 << 6) /**< \brief (HSMCI_IMR) End of Receive Buffer Interrupt Mask */ +#define HSMCI_IMR_ENDTX (0x1 << 7) /**< \brief (HSMCI_IMR) End of Transmit Buffer Interrupt Mask */ +#define HSMCI_IMR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */ +#define HSMCI_IMR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */ +#define HSMCI_IMR_CSRCV (0x1 << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */ +#define HSMCI_IMR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IMR) Receive Buffer Full Interrupt Mask */ +#define HSMCI_IMR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IMR) Transmit Buffer Empty Interrupt Mask */ +#define HSMCI_IMR_RINDE (0x1 << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */ +#define HSMCI_IMR_RDIRE (0x1 << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */ +#define HSMCI_IMR_RCRCE (0x1 << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */ +#define HSMCI_IMR_RENDE (0x1 << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */ +#define HSMCI_IMR_RTOE (0x1 << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */ +#define HSMCI_IMR_DCRCE (0x1 << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */ +#define HSMCI_IMR_DTOE (0x1 << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */ +#define HSMCI_IMR_CSTOE (0x1 << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */ +#define HSMCI_IMR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */ +#define HSMCI_IMR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */ +#define HSMCI_IMR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */ +#define HSMCI_IMR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */ +#define HSMCI_IMR_OVRE (0x1 << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */ +#define HSMCI_IMR_UNRE (0x1 << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */ +/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */ +#define HSMCI_CFG_FIFOMODE (0x1 << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */ +#define HSMCI_CFG_FERRCTRL (0x1 << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */ +#define HSMCI_CFG_HSMODE (0x1 << 8) /**< \brief (HSMCI_CFG) High Speed Mode */ +#define HSMCI_CFG_LSYNC (0x1 << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */ +/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */ +#define HSMCI_WPMR_WP_EN (0x1 << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */ +#define HSMCI_WPMR_WP_KEY (0xffffff << 8) /**< \brief (HSMCI_WPMR) Write Protection Key password */ +/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */ +#define HSMCI_WPSR_WP_VS (0xf << 0) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */ +#define HSMCI_WPSR_WP_VSRC (0xffff << 8) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */ +/* -------- HSMCI_RPR : (HSMCI Offset: 0x100) Receive Pointer Register -------- */ +#define HSMCI_RPR_RXPTR (0xffffffff << 0) /**< \brief (HSMCI_RPR) Receive Pointer Register */ +/* -------- HSMCI_RCR : (HSMCI Offset: 0x104) Receive Counter Register -------- */ +#define HSMCI_RCR_RXCTR (0xffff << 0) /**< \brief (HSMCI_RCR) Receive Counter Register */ +/* -------- HSMCI_TPR : (HSMCI Offset: 0x108) Transmit Pointer Register -------- */ +#define HSMCI_TPR_TXPTR (0xffffffff << 0) /**< \brief (HSMCI_TPR) Transmit Counter Register */ +/* -------- HSMCI_TCR : (HSMCI Offset: 0x10C) Transmit Counter Register -------- */ +#define HSMCI_TCR_TXCTR (0xffff << 0) /**< \brief (HSMCI_TCR) Transmit Counter Register */ +/* -------- HSMCI_RNPR : (HSMCI Offset: 0x110) Receive Next Pointer Register -------- */ +#define HSMCI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (HSMCI_RNPR) Receive Next Pointer */ +/* -------- HSMCI_RNCR : (HSMCI Offset: 0x114) Receive Next Counter Register -------- */ +#define HSMCI_RNCR_RXNCTR (0xffff << 0) /**< \brief (HSMCI_RNCR) Receive Next Counter */ +/* -------- HSMCI_TNPR : (HSMCI Offset: 0x118) Transmit Next Pointer Register -------- */ +#define HSMCI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (HSMCI_TNPR) Transmit Next Pointer */ +/* -------- HSMCI_TNCR : (HSMCI Offset: 0x11C) Transmit Next Counter Register -------- */ +#define HSMCI_TNCR_TXNCTR (0xffff << 0) /**< \brief (HSMCI_TNCR) Transmit Counter Next */ +/* -------- HSMCI_PTCR : (HSMCI Offset: 0x120) Transfer Control Register -------- */ +#define HSMCI_PTCR_RXTEN (0x1 << 0) /**< \brief (HSMCI_PTCR) Receiver Transfer Enable */ +#define HSMCI_PTCR_RXTDIS (0x1 << 1) /**< \brief (HSMCI_PTCR) Receiver Transfer Disable */ +#define HSMCI_PTCR_TXTEN (0x1 << 8) /**< \brief (HSMCI_PTCR) Transmitter Transfer Enable */ +#define HSMCI_PTCR_TXTDIS (0x1 << 9) /**< \brief (HSMCI_PTCR) Transmitter Transfer Disable */ +/* -------- HSMCI_PTSR : (HSMCI Offset: 0x124) Transfer Status Register -------- */ +#define HSMCI_PTSR_RXTEN (0x1 << 0) /**< \brief (HSMCI_PTSR) Receiver Transfer Enable */ +#define HSMCI_PTSR_TXTEN (0x1 << 8) /**< \brief (HSMCI_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_MATRIX AHB Bus Matrix */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Matrix hardware registers */ +typedef struct { + RwReg MATRIX_MCFG[4]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */ + RwReg Reserved1[12]; + RwReg MATRIX_SCFG[5]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */ + RwReg Reserved2[11]; + RwReg MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */ + RwReg Reserved3[1]; + RwReg MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */ + RwReg Reserved4[1]; + RwReg MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */ + RwReg Reserved5[1]; + RwReg MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */ + RwReg Reserved6[1]; + RwReg MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */ + RwReg Reserved7[28]; + RwReg CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System IO Configuration register */ + RwReg Reserved8[1]; + RwReg CCFG_SMCNFCS; /**< \brief (Matrix Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register */ + RwReg Reserved9[49]; + RwReg MATRIX_WPMR; /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */ + RoReg MATRIX_WPSR; /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */ +} Matrix; +#endif /* __ASSEMBLY__ */ +/* -------- MATRIX_MCFG[4] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */ +#define MATRIX_MCFG_ULBT (0x7 << 0) /**< \brief (MATRIX_MCFG[4]) Undefined Length Burst Type */ +/* -------- MATRIX_SCFG[5] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ +#define MATRIX_SCFG_SLOT_CYCLE (0xff << 0) /**< \brief (MATRIX_SCFG[5]) Maximum Number of Allowed Cycles for a Burst */ +#define MATRIX_SCFG_DEFMSTR_TYPE (0x3 << 16) /**< \brief (MATRIX_SCFG[5]) Default Master Type */ +#define MATRIX_SCFG_FIXED_DEFMSTR (0x7 << 18) /**< \brief (MATRIX_SCFG[5]) Fixed Default Master */ +#define MATRIX_SCFG_ARBT (0x3 << 24) /**< \brief (MATRIX_SCFG[5]) Arbitration Type */ +/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */ +#define MATRIX_PRAS0_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS0) Master 0 Priority */ +#define MATRIX_PRAS0_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS0) Master 1 Priority */ +#define MATRIX_PRAS0_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS0) Master 2 Priority */ +#define MATRIX_PRAS0_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS0) Master 3 Priority */ +#define MATRIX_PRAS0_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS0) Master 4 Priority */ +/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */ +#define MATRIX_PRAS1_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS1) Master 0 Priority */ +#define MATRIX_PRAS1_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS1) Master 1 Priority */ +#define MATRIX_PRAS1_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS1) Master 2 Priority */ +#define MATRIX_PRAS1_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS1) Master 3 Priority */ +#define MATRIX_PRAS1_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS1) Master 4 Priority */ +/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */ +#define MATRIX_PRAS2_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS2) Master 0 Priority */ +#define MATRIX_PRAS2_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS2) Master 1 Priority */ +#define MATRIX_PRAS2_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS2) Master 2 Priority */ +#define MATRIX_PRAS2_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS2) Master 3 Priority */ +#define MATRIX_PRAS2_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS2) Master 4 Priority */ +/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */ +#define MATRIX_PRAS3_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS3) Master 0 Priority */ +#define MATRIX_PRAS3_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS3) Master 1 Priority */ +#define MATRIX_PRAS3_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS3) Master 2 Priority */ +#define MATRIX_PRAS3_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS3) Master 3 Priority */ +#define MATRIX_PRAS3_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS3) Master 4 Priority */ +/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */ +#define MATRIX_PRAS4_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS4) Master 0 Priority */ +#define MATRIX_PRAS4_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS4) Master 1 Priority */ +#define MATRIX_PRAS4_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS4) Master 2 Priority */ +#define MATRIX_PRAS4_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS4) Master 3 Priority */ +#define MATRIX_PRAS4_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS4) Master 4 Priority */ +/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System IO Configuration register -------- */ +#define CCFG_SYSIO_SYSIO4 (0x1 << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */ +#define CCFG_SYSIO_SYSIO5 (0x1 << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */ +#define CCFG_SYSIO_SYSIO6 (0x1 << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */ +#define CCFG_SYSIO_SYSIO7 (0x1 << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */ +#define CCFG_SYSIO_SYSIO10 (0x1 << 10) /**< \brief (CCFG_SYSIO) PB10 or DDM Assignment */ +#define CCFG_SYSIO_SYSIO11 (0x1 << 11) /**< \brief (CCFG_SYSIO) PB11 or DDP Assignment */ +#define CCFG_SYSIO_SYSIO12 (0x1 << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */ +/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register -------- */ +#define CCFG_SMCNFCS_SMC_NFCS0 (0x1 << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS1 (0x1 << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS2 (0x1 << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS3 (0x1 << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */ +/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */ +#define MATRIX_WPMR_WPEN (0x1 << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */ +#define MATRIX_WPMR_WPKEY (0xffffff << 8) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */ +/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */ +#define MATRIX_WPSR_WPVS (0x1 << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */ +#define MATRIX_WPSR_WPVSRC (0xffff << 8) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_PDC Peripheral DMA Controller */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Pdc hardware registers */ +typedef struct { + RwReg Reserved1[64]; + RwReg PERIPH_RPR; /**< \brief (Pdc Offset: 0x100) Receive Pointer Register */ + RwReg PERIPH_RCR; /**< \brief (Pdc Offset: 0x104) Receive Counter Register */ + RwReg PERIPH_TPR; /**< \brief (Pdc Offset: 0x108) Transmit Pointer Register */ + RwReg PERIPH_TCR; /**< \brief (Pdc Offset: 0x10C) Transmit Counter Register */ + RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x110) Receive Next Pointer Register */ + RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x114) Receive Next Counter Register */ + RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x118) Transmit Next Pointer Register */ + RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x11C) Transmit Next Counter Register */ + WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x120) Transfer Control Register */ + RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x124) Transfer Status Register */ +} Pdc; +#endif /* __ASSEMBLY__ */ +/* -------- PERIPH_RPR : (PDC Offset: 0x100) Receive Pointer Register -------- */ +#define PERIPH_RPR_RXPTR (0xffffffff << 0) /**< \brief (PERIPH_RPR) Receive Pointer Register */ +/* -------- PERIPH_RCR : (PDC Offset: 0x104) Receive Counter Register -------- */ +#define PERIPH_RCR_RXCTR (0xffff << 0) /**< \brief (PERIPH_RCR) Receive Counter Register */ +/* -------- PERIPH_TPR : (PDC Offset: 0x108) Transmit Pointer Register -------- */ +#define PERIPH_TPR_TXPTR (0xffffffff << 0) /**< \brief (PERIPH_TPR) Transmit Counter Register */ +/* -------- PERIPH_TCR : (PDC Offset: 0x10C) Transmit Counter Register -------- */ +#define PERIPH_TCR_TXCTR (0xffff << 0) /**< \brief (PERIPH_TCR) Transmit Counter Register */ +/* -------- PERIPH_RNPR : (PDC Offset: 0x110) Receive Next Pointer Register -------- */ +#define PERIPH_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (PERIPH_RNPR) Receive Next Pointer */ +/* -------- PERIPH_RNCR : (PDC Offset: 0x114) Receive Next Counter Register -------- */ +#define PERIPH_RNCR_RXNCTR (0xffff << 0) /**< \brief (PERIPH_RNCR) Receive Next Counter */ +/* -------- PERIPH_TNPR : (PDC Offset: 0x118) Transmit Next Pointer Register -------- */ +#define PERIPH_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */ +/* -------- PERIPH_TNCR : (PDC Offset: 0x11C) Transmit Next Counter Register -------- */ +#define PERIPH_TNCR_TXNCTR (0xffff << 0) /**< \brief (PERIPH_TNCR) Transmit Counter Next */ +/* -------- PERIPH_PTCR : (PDC Offset: 0x120) Transfer Control Register -------- */ +#define PERIPH_PTCR_RXTEN (0x1 << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */ +#define PERIPH_PTCR_RXTDIS (0x1 << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */ +#define PERIPH_PTCR_TXTEN (0x1 << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */ +#define PERIPH_PTCR_TXTDIS (0x1 << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */ +/* -------- PERIPH_PTSR : (PDC Offset: 0x124) Transfer Status Register -------- */ +#define PERIPH_PTSR_RXTEN (0x1 << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */ +#define PERIPH_PTSR_TXTEN (0x1 << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Parallel Input/Output */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_PIO Parallel Input/Output */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Pio hardware registers */ +typedef struct { + WoReg PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */ + WoReg PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */ + RoReg PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */ + RwReg Reserved1[1]; + WoReg PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */ + WoReg PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */ + RoReg PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */ + RwReg Reserved2[1]; + WoReg PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ + WoReg PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ + RoReg PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */ + RwReg Reserved3[1]; + WoReg PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */ + WoReg PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */ + RwReg PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */ + RoReg PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */ + WoReg PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */ + WoReg PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */ + RoReg PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */ + RoReg PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */ + WoReg PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */ + WoReg PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */ + RoReg PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */ + RwReg Reserved4[1]; + WoReg PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */ + WoReg PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */ + RoReg PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */ + RwReg Reserved5[1]; + RwReg PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */ + RwReg Reserved6[2]; + WoReg PIO_SCIFSR; /**< \brief (Pio Offset: 0x0080) System Clock Glitch Input Filter Select Register */ + WoReg PIO_DIFSR; /**< \brief (Pio Offset: 0x0084) Debouncing Input Filter Select Register */ + RoReg PIO_IFDGSR; /**< \brief (Pio Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register */ + RwReg PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ + WoReg PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */ + WoReg PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */ + RoReg PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */ + RwReg Reserved7[1]; + WoReg PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */ + WoReg PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */ + RoReg PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */ + RwReg Reserved8[1]; + WoReg PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ + WoReg PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */ + RoReg PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ + RwReg Reserved9[1]; + WoReg PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */ + WoReg PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */ + RoReg PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */ + RwReg Reserved10[1]; + WoReg PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */ + WoReg PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */ + RoReg PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ + RwReg Reserved11[1]; + RoReg PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */ + RwReg PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */ + RoReg PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */ + RwReg Reserved12[5]; + RwReg PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */ + RwReg Reserved13[19]; + RwReg PIO_PCMR; /**< \brief (Pio Offset: 0x150) Parallel Capture Mode Register */ + WoReg PIO_PCIER; /**< \brief (Pio Offset: 0x154) Parallel Capture Interrupt Enable Register */ + WoReg PIO_PCIDR; /**< \brief (Pio Offset: 0x158) Parallel Capture Interrupt Disable Register */ + RoReg PIO_PCIMR; /**< \brief (Pio Offset: 0x15C) Parallel Capture Interrupt Mask Register */ + RoReg PIO_PCISR; /**< \brief (Pio Offset: 0x160) Parallel Capture Interrupt Status Register */ + RoReg PIO_PCRHR; /**< \brief (Pio Offset: 0x164) Parallel Capture Reception Holding Register */ + RwReg Reserved14[38]; +} Pio; +#endif /* __ASSEMBLY__ */ +/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ +#define PIO_PER_P0 (0x1 << 0) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P1 (0x1 << 1) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P2 (0x1 << 2) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P3 (0x1 << 3) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P4 (0x1 << 4) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P5 (0x1 << 5) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P6 (0x1 << 6) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P7 (0x1 << 7) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P8 (0x1 << 8) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P9 (0x1 << 9) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P10 (0x1 << 10) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P11 (0x1 << 11) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P12 (0x1 << 12) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P13 (0x1 << 13) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P14 (0x1 << 14) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P15 (0x1 << 15) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P16 (0x1 << 16) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P17 (0x1 << 17) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P18 (0x1 << 18) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P19 (0x1 << 19) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P20 (0x1 << 20) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P21 (0x1 << 21) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P22 (0x1 << 22) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P23 (0x1 << 23) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P24 (0x1 << 24) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P25 (0x1 << 25) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P26 (0x1 << 26) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P27 (0x1 << 27) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P28 (0x1 << 28) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P29 (0x1 << 29) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P30 (0x1 << 30) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P31 (0x1 << 31) /**< \brief (PIO_PER) PIO Enable */ +/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ +#define PIO_PDR_P0 (0x1 << 0) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P1 (0x1 << 1) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P2 (0x1 << 2) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P3 (0x1 << 3) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P4 (0x1 << 4) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P5 (0x1 << 5) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P6 (0x1 << 6) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P7 (0x1 << 7) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P8 (0x1 << 8) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P9 (0x1 << 9) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P10 (0x1 << 10) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P11 (0x1 << 11) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P12 (0x1 << 12) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P13 (0x1 << 13) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P14 (0x1 << 14) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P15 (0x1 << 15) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P16 (0x1 << 16) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P17 (0x1 << 17) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P18 (0x1 << 18) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P19 (0x1 << 19) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P20 (0x1 << 20) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P21 (0x1 << 21) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P22 (0x1 << 22) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P23 (0x1 << 23) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P24 (0x1 << 24) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P25 (0x1 << 25) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P26 (0x1 << 26) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P27 (0x1 << 27) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P28 (0x1 << 28) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P29 (0x1 << 29) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P30 (0x1 << 30) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P31 (0x1 << 31) /**< \brief (PIO_PDR) PIO Disable */ +/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ +#define PIO_PSR_P0 (0x1 << 0) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P1 (0x1 << 1) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P2 (0x1 << 2) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P3 (0x1 << 3) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P4 (0x1 << 4) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P5 (0x1 << 5) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P6 (0x1 << 6) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P7 (0x1 << 7) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P8 (0x1 << 8) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P9 (0x1 << 9) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P10 (0x1 << 10) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P11 (0x1 << 11) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P12 (0x1 << 12) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P13 (0x1 << 13) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P14 (0x1 << 14) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P15 (0x1 << 15) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P16 (0x1 << 16) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P17 (0x1 << 17) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P18 (0x1 << 18) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P19 (0x1 << 19) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P20 (0x1 << 20) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P21 (0x1 << 21) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P22 (0x1 << 22) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P23 (0x1 << 23) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P24 (0x1 << 24) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P25 (0x1 << 25) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P26 (0x1 << 26) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P27 (0x1 << 27) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P28 (0x1 << 28) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P29 (0x1 << 29) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P30 (0x1 << 30) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P31 (0x1 << 31) /**< \brief (PIO_PSR) PIO Status */ +/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ +#define PIO_OER_P0 (0x1 << 0) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P1 (0x1 << 1) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P2 (0x1 << 2) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P3 (0x1 << 3) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P4 (0x1 << 4) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P5 (0x1 << 5) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P6 (0x1 << 6) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P7 (0x1 << 7) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P8 (0x1 << 8) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P9 (0x1 << 9) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P10 (0x1 << 10) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P11 (0x1 << 11) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P12 (0x1 << 12) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P13 (0x1 << 13) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P14 (0x1 << 14) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P15 (0x1 << 15) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P16 (0x1 << 16) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P17 (0x1 << 17) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P18 (0x1 << 18) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P19 (0x1 << 19) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P20 (0x1 << 20) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P21 (0x1 << 21) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P22 (0x1 << 22) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P23 (0x1 << 23) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P24 (0x1 << 24) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P25 (0x1 << 25) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P26 (0x1 << 26) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P27 (0x1 << 27) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P28 (0x1 << 28) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P29 (0x1 << 29) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P30 (0x1 << 30) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P31 (0x1 << 31) /**< \brief (PIO_OER) Output Enable */ +/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ +#define PIO_ODR_P0 (0x1 << 0) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P1 (0x1 << 1) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P2 (0x1 << 2) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P3 (0x1 << 3) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P4 (0x1 << 4) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P5 (0x1 << 5) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P6 (0x1 << 6) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P7 (0x1 << 7) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P8 (0x1 << 8) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P9 (0x1 << 9) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P10 (0x1 << 10) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P11 (0x1 << 11) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P12 (0x1 << 12) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P13 (0x1 << 13) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P14 (0x1 << 14) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P15 (0x1 << 15) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P16 (0x1 << 16) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P17 (0x1 << 17) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P18 (0x1 << 18) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P19 (0x1 << 19) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P20 (0x1 << 20) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P21 (0x1 << 21) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P22 (0x1 << 22) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P23 (0x1 << 23) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P24 (0x1 << 24) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P25 (0x1 << 25) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P26 (0x1 << 26) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P27 (0x1 << 27) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P28 (0x1 << 28) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P29 (0x1 << 29) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P30 (0x1 << 30) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P31 (0x1 << 31) /**< \brief (PIO_ODR) Output Disable */ +/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ +#define PIO_OSR_P0 (0x1 << 0) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P1 (0x1 << 1) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P2 (0x1 << 2) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P3 (0x1 << 3) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P4 (0x1 << 4) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P5 (0x1 << 5) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P6 (0x1 << 6) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P7 (0x1 << 7) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P8 (0x1 << 8) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P9 (0x1 << 9) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P10 (0x1 << 10) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P11 (0x1 << 11) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P12 (0x1 << 12) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P13 (0x1 << 13) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P14 (0x1 << 14) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P15 (0x1 << 15) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P16 (0x1 << 16) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P17 (0x1 << 17) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P18 (0x1 << 18) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P19 (0x1 << 19) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P20 (0x1 << 20) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P21 (0x1 << 21) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P22 (0x1 << 22) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P23 (0x1 << 23) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P24 (0x1 << 24) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P25 (0x1 << 25) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P26 (0x1 << 26) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P27 (0x1 << 27) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P28 (0x1 << 28) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P29 (0x1 << 29) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P30 (0x1 << 30) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P31 (0x1 << 31) /**< \brief (PIO_OSR) Output Status */ +/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ +#define PIO_IFER_P0 (0x1 << 0) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P1 (0x1 << 1) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P2 (0x1 << 2) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P3 (0x1 << 3) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P4 (0x1 << 4) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P5 (0x1 << 5) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P6 (0x1 << 6) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P7 (0x1 << 7) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P8 (0x1 << 8) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P9 (0x1 << 9) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P10 (0x1 << 10) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P11 (0x1 << 11) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P12 (0x1 << 12) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P13 (0x1 << 13) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P14 (0x1 << 14) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P15 (0x1 << 15) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P16 (0x1 << 16) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P17 (0x1 << 17) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P18 (0x1 << 18) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P19 (0x1 << 19) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P20 (0x1 << 20) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P21 (0x1 << 21) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P22 (0x1 << 22) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P23 (0x1 << 23) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P24 (0x1 << 24) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P25 (0x1 << 25) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P26 (0x1 << 26) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P27 (0x1 << 27) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P28 (0x1 << 28) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P29 (0x1 << 29) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P30 (0x1 << 30) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P31 (0x1 << 31) /**< \brief (PIO_IFER) Input Filter Enable */ +/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ +#define PIO_IFDR_P0 (0x1 << 0) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P1 (0x1 << 1) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P2 (0x1 << 2) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P3 (0x1 << 3) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P4 (0x1 << 4) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P5 (0x1 << 5) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P6 (0x1 << 6) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P7 (0x1 << 7) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P8 (0x1 << 8) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P9 (0x1 << 9) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P10 (0x1 << 10) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P11 (0x1 << 11) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P12 (0x1 << 12) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P13 (0x1 << 13) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P14 (0x1 << 14) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P15 (0x1 << 15) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P16 (0x1 << 16) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P17 (0x1 << 17) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P18 (0x1 << 18) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P19 (0x1 << 19) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P20 (0x1 << 20) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P21 (0x1 << 21) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P22 (0x1 << 22) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P23 (0x1 << 23) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P24 (0x1 << 24) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P25 (0x1 << 25) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P26 (0x1 << 26) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P27 (0x1 << 27) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P28 (0x1 << 28) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P29 (0x1 << 29) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P30 (0x1 << 30) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P31 (0x1 << 31) /**< \brief (PIO_IFDR) Input Filter Disable */ +/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ +#define PIO_IFSR_P0 (0x1 << 0) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P1 (0x1 << 1) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P2 (0x1 << 2) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P3 (0x1 << 3) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P4 (0x1 << 4) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P5 (0x1 << 5) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P6 (0x1 << 6) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P7 (0x1 << 7) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P8 (0x1 << 8) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P9 (0x1 << 9) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P10 (0x1 << 10) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P11 (0x1 << 11) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P12 (0x1 << 12) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P13 (0x1 << 13) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P14 (0x1 << 14) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P15 (0x1 << 15) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P16 (0x1 << 16) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P17 (0x1 << 17) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P18 (0x1 << 18) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P19 (0x1 << 19) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P20 (0x1 << 20) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P21 (0x1 << 21) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P22 (0x1 << 22) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P23 (0x1 << 23) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P24 (0x1 << 24) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P25 (0x1 << 25) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P26 (0x1 << 26) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P27 (0x1 << 27) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P28 (0x1 << 28) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P29 (0x1 << 29) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P30 (0x1 << 30) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P31 (0x1 << 31) /**< \brief (PIO_IFSR) Input Filer Status */ +/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ +#define PIO_SODR_P0 (0x1 << 0) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P1 (0x1 << 1) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P2 (0x1 << 2) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P3 (0x1 << 3) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P4 (0x1 << 4) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P5 (0x1 << 5) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P6 (0x1 << 6) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P7 (0x1 << 7) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P8 (0x1 << 8) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P9 (0x1 << 9) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P10 (0x1 << 10) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P11 (0x1 << 11) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P12 (0x1 << 12) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P13 (0x1 << 13) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P14 (0x1 << 14) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P15 (0x1 << 15) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P16 (0x1 << 16) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P17 (0x1 << 17) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P18 (0x1 << 18) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P19 (0x1 << 19) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P20 (0x1 << 20) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P21 (0x1 << 21) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P22 (0x1 << 22) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P23 (0x1 << 23) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P24 (0x1 << 24) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P25 (0x1 << 25) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P26 (0x1 << 26) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P27 (0x1 << 27) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P28 (0x1 << 28) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P29 (0x1 << 29) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P30 (0x1 << 30) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P31 (0x1 << 31) /**< \brief (PIO_SODR) Set Output Data */ +/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ +#define PIO_CODR_P0 (0x1 << 0) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P1 (0x1 << 1) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P2 (0x1 << 2) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P3 (0x1 << 3) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P4 (0x1 << 4) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P5 (0x1 << 5) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P6 (0x1 << 6) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P7 (0x1 << 7) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P8 (0x1 << 8) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P9 (0x1 << 9) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P10 (0x1 << 10) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P11 (0x1 << 11) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P12 (0x1 << 12) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P13 (0x1 << 13) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P14 (0x1 << 14) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P15 (0x1 << 15) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P16 (0x1 << 16) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P17 (0x1 << 17) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P18 (0x1 << 18) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P19 (0x1 << 19) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P20 (0x1 << 20) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P21 (0x1 << 21) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P22 (0x1 << 22) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P23 (0x1 << 23) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P24 (0x1 << 24) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P25 (0x1 << 25) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P26 (0x1 << 26) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P27 (0x1 << 27) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P28 (0x1 << 28) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P29 (0x1 << 29) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P30 (0x1 << 30) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P31 (0x1 << 31) /**< \brief (PIO_CODR) Clear Output Data */ +/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ +#define PIO_ODSR_P0 (0x1 << 0) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P1 (0x1 << 1) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P2 (0x1 << 2) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P3 (0x1 << 3) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P4 (0x1 << 4) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P5 (0x1 << 5) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P6 (0x1 << 6) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P7 (0x1 << 7) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P8 (0x1 << 8) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P9 (0x1 << 9) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P10 (0x1 << 10) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P11 (0x1 << 11) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P12 (0x1 << 12) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P13 (0x1 << 13) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P14 (0x1 << 14) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P15 (0x1 << 15) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P16 (0x1 << 16) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P17 (0x1 << 17) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P18 (0x1 << 18) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P19 (0x1 << 19) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P20 (0x1 << 20) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P21 (0x1 << 21) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P22 (0x1 << 22) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P23 (0x1 << 23) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P24 (0x1 << 24) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P25 (0x1 << 25) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P26 (0x1 << 26) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P27 (0x1 << 27) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P28 (0x1 << 28) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P29 (0x1 << 29) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P30 (0x1 << 30) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P31 (0x1 << 31) /**< \brief (PIO_ODSR) Output Data Status */ +/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ +#define PIO_PDSR_P0 (0x1 << 0) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P1 (0x1 << 1) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P2 (0x1 << 2) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P3 (0x1 << 3) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P4 (0x1 << 4) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P5 (0x1 << 5) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P6 (0x1 << 6) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P7 (0x1 << 7) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P8 (0x1 << 8) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P9 (0x1 << 9) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P10 (0x1 << 10) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P11 (0x1 << 11) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P12 (0x1 << 12) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P13 (0x1 << 13) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P14 (0x1 << 14) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P15 (0x1 << 15) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P16 (0x1 << 16) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P17 (0x1 << 17) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P18 (0x1 << 18) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P19 (0x1 << 19) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P20 (0x1 << 20) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P21 (0x1 << 21) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P22 (0x1 << 22) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P23 (0x1 << 23) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P24 (0x1 << 24) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P25 (0x1 << 25) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P26 (0x1 << 26) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P27 (0x1 << 27) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P28 (0x1 << 28) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P29 (0x1 << 29) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P30 (0x1 << 30) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P31 (0x1 << 31) /**< \brief (PIO_PDSR) Output Data Status */ +/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ +#define PIO_IER_P0 (0x1 << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P1 (0x1 << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P2 (0x1 << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P3 (0x1 << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P4 (0x1 << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P5 (0x1 << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P6 (0x1 << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P7 (0x1 << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P8 (0x1 << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P9 (0x1 << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P10 (0x1 << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P11 (0x1 << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P12 (0x1 << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P13 (0x1 << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P14 (0x1 << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P15 (0x1 << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P16 (0x1 << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P17 (0x1 << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P18 (0x1 << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P19 (0x1 << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P20 (0x1 << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P21 (0x1 << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P22 (0x1 << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P23 (0x1 << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P24 (0x1 << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P25 (0x1 << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P26 (0x1 << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P27 (0x1 << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P28 (0x1 << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P29 (0x1 << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P30 (0x1 << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P31 (0x1 << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ +#define PIO_IDR_P0 (0x1 << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P1 (0x1 << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P2 (0x1 << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P3 (0x1 << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P4 (0x1 << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P5 (0x1 << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P6 (0x1 << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P7 (0x1 << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P8 (0x1 << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P9 (0x1 << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P10 (0x1 << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P11 (0x1 << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P12 (0x1 << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P13 (0x1 << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P14 (0x1 << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P15 (0x1 << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P16 (0x1 << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P17 (0x1 << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P18 (0x1 << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P19 (0x1 << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P20 (0x1 << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P21 (0x1 << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P22 (0x1 << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P23 (0x1 << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P24 (0x1 << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P25 (0x1 << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P26 (0x1 << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P27 (0x1 << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P28 (0x1 << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P29 (0x1 << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P30 (0x1 << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P31 (0x1 << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ +#define PIO_IMR_P0 (0x1 << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P1 (0x1 << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P2 (0x1 << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P3 (0x1 << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P4 (0x1 << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P5 (0x1 << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P6 (0x1 << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P7 (0x1 << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P8 (0x1 << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P9 (0x1 << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P10 (0x1 << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P11 (0x1 << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P12 (0x1 << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P13 (0x1 << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P14 (0x1 << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P15 (0x1 << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P16 (0x1 << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P17 (0x1 << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P18 (0x1 << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P19 (0x1 << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P20 (0x1 << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P21 (0x1 << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P22 (0x1 << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P23 (0x1 << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P24 (0x1 << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P25 (0x1 << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P26 (0x1 << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P27 (0x1 << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P28 (0x1 << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P29 (0x1 << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P30 (0x1 << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P31 (0x1 << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ +#define PIO_ISR_P0 (0x1 << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P1 (0x1 << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P2 (0x1 << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P3 (0x1 << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P4 (0x1 << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P5 (0x1 << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P6 (0x1 << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P7 (0x1 << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P8 (0x1 << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P9 (0x1 << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P10 (0x1 << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P11 (0x1 << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P12 (0x1 << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P13 (0x1 << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P14 (0x1 << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P15 (0x1 << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P16 (0x1 << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P17 (0x1 << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P18 (0x1 << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P19 (0x1 << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P20 (0x1 << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P21 (0x1 << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P22 (0x1 << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P23 (0x1 << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P24 (0x1 << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P25 (0x1 << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P26 (0x1 << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P27 (0x1 << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P28 (0x1 << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P29 (0x1 << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P30 (0x1 << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P31 (0x1 << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ +#define PIO_MDER_P0 (0x1 << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P1 (0x1 << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P2 (0x1 << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P3 (0x1 << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P4 (0x1 << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P5 (0x1 << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P6 (0x1 << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P7 (0x1 << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P8 (0x1 << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P9 (0x1 << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P10 (0x1 << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P11 (0x1 << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P12 (0x1 << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P13 (0x1 << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P14 (0x1 << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P15 (0x1 << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P16 (0x1 << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P17 (0x1 << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P18 (0x1 << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P19 (0x1 << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P20 (0x1 << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P21 (0x1 << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P22 (0x1 << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P23 (0x1 << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P24 (0x1 << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P25 (0x1 << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P26 (0x1 << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P27 (0x1 << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P28 (0x1 << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P29 (0x1 << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P30 (0x1 << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P31 (0x1 << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */ +/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ +#define PIO_MDDR_P0 (0x1 << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P1 (0x1 << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P2 (0x1 << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P3 (0x1 << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P4 (0x1 << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P5 (0x1 << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P6 (0x1 << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P7 (0x1 << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P8 (0x1 << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P9 (0x1 << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P10 (0x1 << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P11 (0x1 << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P12 (0x1 << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P13 (0x1 << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P14 (0x1 << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P15 (0x1 << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P16 (0x1 << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P17 (0x1 << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P18 (0x1 << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P19 (0x1 << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P20 (0x1 << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P21 (0x1 << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P22 (0x1 << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P23 (0x1 << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P24 (0x1 << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P25 (0x1 << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P26 (0x1 << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P27 (0x1 << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P28 (0x1 << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P29 (0x1 << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P30 (0x1 << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P31 (0x1 << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ +#define PIO_MDSR_P0 (0x1 << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P1 (0x1 << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P2 (0x1 << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P3 (0x1 << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P4 (0x1 << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P5 (0x1 << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P6 (0x1 << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P7 (0x1 << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P8 (0x1 << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P9 (0x1 << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P10 (0x1 << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P11 (0x1 << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P12 (0x1 << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P13 (0x1 << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P14 (0x1 << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P15 (0x1 << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P16 (0x1 << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P17 (0x1 << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P18 (0x1 << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P19 (0x1 << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P20 (0x1 << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P21 (0x1 << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P22 (0x1 << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P23 (0x1 << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P24 (0x1 << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P25 (0x1 << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P26 (0x1 << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P27 (0x1 << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P28 (0x1 << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P29 (0x1 << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P30 (0x1 << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P31 (0x1 << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */ +/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ +#define PIO_PUDR_P0 (0x1 << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P1 (0x1 << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P2 (0x1 << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P3 (0x1 << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P4 (0x1 << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P5 (0x1 << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P6 (0x1 << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P7 (0x1 << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P8 (0x1 << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P9 (0x1 << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P10 (0x1 << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P11 (0x1 << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P12 (0x1 << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P13 (0x1 << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P14 (0x1 << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P15 (0x1 << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P16 (0x1 << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P17 (0x1 << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P18 (0x1 << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P19 (0x1 << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P20 (0x1 << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P21 (0x1 << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P22 (0x1 << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P23 (0x1 << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P24 (0x1 << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P25 (0x1 << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P26 (0x1 << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P27 (0x1 << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P28 (0x1 << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P29 (0x1 << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P30 (0x1 << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P31 (0x1 << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */ +/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ +#define PIO_PUER_P0 (0x1 << 0) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P1 (0x1 << 1) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P2 (0x1 << 2) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P3 (0x1 << 3) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P4 (0x1 << 4) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P5 (0x1 << 5) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P6 (0x1 << 6) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P7 (0x1 << 7) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P8 (0x1 << 8) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P9 (0x1 << 9) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P10 (0x1 << 10) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P11 (0x1 << 11) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P12 (0x1 << 12) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P13 (0x1 << 13) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P14 (0x1 << 14) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P15 (0x1 << 15) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P16 (0x1 << 16) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P17 (0x1 << 17) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P18 (0x1 << 18) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P19 (0x1 << 19) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P20 (0x1 << 20) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P21 (0x1 << 21) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P22 (0x1 << 22) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P23 (0x1 << 23) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P24 (0x1 << 24) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P25 (0x1 << 25) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P26 (0x1 << 26) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P27 (0x1 << 27) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P28 (0x1 << 28) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P29 (0x1 << 29) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P30 (0x1 << 30) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P31 (0x1 << 31) /**< \brief (PIO_PUER) Pull Up Enable. */ +/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ +#define PIO_PUSR_P0 (0x1 << 0) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P1 (0x1 << 1) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P2 (0x1 << 2) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P3 (0x1 << 3) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P4 (0x1 << 4) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P5 (0x1 << 5) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P6 (0x1 << 6) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P7 (0x1 << 7) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P8 (0x1 << 8) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P9 (0x1 << 9) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P10 (0x1 << 10) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P11 (0x1 << 11) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P12 (0x1 << 12) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P13 (0x1 << 13) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P14 (0x1 << 14) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P15 (0x1 << 15) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P16 (0x1 << 16) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P17 (0x1 << 17) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P18 (0x1 << 18) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P19 (0x1 << 19) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P20 (0x1 << 20) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P21 (0x1 << 21) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P22 (0x1 << 22) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P23 (0x1 << 23) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P24 (0x1 << 24) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P25 (0x1 << 25) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P26 (0x1 << 26) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P27 (0x1 << 27) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P28 (0x1 << 28) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P29 (0x1 << 29) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P30 (0x1 << 30) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P31 (0x1 << 31) /**< \brief (PIO_PUSR) Pull Up Status. */ +/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */ +#define PIO_ABCDSR_P0 (0x1 << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P1 (0x1 << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P2 (0x1 << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P3 (0x1 << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P4 (0x1 << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P5 (0x1 << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P6 (0x1 << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P7 (0x1 << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P8 (0x1 << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P9 (0x1 << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P10 (0x1 << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P11 (0x1 << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P12 (0x1 << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P13 (0x1 << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P14 (0x1 << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P15 (0x1 << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P16 (0x1 << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P17 (0x1 << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P18 (0x1 << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P19 (0x1 << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P20 (0x1 << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P21 (0x1 << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P22 (0x1 << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P23 (0x1 << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P24 (0x1 << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P25 (0x1 << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P26 (0x1 << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P27 (0x1 << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P28 (0x1 << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P29 (0x1 << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P30 (0x1 << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P31 (0x1 << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +/* -------- PIO_SCIFSR : (PIO Offset: 0x0080) System Clock Glitch Input Filter Select Register -------- */ +#define PIO_SCIFSR_P0 (0x1 << 0) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P1 (0x1 << 1) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P2 (0x1 << 2) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P3 (0x1 << 3) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P4 (0x1 << 4) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P5 (0x1 << 5) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P6 (0x1 << 6) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P7 (0x1 << 7) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P8 (0x1 << 8) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P9 (0x1 << 9) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P10 (0x1 << 10) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P11 (0x1 << 11) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P12 (0x1 << 12) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P13 (0x1 << 13) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P14 (0x1 << 14) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P15 (0x1 << 15) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P16 (0x1 << 16) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P17 (0x1 << 17) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P18 (0x1 << 18) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P19 (0x1 << 19) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P20 (0x1 << 20) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P21 (0x1 << 21) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P22 (0x1 << 22) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P23 (0x1 << 23) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P24 (0x1 << 24) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P25 (0x1 << 25) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P26 (0x1 << 26) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P27 (0x1 << 27) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P28 (0x1 << 28) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P29 (0x1 << 29) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P30 (0x1 << 30) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P31 (0x1 << 31) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +/* -------- PIO_DIFSR : (PIO Offset: 0x0084) Debouncing Input Filter Select Register -------- */ +#define PIO_DIFSR_P0 (0x1 << 0) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P1 (0x1 << 1) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P2 (0x1 << 2) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P3 (0x1 << 3) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P4 (0x1 << 4) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P5 (0x1 << 5) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P6 (0x1 << 6) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P7 (0x1 << 7) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P8 (0x1 << 8) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P9 (0x1 << 9) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P10 (0x1 << 10) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P11 (0x1 << 11) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P12 (0x1 << 12) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P13 (0x1 << 13) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P14 (0x1 << 14) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P15 (0x1 << 15) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P16 (0x1 << 16) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P17 (0x1 << 17) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P18 (0x1 << 18) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P19 (0x1 << 19) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P20 (0x1 << 20) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P21 (0x1 << 21) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P22 (0x1 << 22) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P23 (0x1 << 23) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P24 (0x1 << 24) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P25 (0x1 << 25) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P26 (0x1 << 26) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P27 (0x1 << 27) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P28 (0x1 << 28) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P29 (0x1 << 29) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P30 (0x1 << 30) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P31 (0x1 << 31) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +/* -------- PIO_IFDGSR : (PIO Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register -------- */ +#define PIO_IFDGSR_P0 (0x1 << 0) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P1 (0x1 << 1) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P2 (0x1 << 2) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P3 (0x1 << 3) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P4 (0x1 << 4) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P5 (0x1 << 5) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P6 (0x1 << 6) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P7 (0x1 << 7) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P8 (0x1 << 8) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P9 (0x1 << 9) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P10 (0x1 << 10) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P11 (0x1 << 11) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P12 (0x1 << 12) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P13 (0x1 << 13) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P14 (0x1 << 14) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P15 (0x1 << 15) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P16 (0x1 << 16) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P17 (0x1 << 17) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P18 (0x1 << 18) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P19 (0x1 << 19) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P20 (0x1 << 20) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P21 (0x1 << 21) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P22 (0x1 << 22) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P23 (0x1 << 23) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P24 (0x1 << 24) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P25 (0x1 << 25) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P26 (0x1 << 26) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P27 (0x1 << 27) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P28 (0x1 << 28) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P29 (0x1 << 29) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P30 (0x1 << 30) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P31 (0x1 << 31) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ +#define PIO_SCDR_DIV0 (0x1 << 0) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV1 (0x1 << 1) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV2 (0x1 << 2) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV3 (0x1 << 3) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV4 (0x1 << 4) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV5 (0x1 << 5) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV6 (0x1 << 6) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV7 (0x1 << 7) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV8 (0x1 << 8) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV9 (0x1 << 9) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV10 (0x1 << 10) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV11 (0x1 << 11) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV12 (0x1 << 12) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV13 (0x1 << 13) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */ +#define PIO_PPDDR_P0 (0x1 << 0) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P1 (0x1 << 1) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P2 (0x1 << 2) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P3 (0x1 << 3) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P4 (0x1 << 4) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P5 (0x1 << 5) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P6 (0x1 << 6) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P7 (0x1 << 7) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P8 (0x1 << 8) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P9 (0x1 << 9) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P10 (0x1 << 10) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P11 (0x1 << 11) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P12 (0x1 << 12) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P13 (0x1 << 13) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P14 (0x1 << 14) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P15 (0x1 << 15) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P16 (0x1 << 16) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P17 (0x1 << 17) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P18 (0x1 << 18) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P19 (0x1 << 19) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P20 (0x1 << 20) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P21 (0x1 << 21) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P22 (0x1 << 22) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P23 (0x1 << 23) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P24 (0x1 << 24) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P25 (0x1 << 25) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P26 (0x1 << 26) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P27 (0x1 << 27) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P28 (0x1 << 28) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P29 (0x1 << 29) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P30 (0x1 << 30) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P31 (0x1 << 31) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */ +#define PIO_PPDER_P0 (0x1 << 0) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P1 (0x1 << 1) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P2 (0x1 << 2) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P3 (0x1 << 3) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P4 (0x1 << 4) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P5 (0x1 << 5) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P6 (0x1 << 6) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P7 (0x1 << 7) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P8 (0x1 << 8) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P9 (0x1 << 9) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P10 (0x1 << 10) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P11 (0x1 << 11) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P12 (0x1 << 12) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P13 (0x1 << 13) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P14 (0x1 << 14) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P15 (0x1 << 15) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P16 (0x1 << 16) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P17 (0x1 << 17) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P18 (0x1 << 18) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P19 (0x1 << 19) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P20 (0x1 << 20) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P21 (0x1 << 21) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P22 (0x1 << 22) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P23 (0x1 << 23) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P24 (0x1 << 24) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P25 (0x1 << 25) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P26 (0x1 << 26) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P27 (0x1 << 27) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P28 (0x1 << 28) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P29 (0x1 << 29) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P30 (0x1 << 30) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P31 (0x1 << 31) /**< \brief (PIO_PPDER) Pull Down Enable. */ +/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */ +#define PIO_PPDSR_P0 (0x1 << 0) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P1 (0x1 << 1) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P2 (0x1 << 2) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P3 (0x1 << 3) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P4 (0x1 << 4) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P5 (0x1 << 5) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P6 (0x1 << 6) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P7 (0x1 << 7) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P8 (0x1 << 8) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P9 (0x1 << 9) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P10 (0x1 << 10) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P11 (0x1 << 11) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P12 (0x1 << 12) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P13 (0x1 << 13) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P14 (0x1 << 14) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P15 (0x1 << 15) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P16 (0x1 << 16) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P17 (0x1 << 17) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P18 (0x1 << 18) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P19 (0x1 << 19) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P20 (0x1 << 20) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P21 (0x1 << 21) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P22 (0x1 << 22) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P23 (0x1 << 23) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P24 (0x1 << 24) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P25 (0x1 << 25) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P26 (0x1 << 26) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P27 (0x1 << 27) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P28 (0x1 << 28) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P29 (0x1 << 29) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P30 (0x1 << 30) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P31 (0x1 << 31) /**< \brief (PIO_PPDSR) Pull Down Status. */ +/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ +#define PIO_OWER_P0 (0x1 << 0) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P1 (0x1 << 1) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P2 (0x1 << 2) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P3 (0x1 << 3) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P4 (0x1 << 4) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P5 (0x1 << 5) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P6 (0x1 << 6) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P7 (0x1 << 7) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P8 (0x1 << 8) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P9 (0x1 << 9) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P10 (0x1 << 10) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P11 (0x1 << 11) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P12 (0x1 << 12) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P13 (0x1 << 13) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P14 (0x1 << 14) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P15 (0x1 << 15) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P16 (0x1 << 16) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P17 (0x1 << 17) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P18 (0x1 << 18) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P19 (0x1 << 19) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P20 (0x1 << 20) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P21 (0x1 << 21) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P22 (0x1 << 22) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P23 (0x1 << 23) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P24 (0x1 << 24) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P25 (0x1 << 25) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P26 (0x1 << 26) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P27 (0x1 << 27) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P28 (0x1 << 28) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P29 (0x1 << 29) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P30 (0x1 << 30) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P31 (0x1 << 31) /**< \brief (PIO_OWER) Output Write Enable. */ +/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ +#define PIO_OWDR_P0 (0x1 << 0) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P1 (0x1 << 1) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P2 (0x1 << 2) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P3 (0x1 << 3) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P4 (0x1 << 4) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P5 (0x1 << 5) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P6 (0x1 << 6) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P7 (0x1 << 7) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P8 (0x1 << 8) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P9 (0x1 << 9) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P10 (0x1 << 10) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P11 (0x1 << 11) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P12 (0x1 << 12) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P13 (0x1 << 13) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P14 (0x1 << 14) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P15 (0x1 << 15) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P16 (0x1 << 16) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P17 (0x1 << 17) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P18 (0x1 << 18) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P19 (0x1 << 19) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P20 (0x1 << 20) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P21 (0x1 << 21) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P22 (0x1 << 22) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P23 (0x1 << 23) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P24 (0x1 << 24) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P25 (0x1 << 25) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P26 (0x1 << 26) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P27 (0x1 << 27) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P28 (0x1 << 28) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P29 (0x1 << 29) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P30 (0x1 << 30) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P31 (0x1 << 31) /**< \brief (PIO_OWDR) Output Write Disable. */ +/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ +#define PIO_OWSR_P0 (0x1 << 0) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P1 (0x1 << 1) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P2 (0x1 << 2) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P3 (0x1 << 3) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P4 (0x1 << 4) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P5 (0x1 << 5) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P6 (0x1 << 6) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P7 (0x1 << 7) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P8 (0x1 << 8) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P9 (0x1 << 9) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P10 (0x1 << 10) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P11 (0x1 << 11) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P12 (0x1 << 12) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P13 (0x1 << 13) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P14 (0x1 << 14) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P15 (0x1 << 15) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P16 (0x1 << 16) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P17 (0x1 << 17) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P18 (0x1 << 18) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P19 (0x1 << 19) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P20 (0x1 << 20) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P21 (0x1 << 21) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P22 (0x1 << 22) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P23 (0x1 << 23) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P24 (0x1 << 24) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P25 (0x1 << 25) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P26 (0x1 << 26) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P27 (0x1 << 27) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P28 (0x1 << 28) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P29 (0x1 << 29) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P30 (0x1 << 30) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P31 (0x1 << 31) /**< \brief (PIO_OWSR) Output Write Status. */ +/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ +#define PIO_AIMER_P0 (0x1 << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P1 (0x1 << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P2 (0x1 << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P3 (0x1 << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P4 (0x1 << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P5 (0x1 << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P6 (0x1 << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P7 (0x1 << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P8 (0x1 << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P9 (0x1 << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P10 (0x1 << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P11 (0x1 << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P12 (0x1 << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P13 (0x1 << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P14 (0x1 << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P15 (0x1 << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P16 (0x1 << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P17 (0x1 << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P18 (0x1 << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P19 (0x1 << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P20 (0x1 << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P21 (0x1 << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P22 (0x1 << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P23 (0x1 << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P24 (0x1 << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P25 (0x1 << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P26 (0x1 << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P27 (0x1 << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P28 (0x1 << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P29 (0x1 << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P30 (0x1 << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P31 (0x1 << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */ +#define PIO_AIMDR_P0 (0x1 << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P1 (0x1 << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P2 (0x1 << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P3 (0x1 << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P4 (0x1 << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P5 (0x1 << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P6 (0x1 << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P7 (0x1 << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P8 (0x1 << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P9 (0x1 << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P10 (0x1 << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P11 (0x1 << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P12 (0x1 << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P13 (0x1 << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P14 (0x1 << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P15 (0x1 << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P16 (0x1 << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P17 (0x1 << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P18 (0x1 << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P19 (0x1 << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P20 (0x1 << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P21 (0x1 << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P22 (0x1 << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P23 (0x1 << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P24 (0x1 << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P25 (0x1 << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P26 (0x1 << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P27 (0x1 << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P28 (0x1 << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P29 (0x1 << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P30 (0x1 << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P31 (0x1 << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ +#define PIO_AIMMR_P0 (0x1 << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P1 (0x1 << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P2 (0x1 << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P3 (0x1 << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P4 (0x1 << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P5 (0x1 << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P6 (0x1 << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P7 (0x1 << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P8 (0x1 << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P9 (0x1 << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P10 (0x1 << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P11 (0x1 << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P12 (0x1 << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P13 (0x1 << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P14 (0x1 << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P15 (0x1 << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P16 (0x1 << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P17 (0x1 << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P18 (0x1 << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P19 (0x1 << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P20 (0x1 << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P21 (0x1 << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P22 (0x1 << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P23 (0x1 << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P24 (0x1 << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P25 (0x1 << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P26 (0x1 << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P27 (0x1 << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P28 (0x1 << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P29 (0x1 << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P30 (0x1 << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P31 (0x1 << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ +#define PIO_ESR_P0 (0x1 << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P1 (0x1 << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P2 (0x1 << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P3 (0x1 << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P4 (0x1 << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P5 (0x1 << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P6 (0x1 << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P7 (0x1 << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P8 (0x1 << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P9 (0x1 << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P10 (0x1 << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P11 (0x1 << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P12 (0x1 << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P13 (0x1 << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P14 (0x1 << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P15 (0x1 << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P16 (0x1 << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P17 (0x1 << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P18 (0x1 << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P19 (0x1 << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P20 (0x1 << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P21 (0x1 << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P22 (0x1 << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P23 (0x1 << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P24 (0x1 << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P25 (0x1 << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P26 (0x1 << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P27 (0x1 << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P28 (0x1 << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P29 (0x1 << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P30 (0x1 << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P31 (0x1 << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ +#define PIO_LSR_P0 (0x1 << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P1 (0x1 << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P2 (0x1 << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P3 (0x1 << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P4 (0x1 << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P5 (0x1 << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P6 (0x1 << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P7 (0x1 << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P8 (0x1 << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P9 (0x1 << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P10 (0x1 << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P11 (0x1 << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P12 (0x1 << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P13 (0x1 << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P14 (0x1 << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P15 (0x1 << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P16 (0x1 << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P17 (0x1 << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P18 (0x1 << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P19 (0x1 << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P20 (0x1 << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P21 (0x1 << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P22 (0x1 << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P23 (0x1 << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P24 (0x1 << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P25 (0x1 << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P26 (0x1 << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P27 (0x1 << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P28 (0x1 << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P29 (0x1 << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P30 (0x1 << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P31 (0x1 << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ +#define PIO_ELSR_P0 (0x1 << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P1 (0x1 << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P2 (0x1 << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P3 (0x1 << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P4 (0x1 << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P5 (0x1 << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P6 (0x1 << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P7 (0x1 << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P8 (0x1 << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P9 (0x1 << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P10 (0x1 << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P11 (0x1 << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P12 (0x1 << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P13 (0x1 << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P14 (0x1 << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P15 (0x1 << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P16 (0x1 << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P17 (0x1 << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P18 (0x1 << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P19 (0x1 << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P20 (0x1 << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P21 (0x1 << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P22 (0x1 << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P23 (0x1 << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P24 (0x1 << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P25 (0x1 << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P26 (0x1 << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P27 (0x1 << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P28 (0x1 << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P29 (0x1 << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P30 (0x1 << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P31 (0x1 << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */ +#define PIO_FELLSR_P0 (0x1 << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P1 (0x1 << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P2 (0x1 << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P3 (0x1 << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P4 (0x1 << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P5 (0x1 << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P6 (0x1 << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P7 (0x1 << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P8 (0x1 << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P9 (0x1 << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P10 (0x1 << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P11 (0x1 << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P12 (0x1 << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P13 (0x1 << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P14 (0x1 << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P15 (0x1 << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P16 (0x1 << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P17 (0x1 << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P18 (0x1 << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P19 (0x1 << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P20 (0x1 << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P21 (0x1 << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P22 (0x1 << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P23 (0x1 << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P24 (0x1 << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P25 (0x1 << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P26 (0x1 << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P27 (0x1 << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P28 (0x1 << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P29 (0x1 << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P30 (0x1 << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P31 (0x1 << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */ +#define PIO_REHLSR_P0 (0x1 << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P1 (0x1 << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P2 (0x1 << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P3 (0x1 << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P4 (0x1 << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P5 (0x1 << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P6 (0x1 << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P7 (0x1 << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P8 (0x1 << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P9 (0x1 << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P10 (0x1 << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P11 (0x1 << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P12 (0x1 << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P13 (0x1 << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P14 (0x1 << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P15 (0x1 << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P16 (0x1 << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P17 (0x1 << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P18 (0x1 << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P19 (0x1 << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P20 (0x1 << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P21 (0x1 << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P22 (0x1 << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P23 (0x1 << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P24 (0x1 << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P25 (0x1 << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P26 (0x1 << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P27 (0x1 << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P28 (0x1 << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P29 (0x1 << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P30 (0x1 << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P31 (0x1 << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ +#define PIO_FRLHSR_P0 (0x1 << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P1 (0x1 << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P2 (0x1 << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P3 (0x1 << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P4 (0x1 << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P5 (0x1 << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P6 (0x1 << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P7 (0x1 << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P8 (0x1 << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P9 (0x1 << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P10 (0x1 << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P11 (0x1 << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P12 (0x1 << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P13 (0x1 << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P14 (0x1 << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P15 (0x1 << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P16 (0x1 << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P17 (0x1 << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P18 (0x1 << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P19 (0x1 << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P20 (0x1 << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P21 (0x1 << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P22 (0x1 << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P23 (0x1 << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P24 (0x1 << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P25 (0x1 << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P26 (0x1 << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P27 (0x1 << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P28 (0x1 << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P29 (0x1 << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P30 (0x1 << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P31 (0x1 << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */ +#define PIO_LOCKSR_P0 (0x1 << 0) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P1 (0x1 << 1) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P2 (0x1 << 2) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P3 (0x1 << 3) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P4 (0x1 << 4) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P5 (0x1 << 5) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P6 (0x1 << 6) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P7 (0x1 << 7) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P8 (0x1 << 8) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P9 (0x1 << 9) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P10 (0x1 << 10) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P11 (0x1 << 11) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P12 (0x1 << 12) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P13 (0x1 << 13) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P14 (0x1 << 14) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P15 (0x1 << 15) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P16 (0x1 << 16) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P17 (0x1 << 17) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P18 (0x1 << 18) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P19 (0x1 << 19) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P20 (0x1 << 20) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P21 (0x1 << 21) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P22 (0x1 << 22) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P23 (0x1 << 23) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P24 (0x1 << 24) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P25 (0x1 << 25) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P26 (0x1 << 26) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P27 (0x1 << 27) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P28 (0x1 << 28) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P29 (0x1 << 29) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P30 (0x1 << 30) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P31 (0x1 << 31) /**< \brief (PIO_LOCKSR) Lock Status. */ +/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */ +#define PIO_WPMR_WPEN (0x1 << 0) /**< \brief (PIO_WPMR) Write Protect Enable */ +#define PIO_WPMR_WPKEY (0xffffff << 8) /**< \brief (PIO_WPMR) Write Protect KEY */ +/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */ +#define PIO_WPSR_WPVS (0x1 << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */ +#define PIO_WPSR_WPVSRC (0xffff << 8) /**< \brief (PIO_WPSR) Write Protect Violation Source */ +/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */ +#define PIO_SCHMITT_SCHMITT0 (0x1 << 0) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT1 (0x1 << 1) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT2 (0x1 << 2) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT3 (0x1 << 3) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT4 (0x1 << 4) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT5 (0x1 << 5) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT6 (0x1 << 6) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT7 (0x1 << 7) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT8 (0x1 << 8) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT9 (0x1 << 9) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT10 (0x1 << 10) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT11 (0x1 << 11) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT12 (0x1 << 12) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT13 (0x1 << 13) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT14 (0x1 << 14) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT15 (0x1 << 15) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT16 (0x1 << 16) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT17 (0x1 << 17) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT18 (0x1 << 18) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT19 (0x1 << 19) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT20 (0x1 << 20) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT21 (0x1 << 21) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT22 (0x1 << 22) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT23 (0x1 << 23) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT24 (0x1 << 24) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT25 (0x1 << 25) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT26 (0x1 << 26) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT27 (0x1 << 27) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT28 (0x1 << 28) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT29 (0x1 << 29) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT30 (0x1 << 30) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT31 (0x1 << 31) /**< \brief (PIO_SCHMITT) */ +/* -------- PIO_PCMR : (PIO Offset: 0x150) Parallel Capture Mode Register -------- */ +#define PIO_PCMR_PCEN (0x1 << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */ +#define PIO_PCMR_DSIZE (0x3 << 4) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */ +#define PIO_PCMR_ALWYS (0x1 << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */ +#define PIO_PCMR_HALFS (0x1 << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */ +#define PIO_PCMR_FRSTS (0x1 << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */ +/* -------- PIO_PCIER : (PIO Offset: 0x154) Parallel Capture Interrupt Enable Register -------- */ +#define PIO_PCIER_DRDY (0x1 << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */ +#define PIO_PCIER_OVRE (0x1 << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */ +#define PIO_PCIER_ENDRX (0x1 << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */ +#define PIO_PCIER_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */ +/* -------- PIO_PCIDR : (PIO Offset: 0x158) Parallel Capture Interrupt Disable Register -------- */ +#define PIO_PCIDR_DRDY (0x1 << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */ +#define PIO_PCIDR_OVRE (0x1 << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */ +#define PIO_PCIDR_ENDRX (0x1 << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */ +#define PIO_PCIDR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */ +/* -------- PIO_PCIMR : (PIO Offset: 0x15C) Parallel Capture Interrupt Mask Register -------- */ +#define PIO_PCIMR_DRDY (0x1 << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */ +#define PIO_PCIMR_OVRE (0x1 << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */ +#define PIO_PCIMR_ENDRX (0x1 << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */ +#define PIO_PCIMR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */ +/* -------- PIO_PCISR : (PIO Offset: 0x160) Parallel Capture Interrupt Status Register -------- */ +#define PIO_PCISR_DRDY (0x1 << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */ +#define PIO_PCISR_OVRE (0x1 << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error. */ +#define PIO_PCISR_ENDRX (0x1 << 2) /**< \brief (PIO_PCISR) End of Reception Transfer. */ +#define PIO_PCISR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCISR) Reception Buffer Full */ +/* -------- PIO_PCRHR : (PIO Offset: 0x164) Parallel Capture Reception Holding Register -------- */ +#define PIO_PCRHR_RDATA (0xffffffff << 0) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data. */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_PMC Power Management Controller */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Pmc hardware registers */ +typedef struct { + WoReg PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */ + WoReg PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */ + RoReg PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */ + RwReg Reserved1[1]; + WoReg PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */ + WoReg PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */ + RoReg PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */ + RwReg Reserved2[1]; + RwReg CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */ + RoReg CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */ + RwReg CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */ + RwReg CKGR_PLLBR; /**< \brief (Pmc Offset: 0x002C) PLLB Register */ + RwReg PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */ + RwReg Reserved3[1]; + RwReg PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */ + RwReg Reserved4[1]; + RwReg PMC_PCK[3]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */ + RwReg Reserved5[5]; + WoReg PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */ + WoReg PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */ + RoReg PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */ + RoReg PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */ + RwReg PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */ + RwReg PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */ + WoReg PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */ + RwReg Reserved6[26]; + RwReg PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */ + RoReg PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */ + RwReg Reserved7[5]; + WoReg PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */ + WoReg PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */ + RoReg PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */ + RwReg Reserved8[1]; + RwReg PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */ +} Pmc; +#endif /* __ASSEMBLY__ */ +/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ +#define PMC_SCER_UDP (0x1 << 7) /**< \brief (PMC_SCER) USB Device Port Clock Enable */ +#define PMC_SCER_PCK0 (0x1 << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */ +#define PMC_SCER_PCK1 (0x1 << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */ +#define PMC_SCER_PCK2 (0x1 << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */ +/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */ +#define PMC_SCDR_UDP (0x1 << 7) /**< \brief (PMC_SCDR) USB Device Port Clock Disable */ +#define PMC_SCDR_PCK0 (0x1 << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */ +#define PMC_SCDR_PCK1 (0x1 << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */ +#define PMC_SCDR_PCK2 (0x1 << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */ +/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */ +#define PMC_SCSR_UDP (0x1 << 7) /**< \brief (PMC_SCSR) USB Device Port Clock Status */ +#define PMC_SCSR_PCK0 (0x1 << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */ +#define PMC_SCSR_PCK1 (0x1 << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */ +#define PMC_SCSR_PCK2 (0x1 << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */ +/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */ +#define PMC_PCER0_PID2 (0x1 << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */ +#define PMC_PCER0_PID3 (0x1 << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */ +#define PMC_PCER0_PID4 (0x1 << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */ +#define PMC_PCER0_PID5 (0x1 << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */ +#define PMC_PCER0_PID6 (0x1 << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */ +#define PMC_PCER0_PID7 (0x1 << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */ +#define PMC_PCER0_PID8 (0x1 << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */ +#define PMC_PCER0_PID9 (0x1 << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */ +#define PMC_PCER0_PID10 (0x1 << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */ +#define PMC_PCER0_PID11 (0x1 << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */ +#define PMC_PCER0_PID12 (0x1 << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */ +#define PMC_PCER0_PID13 (0x1 << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */ +#define PMC_PCER0_PID14 (0x1 << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */ +#define PMC_PCER0_PID15 (0x1 << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */ +#define PMC_PCER0_PID16 (0x1 << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */ +#define PMC_PCER0_PID17 (0x1 << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */ +#define PMC_PCER0_PID18 (0x1 << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */ +#define PMC_PCER0_PID19 (0x1 << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */ +#define PMC_PCER0_PID20 (0x1 << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */ +#define PMC_PCER0_PID21 (0x1 << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */ +#define PMC_PCER0_PID22 (0x1 << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */ +#define PMC_PCER0_PID23 (0x1 << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */ +#define PMC_PCER0_PID24 (0x1 << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */ +#define PMC_PCER0_PID25 (0x1 << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */ +#define PMC_PCER0_PID26 (0x1 << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */ +#define PMC_PCER0_PID27 (0x1 << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */ +#define PMC_PCER0_PID28 (0x1 << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */ +#define PMC_PCER0_PID29 (0x1 << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */ +#define PMC_PCER0_PID30 (0x1 << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */ +#define PMC_PCER0_PID31 (0x1 << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */ +/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */ +#define PMC_PCDR0_PID2 (0x1 << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */ +#define PMC_PCDR0_PID3 (0x1 << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */ +#define PMC_PCDR0_PID4 (0x1 << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */ +#define PMC_PCDR0_PID5 (0x1 << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */ +#define PMC_PCDR0_PID6 (0x1 << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */ +#define PMC_PCDR0_PID7 (0x1 << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */ +#define PMC_PCDR0_PID8 (0x1 << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */ +#define PMC_PCDR0_PID9 (0x1 << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */ +#define PMC_PCDR0_PID10 (0x1 << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */ +#define PMC_PCDR0_PID11 (0x1 << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */ +#define PMC_PCDR0_PID12 (0x1 << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */ +#define PMC_PCDR0_PID13 (0x1 << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */ +#define PMC_PCDR0_PID14 (0x1 << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */ +#define PMC_PCDR0_PID15 (0x1 << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */ +#define PMC_PCDR0_PID16 (0x1 << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */ +#define PMC_PCDR0_PID17 (0x1 << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */ +#define PMC_PCDR0_PID18 (0x1 << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */ +#define PMC_PCDR0_PID19 (0x1 << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */ +#define PMC_PCDR0_PID20 (0x1 << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */ +#define PMC_PCDR0_PID21 (0x1 << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */ +#define PMC_PCDR0_PID22 (0x1 << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */ +#define PMC_PCDR0_PID23 (0x1 << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */ +#define PMC_PCDR0_PID24 (0x1 << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */ +#define PMC_PCDR0_PID25 (0x1 << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */ +#define PMC_PCDR0_PID26 (0x1 << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */ +#define PMC_PCDR0_PID27 (0x1 << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */ +#define PMC_PCDR0_PID28 (0x1 << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */ +#define PMC_PCDR0_PID29 (0x1 << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */ +#define PMC_PCDR0_PID30 (0x1 << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */ +#define PMC_PCDR0_PID31 (0x1 << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */ +/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */ +#define PMC_PCSR0_PID2 (0x1 << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */ +#define PMC_PCSR0_PID3 (0x1 << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */ +#define PMC_PCSR0_PID4 (0x1 << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */ +#define PMC_PCSR0_PID5 (0x1 << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */ +#define PMC_PCSR0_PID6 (0x1 << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */ +#define PMC_PCSR0_PID7 (0x1 << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */ +#define PMC_PCSR0_PID8 (0x1 << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */ +#define PMC_PCSR0_PID9 (0x1 << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */ +#define PMC_PCSR0_PID10 (0x1 << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */ +#define PMC_PCSR0_PID11 (0x1 << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */ +#define PMC_PCSR0_PID12 (0x1 << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */ +#define PMC_PCSR0_PID13 (0x1 << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */ +#define PMC_PCSR0_PID14 (0x1 << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */ +#define PMC_PCSR0_PID15 (0x1 << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */ +#define PMC_PCSR0_PID16 (0x1 << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */ +#define PMC_PCSR0_PID17 (0x1 << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */ +#define PMC_PCSR0_PID18 (0x1 << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */ +#define PMC_PCSR0_PID19 (0x1 << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */ +#define PMC_PCSR0_PID20 (0x1 << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */ +#define PMC_PCSR0_PID21 (0x1 << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */ +#define PMC_PCSR0_PID22 (0x1 << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */ +#define PMC_PCSR0_PID23 (0x1 << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */ +#define PMC_PCSR0_PID24 (0x1 << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */ +#define PMC_PCSR0_PID25 (0x1 << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */ +#define PMC_PCSR0_PID26 (0x1 << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */ +#define PMC_PCSR0_PID27 (0x1 << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */ +#define PMC_PCSR0_PID28 (0x1 << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */ +#define PMC_PCSR0_PID29 (0x1 << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */ +#define PMC_PCSR0_PID30 (0x1 << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */ +#define PMC_PCSR0_PID31 (0x1 << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */ +/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */ +#define CKGR_MOR_MOSCXTEN (0x1 << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */ +#define CKGR_MOR_MOSCXTBY (0x1 << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */ +#define CKGR_MOR_WAITMODE (0x1 << 2) /**< \brief (CKGR_MOR) Wait Mode Command */ +#define CKGR_MOR_MOSCRCEN (0x1 << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */ +#define CKGR_MOR_MOSCRCF (0x7 << 4) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */ +#define CKGR_MOR_MOSCXTST (0xff << 8) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */ +#define CKGR_MOR_KEY (0xff << 16) /**< \brief (CKGR_MOR) Password */ +#define CKGR_MOR_MOSCSEL (0x1 << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */ +#define CKGR_MOR_CFDEN (0x1 << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */ +/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */ +#define CKGR_MCFR_MAINF (0xffff << 0) /**< \brief (CKGR_MCFR) Main Clock Frequency */ +#define CKGR_MCFR_MAINFRDY (0x1 << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */ +/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */ +#define CKGR_PLLAR_DIVA (0xff << 0) /**< \brief (CKGR_PLLAR) Divider */ +#define CKGR_PLLAR_PLLACOUNT (0x3f << 8) /**< \brief (CKGR_PLLAR) PLLA Counter */ +#define CKGR_PLLAR_MULA (0x7ff << 16) /**< \brief (CKGR_PLLAR) PLLA Multiplier */ +#define CKGR_PLLAR_STUCKTO1 (0x1 << 29) /**< \brief (CKGR_PLLAR) */ +/* -------- CKGR_PLLBR : (PMC Offset: 0x002C) PLLB Register -------- */ +#define CKGR_PLLBR_DIVB_Pos 0 +#define CKGR_PLLBR_DIVB_Msk (0xffu << CKGR_PLLBR_DIVB_Pos) /**< \brief (CKGR_PLLBR) Divider */ +#define CKGR_PLLBR_DIVB(value) ((CKGR_PLLBR_DIVB_Msk & ((value) << CKGR_PLLBR_DIVB_Pos))) +#define CKGR_PLLBR_PLLBCOUNT (0x3f << 8) /**< \brief (CKGR_PLLBR) PLLB Counter */ +#define CKGR_PLLBR_MULB_Pos 16 +#define CKGR_PLLBR_MULB_Msk (0x7ffu << CKGR_PLLBR_MULB_Pos) /**< \brief (CKGR_PLLBR) PLLB Multiplier */ +#define CKGR_PLLBR_MULB(value) ((CKGR_PLLBR_MULB_Msk & ((value) << CKGR_PLLBR_MULB_Pos))) +/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */ +#define PMC_MCKR_CSS (0x3 << 0) /**< \brief (PMC_MCKR) Master Clock Source Selection */ +#define PMC_MCKR_CSS_SLOW_CLK (0x0 << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */ +#define PMC_MCKR_CSS_MAIN_CLK (0x1 << 0) /**< \brief (PMC_MCKR) Main Clock is selected */ +#define PMC_MCKR_CSS_PLLA_CLK (0x2 << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ +#define PMC_MCKR_CSS_PLLB_CLK (0x3 << 0) /**< \brief (PMC_MCKR) PLLB Clock is selected */ +#define PMC_MCKR_PRES (0x7 << 4) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ +#define PMC_MCKR_PRES_CLK (0x0 << 4) /**< \brief (PMC_MCKR) Selected clock */ +#define PMC_MCKR_PRES_CLK_2 (0x1 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ +#define PMC_MCKR_PRES_CLK_4 (0x2 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ +#define PMC_MCKR_PRES_CLK_8 (0x3 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ +#define PMC_MCKR_PRES_CLK_16 (0x4 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */ +#define PMC_MCKR_PRES_CLK_32 (0x5 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */ +#define PMC_MCKR_PRES_CLK_64 (0x6 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */ +#define PMC_MCKR_PLLADIV2 (0x1 << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */ +#define PMC_MCKR_PLLBDIV2 (0x1 << 13) /**< \brief (PMC_MCKR) PLLB Divisor by 2 */ +/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */ +#define PMC_USB_USBS (0x1 << 0) /**< \brief (PMC_USB) USB Input Clock Selection */ +#define PMC_USB_USBDIV_Pos 8 +#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock. */ +#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)))/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */ +#define PMC_PCK_CSS (0x7 << 0) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */ +#define PMC_PCK_PRES (0x7 << 4) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */ +/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ +#define PMC_IER_MOSCXTS (0x1 << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */ +#define PMC_IER_LOCKA (0x1 << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ +#define PMC_IER_LOCKB (0x1 << 2) /**< \brief (PMC_IER) PLLB Lock Interrupt Enable */ +#define PMC_IER_MCKRDY (0x1 << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ +#define PMC_IER_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ +#define PMC_IER_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ +#define PMC_IER_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */ +#define PMC_IER_MOSCSELS (0x1 << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */ +#define PMC_IER_MOSCRCS (0x1 << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */ +#define PMC_IER_CFDEV (0x1 << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */ +/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */ +#define PMC_IDR_MOSCXTS (0x1 << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */ +#define PMC_IDR_LOCKA (0x1 << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */ +#define PMC_IDR_LOCKB (0x1 << 2) /**< \brief (PMC_IDR) PLLB Lock Interrupt Disable */ +#define PMC_IDR_MCKRDY (0x1 << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ +#define PMC_IDR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ +#define PMC_IDR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ +#define PMC_IDR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */ +#define PMC_IDR_MOSCSELS (0x1 << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */ +#define PMC_IDR_MOSCRCS (0x1 << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */ +#define PMC_IDR_CFDEV (0x1 << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */ +/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */ +#define PMC_SR_MOSCXTS (0x1 << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */ +#define PMC_SR_LOCKA (0x1 << 1) /**< \brief (PMC_SR) PLLA Lock Status */ +#define PMC_SR_LOCKB (0x1 << 2) /**< \brief (PMC_SR) PLLB Lock Status */ +#define PMC_SR_MCKRDY (0x1 << 3) /**< \brief (PMC_SR) Master Clock Status */ +#define PMC_SR_OSCSELS (0x1 << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */ +#define PMC_SR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_MOSCSELS (0x1 << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */ +#define PMC_SR_MOSCRCS (0x1 << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */ +#define PMC_SR_CFDEV (0x1 << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */ +#define PMC_SR_CFDS (0x1 << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */ +#define PMC_SR_FOS (0x1 << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */ +/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */ +#define PMC_IMR_MOSCXTS (0x1 << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */ +#define PMC_IMR_LOCKA (0x1 << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */ +#define PMC_IMR_LOCKB (0x1 << 2) /**< \brief (PMC_IMR) PLLB Lock Interrupt Mask */ +#define PMC_IMR_MCKRDY (0x1 << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ +#define PMC_IMR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ +#define PMC_IMR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ +#define PMC_IMR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */ +#define PMC_IMR_MOSCSELS (0x1 << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */ +#define PMC_IMR_MOSCRCS (0x1 << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */ +#define PMC_IMR_CFDEV (0x1 << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */ +/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */ +#define PMC_FSMR_FSTT0 (0x1 << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */ +#define PMC_FSMR_FSTT1 (0x1 << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */ +#define PMC_FSMR_FSTT2 (0x1 << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */ +#define PMC_FSMR_FSTT3 (0x1 << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */ +#define PMC_FSMR_FSTT4 (0x1 << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */ +#define PMC_FSMR_FSTT5 (0x1 << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */ +#define PMC_FSMR_FSTT6 (0x1 << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */ +#define PMC_FSMR_FSTT7 (0x1 << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */ +#define PMC_FSMR_FSTT8 (0x1 << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */ +#define PMC_FSMR_FSTT9 (0x1 << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */ +#define PMC_FSMR_FSTT10 (0x1 << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */ +#define PMC_FSMR_FSTT11 (0x1 << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */ +#define PMC_FSMR_FSTT12 (0x1 << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */ +#define PMC_FSMR_FSTT13 (0x1 << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */ +#define PMC_FSMR_FSTT14 (0x1 << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */ +#define PMC_FSMR_FSTT15 (0x1 << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */ +#define PMC_FSMR_RTTAL (0x1 << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */ +#define PMC_FSMR_RTCAL (0x1 << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */ +#define PMC_FSMR_USBAL (0x1 << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */ +#define PMC_FSMR_LPM (0x1 << 20) /**< \brief (PMC_FSMR) Low Power Mode */ +/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */ +#define PMC_FSPR_FSTP0 (0x1 << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP1 (0x1 << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP2 (0x1 << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP3 (0x1 << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP4 (0x1 << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP5 (0x1 << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP6 (0x1 << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP7 (0x1 << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP8 (0x1 << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP9 (0x1 << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP10 (0x1 << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP11 (0x1 << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP12 (0x1 << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP13 (0x1 << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP14 (0x1 << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP15 (0x1 << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */ +#define PMC_FOCR_FOCLR (0x1 << 0) /**< \brief (PMC_FOCR) Fault Output Clear */ +/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */ +#define PMC_WPMR_WPEN (0x1 << 0) /**< \brief (PMC_WPMR) Write Protect Enable */ +#define PMC_WPMR_WPKEY (0xffffff << 8) /**< \brief (PMC_WPMR) Write Protect KEY */ +/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */ +#define PMC_WPSR_WPVS (0x1 << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */ +#define PMC_WPSR_WPVSRC (0xffff << 8) /**< \brief (PMC_WPSR) Write Protect Violation Source */ +/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */ +#define PMC_PCER1_PID32 (0x1 << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */ +#define PMC_PCER1_PID33 (0x1 << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */ +#define PMC_PCER1_PID34 (0x1 << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */ +#define PMC_PCER1_PID35 (0x1 << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */ +#define PMC_PCER1_PID36 (0x1 << 4) /**< \brief (PMC_PCER1) Peripheral Clock 36 Enable */ +#define PMC_PCER1_PID37 (0x1 << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */ +#define PMC_PCER1_PID38 (0x1 << 6) /**< \brief (PMC_PCER1) Peripheral Clock 38 Enable */ +#define PMC_PCER1_PID39 (0x1 << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */ +#define PMC_PCER1_PID40 (0x1 << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */ +#define PMC_PCER1_PID41 (0x1 << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */ +#define PMC_PCER1_PID42 (0x1 << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */ +#define PMC_PCER1_PID43 (0x1 << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */ +#define PMC_PCER1_PID44 (0x1 << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */ +#define PMC_PCER1_PID45 (0x1 << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */ +#define PMC_PCER1_PID46 (0x1 << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */ +#define PMC_PCER1_PID47 (0x1 << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */ +#define PMC_PCER1_PID48 (0x1 << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */ +#define PMC_PCER1_PID49 (0x1 << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */ +#define PMC_PCER1_PID50 (0x1 << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */ +#define PMC_PCER1_PID51 (0x1 << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */ +#define PMC_PCER1_PID52 (0x1 << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */ +#define PMC_PCER1_PID53 (0x1 << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */ +#define PMC_PCER1_PID54 (0x1 << 22) /**< \brief (PMC_PCER1) Peripheral Clock 54 Enable */ +#define PMC_PCER1_PID55 (0x1 << 23) /**< \brief (PMC_PCER1) Peripheral Clock 55 Enable */ +#define PMC_PCER1_PID56 (0x1 << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */ +#define PMC_PCER1_PID57 (0x1 << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */ +#define PMC_PCER1_PID58 (0x1 << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */ +#define PMC_PCER1_PID59 (0x1 << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */ +#define PMC_PCER1_PID60 (0x1 << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */ +#define PMC_PCER1_PID61 (0x1 << 29) /**< \brief (PMC_PCER1) Peripheral Clock 61 Enable */ +#define PMC_PCER1_PID62 (0x1 << 30) /**< \brief (PMC_PCER1) Peripheral Clock 62 Enable */ +#define PMC_PCER1_PID63 (0x1 << 31) /**< \brief (PMC_PCER1) Peripheral Clock 63 Enable */ +/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */ +#define PMC_PCDR1_PID32 (0x1 << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */ +#define PMC_PCDR1_PID33 (0x1 << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */ +#define PMC_PCDR1_PID34 (0x1 << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */ +#define PMC_PCDR1_PID35 (0x1 << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */ +#define PMC_PCDR1_PID36 (0x1 << 4) /**< \brief (PMC_PCDR1) Peripheral Clock 36 Disable */ +#define PMC_PCDR1_PID37 (0x1 << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */ +#define PMC_PCDR1_PID38 (0x1 << 6) /**< \brief (PMC_PCDR1) Peripheral Clock 38 Disable */ +#define PMC_PCDR1_PID39 (0x1 << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */ +#define PMC_PCDR1_PID40 (0x1 << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */ +#define PMC_PCDR1_PID41 (0x1 << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */ +#define PMC_PCDR1_PID42 (0x1 << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */ +#define PMC_PCDR1_PID43 (0x1 << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */ +#define PMC_PCDR1_PID44 (0x1 << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */ +#define PMC_PCDR1_PID45 (0x1 << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */ +#define PMC_PCDR1_PID46 (0x1 << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */ +#define PMC_PCDR1_PID47 (0x1 << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */ +#define PMC_PCDR1_PID48 (0x1 << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */ +#define PMC_PCDR1_PID49 (0x1 << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */ +#define PMC_PCDR1_PID50 (0x1 << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */ +#define PMC_PCDR1_PID51 (0x1 << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */ +#define PMC_PCDR1_PID52 (0x1 << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */ +#define PMC_PCDR1_PID53 (0x1 << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */ +#define PMC_PCDR1_PID54 (0x1 << 22) /**< \brief (PMC_PCDR1) Peripheral Clock 54 Disable */ +#define PMC_PCDR1_PID55 (0x1 << 23) /**< \brief (PMC_PCDR1) Peripheral Clock 55 Disable */ +#define PMC_PCDR1_PID56 (0x1 << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */ +#define PMC_PCDR1_PID57 (0x1 << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */ +#define PMC_PCDR1_PID58 (0x1 << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */ +#define PMC_PCDR1_PID59 (0x1 << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */ +#define PMC_PCDR1_PID60 (0x1 << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */ +#define PMC_PCDR1_PID61 (0x1 << 29) /**< \brief (PMC_PCDR1) Peripheral Clock 61 Disable */ +#define PMC_PCDR1_PID62 (0x1 << 30) /**< \brief (PMC_PCDR1) Peripheral Clock 62 Disable */ +#define PMC_PCDR1_PID63 (0x1 << 31) /**< \brief (PMC_PCDR1) Peripheral Clock 63 Disable */ +/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */ +#define PMC_PCSR1_PID32 (0x1 << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */ +#define PMC_PCSR1_PID33 (0x1 << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */ +#define PMC_PCSR1_PID34 (0x1 << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */ +#define PMC_PCSR1_PID35 (0x1 << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */ +#define PMC_PCSR1_PID36 (0x1 << 4) /**< \brief (PMC_PCSR1) Peripheral Clock 36 Status */ +#define PMC_PCSR1_PID37 (0x1 << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */ +#define PMC_PCSR1_PID38 (0x1 << 6) /**< \brief (PMC_PCSR1) Peripheral Clock 38 Status */ +#define PMC_PCSR1_PID39 (0x1 << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */ +#define PMC_PCSR1_PID40 (0x1 << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */ +#define PMC_PCSR1_PID41 (0x1 << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */ +#define PMC_PCSR1_PID42 (0x1 << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */ +#define PMC_PCSR1_PID43 (0x1 << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */ +#define PMC_PCSR1_PID44 (0x1 << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */ +#define PMC_PCSR1_PID45 (0x1 << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */ +#define PMC_PCSR1_PID46 (0x1 << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */ +#define PMC_PCSR1_PID47 (0x1 << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */ +#define PMC_PCSR1_PID48 (0x1 << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */ +#define PMC_PCSR1_PID49 (0x1 << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */ +#define PMC_PCSR1_PID50 (0x1 << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */ +#define PMC_PCSR1_PID51 (0x1 << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */ +#define PMC_PCSR1_PID52 (0x1 << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */ +#define PMC_PCSR1_PID53 (0x1 << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */ +#define PMC_PCSR1_PID54 (0x1 << 22) /**< \brief (PMC_PCSR1) Peripheral Clock 54 Status */ +#define PMC_PCSR1_PID55 (0x1 << 23) /**< \brief (PMC_PCSR1) Peripheral Clock 55 Status */ +#define PMC_PCSR1_PID56 (0x1 << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */ +#define PMC_PCSR1_PID57 (0x1 << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */ +#define PMC_PCSR1_PID58 (0x1 << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */ +#define PMC_PCSR1_PID59 (0x1 << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */ +#define PMC_PCSR1_PID60 (0x1 << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */ +#define PMC_PCSR1_PID61 (0x1 << 29) /**< \brief (PMC_PCSR1) Peripheral Clock 61 Status */ +#define PMC_PCSR1_PID62 (0x1 << 30) /**< \brief (PMC_PCSR1) Peripheral Clock 62 Status */ +#define PMC_PCSR1_PID63 (0x1 << 31) /**< \brief (PMC_PCSR1) Peripheral Clock 63 Status */ +/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */ +#define PMC_OCR_CAL4 (0x7f << 0) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 Mhz */ +#define PMC_OCR_SEL4 (0x1 << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 Mhz */ +#define PMC_OCR_CAL8 (0x7f << 8) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 Mhz */ +#define PMC_OCR_SEL8 (0x1 << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 Mhz */ +#define PMC_OCR_CAL12 (0x7f << 16) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 Mhz */ +#define PMC_OCR_SEL12 (0x1 << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 Mhz */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_PWM Pulse Width Modulation Controller */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief PwmCh_num hardware registers */ +typedef struct { + RwReg PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */ + RwReg PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */ + RwReg PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */ + RwReg PWM_CPDR; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */ + RwReg PWM_CPDRUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */ + RwReg PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */ + RwReg PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */ + RwReg PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */ +} PwmCh_num; +/** \brief Pwm hardware registers */ +typedef struct { + RwReg PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */ + WoReg PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */ + WoReg PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */ + RoReg PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */ + WoReg PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */ + WoReg PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */ + RoReg PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */ + RoReg PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */ + RwReg PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */ + RwReg Reserved1[1]; + RwReg PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */ + RwReg PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */ + WoReg PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */ + WoReg PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */ + WoReg PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */ + RoReg PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */ + RoReg PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */ + RwReg PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */ + RwReg PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */ + WoReg PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */ + WoReg PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */ + WoReg PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */ + WoReg PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */ + RwReg PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */ + RoReg PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */ + WoReg PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */ + RwReg PWM_FPV; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */ + RwReg PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */ + RwReg Reserved2[3]; + RwReg PWM_ELxMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */ + RwReg Reserved3[11]; + RwReg PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */ + RwReg Reserved4[12]; + WoReg PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */ + RoReg PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */ + RwReg Reserved5[5]; + RwReg PWM_RPR; /**< \brief (Pwm Offset: 0x100) Receive Pointer Register */ + RwReg PWM_RCR; /**< \brief (Pwm Offset: 0x104) Receive Counter Register */ + RwReg PWM_TPR; /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */ + RwReg PWM_TCR; /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */ + RwReg PWM_RNPR; /**< \brief (Pwm Offset: 0x110) Receive Next Pointer Register */ + RwReg PWM_RNCR; /**< \brief (Pwm Offset: 0x114) Receive Next Counter Register */ + RwReg PWM_TNPR; /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */ + RwReg PWM_TNCR; /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */ + WoReg PWM_PTCR; /**< \brief (Pwm Offset: 0x120) Transfer Control Register */ + RoReg PWM_PTSR; /**< \brief (Pwm Offset: 0x124) Transfer Status Register */ + RwReg Reserved6[2]; + RwReg PWM_CMP0V; /**< \brief (Pwm Offset: 0x130) PWM Comparison 0 Value Register */ + WoReg PWM_CMP0VUPD; /**< \brief (Pwm Offset: 0x134) PWM Comparison 0 Value Update Register */ + RwReg PWM_CMP0M; /**< \brief (Pwm Offset: 0x138) PWM Comparison 0 Mode Register */ + WoReg PWM_CMP0MUPD; /**< \brief (Pwm Offset: 0x13C) PWM Comparison 0 Mode Update Register */ + RwReg PWM_CMP1V; /**< \brief (Pwm Offset: 0x140) PWM Comparison 1 Value Register */ + WoReg PWM_CMP1VUPD; /**< \brief (Pwm Offset: 0x144) PWM Comparison 1 Value Update Register */ + RwReg PWM_CMP1M; /**< \brief (Pwm Offset: 0x148) PWM Comparison 1 Mode Register */ + WoReg PWM_CMP1MUPD; /**< \brief (Pwm Offset: 0x14C) PWM Comparison 1 Mode Update Register */ + RwReg PWM_CMP2V; /**< \brief (Pwm Offset: 0x150) PWM Comparison 2 Value Register */ + WoReg PWM_CMP2VUPD; /**< \brief (Pwm Offset: 0x154) PWM Comparison 2 Value Update Register */ + RwReg PWM_CMP2M; /**< \brief (Pwm Offset: 0x158) PWM Comparison 2 Mode Register */ + WoReg PWM_CMP2MUPD; /**< \brief (Pwm Offset: 0x15C) PWM Comparison 2 Mode Update Register */ + RwReg PWM_CMP3V; /**< \brief (Pwm Offset: 0x160) PWM Comparison 3 Value Register */ + WoReg PWM_CMP3VUPD; /**< \brief (Pwm Offset: 0x164) PWM Comparison 3 Value Update Register */ + RwReg PWM_CMP3M; /**< \brief (Pwm Offset: 0x168) PWM Comparison 3 Mode Register */ + WoReg PWM_CMP3MUPD; /**< \brief (Pwm Offset: 0x16C) PWM Comparison 3 Mode Update Register */ + RwReg PWM_CMP4V; /**< \brief (Pwm Offset: 0x170) PWM Comparison 4 Value Register */ + WoReg PWM_CMP4VUPD; /**< \brief (Pwm Offset: 0x174) PWM Comparison 4 Value Update Register */ + RwReg PWM_CMP4M; /**< \brief (Pwm Offset: 0x178) PWM Comparison 4 Mode Register */ + WoReg PWM_CMP4MUPD; /**< \brief (Pwm Offset: 0x17C) PWM Comparison 4 Mode Update Register */ + RwReg PWM_CMP5V; /**< \brief (Pwm Offset: 0x180) PWM Comparison 5 Value Register */ + WoReg PWM_CMP5VUPD; /**< \brief (Pwm Offset: 0x184) PWM Comparison 5 Value Update Register */ + RwReg PWM_CMP5M; /**< \brief (Pwm Offset: 0x188) PWM Comparison 5 Mode Register */ + WoReg PWM_CMP5MUPD; /**< \brief (Pwm Offset: 0x18C) PWM Comparison 5 Mode Update Register */ + RwReg PWM_CMP6V; /**< \brief (Pwm Offset: 0x190) PWM Comparison 6 Value Register */ + WoReg PWM_CMP6VUPD; /**< \brief (Pwm Offset: 0x194) PWM Comparison 6 Value Update Register */ + RwReg PWM_CMP6M; /**< \brief (Pwm Offset: 0x198) PWM Comparison 6 Mode Register */ + WoReg PWM_CMP6MUPD; /**< \brief (Pwm Offset: 0x19C) PWM Comparison 6 Mode Update Register */ + RwReg PWM_CMP7V; /**< \brief (Pwm Offset: 0x1A0) PWM Comparison 7 Value Register */ + WoReg PWM_CMP7VUPD; /**< \brief (Pwm Offset: 0x1A4) PWM Comparison 7 Value Update Register */ + RwReg PWM_CMP7M; /**< \brief (Pwm Offset: 0x1A8) PWM Comparison 7 Mode Register */ + WoReg PWM_CMP7MUPD; /**< \brief (Pwm Offset: 0x1AC) PWM Comparison 7 Mode Update Register */ + RwReg Reserved7[20]; + PwmCh_num PWM_CH_NUM[4]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */ +} Pwm; +#endif /* __ASSEMBLY__ */ +/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */ +#define PWM_CLK_DIVA (0xff << 0) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ +#define PWM_CLK_PREA (0xf << 8) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ +#define PWM_CLK_DIVB (0xff << 16) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ +#define PWM_CLK_PREB (0xf << 24) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ +/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */ +#define PWM_ENA_CHID0 (0x1 << 0) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID1 (0x1 << 1) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID2 (0x1 << 2) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID3 (0x1 << 3) /**< \brief (PWM_ENA) Channel ID */ +/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */ +#define PWM_DIS_CHID0 (0x1 << 0) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID1 (0x1 << 1) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID2 (0x1 << 2) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID3 (0x1 << 3) /**< \brief (PWM_DIS) Channel ID */ +/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */ +#define PWM_SR_CHID0 (0x1 << 0) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID1 (0x1 << 1) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID2 (0x1 << 2) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID3 (0x1 << 3) /**< \brief (PWM_SR) Channel ID */ +/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */ +#define PWM_IER1_CHID0 (0x1 << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */ +#define PWM_IER1_CHID1 (0x1 << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */ +#define PWM_IER1_CHID2 (0x1 << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */ +#define PWM_IER1_CHID3 (0x1 << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */ +#define PWM_IER1_FCHID0 (0x1 << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */ +#define PWM_IER1_FCHID1 (0x1 << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */ +#define PWM_IER1_FCHID2 (0x1 << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */ +#define PWM_IER1_FCHID3 (0x1 << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */ +/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */ +#define PWM_IDR1_CHID0 (0x1 << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */ +#define PWM_IDR1_CHID1 (0x1 << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */ +#define PWM_IDR1_CHID2 (0x1 << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */ +#define PWM_IDR1_CHID3 (0x1 << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */ +#define PWM_IDR1_FCHID0 (0x1 << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */ +#define PWM_IDR1_FCHID1 (0x1 << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */ +#define PWM_IDR1_FCHID2 (0x1 << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */ +#define PWM_IDR1_FCHID3 (0x1 << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */ +/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */ +#define PWM_IMR1_CHID0 (0x1 << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */ +#define PWM_IMR1_CHID1 (0x1 << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */ +#define PWM_IMR1_CHID2 (0x1 << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */ +#define PWM_IMR1_CHID3 (0x1 << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */ +#define PWM_IMR1_FCHID0 (0x1 << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */ +#define PWM_IMR1_FCHID1 (0x1 << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */ +#define PWM_IMR1_FCHID2 (0x1 << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */ +#define PWM_IMR1_FCHID3 (0x1 << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */ +/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */ +#define PWM_ISR1_CHID0 (0x1 << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */ +#define PWM_ISR1_CHID1 (0x1 << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */ +#define PWM_ISR1_CHID2 (0x1 << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */ +#define PWM_ISR1_CHID3 (0x1 << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */ +#define PWM_ISR1_FCHID0 (0x1 << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */ +#define PWM_ISR1_FCHID1 (0x1 << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */ +#define PWM_ISR1_FCHID2 (0x1 << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */ +#define PWM_ISR1_FCHID3 (0x1 << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */ +/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */ +#define PWM_SCM_SYNC0 (0x1 << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */ +#define PWM_SCM_SYNC1 (0x1 << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */ +#define PWM_SCM_SYNC2 (0x1 << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */ +#define PWM_SCM_SYNC3 (0x1 << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */ +#define PWM_SCM_UPDM (0x3 << 16) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */ +#define PWM_SCM_PTRM (0x1 << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */ +#define PWM_SCM_PTRCS (0x7 << 21) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */ +/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */ +#define PWM_SCUC_UPDULOCK (0x1 << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */ +/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */ +#define PWM_SCUP_UPR (0xf << 0) /**< \brief (PWM_SCUP) Update Period */ +#define PWM_SCUP_UPRCNT (0xf << 4) /**< \brief (PWM_SCUP) Update Period Counter */ +/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */ +#define PWM_SCUPUPD_UPRUPD (0xf << 0) /**< \brief (PWM_SCUPUPD) Update Period Update */ +/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */ +#define PWM_IER2_WRDY (0x1 << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */ +#define PWM_IER2_ENDTX (0x1 << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */ +#define PWM_IER2_TXBUFE (0x1 << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */ +#define PWM_IER2_UNRE (0x1 << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */ +#define PWM_IER2_CMPM0 (0x1 << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */ +#define PWM_IER2_CMPM1 (0x1 << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */ +#define PWM_IER2_CMPM2 (0x1 << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */ +#define PWM_IER2_CMPM3 (0x1 << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */ +#define PWM_IER2_CMPM4 (0x1 << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */ +#define PWM_IER2_CMPM5 (0x1 << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */ +#define PWM_IER2_CMPM6 (0x1 << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */ +#define PWM_IER2_CMPM7 (0x1 << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */ +#define PWM_IER2_CMPU0 (0x1 << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */ +#define PWM_IER2_CMPU1 (0x1 << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */ +#define PWM_IER2_CMPU2 (0x1 << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */ +#define PWM_IER2_CMPU3 (0x1 << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */ +#define PWM_IER2_CMPU4 (0x1 << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */ +#define PWM_IER2_CMPU5 (0x1 << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */ +#define PWM_IER2_CMPU6 (0x1 << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */ +#define PWM_IER2_CMPU7 (0x1 << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */ +/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */ +#define PWM_IDR2_WRDY (0x1 << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */ +#define PWM_IDR2_ENDTX (0x1 << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */ +#define PWM_IDR2_TXBUFE (0x1 << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */ +#define PWM_IDR2_UNRE (0x1 << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */ +#define PWM_IDR2_CMPM0 (0x1 << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */ +#define PWM_IDR2_CMPM1 (0x1 << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */ +#define PWM_IDR2_CMPM2 (0x1 << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */ +#define PWM_IDR2_CMPM3 (0x1 << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */ +#define PWM_IDR2_CMPM4 (0x1 << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */ +#define PWM_IDR2_CMPM5 (0x1 << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */ +#define PWM_IDR2_CMPM6 (0x1 << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */ +#define PWM_IDR2_CMPM7 (0x1 << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */ +#define PWM_IDR2_CMPU0 (0x1 << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */ +#define PWM_IDR2_CMPU1 (0x1 << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */ +#define PWM_IDR2_CMPU2 (0x1 << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */ +#define PWM_IDR2_CMPU3 (0x1 << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */ +#define PWM_IDR2_CMPU4 (0x1 << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */ +#define PWM_IDR2_CMPU5 (0x1 << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */ +#define PWM_IDR2_CMPU6 (0x1 << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */ +#define PWM_IDR2_CMPU7 (0x1 << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */ +/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */ +#define PWM_IMR2_WRDY (0x1 << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */ +#define PWM_IMR2_ENDTX (0x1 << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */ +#define PWM_IMR2_TXBUFE (0x1 << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */ +#define PWM_IMR2_UNRE (0x1 << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */ +#define PWM_IMR2_CMPM0 (0x1 << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */ +#define PWM_IMR2_CMPM1 (0x1 << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */ +#define PWM_IMR2_CMPM2 (0x1 << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */ +#define PWM_IMR2_CMPM3 (0x1 << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */ +#define PWM_IMR2_CMPM4 (0x1 << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */ +#define PWM_IMR2_CMPM5 (0x1 << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */ +#define PWM_IMR2_CMPM6 (0x1 << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */ +#define PWM_IMR2_CMPM7 (0x1 << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */ +#define PWM_IMR2_CMPU0 (0x1 << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */ +#define PWM_IMR2_CMPU1 (0x1 << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */ +#define PWM_IMR2_CMPU2 (0x1 << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */ +#define PWM_IMR2_CMPU3 (0x1 << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */ +#define PWM_IMR2_CMPU4 (0x1 << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */ +#define PWM_IMR2_CMPU5 (0x1 << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */ +#define PWM_IMR2_CMPU6 (0x1 << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */ +#define PWM_IMR2_CMPU7 (0x1 << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */ +/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */ +#define PWM_ISR2_WRDY (0x1 << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */ +#define PWM_ISR2_ENDTX (0x1 << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */ +#define PWM_ISR2_TXBUFE (0x1 << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */ +#define PWM_ISR2_UNRE (0x1 << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */ +#define PWM_ISR2_CMPM0 (0x1 << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */ +#define PWM_ISR2_CMPM1 (0x1 << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */ +#define PWM_ISR2_CMPM2 (0x1 << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */ +#define PWM_ISR2_CMPM3 (0x1 << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */ +#define PWM_ISR2_CMPM4 (0x1 << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */ +#define PWM_ISR2_CMPM5 (0x1 << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */ +#define PWM_ISR2_CMPM6 (0x1 << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */ +#define PWM_ISR2_CMPM7 (0x1 << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */ +#define PWM_ISR2_CMPU0 (0x1 << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */ +#define PWM_ISR2_CMPU1 (0x1 << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */ +#define PWM_ISR2_CMPU2 (0x1 << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */ +#define PWM_ISR2_CMPU3 (0x1 << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */ +#define PWM_ISR2_CMPU4 (0x1 << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */ +#define PWM_ISR2_CMPU5 (0x1 << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */ +#define PWM_ISR2_CMPU6 (0x1 << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */ +#define PWM_ISR2_CMPU7 (0x1 << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */ +/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */ +#define PWM_OOV_OOVH0 (0x1 << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */ +#define PWM_OOV_OOVH1 (0x1 << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */ +#define PWM_OOV_OOVH2 (0x1 << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */ +#define PWM_OOV_OOVH3 (0x1 << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */ +#define PWM_OOV_OOVL0 (0x1 << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */ +#define PWM_OOV_OOVL1 (0x1 << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */ +#define PWM_OOV_OOVL2 (0x1 << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */ +#define PWM_OOV_OOVL3 (0x1 << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */ +/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */ +#define PWM_OS_OSH0 (0x1 << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */ +#define PWM_OS_OSH1 (0x1 << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */ +#define PWM_OS_OSH2 (0x1 << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */ +#define PWM_OS_OSH3 (0x1 << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */ +#define PWM_OS_OSL0 (0x1 << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */ +#define PWM_OS_OSL1 (0x1 << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */ +#define PWM_OS_OSL2 (0x1 << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */ +#define PWM_OS_OSL3 (0x1 << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */ +/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */ +#define PWM_OSS_OSSH0 (0x1 << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSS_OSSH1 (0x1 << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSS_OSSH2 (0x1 << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSS_OSSH3 (0x1 << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSS_OSSL0 (0x1 << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSS_OSSL1 (0x1 << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSS_OSSL2 (0x1 << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSS_OSSL3 (0x1 << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */ +#define PWM_OSC_OSCH0 (0x1 << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSC_OSCH1 (0x1 << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSC_OSCH2 (0x1 << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSC_OSCH3 (0x1 << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSC_OSCL0 (0x1 << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSC_OSCL1 (0x1 << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSC_OSCL2 (0x1 << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSC_OSCL3 (0x1 << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */ +#define PWM_OSSUPD_OSSUPH0 (0x1 << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSSUPD_OSSUPH1 (0x1 << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSSUPD_OSSUPH2 (0x1 << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSSUPD_OSSUPH3 (0x1 << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSSUPD_OSSUPL0 (0x1 << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSSUPD_OSSUPL1 (0x1 << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSSUPD_OSSUPL2 (0x1 << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSSUPD_OSSUPL3 (0x1 << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */ +#define PWM_OSCUPD_OSCUPH0 (0x1 << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSCUPD_OSCUPH1 (0x1 << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSCUPD_OSCUPH2 (0x1 << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSCUPD_OSCUPH3 (0x1 << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSCUPD_OSCUPL0 (0x1 << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSCUPD_OSCUPL1 (0x1 << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSCUPD_OSCUPL2 (0x1 << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSCUPD_OSCUPL3 (0x1 << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */ +#define PWM_FMR_FPOL0 (0x1 << 0) /**< \brief (PWM_FMR) Fault 0 Polarity */ +#define PWM_FMR_FPOL1 (0x1 << 1) /**< \brief (PWM_FMR) Fault 1 Polarity */ +#define PWM_FMR_FPOL2 (0x1 << 2) /**< \brief (PWM_FMR) Fault 2 Polarity */ +#define PWM_FMR_FPOL3 (0x1 << 3) /**< \brief (PWM_FMR) Fault 3 Polarity */ +#define PWM_FMR_FMOD0 (0x1 << 8) /**< \brief (PWM_FMR) Fault 0 Activation Mode */ +#define PWM_FMR_FMOD1 (0x1 << 9) /**< \brief (PWM_FMR) Fault 1 Activation Mode */ +#define PWM_FMR_FMOD2 (0x1 << 10) /**< \brief (PWM_FMR) Fault 2 Activation Mode */ +#define PWM_FMR_FMOD3 (0x1 << 11) /**< \brief (PWM_FMR) Fault 3 Activation Mode */ +#define PWM_FMR_FFIL0 (0x1 << 16) /**< \brief (PWM_FMR) Fault 0 Filtering */ +#define PWM_FMR_FFIL1 (0x1 << 17) /**< \brief (PWM_FMR) Fault 1 Filtering */ +#define PWM_FMR_FFIL2 (0x1 << 18) /**< \brief (PWM_FMR) Fault 2 Filtering */ +#define PWM_FMR_FFIL3 (0x1 << 19) /**< \brief (PWM_FMR) Fault 3 Filtering */ +/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */ +#define PWM_FSR_FIV0 (0x1 << 0) /**< \brief (PWM_FSR) Fault Input 0 Value */ +#define PWM_FSR_FIV1 (0x1 << 1) /**< \brief (PWM_FSR) Fault Input 1 Value */ +#define PWM_FSR_FIV2 (0x1 << 2) /**< \brief (PWM_FSR) Fault Input 2 Value */ +#define PWM_FSR_FIV3 (0x1 << 3) /**< \brief (PWM_FSR) Fault Input 3 Value */ +#define PWM_FSR_FS0 (0x1 << 8) /**< \brief (PWM_FSR) Fault 0 Status */ +#define PWM_FSR_FS1 (0x1 << 9) /**< \brief (PWM_FSR) Fault 1 Status */ +#define PWM_FSR_FS2 (0x1 << 10) /**< \brief (PWM_FSR) Fault 2 Status */ +#define PWM_FSR_FS3 (0x1 << 11) /**< \brief (PWM_FSR) Fault 3 Status */ +/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */ +#define PWM_FCR_FCLR0 (0x1 << 0) /**< \brief (PWM_FCR) Fault 0 Clear */ +#define PWM_FCR_FCLR1 (0x1 << 1) /**< \brief (PWM_FCR) Fault 1 Clear */ +#define PWM_FCR_FCLR2 (0x1 << 2) /**< \brief (PWM_FCR) Fault 2 Clear */ +#define PWM_FCR_FCLR3 (0x1 << 3) /**< \brief (PWM_FCR) Fault 3 Clear */ +/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */ +#define PWM_FPV_FPVH0 (0x1 << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */ +#define PWM_FPV_FPVH1 (0x1 << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */ +#define PWM_FPV_FPVH2 (0x1 << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */ +#define PWM_FPV_FPVH3 (0x1 << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */ +#define PWM_FPV_FPVL0 (0x1 << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */ +#define PWM_FPV_FPVL1 (0x1 << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */ +#define PWM_FPV_FPVL2 (0x1 << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */ +#define PWM_FPV_FPVL3 (0x1 << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */ +/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */ +#define PWM_FPE_FPE0 (0xff << 0) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 0 for channel x */ +#define PWM_FPE_FPE1 (0xff << 8) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 1 for channel x */ +#define PWM_FPE_FPE2 (0xff << 16) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 2 for channel x */ +#define PWM_FPE_FPE3 (0xff << 24) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 3 for channel x */ +/* -------- PWM_ELxMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */ +#define PWM_ELxMR_CSEL0 (0x1 << 0) /**< \brief (PWM_ELxMR[2]) Comparison 0 Selection */ +#define PWM_ELxMR_CSEL1 (0x1 << 1) /**< \brief (PWM_ELxMR[2]) Comparison 1 Selection */ +#define PWM_ELxMR_CSEL2 (0x1 << 2) /**< \brief (PWM_ELxMR[2]) Comparison 2 Selection */ +#define PWM_ELxMR_CSEL3 (0x1 << 3) /**< \brief (PWM_ELxMR[2]) Comparison 3 Selection */ +#define PWM_ELxMR_CSEL4 (0x1 << 4) /**< \brief (PWM_ELxMR[2]) Comparison 4 Selection */ +#define PWM_ELxMR_CSEL5 (0x1 << 5) /**< \brief (PWM_ELxMR[2]) Comparison 5 Selection */ +#define PWM_ELxMR_CSEL6 (0x1 << 6) /**< \brief (PWM_ELxMR[2]) Comparison 6 Selection */ +#define PWM_ELxMR_CSEL7 (0x1 << 7) /**< \brief (PWM_ELxMR[2]) Comparison 7 Selection */ +/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */ +#define PWM_SMMR_GCEN0 (0x1 << 0) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_GCEN1 (0x1 << 1) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_DOWN0 (0x1 << 16) /**< \brief (PWM_SMMR) DOWN Count */ +#define PWM_SMMR_DOWN1 (0x1 << 17) /**< \brief (PWM_SMMR) DOWN Count */ +/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */ +#define PWM_WPCR_WPCMD (0x3 << 0) /**< \brief (PWM_WPCR) Write Protect Command */ +#define PWM_WPCR_WPRG0 (0x1 << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */ +#define PWM_WPCR_WPRG1 (0x1 << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */ +#define PWM_WPCR_WPRG2 (0x1 << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */ +#define PWM_WPCR_WPRG3 (0x1 << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */ +#define PWM_WPCR_WPRG4 (0x1 << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */ +#define PWM_WPCR_WPRG5 (0x1 << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */ +#define PWM_WPCR_WPKEY (0xffffff << 8) /**< \brief (PWM_WPCR) Write Protect Key */ +/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */ +#define PWM_WPSR_WPSWS0 (0x1 << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS1 (0x1 << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS2 (0x1 << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS3 (0x1 << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS4 (0x1 << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS5 (0x1 << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPVS (0x1 << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */ +#define PWM_WPSR_WPHWS0 (0x1 << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS1 (0x1 << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS2 (0x1 << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS3 (0x1 << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS4 (0x1 << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS5 (0x1 << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPVSRC (0xffff << 16) /**< \brief (PWM_WPSR) Write Protect Violation Source */ +/* -------- PWM_RPR : (PWM Offset: 0x100) Receive Pointer Register -------- */ +#define PWM_RPR_RXPTR (0xffffffff << 0) /**< \brief (PWM_RPR) Receive Pointer Register */ +/* -------- PWM_RCR : (PWM Offset: 0x104) Receive Counter Register -------- */ +#define PWM_RCR_RXCTR (0xffff << 0) /**< \brief (PWM_RCR) Receive Counter Register */ +/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */ +#define PWM_TPR_TXPTR (0xffffffff << 0) /**< \brief (PWM_TPR) Transmit Counter Register */ +/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */ +#define PWM_TCR_TXCTR (0xffff << 0) /**< \brief (PWM_TCR) Transmit Counter Register */ +/* -------- PWM_RNPR : (PWM Offset: 0x110) Receive Next Pointer Register -------- */ +#define PWM_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (PWM_RNPR) Receive Next Pointer */ +/* -------- PWM_RNCR : (PWM Offset: 0x114) Receive Next Counter Register -------- */ +#define PWM_RNCR_RXNCTR (0xffff << 0) /**< \brief (PWM_RNCR) Receive Next Counter */ +/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */ +#define PWM_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (PWM_TNPR) Transmit Next Pointer */ +/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */ +#define PWM_TNCR_TXNCTR (0xffff << 0) /**< \brief (PWM_TNCR) Transmit Counter Next */ +/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */ +#define PWM_PTCR_RXTEN (0x1 << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */ +#define PWM_PTCR_RXTDIS (0x1 << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */ +#define PWM_PTCR_TXTEN (0x1 << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */ +#define PWM_PTCR_TXTDIS (0x1 << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */ +/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */ +#define PWM_PTSR_RXTEN (0x1 << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */ +#define PWM_PTSR_TXTEN (0x1 << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */ +/* -------- PWM_CMP0V : (PWM Offset: 0x130) PWM Comparison 0 Value Register -------- */ +#define PWM_CMP0V_CV (0xffffff << 0) /**< \brief (PWM_CMP0V) Comparison x Value */ +#define PWM_CMP0V_CVM (0x1 << 24) /**< \brief (PWM_CMP0V) Comparison x Value Mode */ +/* -------- PWM_CMP0VUPD : (PWM Offset: 0x134) PWM Comparison 0 Value Update Register -------- */ +#define PWM_CMP0VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP0VUPD) Comparison x Value Update */ +#define PWM_CMP0VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP0VUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMP0M : (PWM Offset: 0x138) PWM Comparison 0 Mode Register -------- */ +#define PWM_CMP0M_CEN (0x1 << 0) /**< \brief (PWM_CMP0M) Comparison x Enable */ +#define PWM_CMP0M_CTR (0xf << 4) /**< \brief (PWM_CMP0M) Comparison x Trigger */ +#define PWM_CMP0M_CPR (0xf << 8) /**< \brief (PWM_CMP0M) Comparison x Period */ +#define PWM_CMP0M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP0M) Comparison x Period Counter */ +#define PWM_CMP0M_CUPR (0xf << 16) /**< \brief (PWM_CMP0M) Comparison x Update Period */ +#define PWM_CMP0M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP0M) Comparison x Update Period Counter */ +/* -------- PWM_CMP0MUPD : (PWM Offset: 0x13C) PWM Comparison 0 Mode Update Register -------- */ +#define PWM_CMP0MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP0MUPD) Comparison x Enable Update */ +#define PWM_CMP0MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP0MUPD) Comparison x Trigger Update */ +#define PWM_CMP0MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP0MUPD) Comparison x Period Update */ +#define PWM_CMP0MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP0MUPD) Comparison x Update Period Update */ +/* -------- PWM_CMP1V : (PWM Offset: 0x140) PWM Comparison 1 Value Register -------- */ +#define PWM_CMP1V_CV (0xffffff << 0) /**< \brief (PWM_CMP1V) Comparison x Value */ +#define PWM_CMP1V_CVM (0x1 << 24) /**< \brief (PWM_CMP1V) Comparison x Value Mode */ +/* -------- PWM_CMP1VUPD : (PWM Offset: 0x144) PWM Comparison 1 Value Update Register -------- */ +#define PWM_CMP1VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP1VUPD) Comparison x Value Update */ +#define PWM_CMP1VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP1VUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMP1M : (PWM Offset: 0x148) PWM Comparison 1 Mode Register -------- */ +#define PWM_CMP1M_CEN (0x1 << 0) /**< \brief (PWM_CMP1M) Comparison x Enable */ +#define PWM_CMP1M_CTR (0xf << 4) /**< \brief (PWM_CMP1M) Comparison x Trigger */ +#define PWM_CMP1M_CPR (0xf << 8) /**< \brief (PWM_CMP1M) Comparison x Period */ +#define PWM_CMP1M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP1M) Comparison x Period Counter */ +#define PWM_CMP1M_CUPR (0xf << 16) /**< \brief (PWM_CMP1M) Comparison x Update Period */ +#define PWM_CMP1M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP1M) Comparison x Update Period Counter */ +/* -------- PWM_CMP1MUPD : (PWM Offset: 0x14C) PWM Comparison 1 Mode Update Register -------- */ +#define PWM_CMP1MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP1MUPD) Comparison x Enable Update */ +#define PWM_CMP1MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP1MUPD) Comparison x Trigger Update */ +#define PWM_CMP1MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP1MUPD) Comparison x Period Update */ +#define PWM_CMP1MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP1MUPD) Comparison x Update Period Update */ +/* -------- PWM_CMP2V : (PWM Offset: 0x150) PWM Comparison 2 Value Register -------- */ +#define PWM_CMP2V_CV (0xffffff << 0) /**< \brief (PWM_CMP2V) Comparison x Value */ +#define PWM_CMP2V_CVM (0x1 << 24) /**< \brief (PWM_CMP2V) Comparison x Value Mode */ +/* -------- PWM_CMP2VUPD : (PWM Offset: 0x154) PWM Comparison 2 Value Update Register -------- */ +#define PWM_CMP2VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP2VUPD) Comparison x Value Update */ +#define PWM_CMP2VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP2VUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMP2M : (PWM Offset: 0x158) PWM Comparison 2 Mode Register -------- */ +#define PWM_CMP2M_CEN (0x1 << 0) /**< \brief (PWM_CMP2M) Comparison x Enable */ +#define PWM_CMP2M_CTR (0xf << 4) /**< \brief (PWM_CMP2M) Comparison x Trigger */ +#define PWM_CMP2M_CPR (0xf << 8) /**< \brief (PWM_CMP2M) Comparison x Period */ +#define PWM_CMP2M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP2M) Comparison x Period Counter */ +#define PWM_CMP2M_CUPR (0xf << 16) /**< \brief (PWM_CMP2M) Comparison x Update Period */ +#define PWM_CMP2M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP2M) Comparison x Update Period Counter */ +/* -------- PWM_CMP2MUPD : (PWM Offset: 0x15C) PWM Comparison 2 Mode Update Register -------- */ +#define PWM_CMP2MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP2MUPD) Comparison x Enable Update */ +#define PWM_CMP2MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP2MUPD) Comparison x Trigger Update */ +#define PWM_CMP2MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP2MUPD) Comparison x Period Update */ +#define PWM_CMP2MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP2MUPD) Comparison x Update Period Update */ +/* -------- PWM_CMP3V : (PWM Offset: 0x160) PWM Comparison 3 Value Register -------- */ +#define PWM_CMP3V_CV (0xffffff << 0) /**< \brief (PWM_CMP3V) Comparison x Value */ +#define PWM_CMP3V_CVM (0x1 << 24) /**< \brief (PWM_CMP3V) Comparison x Value Mode */ +/* -------- PWM_CMP3VUPD : (PWM Offset: 0x164) PWM Comparison 3 Value Update Register -------- */ +#define PWM_CMP3VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP3VUPD) Comparison x Value Update */ +#define PWM_CMP3VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP3VUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMP3M : (PWM Offset: 0x168) PWM Comparison 3 Mode Register -------- */ +#define PWM_CMP3M_CEN (0x1 << 0) /**< \brief (PWM_CMP3M) Comparison x Enable */ +#define PWM_CMP3M_CTR (0xf << 4) /**< \brief (PWM_CMP3M) Comparison x Trigger */ +#define PWM_CMP3M_CPR (0xf << 8) /**< \brief (PWM_CMP3M) Comparison x Period */ +#define PWM_CMP3M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP3M) Comparison x Period Counter */ +#define PWM_CMP3M_CUPR (0xf << 16) /**< \brief (PWM_CMP3M) Comparison x Update Period */ +#define PWM_CMP3M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP3M) Comparison x Update Period Counter */ +/* -------- PWM_CMP3MUPD : (PWM Offset: 0x16C) PWM Comparison 3 Mode Update Register -------- */ +#define PWM_CMP3MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP3MUPD) Comparison x Enable Update */ +#define PWM_CMP3MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP3MUPD) Comparison x Trigger Update */ +#define PWM_CMP3MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP3MUPD) Comparison x Period Update */ +#define PWM_CMP3MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP3MUPD) Comparison x Update Period Update */ +/* -------- PWM_CMP4V : (PWM Offset: 0x170) PWM Comparison 4 Value Register -------- */ +#define PWM_CMP4V_CV (0xffffff << 0) /**< \brief (PWM_CMP4V) Comparison x Value */ +#define PWM_CMP4V_CVM (0x1 << 24) /**< \brief (PWM_CMP4V) Comparison x Value Mode */ +/* -------- PWM_CMP4VUPD : (PWM Offset: 0x174) PWM Comparison 4 Value Update Register -------- */ +#define PWM_CMP4VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP4VUPD) Comparison x Value Update */ +#define PWM_CMP4VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP4VUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMP4M : (PWM Offset: 0x178) PWM Comparison 4 Mode Register -------- */ +#define PWM_CMP4M_CEN (0x1 << 0) /**< \brief (PWM_CMP4M) Comparison x Enable */ +#define PWM_CMP4M_CTR (0xf << 4) /**< \brief (PWM_CMP4M) Comparison x Trigger */ +#define PWM_CMP4M_CPR (0xf << 8) /**< \brief (PWM_CMP4M) Comparison x Period */ +#define PWM_CMP4M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP4M) Comparison x Period Counter */ +#define PWM_CMP4M_CUPR (0xf << 16) /**< \brief (PWM_CMP4M) Comparison x Update Period */ +#define PWM_CMP4M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP4M) Comparison x Update Period Counter */ +/* -------- PWM_CMP4MUPD : (PWM Offset: 0x17C) PWM Comparison 4 Mode Update Register -------- */ +#define PWM_CMP4MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP4MUPD) Comparison x Enable Update */ +#define PWM_CMP4MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP4MUPD) Comparison x Trigger Update */ +#define PWM_CMP4MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP4MUPD) Comparison x Period Update */ +#define PWM_CMP4MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP4MUPD) Comparison x Update Period Update */ +/* -------- PWM_CMP5V : (PWM Offset: 0x180) PWM Comparison 5 Value Register -------- */ +#define PWM_CMP5V_CV (0xffffff << 0) /**< \brief (PWM_CMP5V) Comparison x Value */ +#define PWM_CMP5V_CVM (0x1 << 24) /**< \brief (PWM_CMP5V) Comparison x Value Mode */ +/* -------- PWM_CMP5VUPD : (PWM Offset: 0x184) PWM Comparison 5 Value Update Register -------- */ +#define PWM_CMP5VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP5VUPD) Comparison x Value Update */ +#define PWM_CMP5VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP5VUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMP5M : (PWM Offset: 0x188) PWM Comparison 5 Mode Register -------- */ +#define PWM_CMP5M_CEN (0x1 << 0) /**< \brief (PWM_CMP5M) Comparison x Enable */ +#define PWM_CMP5M_CTR (0xf << 4) /**< \brief (PWM_CMP5M) Comparison x Trigger */ +#define PWM_CMP5M_CPR (0xf << 8) /**< \brief (PWM_CMP5M) Comparison x Period */ +#define PWM_CMP5M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP5M) Comparison x Period Counter */ +#define PWM_CMP5M_CUPR (0xf << 16) /**< \brief (PWM_CMP5M) Comparison x Update Period */ +#define PWM_CMP5M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP5M) Comparison x Update Period Counter */ +/* -------- PWM_CMP5MUPD : (PWM Offset: 0x18C) PWM Comparison 5 Mode Update Register -------- */ +#define PWM_CMP5MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP5MUPD) Comparison x Enable Update */ +#define PWM_CMP5MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP5MUPD) Comparison x Trigger Update */ +#define PWM_CMP5MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP5MUPD) Comparison x Period Update */ +#define PWM_CMP5MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP5MUPD) Comparison x Update Period Update */ +/* -------- PWM_CMP6V : (PWM Offset: 0x190) PWM Comparison 6 Value Register -------- */ +#define PWM_CMP6V_CV (0xffffff << 0) /**< \brief (PWM_CMP6V) Comparison x Value */ +#define PWM_CMP6V_CVM (0x1 << 24) /**< \brief (PWM_CMP6V) Comparison x Value Mode */ +/* -------- PWM_CMP6VUPD : (PWM Offset: 0x194) PWM Comparison 6 Value Update Register -------- */ +#define PWM_CMP6VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP6VUPD) Comparison x Value Update */ +#define PWM_CMP6VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP6VUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMP6M : (PWM Offset: 0x198) PWM Comparison 6 Mode Register -------- */ +#define PWM_CMP6M_CEN (0x1 << 0) /**< \brief (PWM_CMP6M) Comparison x Enable */ +#define PWM_CMP6M_CTR (0xf << 4) /**< \brief (PWM_CMP6M) Comparison x Trigger */ +#define PWM_CMP6M_CPR (0xf << 8) /**< \brief (PWM_CMP6M) Comparison x Period */ +#define PWM_CMP6M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP6M) Comparison x Period Counter */ +#define PWM_CMP6M_CUPR (0xf << 16) /**< \brief (PWM_CMP6M) Comparison x Update Period */ +#define PWM_CMP6M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP6M) Comparison x Update Period Counter */ +/* -------- PWM_CMP6MUPD : (PWM Offset: 0x19C) PWM Comparison 6 Mode Update Register -------- */ +#define PWM_CMP6MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP6MUPD) Comparison x Enable Update */ +#define PWM_CMP6MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP6MUPD) Comparison x Trigger Update */ +#define PWM_CMP6MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP6MUPD) Comparison x Period Update */ +#define PWM_CMP6MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP6MUPD) Comparison x Update Period Update */ +/* -------- PWM_CMP7V : (PWM Offset: 0x1A0) PWM Comparison 7 Value Register -------- */ +#define PWM_CMP7V_CV (0xffffff << 0) /**< \brief (PWM_CMP7V) Comparison x Value */ +#define PWM_CMP7V_CVM (0x1 << 24) /**< \brief (PWM_CMP7V) Comparison x Value Mode */ +/* -------- PWM_CMP7VUPD : (PWM Offset: 0x1A4) PWM Comparison 7 Value Update Register -------- */ +#define PWM_CMP7VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP7VUPD) Comparison x Value Update */ +#define PWM_CMP7VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP7VUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMP7M : (PWM Offset: 0x1A8) PWM Comparison 7 Mode Register -------- */ +#define PWM_CMP7M_CEN (0x1 << 0) /**< \brief (PWM_CMP7M) Comparison x Enable */ +#define PWM_CMP7M_CTR (0xf << 4) /**< \brief (PWM_CMP7M) Comparison x Trigger */ +#define PWM_CMP7M_CPR (0xf << 8) /**< \brief (PWM_CMP7M) Comparison x Period */ +#define PWM_CMP7M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP7M) Comparison x Period Counter */ +#define PWM_CMP7M_CUPR (0xf << 16) /**< \brief (PWM_CMP7M) Comparison x Update Period */ +#define PWM_CMP7M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP7M) Comparison x Update Period Counter */ +/* -------- PWM_CMP7MUPD : (PWM Offset: 0x1AC) PWM Comparison 7 Mode Update Register -------- */ +#define PWM_CMP7MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP7MUPD) Comparison x Enable Update */ +#define PWM_CMP7MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP7MUPD) Comparison x Trigger Update */ +#define PWM_CMP7MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP7MUPD) Comparison x Period Update */ +#define PWM_CMP7MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP7MUPD) Comparison x Update Period Update */ +/* -------- PWM_CMR0 : (PWM Offset: 0x200) PWM Channel Mode Register (ch_num = 0) -------- */ +#define PWM_CMR0_CPRE (0xf << 0) /**< \brief (PWM_CMR0) Channel Pre-scaler */ +#define PWM_CMR0_CALG (0x1 << 8) /**< \brief (PWM_CMR0) Channel Alignment */ +#define PWM_CMR0_CPOL (0x1 << 9) /**< \brief (PWM_CMR0) Channel Polarity */ +#define PWM_CMR0_CES (0x1 << 10) /**< \brief (PWM_CMR0) Counter Event Selection */ +#define PWM_CMR0_DTE (0x1 << 16) /**< \brief (PWM_CMR0) Dead-Time Generator Enable */ +#define PWM_CMR0_DTHI (0x1 << 17) /**< \brief (PWM_CMR0) Dead-Time PWMHx Output Inverted */ +#define PWM_CMR0_DTLI (0x1 << 18) /**< \brief (PWM_CMR0) Dead-Time PWMLx Output Inverted */ +/* -------- PWM_CDTY0 : (PWM Offset: 0x204) PWM Channel Duty Cycle Register (ch_num = 0) -------- */ +#define PWM_CDTY0_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY0) Channel Duty-Cycle */ +/* -------- PWM_CDTYUPD0 : (PWM Offset: 0x208) PWM Channel Duty Cycle Update Register (ch_num = 0) -------- */ +#define PWM_CDTYUPD0_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD0) Channel Duty-Cycle Update */ +/* -------- PWM_CPRD0 : (PWM Offset: 0x20C) PWM Channel Period Register (ch_num = 0) -------- */ +#define PWM_CPRD0_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD0) Channel Period */ +/* -------- PWM_CPRDUPD0 : (PWM Offset: 0x210) PWM Channel Period Update Register (ch_num = 0) -------- */ +#define PWM_CPRDUPD0_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD0) Channel Period Update */ +/* -------- PWM_CCNT0 : (PWM Offset: 0x214) PWM Channel Counter Register (ch_num = 0) -------- */ +#define PWM_CCNT0_CNT (0xffffff << 0) /**< \brief (PWM_CCNT0) Channel Counter Register */ +/* -------- PWM_DT0 : (PWM Offset: 0x218) PWM Channel Dead Time Register (ch_num = 0) -------- */ +#define PWM_DT0_DTH (0xffff << 0) /**< \brief (PWM_DT0) Dead-Time Value for PWMHx Output */ +#define PWM_DT0_DTL (0xffff << 16) /**< \brief (PWM_DT0) Dead-Time Value for PWMLx Output */ +/* -------- PWM_DTUPD0 : (PWM Offset: 0x21C) PWM Channel Dead Time Update Register (ch_num = 0) -------- */ +#define PWM_DTUPD0_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD0) Dead-Time Value Update for PWMHx Output */ +#define PWM_DTUPD0_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD0) Dead-Time Value Update for PWMLx Output */ +/* -------- PWM_CMR1 : (PWM Offset: 0x220) PWM Channel Mode Register (ch_num = 1) -------- */ +#define PWM_CMR1_CPRE (0xf << 0) /**< \brief (PWM_CMR1) Channel Pre-scaler */ +#define PWM_CMR1_CALG (0x1 << 8) /**< \brief (PWM_CMR1) Channel Alignment */ +#define PWM_CMR1_CPOL (0x1 << 9) /**< \brief (PWM_CMR1) Channel Polarity */ +#define PWM_CMR1_CES (0x1 << 10) /**< \brief (PWM_CMR1) Counter Event Selection */ +#define PWM_CMR1_DTE (0x1 << 16) /**< \brief (PWM_CMR1) Dead-Time Generator Enable */ +#define PWM_CMR1_DTHI (0x1 << 17) /**< \brief (PWM_CMR1) Dead-Time PWMHx Output Inverted */ +#define PWM_CMR1_DTLI (0x1 << 18) /**< \brief (PWM_CMR1) Dead-Time PWMLx Output Inverted */ +/* -------- PWM_CDTY1 : (PWM Offset: 0x224) PWM Channel Duty Cycle Register (ch_num = 1) -------- */ +#define PWM_CDTY1_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY1) Channel Duty-Cycle */ +/* -------- PWM_CDTYUPD1 : (PWM Offset: 0x228) PWM Channel Duty Cycle Update Register (ch_num = 1) -------- */ +#define PWM_CDTYUPD1_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD1) Channel Duty-Cycle Update */ +/* -------- PWM_CPRD1 : (PWM Offset: 0x22C) PWM Channel Period Register (ch_num = 1) -------- */ +#define PWM_CPRD1_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD1) Channel Period */ +/* -------- PWM_CPRDUPD1 : (PWM Offset: 0x230) PWM Channel Period Update Register (ch_num = 1) -------- */ +#define PWM_CPRDUPD1_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD1) Channel Period Update */ +/* -------- PWM_CCNT1 : (PWM Offset: 0x234) PWM Channel Counter Register (ch_num = 1) -------- */ +#define PWM_CCNT1_CNT (0xffffff << 0) /**< \brief (PWM_CCNT1) Channel Counter Register */ +/* -------- PWM_DT1 : (PWM Offset: 0x238) PWM Channel Dead Time Register (ch_num = 1) -------- */ +#define PWM_DT1_DTH (0xffff << 0) /**< \brief (PWM_DT1) Dead-Time Value for PWMHx Output */ +#define PWM_DT1_DTL (0xffff << 16) /**< \brief (PWM_DT1) Dead-Time Value for PWMLx Output */ +/* -------- PWM_DTUPD1 : (PWM Offset: 0x23C) PWM Channel Dead Time Update Register (ch_num = 1) -------- */ +#define PWM_DTUPD1_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD1) Dead-Time Value Update for PWMHx Output */ +#define PWM_DTUPD1_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD1) Dead-Time Value Update for PWMLx Output */ +/* -------- PWM_CMR2 : (PWM Offset: 0x240) PWM Channel Mode Register (ch_num = 2) -------- */ +#define PWM_CMR2_CPRE (0xf << 0) /**< \brief (PWM_CMR2) Channel Pre-scaler */ +#define PWM_CMR2_CALG (0x1 << 8) /**< \brief (PWM_CMR2) Channel Alignment */ +#define PWM_CMR2_CPOL (0x1 << 9) /**< \brief (PWM_CMR2) Channel Polarity */ +#define PWM_CMR2_CES (0x1 << 10) /**< \brief (PWM_CMR2) Counter Event Selection */ +#define PWM_CMR2_DTE (0x1 << 16) /**< \brief (PWM_CMR2) Dead-Time Generator Enable */ +#define PWM_CMR2_DTHI (0x1 << 17) /**< \brief (PWM_CMR2) Dead-Time PWMHx Output Inverted */ +#define PWM_CMR2_DTLI (0x1 << 18) /**< \brief (PWM_CMR2) Dead-Time PWMLx Output Inverted */ +/* -------- PWM_CDTY2 : (PWM Offset: 0x244) PWM Channel Duty Cycle Register (ch_num = 2) -------- */ +#define PWM_CDTY2_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY2) Channel Duty-Cycle */ +/* -------- PWM_CDTYUPD2 : (PWM Offset: 0x248) PWM Channel Duty Cycle Update Register (ch_num = 2) -------- */ +#define PWM_CDTYUPD2_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD2) Channel Duty-Cycle Update */ +/* -------- PWM_CPRD2 : (PWM Offset: 0x24C) PWM Channel Period Register (ch_num = 2) -------- */ +#define PWM_CPRD2_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD2) Channel Period */ +/* -------- PWM_CPRDUPD2 : (PWM Offset: 0x250) PWM Channel Period Update Register (ch_num = 2) -------- */ +#define PWM_CPRDUPD2_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD2) Channel Period Update */ +/* -------- PWM_CCNT2 : (PWM Offset: 0x254) PWM Channel Counter Register (ch_num = 2) -------- */ +#define PWM_CCNT2_CNT (0xffffff << 0) /**< \brief (PWM_CCNT2) Channel Counter Register */ +/* -------- PWM_DT2 : (PWM Offset: 0x258) PWM Channel Dead Time Register (ch_num = 2) -------- */ +#define PWM_DT2_DTH (0xffff << 0) /**< \brief (PWM_DT2) Dead-Time Value for PWMHx Output */ +#define PWM_DT2_DTL (0xffff << 16) /**< \brief (PWM_DT2) Dead-Time Value for PWMLx Output */ +/* -------- PWM_DTUPD2 : (PWM Offset: 0x25C) PWM Channel Dead Time Update Register (ch_num = 2) -------- */ +#define PWM_DTUPD2_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD2) Dead-Time Value Update for PWMHx Output */ +#define PWM_DTUPD2_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD2) Dead-Time Value Update for PWMLx Output */ +/* -------- PWM_CMR3 : (PWM Offset: 0x260) PWM Channel Mode Register (ch_num = 3) -------- */ +#define PWM_CMR3_CPRE (0xf << 0) /**< \brief (PWM_CMR3) Channel Pre-scaler */ +#define PWM_CMR3_CALG (0x1 << 8) /**< \brief (PWM_CMR3) Channel Alignment */ +#define PWM_CMR3_CPOL (0x1 << 9) /**< \brief (PWM_CMR3) Channel Polarity */ +#define PWM_CMR3_CES (0x1 << 10) /**< \brief (PWM_CMR3) Counter Event Selection */ +#define PWM_CMR3_DTE (0x1 << 16) /**< \brief (PWM_CMR3) Dead-Time Generator Enable */ +#define PWM_CMR3_DTHI (0x1 << 17) /**< \brief (PWM_CMR3) Dead-Time PWMHx Output Inverted */ +#define PWM_CMR3_DTLI (0x1 << 18) /**< \brief (PWM_CMR3) Dead-Time PWMLx Output Inverted */ +/* -------- PWM_CDTY3 : (PWM Offset: 0x264) PWM Channel Duty Cycle Register (ch_num = 3) -------- */ +#define PWM_CDTY3_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY3) Channel Duty-Cycle */ +/* -------- PWM_CDTYUPD3 : (PWM Offset: 0x268) PWM Channel Duty Cycle Update Register (ch_num = 3) -------- */ +#define PWM_CDTYUPD3_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD3) Channel Duty-Cycle Update */ +/* -------- PWM_CPRD3 : (PWM Offset: 0x26C) PWM Channel Period Register (ch_num = 3) -------- */ +#define PWM_CPRD3_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD3) Channel Period */ +/* -------- PWM_CPRDUPD3 : (PWM Offset: 0x270) PWM Channel Period Update Register (ch_num = 3) -------- */ +#define PWM_CPRDUPD3_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD3) Channel Period Update */ +/* -------- PWM_CCNT3 : (PWM Offset: 0x274) PWM Channel Counter Register (ch_num = 3) -------- */ +#define PWM_CCNT3_CNT (0xffffff << 0) /**< \brief (PWM_CCNT3) Channel Counter Register */ +/* -------- PWM_DT3 : (PWM Offset: 0x278) PWM Channel Dead Time Register (ch_num = 3) -------- */ +#define PWM_DT3_DTH (0xffff << 0) /**< \brief (PWM_DT3) Dead-Time Value for PWMHx Output */ +#define PWM_DT3_DTL (0xffff << 16) /**< \brief (PWM_DT3) Dead-Time Value for PWMLx Output */ +/* -------- PWM_DTUPD3 : (PWM Offset: 0x27C) PWM Channel Dead Time Update Register (ch_num = 3) -------- */ +#define PWM_DTUPD3_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD3) Dead-Time Value Update for PWMHx Output */ +#define PWM_DTUPD3_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD3) Dead-Time Value Update for PWMLx Output */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Reset Controller */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_RSTC Reset Controller */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Rstc hardware registers */ +typedef struct { + WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */ + RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */ + RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */ +} Rstc; +#endif /* __ASSEMBLY__ */ +/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ +#define RSTC_CR_PROCRST (0x1 << 0) /**< \brief (RSTC_CR) Processor Reset */ +#define RSTC_CR_PERRST (0x1 << 2) /**< \brief (RSTC_CR) Peripheral Reset */ +#define RSTC_CR_EXTRST (0x1 << 3) /**< \brief (RSTC_CR) External Reset */ +#define RSTC_CR_KEY (0xff << 24) /**< \brief (RSTC_CR) Password */ +/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ +#define RSTC_SR_URSTS (0x1 << 0) /**< \brief (RSTC_SR) User Reset Status */ +#define RSTC_SR_RSTTYP (0x7 << 8) /**< \brief (RSTC_SR) Reset Type */ +#define RSTC_SR_NRSTL (0x1 << 16) /**< \brief (RSTC_SR) NRST Pin Level */ +#define RSTC_SR_SRCMP (0x1 << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ +/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ +#define RSTC_MR_URSTEN (0x1 << 0) /**< \brief (RSTC_MR) User Reset Enable */ +#define RSTC_MR_URSTIEN (0x1 << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */ +#define RSTC_MR_ERSTL (0xf << 8) /**< \brief (RSTC_MR) External Reset Length */ +#define RSTC_MR_KEY (0xff << 24) /**< \brief (RSTC_MR) Password */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Clock */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_RTC Real-time Clock */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Rtc hardware registers */ +typedef struct { + RwReg RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */ + RwReg RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */ + RwReg RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */ + RwReg RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */ + RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */ + RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */ + RoReg RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */ + WoReg RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */ + WoReg RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */ + WoReg RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */ + RoReg RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */ + RoReg RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */ +} Rtc; +#endif /* __ASSEMBLY__ */ +/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */ +#define RTC_CR_UPDTIM (0x1 << 0) /**< \brief (RTC_CR) Update Request Time Register */ +#define RTC_CR_UPDCAL (0x1 << 1) /**< \brief (RTC_CR) Update Request Calendar Register */ +#define RTC_CR_TIMEVSEL (0x3 << 8) /**< \brief (RTC_CR) Time Event Selection */ +#define RTC_CR_TIMEVSEL_MINUTE (0x0 << 8) /**< \brief (RTC_CR) Minute change. */ +#define RTC_CR_TIMEVSEL_HOUR (0x1 << 8) /**< \brief (RTC_CR) Hour change. */ +#define RTC_CR_TIMEVSEL_DAY24 (0x2 << 8) /**< \brief (RTC_CR) Every day at midnight. */ +#define RTC_CR_TIMEVSEL_DAY12 (0x3 << 8) /**< \brief (RTC_CR) Every day at noon. */ +#define RTC_CR_CALEVSEL (0x3 << 16) /**< \brief (RTC_CR) Calendar Event Selection */ +#define RTC_CR_CALEVSEL_WEEK (0x0 << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00). */ +#define RTC_CR_CALEVSEL_MONTH (0x1 << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00). */ +/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */ +#define RTC_MR_HRMOD (0x1 << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */ +/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */ +#define RTC_TIMR_SEC (0x7f << 0) /**< \brief (RTC_TIMR) Current Second */ +#define RTC_TIMR_MIN (0x7f << 8) /**< \brief (RTC_TIMR) Current Minute */ +#define RTC_TIMR_HOUR (0x3f << 16) /**< \brief (RTC_TIMR) Current Hour */ +#define RTC_TIMR_AMPM (0x1 << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */ +/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */ +#define RTC_CALR_CENT (0x7f << 0) /**< \brief (RTC_CALR) Current Century */ +#define RTC_CALR_YEAR (0xff << 8) /**< \brief (RTC_CALR) Current Year */ +#define RTC_CALR_MONTH (0x1f << 16) /**< \brief (RTC_CALR) Current Month */ +#define RTC_CALR_DAY (0x7 << 21) /**< \brief (RTC_CALR) Current Day in Current Week */ +#define RTC_CALR_DATE (0x3f << 24) /**< \brief (RTC_CALR) Current Day in Current Month */ +/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */ +#define RTC_TIMALR_SEC (0x7f << 0) /**< \brief (RTC_TIMALR) Second Alarm */ +#define RTC_TIMALR_SECEN (0x1 << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */ +#define RTC_TIMALR_MIN (0x7f << 8) /**< \brief (RTC_TIMALR) Minute Alarm */ +#define RTC_TIMALR_MINEN (0x1 << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */ +#define RTC_TIMALR_HOUR (0x3f << 16) /**< \brief (RTC_TIMALR) Hour Alarm */ +#define RTC_TIMALR_AMPM (0x1 << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */ +#define RTC_TIMALR_HOUREN (0x1 << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */ +/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */ +#define RTC_CALALR_MONTH (0x1f << 16) /**< \brief (RTC_CALALR) Month Alarm */ +#define RTC_CALALR_MTHEN (0x1 << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */ +#define RTC_CALALR_DATE (0x3f << 24) /**< \brief (RTC_CALALR) Date Alarm */ +#define RTC_CALALR_DATEEN (0x1 << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */ +/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */ +#define RTC_SR_ACKUPD (0x1 << 0) /**< \brief (RTC_SR) Acknowledge for Update */ +#define RTC_SR_ALARM (0x1 << 1) /**< \brief (RTC_SR) Alarm Flag */ +#define RTC_SR_SEC (0x1 << 2) /**< \brief (RTC_SR) Second Event */ +#define RTC_SR_TIMEV (0x1 << 3) /**< \brief (RTC_SR) Time Event */ +#define RTC_SR_CALEV (0x1 << 4) /**< \brief (RTC_SR) Calendar Event */ +/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */ +#define RTC_SCCR_ACKCLR (0x1 << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */ +#define RTC_SCCR_ALRCLR (0x1 << 1) /**< \brief (RTC_SCCR) Alarm Clear */ +#define RTC_SCCR_SECCLR (0x1 << 2) /**< \brief (RTC_SCCR) Second Clear */ +#define RTC_SCCR_TIMCLR (0x1 << 3) /**< \brief (RTC_SCCR) Time Clear */ +#define RTC_SCCR_CALCLR (0x1 << 4) /**< \brief (RTC_SCCR) Calendar Clear */ +/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */ +#define RTC_IER_ACKEN (0x1 << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */ +#define RTC_IER_ALREN (0x1 << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */ +#define RTC_IER_SECEN (0x1 << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */ +#define RTC_IER_TIMEN (0x1 << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */ +#define RTC_IER_CALEN (0x1 << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */ +/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */ +#define RTC_IDR_ACKDIS (0x1 << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */ +#define RTC_IDR_ALRDIS (0x1 << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */ +#define RTC_IDR_SECDIS (0x1 << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */ +#define RTC_IDR_TIMDIS (0x1 << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */ +#define RTC_IDR_CALDIS (0x1 << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */ +/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */ +#define RTC_IMR_ACK (0x1 << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */ +#define RTC_IMR_ALR (0x1 << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */ +#define RTC_IMR_SEC (0x1 << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */ +#define RTC_IMR_TIM (0x1 << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */ +#define RTC_IMR_CAL (0x1 << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */ +/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */ +#define RTC_VER_NVTIM (0x1 << 0) /**< \brief (RTC_VER) Non-valid Time */ +#define RTC_VER_NVCAL (0x1 << 1) /**< \brief (RTC_VER) Non-valid Calendar */ +#define RTC_VER_NVTIMALR (0x1 << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */ +#define RTC_VER_NVCALALR (0x1 << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Timer */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_RTT Real-time Timer */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Rtt hardware registers */ +typedef struct { + RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */ + RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */ + RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */ + RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */ +} Rtt; +#endif /* __ASSEMBLY__ */ +/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */ +#define RTT_MR_RTPRES (0xffff << 0) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */ +#define RTT_MR_ALMIEN (0x1 << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */ +#define RTT_MR_RTTINCIEN (0x1 << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */ +#define RTT_MR_RTTRST (0x1 << 18) /**< \brief (RTT_MR) Real-time Timer Restart */ +/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */ +#define RTT_AR_ALMV (0xffffffff << 0) /**< \brief (RTT_AR) Alarm Value */ +/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */ +#define RTT_VR_CRTV (0xffffffff << 0) /**< \brief (RTT_VR) Current Real-time Value */ +/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */ +#define RTT_SR_ALMS (0x1 << 0) /**< \brief (RTT_SR) Real-time Alarm Status */ +#define RTT_SR_RTTINC (0x1 << 1) /**< \brief (RTT_SR) Real-time Timer Increment */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Static Memory Controller */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_SMC Static Memory Controller */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief SmcCs_number hardware registers */ +typedef struct { + RwReg SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */ + RwReg SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */ + RwReg SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */ + RwReg SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC Mode Register */ +} SmcCs_number; +/** \brief Smc hardware registers */ +typedef struct { + SmcCs_number SMC_CS_NUMBER[5]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 4 */ + RwReg Reserved1[12]; + RwReg SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */ + WoReg SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */ + WoReg SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */ + RwReg Reserved2[22]; + RwReg SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protect Mode Register */ + RoReg SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protect Status Register */ +} Smc; +#endif /* __ASSEMBLY__ */ +/* -------- SMC_SETUP0 : (SMC Offset: 0x0) SMC Setup Register (CS_number = 0) -------- */ +#define SMC_SETUP0_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP0) NWE Setup Length */ +#define SMC_SETUP0_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP0) NCS Setup Length in WRITE Access */ +#define SMC_SETUP0_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP0) NRD Setup Length */ +#define SMC_SETUP0_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP0) NCS Setup Length in READ Access */ +/* -------- SMC_PULSE0 : (SMC Offset: 0x4) SMC Pulse Register (CS_number = 0) -------- */ +#define SMC_PULSE0_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE0) NWE Pulse Length */ +#define SMC_PULSE0_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE0) NCS Pulse Length in WRITE Access */ +#define SMC_PULSE0_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE0) NRD Pulse Length */ +#define SMC_PULSE0_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE0) NCS Pulse Length in READ Access */ +/* -------- SMC_CYCLE0 : (SMC Offset: 0x8) SMC Cycle Register (CS_number = 0) -------- */ +#define SMC_CYCLE0_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE0) Total Write Cycle Length */ +#define SMC_CYCLE0_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE0) Total Read Cycle Length */ +/* -------- SMC_MODE0 : (SMC Offset: 0xC) SMC Mode Register (CS_number = 0) -------- */ +#define SMC_MODE0_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE0) */ +#define SMC_MODE0_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE0) */ +#define SMC_MODE0_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE0) NWAIT Mode */ +#define SMC_MODE0_DBW (0x3 << 12) /**< \brief (SMC_MODE0) Data Bus Width */ +#define SMC_MODE0_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE0) Data Float Time */ +#define SMC_MODE0_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE0) TDF Optimization */ +#define SMC_MODE0_PMEN (0x1 << 24) /**< \brief (SMC_MODE0) Page Mode Enabled */ +#define SMC_MODE0_PS (0x3 << 28) /**< \brief (SMC_MODE0) Page Size */ +/* -------- SMC_SETUP1 : (SMC Offset: 0x10) SMC Setup Register (CS_number = 1) -------- */ +#define SMC_SETUP1_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP1) NWE Setup Length */ +#define SMC_SETUP1_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP1) NCS Setup Length in WRITE Access */ +#define SMC_SETUP1_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP1) NRD Setup Length */ +#define SMC_SETUP1_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP1) NCS Setup Length in READ Access */ +/* -------- SMC_PULSE1 : (SMC Offset: 0x14) SMC Pulse Register (CS_number = 1) -------- */ +#define SMC_PULSE1_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE1) NWE Pulse Length */ +#define SMC_PULSE1_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE1) NCS Pulse Length in WRITE Access */ +#define SMC_PULSE1_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE1) NRD Pulse Length */ +#define SMC_PULSE1_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE1) NCS Pulse Length in READ Access */ +/* -------- SMC_CYCLE1 : (SMC Offset: 0x18) SMC Cycle Register (CS_number = 1) -------- */ +#define SMC_CYCLE1_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE1) Total Write Cycle Length */ +#define SMC_CYCLE1_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE1) Total Read Cycle Length */ +/* -------- SMC_MODE1 : (SMC Offset: 0x1C) SMC Mode Register (CS_number = 1) -------- */ +#define SMC_MODE1_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE1) */ +#define SMC_MODE1_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE1) */ +#define SMC_MODE1_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE1) NWAIT Mode */ +#define SMC_MODE1_DBW (0x3 << 12) /**< \brief (SMC_MODE1) Data Bus Width */ +#define SMC_MODE1_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE1) Data Float Time */ +#define SMC_MODE1_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE1) TDF Optimization */ +#define SMC_MODE1_PMEN (0x1 << 24) /**< \brief (SMC_MODE1) Page Mode Enabled */ +#define SMC_MODE1_PS (0x3 << 28) /**< \brief (SMC_MODE1) Page Size */ +/* -------- SMC_SETUP2 : (SMC Offset: 0x20) SMC Setup Register (CS_number = 2) -------- */ +#define SMC_SETUP2_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP2) NWE Setup Length */ +#define SMC_SETUP2_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP2) NCS Setup Length in WRITE Access */ +#define SMC_SETUP2_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP2) NRD Setup Length */ +#define SMC_SETUP2_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP2) NCS Setup Length in READ Access */ +/* -------- SMC_PULSE2 : (SMC Offset: 0x24) SMC Pulse Register (CS_number = 2) -------- */ +#define SMC_PULSE2_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE2) NWE Pulse Length */ +#define SMC_PULSE2_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE2) NCS Pulse Length in WRITE Access */ +#define SMC_PULSE2_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE2) NRD Pulse Length */ +#define SMC_PULSE2_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE2) NCS Pulse Length in READ Access */ +/* -------- SMC_CYCLE2 : (SMC Offset: 0x28) SMC Cycle Register (CS_number = 2) -------- */ +#define SMC_CYCLE2_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE2) Total Write Cycle Length */ +#define SMC_CYCLE2_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE2) Total Read Cycle Length */ +/* -------- SMC_MODE2 : (SMC Offset: 0x2C) SMC Mode Register (CS_number = 2) -------- */ +#define SMC_MODE2_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE2) */ +#define SMC_MODE2_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE2) */ +#define SMC_MODE2_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE2) NWAIT Mode */ +#define SMC_MODE2_DBW (0x3 << 12) /**< \brief (SMC_MODE2) Data Bus Width */ +#define SMC_MODE2_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE2) Data Float Time */ +#define SMC_MODE2_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE2) TDF Optimization */ +#define SMC_MODE2_PMEN (0x1 << 24) /**< \brief (SMC_MODE2) Page Mode Enabled */ +#define SMC_MODE2_PS (0x3 << 28) /**< \brief (SMC_MODE2) Page Size */ +/* -------- SMC_SETUP3 : (SMC Offset: 0x30) SMC Setup Register (CS_number = 3) -------- */ +#define SMC_SETUP3_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP3) NWE Setup Length */ +#define SMC_SETUP3_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP3) NCS Setup Length in WRITE Access */ +#define SMC_SETUP3_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP3) NRD Setup Length */ +#define SMC_SETUP3_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP3) NCS Setup Length in READ Access */ +/* -------- SMC_PULSE3 : (SMC Offset: 0x34) SMC Pulse Register (CS_number = 3) -------- */ +#define SMC_PULSE3_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE3) NWE Pulse Length */ +#define SMC_PULSE3_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE3) NCS Pulse Length in WRITE Access */ +#define SMC_PULSE3_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE3) NRD Pulse Length */ +#define SMC_PULSE3_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE3) NCS Pulse Length in READ Access */ +/* -------- SMC_CYCLE3 : (SMC Offset: 0x38) SMC Cycle Register (CS_number = 3) -------- */ +#define SMC_CYCLE3_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE3) Total Write Cycle Length */ +#define SMC_CYCLE3_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE3) Total Read Cycle Length */ +/* -------- SMC_MODE3 : (SMC Offset: 0x3C) SMC Mode Register (CS_number = 3) -------- */ +#define SMC_MODE3_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE3) */ +#define SMC_MODE3_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE3) */ +#define SMC_MODE3_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE3) NWAIT Mode */ +#define SMC_MODE3_DBW (0x3 << 12) /**< \brief (SMC_MODE3) Data Bus Width */ +#define SMC_MODE3_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE3) Data Float Time */ +#define SMC_MODE3_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE3) TDF Optimization */ +#define SMC_MODE3_PMEN (0x1 << 24) /**< \brief (SMC_MODE3) Page Mode Enabled */ +#define SMC_MODE3_PS (0x3 << 28) /**< \brief (SMC_MODE3) Page Size */ +/* -------- SMC_SETUP4 : (SMC Offset: 0x40) SMC Setup Register (CS_number = 4) -------- */ +#define SMC_SETUP4_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP4) NWE Setup Length */ +#define SMC_SETUP4_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP4) NCS Setup Length in WRITE Access */ +#define SMC_SETUP4_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP4) NRD Setup Length */ +#define SMC_SETUP4_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP4) NCS Setup Length in READ Access */ +/* -------- SMC_PULSE4 : (SMC Offset: 0x44) SMC Pulse Register (CS_number = 4) -------- */ +#define SMC_PULSE4_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE4) NWE Pulse Length */ +#define SMC_PULSE4_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE4) NCS Pulse Length in WRITE Access */ +#define SMC_PULSE4_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE4) NRD Pulse Length */ +#define SMC_PULSE4_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE4) NCS Pulse Length in READ Access */ +/* -------- SMC_CYCLE4 : (SMC Offset: 0x48) SMC Cycle Register (CS_number = 4) -------- */ +#define SMC_CYCLE4_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE4) Total Write Cycle Length */ +#define SMC_CYCLE4_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE4) Total Read Cycle Length */ +/* -------- SMC_MODE4 : (SMC Offset: 0x4C) SMC Mode Register (CS_number = 4) -------- */ +#define SMC_MODE4_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE4) */ +#define SMC_MODE4_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE4) */ +#define SMC_MODE4_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE4) NWAIT Mode */ +#define SMC_MODE4_DBW (0x3 << 12) /**< \brief (SMC_MODE4) Data Bus Width */ +#define SMC_MODE4_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE4) Data Float Time */ +#define SMC_MODE4_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE4) TDF Optimization */ +#define SMC_MODE4_PMEN (0x1 << 24) /**< \brief (SMC_MODE4) Page Mode Enabled */ +#define SMC_MODE4_PS (0x3 << 28) /**< \brief (SMC_MODE4) Page Size */ +/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */ +#define SMC_OCMS_SMSE (0x1 << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */ +#define SMC_OCMS_CS0SE (0x1 << 16) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ +#define SMC_OCMS_CS1SE (0x1 << 17) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ +#define SMC_OCMS_CS2SE (0x1 << 18) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ +#define SMC_OCMS_CS3SE (0x1 << 19) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ +/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */ +#define SMC_KEY1_KEY1 (0xffffffff << 0) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */ +/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */ +#define SMC_KEY2_KEY2 (0xffffffff << 0) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */ +/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protect Mode Register -------- */ +#define SMC_WPMR_WPEN (0x1 << 0) /**< \brief (SMC_WPMR) Write Protect Enable */ +#define SMC_WPMR_WPKEY (0xffffff << 8) /**< \brief (SMC_WPMR) Write Protect KEY */ +/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protect Status Register -------- */ +#define SMC_WPSR_WPVS (0x1 << 0) /**< \brief (SMC_WPSR) Write Protect Enable */ +#define SMC_WPSR_WPVSRC (0xffff << 8) /**< \brief (SMC_WPSR) Write Protect Violation Source */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_SPI Serial Peripheral Interface */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Spi hardware registers */ +typedef struct { + WoReg SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */ + RwReg SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */ + RoReg SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */ + WoReg SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */ + RoReg SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */ + WoReg SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */ + WoReg SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */ + RoReg SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */ + RwReg Reserved1[4]; + RwReg SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */ + RwReg Reserved2[41]; + RwReg SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */ + RoReg SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */ + RwReg Reserved3[5]; + RwReg SPI_RPR; /**< \brief (Spi Offset: 0x100) Receive Pointer Register */ + RwReg SPI_RCR; /**< \brief (Spi Offset: 0x104) Receive Counter Register */ + RwReg SPI_TPR; /**< \brief (Spi Offset: 0x108) Transmit Pointer Register */ + RwReg SPI_TCR; /**< \brief (Spi Offset: 0x10C) Transmit Counter Register */ + RwReg SPI_RNPR; /**< \brief (Spi Offset: 0x110) Receive Next Pointer Register */ + RwReg SPI_RNCR; /**< \brief (Spi Offset: 0x114) Receive Next Counter Register */ + RwReg SPI_TNPR; /**< \brief (Spi Offset: 0x118) Transmit Next Pointer Register */ + RwReg SPI_TNCR; /**< \brief (Spi Offset: 0x11C) Transmit Next Counter Register */ + WoReg SPI_PTCR; /**< \brief (Spi Offset: 0x120) Transfer Control Register */ + RoReg SPI_PTSR; /**< \brief (Spi Offset: 0x124) Transfer Status Register */ +} Spi; +#endif /* __ASSEMBLY__ */ +/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */ +#define SPI_CR_SPIEN (0x1 << 0) /**< \brief (SPI_CR) SPI Enable */ +#define SPI_CR_SPIDIS (0x1 << 1) /**< \brief (SPI_CR) SPI Disable */ +#define SPI_CR_SWRST (0x1 << 7) /**< \brief (SPI_CR) SPI Software Reset */ +#define SPI_CR_LASTXFER (0x1 << 24) /**< \brief (SPI_CR) Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */ +#define SPI_MR_MSTR (0x1 << 0) /**< \brief (SPI_MR) Master/Slave Mode */ +#define SPI_MR_PS (0x1 << 1) /**< \brief (SPI_MR) Peripheral Select */ +#define SPI_MR_PS_FIXED (0x0 << 1) /**< \brief (SPI_MR) Fixed Peripheral Select. */ +#define SPI_MR_PS_VARIABLE (0x1 << 1) /**< \brief (SPI_MR) Variable Peripheral Select. */ +#define SPI_MR_PCSDEC (0x1 << 2) /**< \brief (SPI_MR) Chip Select Decode */ +#define SPI_MR_MODFDIS (0x1 << 4) /**< \brief (SPI_MR) Mode Fault Detection */ +#define SPI_MR_WDRBT (0x1 << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */ +#define SPI_MR_LLB (0x1 << 7) /**< \brief (SPI_MR) Local Loopback Enable */ +#define SPI_MR_PCS (0xf << 16) /**< \brief (SPI_MR) Peripheral Chip Select */ +#define SPI_MR_DLYBCS (0xff << 24) /**< \brief (SPI_MR) Delay Between Chip Selects */ +/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */ +#define SPI_RDR_RD (0xffff << 0) /**< \brief (SPI_RDR) Receive Data */ +#define SPI_RDR_PCS (0xf << 16) /**< \brief (SPI_RDR) Peripheral Chip Select */ +/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */ +#define SPI_TDR_TD (0xffff << 0) /**< \brief (SPI_TDR) Transmit Data */ +#define SPI_TDR_PCS (0xf << 16) /**< \brief (SPI_TDR) Peripheral Chip Select */ +#define SPI_TDR_LASTXFER (0x1 << 24) /**< \brief (SPI_TDR) Last Transfer */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define SPI_SR_RDRF (0x1 << 0) /**< \brief (SPI_SR) Receive Data Register Full */ +#define SPI_SR_TDRE (0x1 << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */ +#define SPI_SR_MODF (0x1 << 2) /**< \brief (SPI_SR) Mode Fault Error */ +#define SPI_SR_OVRES (0x1 << 3) /**< \brief (SPI_SR) Overrun Error Status */ +#define SPI_SR_ENDRX (0x1 << 4) /**< \brief (SPI_SR) End of RX buffer */ +#define SPI_SR_ENDTX (0x1 << 5) /**< \brief (SPI_SR) End of TX buffer */ +#define SPI_SR_RXBUFF (0x1 << 6) /**< \brief (SPI_SR) RX Buffer Full */ +#define SPI_SR_TXBUFE (0x1 << 7) /**< \brief (SPI_SR) TX Buffer Empty */ +#define SPI_SR_NSSR (0x1 << 8) /**< \brief (SPI_SR) NSS Rising */ +#define SPI_SR_TXEMPTY (0x1 << 9) /**< \brief (SPI_SR) Transmission Registers Empty */ +#define SPI_SR_UNDES (0x1 << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */ +#define SPI_SR_SPIENS (0x1 << 16) /**< \brief (SPI_SR) SPI Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +#define SPI_IER_RDRF (0x1 << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */ +#define SPI_IER_TDRE (0x1 << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */ +#define SPI_IER_MODF (0x1 << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */ +#define SPI_IER_OVRES (0x1 << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */ +#define SPI_IER_ENDRX (0x1 << 4) /**< \brief (SPI_IER) End of Receive Buffer Interrupt Enable */ +#define SPI_IER_ENDTX (0x1 << 5) /**< \brief (SPI_IER) End of Transmit Buffer Interrupt Enable */ +#define SPI_IER_RXBUFF (0x1 << 6) /**< \brief (SPI_IER) Receive Buffer Full Interrupt Enable */ +#define SPI_IER_TXBUFE (0x1 << 7) /**< \brief (SPI_IER) Transmit Buffer Empty Interrupt Enable */ +#define SPI_IER_NSSR (0x1 << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */ +#define SPI_IER_TXEMPTY (0x1 << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */ +#define SPI_IER_UNDES (0x1 << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +#define SPI_IDR_RDRF (0x1 << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */ +#define SPI_IDR_TDRE (0x1 << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */ +#define SPI_IDR_MODF (0x1 << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */ +#define SPI_IDR_OVRES (0x1 << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */ +#define SPI_IDR_ENDRX (0x1 << 4) /**< \brief (SPI_IDR) End of Receive Buffer Interrupt Disable */ +#define SPI_IDR_ENDTX (0x1 << 5) /**< \brief (SPI_IDR) End of Transmit Buffer Interrupt Disable */ +#define SPI_IDR_RXBUFF (0x1 << 6) /**< \brief (SPI_IDR) Receive Buffer Full Interrupt Disable */ +#define SPI_IDR_TXBUFE (0x1 << 7) /**< \brief (SPI_IDR) Transmit Buffer Empty Interrupt Disable */ +#define SPI_IDR_NSSR (0x1 << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */ +#define SPI_IDR_TXEMPTY (0x1 << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */ +#define SPI_IDR_UNDES (0x1 << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */ +/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */ +#define SPI_IMR_RDRF (0x1 << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */ +#define SPI_IMR_TDRE (0x1 << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */ +#define SPI_IMR_MODF (0x1 << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */ +#define SPI_IMR_OVRES (0x1 << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */ +#define SPI_IMR_ENDRX (0x1 << 4) /**< \brief (SPI_IMR) End of Receive Buffer Interrupt Mask */ +#define SPI_IMR_ENDTX (0x1 << 5) /**< \brief (SPI_IMR) End of Transmit Buffer Interrupt Mask */ +#define SPI_IMR_RXBUFF (0x1 << 6) /**< \brief (SPI_IMR) Receive Buffer Full Interrupt Mask */ +#define SPI_IMR_TXBUFE (0x1 << 7) /**< \brief (SPI_IMR) Transmit Buffer Empty Interrupt Mask */ +#define SPI_IMR_NSSR (0x1 << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */ +#define SPI_IMR_TXEMPTY (0x1 << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */ +#define SPI_IMR_UNDES (0x1 << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */ +/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */ +#define SPI_CSR_CPOL (0x1 << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */ +#define SPI_CSR_NCPHA (0x1 << 1) /**< \brief (SPI_CSR[4]) Clock Phase */ +#define SPI_CSR_CSNAAT (0x1 << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ +#define SPI_CSR_CSAAT (0x1 << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ +#define SPI_CSR_BITS (0xf << 4) /**< \brief (SPI_CSR[4]) Bits Per Transfer (See the (Note:) below the register table; Section 9.9 "SPI Chip Select Register" on page 35.) */ +#define SPI_CSR_BITS_8 (0x0 << 4) /**< \brief (SPI_CSR[4]) 8 */ +#define SPI_CSR_BITS_9 (0x1 << 4) /**< \brief (SPI_CSR[4]) 9 */ +#define SPI_CSR_BITS_10 (0x2 << 4) /**< \brief (SPI_CSR[4]) 10 */ +#define SPI_CSR_BITS_11 (0x3 << 4) /**< \brief (SPI_CSR[4]) 11 */ +#define SPI_CSR_BITS_12 (0x4 << 4) /**< \brief (SPI_CSR[4]) 12 */ +#define SPI_CSR_BITS_13 (0x5 << 4) /**< \brief (SPI_CSR[4]) 13 */ +#define SPI_CSR_BITS_14 (0x6 << 4) /**< \brief (SPI_CSR[4]) 14 */ +#define SPI_CSR_BITS_15 (0x7 << 4) /**< \brief (SPI_CSR[4]) 15 */ +#define SPI_CSR_BITS_16 (0x8 << 4) /**< \brief (SPI_CSR[4]) 16 */ +#define SPI_CSR_SCBR (0xff << 8) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */ +#define SPI_CSR_DLYBS (0xff << 16) /**< \brief (SPI_CSR[4]) Delay Before SPCK */ +#define SPI_CSR_DLYBCT (0xff << 24) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */ +/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */ +#define SPI_WPMR_SPIWPEN (0x1 << 0) /**< \brief (SPI_WPMR) SPI Write Protection Enable */ +#define SPI_WPMR_SPIWPKEY (0xffffff << 8) /**< \brief (SPI_WPMR) SPI Write Protection Key Password */ +/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */ +#define SPI_WPSR_SPIWPVS (0x7 << 0) /**< \brief (SPI_WPSR) SPI Write Protection Violation Status */ +#define SPI_WPSR_SPIWPVSRC (0xff << 8) /**< \brief (SPI_WPSR) SPI Write Protection Violation Source */ +/* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */ +#define SPI_RPR_RXPTR (0xffffffff << 0) /**< \brief (SPI_RPR) Receive Pointer Register */ +/* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */ +#define SPI_RCR_RXCTR (0xffff << 0) /**< \brief (SPI_RCR) Receive Counter Register */ +/* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */ +#define SPI_TPR_TXPTR (0xffffffff << 0) /**< \brief (SPI_TPR) Transmit Counter Register */ +/* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */ +#define SPI_TCR_TXCTR (0xffff << 0) /**< \brief (SPI_TCR) Transmit Counter Register */ +/* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */ +#define SPI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (SPI_RNPR) Receive Next Pointer */ +/* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */ +#define SPI_RNCR_RXNCTR (0xffff << 0) /**< \brief (SPI_RNCR) Receive Next Counter */ +/* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */ +#define SPI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (SPI_TNPR) Transmit Next Pointer */ +/* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */ +#define SPI_TNCR_TXNCTR (0xffff << 0) /**< \brief (SPI_TNCR) Transmit Counter Next */ +/* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */ +#define SPI_PTCR_RXTEN (0x1 << 0) /**< \brief (SPI_PTCR) Receiver Transfer Enable */ +#define SPI_PTCR_RXTDIS (0x1 << 1) /**< \brief (SPI_PTCR) Receiver Transfer Disable */ +#define SPI_PTCR_TXTEN (0x1 << 8) /**< \brief (SPI_PTCR) Transmitter Transfer Enable */ +#define SPI_PTCR_TXTDIS (0x1 << 9) /**< \brief (SPI_PTCR) Transmitter Transfer Disable */ +/* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */ +#define SPI_PTSR_RXTEN (0x1 << 0) /**< \brief (SPI_PTSR) Receiver Transfer Enable */ +#define SPI_PTSR_TXTEN (0x1 << 8) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_SSC Synchronous Serial Controller */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Ssc hardware registers */ +typedef struct { + WoReg SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */ + RwReg SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */ + RwReg Reserved1[2]; + RwReg SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */ + RwReg SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */ + RwReg SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */ + RwReg SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */ + RoReg SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */ + WoReg SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */ + RwReg Reserved2[2]; + RoReg SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */ + RwReg SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */ + RwReg SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */ + RwReg SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */ + RoReg SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */ + WoReg SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */ + WoReg SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */ + RoReg SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */ + RwReg Reserved3[37]; + RwReg SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */ + RoReg SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */ + RwReg Reserved4[5]; + RwReg SSC_RPR; /**< \brief (Ssc Offset: 0x100) Receive Pointer Register */ + RwReg SSC_RCR; /**< \brief (Ssc Offset: 0x104) Receive Counter Register */ + RwReg SSC_TPR; /**< \brief (Ssc Offset: 0x108) Transmit Pointer Register */ + RwReg SSC_TCR; /**< \brief (Ssc Offset: 0x10C) Transmit Counter Register */ + RwReg SSC_RNPR; /**< \brief (Ssc Offset: 0x110) Receive Next Pointer Register */ + RwReg SSC_RNCR; /**< \brief (Ssc Offset: 0x114) Receive Next Counter Register */ + RwReg SSC_TNPR; /**< \brief (Ssc Offset: 0x118) Transmit Next Pointer Register */ + RwReg SSC_TNCR; /**< \brief (Ssc Offset: 0x11C) Transmit Next Counter Register */ + WoReg SSC_PTCR; /**< \brief (Ssc Offset: 0x120) Transfer Control Register */ + RoReg SSC_PTSR; /**< \brief (Ssc Offset: 0x124) Transfer Status Register */ +} Ssc; +#endif /* __ASSEMBLY__ */ +/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */ +#define SSC_CR_RXEN (0x1 << 0) /**< \brief (SSC_CR) Receive Enable */ +#define SSC_CR_RXDIS (0x1 << 1) /**< \brief (SSC_CR) Receive Disable */ +#define SSC_CR_TXEN (0x1 << 8) /**< \brief (SSC_CR) Transmit Enable */ +#define SSC_CR_TXDIS (0x1 << 9) /**< \brief (SSC_CR) Transmit Disable */ +#define SSC_CR_SWRST (0x1 << 15) /**< \brief (SSC_CR) Software Reset */ +/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */ +#define SSC_CMR_DIV (0xfff << 0) /**< \brief (SSC_CMR) Clock Divider */ +/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */ +#define SSC_RCMR_CKS (0x3 << 0) /**< \brief (SSC_RCMR) Receive Clock Selection */ +#define SSC_RCMR_CKS_DIV (0x0 << 0) /**< \brief (SSC_RCMR) Divided Clock */ +#define SSC_RCMR_CKS_TK (0x1 << 0) /**< \brief (SSC_RCMR) TK Clock signal */ +#define SSC_RCMR_CKS_RK (0x2 << 0) /**< \brief (SSC_RCMR) RK pin */ +#define SSC_RCMR_CKO (0x7 << 2) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */ +#define SSC_RCMR_CKI (0x1 << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */ +#define SSC_RCMR_CKG (0x3 << 6) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */ +#define SSC_RCMR_CKG_NONE (0x0 << 6) /**< \brief (SSC_RCMR) None, continuous clock */ +#define SSC_RCMR_CKG_LOW (0x1 << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */ +#define SSC_RCMR_CKG_HIGH (0x2 << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */ +#define SSC_RCMR_START (0xf << 8) /**< \brief (SSC_RCMR) Receive Start Selection */ +#define SSC_RCMR_STOP (0x1 << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */ +#define SSC_RCMR_STTDLY (0xff << 16) /**< \brief (SSC_RCMR) Receive Start Delay */ +#define SSC_RCMR_PERIOD (0xff << 24) /**< \brief (SSC_RCMR) Receive Period Divider Selection */ +/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */ +#define SSC_RFMR_DATLEN (0x1f << 0) /**< \brief (SSC_RFMR) Data Length */ +#define SSC_RFMR_LOOP (0x1 << 5) /**< \brief (SSC_RFMR) Loop Mode */ +#define SSC_RFMR_MSBF (0x1 << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */ +#define SSC_RFMR_DATNB (0xf << 8) /**< \brief (SSC_RFMR) Data Number per Frame */ +#define SSC_RFMR_FSLEN (0xf << 16) /**< \brief (SSC_RFMR) Receive Frame Sync Length */ +#define SSC_RFMR_FSOS (0x7 << 20) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */ +#define SSC_RFMR_FSEDGE (0x1 << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */ +#define SSC_RFMR_FSLEN_EXT (0xf << 28) /**< \brief (SSC_RFMR) FSLEN Field Extension */ +/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */ +#define SSC_TCMR_CKS (0x3 << 0) /**< \brief (SSC_TCMR) Transmit Clock Selection */ +#define SSC_TCMR_CKO (0x7 << 2) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */ +#define SSC_TCMR_CKI (0x1 << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */ +#define SSC_TCMR_CKG (0x3 << 6) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */ +#define SSC_TCMR_START (0xf << 8) /**< \brief (SSC_TCMR) Transmit Start Selection */ +#define SSC_TCMR_STTDLY (0xff << 16) /**< \brief (SSC_TCMR) Transmit Start Delay */ +#define SSC_TCMR_PERIOD (0xff << 24) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */ +/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */ +#define SSC_TFMR_DATLEN (0x1f << 0) /**< \brief (SSC_TFMR) Data Length */ +#define SSC_TFMR_DATDEF (0x1 << 5) /**< \brief (SSC_TFMR) Data Default Value */ +#define SSC_TFMR_MSBF (0x1 << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */ +#define SSC_TFMR_DATNB (0xf << 8) /**< \brief (SSC_TFMR) Data Number per frame */ +#define SSC_TFMR_FSLEN (0xf << 16) /**< \brief (SSC_TFMR) Transmit Frame Syn Length */ +#define SSC_TFMR_FSOS (0x7 << 20) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */ +#define SSC_TFMR_FSDEN (0x1 << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */ +#define SSC_TFMR_FSEDGE (0x1 << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */ +#define SSC_TFMR_FSLEN_EXT (0xf << 28) /**< \brief (SSC_TFMR) FSLEN Field Extension */ +/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */ +#define SSC_RHR_RDAT (0xffffffff << 0) /**< \brief (SSC_RHR) Receive Data */ +/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */ +#define SSC_THR_TDAT (0xffffffff << 0) /**< \brief (SSC_THR) Transmit Data */ +/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */ +#define SSC_RSHR_RSDAT (0xffff << 0) /**< \brief (SSC_RSHR) Receive Synchronization Data */ +/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */ +#define SSC_TSHR_TSDAT (0xffff << 0) /**< \brief (SSC_TSHR) Transmit Synchronization Data */ +/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */ +#define SSC_RC0R_CP0 (0xffff << 0) /**< \brief (SSC_RC0R) Receive Compare Data 0 */ +/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */ +#define SSC_RC1R_CP1 (0xffff << 0) /**< \brief (SSC_RC1R) Receive Compare Data 1 */ +/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */ +#define SSC_SR_TXRDY (0x1 << 0) /**< \brief (SSC_SR) Transmit Ready */ +#define SSC_SR_TXEMPTY (0x1 << 1) /**< \brief (SSC_SR) Transmit Empty */ +#define SSC_SR_ENDTX (0x1 << 2) /**< \brief (SSC_SR) End of Transmission */ +#define SSC_SR_TXBUFE (0x1 << 3) /**< \brief (SSC_SR) Transmit Buffer Empty */ +#define SSC_SR_RXRDY (0x1 << 4) /**< \brief (SSC_SR) Receive Ready */ +#define SSC_SR_OVRUN (0x1 << 5) /**< \brief (SSC_SR) Receive Overrun */ +#define SSC_SR_ENDRX (0x1 << 6) /**< \brief (SSC_SR) End of Reception */ +#define SSC_SR_RXBUFF (0x1 << 7) /**< \brief (SSC_SR) Receive Buffer Full */ +#define SSC_SR_CP0 (0x1 << 8) /**< \brief (SSC_SR) Compare 0 */ +#define SSC_SR_CP1 (0x1 << 9) /**< \brief (SSC_SR) Compare 1 */ +#define SSC_SR_TXSYN (0x1 << 10) /**< \brief (SSC_SR) Transmit Sync */ +#define SSC_SR_RXSYN (0x1 << 11) /**< \brief (SSC_SR) Receive Sync */ +#define SSC_SR_TXEN (0x1 << 16) /**< \brief (SSC_SR) Transmit Enable */ +#define SSC_SR_RXEN (0x1 << 17) /**< \brief (SSC_SR) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */ +#define SSC_IER_TXRDY (0x1 << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */ +#define SSC_IER_TXEMPTY (0x1 << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */ +#define SSC_IER_ENDTX (0x1 << 2) /**< \brief (SSC_IER) End of Transmission Interrupt Enable */ +#define SSC_IER_TXBUFE (0x1 << 3) /**< \brief (SSC_IER) Transmit Buffer Empty Interrupt Enable */ +#define SSC_IER_RXRDY (0x1 << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */ +#define SSC_IER_OVRUN (0x1 << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */ +#define SSC_IER_ENDRX (0x1 << 6) /**< \brief (SSC_IER) End of Reception Interrupt Enable */ +#define SSC_IER_RXBUFF (0x1 << 7) /**< \brief (SSC_IER) Receive Buffer Full Interrupt Enable */ +#define SSC_IER_CP0 (0x1 << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */ +#define SSC_IER_CP1 (0x1 << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */ +#define SSC_IER_TXSYN (0x1 << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */ +#define SSC_IER_RXSYN (0x1 << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */ +/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */ +#define SSC_IDR_TXRDY (0x1 << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */ +#define SSC_IDR_TXEMPTY (0x1 << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */ +#define SSC_IDR_ENDTX (0x1 << 2) /**< \brief (SSC_IDR) End of Transmission Interrupt Disable */ +#define SSC_IDR_TXBUFE (0x1 << 3) /**< \brief (SSC_IDR) Transmit Buffer Empty Interrupt Disable */ +#define SSC_IDR_RXRDY (0x1 << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */ +#define SSC_IDR_OVRUN (0x1 << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */ +#define SSC_IDR_ENDRX (0x1 << 6) /**< \brief (SSC_IDR) End of Reception Interrupt Disable */ +#define SSC_IDR_RXBUFF (0x1 << 7) /**< \brief (SSC_IDR) Receive Buffer Full Interrupt Disable */ +#define SSC_IDR_CP0 (0x1 << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */ +#define SSC_IDR_CP1 (0x1 << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */ +#define SSC_IDR_TXSYN (0x1 << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */ +#define SSC_IDR_RXSYN (0x1 << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */ +/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */ +#define SSC_IMR_TXRDY (0x1 << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */ +#define SSC_IMR_TXEMPTY (0x1 << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */ +#define SSC_IMR_ENDTX (0x1 << 2) /**< \brief (SSC_IMR) End of Transmission Interrupt Mask */ +#define SSC_IMR_TXBUFE (0x1 << 3) /**< \brief (SSC_IMR) Transmit Buffer Empty Interrupt Mask */ +#define SSC_IMR_RXRDY (0x1 << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */ +#define SSC_IMR_OVRUN (0x1 << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */ +#define SSC_IMR_ENDRX (0x1 << 6) /**< \brief (SSC_IMR) End of Reception Interrupt Mask */ +#define SSC_IMR_RXBUFF (0x1 << 7) /**< \brief (SSC_IMR) Receive Buffer Full Interrupt Mask */ +#define SSC_IMR_CP0 (0x1 << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */ +#define SSC_IMR_CP1 (0x1 << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */ +#define SSC_IMR_TXSYN (0x1 << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */ +#define SSC_IMR_RXSYN (0x1 << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */ +/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */ +#define SSC_WPMR_WPEN (0x1 << 0) /**< \brief (SSC_WPMR) Write Protect Enable */ +#define SSC_WPMR_WPKEY (0xffffff << 8) /**< \brief (SSC_WPMR) Write Protect KEY */ +/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */ +#define SSC_WPSR_WPVS (0x1 << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */ +#define SSC_WPSR_WPVSRC (0xffff << 8) /**< \brief (SSC_WPSR) Write Protect Violation Source */ +/* -------- SSC_RPR : (SSC Offset: 0x100) Receive Pointer Register -------- */ +#define SSC_RPR_RXPTR (0xffffffff << 0) /**< \brief (SSC_RPR) Receive Pointer Register */ +/* -------- SSC_RCR : (SSC Offset: 0x104) Receive Counter Register -------- */ +#define SSC_RCR_RXCTR (0xffff << 0) /**< \brief (SSC_RCR) Receive Counter Register */ +/* -------- SSC_TPR : (SSC Offset: 0x108) Transmit Pointer Register -------- */ +#define SSC_TPR_TXPTR (0xffffffff << 0) /**< \brief (SSC_TPR) Transmit Counter Register */ +/* -------- SSC_TCR : (SSC Offset: 0x10C) Transmit Counter Register -------- */ +#define SSC_TCR_TXCTR (0xffff << 0) /**< \brief (SSC_TCR) Transmit Counter Register */ +/* -------- SSC_RNPR : (SSC Offset: 0x110) Receive Next Pointer Register -------- */ +#define SSC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (SSC_RNPR) Receive Next Pointer */ +/* -------- SSC_RNCR : (SSC Offset: 0x114) Receive Next Counter Register -------- */ +#define SSC_RNCR_RXNCTR (0xffff << 0) /**< \brief (SSC_RNCR) Receive Next Counter */ +/* -------- SSC_TNPR : (SSC Offset: 0x118) Transmit Next Pointer Register -------- */ +#define SSC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (SSC_TNPR) Transmit Next Pointer */ +/* -------- SSC_TNCR : (SSC Offset: 0x11C) Transmit Next Counter Register -------- */ +#define SSC_TNCR_TXNCTR (0xffff << 0) /**< \brief (SSC_TNCR) Transmit Counter Next */ +/* -------- SSC_PTCR : (SSC Offset: 0x120) Transfer Control Register -------- */ +#define SSC_PTCR_RXTEN (0x1 << 0) /**< \brief (SSC_PTCR) Receiver Transfer Enable */ +#define SSC_PTCR_RXTDIS (0x1 << 1) /**< \brief (SSC_PTCR) Receiver Transfer Disable */ +#define SSC_PTCR_TXTEN (0x1 << 8) /**< \brief (SSC_PTCR) Transmitter Transfer Enable */ +#define SSC_PTCR_TXTDIS (0x1 << 9) /**< \brief (SSC_PTCR) Transmitter Transfer Disable */ +/* -------- SSC_PTSR : (SSC Offset: 0x124) Transfer Status Register -------- */ +#define SSC_PTSR_RXTEN (0x1 << 0) /**< \brief (SSC_PTSR) Receiver Transfer Enable */ +#define SSC_PTSR_TXTEN (0x1 << 8) /**< \brief (SSC_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Supply Controller */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_SUPC Supply Controller */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Supc hardware registers */ +typedef struct { + WoReg SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */ + RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */ + RwReg SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */ + RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */ + RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */ + RoReg SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */ +} Supc; +#endif /* __ASSEMBLY__ */ +/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */ +#define SUPC_CR_VROFF (0x1 << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */ +#define SUPC_CR_VROFF_NO_EFFECT (0x0 << 2) /**< \brief (SUPC_CR) no effect. */ +#define SUPC_CR_VROFF_STOP_VREG (0x1 << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */ +#define SUPC_CR_XTALSEL (0x1 << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */ +#define SUPC_CR_XTALSEL_NO_EFFECT (0x0 << 3) /**< \brief (SUPC_CR) no effect. */ +#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1 << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */ +#define SUPC_CR_KEY (0xff << 24) /**< \brief (SUPC_CR) Password */ +/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */ +#define SUPC_SMMR_SMTH (0xf << 0) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */ +#define SUPC_SMMR_SMTH_1_9V (0x0 << 0) /**< \brief (SUPC_SMMR) 1.9 V */ +#define SUPC_SMMR_SMTH_2_0V (0x1 << 0) /**< \brief (SUPC_SMMR) 2.0 V */ +#define SUPC_SMMR_SMTH_2_1V (0x2 << 0) /**< \brief (SUPC_SMMR) 2.1 V */ +#define SUPC_SMMR_SMTH_2_2V (0x3 << 0) /**< \brief (SUPC_SMMR) 2.2 V */ +#define SUPC_SMMR_SMTH_2_3V (0x4 << 0) /**< \brief (SUPC_SMMR) 2.3 V */ +#define SUPC_SMMR_SMTH_2_4V (0x5 << 0) /**< \brief (SUPC_SMMR) 2.4 V */ +#define SUPC_SMMR_SMTH_2_5V (0x6 << 0) /**< \brief (SUPC_SMMR) 2.5 V */ +#define SUPC_SMMR_SMTH_2_6V (0x7 << 0) /**< \brief (SUPC_SMMR) 2.6 V */ +#define SUPC_SMMR_SMTH_2_7V (0x8 << 0) /**< \brief (SUPC_SMMR) 2.7 V */ +#define SUPC_SMMR_SMTH_2_8V (0x9 << 0) /**< \brief (SUPC_SMMR) 2.8 V */ +#define SUPC_SMMR_SMTH_2_9V (0xA << 0) /**< \brief (SUPC_SMMR) 2.9 V */ +#define SUPC_SMMR_SMTH_3_0V (0xB << 0) /**< \brief (SUPC_SMMR) 3.0 V */ +#define SUPC_SMMR_SMTH_3_1V (0xC << 0) /**< \brief (SUPC_SMMR) 3.1 V */ +#define SUPC_SMMR_SMTH_3_2V (0xD << 0) /**< \brief (SUPC_SMMR) 3.2 V */ +#define SUPC_SMMR_SMTH_3_3V (0xE << 0) /**< \brief (SUPC_SMMR) 3.3 V */ +#define SUPC_SMMR_SMTH_3_4V (0xF << 0) /**< \brief (SUPC_SMMR) 3.4 V */ +#define SUPC_SMMR_SMSMPL (0x7 << 8) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */ +#define SUPC_SMMR_SMSMPL_SMD (0x0 << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */ +#define SUPC_SMMR_SMSMPL_CSM (0x1 << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */ +#define SUPC_SMMR_SMSMPL_32SLCK (0x2 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ +#define SUPC_SMMR_SMSMPL_256SLCK (0x3 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ +#define SUPC_SMMR_SMSMPL_2048SLCK (0x4 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ +#define SUPC_SMMR_SMRSTEN (0x1 << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */ +#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMRSTEN_ENABLE (0x1 << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN (0x1 << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */ +#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0 << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN_ENABLE (0x1 << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */ +/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */ +#define SUPC_MR_BODRSTEN (0x1 << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */ +#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */ +#define SUPC_MR_BODRSTEN_ENABLE (0x1 << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ +#define SUPC_MR_BODDIS (0x1 << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */ +#define SUPC_MR_BODDIS_ENABLE (0x0 << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */ +#define SUPC_MR_BODDIS_DISABLE (0x1 << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */ +#define SUPC_MR_ONREG (0x1 << 14) /**< \brief (SUPC_MR) Voltage Regulator enable */ +#define SUPC_MR_ONREG_ONREG_UNUSED (0x0 << 14) /**< \brief (SUPC_MR) Voltage Regulator is not used */ +#define SUPC_MR_ONREG_ONREG_USED (0x1 << 14) /**< \brief (SUPC_MR) Voltage Regulator is used */ +#define SUPC_MR_OSCBYPASS (0x1 << 20) /**< \brief (SUPC_MR) Oscillator Bypass */ +#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0 << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */ +#define SUPC_MR_OSCBYPASS_BYPASS (0x1 << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */ +#define SUPC_MR_KEY (0xff << 24) /**< \brief (SUPC_MR) Password Key */ +/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */ +#define SUPC_WUMR_SMEN (0x1 << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */ +#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0 << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */ +#define SUPC_WUMR_SMEN_ENABLE (0x1 << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */ +#define SUPC_WUMR_RTTEN (0x1 << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */ +#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0 << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */ +#define SUPC_WUMR_RTTEN_ENABLE (0x1 << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */ +#define SUPC_WUMR_RTCEN (0x1 << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */ +#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0 << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */ +#define SUPC_WUMR_RTCEN_ENABLE (0x1 << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */ +#define SUPC_WUMR_WKUPDBC (0x7 << 12) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer */ +#define SUPC_WUMR_WKUPDBC_1SCLK (0x0 << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ +#define SUPC_WUMR_WKUPDBC_3SCLK (0x1 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 3 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32SCLK (0x2 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 32 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_512SCLK (0x3 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 512 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_4096SCLK (0x4 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 4,096 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32768SCLK (0x5 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 32,768 SLCK periods */ +/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */ +#define SUPC_WUIR_WKUPEN0 (0x1 << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */ +#define SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0 << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN0_ENABLE (0x1 << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN1 (0x1 << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */ +#define SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0 << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN1_ENABLE (0x1 << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN2 (0x1 << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */ +#define SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0 << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN2_ENABLE (0x1 << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN3 (0x1 << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */ +#define SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0 << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN3_ENABLE (0x1 << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN4 (0x1 << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */ +#define SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0 << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN4_ENABLE (0x1 << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN5 (0x1 << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */ +#define SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0 << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN5_ENABLE (0x1 << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN6 (0x1 << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */ +#define SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0 << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN6_ENABLE (0x1 << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN7 (0x1 << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */ +#define SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0 << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN7_ENABLE (0x1 << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN8 (0x1 << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */ +#define SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0 << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN8_ENABLE (0x1 << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN9 (0x1 << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */ +#define SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0 << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN9_ENABLE (0x1 << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN10 (0x1 << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */ +#define SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0 << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN10_ENABLE (0x1 << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN11 (0x1 << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */ +#define SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0 << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN11_ENABLE (0x1 << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN12 (0x1 << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */ +#define SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN12_ENABLE (0x1 << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN13 (0x1 << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */ +#define SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0 << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN13_ENABLE (0x1 << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN14 (0x1 << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */ +#define SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0 << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN14_ENABLE (0x1 << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN15 (0x1 << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */ +#define SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0 << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN15_ENABLE (0x1 << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT0 (0x1 << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */ +#define SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0 << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1 << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT1 (0x1 << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */ +#define SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0 << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1 << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT2 (0x1 << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */ +#define SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0 << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1 << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT3 (0x1 << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */ +#define SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0 << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1 << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT4 (0x1 << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */ +#define SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0 << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1 << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT5 (0x1 << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */ +#define SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0 << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1 << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT6 (0x1 << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */ +#define SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0 << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1 << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT7 (0x1 << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */ +#define SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0 << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1 << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT8 (0x1 << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */ +#define SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0 << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1 << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT9 (0x1 << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */ +#define SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0 << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1 << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT10 (0x1 << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */ +#define SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0 << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1 << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT11 (0x1 << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */ +#define SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0 << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1 << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT12 (0x1 << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */ +#define SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0 << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1 << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT13 (0x1 << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */ +#define SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0 << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1 << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT14 (0x1 << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */ +#define SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0 << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1 << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT15 (0x1 << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */ +#define SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0 << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1 << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */ +#define SUPC_SR_WKUPS (0x1 << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */ +#define SUPC_SR_WKUPS_NO (0x0 << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPS_PRESENT (0x1 << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS (0x1 << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */ +#define SUPC_SR_SMWS_NO (0x0 << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS_PRESENT (0x1 << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_BODRSTS (0x1 << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */ +#define SUPC_SR_BODRSTS_NO (0x0 << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_BODRSTS_PRESENT (0x1 << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS (0x1 << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */ +#define SUPC_SR_SMRSTS_NO (0x0 << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS_PRESENT (0x1 << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMS (0x1 << 5) /**< \brief (SUPC_SR) Supply Monitor Status */ +#define SUPC_SR_SMS_NO (0x0 << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMS_PRESENT (0x1 << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMOS (0x1 << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */ +#define SUPC_SR_SMOS_HIGH (0x0 << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO higher than its threshold at its last measurement. */ +#define SUPC_SR_SMOS_LOW (0x1 << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO lower than its threshold at its last measurement. */ +#define SUPC_SR_OSCSEL (0x1 << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */ +#define SUPC_SR_OSCSEL_RC (0x0 << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */ +#define SUPC_SR_OSCSEL_CRYST (0x1 << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */ +#define SUPC_SR_WKUPIS0 (0x1 << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */ +#define SUPC_SR_WKUPIS0_DIS (0x0 << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS0_EN (0x1 << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS1 (0x1 << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */ +#define SUPC_SR_WKUPIS1_DIS (0x0 << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS1_EN (0x1 << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS2 (0x1 << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */ +#define SUPC_SR_WKUPIS2_DIS (0x0 << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS2_EN (0x1 << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS3 (0x1 << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */ +#define SUPC_SR_WKUPIS3_DIS (0x0 << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS3_EN (0x1 << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS4 (0x1 << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */ +#define SUPC_SR_WKUPIS4_DIS (0x0 << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS4_EN (0x1 << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS5 (0x1 << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */ +#define SUPC_SR_WKUPIS5_DIS (0x0 << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS5_EN (0x1 << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS6 (0x1 << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */ +#define SUPC_SR_WKUPIS6_DIS (0x0 << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS6_EN (0x1 << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS7 (0x1 << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */ +#define SUPC_SR_WKUPIS7_DIS (0x0 << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS7_EN (0x1 << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS8 (0x1 << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */ +#define SUPC_SR_WKUPIS8_DIS (0x0 << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS8_EN (0x1 << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS9 (0x1 << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */ +#define SUPC_SR_WKUPIS9_DIS (0x0 << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS9_EN (0x1 << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS10 (0x1 << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */ +#define SUPC_SR_WKUPIS10_DIS (0x0 << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS10_EN (0x1 << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS11 (0x1 << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */ +#define SUPC_SR_WKUPIS11_DIS (0x0 << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS11_EN (0x1 << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS12 (0x1 << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */ +#define SUPC_SR_WKUPIS12_DIS (0x0 << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS12_EN (0x1 << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS13 (0x1 << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */ +#define SUPC_SR_WKUPIS13_DIS (0x0 << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS13_EN (0x1 << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS14 (0x1 << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */ +#define SUPC_SR_WKUPIS14_DIS (0x0 << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS14_EN (0x1 << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS15 (0x1 << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */ +#define SUPC_SR_WKUPIS15_DIS (0x0 << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS15_EN (0x1 << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Timer Counter */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_TC Timer Counter */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief TcChannel hardware registers */ +typedef struct { + RwReg TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ + RwReg TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ + RwReg Reserved1[2]; + RwReg TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ + RwReg TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ + RwReg TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ + RwReg TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ + RwReg TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ + RwReg TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ + RwReg TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ + RwReg TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ + RwReg Reserved2[4]; +} TcChannel; +/** \brief Tc hardware registers */ +typedef struct { + TcChannel TC_CHANNEL[3]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ + WoReg TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ + RwReg TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ + WoReg TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ + WoReg TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ + RoReg TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ + RoReg TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ + RwReg TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */ + RwReg Reserved1[2]; + RwReg TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */ + RwReg Reserved2[5]; + RoReg TC_VER; /**< \brief (Tc Offset: 0xFC) Version Register */ +} Tc; +#endif /* __ASSEMBLY__ */ +/* -------- TC_CCR0 : (TC Offset: 0x0) Channel Control Register (channel = 0) -------- */ +#define TC_CCR0_CLKEN (0x1 << 0) /**< \brief (TC_CCR0) Counter Clock Enable Command */ +#define TC_CCR0_CLKDIS (0x1 << 1) /**< \brief (TC_CCR0) Counter Clock Disable Command */ +#define TC_CCR0_SWTRG (0x1 << 2) /**< \brief (TC_CCR0) Software Trigger Command */ +/* -------- TC_CMR0 : (TC Offset: 0x4) Channel Mode Register (channel = 0) -------- */ +#define TC_CMR0_TCCLKS (0x7 << 0) /**< \brief (TC_CMR0) Clock Selection */ +#define TC_CM0_TCCLKS_TIMER_DIV1_CLOCK (0x0 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV1_CLOCK*/ +#define TC_CM0_TCCLKS_TIMER_DIV2_CLOCK (0x1 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV2_CLOCK*/ +#define TC_CM0_TCCLKS_TIMER_DIV3_CLOCK (0x2 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV3_CLOCK*/ +#define TC_CM0_TCCLKS_TIMER_DIV4_CLOCK (0x3 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV4_CLOCK*/ +#define TC_CM0_TCCLKS_TIMER_DIV5_CLOCK (0x4 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV5_CLOCK*/ +#define TC_CM0_TCCLKS_XC0 (0x5 << 0) /**< (TC_CMR0) Clock selected: XC0*/ +#define TC_CM0_TCCLKS_XC1 (0x6 << 0) /**< (TC_CMR0) Clock selected: XC1*/ +#define TC_CM0_TCCLKS_XC2 (0x7 << 0) /**< (TC_CMR0) Clock selected: XC2*/ +#define TC_CMR0_CLKI (0x1 << 3) /**< \brief (TC_CMR0) Clock Invert */ +#define TC_CMR0_BURST (0x3 << 4) /**< \brief (TC_CMR0) Burst Signal Selection */ +#define TC_CMR0_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR0) The clock is not gated by an external signal. */ +#define TC_CMR0_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR0) XC0 is ANDed with the selected clock. */ +#define TC_CMR0_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR0) XC1 is ANDed with the selected clock. */ +#define TC_CMR0_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR0) XC2 is ANDed with the selected clock. */ +#define TC_CMR0_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR0) Counter Clock Stopped with RB Loading */ +#define TC_CMR0_LDBDIS (0x1 << 7) /**< \brief (TC_CMR0) Counter Clock Disable with RB Loading */ +#define TC_CMR0_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR0) External Trigger Edge Selection */ +#define TC_CMR0_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR0) none */ +#define TC_CMR0_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR0) rising edge */ +#define TC_CMR0_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR0) falling edge */ +#define TC_CMR0_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR0) each edge */ +#define TC_CMR0_ABETRG (0x1 << 10) /**< \brief (TC_CMR0) TIOA or TIOB External Trigger Selection */ +#define TC_CMR0_CPCTRG (0x1 << 14) /**< \brief (TC_CMR0) RC Compare Trigger Enable */ +#define TC_CMR0_WAVE (0x1 << 15) /**< \brief (TC_CMR0) */ +#define TC_CMR0_LDRA (0x3 << 16) /**< \brief (TC_CMR0) RA Loading Selection */ +#define TC_CMR0_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR0) none */ +#define TC_CMR0_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR0) rising edge of TIOA */ +#define TC_CMR0_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR0) falling edge of TIOA */ +#define TC_CMR0_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR0) each edge of TIOA */ +#define TC_CMR0_LDRB (0x3 << 18) /**< \brief (TC_CMR0) RB Loading Selection */ +#define TC_CMR0_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR0) none */ +#define TC_CMR0_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR0) rising edge of TIOA */ +#define TC_CMR0_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR0) falling edge of TIOA */ +#define TC_CMR0_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR0) each edge of TIOA */ + +#define TC_CMR0_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define TC_CMR0_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define TC_CMR0_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define TC_CMR0_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle + +#define TC_CMR0_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define TC_CMR0_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define TC_CMR0_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define TC_CMR0_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +/* -------- TC_CV0 : (TC Offset: 0x10) Counter Value (channel = 0) -------- */ +#define TC_CV0_CV (0xffff << 0) /**< \brief (TC_CV0) Counter Value */ +/* -------- TC_RA0 : (TC Offset: 0x14) Register A (channel = 0) -------- */ +#define TC_RA0_RA (0xffff << 0) /**< \brief (TC_RA0) Register A */ +/* -------- TC_RB0 : (TC Offset: 0x18) Register B (channel = 0) -------- */ +#define TC_RB0_RB (0xffff << 0) /**< \brief (TC_RB0) Register B */ +/* -------- TC_RC0 : (TC Offset: 0x1C) Register C (channel = 0) -------- */ +#define TC_RC0_RC (0xffff << 0) /**< \brief (TC_RC0) Register C */ +/* -------- TC_SR0 : (TC Offset: 0x20) Status Register (channel = 0) -------- */ +#define TC_SR0_COVFS (0x1 << 0) /**< \brief (TC_SR0) Counter Overflow Status */ +#define TC_SR0_LOVRS (0x1 << 1) /**< \brief (TC_SR0) Load Overrun Status */ +#define TC_SR0_CPAS (0x1 << 2) /**< \brief (TC_SR0) RA Compare Status */ +#define TC_SR0_CPBS (0x1 << 3) /**< \brief (TC_SR0) RB Compare Status */ +#define TC_SR0_CPCS (0x1 << 4) /**< \brief (TC_SR0) RC Compare Status */ +#define TC_SR0_LDRAS (0x1 << 5) /**< \brief (TC_SR0) RA Loading Status */ +#define TC_SR0_LDRBS (0x1 << 6) /**< \brief (TC_SR0) RB Loading Status */ +#define TC_SR0_ETRGS (0x1 << 7) /**< \brief (TC_SR0) External Trigger Status */ +#define TC_SR0_CLKSTA (0x1 << 16) /**< \brief (TC_SR0) Clock Enabling Status */ +#define TC_SR0_MTIOA (0x1 << 17) /**< \brief (TC_SR0) TIOA Mirror */ +#define TC_SR0_MTIOB (0x1 << 18) /**< \brief (TC_SR0) TIOB Mirror */ +/* -------- TC_IER0 : (TC Offset: 0x24) Interrupt Enable Register (channel = 0) -------- */ +#define TC_IER0_COVFS (0x1 << 0) /**< \brief (TC_IER0) Counter Overflow */ +#define TC_IER0_LOVRS (0x1 << 1) /**< \brief (TC_IER0) Load Overrun */ +#define TC_IER0_CPAS (0x1 << 2) /**< \brief (TC_IER0) RA Compare */ +#define TC_IER0_CPBS (0x1 << 3) /**< \brief (TC_IER0) RB Compare */ +#define TC_IER0_CPCS (0x1 << 4) /**< \brief (TC_IER0) RC Compare */ +#define TC_IER0_LDRAS (0x1 << 5) /**< \brief (TC_IER0) RA Loading */ +#define TC_IER0_LDRBS (0x1 << 6) /**< \brief (TC_IER0) RB Loading */ +#define TC_IER0_ETRGS (0x1 << 7) /**< \brief (TC_IER0) External Trigger */ +/* -------- TC_IDR0 : (TC Offset: 0x28) Interrupt Disable Register (channel = 0) -------- */ +#define TC_IDR0_COVFS (0x1 << 0) /**< \brief (TC_IDR0) Counter Overflow */ +#define TC_IDR0_LOVRS (0x1 << 1) /**< \brief (TC_IDR0) Load Overrun */ +#define TC_IDR0_CPAS (0x1 << 2) /**< \brief (TC_IDR0) RA Compare */ +#define TC_IDR0_CPBS (0x1 << 3) /**< \brief (TC_IDR0) RB Compare */ +#define TC_IDR0_CPCS (0x1 << 4) /**< \brief (TC_IDR0) RC Compare */ +#define TC_IDR0_LDRAS (0x1 << 5) /**< \brief (TC_IDR0) RA Loading */ +#define TC_IDR0_LDRBS (0x1 << 6) /**< \brief (TC_IDR0) RB Loading */ +#define TC_IDR0_ETRGS (0x1 << 7) /**< \brief (TC_IDR0) External Trigger */ +/* -------- TC_IMR0 : (TC Offset: 0x2C) Interrupt Mask Register (channel = 0) -------- */ +#define TC_IMR0_COVFS (0x1 << 0) /**< \brief (TC_IMR0) Counter Overflow */ +#define TC_IMR0_LOVRS (0x1 << 1) /**< \brief (TC_IMR0) Load Overrun */ +#define TC_IMR0_CPAS (0x1 << 2) /**< \brief (TC_IMR0) RA Compare */ +#define TC_IMR0_CPBS (0x1 << 3) /**< \brief (TC_IMR0) RB Compare */ +#define TC_IMR0_CPCS (0x1 << 4) /**< \brief (TC_IMR0) RC Compare */ +#define TC_IMR0_LDRAS (0x1 << 5) /**< \brief (TC_IMR0) RA Loading */ +#define TC_IMR0_LDRBS (0x1 << 6) /**< \brief (TC_IMR0) RB Loading */ +#define TC_IMR0_ETRGS (0x1 << 7) /**< \brief (TC_IMR0) External Trigger */ +/* -------- TC_CCR1 : (TC Offset: 0x40) Channel Control Register (channel = 1) -------- */ +#define TC_CCR1_CLKEN (0x1 << 0) /**< \brief (TC_CCR1) Counter Clock Enable Command */ +#define TC_CCR1_CLKDIS (0x1 << 1) /**< \brief (TC_CCR1) Counter Clock Disable Command */ +#define TC_CCR1_SWTRG (0x1 << 2) /**< \brief (TC_CCR1) Software Trigger Command */ +/* -------- TC_CMR1 : (TC Offset: 0x44) Channel Mode Register (channel = 1) -------- */ +#define TC_CMR1_TCCLKS (0x7 << 0) /**< \brief (TC_CMR1) Clock Selection */ +#define TC_CMR1_CLKI (0x1 << 3) /**< \brief (TC_CMR1) Clock Invert */ +#define TC_CMR1_BURST (0x3 << 4) /**< \brief (TC_CMR1) Burst Signal Selection */ +#define TC_CMR1_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR1) The clock is not gated by an external signal. */ +#define TC_CMR1_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR1) XC0 is ANDed with the selected clock. */ +#define TC_CMR1_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR1) XC1 is ANDed with the selected clock. */ +#define TC_CMR1_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR1) XC2 is ANDed with the selected clock. */ +#define TC_CMR1_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR1) Counter Clock Stopped with RB Loading */ +#define TC_CMR1_LDBDIS (0x1 << 7) /**< \brief (TC_CMR1) Counter Clock Disable with RB Loading */ +#define TC_CMR1_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR1) External Trigger Edge Selection */ +#define TC_CMR1_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR1) none */ +#define TC_CMR1_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR1) rising edge */ +#define TC_CMR1_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR1) falling edge */ +#define TC_CMR1_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR1) each edge */ +#define TC_CMR1_ABETRG (0x1 << 10) /**< \brief (TC_CMR1) TIOA or TIOB External Trigger Selection */ +#define TC_CMR1_CPCTRG (0x1 << 14) /**< \brief (TC_CMR1) RC Compare Trigger Enable */ +#define TC_CMR1_WAVE (0x1 << 15) /**< \brief (TC_CMR1) */ +#define TC_CMR1_LDRA (0x3 << 16) /**< \brief (TC_CMR1) RA Loading Selection */ +#define TC_CMR1_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR1) none */ +#define TC_CMR1_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR1) rising edge of TIOA */ +#define TC_CMR1_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR1) falling edge of TIOA */ +#define TC_CMR1_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR1) each edge of TIOA */ +#define TC_CMR1_LDRB (0x3 << 18) /**< \brief (TC_CMR1) RB Loading Selection */ +#define TC_CMR1_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR1) none */ +#define TC_CMR1_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR1) rising edge of TIOA */ +#define TC_CMR1_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR1) falling edge of TIOA */ +#define TC_CMR1_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR1) each edge of TIOA */ +/* -------- TC_CV1 : (TC Offset: 0x50) Counter Value (channel = 1) -------- */ +#define TC_CV1_CV (0xffff << 0) /**< \brief (TC_CV1) Counter Value */ +/* -------- TC_RA1 : (TC Offset: 0x54) Register A (channel = 1) -------- */ +#define TC_RA1_RA (0xffff << 0) /**< \brief (TC_RA1) Register A */ +/* -------- TC_RB1 : (TC Offset: 0x58) Register B (channel = 1) -------- */ +#define TC_RB1_RB (0xffff << 0) /**< \brief (TC_RB1) Register B */ +/* -------- TC_RC1 : (TC Offset: 0x5C) Register C (channel = 1) -------- */ +#define TC_RC1_RC (0xffff << 0) /**< \brief (TC_RC1) Register C */ +/* -------- TC_SR1 : (TC Offset: 0x60) Status Register (channel = 1) -------- */ +#define TC_SR1_COVFS (0x1 << 0) /**< \brief (TC_SR1) Counter Overflow Status */ +#define TC_SR1_LOVRS (0x1 << 1) /**< \brief (TC_SR1) Load Overrun Status */ +#define TC_SR1_CPAS (0x1 << 2) /**< \brief (TC_SR1) RA Compare Status */ +#define TC_SR1_CPBS (0x1 << 3) /**< \brief (TC_SR1) RB Compare Status */ +#define TC_SR1_CPCS (0x1 << 4) /**< \brief (TC_SR1) RC Compare Status */ +#define TC_SR1_LDRAS (0x1 << 5) /**< \brief (TC_SR1) RA Loading Status */ +#define TC_SR1_LDRBS (0x1 << 6) /**< \brief (TC_SR1) RB Loading Status */ +#define TC_SR1_ETRGS (0x1 << 7) /**< \brief (TC_SR1) External Trigger Status */ +#define TC_SR1_CLKSTA (0x1 << 16) /**< \brief (TC_SR1) Clock Enabling Status */ +#define TC_SR1_MTIOA (0x1 << 17) /**< \brief (TC_SR1) TIOA Mirror */ +#define TC_SR1_MTIOB (0x1 << 18) /**< \brief (TC_SR1) TIOB Mirror */ +/* -------- TC_IER1 : (TC Offset: 0x64) Interrupt Enable Register (channel = 1) -------- */ +#define TC_IER1_COVFS (0x1 << 0) /**< \brief (TC_IER1) Counter Overflow */ +#define TC_IER1_LOVRS (0x1 << 1) /**< \brief (TC_IER1) Load Overrun */ +#define TC_IER1_CPAS (0x1 << 2) /**< \brief (TC_IER1) RA Compare */ +#define TC_IER1_CPBS (0x1 << 3) /**< \brief (TC_IER1) RB Compare */ +#define TC_IER1_CPCS (0x1 << 4) /**< \brief (TC_IER1) RC Compare */ +#define TC_IER1_LDRAS (0x1 << 5) /**< \brief (TC_IER1) RA Loading */ +#define TC_IER1_LDRBS (0x1 << 6) /**< \brief (TC_IER1) RB Loading */ +#define TC_IER1_ETRGS (0x1 << 7) /**< \brief (TC_IER1) External Trigger */ +/* -------- TC_IDR1 : (TC Offset: 0x68) Interrupt Disable Register (channel = 1) -------- */ +#define TC_IDR1_COVFS (0x1 << 0) /**< \brief (TC_IDR1) Counter Overflow */ +#define TC_IDR1_LOVRS (0x1 << 1) /**< \brief (TC_IDR1) Load Overrun */ +#define TC_IDR1_CPAS (0x1 << 2) /**< \brief (TC_IDR1) RA Compare */ +#define TC_IDR1_CPBS (0x1 << 3) /**< \brief (TC_IDR1) RB Compare */ +#define TC_IDR1_CPCS (0x1 << 4) /**< \brief (TC_IDR1) RC Compare */ +#define TC_IDR1_LDRAS (0x1 << 5) /**< \brief (TC_IDR1) RA Loading */ +#define TC_IDR1_LDRBS (0x1 << 6) /**< \brief (TC_IDR1) RB Loading */ +#define TC_IDR1_ETRGS (0x1 << 7) /**< \brief (TC_IDR1) External Trigger */ +/* -------- TC_IMR1 : (TC Offset: 0x6C) Interrupt Mask Register (channel = 1) -------- */ +#define TC_IMR1_COVFS (0x1 << 0) /**< \brief (TC_IMR1) Counter Overflow */ +#define TC_IMR1_LOVRS (0x1 << 1) /**< \brief (TC_IMR1) Load Overrun */ +#define TC_IMR1_CPAS (0x1 << 2) /**< \brief (TC_IMR1) RA Compare */ +#define TC_IMR1_CPBS (0x1 << 3) /**< \brief (TC_IMR1) RB Compare */ +#define TC_IMR1_CPCS (0x1 << 4) /**< \brief (TC_IMR1) RC Compare */ +#define TC_IMR1_LDRAS (0x1 << 5) /**< \brief (TC_IMR1) RA Loading */ +#define TC_IMR1_LDRBS (0x1 << 6) /**< \brief (TC_IMR1) RB Loading */ +#define TC_IMR1_ETRGS (0x1 << 7) /**< \brief (TC_IMR1) External Trigger */ +/* -------- TC_CCR2 : (TC Offset: 0x80) Channel Control Register (channel = 2) -------- */ +#define TC_CCR2_CLKEN (0x1 << 0) /**< \brief (TC_CCR2) Counter Clock Enable Command */ +#define TC_CCR2_CLKDIS (0x1 << 1) /**< \brief (TC_CCR2) Counter Clock Disable Command */ +#define TC_CCR2_SWTRG (0x1 << 2) /**< \brief (TC_CCR2) Software Trigger Command */ +/* -------- TC_CMR2 : (TC Offset: 0x84) Channel Mode Register (channel = 2) -------- */ +#define TC_CMR2_TCCLKS (0x7 << 0) /**< \brief (TC_CMR2) Clock Selection */ +#define TC_CMR2_CLKI (0x1 << 3) /**< \brief (TC_CMR2) Clock Invert */ +#define TC_CMR2_BURST (0x3 << 4) /**< \brief (TC_CMR2) Burst Signal Selection */ +#define TC_CMR2_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR2) The clock is not gated by an external signal. */ +#define TC_CMR2_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR2) XC0 is ANDed with the selected clock. */ +#define TC_CMR2_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR2) XC1 is ANDed with the selected clock. */ +#define TC_CMR2_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR2) XC2 is ANDed with the selected clock. */ +#define TC_CMR2_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR2) Counter Clock Stopped with RB Loading */ +#define TC_CMR2_LDBDIS (0x1 << 7) /**< \brief (TC_CMR2) Counter Clock Disable with RB Loading */ +#define TC_CMR2_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR2) External Trigger Edge Selection */ +#define TC_CMR2_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR2) none */ +#define TC_CMR2_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR2) rising edge */ +#define TC_CMR2_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR2) falling edge */ +#define TC_CMR2_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR2) each edge */ +#define TC_CMR2_ABETRG (0x1 << 10) /**< \brief (TC_CMR2) TIOA or TIOB External Trigger Selection */ +#define TC_CMR2_CPCTRG (0x1 << 14) /**< \brief (TC_CMR2) RC Compare Trigger Enable */ +#define TC_CMR2_WAVE (0x1 << 15) /**< \brief (TC_CMR2) */ +#define TC_CMR2_LDRA (0x3 << 16) /**< \brief (TC_CMR2) RA Loading Selection */ +#define TC_CMR2_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR2) none */ +#define TC_CMR2_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR2) rising edge of TIOA */ +#define TC_CMR2_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR2) falling edge of TIOA */ +#define TC_CMR2_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR2) each edge of TIOA */ +#define TC_CMR2_LDRB (0x3 << 18) /**< \brief (TC_CMR2) RB Loading Selection */ +#define TC_CMR2_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR2) none */ +#define TC_CMR2_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR2) rising edge of TIOA */ +#define TC_CMR2_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR2) falling edge of TIOA */ +#define TC_CMR2_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR2) each edge of TIOA */ +/* -------- TC_CV2 : (TC Offset: 0x90) Counter Value (channel = 2) -------- */ +#define TC_CV2_CV (0xffff << 0) /**< \brief (TC_CV2) Counter Value */ +/* -------- TC_RA2 : (TC Offset: 0x94) Register A (channel = 2) -------- */ +#define TC_RA2_RA (0xffff << 0) /**< \brief (TC_RA2) Register A */ +/* -------- TC_RB2 : (TC Offset: 0x98) Register B (channel = 2) -------- */ +#define TC_RB2_RB (0xffff << 0) /**< \brief (TC_RB2) Register B */ +/* -------- TC_RC2 : (TC Offset: 0x9C) Register C (channel = 2) -------- */ +#define TC_RC2_RC (0xffff << 0) /**< \brief (TC_RC2) Register C */ +/* -------- TC_SR2 : (TC Offset: 0xA0) Status Register (channel = 2) -------- */ +#define TC_SR2_COVFS (0x1 << 0) /**< \brief (TC_SR2) Counter Overflow Status */ +#define TC_SR2_LOVRS (0x1 << 1) /**< \brief (TC_SR2) Load Overrun Status */ +#define TC_SR2_CPAS (0x1 << 2) /**< \brief (TC_SR2) RA Compare Status */ +#define TC_SR2_CPBS (0x1 << 3) /**< \brief (TC_SR2) RB Compare Status */ +#define TC_SR2_CPCS (0x1 << 4) /**< \brief (TC_SR2) RC Compare Status */ +#define TC_SR2_LDRAS (0x1 << 5) /**< \brief (TC_SR2) RA Loading Status */ +#define TC_SR2_LDRBS (0x1 << 6) /**< \brief (TC_SR2) RB Loading Status */ +#define TC_SR2_ETRGS (0x1 << 7) /**< \brief (TC_SR2) External Trigger Status */ +#define TC_SR2_CLKSTA (0x1 << 16) /**< \brief (TC_SR2) Clock Enabling Status */ +#define TC_SR2_MTIOA (0x1 << 17) /**< \brief (TC_SR2) TIOA Mirror */ +#define TC_SR2_MTIOB (0x1 << 18) /**< \brief (TC_SR2) TIOB Mirror */ +/* -------- TC_IER2 : (TC Offset: 0xA4) Interrupt Enable Register (channel = 2) -------- */ +#define TC_IER2_COVFS (0x1 << 0) /**< \brief (TC_IER2) Counter Overflow */ +#define TC_IER2_LOVRS (0x1 << 1) /**< \brief (TC_IER2) Load Overrun */ +#define TC_IER2_CPAS (0x1 << 2) /**< \brief (TC_IER2) RA Compare */ +#define TC_IER2_CPBS (0x1 << 3) /**< \brief (TC_IER2) RB Compare */ +#define TC_IER2_CPCS (0x1 << 4) /**< \brief (TC_IER2) RC Compare */ +#define TC_IER2_LDRAS (0x1 << 5) /**< \brief (TC_IER2) RA Loading */ +#define TC_IER2_LDRBS (0x1 << 6) /**< \brief (TC_IER2) RB Loading */ +#define TC_IER2_ETRGS (0x1 << 7) /**< \brief (TC_IER2) External Trigger */ +/* -------- TC_IDR2 : (TC Offset: 0xA8) Interrupt Disable Register (channel = 2) -------- */ +#define TC_IDR2_COVFS (0x1 << 0) /**< \brief (TC_IDR2) Counter Overflow */ +#define TC_IDR2_LOVRS (0x1 << 1) /**< \brief (TC_IDR2) Load Overrun */ +#define TC_IDR2_CPAS (0x1 << 2) /**< \brief (TC_IDR2) RA Compare */ +#define TC_IDR2_CPBS (0x1 << 3) /**< \brief (TC_IDR2) RB Compare */ +#define TC_IDR2_CPCS (0x1 << 4) /**< \brief (TC_IDR2) RC Compare */ +#define TC_IDR2_LDRAS (0x1 << 5) /**< \brief (TC_IDR2) RA Loading */ +#define TC_IDR2_LDRBS (0x1 << 6) /**< \brief (TC_IDR2) RB Loading */ +#define TC_IDR2_ETRGS (0x1 << 7) /**< \brief (TC_IDR2) External Trigger */ +/* -------- TC_IMR2 : (TC Offset: 0xAC) Interrupt Mask Register (channel = 2) -------- */ +#define TC_IMR2_COVFS (0x1 << 0) /**< \brief (TC_IMR2) Counter Overflow */ +#define TC_IMR2_LOVRS (0x1 << 1) /**< \brief (TC_IMR2) Load Overrun */ +#define TC_IMR2_CPAS (0x1 << 2) /**< \brief (TC_IMR2) RA Compare */ +#define TC_IMR2_CPBS (0x1 << 3) /**< \brief (TC_IMR2) RB Compare */ +#define TC_IMR2_CPCS (0x1 << 4) /**< \brief (TC_IMR2) RC Compare */ +#define TC_IMR2_LDRAS (0x1 << 5) /**< \brief (TC_IMR2) RA Loading */ +#define TC_IMR2_LDRBS (0x1 << 6) /**< \brief (TC_IMR2) RB Loading */ +#define TC_IMR2_ETRGS (0x1 << 7) /**< \brief (TC_IMR2) External Trigger */ +/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ +#define TC_BCR_SYNC (0x1 << 0) /**< \brief (TC_BCR) Synchro Command */ +/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ +#define TC_BMR_TC0XC0S (0x3 << 0) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ +#define TC_BMR_TC0XC0S_TCLK0 (0x0 << 0) /**< \brief (TC_BMR) TCLK0 */ +#define TC_BMR_TC0XC0S_NONE (0x1 << 0) /**< \brief (TC_BMR) none */ +#define TC_BMR_TC0XC0S_TIOA1 (0x2 << 0) /**< \brief (TC_BMR) TIOA1 */ +#define TC_BMR_TC0XC0S_TIOA2 (0x3 << 0) /**< \brief (TC_BMR) TIOA2 */ +#define TC_BMR_TC1XC1S (0x3 << 2) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ +#define TC_BMR_TC1XC1S_TCLK1 (0x0 << 2) /**< \brief (TC_BMR) TCLK1 */ +#define TC_BMR_TC1XC1S_NONE (0x1 << 2) /**< \brief (TC_BMR) none */ +#define TC_BMR_TC1XC1S_TIOA0 (0x2 << 2) /**< \brief (TC_BMR) TIOA0 */ +#define TC_BMR_TC1XC1S_TIOA2 (0x3 << 2) /**< \brief (TC_BMR) TIOA2 */ +#define TC_BMR_TC2XC2S (0x3 << 4) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ +#define TC_BMR_TC2XC2S_TCLK2 (0x0 << 4) /**< \brief (TC_BMR) TCLK2 */ +#define TC_BMR_TC2XC2S_NONE (0x1 << 4) /**< \brief (TC_BMR) none */ +#define TC_BMR_TC2XC2S_TIOA0 (0x2 << 4) /**< \brief (TC_BMR) TIOA0 */ +#define TC_BMR_TC2XC2S_TIOA1 (0x3 << 4) /**< \brief (TC_BMR) TIOA1 */ +#define TC_BMR_QDEN (0x1 << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */ +#define TC_BMR_POSEN (0x1 << 9) /**< \brief (TC_BMR) POSition ENabled */ +#define TC_BMR_SPEEDEN (0x1 << 10) /**< \brief (TC_BMR) SPEED ENabled */ +#define TC_BMR_QDTRANS (0x1 << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */ +#define TC_BMR_EDGPHA (0x1 << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */ +#define TC_BMR_INVA (0x1 << 13) /**< \brief (TC_BMR) INVerted phA */ +#define TC_BMR_INVB (0x1 << 14) /**< \brief (TC_BMR) INVerted phB */ +#define TC_BMR_INVIDX (0x1 << 15) /**< \brief (TC_BMR) INVerted InDeX */ +#define TC_BMR_SWAP (0x1 << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */ +#define TC_BMR_IDXPHB (0x1 << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */ +#define TC_BMR_FILTER (0x1 << 19) /**< \brief (TC_BMR) */ +#define TC_BMR_MAXFILT (0x3f << 20) /**< \brief (TC_BMR) MAXimum FILTer */ +/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ +#define TC_QIER_IDX (0x1 << 0) /**< \brief (TC_QIER) InDeX */ +#define TC_QIER_DIRCHG (0x1 << 1) /**< \brief (TC_QIER) DIRection CHanGe */ +#define TC_QIER_QERR (0x1 << 2) /**< \brief (TC_QIER) Quadrature ERRor */ +/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ +#define TC_QIDR_IDX (0x1 << 0) /**< \brief (TC_QIDR) InDeX */ +#define TC_QIDR_DIRCHG (0x1 << 1) /**< \brief (TC_QIDR) DIRection CHanGe */ +#define TC_QIDR_QERR (0x1 << 2) /**< \brief (TC_QIDR) Quadrature ERRor */ +/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ +#define TC_QIMR_IDX (0x1 << 0) /**< \brief (TC_QIMR) InDeX */ +#define TC_QIMR_DIRCHG (0x1 << 1) /**< \brief (TC_QIMR) DIRection CHanGe */ +#define TC_QIMR_QERR (0x1 << 2) /**< \brief (TC_QIMR) Quadrature ERRor */ +/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ +#define TC_QISR_IDX (0x1 << 0) /**< \brief (TC_QISR) InDeX */ +#define TC_QISR_DIRCHG (0x1 << 1) /**< \brief (TC_QISR) DIRection CHanGe */ +#define TC_QISR_QERR (0x1 << 2) /**< \brief (TC_QISR) Quadrature ERRor */ +#define TC_QISR_DIR (0x1 << 8) /**< \brief (TC_QISR) Direction */ +/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */ +#define TC_FMR_ENCF0 (0x1 << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */ +#define TC_FMR_ENCF1 (0x1 << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */ +/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */ +#define TC_WPMR_WPEN (0x1 << 0) /**< \brief (TC_WPMR) Write Protect Enable */ +#define TC_WPMR_WPKEY (0xffffff << 8) /**< \brief (TC_WPMR) Write Protect KEY */ +/* -------- TC_VER : (TC Offset: 0xFC) Version Register -------- */ +#define TC_VER_VERSION (0xfff << 0) /**< \brief (TC_VER) */ +#define TC_VER_MFN (0x7 << 16) /**< \brief (TC_VER) */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Two-wire Interface */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_TWI Two-wire Interface */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Twi hardware registers */ +typedef struct { + WoReg TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */ + RwReg TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */ + RwReg TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */ + RwReg TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */ + RwReg TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */ + RwReg Reserved1[3]; + RoReg TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */ + WoReg TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */ + WoReg TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */ + RoReg TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */ + RoReg TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */ + WoReg TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */ + RwReg Reserved2[50]; + RwReg TWI_RPR; /**< \brief (Twi Offset: 0x100) Receive Pointer Register */ + RwReg TWI_RCR; /**< \brief (Twi Offset: 0x104) Receive Counter Register */ + RwReg TWI_TPR; /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */ + RwReg TWI_TCR; /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */ + RwReg TWI_RNPR; /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */ + RwReg TWI_RNCR; /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */ + RwReg TWI_TNPR; /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */ + RwReg TWI_TNCR; /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */ + WoReg TWI_PTCR; /**< \brief (Twi Offset: 0x120) Transfer Control Register */ + RoReg TWI_PTSR; /**< \brief (Twi Offset: 0x124) Transfer Status Register */ +} Twi; +#endif /* __ASSEMBLY__ */ +/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */ +#define TWI_CR_START (0x1 << 0) /**< \brief (TWI_CR) Send a START Condition */ +#define TWI_CR_STOP (0x1 << 1) /**< \brief (TWI_CR) Send a STOP Condition */ +#define TWI_CR_MSEN (0x1 << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */ +#define TWI_CR_MSDIS (0x1 << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */ +#define TWI_CR_SVEN (0x1 << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */ +#define TWI_CR_SVDIS (0x1 << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */ +#define TWI_CR_QUICK (0x1 << 6) /**< \brief (TWI_CR) SMBUS Quick Command */ +#define TWI_CR_SWRST (0x1 << 7) /**< \brief (TWI_CR) Software Reset */ +/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */ +#define TWI_MMR_IADRSZ (0x3 << 8) /**< \brief (TWI_MMR) Internal Device Address Size */ +#define TWI_MMR_IADRSZ_NO (0x0 << 8) /**< \brief (TWI_MMR) No internal device address */ +#define TWI_MMR_IADRSZ_1_BYTE (0x1 << 8) /**< \brief (TWI_MMR) One-byte internal device address */ +#define TWI_MMR_IADRSZ_2_BYTE (0x2 << 8) /**< \brief (TWI_MMR) Two-byte internal device address */ +#define TWI_MMR_IADRSZ_3_BYTE (0x3 << 8) /**< \brief (TWI_MMR) Three-byte internal device address */ +#define TWI_MMR_MREAD (0x1 << 12) /**< \brief (TWI_MMR) Master Read Direction */ +#define TWI_MMR_DADR (0x7f << 16) /**< \brief (TWI_MMR) Device Address */ +/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */ +#define TWI_SMR_SADR (0x7f << 16) /**< \brief (TWI_SMR) Slave Address */ +/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */ +#define TWI_IADR_IADR (0xffffff << 0) /**< \brief (TWI_IADR) Internal Address */ +/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */ +#define TWI_CWGR_CLDIV (0xff << 0) /**< \brief (TWI_CWGR) Clock Low Divider */ +#define TWI_CWGR_CHDIV (0xff << 8) /**< \brief (TWI_CWGR) Clock High Divider */ +#define TWI_CWGR_CKDIV (0x7 << 16) /**< \brief (TWI_CWGR) Clock Divider */ +/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */ +#define TWI_SR_TXCOMP (0x1 << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */ +#define TWI_SR_RXRDY (0x1 << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */ +#define TWI_SR_TXRDY (0x1 << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */ +#define TWI_SR_SVREAD (0x1 << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */ +#define TWI_SR_SVACC (0x1 << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */ +#define TWI_SR_GACC (0x1 << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */ +#define TWI_SR_OVRE (0x1 << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */ +#define TWI_SR_NACK (0x1 << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */ +#define TWI_SR_ARBLST (0x1 << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */ +#define TWI_SR_SCLWS (0x1 << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */ +#define TWI_SR_EOSACC (0x1 << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */ +#define TWI_SR_ENDRX (0x1 << 12) /**< \brief (TWI_SR) End of RX buffer */ +#define TWI_SR_ENDTX (0x1 << 13) /**< \brief (TWI_SR) End of TX buffer */ +#define TWI_SR_RXBUFF (0x1 << 14) /**< \brief (TWI_SR) RX Buffer Full */ +#define TWI_SR_TXBUFE (0x1 << 15) /**< \brief (TWI_SR) TX Buffer Empty */ +/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */ +#define TWI_IER_TXCOMP (0x1 << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */ +#define TWI_IER_RXRDY (0x1 << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */ +#define TWI_IER_TXRDY (0x1 << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */ +#define TWI_IER_SVACC (0x1 << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */ +#define TWI_IER_GACC (0x1 << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */ +#define TWI_IER_OVRE (0x1 << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */ +#define TWI_IER_NACK (0x1 << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */ +#define TWI_IER_ARBLST (0x1 << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */ +#define TWI_IER_SCL_WS (0x1 << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */ +#define TWI_IER_EOSACC (0x1 << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */ +#define TWI_IER_ENDRX (0x1 << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */ +#define TWI_IER_ENDTX (0x1 << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */ +#define TWI_IER_RXBUFF (0x1 << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */ +#define TWI_IER_TXBUFE (0x1 << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */ +/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */ +#define TWI_IDR_TXCOMP (0x1 << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */ +#define TWI_IDR_RXRDY (0x1 << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */ +#define TWI_IDR_TXRDY (0x1 << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */ +#define TWI_IDR_SVACC (0x1 << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */ +#define TWI_IDR_GACC (0x1 << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */ +#define TWI_IDR_OVRE (0x1 << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */ +#define TWI_IDR_NACK (0x1 << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */ +#define TWI_IDR_ARBLST (0x1 << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */ +#define TWI_IDR_SCL_WS (0x1 << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */ +#define TWI_IDR_EOSACC (0x1 << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */ +#define TWI_IDR_ENDRX (0x1 << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */ +#define TWI_IDR_ENDTX (0x1 << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */ +#define TWI_IDR_RXBUFF (0x1 << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */ +#define TWI_IDR_TXBUFE (0x1 << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */ +/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */ +#define TWI_IMR_TXCOMP (0x1 << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */ +#define TWI_IMR_RXRDY (0x1 << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */ +#define TWI_IMR_TXRDY (0x1 << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */ +#define TWI_IMR_SVACC (0x1 << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */ +#define TWI_IMR_GACC (0x1 << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */ +#define TWI_IMR_OVRE (0x1 << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */ +#define TWI_IMR_NACK (0x1 << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */ +#define TWI_IMR_ARBLST (0x1 << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */ +#define TWI_IMR_SCL_WS (0x1 << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */ +#define TWI_IMR_EOSACC (0x1 << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */ +#define TWI_IMR_ENDRX (0x1 << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */ +#define TWI_IMR_ENDTX (0x1 << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */ +#define TWI_IMR_RXBUFF (0x1 << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */ +#define TWI_IMR_TXBUFE (0x1 << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */ +/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */ +#define TWI_RHR_RXDATA (0xff << 0) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */ +/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */ +#define TWI_THR_TXDATA (0xff << 0) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */ +/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */ +#define TWI_RPR_RXPTR (0xffffffff << 0) /**< \brief (TWI_RPR) Receive Pointer Register */ +/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */ +#define TWI_RCR_RXCTR (0xffff << 0) /**< \brief (TWI_RCR) Receive Counter Register */ +/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */ +#define TWI_TPR_TXPTR (0xffffffff << 0) /**< \brief (TWI_TPR) Transmit Counter Register */ +/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */ +#define TWI_TCR_TXCTR (0xffff << 0) /**< \brief (TWI_TCR) Transmit Counter Register */ +/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */ +#define TWI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (TWI_RNPR) Receive Next Pointer */ +/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */ +#define TWI_RNCR_RXNCTR (0xffff << 0) /**< \brief (TWI_RNCR) Receive Next Counter */ +/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */ +#define TWI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (TWI_TNPR) Transmit Next Pointer */ +/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */ +#define TWI_TNCR_TXNCTR (0xffff << 0) /**< \brief (TWI_TNCR) Transmit Counter Next */ +/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */ +#define TWI_PTCR_RXTEN (0x1 << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */ +#define TWI_PTCR_RXTDIS (0x1 << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */ +#define TWI_PTCR_TXTEN (0x1 << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */ +#define TWI_PTCR_TXTDIS (0x1 << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */ +/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */ +#define TWI_PTSR_RXTEN (0x1 << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */ +#define TWI_PTSR_TXTEN (0x1 << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_UART Universal Asynchronous Receiver Transmitter */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Uart hardware registers */ +typedef struct { + WoReg UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ + RwReg UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ + WoReg UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ + WoReg UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ + RoReg UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ + RoReg UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ + RoReg UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ + WoReg UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ + RwReg UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ + RwReg Reserved1[55]; + RwReg UART_RPR; /**< \brief (Uart Offset: 0x100) Receive Pointer Register */ + RwReg UART_RCR; /**< \brief (Uart Offset: 0x104) Receive Counter Register */ + RwReg UART_TPR; /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */ + RwReg UART_TCR; /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */ + RwReg UART_RNPR; /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */ + RwReg UART_RNCR; /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */ + RwReg UART_TNPR; /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */ + RwReg UART_TNCR; /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */ + WoReg UART_PTCR; /**< \brief (Uart Offset: 0x120) Transfer Control Register */ + RoReg UART_PTSR; /**< \brief (Uart Offset: 0x124) Transfer Status Register */ +} Uart; +#endif /* __ASSEMBLY__ */ +/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ +#define UART_CR_RSTRX (0x1 << 2) /**< \brief (UART_CR) Reset Receiver */ +#define UART_CR_RSTTX (0x1 << 3) /**< \brief (UART_CR) Reset Transmitter */ +#define UART_CR_RXEN (0x1 << 4) /**< \brief (UART_CR) Receiver Enable */ +#define UART_CR_RXDIS (0x1 << 5) /**< \brief (UART_CR) Receiver Disable */ +#define UART_CR_TXEN (0x1 << 6) /**< \brief (UART_CR) Transmitter Enable */ +#define UART_CR_TXDIS (0x1 << 7) /**< \brief (UART_CR) Transmitter Disable */ +#define UART_CR_RSTSTA (0x1 << 8) /**< \brief (UART_CR) Reset Status Bits */ +/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ +#define UART_MR_PAR (0x7 << 9) /**< \brief (UART_MR) Parity Type */ +#define UART_MR_CHMODE (0x3 << 14) /**< \brief (UART_MR) Channel Mode */ +/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ +#define UART_IER_RXRDY (0x1 << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ +#define UART_IER_TXRDY (0x1 << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ +#define UART_IER_ENDRX (0x1 << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */ +#define UART_IER_ENDTX (0x1 << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */ +#define UART_IER_OVRE (0x1 << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ +#define UART_IER_FRAME (0x1 << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ +#define UART_IER_PARE (0x1 << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ +#define UART_IER_TXEMPTY (0x1 << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ +#define UART_IER_TXBUFE (0x1 << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */ +#define UART_IER_RXBUFF (0x1 << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */ +/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ +#define UART_IDR_RXRDY (0x1 << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ +#define UART_IDR_TXRDY (0x1 << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ +#define UART_IDR_ENDRX (0x1 << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */ +#define UART_IDR_ENDTX (0x1 << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */ +#define UART_IDR_OVRE (0x1 << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ +#define UART_IDR_FRAME (0x1 << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ +#define UART_IDR_PARE (0x1 << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ +#define UART_IDR_TXEMPTY (0x1 << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ +#define UART_IDR_TXBUFE (0x1 << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */ +#define UART_IDR_RXBUFF (0x1 << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */ +/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ +#define UART_IMR_RXRDY (0x1 << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ +#define UART_IMR_TXRDY (0x1 << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ +#define UART_IMR_ENDRX (0x1 << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */ +#define UART_IMR_ENDTX (0x1 << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */ +#define UART_IMR_OVRE (0x1 << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ +#define UART_IMR_FRAME (0x1 << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ +#define UART_IMR_PARE (0x1 << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ +#define UART_IMR_TXEMPTY (0x1 << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ +#define UART_IMR_TXBUFE (0x1 << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */ +#define UART_IMR_RXBUFF (0x1 << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */ +/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ +#define UART_SR_RXRDY (0x1 << 0) /**< \brief (UART_SR) Receiver Ready */ +#define UART_SR_TXRDY (0x1 << 1) /**< \brief (UART_SR) Transmitter Ready */ +#define UART_SR_ENDRX (0x1 << 3) /**< \brief (UART_SR) End of Receiver Transfer */ +#define UART_SR_ENDTX (0x1 << 4) /**< \brief (UART_SR) End of Transmitter Transfer */ +#define UART_SR_OVRE (0x1 << 5) /**< \brief (UART_SR) Overrun Error */ +#define UART_SR_FRAME (0x1 << 6) /**< \brief (UART_SR) Framing Error */ +#define UART_SR_PARE (0x1 << 7) /**< \brief (UART_SR) Parity Error */ +#define UART_SR_TXEMPTY (0x1 << 9) /**< \brief (UART_SR) Transmitter Empty */ +#define UART_SR_TXBUFE (0x1 << 11) /**< \brief (UART_SR) Transmission Buffer Empty */ +#define UART_SR_RXBUFF (0x1 << 12) /**< \brief (UART_SR) Receive Buffer Full */ +/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ +#define UART_RHR_RXCHR (0xff << 0) /**< \brief (UART_RHR) Received Character */ +/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ +#define UART_THR_TXCHR (0xff << 0) /**< \brief (UART_THR) Character to be Transmitted */ +/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define UART_BRGR_CD (0xffff << 0) /**< \brief (UART_BRGR) Clock Divisor */ +/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */ +#define UART_RPR_RXPTR (0xffffffff << 0) /**< \brief (UART_RPR) Receive Pointer Register */ +/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */ +#define UART_RCR_RXCTR (0xffff << 0) /**< \brief (UART_RCR) Receive Counter Register */ +/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */ +#define UART_TPR_TXPTR (0xffffffff << 0) /**< \brief (UART_TPR) Transmit Counter Register */ +/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */ +#define UART_TCR_TXCTR (0xffff << 0) /**< \brief (UART_TCR) Transmit Counter Register */ +/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */ +#define UART_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (UART_RNPR) Receive Next Pointer */ +/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */ +#define UART_RNCR_RXNCTR (0xffff << 0) /**< \brief (UART_RNCR) Receive Next Counter */ +/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */ +#define UART_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (UART_TNPR) Transmit Next Pointer */ +/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */ +#define UART_TNCR_TXNCTR (0xffff << 0) /**< \brief (UART_TNCR) Transmit Counter Next */ +/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */ +#define UART_PTCR_RXTEN (0x1 << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */ +#define UART_PTCR_RXTDIS (0x1 << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */ +#define UART_PTCR_TXTEN (0x1 << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */ +#define UART_PTCR_TXTDIS (0x1 << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */ +/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */ +#define UART_PTSR_RXTEN (0x1 << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */ +#define UART_PTSR_TXTEN (0x1 << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR USB Device Port */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_UDP USB Device Port */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Udp hardware registers */ +typedef struct { + RoReg UDP_FRM_NUM; /**< \brief (Udp Offset: 0x000) Frame Number Register */ + RwReg UDP_GLB_STAT; /**< \brief (Udp Offset: 0x004) Global State Register */ + RwReg UDP_FADDR; /**< \brief (Udp Offset: 0x008) Function Address Register */ + RwReg Reserved1[1]; + WoReg UDP_IER; /**< \brief (Udp Offset: 0x010) Interrupt Enable Register */ + WoReg UDP_IDR; /**< \brief (Udp Offset: 0x014) Interrupt Disable Register */ + RoReg UDP_IMR; /**< \brief (Udp Offset: 0x018) Interrupt Mask Register */ + RoReg UDP_ISR; /**< \brief (Udp Offset: 0x01C) Interrupt Status Register */ + WoReg UDP_ICR; /**< \brief (Udp Offset: 0x020) Interrupt Clear Register */ + RwReg Reserved2[1]; + RwReg UDP_RST_EP; /**< \brief (Udp Offset: 0x028) Reset Endpoint Register */ + RwReg Reserved3[1]; + RwReg UDP_CSR[8]; /**< \brief (Udp Offset: 0x30) Endpoint Control and Status Register (ept_num = 0) */ + RwReg UDP_FDR[8]; /**< \brief (Udp Offset: 0x50) Endpoint FIFO Data Register (ept_num = 0) */ + RwReg Reserved4[1]; + RwReg UDP_TXVC; /**< \brief (Udp Offset: 0x074) Transceiver Control Register */ +} Udp; +#endif /* __ASSEMBLY__ */ +/* -------- UDP_FRM_NUM : (UDP Offset: 0x000) Frame Number Register -------- */ +#define UDP_FRM_NUM_FRM_NUM (0x7ff << 0) /**< \brief (UDP_FRM_NUM) Frame Number as Defined in the Packet Field Formats */ +#define UDP_FRM_NUM_FRM_ERR (0x1 << 16) /**< \brief (UDP_FRM_NUM) Frame Error */ +#define UDP_FRM_NUM_FRM_OK (0x1 << 17) /**< \brief (UDP_FRM_NUM) Frame OK */ +/* -------- UDP_GLB_STAT : (UDP Offset: 0x004) Global State Register -------- */ +#define UDP_GLB_STAT_FADDEN (0x1 << 0) /**< \brief (UDP_GLB_STAT) Function Address Enable */ +#define UDP_GLB_STAT_CONFG (0x1 << 1) /**< \brief (UDP_GLB_STAT) Configured */ +#define UDP_GLB_STAT_ESR (0x1 << 2) /**< \brief (UDP_GLB_STAT) Enable Send Resume */ +#define UDP_GLB_STAT_RSMINPR (0x1 << 3) /**< \brief (UDP_GLB_STAT) */ +#define UDP_GLB_STAT_RMWUPE (0x1 << 4) /**< \brief (UDP_GLB_STAT) Remote Wake Up Enable */ +/* -------- UDP_FADDR : (UDP Offset: 0x008) Function Address Register -------- */ +#define UDP_FADDR_FADD (0x7f << 0) /**< \brief (UDP_FADDR) Function Address Value */ +#define UDP_FADDR_FEN (0x1 << 8) /**< \brief (UDP_FADDR) Function Enable */ +/* -------- UDP_IER : (UDP Offset: 0x010) Interrupt Enable Register -------- */ +#define UDP_IER_EP0INT (0x1 << 0) /**< \brief (UDP_IER) Enable Endpoint 0 Interrupt */ +#define UDP_IER_EP1INT (0x1 << 1) /**< \brief (UDP_IER) Enable Endpoint 1 Interrupt */ +#define UDP_IER_EP2INT (0x1 << 2) /**< \brief (UDP_IER) Enable Endpoint 2Interrupt */ +#define UDP_IER_EP3INT (0x1 << 3) /**< \brief (UDP_IER) Enable Endpoint 3 Interrupt */ +#define UDP_IER_EP4INT (0x1 << 4) /**< \brief (UDP_IER) Enable Endpoint 4 Interrupt */ +#define UDP_IER_EP5INT (0x1 << 5) /**< \brief (UDP_IER) Enable Endpoint 5 Interrupt */ +#define UDP_IER_EP6INT (0x1 << 6) /**< \brief (UDP_IER) Enable Endpoint 6 Interrupt */ +#define UDP_IER_EP7INT (0x1 << 7) /**< \brief (UDP_IER) Enable Endpoint 7 Interrupt */ +#define UDP_IER_RXSUSP (0x1 << 8) /**< \brief (UDP_IER) Enable UDP Suspend Interrupt */ +#define UDP_IER_RXRSM (0x1 << 9) /**< \brief (UDP_IER) Enable UDP Resume Interrupt */ +#define UDP_IER_EXTRSM (0x1 << 10) /**< \brief (UDP_IER) */ +#define UDP_IER_SOFINT (0x1 << 11) /**< \brief (UDP_IER) Enable Start Of Frame Interrupt */ +#define UDP_IER_WAKEUP (0x1 << 13) /**< \brief (UDP_IER) Enable UDP bus Wakeup Interrupt */ +/* -------- UDP_IDR : (UDP Offset: 0x014) Interrupt Disable Register -------- */ +#define UDP_IDR_EP0INT (0x1 << 0) /**< \brief (UDP_IDR) Disable Endpoint 0 Interrupt */ +#define UDP_IDR_EP1INT (0x1 << 1) /**< \brief (UDP_IDR) Disable Endpoint 1 Interrupt */ +#define UDP_IDR_EP2INT (0x1 << 2) /**< \brief (UDP_IDR) Disable Endpoint 2 Interrupt */ +#define UDP_IDR_EP3INT (0x1 << 3) /**< \brief (UDP_IDR) Disable Endpoint 3 Interrupt */ +#define UDP_IDR_EP4INT (0x1 << 4) /**< \brief (UDP_IDR) Disable Endpoint 4 Interrupt */ +#define UDP_IDR_EP5INT (0x1 << 5) /**< \brief (UDP_IDR) Disable Endpoint 5 Interrupt */ +#define UDP_IDR_EP6INT (0x1 << 6) /**< \brief (UDP_IDR) Disable Endpoint 6 Interrupt */ +#define UDP_IDR_EP7INT (0x1 << 7) /**< \brief (UDP_IDR) Disable Endpoint 7 Interrupt */ +#define UDP_IDR_RXSUSP (0x1 << 8) /**< \brief (UDP_IDR) Disable UDP Suspend Interrupt */ +#define UDP_IDR_RXRSM (0x1 << 9) /**< \brief (UDP_IDR) Disable UDP Resume Interrupt */ +#define UDP_IDR_EXTRSM (0x1 << 10) /**< \brief (UDP_IDR) */ +#define UDP_IDR_SOFINT (0x1 << 11) /**< \brief (UDP_IDR) Disable Start Of Frame Interrupt */ +#define UDP_IDR_WAKEUP (0x1 << 13) /**< \brief (UDP_IDR) Disable USB Bus Interrupt */ +/* -------- UDP_IMR : (UDP Offset: 0x018) Interrupt Mask Register -------- */ +#define UDP_IMR_EP0INT (0x1 << 0) /**< \brief (UDP_IMR) Mask Endpoint 0 Interrupt */ +#define UDP_IMR_EP1INT (0x1 << 1) /**< \brief (UDP_IMR) Mask Endpoint 1 Interrupt */ +#define UDP_IMR_EP2INT (0x1 << 2) /**< \brief (UDP_IMR) Mask Endpoint 2 Interrupt */ +#define UDP_IMR_EP3INT (0x1 << 3) /**< \brief (UDP_IMR) Mask Endpoint 3 Interrupt */ +#define UDP_IMR_EP4INT (0x1 << 4) /**< \brief (UDP_IMR) Mask Endpoint 4 Interrupt */ +#define UDP_IMR_EP5INT (0x1 << 5) /**< \brief (UDP_IMR) Mask Endpoint 5 Interrupt */ +#define UDP_IMR_EP6INT (0x1 << 6) /**< \brief (UDP_IMR) Mask Endpoint 6 Interrupt */ +#define UDP_IMR_EP7INT (0x1 << 7) /**< \brief (UDP_IMR) Mask Endpoint 7 Interrupt */ +#define UDP_IMR_RXSUSP (0x1 << 8) /**< \brief (UDP_IMR) Mask UDP Suspend Interrupt */ +#define UDP_IMR_RXRSM (0x1 << 9) /**< \brief (UDP_IMR) Mask UDP Resume Interrupt. */ +#define UDP_IMR_EXTRSM (0x1 << 10) /**< \brief (UDP_IMR) */ +#define UDP_IMR_SOFINT (0x1 << 11) /**< \brief (UDP_IMR) Mask Start Of Frame Interrupt */ +#define UDP_IMR_BIT12 (0x1 << 12) /**< \brief (UDP_IMR) UDP_IMR Bit 12 */ +#define UDP_IMR_WAKEUP (0x1 << 13) /**< \brief (UDP_IMR) USB Bus WAKEUP Interrupt */ +/* -------- UDP_ISR : (UDP Offset: 0x01C) Interrupt Status Register -------- */ +#define UDP_ISR_EP0INT (0x1 << 0) /**< \brief (UDP_ISR) Endpoint 0 Interrupt Status */ +#define UDP_ISR_EP1INT (0x1 << 1) /**< \brief (UDP_ISR) Endpoint 1 Interrupt Status */ +#define UDP_ISR_EP2INT (0x1 << 2) /**< \brief (UDP_ISR) Endpoint 2 Interrupt Status */ +#define UDP_ISR_EP3INT (0x1 << 3) /**< \brief (UDP_ISR) Endpoint 3 Interrupt Status */ +#define UDP_ISR_EP4INT (0x1 << 4) /**< \brief (UDP_ISR) Endpoint 4 Interrupt Status */ +#define UDP_ISR_EP5INT (0x1 << 5) /**< \brief (UDP_ISR) Endpoint 5 Interrupt Status */ +#define UDP_ISR_EP6INT (0x1 << 6) /**< \brief (UDP_ISR) Endpoint 6 Interrupt Status */ +#define UDP_ISR_EP7INT (0x1 << 7) /**< \brief (UDP_ISR) Endpoint 7Interrupt Status */ +#define UDP_ISR_RXSUSP (0x1 << 8) /**< \brief (UDP_ISR) UDP Suspend Interrupt Status */ +#define UDP_ISR_RXRSM (0x1 << 9) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */ +#define UDP_ISR_EXTRSM (0x1 << 10) /**< \brief (UDP_ISR) */ +#define UDP_ISR_SOFINT (0x1 << 11) /**< \brief (UDP_ISR) Start of Frame Interrupt Status */ +#define UDP_ISR_ENDBUSRES (0x1 << 12) /**< \brief (UDP_ISR) End of BUS Reset Interrupt Status */ +#define UDP_ISR_WAKEUP (0x1 << 13) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */ +/* -------- UDP_ICR : (UDP Offset: 0x020) Interrupt Clear Register -------- */ +#define UDP_ICR_RXSUSP (0x1 << 8) /**< \brief (UDP_ICR) Clear UDP Suspend Interrupt */ +#define UDP_ICR_RXRSM (0x1 << 9) /**< \brief (UDP_ICR) Clear UDP Resume Interrupt */ +#define UDP_ICR_EXTRSM (0x1 << 10) /**< \brief (UDP_ICR) */ +#define UDP_ICR_SOFINT (0x1 << 11) /**< \brief (UDP_ICR) Clear Start Of Frame Interrupt */ +#define UDP_ICR_ENDBUSRES (0x1 << 12) /**< \brief (UDP_ICR) Clear End of Bus Reset Interrupt */ +#define UDP_ICR_WAKEUP (0x1 << 13) /**< \brief (UDP_ICR) Clear Wakeup Interrupt */ +/* -------- UDP_RST_EP : (UDP Offset: 0x028) Reset Endpoint Register -------- */ +#define UDP_RST_EP_EP0 (0x1 << 0) /**< \brief (UDP_RST_EP) Reset Endpoint 0 */ +#define UDP_RST_EP_EP1 (0x1 << 1) /**< \brief (UDP_RST_EP) Reset Endpoint 1 */ +#define UDP_RST_EP_EP2 (0x1 << 2) /**< \brief (UDP_RST_EP) Reset Endpoint 2 */ +#define UDP_RST_EP_EP3 (0x1 << 3) /**< \brief (UDP_RST_EP) Reset Endpoint 3 */ +#define UDP_RST_EP_EP4 (0x1 << 4) /**< \brief (UDP_RST_EP) Reset Endpoint 4 */ +#define UDP_RST_EP_EP5 (0x1 << 5) /**< \brief (UDP_RST_EP) Reset Endpoint 5 */ +#define UDP_RST_EP_EP6 (0x1 << 6) /**< \brief (UDP_RST_EP) Reset Endpoint 6 */ +#define UDP_RST_EP_EP7 (0x1 << 7) /**< \brief (UDP_RST_EP) Reset Endpoint 7 */ +/* -------- UDP_CSR[8] : (UDP Offset: 0x2C) Endpoint Control and Status Register (ept_num = 0) -------- */ +#define UDP_CSR_TXCOMP (0x1 << 0) /**< \brief (UDP_CSR[8]) Generates an IN Packet with Data Previously Written in the DPR */ +#define UDP_CSR_RX_DATA_BK0 (0x1 << 1) /**< \brief (UDP_CSR[8]) Receive Data Bank 0 */ +#define UDP_CSR_RXSETUP (0x1 << 2) /**< \brief (UDP_CSR[8]) Received Setup */ +#define UDP_CSR_STALLSENTISOERROR (0x1 << 3) /**< \brief (UDP_CSR[8]) */ +#define UDP_CSR_TXPKTRDY (0x1 << 4) /**< \brief (UDP_CSR[8]) Transmit Packet Ready */ +#define UDP_CSR_FORCESTALL (0x1 << 5) /**< \brief (UDP_CSR[8]) Force Stall (used by Control, Bulk and Isochronous Endpoints) */ +#define UDP_CSR_RX_DATA_BK1 (0x1 << 6) /**< \brief (UDP_CSR[8]) Receive Data Bank 1 (only used by endpoints with ping-pong attributes) */ +#define UDP_CSR_DIR (0x1 << 7) /**< \brief (UDP_CSR[8]) Transfer Direction (only available for control endpoints) */ +#define UDP_CSR_EPTYPE (0x7 << 8) /**< \brief (UDP_CSR[8]) Endpoint Type */ +#define UDP_CSR_EPTYPE_CTRL (0x0 << 8) /**< \brief (UDP_CSR[8]) Control */ +#define UDP_CSR_EPTYPE_ISO_OUT (0x1 << 8) /**< \brief (UDP_CSR[8]) Isochronous OUT */ +#define UDP_CSR_EPTYPE_BULK_OUT (0x2 << 8) /**< \brief (UDP_CSR[8]) Bulk OUT */ +#define UDP_CSR_EPTYPE_INT_OUT (0x3 << 8) /**< \brief (UDP_CSR[8]) Interrupt OUT */ +#define UDP_CSR_EPTYPE_ISO_IN (0x5 << 8) /**< \brief (UDP_CSR[8]) Isochronous IN */ +#define UDP_CSR_EPTYPE_BULK_IN (0x6 << 8) /**< \brief (UDP_CSR[8]) Bulk IN */ +#define UDP_CSR_EPTYPE_INT_IN (0x7 << 8) /**< \brief (UDP_CSR[8]) Interrupt IN */ +#define UDP_CSR_DTGLE (0x1 << 11) /**< \brief (UDP_CSR[8]) Data Toggle */ +#define UDP_CSR_EPEDS (0x1 << 15) /**< \brief (UDP_CSR[8]) Endpoint Enable Disable */ +#define UDP_CSR_RXBYTECNT (0x7ff << 16) /**< \brief (UDP_CSR[8]) Number of Bytes Available in the FIFO */ +/* -------- UDP_FDR[8] : (UDP Offset: 0x4C) Endpoint FIFO Data Register (ept_num = 0) -------- */ +#define UDP_FDR_FIFO_DATA (0xff << 0) /**< \brief (UDP_FDR[8]) FIFO Data Value */ +/* -------- UDP_TXVC : (UDP Offset: 0x074) Transceiver Control Register -------- */ +#define UDP_TXVC_TXVDIS (0x1 << 8) /**< \brief (UDP_TXVC) Transceiver Disable */ +#define UDP_TXVC_PUON (0x1 << 9) /**< \brief (UDP_TXVC) Pullup On */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_USART Universal Synchronous Asynchronous Receiver Transmitter */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Usart hardware registers */ +typedef struct { + WoReg US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */ + RwReg US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */ + WoReg US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */ + WoReg US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */ + RoReg US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */ + RoReg US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */ + RoReg US_RHR; /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */ + WoReg US_THR; /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */ + RwReg US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */ + RwReg US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */ + RwReg US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */ + RwReg Reserved1[5]; + RwReg US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */ + RoReg US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */ + RwReg Reserved2[1]; + RwReg US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */ + RwReg US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */ + RwReg Reserved3[36]; + RwReg US_WPMR; /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */ + RoReg US_WPSR; /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */ + RwReg Reserved4[4]; + RoReg US_VERSION; /**< \brief (Usart Offset: 0xFC) Version Register */ + RwReg US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */ + RwReg US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */ + RwReg US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */ + RwReg US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */ + RwReg US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */ + RwReg US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */ + RwReg US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */ + RwReg US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */ + WoReg US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */ + RoReg US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */ +} Usart; +#endif /* __ASSEMBLY__ */ +/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */ +#define US_CR_RSTRX (0x1 << 2) /**< \brief (US_CR) Reset Receiver */ +#define US_CR_RSTTX (0x1 << 3) /**< \brief (US_CR) Reset Transmitter */ +#define US_CR_RXEN (0x1 << 4) /**< \brief (US_CR) Receiver Enable */ +#define US_CR_RXDIS (0x1 << 5) /**< \brief (US_CR) Receiver Disable */ +#define US_CR_TXEN (0x1 << 6) /**< \brief (US_CR) Transmitter Enable */ +#define US_CR_TXDIS (0x1 << 7) /**< \brief (US_CR) Transmitter Disable */ +#define US_CR_RSTSTA (0x1 << 8) /**< \brief (US_CR) Reset Status Bits */ +#define US_CR_STTBRK (0x1 << 9) /**< \brief (US_CR) Start Break */ +#define US_CR_STPBRK (0x1 << 10) /**< \brief (US_CR) Stop Break */ +#define US_CR_STTTO (0x1 << 11) /**< \brief (US_CR) Start Time-out */ +#define US_CR_SENDA (0x1 << 12) /**< \brief (US_CR) Send Address */ +#define US_CR_RSTIT (0x1 << 13) /**< \brief (US_CR) Reset Iterations */ +#define US_CR_RSTNACK (0x1 << 14) /**< \brief (US_CR) Reset Non Acknowledge */ +#define US_CR_RETTO (0x1 << 15) /**< \brief (US_CR) Rearm Time-out */ +#define US_CR_DTREN (0x1 << 16) /**< \brief (US_CR) Data Terminal Ready Enable */ +#define US_CR_DTRDIS (0x1 << 17) /**< \brief (US_CR) Data Terminal Ready Disable */ +#define US_CR_RTSEN__FCS (0x1 << 18) /**< \brief (US_CR) Request to Send Enable/Force SPI Chip Select */ +#define US_CR_RTSDIS__RCS (0x1 << 19) /**< \brief (US_CR) Request to Send Disable/Release SPI Chip Select */ +/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */ +#define US_MR_USART_MODE (0xf << 0) /**< \brief (US_MR) */ +#define US_MR_USART_MODE_NORMAL (0x0) /**< (USART) Normal*/ +#define US_MR_USART_MODE_RS485 (0x1) /**< (USART) RS485*/ +#define US_MR_USART_MODE_HWHSH (0x2) /**< (USART) Hardware Handshaking*/ +#define US_MR_USART_MODE_ISO7816_0 (0x4) /**< (USART) ISO7816 protocol: T = 0*/ +#define US_MR_USART_MODE_ISO7816_1 (0x6) /**< (USART) ISO7816 protocol: T = 1*/ +#define US_MR_USART_MODE_IRDA (0x8) /**< (USART) IrDA*/ +#define US_MR_USART_MODE_SPIM (0xE) /**< (USART) SPI Master*/ +#define US_MR_USART_MODE_SPIS (0xF) /**< (USART) SPI Slave*/ +#define US_MR_USCLKS (0x3 << 4) /**< \brief (US_MR) Clock Selection */ +#define US_MR_USCLKS_CLOCK (0x0 << 4) /**< (USART) MCK*/ +#define US_MR_USCLKS_FDIV1 (0x1 << 4) /**< (USART) MCK/DIV(DIV=8)*/ +#define US_MR_USCLKS_SLOW (0x2 << 4) /**< (USART) Reserved*/ +#define US_MR_USCLKS_EXT (0x3 << 4) /**< (USART) SCK*/ +#define US_MR_CHRL (0x3 << 6) /**< \brief (US_MR) Character Length. */ +#define US_MR_CHRL_5_BITS (0x0 << 6) /**< (USART) Character Length: 5 bits*/ +#define US_MR_CHRL_6_BITS (0x1 << 6) /**< (USART) Character Length: 6 bits*/ +#define US_MR_CHRL_7_BITS (0x2 << 6) /**< (USART) Character Length: 7 bits*/ +#define US_MR_CHRL_8_BITS (0x3 << 6) /**< (USART) Character Length: 8 bits*/ +#define US_MR_SYNC__CPHA (0x1 << 8) /**< \brief (US_MR) Synchronous Mode Select or SPI Clock Phase */ +#define US_MR_PAR (0x7 << 9) /**< \brief (US_MR) Parity Type */ +#define US_MR_PAR_EVEN (0x0 << 9) /**< (USART) Even Parity*/ +#define US_MR_PAR_ODD (0x1 << 9) /**< (USART) Odd Parity*/ +#define US_MR_PAR_SPACE (0x2 << 9) /**< (USART) Parity forced to 0 (Space)*/ +#define US_MR_PAR_MARK (0x3 << 9) /**< (USART) Parity forced to 1 (Mark)*/ +#define US_MR_PAR_NONE (0x4 << 9) /**< (USART) No Parity*/ +#define US_MR_PAR_MULTI_DROP (0x6 << 9) /**< (USART) Multi-drop mode*/ +#define US_MR_NBSTOP (0x3 << 12) /**< \brief (US_MR) Number of Stop Bits */ +#define US_MR_NBSTOP_1_BIT (0x0 << 12) /**< (USART) 1 stop bit*/ +#define US_MR_NBSTOP_15_BIT (0x1 << 12) /**< (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits*/ +#define US_MR_NBSTOP_2_BIT (0x2 << 12) /**< (USART) 2 stop bits*/ +#define US_MR_CHMODE (0x3 << 14) /**< \brief (US_MR) Channel Mode */ +#define US_MR_CHMODE_NORMAL (0x0 << 14) /**< (USART) Normal Mode: The USART channel operates as an RX/TX USART.*/ +#define US_MR_CHMODE_AUTO (0x1 << 14) /**< (USART) Automatic Echo: Receiver Data Input is connected to the TXD pin.*/ +#define US_MR_CHMODE_LOCAL (0x2 << 14) /**< (USART) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.*/ +#define US_MR_CHMODE_REMOTE (0x3 << 14) /**< (USART) Remote Loopback: RXD pin is internally connected to TXD pin.*/ +#define US_MR_MSBF__CPOL (0x1 << 16) /**< \brief (US_MR) Bit Order or SPI Clock Polarity */ +#define US_MR_MODE9 (0x1 << 17) /**< \brief (US_MR) 9-bit Character Length */ +#define US_MR_CLKO (0x1 << 18) /**< \brief (US_MR) Clock Output Select */ +#define US_MR_OVER (0x1 << 19) /**< \brief (US_MR) Oversampling Mode */ +#define US_MR_INACK (0x1 << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */ +#define US_MR_DSNACK (0x1 << 21) /**< \brief (US_MR) Disable Successive NACK */ +#define US_MR_VAR_SYNC (0x1 << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */ +#define US_MR_INVDATA (0x1 << 23) /**< \brief (US_MR) INverted Data */ +#define US_MR_MAX_ITERATION (0x7 << 24) /**< \brief (US_MR) */ +#define US_MR_FILTER (0x1 << 28) /**< \brief (US_MR) Infrared Receive Line Filter */ +#define US_MR_MAN (0x1 << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */ +#define US_MR_MODSYNC_ (0x1 << 30) /**< \brief (US_MR) */ +#define US_MR_ONEBIT (0x1 << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */ +/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */ +#define US_IER_RXRDY (0x1 << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */ +#define US_IER_TXRDY (0x1 << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */ +#define US_IER_RXBRK (0x1 << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */ +#define US_IER_ENDRX (0x1 << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */ +#define US_IER_ENDTX (0x1 << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */ +#define US_IER_OVRE (0x1 << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */ +#define US_IER_FRAME (0x1 << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */ +#define US_IER_PARE (0x1 << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */ +#define US_IER_TIMEOUT (0x1 << 8) /**< \brief (US_IER) Time-out Interrupt Enable */ +#define US_IER_TXEMPTY (0x1 << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */ +#define US_IER_ITER__UNRE (0x1 << 10) /**< \brief (US_IER) Iteration or SPI Underrun Error Interrupt Enable */ +#define US_IER_TXBUFE (0x1 << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */ +#define US_IER_RXBUFF (0x1 << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */ +#define US_IER_NACK (0x1 << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */ +#define US_IER_RIIC (0x1 << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */ +#define US_IER_DSRIC (0x1 << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */ +#define US_IER_DCDIC (0x1 << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */ +#define US_IER_CTSIC (0x1 << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */ +#define US_IER_MANE (0x1 << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */ +/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */ +#define US_IDR_RXRDY (0x1 << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */ +#define US_IDR_TXRDY (0x1 << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */ +#define US_IDR_RXBRK (0x1 << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */ +#define US_IDR_ENDRX (0x1 << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */ +#define US_IDR_ENDTX (0x1 << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */ +#define US_IDR_OVRE (0x1 << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */ +#define US_IDR_FRAME (0x1 << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */ +#define US_IDR_PARE (0x1 << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */ +#define US_IDR_TIMEOUT (0x1 << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */ +#define US_IDR_TXEMPTY (0x1 << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */ +#define US_IDR_ITER__UNRE (0x1 << 10) /**< \brief (US_IDR) Iteration or SPI Underrun Error Interrupt Enable */ +#define US_IDR_TXBUFE (0x1 << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */ +#define US_IDR_RXBUFF (0x1 << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */ +#define US_IDR_NACK (0x1 << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */ +#define US_IDR_RIIC (0x1 << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */ +#define US_IDR_DSRIC (0x1 << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */ +#define US_IDR_DCDIC (0x1 << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */ +#define US_IDR_CTSIC (0x1 << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */ +#define US_IDR_MANE (0x1 << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */ +/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */ +#define US_IMR_RXRDY (0x1 << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */ +#define US_IMR_TXRDY (0x1 << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */ +#define US_IMR_RXBRK (0x1 << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */ +#define US_IMR_ENDRX (0x1 << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */ +#define US_IMR_ENDTX (0x1 << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */ +#define US_IMR_OVRE (0x1 << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */ +#define US_IMR_FRAME (0x1 << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */ +#define US_IMR_PARE (0x1 << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */ +#define US_IMR_TIMEOUT (0x1 << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */ +#define US_IMR_TXEMPTY (0x1 << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */ +#define US_IMR_ITER__UNRE (0x1 << 10) /**< \brief (US_IMR) Iteration or SPI Underrun Error Interrupt Enable */ +#define US_IMR_TXBUFE (0x1 << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */ +#define US_IMR_RXBUFF (0x1 << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */ +#define US_IMR_NACK (0x1 << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */ +#define US_IMR_RIIC (0x1 << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */ +#define US_IMR_DSRIC (0x1 << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */ +#define US_IMR_DCDIC (0x1 << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */ +#define US_IMR_CTSIC (0x1 << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */ +#define US_IMR_MANE (0x1 << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */ +/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */ +#define US_CSR_RXRDY (0x1 << 0) /**< \brief (US_CSR) Receiver Ready */ +#define US_CSR_TXRDY (0x1 << 1) /**< \brief (US_CSR) Transmitter Ready */ +#define US_CSR_RXBRK (0x1 << 2) /**< \brief (US_CSR) Break Received/End of Break */ +#define US_CSR_ENDRX (0x1 << 3) /**< \brief (US_CSR) End of Receiver Transfer */ +#define US_CSR_ENDTX (0x1 << 4) /**< \brief (US_CSR) End of Transmitter Transfer */ +#define US_CSR_OVRE (0x1 << 5) /**< \brief (US_CSR) Overrun Error */ +#define US_CSR_FRAME (0x1 << 6) /**< \brief (US_CSR) Framing Error */ +#define US_CSR_PARE (0x1 << 7) /**< \brief (US_CSR) Parity Error */ +#define US_CSR_TIMEOUT (0x1 << 8) /**< \brief (US_CSR) Receiver Time-out */ +#define US_CSR_TXEMPTY (0x1 << 9) /**< \brief (US_CSR) Transmitter Empty */ +#define US_CSR_ITER__UNRE (0x1 << 10) /**< \brief (US_CSR) Max number of Repetitions Reached or SPI Underrun Error */ +#define US_CSR_TXBUFE (0x1 << 11) /**< \brief (US_CSR) Transmission Buffer Empty */ +#define US_CSR_RXBUFF (0x1 << 12) /**< \brief (US_CSR) Reception Buffer Full */ +#define US_CSR_NACK (0x1 << 13) /**< \brief (US_CSR) */ +#define US_CSR_RIIC (0x1 << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */ +#define US_CSR_DSRIC (0x1 << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */ +#define US_CSR_DCDIC (0x1 << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */ +#define US_CSR_CTSIC (0x1 << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */ +#define US_CSR_RI (0x1 << 20) /**< \brief (US_CSR) Image of RI Input */ +#define US_CSR_DSR (0x1 << 21) /**< \brief (US_CSR) Image of DSR Input */ +#define US_CSR_DCD (0x1 << 22) /**< \brief (US_CSR) Image of DCD Input */ +#define US_CSR_CTS (0x1 << 23) /**< \brief (US_CSR) Image of CTS Input */ +#define US_CSR_MANERR (0x1 << 24) /**< \brief (US_CSR) Manchester Error */ +/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */ +#define US_RHR_RXCHR (0x1ff << 0) /**< \brief (US_RHR) Received Character */ +#define US_RHR_RXSYNH (0x1 << 15) /**< \brief (US_RHR) Received Sync */ +/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */ +#define US_THR_TXCHR (0x1ff << 0) /**< \brief (US_THR) Character to be Transmitted */ +#define US_THR_TXSYNH (0x1 << 15) /**< \brief (US_THR) Sync Field to be transmitted */ +/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define US_BRGR_CD (0xffff << 0) /**< \brief (US_BRGR) Clock Divider */ +#define US_BRGR_FP (0x7 << 16) /**< \brief (US_BRGR) Fractional Part */ +/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */ +#define US_RTOR_TO (0xffff << 0) /**< \brief (US_RTOR) Time-out Value */ +/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */ +#define US_TTGR_TG (0xff << 0) /**< \brief (US_TTGR) Timeguard Value */ +/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */ +#define US_FIDI_FI_DI_RATIO (0x7ff << 0) /**< \brief (US_FIDI) FI Over DI Ratio Value */ +/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */ +#define US_NER_NB_ERRORS (0xff << 0) /**< \brief (US_NER) Number of Errors */ +/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */ +#define US_IF_IRDA_FILTER (0xff << 0) /**< \brief (US_IF) IrDA Filter */ +/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */ +#define US_MAN_TX_PL (0xf << 0) /**< \brief (US_MAN) Transmitter Preamble Length */ +#define US_MAN_TX_PP (0x3 << 8) /**< \brief (US_MAN) Transmitter Preamble Pattern */ +#define US_MAN_TX_MPOL (0x1 << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */ +#define US_MAN_RX_PL (0xf << 16) /**< \brief (US_MAN) Receiver Preamble Length */ +#define US_MAN_RX_PP (0x3 << 24) /**< \brief (US_MAN) Receiver Preamble Pattern detected */ +#define US_MAN_RX_MPOL (0x1 << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */ +#define US_MAN_STUCKTO1 (0x1 << 29) /**< \brief (US_MAN) */ +#define US_MAN_DRIFT (0x1 << 30) /**< \brief (US_MAN) Drift compensation */ +/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */ +#define US_WPMR_WPEN (0x1 << 0) /**< \brief (US_WPMR) Write Protect Enable */ +#define US_WPMR_WPKEY (0xffffff << 8) /**< \brief (US_WPMR) Write Protect KEY */ +/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */ +#define US_WPSR_WPVS (0x1 << 0) /**< \brief (US_WPSR) Write Protect Violation Status */ +#define US_WPSR_WPVSRC (0xffff << 8) /**< \brief (US_WPSR) Write Protect Violation Source */ +/* -------- US_VERSION : (USART Offset: 0xFC) Version Register -------- */ +#define US_VERSION_VERSION (0xfff << 0) /**< \brief (US_VERSION) */ +#define US_VERSION_MFN (0x7 << 16) /**< \brief (US_VERSION) */ +/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */ +#define US_RPR_RXPTR (0xffffffff << 0) /**< \brief (US_RPR) Receive Pointer Register */ +/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */ +#define US_RCR_RXCTR (0xffff << 0) /**< \brief (US_RCR) Receive Counter Register */ +/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */ +#define US_TPR_TXPTR (0xffffffff << 0) /**< \brief (US_TPR) Transmit Counter Register */ +/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */ +#define US_TCR_TXCTR (0xffff << 0) /**< \brief (US_TCR) Transmit Counter Register */ +/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */ +#define US_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (US_RNPR) Receive Next Pointer */ +/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */ +#define US_RNCR_RXNCTR (0xffff << 0) /**< \brief (US_RNCR) Receive Next Counter */ +/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */ +#define US_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (US_TNPR) Transmit Next Pointer */ +/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */ +#define US_TNCR_TXNCTR (0xffff << 0) /**< \brief (US_TNCR) Transmit Counter Next */ +/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */ +#define US_PTCR_RXTEN (0x1 << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */ +#define US_PTCR_RXTDIS (0x1 << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */ +#define US_PTCR_TXTEN (0x1 << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */ +#define US_PTCR_TXTDIS (0x1 << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */ +/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */ +#define US_PTSR_RXTEN (0x1 << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */ +#define US_PTSR_TXTEN (0x1 << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Watchdog Timer */ +/* ============================================================================= */ +/** \addtogroup AT91SAM3S_WDT Watchdog Timer */ +/*@{*/ + +#ifndef __ASSEMBLY__ +/** \brief Wdt hardware registers */ +typedef struct { + WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ + RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ + RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ +} Wdt; +#endif /* __ASSEMBLY__ */ +/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ +#define WDT_CR_WDRSTT (0x1 << 0) /**< \brief (WDT_CR) Watchdog Restart */ +#define WDT_CR_KEY (0xff << 24) /**< \brief (WDT_CR) Password */ +/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ +#define WDT_MR_WDV (0xfff << 0) /**< \brief (WDT_MR) Watchdog Counter Value */ +#define WDT_MR_WDFIEN (0x1 << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ +#define WDT_MR_WDRSTEN (0x1 << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ +#define WDT_MR_WDRPROC (0x1 << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */ +#define WDT_MR_WDDIS (0x1 << 15) /**< \brief (WDT_MR) Watchdog Disable */ +#define WDT_MR_WDD (0xfff << 16) /**< \brief (WDT_MR) Watchdog Delta Value */ +#define WDT_MR_WDDBGHLT (0x1 << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ +#define WDT_MR_WDIDLEHLT (0x1 << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ +/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ +#define WDT_SR_WDUNF (0x1 << 0) /**< \brief (WDT_SR) Watchdog Underflow */ +#define WDT_SR_WDERR (0x1 << 1) /**< \brief (WDT_SR) Watchdog Error */ + +/*@}*/ + +/*@}*/ + +/* ***************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR AT91SAM3S */ +/* ***************************************************************************** */ +/** \addtogroup AT91SAM3S_reg Registers Access Definitions */ +/*@{*/ + +/* ========== Register definition for HSMCI peripheral ========== */ +#define REG_HSMCI_CR REG_ACCESS(WoReg, 0x40000000U) /**< \brief (HSMCI) Control Register */ +#define REG_HSMCI_MR REG_ACCESS(RwReg, 0x40000004U) /**< \brief (HSMCI) Mode Register */ +#define REG_HSMCI_DTOR REG_ACCESS(RwReg, 0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ +#define REG_HSMCI_SDCR REG_ACCESS(RwReg, 0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ +#define REG_HSMCI_ARGR REG_ACCESS(RwReg, 0x40000010U) /**< \brief (HSMCI) Argument Register */ +#define REG_HSMCI_CMDR REG_ACCESS(WoReg, 0x40000014U) /**< \brief (HSMCI) Command Register */ +#define REG_HSMCI_BLKR REG_ACCESS(RwReg, 0x40000018U) /**< \brief (HSMCI) Block Register */ +#define REG_HSMCI_CSTOR REG_ACCESS(RwReg, 0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ +#define REG_HSMCI_RSPR REG_ACCESS(RoReg, 0x40000020U) /**< \brief (HSMCI) Response Register */ +#define REG_HSMCI_RDR REG_ACCESS(RoReg, 0x40000030U) /**< \brief (HSMCI) Receive Data Register */ +#define REG_HSMCI_TDR REG_ACCESS(WoReg, 0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ +#define REG_HSMCI_SR REG_ACCESS(RoReg, 0x40000040U) /**< \brief (HSMCI) Status Register */ +#define REG_HSMCI_IER REG_ACCESS(WoReg, 0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ +#define REG_HSMCI_IDR REG_ACCESS(WoReg, 0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ +#define REG_HSMCI_IMR REG_ACCESS(RoReg, 0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ +#define REG_HSMCI_CFG REG_ACCESS(RwReg, 0x40000054U) /**< \brief (HSMCI) Configuration Register */ +#define REG_HSMCI_WPMR REG_ACCESS(RwReg, 0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ +#define REG_HSMCI_WPSR REG_ACCESS(RoReg, 0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ +#define REG_HSMCI_RPR REG_ACCESS(RwReg, 0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */ +#define REG_HSMCI_RCR REG_ACCESS(RwReg, 0x40000104U) /**< \brief (HSMCI) Receive Counter Register */ +#define REG_HSMCI_TPR REG_ACCESS(RwReg, 0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */ +#define REG_HSMCI_TCR REG_ACCESS(RwReg, 0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */ +#define REG_HSMCI_RNPR REG_ACCESS(RwReg, 0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */ +#define REG_HSMCI_RNCR REG_ACCESS(RwReg, 0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */ +#define REG_HSMCI_TNPR REG_ACCESS(RwReg, 0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */ +#define REG_HSMCI_TNCR REG_ACCESS(RwReg, 0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */ +#define REG_HSMCI_PTCR REG_ACCESS(WoReg, 0x40000120U) /**< \brief (HSMCI) Transfer Control Register */ +#define REG_HSMCI_PTSR REG_ACCESS(RoReg, 0x40000124U) /**< \brief (HSMCI) Transfer Status Register */ +/* ========== Register definition for SSC peripheral ========== */ +#define REG_SSC_CR REG_ACCESS(WoReg, 0x40004000U) /**< \brief (SSC) Control Register */ +#define REG_SSC_CMR REG_ACCESS(RwReg, 0x40004004U) /**< \brief (SSC) Clock Mode Register */ +#define REG_SSC_RCMR REG_ACCESS(RwReg, 0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ +#define REG_SSC_RFMR REG_ACCESS(RwReg, 0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ +#define REG_SSC_TCMR REG_ACCESS(RwReg, 0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ +#define REG_SSC_TFMR REG_ACCESS(RwReg, 0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ +#define REG_SSC_RHR REG_ACCESS(RoReg, 0x40004020U) /**< \brief (SSC) Receive Holding Register */ +#define REG_SSC_THR REG_ACCESS(WoReg, 0x40004024U) /**< \brief (SSC) Transmit Holding Register */ +#define REG_SSC_RSHR REG_ACCESS(RoReg, 0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ +#define REG_SSC_TSHR REG_ACCESS(RwReg, 0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ +#define REG_SSC_RC0R REG_ACCESS(RwReg, 0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ +#define REG_SSC_RC1R REG_ACCESS(RwReg, 0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ +#define REG_SSC_SR REG_ACCESS(RoReg, 0x40004040U) /**< \brief (SSC) Status Register */ +#define REG_SSC_IER REG_ACCESS(WoReg, 0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ +#define REG_SSC_IDR REG_ACCESS(WoReg, 0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ +#define REG_SSC_IMR REG_ACCESS(RoReg, 0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ +#define REG_SSC_WPMR REG_ACCESS(RwReg, 0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */ +#define REG_SSC_WPSR REG_ACCESS(RoReg, 0x400040E8U) /**< \brief (SSC) Write Protect Status Register */ +#define REG_SSC_RPR REG_ACCESS(RwReg, 0x40004100U) /**< \brief (SSC) Receive Pointer Register */ +#define REG_SSC_RCR REG_ACCESS(RwReg, 0x40004104U) /**< \brief (SSC) Receive Counter Register */ +#define REG_SSC_TPR REG_ACCESS(RwReg, 0x40004108U) /**< \brief (SSC) Transmit Pointer Register */ +#define REG_SSC_TCR REG_ACCESS(RwReg, 0x4000410CU) /**< \brief (SSC) Transmit Counter Register */ +#define REG_SSC_RNPR REG_ACCESS(RwReg, 0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */ +#define REG_SSC_RNCR REG_ACCESS(RwReg, 0x40004114U) /**< \brief (SSC) Receive Next Counter Register */ +#define REG_SSC_TNPR REG_ACCESS(RwReg, 0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */ +#define REG_SSC_TNCR REG_ACCESS(RwReg, 0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */ +#define REG_SSC_PTCR REG_ACCESS(WoReg, 0x40004120U) /**< \brief (SSC) Transfer Control Register */ +#define REG_SSC_PTSR REG_ACCESS(RoReg, 0x40004124U) /**< \brief (SSC) Transfer Status Register */ +/* ========== Register definition for SPI peripheral ========== */ +#define REG_SPI_CR REG_ACCESS(WoReg, 0x40008000U) /**< \brief (SPI) Control Register */ +#define REG_SPI_MR REG_ACCESS(RwReg, 0x40008004U) /**< \brief (SPI) Mode Register */ +#define REG_SPI_RDR REG_ACCESS(RoReg, 0x40008008U) /**< \brief (SPI) Receive Data Register */ +#define REG_SPI_TDR REG_ACCESS(WoReg, 0x4000800CU) /**< \brief (SPI) Transmit Data Register */ +#define REG_SPI_SR REG_ACCESS(RoReg, 0x40008010U) /**< \brief (SPI) Status Register */ +#define REG_SPI_IER REG_ACCESS(WoReg, 0x40008014U) /**< \brief (SPI) Interrupt Enable Register */ +#define REG_SPI_IDR REG_ACCESS(WoReg, 0x40008018U) /**< \brief (SPI) Interrupt Disable Register */ +#define REG_SPI_IMR REG_ACCESS(RoReg, 0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */ +#define REG_SPI_CSR REG_ACCESS(RwReg, 0x40008030U) /**< \brief (SPI) Chip Select Register */ +#define REG_SPI_WPMR REG_ACCESS(RwReg, 0x400080E4U) /**< \brief (SPI) Write Protection Control Register */ +#define REG_SPI_WPSR REG_ACCESS(RoReg, 0x400080E8U) /**< \brief (SPI) Write Protection Status Register */ +#define REG_SPI_RPR REG_ACCESS(RwReg, 0x40008100U) /**< \brief (SPI) Receive Pointer Register */ +#define REG_SPI_RCR REG_ACCESS(RwReg, 0x40008104U) /**< \brief (SPI) Receive Counter Register */ +#define REG_SPI_TPR REG_ACCESS(RwReg, 0x40008108U) /**< \brief (SPI) Transmit Pointer Register */ +#define REG_SPI_TCR REG_ACCESS(RwReg, 0x4000810CU) /**< \brief (SPI) Transmit Counter Register */ +#define REG_SPI_RNPR REG_ACCESS(RwReg, 0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */ +#define REG_SPI_RNCR REG_ACCESS(RwReg, 0x40008114U) /**< \brief (SPI) Receive Next Counter Register */ +#define REG_SPI_TNPR REG_ACCESS(RwReg, 0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */ +#define REG_SPI_TNCR REG_ACCESS(RwReg, 0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */ +#define REG_SPI_PTCR REG_ACCESS(WoReg, 0x40008120U) /**< \brief (SPI) Transfer Control Register */ +#define REG_SPI_PTSR REG_ACCESS(RoReg, 0x40008124U) /**< \brief (SPI) Transfer Status Register */ +/* ========== Register definition for TC0 peripheral ========== */ +#define REG_TC0_CCR0 REG_ACCESS(WoReg, 0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ +#define REG_TC0_CMR0 REG_ACCESS(RwReg, 0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ +#define REG_TC0_CV0 REG_ACCESS(RoReg, 0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */ +#define REG_TC0_RA0 REG_ACCESS(RwReg, 0x40010014U) /**< \brief (TC0) Register A (channel = 0) */ +#define REG_TC0_RB0 REG_ACCESS(RwReg, 0x40010018U) /**< \brief (TC0) Register B (channel = 0) */ +#define REG_TC0_RC0 REG_ACCESS(RwReg, 0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */ +#define REG_TC0_SR0 REG_ACCESS(RoReg, 0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */ +#define REG_TC0_IER0 REG_ACCESS(WoReg, 0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ +#define REG_TC0_IDR0 REG_ACCESS(WoReg, 0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ +#define REG_TC0_IMR0 REG_ACCESS(RoReg, 0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ +#define REG_TC0_CCR1 REG_ACCESS(WoReg, 0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ +#define REG_TC0_CMR1 REG_ACCESS(RwReg, 0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ +#define REG_TC0_CV1 REG_ACCESS(RoReg, 0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */ +#define REG_TC0_RA1 REG_ACCESS(RwReg, 0x40010054U) /**< \brief (TC0) Register A (channel = 1) */ +#define REG_TC0_RB1 REG_ACCESS(RwReg, 0x40010058U) /**< \brief (TC0) Register B (channel = 1) */ +#define REG_TC0_RC1 REG_ACCESS(RwReg, 0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */ +#define REG_TC0_SR1 REG_ACCESS(RoReg, 0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */ +#define REG_TC0_IER1 REG_ACCESS(WoReg, 0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ +#define REG_TC0_IDR1 REG_ACCESS(WoReg, 0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ +#define REG_TC0_IMR1 REG_ACCESS(RoReg, 0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ +#define REG_TC0_CCR2 REG_ACCESS(WoReg, 0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ +#define REG_TC0_CMR2 REG_ACCESS(RwReg, 0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ +#define REG_TC0_CV2 REG_ACCESS(RoReg, 0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */ +#define REG_TC0_RA2 REG_ACCESS(RwReg, 0x40010094U) /**< \brief (TC0) Register A (channel = 2) */ +#define REG_TC0_RB2 REG_ACCESS(RwReg, 0x40010098U) /**< \brief (TC0) Register B (channel = 2) */ +#define REG_TC0_RC2 REG_ACCESS(RwReg, 0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */ +#define REG_TC0_SR2 REG_ACCESS(RoReg, 0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */ +#define REG_TC0_IER2 REG_ACCESS(WoReg, 0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ +#define REG_TC0_IDR2 REG_ACCESS(WoReg, 0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ +#define REG_TC0_IMR2 REG_ACCESS(RoReg, 0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ +#define REG_TC0_BCR REG_ACCESS(WoReg, 0x400100C0U) /**< \brief (TC0) Block Control Register */ +#define REG_TC0_BMR REG_ACCESS(RwReg, 0x400100C4U) /**< \brief (TC0) Block Mode Register */ +#define REG_TC0_QIER REG_ACCESS(WoReg, 0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ +#define REG_TC0_QIDR REG_ACCESS(WoReg, 0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ +#define REG_TC0_QIMR REG_ACCESS(RoReg, 0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ +#define REG_TC0_QISR REG_ACCESS(RoReg, 0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ +#define REG_TC0_FMR REG_ACCESS(RwReg, 0x400100D8U) /**< \brief (TC0) Fault Mode Register */ +#define REG_TC0_WPMR REG_ACCESS(RwReg, 0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */ +#define REG_TC0_VER REG_ACCESS(RoReg, 0x400100FCU) /**< \brief (TC0) Version Register */ +/* ========== Register definition for TC1 peripheral ========== */ +#define REG_TC1_CCR0 REG_ACCESS(WoReg, 0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ +#define REG_TC1_CMR0 REG_ACCESS(RwReg, 0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ +#define REG_TC1_CV0 REG_ACCESS(RoReg, 0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */ +#define REG_TC1_RA0 REG_ACCESS(RwReg, 0x40014014U) /**< \brief (TC1) Register A (channel = 0) */ +#define REG_TC1_RB0 REG_ACCESS(RwReg, 0x40014018U) /**< \brief (TC1) Register B (channel = 0) */ +#define REG_TC1_RC0 REG_ACCESS(RwReg, 0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */ +#define REG_TC1_SR0 REG_ACCESS(RoReg, 0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */ +#define REG_TC1_IER0 REG_ACCESS(WoReg, 0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ +#define REG_TC1_IDR0 REG_ACCESS(WoReg, 0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ +#define REG_TC1_IMR0 REG_ACCESS(RoReg, 0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ +#define REG_TC1_CCR1 REG_ACCESS(WoReg, 0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ +#define REG_TC1_CMR1 REG_ACCESS(RwReg, 0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ +#define REG_TC1_CV1 REG_ACCESS(RoReg, 0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */ +#define REG_TC1_RA1 REG_ACCESS(RwReg, 0x40014054U) /**< \brief (TC1) Register A (channel = 1) */ +#define REG_TC1_RB1 REG_ACCESS(RwReg, 0x40014058U) /**< \brief (TC1) Register B (channel = 1) */ +#define REG_TC1_RC1 REG_ACCESS(RwReg, 0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */ +#define REG_TC1_SR1 REG_ACCESS(RoReg, 0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */ +#define REG_TC1_IER1 REG_ACCESS(WoReg, 0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ +#define REG_TC1_IDR1 REG_ACCESS(WoReg, 0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ +#define REG_TC1_IMR1 REG_ACCESS(RoReg, 0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ +#define REG_TC1_CCR2 REG_ACCESS(WoReg, 0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ +#define REG_TC1_CMR2 REG_ACCESS(RwReg, 0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ +#define REG_TC1_CV2 REG_ACCESS(RoReg, 0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */ +#define REG_TC1_RA2 REG_ACCESS(RwReg, 0x40014094U) /**< \brief (TC1) Register A (channel = 2) */ +#define REG_TC1_RB2 REG_ACCESS(RwReg, 0x40014098U) /**< \brief (TC1) Register B (channel = 2) */ +#define REG_TC1_RC2 REG_ACCESS(RwReg, 0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */ +#define REG_TC1_SR2 REG_ACCESS(RoReg, 0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */ +#define REG_TC1_IER2 REG_ACCESS(WoReg, 0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ +#define REG_TC1_IDR2 REG_ACCESS(WoReg, 0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ +#define REG_TC1_IMR2 REG_ACCESS(RoReg, 0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ +#define REG_TC1_BCR REG_ACCESS(WoReg, 0x400140C0U) /**< \brief (TC1) Block Control Register */ +#define REG_TC1_BMR REG_ACCESS(RwReg, 0x400140C4U) /**< \brief (TC1) Block Mode Register */ +#define REG_TC1_QIER REG_ACCESS(WoReg, 0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ +#define REG_TC1_QIDR REG_ACCESS(WoReg, 0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ +#define REG_TC1_QIMR REG_ACCESS(RoReg, 0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ +#define REG_TC1_QISR REG_ACCESS(RoReg, 0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ +#define REG_TC1_FMR REG_ACCESS(RwReg, 0x400140D8U) /**< \brief (TC1) Fault Mode Register */ +#define REG_TC1_WPMR REG_ACCESS(RwReg, 0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */ +#define REG_TC1_VER REG_ACCESS(RoReg, 0x400140FCU) /**< \brief (TC1) Version Register */ +/* ========== Register definition for TWI0 peripheral ========== */ +#define REG_TWI0_CR REG_ACCESS(WoReg, 0x40018000U) /**< \brief (TWI0) Control Register */ +#define REG_TWI0_MMR REG_ACCESS(RwReg, 0x40018004U) /**< \brief (TWI0) Master Mode Register */ +#define REG_TWI0_SMR REG_ACCESS(RwReg, 0x40018008U) /**< \brief (TWI0) Slave Mode Register */ +#define REG_TWI0_IADR REG_ACCESS(RwReg, 0x4001800CU) /**< \brief (TWI0) Internal Address Register */ +#define REG_TWI0_CWGR REG_ACCESS(RwReg, 0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */ +#define REG_TWI0_SR REG_ACCESS(RoReg, 0x40018020U) /**< \brief (TWI0) Status Register */ +#define REG_TWI0_IER REG_ACCESS(WoReg, 0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */ +#define REG_TWI0_IDR REG_ACCESS(WoReg, 0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */ +#define REG_TWI0_IMR REG_ACCESS(RoReg, 0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */ +#define REG_TWI0_RHR REG_ACCESS(RoReg, 0x40018030U) /**< \brief (TWI0) Receive Holding Register */ +#define REG_TWI0_THR REG_ACCESS(WoReg, 0x40018034U) /**< \brief (TWI0) Transmit Holding Register */ +#define REG_TWI0_RPR REG_ACCESS(RwReg, 0x40018100U) /**< \brief (TWI0) Receive Pointer Register */ +#define REG_TWI0_RCR REG_ACCESS(RwReg, 0x40018104U) /**< \brief (TWI0) Receive Counter Register */ +#define REG_TWI0_TPR REG_ACCESS(RwReg, 0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */ +#define REG_TWI0_TCR REG_ACCESS(RwReg, 0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */ +#define REG_TWI0_RNPR REG_ACCESS(RwReg, 0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */ +#define REG_TWI0_RNCR REG_ACCESS(RwReg, 0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */ +#define REG_TWI0_TNPR REG_ACCESS(RwReg, 0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */ +#define REG_TWI0_TNCR REG_ACCESS(RwReg, 0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */ +#define REG_TWI0_PTCR REG_ACCESS(WoReg, 0x40018120U) /**< \brief (TWI0) Transfer Control Register */ +#define REG_TWI0_PTSR REG_ACCESS(RoReg, 0x40018124U) /**< \brief (TWI0) Transfer Status Register */ +/* ========== Register definition for TWI1 peripheral ========== */ +#define REG_TWI1_CR REG_ACCESS(WoReg, 0x4001C000U) /**< \brief (TWI1) Control Register */ +#define REG_TWI1_MMR REG_ACCESS(RwReg, 0x4001C004U) /**< \brief (TWI1) Master Mode Register */ +#define REG_TWI1_SMR REG_ACCESS(RwReg, 0x4001C008U) /**< \brief (TWI1) Slave Mode Register */ +#define REG_TWI1_IADR REG_ACCESS(RwReg, 0x4001C00CU) /**< \brief (TWI1) Internal Address Register */ +#define REG_TWI1_CWGR REG_ACCESS(RwReg, 0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */ +#define REG_TWI1_SR REG_ACCESS(RoReg, 0x4001C020U) /**< \brief (TWI1) Status Register */ +#define REG_TWI1_IER REG_ACCESS(WoReg, 0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */ +#define REG_TWI1_IDR REG_ACCESS(WoReg, 0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */ +#define REG_TWI1_IMR REG_ACCESS(RoReg, 0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */ +#define REG_TWI1_RHR REG_ACCESS(RoReg, 0x4001C030U) /**< \brief (TWI1) Receive Holding Register */ +#define REG_TWI1_THR REG_ACCESS(WoReg, 0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */ +#define REG_TWI1_RPR REG_ACCESS(RwReg, 0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */ +#define REG_TWI1_RCR REG_ACCESS(RwReg, 0x4001C104U) /**< \brief (TWI1) Receive Counter Register */ +#define REG_TWI1_TPR REG_ACCESS(RwReg, 0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */ +#define REG_TWI1_TCR REG_ACCESS(RwReg, 0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */ +#define REG_TWI1_RNPR REG_ACCESS(RwReg, 0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */ +#define REG_TWI1_RNCR REG_ACCESS(RwReg, 0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */ +#define REG_TWI1_TNPR REG_ACCESS(RwReg, 0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */ +#define REG_TWI1_TNCR REG_ACCESS(RwReg, 0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */ +#define REG_TWI1_PTCR REG_ACCESS(WoReg, 0x4001C120U) /**< \brief (TWI1) Transfer Control Register */ +#define REG_TWI1_PTSR REG_ACCESS(RoReg, 0x4001C124U) /**< \brief (TWI1) Transfer Status Register */ +/* ========== Register definition for PWM peripheral ========== */ +#define REG_PWM_CLK REG_ACCESS(RwReg, 0x40020000U) /**< \brief (PWM) PWM Clock Register */ +#define REG_PWM_ENA REG_ACCESS(WoReg, 0x40020004U) /**< \brief (PWM) PWM Enable Register */ +#define REG_PWM_DIS REG_ACCESS(WoReg, 0x40020008U) /**< \brief (PWM) PWM Disable Register */ +#define REG_PWM_SR REG_ACCESS(RoReg, 0x4002000CU) /**< \brief (PWM) PWM Status Register */ +#define REG_PWM_IER1 REG_ACCESS(WoReg, 0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ +#define REG_PWM_IDR1 REG_ACCESS(WoReg, 0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ +#define REG_PWM_IMR1 REG_ACCESS(RoReg, 0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ +#define REG_PWM_ISR1 REG_ACCESS(RoReg, 0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ +#define REG_PWM_SCM REG_ACCESS(RwReg, 0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ +#define REG_PWM_SCUC REG_ACCESS(RwReg, 0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ +#define REG_PWM_SCUP REG_ACCESS(RwReg, 0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ +#define REG_PWM_SCUPUPD REG_ACCESS(WoReg, 0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ +#define REG_PWM_IER2 REG_ACCESS(WoReg, 0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ +#define REG_PWM_IDR2 REG_ACCESS(WoReg, 0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ +#define REG_PWM_IMR2 REG_ACCESS(RoReg, 0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ +#define REG_PWM_ISR2 REG_ACCESS(RoReg, 0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ +#define REG_PWM_OOV REG_ACCESS(RwReg, 0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */ +#define REG_PWM_OS REG_ACCESS(RwReg, 0x40020048U) /**< \brief (PWM) PWM Output Selection Register */ +#define REG_PWM_OSS REG_ACCESS(WoReg, 0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */ +#define REG_PWM_OSC REG_ACCESS(WoReg, 0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */ +#define REG_PWM_OSSUPD REG_ACCESS(WoReg, 0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ +#define REG_PWM_OSCUPD REG_ACCESS(WoReg, 0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ +#define REG_PWM_FMR REG_ACCESS(RwReg, 0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */ +#define REG_PWM_FSR REG_ACCESS(RoReg, 0x40020060U) /**< \brief (PWM) PWM Fault Status Register */ +#define REG_PWM_FCR REG_ACCESS(WoReg, 0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */ +#define REG_PWM_FPV REG_ACCESS(RwReg, 0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */ +#define REG_PWM_FPE REG_ACCESS(RwReg, 0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */ +#define REG_PWM_ELxMR REG_ACCESS(RwReg, 0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ +#define REG_PWM_SMMR REG_ACCESS(RwReg, 0x400200B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */ +#define REG_PWM_WPCR REG_ACCESS(WoReg, 0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */ +#define REG_PWM_WPSR REG_ACCESS(RoReg, 0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */ +#define REG_PWM_RPR REG_ACCESS(RwReg, 0x40020100U) /**< \brief (PWM) Receive Pointer Register */ +#define REG_PWM_RCR REG_ACCESS(RwReg, 0x40020104U) /**< \brief (PWM) Receive Counter Register */ +#define REG_PWM_TPR REG_ACCESS(RwReg, 0x40020108U) /**< \brief (PWM) Transmit Pointer Register */ +#define REG_PWM_TCR REG_ACCESS(RwReg, 0x4002010CU) /**< \brief (PWM) Transmit Counter Register */ +#define REG_PWM_RNPR REG_ACCESS(RwReg, 0x40020110U) /**< \brief (PWM) Receive Next Pointer Register */ +#define REG_PWM_RNCR REG_ACCESS(RwReg, 0x40020114U) /**< \brief (PWM) Receive Next Counter Register */ +#define REG_PWM_TNPR REG_ACCESS(RwReg, 0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */ +#define REG_PWM_TNCR REG_ACCESS(RwReg, 0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */ +#define REG_PWM_PTCR REG_ACCESS(WoReg, 0x40020120U) /**< \brief (PWM) Transfer Control Register */ +#define REG_PWM_PTSR REG_ACCESS(RoReg, 0x40020124U) /**< \brief (PWM) Transfer Status Register */ +#define REG_PWM_CMP0V REG_ACCESS(RwReg, 0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ +#define REG_PWM_CMP0VUPD REG_ACCESS(WoReg, 0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ +#define REG_PWM_CMP0M REG_ACCESS(RwReg, 0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ +#define REG_PWM_CMP0MUPD REG_ACCESS(WoReg, 0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ +#define REG_PWM_CMP1V REG_ACCESS(RwReg, 0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ +#define REG_PWM_CMP1VUPD REG_ACCESS(WoReg, 0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ +#define REG_PWM_CMP1M REG_ACCESS(RwReg, 0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ +#define REG_PWM_CMP1MUPD REG_ACCESS(WoReg, 0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ +#define REG_PWM_CMP2V REG_ACCESS(RwReg, 0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ +#define REG_PWM_CMP2VUPD REG_ACCESS(WoReg, 0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ +#define REG_PWM_CMP2M REG_ACCESS(RwReg, 0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ +#define REG_PWM_CMP2MUPD REG_ACCESS(WoReg, 0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ +#define REG_PWM_CMP3V REG_ACCESS(RwReg, 0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ +#define REG_PWM_CMP3VUPD REG_ACCESS(WoReg, 0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ +#define REG_PWM_CMP3M REG_ACCESS(RwReg, 0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ +#define REG_PWM_CMP3MUPD REG_ACCESS(WoReg, 0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ +#define REG_PWM_CMP4V REG_ACCESS(RwReg, 0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ +#define REG_PWM_CMP4VUPD REG_ACCESS(WoReg, 0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ +#define REG_PWM_CMP4M REG_ACCESS(RwReg, 0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ +#define REG_PWM_CMP4MUPD REG_ACCESS(WoReg, 0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ +#define REG_PWM_CMP5V REG_ACCESS(RwReg, 0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ +#define REG_PWM_CMP5VUPD REG_ACCESS(WoReg, 0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ +#define REG_PWM_CMP5M REG_ACCESS(RwReg, 0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ +#define REG_PWM_CMP5MUPD REG_ACCESS(WoReg, 0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ +#define REG_PWM_CMP6V REG_ACCESS(RwReg, 0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ +#define REG_PWM_CMP6VUPD REG_ACCESS(WoReg, 0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ +#define REG_PWM_CMP6M REG_ACCESS(RwReg, 0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ +#define REG_PWM_CMP6MUPD REG_ACCESS(WoReg, 0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ +#define REG_PWM_CMP7V REG_ACCESS(RwReg, 0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ +#define REG_PWM_CMP7VUPD REG_ACCESS(WoReg, 0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ +#define REG_PWM_CMP7M REG_ACCESS(RwReg, 0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ +#define REG_PWM_CMP7MUPD REG_ACCESS(WoReg, 0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ +#define REG_PWM_CMR0 REG_ACCESS(RwReg, 0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ +#define REG_PWM_CDTY0 REG_ACCESS(RwReg, 0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ +#define REG_PWM_CDTYUPD0 REG_ACCESS(WoReg, 0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ +#define REG_PWM_CPRD0 REG_ACCESS(RwReg, 0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ +#define REG_PWM_CPRDUPD0 REG_ACCESS(WoReg, 0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ +#define REG_PWM_CCNT0 REG_ACCESS(RoReg, 0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ +#define REG_PWM_DT0 REG_ACCESS(RwReg, 0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ +#define REG_PWM_DTUPD0 REG_ACCESS(WoReg, 0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ +#define REG_PWM_CMR1 REG_ACCESS(RwReg, 0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ +#define REG_PWM_CDTY1 REG_ACCESS(RwReg, 0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ +#define REG_PWM_CDTYUPD1 REG_ACCESS(WoReg, 0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ +#define REG_PWM_CPRD1 REG_ACCESS(RwReg, 0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ +#define REG_PWM_CPRDUPD1 REG_ACCESS(WoReg, 0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ +#define REG_PWM_CCNT1 REG_ACCESS(RoReg, 0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ +#define REG_PWM_DT1 REG_ACCESS(RwReg, 0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ +#define REG_PWM_DTUPD1 REG_ACCESS(WoReg, 0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ +#define REG_PWM_CMR2 REG_ACCESS(RwReg, 0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ +#define REG_PWM_CDTY2 REG_ACCESS(RwReg, 0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ +#define REG_PWM_CDTYUPD2 REG_ACCESS(WoReg, 0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ +#define REG_PWM_CPRD2 REG_ACCESS(RwReg, 0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ +#define REG_PWM_CPRDUPD2 REG_ACCESS(WoReg, 0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ +#define REG_PWM_CCNT2 REG_ACCESS(RoReg, 0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ +#define REG_PWM_DT2 REG_ACCESS(RwReg, 0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ +#define REG_PWM_DTUPD2 REG_ACCESS(WoReg, 0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ +#define REG_PWM_CMR3 REG_ACCESS(RwReg, 0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ +#define REG_PWM_CDTY3 REG_ACCESS(RwReg, 0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ +#define REG_PWM_CDTYUPD3 REG_ACCESS(WoReg, 0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ +#define REG_PWM_CPRD3 REG_ACCESS(RwReg, 0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ +#define REG_PWM_CPRDUPD3 REG_ACCESS(WoReg, 0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ +#define REG_PWM_CCNT3 REG_ACCESS(RoReg, 0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ +#define REG_PWM_DT3 REG_ACCESS(RwReg, 0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ +#define REG_PWM_DTUPD3 REG_ACCESS(WoReg, 0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ +/* ========== Register definition for USART0 peripheral ========== */ +#define REG_USART0_CR REG_ACCESS(WoReg, 0x40024000U) /**< \brief (USART0) Control Register */ +#define REG_USART0_MR REG_ACCESS(RwReg, 0x40024004U) /**< \brief (USART0) Mode Register */ +#define REG_USART0_IER REG_ACCESS(WoReg, 0x40024008U) /**< \brief (USART0) Interrupt Enable Register */ +#define REG_USART0_IDR REG_ACCESS(WoReg, 0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */ +#define REG_USART0_IMR REG_ACCESS(RoReg, 0x40024010U) /**< \brief (USART0) Interrupt Mask Register */ +#define REG_USART0_CSR REG_ACCESS(RoReg, 0x40024014U) /**< \brief (USART0) Channel Status Register */ +#define REG_USART0_RHR REG_ACCESS(RoReg, 0x40024018U) /**< \brief (USART0) Receiver Holding Register */ +#define REG_USART0_THR REG_ACCESS(WoReg, 0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */ +#define REG_USART0_BRGR REG_ACCESS(RwReg, 0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */ +#define REG_USART0_RTOR REG_ACCESS(RwReg, 0x40024024U) /**< \brief (USART0) Receiver Time-out Register */ +#define REG_USART0_TTGR REG_ACCESS(RwReg, 0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */ +#define REG_USART0_FIDI REG_ACCESS(RwReg, 0x40024040U) /**< \brief (USART0) FI DI Ratio Register */ +#define REG_USART0_NER REG_ACCESS(RoReg, 0x40024044U) /**< \brief (USART0) Number of Errors Register */ +#define REG_USART0_IF REG_ACCESS(RwReg, 0x4002404CU) /**< \brief (USART0) IrDA Filter Register */ +#define REG_USART0_MAN REG_ACCESS(RwReg, 0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */ +#define REG_USART0_WPMR REG_ACCESS(RwReg, 0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */ +#define REG_USART0_WPSR REG_ACCESS(RoReg, 0x400240E8U) /**< \brief (USART0) Write Protect Status Register */ +#define REG_USART0_VERSION REG_ACCESS(RoReg, 0x400240FCU) /**< \brief (USART0) Version Register */ +#define REG_USART0_RPR REG_ACCESS(RwReg, 0x40024100U) /**< \brief (USART0) Receive Pointer Register */ +#define REG_USART0_RCR REG_ACCESS(RwReg, 0x40024104U) /**< \brief (USART0) Receive Counter Register */ +#define REG_USART0_TPR REG_ACCESS(RwReg, 0x40024108U) /**< \brief (USART0) Transmit Pointer Register */ +#define REG_USART0_TCR REG_ACCESS(RwReg, 0x4002410CU) /**< \brief (USART0) Transmit Counter Register */ +#define REG_USART0_RNPR REG_ACCESS(RwReg, 0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */ +#define REG_USART0_RNCR REG_ACCESS(RwReg, 0x40024114U) /**< \brief (USART0) Receive Next Counter Register */ +#define REG_USART0_TNPR REG_ACCESS(RwReg, 0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */ +#define REG_USART0_TNCR REG_ACCESS(RwReg, 0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */ +#define REG_USART0_PTCR REG_ACCESS(WoReg, 0x40024120U) /**< \brief (USART0) Transfer Control Register */ +#define REG_USART0_PTSR REG_ACCESS(RoReg, 0x40024124U) /**< \brief (USART0) Transfer Status Register */ +/* ========== Register definition for USART1 peripheral ========== */ +#define REG_USART1_CR REG_ACCESS(WoReg, 0x40028000U) /**< \brief (USART1) Control Register */ +#define REG_USART1_MR REG_ACCESS(RwReg, 0x40028004U) /**< \brief (USART1) Mode Register */ +#define REG_USART1_IER REG_ACCESS(WoReg, 0x40028008U) /**< \brief (USART1) Interrupt Enable Register */ +#define REG_USART1_IDR REG_ACCESS(WoReg, 0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */ +#define REG_USART1_IMR REG_ACCESS(RoReg, 0x40028010U) /**< \brief (USART1) Interrupt Mask Register */ +#define REG_USART1_CSR REG_ACCESS(RoReg, 0x40028014U) /**< \brief (USART1) Channel Status Register */ +#define REG_USART1_RHR REG_ACCESS(RoReg, 0x40028018U) /**< \brief (USART1) Receiver Holding Register */ +#define REG_USART1_THR REG_ACCESS(WoReg, 0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */ +#define REG_USART1_BRGR REG_ACCESS(RwReg, 0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */ +#define REG_USART1_RTOR REG_ACCESS(RwReg, 0x40028024U) /**< \brief (USART1) Receiver Time-out Register */ +#define REG_USART1_TTGR REG_ACCESS(RwReg, 0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */ +#define REG_USART1_FIDI REG_ACCESS(RwReg, 0x40028040U) /**< \brief (USART1) FI DI Ratio Register */ +#define REG_USART1_NER REG_ACCESS(RoReg, 0x40028044U) /**< \brief (USART1) Number of Errors Register */ +#define REG_USART1_IF REG_ACCESS(RwReg, 0x4002804CU) /**< \brief (USART1) IrDA Filter Register */ +#define REG_USART1_MAN REG_ACCESS(RwReg, 0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ +#define REG_USART1_WPMR REG_ACCESS(RwReg, 0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */ +#define REG_USART1_WPSR REG_ACCESS(RoReg, 0x400280E8U) /**< \brief (USART1) Write Protect Status Register */ +#define REG_USART1_VERSION REG_ACCESS(RoReg, 0x400280FCU) /**< \brief (USART1) Version Register */ +#define REG_USART1_RPR REG_ACCESS(RwReg, 0x40028100U) /**< \brief (USART1) Receive Pointer Register */ +#define REG_USART1_RCR REG_ACCESS(RwReg, 0x40028104U) /**< \brief (USART1) Receive Counter Register */ +#define REG_USART1_TPR REG_ACCESS(RwReg, 0x40028108U) /**< \brief (USART1) Transmit Pointer Register */ +#define REG_USART1_TCR REG_ACCESS(RwReg, 0x4002810CU) /**< \brief (USART1) Transmit Counter Register */ +#define REG_USART1_RNPR REG_ACCESS(RwReg, 0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */ +#define REG_USART1_RNCR REG_ACCESS(RwReg, 0x40028114U) /**< \brief (USART1) Receive Next Counter Register */ +#define REG_USART1_TNPR REG_ACCESS(RwReg, 0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */ +#define REG_USART1_TNCR REG_ACCESS(RwReg, 0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */ +#define REG_USART1_PTCR REG_ACCESS(WoReg, 0x40028120U) /**< \brief (USART1) Transfer Control Register */ +#define REG_USART1_PTSR REG_ACCESS(RoReg, 0x40028124U) /**< \brief (USART1) Transfer Status Register */ +/* ========== Register definition for UDP peripheral ========== */ +#define REG_UDP_FRM_NUM REG_ACCESS(RoReg, 0x40034000U) /**< \brief (UDP) Frame Number Register */ +#define REG_UDP_GLB_STAT REG_ACCESS(RwReg, 0x40034004U) /**< \brief (UDP) Global State Register */ +#define REG_UDP_FADDR REG_ACCESS(RwReg, 0x40034008U) /**< \brief (UDP) Function Address Register */ +#define REG_UDP_IER REG_ACCESS(WoReg, 0x40034010U) /**< \brief (UDP) Interrupt Enable Register */ +#define REG_UDP_IDR REG_ACCESS(WoReg, 0x40034014U) /**< \brief (UDP) Interrupt Disable Register */ +#define REG_UDP_IMR REG_ACCESS(RoReg, 0x40034018U) /**< \brief (UDP) Interrupt Mask Register */ +#define REG_UDP_ISR REG_ACCESS(RoReg, 0x4003401CU) /**< \brief (UDP) Interrupt Status Register */ +#define REG_UDP_ICR REG_ACCESS(WoReg, 0x40034020U) /**< \brief (UDP) Interrupt Clear Register */ +#define REG_UDP_RST_EP REG_ACCESS(RwReg, 0x40034028U) /**< \brief (UDP) Reset Endpoint Register */ +#define REG_UDP_CSR REG_ACCESS(RwReg, 0x4003402CU) /**< \brief (UDP) Endpoint Control and Status Register (ept_num = 0) */ +#define REG_UDP_FDR REG_ACCESS(RwReg, 0x4003404CU) /**< \brief (UDP) Endpoint FIFO Data Register (ept_num = 0) */ +#define REG_UDP_TXVC REG_ACCESS(RwReg, 0x40034074U) /**< \brief (UDP) Transceiver Control Register */ +/* ========== Register definition for ADC peripheral ========== */ +#define REG_ADC_CR REG_ACCESS(WoReg, 0x40038000U) /**< \brief (ADC) Control Register */ +#define REG_ADC_MR REG_ACCESS(RwReg, 0x40038004U) /**< \brief (ADC) Mode Register */ +#define REG_ADC_SEQ1R REG_ACCESS(RwReg, 0x40038008U) /**< \brief (ADC) Channel Sequence 1Register */ +#define REG_ADC_SEQ2R REG_ACCESS(RwReg, 0x4003800CU) /**< \brief (ADC) Channel Sequence 2 Register */ +#define REG_ADC_CHER REG_ACCESS(WoReg, 0x40038010U) /**< \brief (ADC) Channel Enable Register */ +#define REG_ADC_CHDR REG_ACCESS(WoReg, 0x40038014U) /**< \brief (ADC) Channel Disable Register */ +#define REG_ADC_CHSR REG_ACCESS(RoReg, 0x40038018U) /**< \brief (ADC) Channel Status Register */ +#define REG_ADC_LCDR REG_ACCESS(RoReg, 0x40038020U) /**< \brief (ADC) Last Converted Data Register */ +#define REG_ADC_IER REG_ACCESS(WoReg, 0x40038024U) /**< \brief (ADC) Interrupt Enable Register */ +#define REG_ADC_IDR REG_ACCESS(WoReg, 0x40038028U) /**< \brief (ADC) Interrupt Disable Register */ +#define REG_ADC_IMR REG_ACCESS(RoReg, 0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */ +#define REG_ADC_ISR REG_ACCESS(RoReg, 0x40038030U) /**< \brief (ADC) Interrupt Status Register */ +#define REG_ADC_OVER REG_ACCESS(RoReg, 0x4003803CU) /**< \brief (ADC) Overrun Status Register */ +#define REG_ADC_EMR REG_ACCESS(RwReg, 0x40038040U) /**< \brief (ADC) Extended Mode Register */ +#define REG_ADC_CWR REG_ACCESS(RwReg, 0x40038044U) /**< \brief (ADC) Compare Window Register */ +#define REG_ADC_CGR REG_ACCESS(RwReg, 0x40038048U) /**< \brief (ADC) Channel Gain Register */ +#define REG_ADC_COR REG_ACCESS(RwReg, 0x4003804CU) /**< \brief (ADC) Channel Offset Register */ +#define REG_ADC_CDR0 REG_ACCESS(RoReg, 0x40038050U) /**< \brief (ADC) Channel Data Register 0 */ +#define REG_ADC_CDR1 REG_ACCESS(RoReg, 0x40038054U) /**< \brief (ADC) Channel Data Register 1 */ +#define REG_ADC_CDR2 REG_ACCESS(RoReg, 0x40038058U) /**< \brief (ADC) Channel Data Register 2 */ +#define REG_ADC_CDR3 REG_ACCESS(RoReg, 0x4003805CU) /**< \brief (ADC) Channel Data Register 3 */ +#define REG_ADC_CDR4 REG_ACCESS(RoReg, 0x40038060U) /**< \brief (ADC) Channel Data Register 4 */ +#define REG_ADC_CDR5 REG_ACCESS(RoReg, 0x40038064U) /**< \brief (ADC) Channel Data Register 5 */ +#define REG_ADC_CDR6 REG_ACCESS(RoReg, 0x40038068U) /**< \brief (ADC) Channel Data Register 6 */ +#define REG_ADC_CDR15 REG_ACCESS(RoReg, 0x4003806CU) /**< \brief (ADC) Channel Data Register 15 */ +#define REG_ADC_ACR REG_ACCESS(RwReg, 0x40038094U) /**< \brief (ADC) Analog Control Register */ +#define REG_ADC_WPMR REG_ACCESS(RwReg, 0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */ +#define REG_ADC_WPSR REG_ACCESS(RoReg, 0x400380E8U) /**< \brief (ADC) Write Protect Status Register */ +#define REG_ADC_RPR REG_ACCESS(RwReg, 0x40038100U) /**< \brief (ADC) Receive Pointer Register */ +#define REG_ADC_RCR REG_ACCESS(RwReg, 0x40038104U) /**< \brief (ADC) Receive Counter Register */ +#define REG_ADC_TPR REG_ACCESS(RwReg, 0x40038108U) /**< \brief (ADC) Transmit Pointer Register */ +#define REG_ADC_TCR REG_ACCESS(RwReg, 0x4003810CU) /**< \brief (ADC) Transmit Counter Register */ +#define REG_ADC_RNPR REG_ACCESS(RwReg, 0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */ +#define REG_ADC_RNCR REG_ACCESS(RwReg, 0x40038114U) /**< \brief (ADC) Receive Next Counter Register */ +#define REG_ADC_TNPR REG_ACCESS(RwReg, 0x40038118U) /**< \brief (ADC) Transmit Next Pointer Register */ +#define REG_ADC_TNCR REG_ACCESS(RwReg, 0x4003811CU) /**< \brief (ADC) Transmit Next Counter Register */ +#define REG_ADC_PTCR REG_ACCESS(WoReg, 0x40038120U) /**< \brief (ADC) Transfer Control Register */ +#define REG_ADC_PTSR REG_ACCESS(RoReg, 0x40038124U) /**< \brief (ADC) Transfer Status Register */ +/* ========== Register definition for DACC peripheral ========== */ +#define REG_DACC_CR REG_ACCESS(WoReg, 0x4003C000U) /**< \brief (DACC) Control Register */ +#define REG_DACC_MR REG_ACCESS(RwReg, 0x4003C004U) /**< \brief (DACC) Mode Register */ +#define REG_DACC_CHER REG_ACCESS(WoReg, 0x4003C010U) /**< \brief (DACC) Channel Enable Register */ +#define REG_DACC_CHDR REG_ACCESS(WoReg, 0x4003C014U) /**< \brief (DACC) Channel Disable Register */ +#define REG_DACC_CHSR REG_ACCESS(RoReg, 0x4003C018U) /**< \brief (DACC) Channel Status Register */ +#define REG_DACC_CDR REG_ACCESS(WoReg, 0x4003C020U) /**< \brief (DACC) Conversion Data Register */ +#define REG_DACC_IER REG_ACCESS(WoReg, 0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */ +#define REG_DACC_IDR REG_ACCESS(WoReg, 0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */ +#define REG_DACC_IMR REG_ACCESS(RoReg, 0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */ +#define REG_DACC_ISR REG_ACCESS(RoReg, 0x4003C030U) /**< \brief (DACC) Interrupt Status Register */ +#define REG_DACC_ACR REG_ACCESS(RwReg, 0x4003C094U) /**< \brief (DACC) Analog Current Register */ +#define REG_DACC_WPMR REG_ACCESS(RwReg, 0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */ +#define REG_DACC_WPSR REG_ACCESS(RoReg, 0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */ +#define REG_DACC_RPR REG_ACCESS(RwReg, 0x4003C100U) /**< \brief (DACC) Receive Pointer Register */ +#define REG_DACC_RCR REG_ACCESS(RwReg, 0x4003C104U) /**< \brief (DACC) Receive Counter Register */ +#define REG_DACC_TPR REG_ACCESS(RwReg, 0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */ +#define REG_DACC_TCR REG_ACCESS(RwReg, 0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */ +#define REG_DACC_RNPR REG_ACCESS(RwReg, 0x4003C110U) /**< \brief (DACC) Receive Next Pointer Register */ +#define REG_DACC_RNCR REG_ACCESS(RwReg, 0x4003C114U) /**< \brief (DACC) Receive Next Counter Register */ +#define REG_DACC_TNPR REG_ACCESS(RwReg, 0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */ +#define REG_DACC_TNCR REG_ACCESS(RwReg, 0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */ +#define REG_DACC_PTCR REG_ACCESS(WoReg, 0x4003C120U) /**< \brief (DACC) Transfer Control Register */ +#define REG_DACC_PTSR REG_ACCESS(RoReg, 0x4003C124U) /**< \brief (DACC) Transfer Status Register */ +/* ========== Register definition for ACC peripheral ========== */ +#define REG_ACC_CR REG_ACCESS(WoReg, 0x40040000U) /**< \brief (ACC) Control Register */ +#define REG_ACC_MR REG_ACCESS(RwReg, 0x40040004U) /**< \brief (ACC) Mode Register */ +#define REG_ACC_IER REG_ACCESS(WoReg, 0x40040024U) /**< \brief (ACC) Interrupt Enable Register */ +#define REG_ACC_IDR REG_ACCESS(WoReg, 0x40040028U) /**< \brief (ACC) Interrupt Disable Register */ +#define REG_ACC_IMR REG_ACCESS(RoReg, 0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */ +#define REG_ACC_ISR REG_ACCESS(RoReg, 0x40040030U) /**< \brief (ACC) Interrupt Status Register */ +#define REG_ACC_ACR REG_ACCESS(RwReg, 0x40040094U) /**< \brief (ACC) Analog Control Register */ +#define REG_ACC_WPMR REG_ACCESS(RwReg, 0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */ +#define REG_ACC_WPSR REG_ACCESS(RoReg, 0x400400E8U) /**< \brief (ACC) Write Protect Status Register */ +/* ========== Register definition for CRCCU peripheral ========== */ +#define REG_CRCCU_DSCR REG_ACCESS(RwReg, 0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */ +#define REG_CRCCU_DMA_EN REG_ACCESS(WoReg, 0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */ +#define REG_CRCCU_DMA_DIS REG_ACCESS(WoReg, 0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */ +#define REG_CRCCU_DMA_SR REG_ACCESS(RoReg, 0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */ +#define REG_CRCCU_DMA_IER REG_ACCESS(WoReg, 0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */ +#define REG_CRCCU_DMA_IDR REG_ACCESS(WoReg, 0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */ +#define REG_CRCCU_DMA_IMR REG_ACCESS(RoReg, 0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */ +#define REG_CRCCU_DMA_ISR REG_ACCESS(RoReg, 0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */ +#define REG_CRCCU_CR REG_ACCESS(WoReg, 0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */ +#define REG_CRCCU_MR REG_ACCESS(RwReg, 0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */ +#define REG_CRCCU_SR REG_ACCESS(RoReg, 0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */ +#define REG_CRCCU_IER REG_ACCESS(WoReg, 0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */ +#define REG_CRCCU_IDR REG_ACCESS(WoReg, 0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */ +#define REG_CRCCU_IMR REG_ACCESS(RoReg, 0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */ +#define REG_CRCCU_ISR REG_ACCESS(RoReg, 0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */ +/* ========== Register definition for SMC peripheral ========== */ +#define REG_SMC_SETUP0 REG_ACCESS(RwReg, 0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ +#define REG_SMC_PULSE0 REG_ACCESS(RwReg, 0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ +#define REG_SMC_CYCLE0 REG_ACCESS(RwReg, 0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ +#define REG_SMC_MODE0 REG_ACCESS(RwReg, 0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ +#define REG_SMC_SETUP1 REG_ACCESS(RwReg, 0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ +#define REG_SMC_PULSE1 REG_ACCESS(RwReg, 0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ +#define REG_SMC_CYCLE1 REG_ACCESS(RwReg, 0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ +#define REG_SMC_MODE1 REG_ACCESS(RwReg, 0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ +#define REG_SMC_SETUP2 REG_ACCESS(RwReg, 0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ +#define REG_SMC_PULSE2 REG_ACCESS(RwReg, 0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ +#define REG_SMC_CYCLE2 REG_ACCESS(RwReg, 0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ +#define REG_SMC_MODE2 REG_ACCESS(RwReg, 0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ +#define REG_SMC_SETUP3 REG_ACCESS(RwReg, 0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ +#define REG_SMC_PULSE3 REG_ACCESS(RwReg, 0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ +#define REG_SMC_CYCLE3 REG_ACCESS(RwReg, 0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ +#define REG_SMC_MODE3 REG_ACCESS(RwReg, 0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ +#define REG_SMC_SETUP4 REG_ACCESS(RwReg, 0x400E0040U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */ +#define REG_SMC_PULSE4 REG_ACCESS(RwReg, 0x400E0044U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */ +#define REG_SMC_CYCLE4 REG_ACCESS(RwReg, 0x400E0048U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */ +#define REG_SMC_MODE4 REG_ACCESS(RwReg, 0x400E004CU) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */ +#define REG_SMC_OCMS REG_ACCESS(RwReg, 0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */ +#define REG_SMC_KEY1 REG_ACCESS(WoReg, 0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */ +#define REG_SMC_KEY2 REG_ACCESS(WoReg, 0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */ +#define REG_SMC_WPMR REG_ACCESS(RwReg, 0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */ +#define REG_SMC_WPSR REG_ACCESS(RoReg, 0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */ +/* ========== Register definition for MATRIX peripheral ========== */ +#define REG_MATRIX_MCFG REG_ACCESS(RwReg, 0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */ +#define REG_MATRIX_SCFG REG_ACCESS(RwReg, 0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */ +#define REG_MATRIX_PRAS0 REG_ACCESS(RwReg, 0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ +#define REG_MATRIX_PRAS1 REG_ACCESS(RwReg, 0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ +#define REG_MATRIX_PRAS2 REG_ACCESS(RwReg, 0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ +#define REG_MATRIX_PRAS3 REG_ACCESS(RwReg, 0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ +#define REG_MATRIX_PRAS4 REG_ACCESS(RwReg, 0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ +#define REG_MATRIX_SYSIO REG_ACCESS(RwReg, 0x400E0314U) /**< \brief (MATRIX) System IO Configuration register */ +#define REG_MATRIX_SMCNFCS REG_ACCESS(RwReg, 0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */ +#define REG_MATRIX_WPMR REG_ACCESS(RwReg, 0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */ +#define REG_MATRIX_WPSR REG_ACCESS(RoReg, 0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */ +/* ========== Register definition for PMC peripheral ========== */ +#define REG_PMC_SCER REG_ACCESS(WoReg, 0x400E0400U) /**< \brief (PMC) System Clock Enable Register */ +#define REG_PMC_SCDR REG_ACCESS(WoReg, 0x400E0404U) /**< \brief (PMC) System Clock Disable Register */ +#define REG_PMC_SCSR REG_ACCESS(RoReg, 0x400E0408U) /**< \brief (PMC) System Clock Status Register */ +#define REG_PMC_PCER0 REG_ACCESS(WoReg, 0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ +#define REG_PMC_PCDR0 REG_ACCESS(WoReg, 0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ +#define REG_PMC_PCSR0 REG_ACCESS(RoReg, 0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ +#define REG_PMC_MOR REG_ACCESS(RwReg, 0x400E0420U) /**< \brief (PMC) Main Oscillator Register */ +#define REG_PMC_MCFR REG_ACCESS(RoReg, 0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */ +#define REG_PMC_PLLAR REG_ACCESS(RwReg, 0x400E0428U) /**< \brief (PMC) PLLA Register */ +#define REG_PMC_PLLBR REG_ACCESS(RwReg, 0x400E042CU) /**< \brief (PMC) PLLB Register */ +#define REG_PMC_MCKR REG_ACCESS(RwReg, 0x400E0430U) /**< \brief (PMC) Master Clock Register */ +#define REG_PMC_USB REG_ACCESS(RwReg, 0x400E0438U) /**< \brief (PMC) USB Clock Register */ +#define REG_PMC_PCK REG_ACCESS(RwReg, 0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */ +#define REG_PMC_IER REG_ACCESS(WoReg, 0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */ +#define REG_PMC_IDR REG_ACCESS(WoReg, 0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */ +#define REG_PMC_SR REG_ACCESS(RoReg, 0x400E0468U) /**< \brief (PMC) Status Register */ +#define REG_PMC_IMR REG_ACCESS(RoReg, 0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */ +#define REG_PMC_FSMR REG_ACCESS(RwReg, 0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */ +#define REG_PMC_FSPR REG_ACCESS(RwReg, 0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */ +#define REG_PMC_FOCR REG_ACCESS(WoReg, 0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */ +#define REG_PMC_WPMR REG_ACCESS(RwReg, 0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */ +#define REG_PMC_WPSR REG_ACCESS(RoReg, 0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */ +#define REG_PMC_PCER1 REG_ACCESS(WoReg, 0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ +#define REG_PMC_PCDR1 REG_ACCESS(WoReg, 0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ +#define REG_PMC_PCSR1 REG_ACCESS(RoReg, 0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ +#define REG_PMC_OCR REG_ACCESS(RwReg, 0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */ +/* ========== Register definition for UART0 peripheral ========== */ +#define REG_UART0_CR REG_ACCESS(WoReg, 0x400E0600U) /**< \brief (UART0) Control Register */ +#define REG_UART0_MR REG_ACCESS(RwReg, 0x400E0604U) /**< \brief (UART0) Mode Register */ +#define REG_UART0_IER REG_ACCESS(WoReg, 0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */ +#define REG_UART0_IDR REG_ACCESS(WoReg, 0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */ +#define REG_UART0_IMR REG_ACCESS(RoReg, 0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */ +#define REG_UART0_SR REG_ACCESS(RoReg, 0x400E0614U) /**< \brief (UART0) Status Register */ +#define REG_UART0_RHR REG_ACCESS(RoReg, 0x400E0618U) /**< \brief (UART0) Receive Holding Register */ +#define REG_UART0_THR REG_ACCESS(WoReg, 0x400E061CU) /**< \brief (UART0) Transmit Holding Register */ +#define REG_UART0_BRGR REG_ACCESS(RwReg, 0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */ +#define REG_UART0_RPR REG_ACCESS(RwReg, 0x400E0700U) /**< \brief (UART0) Receive Pointer Register */ +#define REG_UART0_RCR REG_ACCESS(RwReg, 0x400E0704U) /**< \brief (UART0) Receive Counter Register */ +#define REG_UART0_TPR REG_ACCESS(RwReg, 0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */ +#define REG_UART0_TCR REG_ACCESS(RwReg, 0x400E070CU) /**< \brief (UART0) Transmit Counter Register */ +#define REG_UART0_RNPR REG_ACCESS(RwReg, 0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */ +#define REG_UART0_RNCR REG_ACCESS(RwReg, 0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */ +#define REG_UART0_TNPR REG_ACCESS(RwReg, 0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */ +#define REG_UART0_TNCR REG_ACCESS(RwReg, 0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */ +#define REG_UART0_PTCR REG_ACCESS(WoReg, 0x400E0720U) /**< \brief (UART0) Transfer Control Register */ +#define REG_UART0_PTSR REG_ACCESS(RoReg, 0x400E0724U) /**< \brief (UART0) Transfer Status Register */ +/* ========== Register definition for CHIPID peripheral ========== */ +#define REG_CHIPID_CIDR REG_ACCESS(RoReg, 0x400E0740U) /**< \brief (CHIPID) Chip ID Register */ +#define REG_CHIPID_EXID REG_ACCESS(RoReg, 0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */ +/* ========== Register definition for UART1 peripheral ========== */ +#define REG_UART1_CR REG_ACCESS(WoReg, 0x400E0800U) /**< \brief (UART1) Control Register */ +#define REG_UART1_MR REG_ACCESS(RwReg, 0x400E0804U) /**< \brief (UART1) Mode Register */ +#define REG_UART1_IER REG_ACCESS(WoReg, 0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */ +#define REG_UART1_IDR REG_ACCESS(WoReg, 0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */ +#define REG_UART1_IMR REG_ACCESS(RoReg, 0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */ +#define REG_UART1_SR REG_ACCESS(RoReg, 0x400E0814U) /**< \brief (UART1) Status Register */ +#define REG_UART1_RHR REG_ACCESS(RoReg, 0x400E0818U) /**< \brief (UART1) Receive Holding Register */ +#define REG_UART1_THR REG_ACCESS(WoReg, 0x400E081CU) /**< \brief (UART1) Transmit Holding Register */ +#define REG_UART1_BRGR REG_ACCESS(RwReg, 0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */ +#define REG_UART1_RPR REG_ACCESS(RwReg, 0x400E0900U) /**< \brief (UART1) Receive Pointer Register */ +#define REG_UART1_RCR REG_ACCESS(RwReg, 0x400E0904U) /**< \brief (UART1) Receive Counter Register */ +#define REG_UART1_TPR REG_ACCESS(RwReg, 0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */ +#define REG_UART1_TCR REG_ACCESS(RwReg, 0x400E090CU) /**< \brief (UART1) Transmit Counter Register */ +#define REG_UART1_RNPR REG_ACCESS(RwReg, 0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */ +#define REG_UART1_RNCR REG_ACCESS(RwReg, 0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */ +#define REG_UART1_TNPR REG_ACCESS(RwReg, 0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */ +#define REG_UART1_TNCR REG_ACCESS(RwReg, 0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */ +#define REG_UART1_PTCR REG_ACCESS(WoReg, 0x400E0920U) /**< \brief (UART1) Transfer Control Register */ +#define REG_UART1_PTSR REG_ACCESS(RoReg, 0x400E0924U) /**< \brief (UART1) Transfer Status Register */ +/* ========== Register definition for EFC peripheral ========== */ +#define REG_EFC_FMR REG_ACCESS(RwReg, 0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */ +#define REG_EFC_FCR REG_ACCESS(WoReg, 0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */ +#define REG_EFC_FSR REG_ACCESS(RoReg, 0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */ +#define REG_EFC_FRR REG_ACCESS(RoReg, 0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */ +/* ========== Register definition for PIOA peripheral ========== */ +#define REG_PIOA_PER REG_ACCESS(WoReg, 0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ +#define REG_PIOA_PDR REG_ACCESS(WoReg, 0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ +#define REG_PIOA_PSR REG_ACCESS(RoReg, 0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ +#define REG_PIOA_OER REG_ACCESS(WoReg, 0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ +#define REG_PIOA_ODR REG_ACCESS(WoReg, 0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ +#define REG_PIOA_OSR REG_ACCESS(RoReg, 0x400E0E18U) /**< \brief (PIOA) Output Status Register */ +#define REG_PIOA_IFER REG_ACCESS(WoReg, 0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ +#define REG_PIOA_IFDR REG_ACCESS(WoReg, 0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ +#define REG_PIOA_IFSR REG_ACCESS(RoReg, 0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ +#define REG_PIOA_SODR REG_ACCESS(WoReg, 0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ +#define REG_PIOA_CODR REG_ACCESS(WoReg, 0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ +#define REG_PIOA_ODSR REG_ACCESS(RwReg, 0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ +#define REG_PIOA_PDSR REG_ACCESS(RoReg, 0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ +#define REG_PIOA_IER REG_ACCESS(WoReg, 0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ +#define REG_PIOA_IDR REG_ACCESS(WoReg, 0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ +#define REG_PIOA_IMR REG_ACCESS(RoReg, 0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ +#define REG_PIOA_ISR REG_ACCESS(RoReg, 0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ +#define REG_PIOA_MDER REG_ACCESS(WoReg, 0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ +#define REG_PIOA_MDDR REG_ACCESS(WoReg, 0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ +#define REG_PIOA_MDSR REG_ACCESS(RoReg, 0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ +#define REG_PIOA_PUDR REG_ACCESS(WoReg, 0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ +#define REG_PIOA_PUER REG_ACCESS(WoReg, 0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ +#define REG_PIOA_PUSR REG_ACCESS(RoReg, 0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ +#define REG_PIOA_ABCDSR REG_ACCESS(RwReg, 0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ +#define REG_PIOA_SCIFSR REG_ACCESS(WoReg, 0x400E0E80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */ +#define REG_PIOA_DIFSR REG_ACCESS(WoReg, 0x400E0E84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */ +#define REG_PIOA_IFDGSR REG_ACCESS(RoReg, 0x400E0E88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOA_SCDR REG_ACCESS(RwReg, 0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ +#define REG_PIOA_PPDDR REG_ACCESS(WoReg, 0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ +#define REG_PIOA_PPDER REG_ACCESS(WoReg, 0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ +#define REG_PIOA_PPDSR REG_ACCESS(RoReg, 0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ +#define REG_PIOA_OWER REG_ACCESS(WoReg, 0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ +#define REG_PIOA_OWDR REG_ACCESS(WoReg, 0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ +#define REG_PIOA_OWSR REG_ACCESS(RoReg, 0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ +#define REG_PIOA_AIMER REG_ACCESS(WoReg, 0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ +#define REG_PIOA_AIMDR REG_ACCESS(WoReg, 0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */ +#define REG_PIOA_AIMMR REG_ACCESS(RoReg, 0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ +#define REG_PIOA_ESR REG_ACCESS(WoReg, 0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ +#define REG_PIOA_LSR REG_ACCESS(WoReg, 0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ +#define REG_PIOA_ELSR REG_ACCESS(RoReg, 0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ +#define REG_PIOA_FELLSR REG_ACCESS(WoReg, 0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */ +#define REG_PIOA_REHLSR REG_ACCESS(WoReg, 0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */ +#define REG_PIOA_FRLHSR REG_ACCESS(RoReg, 0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ +#define REG_PIOA_LOCKSR REG_ACCESS(RoReg, 0x400E0EE0U) /**< \brief (PIOA) Lock Status */ +#define REG_PIOA_WPMR REG_ACCESS(RwReg, 0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */ +#define REG_PIOA_WPSR REG_ACCESS(RoReg, 0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */ +#define REG_PIOA_SCHMITT REG_ACCESS(RwReg, 0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ +#define REG_PIOA_PCMR REG_ACCESS(RwReg, 0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */ +#define REG_PIOA_PCIER REG_ACCESS(WoReg, 0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */ +#define REG_PIOA_PCIDR REG_ACCESS(WoReg, 0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */ +#define REG_PIOA_PCIMR REG_ACCESS(RoReg, 0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */ +#define REG_PIOA_PCISR REG_ACCESS(RoReg, 0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */ +#define REG_PIOA_PCRHR REG_ACCESS(RoReg, 0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */ +/* ========== Register definition for PIOB peripheral ========== */ +#define REG_PIOB_PER REG_ACCESS(WoReg, 0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ +#define REG_PIOB_PDR REG_ACCESS(WoReg, 0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ +#define REG_PIOB_PSR REG_ACCESS(RoReg, 0x400E1008U) /**< \brief (PIOB) PIO Status Register */ +#define REG_PIOB_OER REG_ACCESS(WoReg, 0x400E1010U) /**< \brief (PIOB) Output Enable Register */ +#define REG_PIOB_ODR REG_ACCESS(WoReg, 0x400E1014U) /**< \brief (PIOB) Output Disable Register */ +#define REG_PIOB_OSR REG_ACCESS(RoReg, 0x400E1018U) /**< \brief (PIOB) Output Status Register */ +#define REG_PIOB_IFER REG_ACCESS(WoReg, 0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ +#define REG_PIOB_IFDR REG_ACCESS(WoReg, 0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ +#define REG_PIOB_IFSR REG_ACCESS(RoReg, 0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ +#define REG_PIOB_SODR REG_ACCESS(WoReg, 0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ +#define REG_PIOB_CODR REG_ACCESS(WoReg, 0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ +#define REG_PIOB_ODSR REG_ACCESS(RwReg, 0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ +#define REG_PIOB_PDSR REG_ACCESS(RoReg, 0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ +#define REG_PIOB_IER REG_ACCESS(WoReg, 0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ +#define REG_PIOB_IDR REG_ACCESS(WoReg, 0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ +#define REG_PIOB_IMR REG_ACCESS(RoReg, 0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ +#define REG_PIOB_ISR REG_ACCESS(RoReg, 0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ +#define REG_PIOB_MDER REG_ACCESS(WoReg, 0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ +#define REG_PIOB_MDDR REG_ACCESS(WoReg, 0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ +#define REG_PIOB_MDSR REG_ACCESS(RoReg, 0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ +#define REG_PIOB_PUDR REG_ACCESS(WoReg, 0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ +#define REG_PIOB_PUER REG_ACCESS(WoReg, 0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ +#define REG_PIOB_PUSR REG_ACCESS(RoReg, 0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ +#define REG_PIOB_ABCDSR REG_ACCESS(RwReg, 0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */ +#define REG_PIOB_SCIFSR REG_ACCESS(WoReg, 0x400E1080U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */ +#define REG_PIOB_DIFSR REG_ACCESS(WoReg, 0x400E1084U) /**< \brief (PIOB) Debouncing Input Filter Select Register */ +#define REG_PIOB_IFDGSR REG_ACCESS(RoReg, 0x400E1088U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOB_SCDR REG_ACCESS(RwReg, 0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ +#define REG_PIOB_PPDDR REG_ACCESS(WoReg, 0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */ +#define REG_PIOB_PPDER REG_ACCESS(WoReg, 0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */ +#define REG_PIOB_PPDSR REG_ACCESS(RoReg, 0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */ +#define REG_PIOB_OWER REG_ACCESS(WoReg, 0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ +#define REG_PIOB_OWDR REG_ACCESS(WoReg, 0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ +#define REG_PIOB_OWSR REG_ACCESS(RoReg, 0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ +#define REG_PIOB_AIMER REG_ACCESS(WoReg, 0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ +#define REG_PIOB_AIMDR REG_ACCESS(WoReg, 0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */ +#define REG_PIOB_AIMMR REG_ACCESS(RoReg, 0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ +#define REG_PIOB_ESR REG_ACCESS(WoReg, 0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ +#define REG_PIOB_LSR REG_ACCESS(WoReg, 0x400E10C4U) /**< \brief (PIOB) Level Select Register */ +#define REG_PIOB_ELSR REG_ACCESS(RoReg, 0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ +#define REG_PIOB_FELLSR REG_ACCESS(WoReg, 0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */ +#define REG_PIOB_REHLSR REG_ACCESS(WoReg, 0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */ +#define REG_PIOB_FRLHSR REG_ACCESS(RoReg, 0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ +#define REG_PIOB_LOCKSR REG_ACCESS(RoReg, 0x400E10E0U) /**< \brief (PIOB) Lock Status */ +#define REG_PIOB_WPMR REG_ACCESS(RwReg, 0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */ +#define REG_PIOB_WPSR REG_ACCESS(RoReg, 0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */ +#define REG_PIOB_SCHMITT REG_ACCESS(RwReg, 0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */ +#define REG_PIOB_PCMR REG_ACCESS(RwReg, 0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */ +#define REG_PIOB_PCIER REG_ACCESS(WoReg, 0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */ +#define REG_PIOB_PCIDR REG_ACCESS(WoReg, 0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */ +#define REG_PIOB_PCIMR REG_ACCESS(RoReg, 0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */ +#define REG_PIOB_PCISR REG_ACCESS(RoReg, 0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */ +#define REG_PIOB_PCRHR REG_ACCESS(RoReg, 0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */ +/* ========== Register definition for PIOC peripheral ========== */ +#define REG_PIOC_PER REG_ACCESS(WoReg, 0x400E1200U) /**< \brief (PIOC) PIO Enable Register */ +#define REG_PIOC_PDR REG_ACCESS(WoReg, 0x400E1204U) /**< \brief (PIOC) PIO Disable Register */ +#define REG_PIOC_PSR REG_ACCESS(RoReg, 0x400E1208U) /**< \brief (PIOC) PIO Status Register */ +#define REG_PIOC_OER REG_ACCESS(WoReg, 0x400E1210U) /**< \brief (PIOC) Output Enable Register */ +#define REG_PIOC_ODR REG_ACCESS(WoReg, 0x400E1214U) /**< \brief (PIOC) Output Disable Register */ +#define REG_PIOC_OSR REG_ACCESS(RoReg, 0x400E1218U) /**< \brief (PIOC) Output Status Register */ +#define REG_PIOC_IFER REG_ACCESS(WoReg, 0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ +#define REG_PIOC_IFDR REG_ACCESS(WoReg, 0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ +#define REG_PIOC_IFSR REG_ACCESS(RoReg, 0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */ +#define REG_PIOC_SODR REG_ACCESS(WoReg, 0x400E1230U) /**< \brief (PIOC) Set Output Data Register */ +#define REG_PIOC_CODR REG_ACCESS(WoReg, 0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */ +#define REG_PIOC_ODSR REG_ACCESS(RwReg, 0x400E1238U) /**< \brief (PIOC) Output Data Status Register */ +#define REG_PIOC_PDSR REG_ACCESS(RoReg, 0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */ +#define REG_PIOC_IER REG_ACCESS(WoReg, 0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */ +#define REG_PIOC_IDR REG_ACCESS(WoReg, 0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */ +#define REG_PIOC_IMR REG_ACCESS(RoReg, 0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */ +#define REG_PIOC_ISR REG_ACCESS(RoReg, 0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */ +#define REG_PIOC_MDER REG_ACCESS(WoReg, 0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */ +#define REG_PIOC_MDDR REG_ACCESS(WoReg, 0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */ +#define REG_PIOC_MDSR REG_ACCESS(RoReg, 0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */ +#define REG_PIOC_PUDR REG_ACCESS(WoReg, 0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */ +#define REG_PIOC_PUER REG_ACCESS(WoReg, 0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */ +#define REG_PIOC_PUSR REG_ACCESS(RoReg, 0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */ +#define REG_PIOC_ABCDSR REG_ACCESS(RwReg, 0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */ +#define REG_PIOC_SCIFSR REG_ACCESS(WoReg, 0x400E1280U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */ +#define REG_PIOC_DIFSR REG_ACCESS(WoReg, 0x400E1284U) /**< \brief (PIOC) Debouncing Input Filter Select Register */ +#define REG_PIOC_IFDGSR REG_ACCESS(RoReg, 0x400E1288U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOC_SCDR REG_ACCESS(RwReg, 0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ +#define REG_PIOC_PPDDR REG_ACCESS(WoReg, 0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */ +#define REG_PIOC_PPDER REG_ACCESS(WoReg, 0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */ +#define REG_PIOC_PPDSR REG_ACCESS(RoReg, 0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */ +#define REG_PIOC_OWER REG_ACCESS(WoReg, 0x400E12A0U) /**< \brief (PIOC) Output Write Enable */ +#define REG_PIOC_OWDR REG_ACCESS(WoReg, 0x400E12A4U) /**< \brief (PIOC) Output Write Disable */ +#define REG_PIOC_OWSR REG_ACCESS(RoReg, 0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */ +#define REG_PIOC_AIMER REG_ACCESS(WoReg, 0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ +#define REG_PIOC_AIMDR REG_ACCESS(WoReg, 0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */ +#define REG_PIOC_AIMMR REG_ACCESS(RoReg, 0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ +#define REG_PIOC_ESR REG_ACCESS(WoReg, 0x400E12C0U) /**< \brief (PIOC) Edge Select Register */ +#define REG_PIOC_LSR REG_ACCESS(WoReg, 0x400E12C4U) /**< \brief (PIOC) Level Select Register */ +#define REG_PIOC_ELSR REG_ACCESS(RoReg, 0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */ +#define REG_PIOC_FELLSR REG_ACCESS(WoReg, 0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */ +#define REG_PIOC_REHLSR REG_ACCESS(WoReg, 0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */ +#define REG_PIOC_FRLHSR REG_ACCESS(RoReg, 0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ +#define REG_PIOC_LOCKSR REG_ACCESS(RoReg, 0x400E12E0U) /**< \brief (PIOC) Lock Status */ +#define REG_PIOC_WPMR REG_ACCESS(RwReg, 0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */ +#define REG_PIOC_WPSR REG_ACCESS(RoReg, 0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */ +#define REG_PIOC_SCHMITT REG_ACCESS(RwReg, 0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */ +#define REG_PIOC_PCMR REG_ACCESS(RwReg, 0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */ +#define REG_PIOC_PCIER REG_ACCESS(WoReg, 0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */ +#define REG_PIOC_PCIDR REG_ACCESS(WoReg, 0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */ +#define REG_PIOC_PCIMR REG_ACCESS(RoReg, 0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */ +#define REG_PIOC_PCISR REG_ACCESS(RoReg, 0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */ +#define REG_PIOC_PCRHR REG_ACCESS(RoReg, 0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */ +/* ========== Register definition for RSTC peripheral ========== */ +#define REG_RSTC_CR REG_ACCESS(WoReg, 0x400E1400U) /**< \brief (RSTC) Control Register */ +#define REG_RSTC_SR REG_ACCESS(RoReg, 0x400E1404U) /**< \brief (RSTC) Status Register */ +#define REG_RSTC_MR REG_ACCESS(RwReg, 0x400E1408U) /**< \brief (RSTC) Mode Register */ +/* ========== Register definition for SUPC peripheral ========== */ +#define REG_SUPC_CR REG_ACCESS(WoReg, 0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */ +#define REG_SUPC_SMMR REG_ACCESS(RwReg, 0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ +#define REG_SUPC_MR REG_ACCESS(RwReg, 0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */ +#define REG_SUPC_WUMR REG_ACCESS(RwReg, 0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */ +#define REG_SUPC_WUIR REG_ACCESS(RwReg, 0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */ +#define REG_SUPC_SR REG_ACCESS(RoReg, 0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */ +/* ========== Register definition for RTT peripheral ========== */ +#define REG_RTT_MR REG_ACCESS(RwReg, 0x400E1430U) /**< \brief (RTT) Mode Register */ +#define REG_RTT_AR REG_ACCESS(RwReg, 0x400E1434U) /**< \brief (RTT) Alarm Register */ +#define REG_RTT_VR REG_ACCESS(RoReg, 0x400E1438U) /**< \brief (RTT) Value Register */ +#define REG_RTT_SR REG_ACCESS(RoReg, 0x400E143CU) /**< \brief (RTT) Status Register */ +/* ========== Register definition for WDT peripheral ========== */ +#define REG_WDT_CR REG_ACCESS(WoReg, 0x400E1450U) /**< \brief (WDT) Control Register */ +#define REG_WDT_MR REG_ACCESS(RwReg, 0x400E1454U) /**< \brief (WDT) Mode Register */ +#define REG_WDT_SR REG_ACCESS(RoReg, 0x400E1458U) /**< \brief (WDT) Status Register */ +/* ========== Register definition for RTC peripheral ========== */ +#define REG_RTC_CR REG_ACCESS(RwReg, 0x400E1460U) /**< \brief (RTC) Control Register */ +#define REG_RTC_MR REG_ACCESS(RwReg, 0x400E1464U) /**< \brief (RTC) Mode Register */ +#define REG_RTC_TIMR REG_ACCESS(RwReg, 0x400E1468U) /**< \brief (RTC) Time Register */ +#define REG_RTC_CALR REG_ACCESS(RwReg, 0x400E146CU) /**< \brief (RTC) Calendar Register */ +#define REG_RTC_TIMALR REG_ACCESS(RwReg, 0x400E1470U) /**< \brief (RTC) Time Alarm Register */ +#define REG_RTC_CALALR REG_ACCESS(RwReg, 0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */ +#define REG_RTC_SR REG_ACCESS(RoReg, 0x400E1478U) /**< \brief (RTC) Status Register */ +#define REG_RTC_SCCR REG_ACCESS(WoReg, 0x400E147CU) /**< \brief (RTC) Status Clear Command Register */ +#define REG_RTC_IER REG_ACCESS(WoReg, 0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */ +#define REG_RTC_IDR REG_ACCESS(WoReg, 0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */ +#define REG_RTC_IMR REG_ACCESS(RoReg, 0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */ +#define REG_RTC_VER REG_ACCESS(RoReg, 0x400E148CU) /**< \brief (RTC) Valid Entry Register */ +/* ========== Register definition for GPBR peripheral ========== */ +#define REG_GPBR_GPBR0 REG_ACCESS(RwReg, 0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register 0 */ +#define REG_GPBR_GPBR1 REG_ACCESS(RwReg, 0x400E1494U) /**< \brief (GPBR) General Purpose Backup Register 1 */ +#define REG_GPBR_GPBR2 REG_ACCESS(RwReg, 0x400E1498U) /**< \brief (GPBR) General Purpose Backup Register 2 */ +#define REG_GPBR_GPBR3 REG_ACCESS(RwReg, 0x400E149CU) /**< \brief (GPBR) General Purpose Backup Register 3 */ +/*@}*/ + +/* ***************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR AT91SAM3S */ +/* ***************************************************************************** */ +/** \addtogroup AT91SAM3S_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Flash Controller (EFC) */ +#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */ +#define ID_SMC (10) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (14) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (15) /**< \brief USART 1 (USART1) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */ +#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */ +#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controler (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */ +#define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_UDP (34) /**< \brief USB Device Port (UDP) */ +/*@}*/ + +/* ***************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR AT91SAM3S */ +/* ***************************************************************************** */ +/** \addtogroup AT91SAM3S_base Peripheral Base Address Definitions */ +/*@{*/ + +#define HSMCI CAST(Hsmci , 0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define PDC_HSMCI CAST(Pdc , 0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ +#define SSC CAST(Ssc , 0x40004000U) /**< \brief (SSC ) Base Address */ +#define PDC_SSC CAST(Pdc , 0x40004100U) /**< \brief (PDC_SSC ) Base Address */ +#define SPI CAST(Spi , 0x40008000U) /**< \brief (SPI ) Base Address */ +#define PDC_SPI CAST(Pdc , 0x40008100U) /**< \brief (PDC_SPI ) Base Address */ +#define TC0 CAST(Tc , 0x40010000U) /**< \brief (TC0 ) Base Address */ +#define TC1 CAST(Tc , 0x40014000U) /**< \brief (TC1 ) Base Address */ +#define TWI0 CAST(Twi , 0x40018000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 CAST(Pdc , 0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 CAST(Twi , 0x4001C000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 CAST(Pdc , 0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM CAST(Pwm , 0x40020000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM CAST(Pdc , 0x40020100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 CAST(Usart , 0x40024000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 CAST(Pdc , 0x40024100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 CAST(Usart , 0x40028000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 CAST(Pdc , 0x40028100U) /**< \brief (PDC_USART1) Base Address */ +#define UDP CAST(Udp , 0x40034000U) /**< \brief (UDP ) Base Address */ +#define ADC CAST(Adc , 0x40038000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC CAST(Pdc , 0x40038100U) /**< \brief (PDC_ADC ) Base Address */ +#define DACC CAST(Dacc , 0x4003C000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC CAST(Pdc , 0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ +#define ACC CAST(Acc , 0x40040000U) /**< \brief (ACC ) Base Address */ +#define CRCCU CAST(Crccu , 0x40044000U) /**< \brief (CRCCU ) Base Address */ +#define SMC CAST(Smc , 0x400E0000U) /**< \brief (SMC ) Base Address */ +#define MATRIX CAST(Matrix , 0x400E0200U) /**< \brief (MATRIX ) Base Address */ +#define PMC CAST(Pmc , 0x400E0400U) /**< \brief (PMC ) Base Address */ +#define UART0 CAST(Uart , 0x400E0600U) /**< \brief (UART0 ) Base Address */ +#define PDC_UART0 CAST(Pdc , 0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ +#define CHIPID CAST(Chipid , 0x400E0740U) /**< \brief (CHIPID ) Base Address */ +#define UART1 CAST(Uart , 0x400E0800U) /**< \brief (UART1 ) Base Address */ +#define PDC_UART1 CAST(Pdc , 0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ +#define EFC CAST(Efc , 0x400E0A00U) /**< \brief (EFC ) Base Address */ +#define PIOA CAST(Pio , 0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB CAST(Pio , 0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC CAST(Pio , 0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define RSTC CAST(Rstc , 0x400E1400U) /**< \brief (RSTC ) Base Address */ +#define SUPC CAST(Supc , 0x400E1410U) /**< \brief (SUPC ) Base Address */ +#define RTT CAST(Rtt , 0x400E1430U) /**< \brief (RTT ) Base Address */ +#define WDT CAST(Wdt , 0x400E1450U) /**< \brief (WDT ) Base Address */ +#define RTC CAST(Rtc , 0x400E1460U) /**< \brief (RTC ) Base Address */ +#define GPBR CAST(Gpbr , 0x400E1490U) /**< \brief (GPBR ) Base Address */ + +// indices for three pio structures +#define iPIOA 0 +#define iPIOB 1 +#define iPIOC 2 +/*@}*/ + +/* ***************************************************************************** */ +/* PIO DEFINITIONS FOR AT91SAM3S */ +/* ***************************************************************************** */ +/** \addtogroup AT91SAM3S_pio Peripheral Pio Definitions */ +/*@{*/ + +#define PIO_PA0 (1 << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1 << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1 << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1 << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1 << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1 << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1 << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1 << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1 << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1 << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1 << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1 << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1 << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1 << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1 << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1 << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1 << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1 << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1 << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1 << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1 << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1 << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1 << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1 << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1 << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1 << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1 << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1 << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1 << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1 << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1 << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1 << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1 << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1 << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1 << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1 << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1 << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1 << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1 << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1 << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1 << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1 << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB10 (1 << 10) /**< \brief Pin Controlled by PB10 */ +#define PIO_PB11 (1 << 11) /**< \brief Pin Controlled by PB11 */ +#define PIO_PB12 (1 << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1 << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PB14 (1 << 14) /**< \brief Pin Controlled by PB14 */ +#define PIO_PC0 (1 << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1 << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1 << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1 << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1 << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1 << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1 << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1 << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1 << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1 << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1 << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1 << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1 << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1 << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1 << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1 << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1 << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1 << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1 << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1 << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1 << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1 << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1 << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1 << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1 << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1 << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1 << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1 << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1 << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1 << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1 << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1 << 31) /**< \brief Pin Controlled by PC31 */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1 << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA29C_MCCK (1 << 29) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1 << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1 << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1 << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1 << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA18A_RD (1 << 18) /**< \brief Ssc signal: RD */ +#define PIO_PA20A_RF (1 << 20) /**< \brief Ssc signal: RF */ +#define PIO_PA19A_RK (1 << 19) /**< \brief Ssc signal: RK */ +#define PIO_PA17A_TD (1 << 17) /**< \brief Ssc signal: TD */ +#define PIO_PA15A_TF (1 << 15) /**< \brief Ssc signal: TF */ +#define PIO_PA16A_TK (1 << 16) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for SPI peripheral ========== */ +#define PIO_PA12A_MISO (1 << 12) /**< \brief Spi signal: MISO */ +#define PIO_PA13A_MOSI (1 << 13) /**< \brief Spi signal: MOSI */ +#define PIO_PA11A_NPCS0 (1 << 11) /**< \brief Spi signal: NPCS0 */ +#define PIO_PA31A_NPCS1 (1 << 31) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA9B_NPCS1 (1 << 9) /**< \brief Spi signal: NPCS1 */ +#define PIO_PB14A_NPCS1 (1 << 14) /**< \brief Spi signal: NPCS1 */ +#define PIO_PC4B_NPCS1 (1 << 4) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA10B_NPCS2 (1 << 10) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA30B_NPCS2 (1 << 30) /**< \brief Spi signal: NPCS2 */ +#define PIO_PB2B_NPCS2 (1 << 2) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA22B_NPCS3 (1 << 22) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA3B_NPCS3 (1 << 3) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA5B_NPCS3 (1 << 5) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA14A_SPCK (1 << 14) /**< \brief Spi signal: SPCK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1 << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1 << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1 << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1 << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1 << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1 << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1 << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1 << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1 << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1 << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1 << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1 << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1 << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1 << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1 << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1 << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1 << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1 << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TWI0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1 << 4) /**< \brief Twi0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1 << 3) /**< \brief Twi0 signal: TWD0 */ +/* ========== Pio definition for TWI1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1 << 5) /**< \brief Twi1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1 << 4) /**< \brief Twi1 signal: TWD1 */ +/* ========== Pio definition for PWM peripheral ========== */ +#define PIO_PA9C_PWMFI0 (1 << 9) /**< \brief Pwm signal: PWMFI0 */ +#define PIO_PA0A_PWMH0 (1 << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA11B_PWMH0 (1 << 11) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA23B_PWMH0 (1 << 23) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PB0A_PWMH0 (1 << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PC18B_PWMH0 (1 << 18) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA1A_PWMH1 (1 << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA12B_PWMH1 (1 << 12) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA24B_PWMH1 (1 << 24) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PB1A_PWMH1 (1 << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PC19B_PWMH1 (1 << 19) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA13B_PWMH2 (1 << 13) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA2A_PWMH2 (1 << 2) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA25B_PWMH2 (1 << 25) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PB4B_PWMH2 (1 << 4) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PC20B_PWMH2 (1 << 20) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA14B_PWMH3 (1 << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA17C_PWMH3 (1 << 17) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA7B_PWMH3 (1 << 7) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PB14B_PWMH3 (1 << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC21B_PWMH3 (1 << 21) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA19B_PWML0 (1 << 19) /**< \brief Pwm signal: PWML0 */ +#define PIO_PB5B_PWML0 (1 << 5) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC0B_PWML0 (1 << 0) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC13B_PWML0 (1 << 13) /**< \brief Pwm signal: PWML0 */ +#define PIO_PA20B_PWML1 (1 << 20) /**< \brief Pwm signal: PWML1 */ +#define PIO_PB12A_PWML1 (1 << 12) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC1B_PWML1 (1 << 1) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC15B_PWML1 (1 << 15) /**< \brief Pwm signal: PWML1 */ +#define PIO_PA16C_PWML2 (1 << 16) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA30A_PWML2 (1 << 30) /**< \brief Pwm signal: PWML2 */ +#define PIO_PB13A_PWML2 (1 << 13) /**< \brief Pwm signal: PWML2 */ +#define PIO_PC2B_PWML2 (1 << 2) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA15C_PWML3 (1 << 15) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC22B_PWML3 (1 << 22) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC3B_PWML3 (1 << 3) /**< \brief Pwm signal: PWML3 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PA8A_CTS0 (1 << 8) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PA7A_RTS0 (1 << 7) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PA5A_RXD0 (1 << 5) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PA2B_SCK0 (1 << 2) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PA6A_TXD0 (1 << 6) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1 << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1 << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1 << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1 << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA29A_RI1 (1 << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1 << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1 << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1 << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PA22A_TXD1 (1 << 22) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for ADC peripheral ========== */ +#define PIO_PA17X1_AD0 (1 << 17) /**< \brief Adc signal: AD0 */ +#define PIO_PA18X1_AD1 (1 << 18) /**< \brief Adc signal: AD1 */ +#define PIO_PC13X1_AD10 (1 << 13) /**< \brief Adc signal: AD10 */ +#define PIO_PC15X1_AD11 (1 << 15) /**< \brief Adc signal: AD11 */ +#define PIO_PC12X1_AD12 (1 << 12) /**< \brief Adc signal: AD12 */ +#define PIO_PC29X1_AD13 (1 << 29) /**< \brief Adc signal: AD13 */ +#define PIO_PC30X1_AD14 (1 << 30) /**< \brief Adc signal: AD14 */ +#define PIO_PA19X1_AD2 (1 << 19) /**< \brief Adc signal: AD2 */ +#define PIO_PA20X1_AD3 (1 << 20) /**< \brief Adc signal: AD3 */ +#define PIO_PB0X1_AD4 (1 << 0) /**< \brief Adc signal: AD4 */ +#define PIO_PB1X1_AD5 (1 << 1) /**< \brief Adc signal: AD5 */ +#define PIO_PB2X1_AD6 (1 << 2) /**< \brief Adc signal: AD6 */ +#define PIO_PB3X1_AD7 (1 << 3) /**< \brief Adc signal: AD7 */ +#define PIO_PA21X1_AD8 (1 << 21) /**< \brief Adc signal: AD8 */ +#define PIO_PA22X1_AD9 (1 << 22) /**< \brief Adc signal: AD9 */ +#define PIO_PA8B_ADTRG (1 << 8) /**< \brief Adc signal: ADTRG */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1 << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PB14X1_DAC1 (1 << 14) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1 << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1 << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1 << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1 << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1 << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA18B_PCK2 (1 << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1 << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1 << 3) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1 << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1 << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PB2A_URXD1 (1 << 2) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PB3A_UTXD1 (1 << 3) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA24X1_PIODC0 (1 << 24) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA25X1_PIODC1 (1 << 25) /**< \brief Pioa signal: PIODC1 */ +#define PIO_PA26X1_PIODC2 (1 << 26) /**< \brief Pioa signal: PIODC2 */ +#define PIO_PA27X1_PIODC3 (1 << 27) /**< \brief Pioa signal: PIODC3 */ +#define PIO_PA28X1_PIODC4 (1 << 28) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA29X1_PIODC5 (1 << 29) /**< \brief Pioa signal: PIODC5 */ +#define PIO_PA30X1_PIODC6 (1 << 30) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA31X1_PIODC7 (1 << 31) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA23X1_PIODCCLK (1 << 23) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA15X1_PIODCEN1 (1 << 15) /**< \brief Pioa signal: PIODCEN1 */ +#define PIO_PA16X1_PIODCEN2 (1 << 16) /**< \brief Pioa signal: PIODCEN2 */ +/*@}*/ + +/* ***************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR AT91SAM3S */ +/* ***************************************************************************** */ + +#define AT91C_IRAM (0x20000000) /**< Internal RAM base address */ +#define AT91C_IFLASH (0x00400000) /**< Internal Flash base address */ +#define AT91C_IROM (0x00800000) /**< Internal ROM base address */ +#define AT91C_IRAM (0x20000000) /**< Internal RAM base address */ +#define AT91C_EBI_CS0 (0x60000000) /**< EBI Chip Select 0 base address */ +#define AT91C_EBI_CS1 (0x61000000) /**< EBI Chip Select 1 base address */ +#define AT91C_EBI_CS2 (0x62000000) /**< EBI Chip Select 2 base address */ +#define AT91C_EBI_CS3 (0x63000000) /**< EBI Chip Select 3 base address */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* AT91SAM3S_H */ diff --git a/radio/bootloader/include/MSD.h b/radio/bootloader/include/MSD.h new file mode 100644 index 000000000..23a934d35 --- /dev/null +++ b/radio/bootloader/include/MSD.h @@ -0,0 +1,233 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// !Purpose +/// +/// Mass Storage class definitions. +/// +/// See +/// - +/// USB Mass Storage Class Spec. Overview +/// - +/// USB Mass Storage Class Bulk-Only Transport +/// +/// !Usage +/// +/// -# Uses "MSD Requests" to check incoming requests from USB Host. +/// -# Uses "MSD Subclass Codes" and "MSD Protocol Codes" to fill %device +/// interface descriptors for a MSD %device. +/// -# Handle the incoming Bulk data with "MSD CBW Definitions" and MSCbw +/// structure. +/// -# Prepare the outgoing Bulk data with "MSD CSW Definitions" and MSCsw +/// structure. +//------------------------------------------------------------------------------ + +#ifndef MSD_H +#define MSD_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "MSD Requests" +/// This page lists MSD-specific requests ( Actually for Bulk-only protocol ). +/// +/// !Requests +/// - MSD_BULK_ONLY_RESET +/// - MSD_GET_MAX_LUN + +/// Reset the mass storage %device and its associated interface. +#define MSD_BULK_ONLY_RESET 0xFF +/// Return the maximum LUN number supported by the %device. +#define MSD_GET_MAX_LUN 0xFE +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "MSD Subclass Codes" +/// This page lists the Subclass Codes for bInterfaceSubClass field. +/// (Table 2.1, USB Mass Storage Class Spec. Overview) +/// +/// !SubClasses +/// - MSD_SUBCLASS_RBC +/// - MSD_SUBCLASS_SFF_MCC +/// - MSD_SUBCLASS_QIC +/// - MSD_SUBCLASS_UFI +/// - MSD_SUBCLASS_SFF +/// - MSD_SUBCLASS_SCSI + +/// Reduced Block Commands (RBC) T10 +#define MSD_SUBCLASS_RBC 0x01 +/// C/DVD devices +#define MSD_SUBCLASS_SFF_MCC 0x02 +/// Tape device +#define MSD_SUBCLASS_QIC 0x03 +/// Floppy disk drive (FDD) device +#define MSD_SUBCLASS_UFI 0x04 +/// Floppy disk drive (FDD) device +#define MSD_SUBCLASS_SFF 0x05 +/// SCSI transparent command set +#define MSD_SUBCLASS_SCSI 0x06 +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +/// \page "MSD Protocol Codes" +/// This page lists the Transport Protocol codes for MSD. +/// (Table 3.1, USB Mass Storage Class Spec. Overview) +/// +/// !Protocols +/// - MSD_PROTOCOL_CBI_COMPLETION +/// - MSD_PROTOCOL_CBI +/// - MSD_PROTOCOL_BULK_ONLY + +/// Control/Bulk/Interrupt (CBI) Transport (with command complete interrupt) +#define MSD_PROTOCOL_CBI_COMPLETION 0x00 +/// Control/Bulk/Interrupt (CBI) Transport (no command complete interrupt) +#define MSD_PROTOCOL_CBI 0x01 +/// Bulk-Only Transport +#define MSD_PROTOCOL_BULK_ONLY 0x50 +//------------------------------------------------------------------------------ + +/// Test unit control: +#define CTRL_NOT_READY 0x00 +#define CTRL_GOOD 0x01 +#define CTRL_BUSY 0x02 + +//------------------------------------------------------------------------------ +/// \page "MSD CBW Definitions" +/// This page lists the Command Block Wrapper (CBW) definitions. +/// +/// !Constants +/// - MSD_CBW_SIZE +/// - MSD_CBW_SIGNATURE +/// +/// !Fields +/// - MSD_CBW_DEVICE_TO_HOST + +/// Command Block Wrapper Size +#define MSD_CBW_SIZE 31 +/// 'USBC' 0x43425355 +#define MSD_CBW_SIGNATURE 0x43425355 + +/// CBW bmCBWFlags field +#define MSD_CBW_DEVICE_TO_HOST (1 << 7) +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "MSD CSW Definitions" +/// This page lists the Command Status Wrapper (CSW) definitions. +/// +/// !Constants +/// - MSD_CSW_SIZE +/// - MSD_CSW_SIGNATURE +/// +/// !Command Block Status Values +/// (Table 5.3 , USB Mass Storage Class Bulk-Only Transport) +/// - MSD_CSW_COMMAND_PASSED +/// - MSD_CSW_COMMAND_FAILED +/// - MSD_CSW_PHASE_ERROR + +/// Command Status Wrapper Size +#define MSD_CSW_SIZE 13 +/// 'USBS' 0x53425355 +#define MSD_CSW_SIGNATURE 0x53425355 + +/// Command Passed (good status) +#define MSD_CSW_COMMAND_PASSED 0 +/// Command Failed +#define MSD_CSW_COMMAND_FAILED 1 +/// Phase Error +#define MSD_CSW_PHASE_ERROR 2 +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Structures +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Command Block Wrapper (CBW), +/// See Table 5.1, USB Mass Storage Class Bulk-Only Transport. +/// +/// The CBW shall start on a packet boundary and shall end as a +/// short packet with exactly 31 (1Fh) bytes transferred. +//------------------------------------------------------------------------------ +typedef struct { + + /// 'USBC' 0x43425355 (little endian) + unsigned int dCBWSignature; + /// Must be the same as dCSWTag + unsigned int dCBWTag; + /// Number of bytes transfer + unsigned int dCBWDataTransferLength; + /// Indicates the directin of the transfer: + /// 0x80=IN=device-to-host, + /// 0x00=OUT=host-to-device + unsigned char bmCBWFlags; + /// bits 0->3: bCBWLUN + unsigned char bCBWLUN :4, + bReserved1:4; /// reserved + /// bits 0->4: bCBWCBLength + unsigned char bCBWCBLength:5, + bReserved2 :3; /// reserved + /// Command block + unsigned char pCommand[16]; + +} MSCbw; + +//------------------------------------------------------------------------------ +/// Command Status Wrapper (CSW), +/// See Table 5.2, USB Mass Storage Class Bulk-Only Transport. +//------------------------------------------------------------------------------ +typedef struct +{ + /// 'USBS' 0x53425355 (little endian) + unsigned int dCSWSignature; + /// Must be the same as dCBWTag + unsigned int dCSWTag; + /// For Data-Out the device shall report in the dCSWDataResidue the + /// difference between the amount of data expected as stated in the + /// dCBWDataTransferLength, and the actual amount of data processed by + /// the device. For Data-In the device shall report in the dCSWDataResidue + /// the difference between the amount of data expected as stated in the + /// dCBWDataTransferLength and the actual amount of relevant data sent by + /// the device. The dCSWDataResidue shall not exceed the value sent in the + /// dCBWDataTransferLength. + unsigned int dCSWDataResidue; + /// Indicates the success or failure of the command. + unsigned char bCSWStatus; + +} MSCsw; + +#endif //#ifndef MSD_H + diff --git a/radio/bootloader/include/MSDDriver.h b/radio/bootloader/include/MSDDriver.h new file mode 100644 index 000000000..30e6b087c --- /dev/null +++ b/radio/bootloader/include/MSDDriver.h @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// !Purpose +/// +/// Mass storage %device driver implementation. +/// +/// !Usage +/// +/// -# Enable and setup USB related pins (see pio & board.h). +/// -# Configure the memory interfaces used for Mass Storage LUNs +/// (see memories, MSDLun.h). +/// -# Configure the USB MSD %driver using MSDDriver_Initialize. +/// -# Invoke MSDDriver_StateMachine in main loop to handle all Mass Storage +/// operations. +//------------------------------------------------------------------------------ + +#ifndef MSDDRIVER_H +#define MSDDRIVER_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "MSD.h" +#include "MSDLun.h" +// #include + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +extern void MSDDriver_Initialize(MSDLun *luns, unsigned char numLuns); + +extern void MSDDriver_RequestHandler(const USBGenericRequest *request); + +extern void MSDDriver_StateMachine(void); + +extern void MSDDriver_RemoteWakeUp(void); + +extern void MSDDriver_DataCallback(unsigned char isRead, + unsigned int dataLength, + unsigned int nullCnt, + unsigned int fullCnt); + +#endif // #ifndef MSDDRIVER_H + diff --git a/radio/bootloader/include/MSDLun.h b/radio/bootloader/include/MSDLun.h new file mode 100644 index 000000000..799775541 --- /dev/null +++ b/radio/bootloader/include/MSDLun.h @@ -0,0 +1,161 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// !Purpose +/// +/// Logical Unit Number (LUN) used by the Mass Storage driver and the SCSI +/// protocol. Represents a logical hard-drive. +/// +/// !Usage +/// -# Initialize Memory related pins (see pio & board.h). +/// -# Initialize a Media instance for the LUN (see memories). +/// -# Initlalize the LUN with LUN_Init, and link to the initialized Media. +/// -# To read data from the LUN linked media, uses LUN_Read. +/// -# To write data to the LUN linked media, uses LUN_Write. +/// -# To unlink the media, uses LUN_Eject. +//------------------------------------------------------------------------------ + +#ifndef MSDLUN_H +#define MSDLUN_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "SBC.h" +#include +#include +#include + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +/// LUN RC: success +#define LUN_STATUS_SUCCESS 0x00 +/// LUN RC: error +#define LUN_STATUS_ERROR 0x02 + +/// Media of LUN is removed +#define LUN_NOT_PRESENT 0x00 +/// LUN is ejected by host +#define LUN_EJECTED 0x01 +/// Media of LUN is changed +#define LUN_CHANGED 0x10 +/// LUN Not Ready to Ready transition +#define LUN_TRANS_READY LUN_CHANGED +/// Media of LUN is ready +#define LUN_READY 0x11 + +//------------------------------------------------------------------------------ +// Structures +//------------------------------------------------------------------------------ + +/// LUN structure +typedef struct { + + /// Pointer to a SBCInquiryData instance. + SBCInquiryData *inquiryData; + /// Fifo for USB transfer, must be assigned. + MSDIOFifo ioFifo; + /// Pointer to Media instance for the LUN. + Media *media; + /// Pointer to a Monitor Function to analyze the flow of LUN. + /// \param flowDirection 1 - device to host (READ10) + /// 0 - host to device (WRITE10) + /// \param dataLength Length of data transferred in bytes. + /// \param fifoNullCount Times that FIFO is NULL to wait + /// \param fifoFullCount Times that FIFO is filled to wait + void (*dataMonitor)(unsigned char flowDirection, + unsigned int dataLength, + unsigned int fifoNullCount, + unsigned int fifoFullCount); + /// The start position of the media (blocks) allocated to the LUN. + unsigned int baseAddress; + /// The size of the media (blocks) allocated to the LUN. + unsigned int size; + /// Sector size of the media in number of media blocks + unsigned short blockSize; + /// The LUN can be readonly even the media is writable +#ifdef __cplusplus + unsigned char protectd; +#else + unsigned char protected; +#endif + + /// The LUN status (Ejected/Changed/) + unsigned char status; + + /// Data for the RequestSense command. + SBCRequestSenseData requestSenseData; + /// Data for the ReadCapacity command. + SBCReadCapacity10Data readCapacityData; + +} MSDLun; + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +extern void LUN_Init(MSDLun *lun, + Media *media, + unsigned char *ioBuffer, + unsigned int ioBufferSize, + unsigned int baseAddress, + unsigned int size, + unsigned short blockSize, +#ifdef __cplusplus + unsigned char protectd, +#else + unsigned char protected, +#endif + void (*dataMonitor)(unsigned char flowDirection, + unsigned int dataLength, + unsigned int fifoNullCount, + unsigned int fifoFullCount)); + +extern unsigned char LUN_Eject(MSDLun *lun); + +extern unsigned char LUN_Write(MSDLun *lun, + unsigned int blockAddress, + void *data, + unsigned int length, + TransferCallback callback, + void *argument); + +extern unsigned char LUN_Read(MSDLun *lun, + unsigned int blockAddress, + void *data, + unsigned int length, + TransferCallback callback, + void *argument); + +#endif //#ifndef MSDLUN_H + diff --git a/radio/bootloader/include/Media.h b/radio/bootloader/include/Media.h new file mode 100644 index 000000000..ef0a22586 --- /dev/null +++ b/radio/bootloader/include/Media.h @@ -0,0 +1,288 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// !Purpose +/// +/// Generic Media type, which provides transparent access to all types of +/// memories. +/// +/// \note The physical or HW related media operations (physical device +/// connection & protection detecting, PIO configurations and interface +/// driver initialization) are excluded. +/// +/// !Usage +/// -# Do PIO initialization for peripheral interfaces. +/// -# Initialize peripheral interface driver & device driver. +/// -# Initialize specific media interface and link to this initialized driver. +/// +//------------------------------------------------------------------------------ + +#ifndef MEDIA_H +#define MEDIA_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//! \brief Operation result code returned by media methods +#define MED_STATUS_SUCCESS 0x00 +#define MED_STATUS_ERROR 0x01 +#define MED_STATUS_BUSY 0x02 +#define MED_STATUS_PROTECTED 0x04 + +//! \brief Media statuses +#define MED_STATE_READY 0x00 /// Media is ready for access +#define MED_STATE_BUSY 0x01 /// Media is busy + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ +typedef struct _Media Media; + +typedef void (*MediaCallback)(void *argument, + unsigned char status, + unsigned int transferred, + unsigned int remaining); + +typedef unsigned char (*Media_write)(Media *media, + unsigned int address, + void *data, + unsigned int length, + MediaCallback callback, + void *argument); + +typedef unsigned char (*Media_read)(Media *media, + unsigned int address, + void *data, + unsigned int length, + MediaCallback callback, + void *argument); + +typedef unsigned char (*Media_cancelIo)(Media *media); + +typedef unsigned char (*Media_lock)(Media *media, + unsigned int start, + unsigned int end, + unsigned int *pActualStart, + unsigned int *pActualEnd); + +typedef unsigned char (*Media_unlock)(Media *media, + unsigned int start, + unsigned int end, + unsigned int *pActualStart, + unsigned int *pActualEnd); + +typedef unsigned char (*Media_ioctl)(Media *media, + unsigned char ctrl, + void *buff); + +typedef unsigned char (*Media_flush)(Media *media); + +typedef void (*Media_handler)(Media *media); + +//! \brief Media transfer +//! \see TransferCallback +typedef struct { + + void *data; //!< Pointer to the data buffer + unsigned int address; //!< Address where to read/write the data + unsigned int length; //!< Size of the data to read/write + MediaCallback callback; //!< Callback to invoke when the transfer done + void *argument; //!< Callback argument + +} MEDTransfer; + +//! \brief Media object +//! \see MEDTransfer +struct _Media { + + Media_write write; //!< Write method + Media_read read; //!< Read method + Media_cancelIo cancelIo; //!< Cancel pending IO method + Media_lock lock; //!< lock method if possible + Media_unlock unlock; //!< unlock method if possible + Media_flush flush; //!< Flush method + Media_handler handler; //!< Interrupt handler + unsigned int blockSize; //!< Block size in bytes (1, 512, 1K, 2K ...) + unsigned int baseAddress; //!< Base address of media in number of blocks + unsigned int size; //!< Size of media in number of blocks + MEDTransfer transfer; //!< Current transfer operation + void *interface; //!< Pointer to the physical interface used + unsigned char bReserved:4, + mappedRD:1, //!< Mapped to memory space to read + mappedWR:1, //!< Mapped to memory space to write +#ifdef __cplusplus + protectd:1, //!< Protected media? +#else + protected:1, //!< Protected media? +#endif + removable:1; //!< Removable/Fixed media? + unsigned char state; //!< Status of media + unsigned short reserved; +}; + +/// Available medias. +extern Media medias[]; + +/// Number of medias which are effectively used. +/// Defined by Media, shared usage by USB MSD & FS ... +extern unsigned int numMedias; + +//------------------------------------------------------------------------------ +// Inline Functions +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +//! \brief Writes data on a media +//! \param media Pointer to a Media instance +//! \param address Address at which to write +//! \param data Pointer to the data to write +//! \param length Size of the data buffer +//! \param callback Optional pointer to a callback function to invoke when +//! the write operation terminates +//! \param argument Optional argument for the callback function +//! \return Operation result code +//! \see TransferCallback +//------------------------------------------------------------------------------ +static inline unsigned char MED_Write(Media *media, + unsigned int address, + void *data, + unsigned int length, + MediaCallback callback, + void *argument) +{ + return media->write(media, address, data, length, callback, argument); +} + +//------------------------------------------------------------------------------ +//! \brief Reads a specified amount of data from a media +//! \param media Pointer to a Media instance +//! \param address Address of the data to read +//! \param data Pointer to the buffer in which to store the retrieved +//! data +//! \param length Length of the buffer +//! \param callback Optional pointer to a callback function to invoke when +//! the operation is finished +//! \param argument Optional pointer to an argument for the callback +//! \return Operation result code +//! \see TransferCallback +//------------------------------------------------------------------------------ +static inline unsigned char MED_Read(Media *media, + unsigned int address, + void *data, + unsigned int length, + MediaCallback callback, + void *argument) +{ + return media->read(media, address, data, length, callback, argument); +} + +//------------------------------------------------------------------------------ +//! \brief Locks all the regions in the given address range. +//! \param media Pointer to a Media instance +/// \param start Start address of lock range. +/// \param end End address of lock range. +/// \param pActualStart Start address of the actual lock range (optional). +/// \param pActualEnd End address of the actual lock range (optional). +/// \return 0 if successful; otherwise returns an error code. +//------------------------------------------------------------------------------ +static inline unsigned char MED_Lock(Media *media, + unsigned int start, + unsigned int end, + unsigned int *pActualStart, + unsigned int *pActualEnd) +{ + if( media->lock ) { + return media->lock(media, start, end, pActualStart, pActualEnd); + } + else { + return MED_STATUS_SUCCESS; + } +} + +//------------------------------------------------------------------------------ +//! \brief Unlocks all the regions in the given address range +//! \param media Pointer to a Media instance +/// \param start Start address of unlock range. +/// \param end End address of unlock range. +/// \param pActualStart Start address of the actual unlock range (optional). +/// \param pActualEnd End address of the actual unlock range (optional). +/// \return 0 if successful; otherwise returns an error code. +//------------------------------------------------------------------------------ +static inline unsigned char MED_Unlock(Media *media, + unsigned int start, + unsigned int end, + unsigned int *pActualStart, + unsigned int *pActualEnd) +{ + if( media->unlock ) { + return media->unlock(media, start, end, pActualStart, pActualEnd); + } + else { + return MED_STATUS_SUCCESS; + } +} + +//------------------------------------------------------------------------------ +//! \brief +//! \param media Pointer to the Media instance to use +//------------------------------------------------------------------------------ +static inline unsigned char MED_Flush(Media *media) +{ + if (media->flush) { + + return media->flush(media); + } + else { + + return MED_STATUS_SUCCESS; + } +} + +//------------------------------------------------------------------------------ +//! \brief Invokes the interrupt handler of the specified media +//! \param media Pointer to the Media instance to use +//------------------------------------------------------------------------------ +static inline void MED_Handler(Media *media) +{ + if (media->handler) { + + media->handler(media); + } +} + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern void MED_HandleAll(Media *medias, unsigned char numMedias); + +#endif // _MEDIA_H + diff --git a/radio/bootloader/include/SBC.h b/radio/bootloader/include/SBC.h new file mode 100644 index 000000000..3c3f93c69 --- /dev/null +++ b/radio/bootloader/include/SBC.h @@ -0,0 +1,653 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// !Purpose +/// +/// SCSI definitions. +/// +/// !Usage +/// +/// -# After command block received, Access and decode the SCSI command block +/// with SBCCommand structure. +//------------------------------------------------------------------------------ + +#ifndef SBC_H +#define SBC_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SBC Operation Codes" +/// This page lists operation codes of commands described in the SBC-3 +/// standard. +/// +/// \note That most commands are actually defined in other standards, +/// like SPC-4. Optional commands are not included here. +/// +/// \see sbc3r07.pdf - Section 5.1 - Table 12 +/// \see spc4r06.pdf +/// \see SBCCommand +/// +/// !Codes +/// - SBC_INQUIRY +/// - SBC_READ_10 +/// - SBC_READ_CAPACITY_10 +/// - SBC_REQUEST_SENSE +/// - SBC_TEST_UNIT_READY +/// - SBC_WRITE_10 +/// +/// !Optional Codes but required by Windows +/// - SBC_PREVENT_ALLOW_MEDIUM_REMOVAL +/// - SBC_MODE_SENSE_6 +/// - SBC_VERIFY_10 +/// - SBC_READ_FORMAT_CAPACITIES + +/// Request information regarding parameters of the target and Logical Unit. +#define SBC_INQUIRY 0x12 +/// Request the transfer data to the host. +#define SBC_READ_10 0x28 +/// Request capacities of the currently installed medium. +#define SBC_READ_CAPACITY_10 0x25 +/// Request that the device server transfer sense data. +#define SBC_REQUEST_SENSE 0x03 +/// Check if the LUN is ready +#define SBC_TEST_UNIT_READY 0x00 +/// Request that the device write the data transferred by the host. +#define SBC_WRITE_10 0x2A + +/// Request that the target enable or disable the removal of the medium in +/// the Logical Unit. +#define SBC_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E +/// Report parameters. +#define SBC_MODE_SENSE_6 0x1A +/// Request that the %device verify the data on the medium. +#define SBC_VERIFY_10 0x2F +/// Request a list of the possible capacities that can be formatted on medium +#define SBC_READ_FORMAT_CAPACITIES 0x23 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SBC Periph. Qualifiers" +/// This page lists the peripheral qualifier values specified in the INQUIRY +/// data +/// \see spc4r06.pdf - Section 6.4.2 - Table 83 +/// \see SBCInquiryData +/// +/// !Qualifiers +/// - SBC_PERIPHERAL_DEVICE_CONNECTED +/// - SBC_PERIPHERAL_DEVICE_NOT_CONNECTED +/// - SBC_PERIPHERAL_DEVICE_NOT_SUPPORTED + +#define SBC_PERIPHERAL_DEVICE_CONNECTED 0x00 +#define SBC_PERIPHERAL_DEVICE_NOT_CONNECTED 0x01 +#define SBC_PERIPHERAL_DEVICE_NOT_SUPPORTED 0x03 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SBC Periph. Types" +/// This page lists peripheral device types specified in the INQUIRY data +/// \see spc4r06.pdf - Section 6.4.2 - Table 84 +/// \see SBCInquiryData +/// +/// !Types +/// - SBC_DIRECT_ACCESS_BLOCK_DEVICE +/// - SBC_SEQUENTIAL_ACCESS_DEVICE +/// - SBC_PRINTER_DEVICE +/// - SBC_PROCESSOR_DEVICE +/// - SBC_WRITE_ONCE_DEVICE +/// - SBC_CD_DVD_DEVICE +/// - SBC_SCANNER_DEVICE +/// - SBC_OPTICAL_MEMORY_DEVICE +/// - SBC_MEDIA_CHANGER_DEVICE +/// - SBC_COMMUNICATION_DEVICE +/// - SBC_STORAGE_ARRAY_CONTROLLER_DEVICE +/// - SBC_ENCLOSURE_SERVICES_DEVICE +/// - SBC_SIMPLIFIED_DIRECT_ACCESS_DEVICE +/// - SBC_OPTICAL_CARD_READER_WRITER_DEVICE +/// - SBC_BRIDGE_CONTROLLER_COMMANDS +/// - SBC_OBJECT_BASED_STORAGE_DEVICE + +#define SBC_DIRECT_ACCESS_BLOCK_DEVICE 0x00 +#define SBC_SEQUENTIAL_ACCESS_DEVICE 0x01 +#define SBC_PRINTER_DEVICE 0x02 +#define SBC_PROCESSOR_DEVICE 0x03 +#define SBC_WRITE_ONCE_DEVICE 0x04 +#define SBC_CD_DVD_DEVICE 0x05 +#define SBC_SCANNER_DEVICE 0x06 +#define SBC_OPTICAL_MEMORY_DEVICE 0x07 +#define SBC_MEDIA_CHANGER_DEVICE 0x08 +#define SBC_COMMUNICATION_DEVICE 0x09 +#define SBC_STORAGE_ARRAY_CONTROLLER_DEVICE 0x0C +#define SBC_ENCLOSURE_SERVICES_DEVICE 0x0D +#define SBC_SIMPLIFIED_DIRECT_ACCESS_DEVICE 0x0E +#define SBC_OPTICAL_CARD_READER_WRITER_DEVICE 0x0F +#define SBC_BRIDGE_CONTROLLER_COMMANDS 0x10 +#define SBC_OBJECT_BASED_STORAGE_DEVICE 0x11 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \brief Version value for the SBC-3 specification +/// \see spc4r06.pdf - Section 6.4.2 - Table 85 +#define SBC_SPC_VERSION_4 0x06 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \brief Values for the TPGS field returned in INQUIRY data +/// \see spc4r06.pdf - Section 6.4.2 - Table 86 +#define SBC_TPGS_NONE 0x0 +#define SBC_TPGS_ASYMMETRIC 0x1 +#define SBC_TPGS_SYMMETRIC 0x2 +#define SBC_TPGS_BOTH 0x3 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \brief Version descriptor value for the SBC-3 specification +/// \see spc4r06.pdf - Section 6.4.2 - Table 87 +#define SBC_VERSION_DESCRIPTOR_SBC_3 0x04C0 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SBC Sense Response Codes" +/// This page lists sense data response codes returned in REQUEST SENSE data +/// \see spc4r06.pdf - Section 4.5.1 - Table 12 +/// +/// !Codes +/// - SBC_SENSE_DATA_FIXED_CURRENT +/// - SBC_SENSE_DATA_FIXED_DEFERRED +/// - SBC_SENSE_DATA_DESCRIPTOR_CURRENT +/// - SBC_SENSE_DATA_DESCRIPTOR_DEFERRED + +#define SBC_SENSE_DATA_FIXED_CURRENT 0x70 +#define SBC_SENSE_DATA_FIXED_DEFERRED 0x71 +#define SBC_SENSE_DATA_DESCRIPTOR_CURRENT 0x72 +#define SBC_SENSE_DATA_DESCRIPTOR_DEFERRED 0x73 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SBC Sense Keys" +/// This page lists sense key values returned in the REQUEST SENSE data +/// \see spc4r06.pdf - Section 4.5.6 - Table 27 +/// +/// !Keys +/// - SBC_SENSE_KEY_NO_SENSE +/// - SBC_SENSE_KEY_RECOVERED_ERROR +/// - SBC_SENSE_KEY_NOT_READY +/// - SBC_SENSE_KEY_MEDIUM_ERROR +/// - SBC_SENSE_KEY_HARDWARE_ERROR +/// - SBC_SENSE_KEY_ILLEGAL_REQUEST +/// - SBC_SENSE_KEY_UNIT_ATTENTION +/// - SBC_SENSE_KEY_DATA_PROTECT +/// - SBC_SENSE_KEY_BLANK_CHECK +/// - SBC_SENSE_KEY_VENDOR_SPECIFIC +/// - SBC_SENSE_KEY_COPY_ABORTED +/// - SBC_SENSE_KEY_ABORTED_COMMAND +/// - SBC_SENSE_KEY_VOLUME_OVERFLOW +/// - SBC_SENSE_KEY_MISCOMPARE + +/// No specific sense key. Successful command. +#define SBC_SENSE_KEY_NO_SENSE 0x00 +/// Command completed succesfully with some recovery action by the %device. +#define SBC_SENSE_KEY_RECOVERED_ERROR 0x01 +/// The device can not be accessed. +#define SBC_SENSE_KEY_NOT_READY 0x02 +/// Command terminated with a error condition that was probably caused by a +/// flaw in the medium or an error in the recorded data. +#define SBC_SENSE_KEY_MEDIUM_ERROR 0x03 +/// Hardware failure while performing the command or during a self test. +#define SBC_SENSE_KEY_HARDWARE_ERROR 0x04 +/// Illegal parameter found in the command or additional parameters. +#define SBC_SENSE_KEY_ILLEGAL_REQUEST 0x05 +/// Removable medium may have been changed or the %device has been reset. +#define SBC_SENSE_KEY_UNIT_ATTENTION 0x06 +/// Write on a block that is protected. +#define SBC_SENSE_KEY_DATA_PROTECT 0x07 +/// Indicates that a write-once device or a sequential-access device +/// encountered blank medium or format-defined end-of-data indication while +/// reading or a write-once device encountered a non-blank medium while writing. +#define SBC_SENSE_KEY_BLANK_CHECK 0x08 +/// Reporting vendor specific conditions. +#define SBC_SENSE_KEY_VENDOR_SPECIFIC 0x09 +/// EXTENDED COPY command was aborted. +#define SBC_SENSE_KEY_COPY_ABORTED 0x0A +/// Device aborted the command. +#define SBC_SENSE_KEY_ABORTED_COMMAND 0x0B +/// A buffered peripheral device is overflow. +#define SBC_SENSE_KEY_VOLUME_OVERFLOW 0x0D +/// The source data did not match the data read from the medium. +#define SBC_SENSE_KEY_MISCOMPARE 0x0E +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SBC Sense Additionals" +/// This page lists additional sense code values returned in REQUEST SENSE data +/// \see spc4r06.pdf - Section 4.5.6 - Table 28 +/// +/// !Additional Codes +/// - SBC_ASC_LOGICAL_UNIT_NOT_READY +/// - SBC_ASC_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE +/// - SBC_ASC_INVALID_FIELD_IN_CDB +/// - SBC_ASC_WRITE_PROTECTED +/// - SBC_ASC_FORMAT_CORRUPTED +/// - SBC_ASC_INVALID_COMMAND_OPERATION_CODE +/// - SBC_ASC_TOO_MUCH_WRITE_DATA +/// - SBC_ASC_NOT_READY_TO_READY_CHANGE +/// - SBC_ASC_MEDIUM_NOT_PRESENT + +#define SBC_ASC_LOGICAL_UNIT_NOT_READY 0x04 +#define SBC_ASC_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE 0x21 +#define SBC_ASC_INVALID_FIELD_IN_CDB 0x24 +#define SBC_ASC_WRITE_PROTECTED 0x27 +#define SBC_ASC_FORMAT_CORRUPTED 0x31 +#define SBC_ASC_INVALID_COMMAND_OPERATION_CODE 0x20 +#define SBC_ASC_TOO_MUCH_WRITE_DATA 0x26 +#define SBC_ASC_NOT_READY_TO_READY_CHANGE 0x28 +#define SBC_ASC_MEDIUM_NOT_PRESENT 0x3A +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \brief MEDIUM TYPE field value for direct-access block devices +/// \see sbc3r06.pdf - Section 6.3.1 +#define SBC_MEDIUM_TYPE_DIRECT_ACCESS_BLOCK_DEVICE 0x00 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \brief MRIE field values +/// \see sbc3r06.pdf - Section 7.4.11 - Table 286 +#define SBC_MRIE_NO_REPORTING 0x00 +#define SBC_MRIE_ASYNCHRONOUS 0x01 +#define SBC_MRIE_GENERATE_UNIT_ATTENTION 0x02 +#define SBC_MRIE_COND_GENERATE_RECOVERED_ERROR 0x03 +#define SBC_MRIE_UNCOND_GENERATE_RECOVERED_ERROR 0x04 +#define SBC_MRIE_GENERATE_NO_SENSE 0x05 +#define SBC_MRIE_ON_REQUEST 0x06 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \brief Supported mode pages +/// \see sbc3r06.pdf - Section 6.3.1 - Table 115 +#define SBC_PAGE_READ_WRITE_ERROR_RECOVERY 0x01 +#define SBC_PAGE_INFORMATIONAL_EXCEPTIONS_CONTROL 0x1C +#define SBC_PAGE_RETURN_ALL 0x3F +#define SBC_PAGE_VENDOR_SPECIFIC 0x00 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "MSD Endian Macros" +/// This page lists the macros for endianness conversion. +/// +/// !Macros +/// - WORDB +/// - DWORDB +/// - STORE_DWORDB +/// - STORE_WORDB +/// \brief Converts a byte array to a word value using the big endian format +#define WORDB(bytes) ((unsigned short) ((bytes[0] << 8) | bytes[1])) + +/// \brief Converts a byte array to a dword value using the big endian format +#define DWORDB(bytes) ((unsigned int) ((bytes[0] << 24) | (bytes[1] << 16) \ + | (bytes[2] << 8) | bytes[3])) + +/// \brief Stores a dword value in a byte array, in big endian format +#define STORE_DWORDB(dword, bytes) \ + bytes[0] = (unsigned char) (((dword) >> 24) & 0xFF); \ + bytes[1] = (unsigned char) (((dword) >> 16) & 0xFF); \ + bytes[2] = (unsigned char) (((dword) >> 8) & 0xFF); \ + bytes[3] = (unsigned char) ((dword) & 0xFF); + +/// \brief Stores a word value in a byte array, in big endian format +#define STORE_WORDB(word, bytes) \ + bytes[0] = (unsigned char) (((word) >> 8) & 0xFF); \ + bytes[1] = (unsigned char) ((word) & 0xFF); +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Structures +//------------------------------------------------------------------------------ + +#ifdef __ICCARM__ // IAR +#pragma pack(1) // IAR +#define __attribute__(...) // IAR +#endif // IAR + +//------------------------------------------------------------------------------ +/// \brief Structure for the INQUIRY command +/// \see spc4r06.pdf - Section 6.4.1 - Table 81 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bOperationCode; //!< 0x12 : SBC_INQUIRY + unsigned char isEVPD:1, //!< Type of requested data + bReserved1:7; //!< Reserved bits + unsigned char bPageCode; //!< Specifies the VPD to return + unsigned char pAllocationLength[2]; //!< Size of host buffer + unsigned char bControl; //!< 0x00 + +} __attribute__ ((packed)) SBCInquiry; // GCC + +//------------------------------------------------------------------------------ +/// \brief Standard INQUIRY data format returned by the device +/// \see spc4r06.pdf - Section 6.4.2 - Table 82 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bPeripheralDeviceType:5, //!< Peripheral device type + bPeripheralQualifier :3; //!< Peripheral qualifier + unsigned char bReserved1:7, //!< Reserved bits + isRMB :1; //!< Is media removable ? + unsigned char bVersion; //!< SPC version used + unsigned char bResponseDataFormat:4, //!< Must be 0x2 + isHIGHSUP :1, //!< Hierarchical addressing used ? + isNORMACA :1, //!< ACA attribute supported ? + bObsolete1 :2; //!< Obsolete bits + unsigned char bAdditionalLength; //!< Length of remaining INQUIRY data + unsigned char isSCCS :1, //!< Embedded SCC ? + isACC :1, //!< Access control coordinator ? + bTPGS :2, //!< Target port support group + is3PC :1, //!< Third-party copy supported ? + bReserved2:2, //!< Reserved bits + isProtect :1; //!< Protection info supported ? + unsigned char bObsolete2:1, //!< Obsolete bit + isEncServ :1, //!< Embedded enclosure service comp? + isVS :1, //!< ??? + isMultiP :1, //!< Multi-port device ? + bObsolete3:3, //!< Obsolete bits + bUnused1 :1; //!< Unused feature + unsigned char bUnused2:6, //!< Unused features + isCmdQue:1, //!< Task management model supported ? + isVS2 :1; //!< ??? + unsigned char pVendorID[8]; //!< T10 vendor identification + unsigned char pProductID[16]; //!< Vendor-defined product ID + unsigned char pProductRevisionLevel[4];//!< Vendor-defined product revision + unsigned char pVendorSpecific[20]; //!< Vendor-specific data + unsigned char bUnused3; //!< Unused features + unsigned char bReserved3; //!< Reserved bits + unsigned short pVersionDescriptors[8]; //!< Standards the device complies to + unsigned char pReserved4[22]; //!< Reserved bytes + +} __attribute__ ((packed)) SBCInquiryData; // GCC + +//------------------------------------------------------------------------------ +/// \brief Data structure for the READ (10) command +/// \see sbc3r07.pdf - Section 5.7 - Table 34 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bOperationCode; //!< 0x28 : SBC_READ_10 + unsigned char bObsolete1:1, //!< Obsolete bit + isFUA_NV:1, //!< Cache control bit + bReserved1:1, //!< Reserved bit + isFUA:1, //!< Cache control bit + isDPO:1, //!< Cache control bit + bRdProtect:3; //!< Protection information to send + unsigned char pLogicalBlockAddress[4]; //!< Index of first block to read + unsigned char bGroupNumber:5, //!< Information grouping + bReserved2:3; //!< Reserved bits + unsigned char pTransferLength[2]; //!< Number of blocks to transmit + unsigned char bControl; //!< 0x00 + +} __attribute__ ((packed)) SBCRead10; // GCC + +//------------------------------------------------------------------------------ +/// \brief Structure for the READ CAPACITY (10) command +/// \see sbc3r07.pdf - Section 5.11.1 - Table 40 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bOperationCode; //!< 0x25 : RBC_READ_CAPACITY + unsigned char bObsolete1:1, //!< Obsolete bit + bReserved1:7; //!< Reserved bits + unsigned char pLogicalBlockAddress[4]; //!< Block to evaluate if PMI is set + unsigned char pReserved2[2]; //!< Reserved bytes + unsigned char isPMI:1, //!< Partial medium indicator bit + bReserved3:7; //!< Reserved bits + unsigned char bControl; //!< 0x00 + +} __attribute__ ((packed)) SBCReadCapacity10; + +//------------------------------------------------------------------------------ +/// \brief Data returned by the device after a READ CAPACITY (10) command +/// \see sbc3r07.pdf - Section 5.11.2 - Table 41 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char pLogicalBlockAddress[4]; //!< Address of last logical block + unsigned char pLogicalBlockLength[4]; //!< Length of each logical block + +} __attribute__ ((packed)) SBCReadCapacity10Data; + +//------------------------------------------------------------------------------ +/// \brief Structure for the REQUEST SENSE command +/// \see spc4r06.pdf - Section 6.26 - Table 170 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bOperationCode; //!< 0x03 : SBC_REQUEST_SENSE + unsigned char isDesc :1, //!< Type of information expected + bReserved1:7; //!< Reserved bits + unsigned char pReserved2[2]; //!< Reserved bytes + unsigned char bAllocationLength; //!< Size of host buffer + unsigned char bControl; //!< 0x00 + +} __attribute__ ((packed)) SBCRequestSense; + +//------------------------------------------------------------------------------ +/// \brief Fixed format sense data returned after a REQUEST SENSE command has +/// been received with a DESC bit cleared. +/// \see spc4r06.pdf - Section 4.5.3 - Table 26 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bResponseCode:7, //!< Sense data format + isValid :1; //!< Information field is standard + unsigned char bObsolete1; //!< Obsolete byte + unsigned char bSenseKey :4, //!< Generic error information + bReserved1:1, //!< Reserved bit + isILI :1, //!< SSC + isEOM :1, //!< SSC + isFilemark:1; //!< SSC + unsigned char pInformation[4]; //!< Command-specific + unsigned char bAdditionalSenseLength; //!< sizeof(SBCRequestSense_data)-8 + unsigned char pCommandSpecificInformation[4]; //!< Command-specific + unsigned char bAdditionalSenseCode; //!< Additional error information + unsigned char bAdditionalSenseCodeQualifier; //!< Further error information + unsigned char bFieldReplaceableUnitCode; //!< Specific component code + unsigned char bSenseKeySpecific:7, //!< Additional exception info + isSKSV :1; //!< Is sense key specific valid? + unsigned char pSenseKeySpecific[2]; //!< Additional exception info + +} __attribute__ ((packed)) SBCRequestSenseData; + +//------------------------------------------------------------------------------ +/// \brief Data structure for the TEST UNIT READY command +/// \see spc4r06.pdf - Section 6.34 - Table 192 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bOperationCode; //!< 0x00 : SBC_TEST_UNIT_READY + unsigned char pReserved1[4]; //!< Reserved bits + unsigned char bControl; //!< 0x00 + +} __attribute__ ((packed)) SBCTestUnitReady; // GCC + +//------------------------------------------------------------------------------ +/// \brief Structure for the WRITE (10) command +/// \see sbc3r07.pdf - Section 5.26 - Table 70 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bOperationCode; //!< 0x2A : SBC_WRITE_10 + unsigned char bObsolete1:1, //!< Obsolete bit + isFUA_NV:1, //!< Cache control bit + bReserved1:1, //!< Reserved bit + isFUA:1, //!< Cache control bit + isDPO:1, //!< Cache control bit + bWrProtect:3; //!< Protection information to send + unsigned char pLogicalBlockAddress[4]; //!< First block to write + unsigned char bGroupNumber:5, //!< Information grouping + bReserved2:3; //!< Reserved bits + unsigned char pTransferLength[2]; //!< Number of blocks to write + unsigned char bControl; //!< 0x00 + +} __attribute__ ((packed)) SBCWrite10; + +//------------------------------------------------------------------------------ +/// \brief Structure for the PREVENT/ALLOW MEDIUM REMOVAL command +/// \see sbc3r07.pdf - Section 5.5 - Table 30 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bOperationCode; //!< 0x1E : SBC_PREVENT_ALLOW_MEDIUM_REMOVAL + unsigned char pReserved1[3]; //!< Reserved bytes + unsigned char bPrevent:2, //!< Accept/prohibit removal + bReserved2:6; //!< Reserved bits + unsigned char bControl; //!< 0x00 + +} __attribute__ ((packed)) SBCMediumRemoval; // GCC + +//------------------------------------------------------------------------------ +/// \brief Structure for the MODE SENSE (6) command +/// \see spc4r06 - Section 6.9.1 - Table 98 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bOperationCode; //!< 0x1A : SBC_MODE_SENSE_6 + unsigned char bReserved1:3, //!< Reserved bits + isDBD:1, //!< Disable block descriptors bit + bReserved2:4; //!< Reserved bits + unsigned char bPageCode:6, //!< Mode page to return + bPC:2; //!< Type of parameter values to return + unsigned char bSubpageCode; //!< Mode subpage to return + unsigned char bAllocationLength; //!< Host buffer allocated size + unsigned char bControl; //!< 0x00 + +} __attribute__ ((packed)) SBCModeSense6; // GCC + +//------------------------------------------------------------------------------ +/// \brief Header for the data returned after a MODE SENSE (6) command +/// \see spc4r06.pdf - Section 7.4.3 - Table 268 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bModeDataLength; //!< Length of mode data to follow + unsigned char bMediumType; //!< Type of medium (SBC_MEDIUM_TYPE_DIRECT_ACCESS_BLOCK_DEVICE) + unsigned char bReserved1:4, //!< Reserved bits + isDPOFUA:1, //!< DPO/FUA bits supported ? + bReserved2:2, //!< Reserved bits + isWP:1; //!< Is medium write-protected ? + unsigned char bBlockDescriptorLength; //!< Length of all block descriptors + +} __attribute__ ((packed)) SBCModeParameterHeader6; // GCC + +//------------------------------------------------------------------------------ +/// \brief Informational exceptions control mode page +/// \see spc4r06.pdf - Section 7.4.11 - Table 285 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bPageCode:6, //!< 0x1C : SBC_PAGE_INFORMATIONAL_EXCEPTIONS_CONTROL + isSPF:1, //!< Page or subpage data format + isPS:1; //!< Parameters saveable ? + unsigned char bPageLength; //!< Length of page data (0x0A) + unsigned char isLogErr:1, //!< Should informational exceptions be logged ? + isEBackErr:1, //!< Enable background error bit + isTest:1, //!< Create a device test failure ? + isDExcpt:1, //!< Disable exception control bit + isEWasc:1, //!< Report warnings ? + isEBF:1, //!< Enable background function bit + bReserved1:1, //!< Reserved bit + isPerf:1; //!< Delay acceptable when treating exceptions ? + unsigned char bMRIE:4, //!< Method of reporting informational exceptions + bReserved2:4; //!< Reserved bits + unsigned char pIntervalTimer[4]; //!< Error reporting period + unsigned char pReportCount[4]; //!< Maximum number of time a report can be issued + +} __attribute__ ((packed)) SBCInformationalExceptionsControl; // GCC + +//------------------------------------------------------------------------------ +/// \brief Read/write error recovery mode page +/// \see sbc3r07.pdf - Section 6.3.5 - Table 122 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bPageCode:6, //!< 0x01 : SBC_PAGE_READ_WRITE_ERROR_RECOVERY + isSPF:1, //!< Page or subpage data format + isPS:1; //!< Parameters saveable ? + unsigned char bPageLength; //!< Length of page data (0x0A) + unsigned char isDCR:1, //!< Disable correction bit + isDTE:1, //!< Data terminate on error bit + isPER:1, //!< Post error bit + isEER:1, //!< Enable early recovery bit + isRC:1, //!< Read continuous bit + isTB:1, //!< Transfer block bit + isARRE:1, //!< Automatic read reallocation enabled bit + isAWRE:1; //!< Automatic write reallocation enabled bit + unsigned char bReadRetryCount; //!< Number of retries when reading + unsigned char pObsolete1[3]; //!< Obsolete bytes + unsigned char bReserved1; //!< Reserved byte + unsigned char bWriteRetryCount; //!< Number of retries when writing + unsigned char bReserved2; //!< Reserved byte + unsigned char pRecoveryTimeLimit[2]; //!< Maximum time duration for error recovery + +} __attribute__ ((packed)) SBCReadWriteErrorRecovery; // GCC + +//------------------------------------------------------------------------------ +/// \brief Generic structure for holding information about SBC commands +/// \see SBCInquiry +/// \see SBCRead10 +/// \see SBCReadCapacity10 +/// \see SBCRequestSense +/// \see SBCTestUnitReady +/// \see SBCWrite10 +/// \see SBCMediumRemoval +/// \see SBCModeSense6 +//------------------------------------------------------------------------------ +typedef union { + + unsigned char bOperationCode; //!< Operation code of the command + SBCInquiry inquiry; //!< INQUIRY command + SBCRead10 read10; //!< READ (10) command + SBCReadCapacity10 readCapacity10; //!< READ CAPACITY (10) command + SBCRequestSense requestSense; //!< REQUEST SENSE command + SBCTestUnitReady testUnitReady; //!< TEST UNIT READY command + SBCWrite10 write10; //!< WRITE (10) command + SBCMediumRemoval mediumRemoval; //!< PREVENT/ALLOW MEDIUM REMOVAL command + SBCModeSense6 modeSense6; //!< MODE SENSE (6) command + +} SBCCommand; + +#ifdef __ICCARM__ // IAR +#pragma pack() // IAR +#endif // IAR + +#endif //#ifndef SBC_H + diff --git a/radio/bootloader/include/aspi.h b/radio/bootloader/include/aspi.h new file mode 100644 index 000000000..36c354311 --- /dev/null +++ b/radio/bootloader/include/aspi.h @@ -0,0 +1,37 @@ +/** + ****************************************************************************** + * @file Project/spi/spi.h + * @author X9D Application Team + * @Hardware version V0.2 + * @date 11-July-2012 + * @brief spi.c' Header file. + * * + ****************************************************************************** +*/ +#ifndef _ASPI_H_ +#define _ASPI_H_ + +#include "stm32f2xx.h" + +#define LCD_NCS_HIGH() (GPIO_LCD->BSRRL = PIN_LCD_NCS) +#define LCD_NCS_LOW() (GPIO_LCD->BSRRH = PIN_LCD_NCS) + +#define LCD_A0_HIGH() (GPIO_LCD->BSRRL = PIN_LCD_A0) +#define LCD_A0_LOW() (GPIO_LCD->BSRRH = PIN_LCD_A0) + +#define LCD_RST_HIGH() (GPIO_LCD->BSRRL = PIN_LCD_RST) +#define LCD_RST_LOW() (GPIO_LCD->BSRRH = PIN_LCD_RST) + +#define LCD_CLK_HIGH() (GPIO_LCD->BSRRL = PIN_LCD_CLK) +#define LCD_CLK_LOW() (GPIO_LCD->BSRRH = PIN_LCD_CLK) + +#define LCD_MOSI_HIGH() (GPIO_LCD->BSRRL = PIN_LCD_MOSI) +#define LCD_MOSI_LOW() (GPIO_LCD->BSRRH = PIN_LCD_MOSI) + + +void AspiCmd(u8 Command_Byte); +void AspiData(u8 Para_data); +//u16 spiRegAccess(u8 addrByte, u8 writeValue); + +#endif + diff --git a/radio/bootloader/include/board.h b/radio/bootloader/include/board.h new file mode 100644 index 000000000..0af66e835 --- /dev/null +++ b/radio/bootloader/include/board.h @@ -0,0 +1,714 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2009, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/** + * \page sam3s_ek_board_desc "SAM3S-EK - Board Description" + * + * \section + * A file is dedicated to descibe the AT91SAM3S-EK board. + * + * \section Contents + * - The code for booting the board is provided by board_cstartup.S and + * board_lowlevel.c. + * - For using board PIOs, board characteristics (clock, etc.) and external + * components, see board.h. + * - For manipulating memories (remapping, SDRAM, etc.), see board_memories.h. + * + * To get more software details and the full list of parameters related to the + * SAM3S-EK board configuration, please have a look at the source file: \n + * \ref board.h\n + * + * This file can be used as a template and modified to fit a custom board, with + * specific PIOs usage or memory connections. + **/ +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +/// \file board.h +/// +/// \par Purpose +/// +/// Definition of AT91SAM3S-EK characteristics, AT91SAM3S-dependant PIOs and +/// external components interfacing. +/// +/// \par Usage +/// -# For operating frequency information, see "SAM3S-EK - Operating frequencies". +/// -# For using portable PIO definitions, see "SAM3S-EK - PIO definitions". +/// -# Several USB definitions are included here (see "SAM3S-EK - USB device"). +//------------------------------------------------------------------------------ + +#ifndef BOARD_H +#define BOARD_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +/* These headers were introduced in C99 by working group ISO/IEC JTC1/SC22/WG14. */ +#include + +#ifdef SIMU +#define CONVERT_PTR(x) ((uint32_t)(uint64_t)(x)) +#else +//#include "core_cm3.h" +#define CONVERT_PTR(x) ((uint32_t)(x)) +#endif + +#ifndef SIMU +#include +#if defined(at91sam3s4) + #include "chip.h" + #include "AT91SAM3S4.h" +#else + #if defined(at91sam3s8) + #include "chip.h" + #include "AT91SAM3S4.h" + #else + #error Board does not support the specified chip. + #endif +#endif +#endif + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \par +/// This page lists several definition related to the board description. +/// +/// Definitions +/// - BOARD_NAME + +/// Name of the board. +#define BOARD_NAME "AT91SAM3S-EK" +/// Board definition. +#define at91sam3sek +/// Family definition (already defined). +#define at91sam3s +/// Core definition +#define cortexm3 + +//#define BOARD_REV_A +#define BOARD_REV_B + +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \par sam3s_ek_opfreq "SAM3S-EK - Operating frequencies" +/// This page lists several definition related to the board operating frequency +/// (when using the initialization done by board_lowlevel.c). +/// +/// !Definitions +/// - BOARD_MAINOSC +/// - BOARD_MCK + +/// Frequency of the board main oscillator. +#define BOARD_MAINOSC 12000000 + +/// Master clock frequency (when using board_lowlevel.c). +//#define BOARD_MCK 48000000 +#define BOARD_MCK 64000000 + +//------------------------------------------------------------------------------ +// ADC +//------------------------------------------------------------------------------ + +/// Startup time max, return from Idle mode (in s) +#define ADC_STARTUP_TIME_MAX 15 +/// Track and hold Acquisition Time min (in ns) +#define ADC_TRACK_HOLD_TIME_MIN 1200 + +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// USB attributes configuration descriptor (bus or self powered, remote wakeup) +//#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_RWAKEUP +#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \par sam3s_ek_piodef "SAM3S-EK - PIO definitions" +/// This pages lists all the pio definitions contained in board.h. The constants +/// are named using the following convention: PIN_* for a constant which defines +/// a single Pin instance (but may include several PIOs sharing the same +/// controller), and PINS_* for a list of Pin instances. +/// +/// !ADC +/// - PIN_ADC0_AD0 +/// - PIN_ADC0_AD1 +/// - PIN_ADC0_AD2 +/// - PIN_ADC0_AD3 +/// - PIN_ADC0_AD4 +/// - PIN_ADC0_AD5 +/// - PIN_ADC0_AD6 +/// - PIN_ADC0_AD7 +/// - PINS_ADC0 +/// +/// !UART +/// - PINS_UART +/// +/// !EBI +/// - PIN_EBI_DATA_BUS +/// - PIN_EBI_NCS0 +/// - PIN_EBI_NRD +/// - PIN_EBI_NWE +/// - PIN_EBI_ADDR_BUS +/// - PIN_EBI_PSRAM_NBS +/// - PIN_EBI_A1 +/// - PIN_EBI_LCD_RS +/// +/// !LEDs +/// - PIN_LED_0 +/// - PIN_LED_1 +/// - PIN_LED_2 +/// - PINS_LEDS +/// +/// !MCI +/// - PINS_MCI +/// +/// !Push buttons +/// - PIN_PUSHBUTTON_1 +/// - PIN_PUSHBUTTON_2 +/// - PINS_PUSHBUTTONS +/// - PUSHBUTTON_BP1 +/// - PUSHBUTTON_BP2 +/// +/// !PWMC +/// - PIN_PWMC_PWMH0 +/// - PIN_PWMC_PWML0 +/// - PIN_PWMC_PWMH1 +/// - PIN_PWMC_PWML1 +/// - PIN_PWMC_PWMH2 +/// - PIN_PWMC_PWML2 +/// - PIN_PWMC_PWMH3 +/// - PIN_PWMC_PWML3 +/// - PIN_PWM_LED0 +/// - PIN_PWM_LED1 +/// - PIN_PWM_LED2 +/// - CHANNEL_PWM_LED0 +/// - CHANNEL_PWM_LED1 +/// - CHANNEL_PWM_LED2 +/// +/// !SPI +/// - PIN_SPI_MISO +/// - PIN_SPI_MOSI +/// - PIN_SPI_SPCK +/// - PINS_SPI +/// - PIN_SPI_NPCS0_PA11 +/// +/// ! SSC +/// - PIN_SSC_TD +/// - PIN_SSC_TK +/// - PIN_SSC_TF +/// - PINS_SSC_CODEC +/// +/// ! PCK0 +/// - PIN_PCK0 +/// +/// !TWI +/// - PIN_TWI_TWD0 +/// - PIN_TWI_TWCK0 +/// - PINS_TWI +/// +/// !USART0 +/// - PIN_USART0_RXD +/// - PIN_USART0_TXD +/// - PIN_USART0_CTS +/// - PIN_USART0_RTS +/// - PIN_USART0_SCK +/// +/// !USB +/// - PIN_USB_PULLUP +/// + +/// ADC_AD0 pin definition. +#define PIN_ADC0_AD0 {1 << 21, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT} +/// ADC_AD1 pin definition. +#define PIN_ADC0_AD1 {1 << 30, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT} +/// ADC_AD2 pin definition. +#define PIN_ADC0_AD2 {1 << 3, PIOB, ID_PIOB, PIO_INPUT, PIO_DEFAULT} +/// ADC_AD3 pin definition. +#define PIN_ADC0_AD3 {1 << 4, PIOB, ID_PIOB, PIO_INPUT, PIO_DEFAULT} +/// ADC_AD4 pin definition. +#define PIN_ADC0_AD4 {1 << 15, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} +/// ADC_AD5 pin definition. +#define PIN_ADC0_AD5 {1 << 16, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} +/// ADC_AD6 pin definition. +#define PIN_ADC0_AD6 {1 << 17, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} +/// ADC_AD7 pin definition. +#define PIN_ADC0_AD7 {1 << 18, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} + +/// Pins ADC +#define PINS_ADC PIN_ADC0_AD0, PIN_ADC0_AD1, PIN_ADC0_AD2, PIN_ADC0_AD3, PIN_ADC0_AD4, PIN_ADC0_AD5, PIN_ADC0_AD6, PIN_ADC0_AD7 + +/** UART pins (UTXD0 and URXD0) definitions, PA9,10. */ +#define PINS_UART {0x00000600, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} + +/// EBI +#define PIN_EBI_DATA_BUS {0xFF, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_NRD {1 << 11, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_NWE {1 << 8, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} + +#define PIN_EBI_NCS0 {1 << 20, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_PSRAM_ADDR_BUS {0x3f00fff, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_PSRAM_NBS {1 << 7, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_PULLUP}, \ + {1 << 15, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_A1 {1 << 19, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} + +#define PIN_EBI_NCS1 {1 << 15, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} /* LCD CS pin */ +#define PIN_EBI_LCD_RS {1 << 19, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} /* LCD RS pin */ + +#ifdef BOARD_REV_A +/** LED #0 pin definition. */ +#define PIN_LED_0 {1 << 20, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +/** LED #1 pin definition. */ +#define PIN_LED_1 {1 << 21, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +/** LED #2 pin definition. */ +#define PIN_LED_2 {1 << 22, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +#endif +#ifdef BOARD_REV_B +/** LED #0 pin definition. */ +#define PIN_LED_0 {1 << 19, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} +/** LED #1 pin definition. */ +#define PIN_LED_1 {1 << 20, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} +/** LED #2 pin definition. */ +#define PIN_LED_2 {1 << 20, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +#endif + +/** List of all LEDs definitions. */ +#define PINS_LEDS PIN_LED_0, PIN_LED_1, PIN_LED_2 + +/// MCI pins definition. +#define PINS_MCI {0x1f8, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_PULLUP}, \ + {1 << 3, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} + +/// MCI pin Card Detect +#define PIN_MCI_CD \ + {AT91C_PIO_PA25, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP} + +/** Push button #0 definition. Attributes = pull-up + debounce + interrupt on rising edge. */ +#define PIN_PUSHBUTTON_1 {1 << 3, PIOB, ID_PIOB, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE} +/** Push button #1 definition. Attributes = pull-up + debounce + interrupt on falling edge. */ +#define PIN_PUSHBUTTON_2 {1 << 12, PIOC, ID_PIOC, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE} +/** List of all push button definitions. */ +#define PINS_PUSHBUTTONS PIN_PUSHBUTTON_1, PIN_PUSHBUTTON_2 + +/** Push button #1 index. */ +#define PUSHBUTTON_BP1 0 +/** Push button #2 index. */ +#define PUSHBUTTON_BP2 1 + +/// Simulated joystick LEFT index. +#define JOYSTICK_LEFT 0 +/// Simulated joystick RIGHT index. +#define JOYSTICK_RIGHT 1 + +/** PWMC PWM0 pin definition. */ +#define PIN_PWMC_PWMH0 {1 << 18, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} +#define PIN_PWMC_PWML0 {1 << 19, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} +/** PWMC PWM1 pin definition. */ +#define PIN_PWMC_PWMH1 {1 << 19, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} +#define PIN_PWMC_PWML1 {1 << 20, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} +/** PWMC PWM2 pin definition. */ +#define PIN_PWMC_PWMH2 {1 << 20, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} +#define PIN_PWMC_PWML2 {1 << 16, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT} +/** PWMC PWM3 pin definition. */ +#define PIN_PWMC_PWMH3 {1 << 21, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} +#define PIN_PWMC_PWML3 {1 << 15, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT} +/** PWM pin definition for LED0 */ +#define PIN_PWM_LED0 PIN_PWMC_PWMH0, PIN_PWMC_PWML0 +/** PWM pin definition for LED1 */ +#define PIN_PWM_LED1 PIN_PWMC_PWMH2, PIN_PWMC_PWML2 +/** PWM pin definition for LED2 */ +#define PIN_PWM_LED2 PIN_PWMC_PWMH3, PIN_PWMC_PWML3 +/** PWM channel for LED0 */ +#define CHANNEL_PWM_LED0 0 +/** PWM channel for LED1 */ +#define CHANNEL_PWM_LED1 2 +/** PWM channel for LED2 */ +#define CHANNEL_PWM_LED2 3 + +/** SPI MISO pin definition. */ +#define PIN_SPI_MISO {1 << 12, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** SPI MOSI pin definition. */ +#define PIN_SPI_MOSI {1 << 13, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** SPI SPCK pin definition. */ +#define PIN_SPI_SPCK {1 << 14, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** SPI chip select pin definition. */ +#define PIN_SPI_NPCS0_PA11 {1 << 11, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** List of SPI pin definitions (MISO, MOSI & SPCK). */ +#define PINS_SPI PIN_SPI_MISO, PIN_SPI_MOSI, PIN_SPI_SPCK + +/// SSC pins definition. +#define PIN_SSC_TD {0x1 << 26, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_SSC_TK {0x1 << 28, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_SSC_TF {0x1 << 30, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PINS_SSC_CODEC PIN_SSC_TD, PIN_SSC_TK, PIN_SSC_TF + +/// PCK0 +#define PIN_PCK0 {0x1 << 21, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} + +/// TWI pins definition. +#define TWI_V3XX +#define PIN_TWI_TWD0 {0x1 << 9, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_TWI_TWCK0 {0x1 << 10, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PINS_TWI0 PIN_TWI_TWD0, PIN_TWI_TWCK0 +#define PIN_TWI_TWD1 {0x1 << 24, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_TWI_TWCK1 {0x1 << 25, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PINS_TWI1 PIN_TWI_TWD1, PIN_TWI_TWCK1 + +/// USART0 +#define PIN_USART0_RXD {0x1 << 19, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART0_TXD {0x1 << 18, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART0_CTS {0x1 << 8, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART0_RTS {0x1 << 7, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART0_SCK {0x1 << 17, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} + +/// USART1 +#define PIN_USART1_RXD {0x1 << 21, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART1_TXD {0x1 << 22, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART1_CTS {0x1 << 25, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART1_RTS {0x1 << 24, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART1_EN {0x1 << 23, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT} + + + +/// USB VBus monitoring pin definition. +#ifdef BOARD_REV_A +#define PIN_USB_VBUS {1 << 23, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} +#endif +#ifdef BOARD_REV_B +#define PIN_USB_VBUS {1 << 21, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} +#endif + +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \par sam3s_ek_extcomp "SAM3S-EK - External components" +/// This page lists the definitions related to external on-board components +/// located in the board.h file for the AT91SAM3S-EK. +/// +/// !AT45 Dataflash Card +/// - BOARD_AT45_A_SPI_BASE +/// - BOARD_AT45_A_SPI_ID +/// - BOARD_AT45_A_SPI_PINS +/// - BOARD_AT45_A_SPI +/// - BOARD_AT45_A_NPCS +/// - BOARD_AT45_A_NPCS_PIN +/// +/// !AT45 Dataflash (serial onboard DataFlash) +/// - BOARD_AT45_B_SPI_BASE +/// - BOARD_AT45_B_SPI_ID +/// - BOARD_AT45_B_SPI_PINS +/// - BOARD_AT45_B_SPI +/// - BOARD_AT45_B_NPCS +/// - BOARD_AT45_B_NPCS_PIN +/// +/// !AT26 Serial Flash +/// - BOARD_AT26_A_SPI_BASE +/// - BOARD_AT26_A_SPI_ID +/// - BOARD_AT26_A_SPI_PINS +/// - BOARD_AT26_A_SPI +/// - BOARD_AT26_A_NPCS +/// - BOARD_AT26_A_NPCS_PIN +/// +/// !SD Card +/// - MCI2_INTERFACE +/// - BOARD_SD_MCI_BASE +/// - BOARD_SD_MCI_ID +/// - BOARD_SD_PINS +/// - BOARD_SD_SLOT +/// +/// !PSRAM +/// - BOARD_PSRAM_PINS +/// +/// !LCD +/// - BOARD_LCD_ILI9325 +/// - BOARD_LCD_PINS +/// - BOARD_BACKLIGHT_PIN +/// - BOARD_LCD_BASE +/// - BOARD_LCD_RS +/// - BOARD_LCD_WIDTH +/// - BOARD_LCD_HEIGHT +/// +/// !TouchScreen +/// - BOARD_TSC_ADS7843 +/// - PIN_TCS_IRQ +/// - PIN_TCS_BUSY +/// - BOARD_TSC_SPI_BASE +/// - BOARD_TSC_SPI_ID +/// - BOARD_TSC_SPI_PINS +/// - BOARD_TSC_NPCS +/// - BOARD_TSC_NPCS_PIN +/// +/// Base address of SPI peripheral connected to the dataflash. +//#define BOARD_AT45_A_SPI_BASE SPI0 +///// Identifier of SPI peripheral connected to the dataflash. +//#define BOARD_AT45_A_SPI_ID ID_SPI0 +///// Pins of the SPI peripheral connected to the dataflash. +//#define BOARD_AT45_A_SPI_PINS PINS_SPI0 +///// Dataflahs SPI number. +//#define BOARD_AT45_A_SPI 0 +///// Chip select connected to the dataflash. +//#define BOARD_AT45_A_NPCS 3 +///// Chip select pin connected to the dataflash. +//#define BOARD_AT45_A_NPCS_PIN PIN_SPI0_NPCS3 + +/// Base address of SPI peripheral connected to the dataflash. +//#define BOARD_AT45_B_SPI_BASE SPI1 +///// Identifier of SPI peripheral connected to the dataflash. +//#define BOARD_AT45_B_SPI_ID ID_SPI1 +///// Pins of the SPI peripheral connected to the dataflash. +//#define BOARD_AT45_B_SPI_PINS PINS_SPI1 +///// Dataflahs SPI number. +//#define BOARD_AT45_B_SPI 1 +///// Chip select connected to the dataflash. +//#define BOARD_AT45_B_NPCS 3 +///// Chip select pin connected to the dataflash. +//#define BOARD_AT45_B_NPCS_PIN PIN_SPI1_NPCS3 + +/// Base address of SPI peripheral connected to the serialflash. +//#define BOARD_AT26_A_SPI_BASE SPI0 +///// Identifier of SPI peripheral connected to the serialflash. +//#define BOARD_AT26_A_SPI_ID ID_SPI0 +///// Pins of the SPI peripheral connected to the serialflash. +//#define BOARD_AT26_A_SPI_PINS PINS_SPI0 +///// Serialflash SPI number. +//#define BOARD_AT26_A_SPI 0 +///// Chip select connected to the serialflash. +//#define BOARD_AT26_A_NPCS 3 +///// Chip select pin connected to the serialflash. +//#define BOARD_AT26_A_NPCS_PIN PIN_SPI0_NPCS3 + +/// ISO7816 +/// - PIN_SMARTCARD_CONNECT +/// - PIN_ISO7816_RSTMC +/// - PINS_ISO7816 + +/// Smartcard detection pin +//#define PIN_SMARTCARD_CONNECT {1 << 5, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT} +/// PIN used for reset the smartcard +//#define PIN_ISO7816_RSTMC {1 << 7, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT} +/// Pins used for connect the smartcard +//#define PINS_ISO7816 PIN_USART0_TXD, PIN_USART0_SCK, PIN_ISO7816_RSTMC + +/// Dma channel number +#define BOARD_MCI_DMA_CHANNEL 0 +/// MCI0 DMA hardware handshaking ID +#define DMA_HW_SRC_REQ_ID_MCI0 AT91C_HDMA_SRC_PER_0 +#define DMA_HW_DEST_REQ_ID_MCI0 AT91C_HDMA_DST_PER_0 +/// MCI1 DMA hardware handshaking ID +#define DMA_HW_SRC_REQ_ID_MCI1 AT91C_HDMA_SRC_PER_13 +#define DMA_HW_DEST_REQ_ID_MCI1 AT91C_HDMA_DST_PER_13 +/// SD DMA hardware handshaking ID +#define BOARD_SD_DMA_HW_SRC_REQ_ID DMA_HW_SRC_REQ_ID_MCI0 +#define BOARD_SD_DMA_HW_DEST_REQ_ID DMA_HW_DEST_REQ_ID_MCI0 + + +/// HS MCI interface +#define MCI2_INTERFACE +/// Base address of the MCI peripheral connected to the SD card. +#define BOARD_SD_MCI_BASE MCI0//MCI +///// Peripheral identifier of the MCI connected to the SD card. +#define BOARD_SD_MCI_ID ID_MCI0 //ID_MCI +///// MCI pins that shall be configured to access the SD card. +#define BOARD_SD_PINS PINS_MCI +///// MCI slot to which the SD card is connected to. +#define BOARD_SD_SLOT MCI_SD_SLOTA +///// MCI Card Detect pin. +#define BOARD_SD_PIN_CD PIN_MCI_CD + +/* +#define BOARD_PSRAM_PINS PIN_EBI_DATA_BUS, PIN_EBI_NCS0, PIN_EBI_NRD, PIN_EBI_NWE, \ + PIN_EBI_PSRAM_ADDR_BUS, PIN_EBI_PSRAM_NBS, PIN_EBI_A1 +*/ + +/** Indicates board has an ILI9325 external component to manage LCD. */ +#define BOARD_LCD_ILI9325 + +/** LCD pins definition. */ +#define BOARD_LCD_PINS PIN_EBI_DATA_BUS, PIN_EBI_NRD, PIN_EBI_NWE, \ + PIN_EBI_NCS1, PIN_EBI_LCD_RS +/** Backlight pin definition. */ +#define BOARD_BACKLIGHT_PIN {1 << 13, PIOC, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT} +/** Define ILI9325 base address. */ +#define BOARD_LCD_BASE 0x61000000 +/** Define ILI9325 register select signal. */ +#define BOARD_LCD_RS (1 << 1) +/** Display width in pixels. */ +#define BOARD_LCD_WIDTH 240 +/** Display height in pixels. */ +#define BOARD_LCD_HEIGHT 320 + +/** Indicates board has an ADS7843 external component to manage Touch Screen */ +#define BOARD_TSC_ADS7843 + +#ifdef BOARD_REV_A +/** Touchscreen controller IRQ pin definition. */ +#define PIN_TCS_IRQ {PIO_PA4, PIOA, ID_PIOA, PIO_INPUT, PIO_DEBOUNCE | PIO_IT_AIME | PIO_IT_EDGE} +#define PIN_TCS_IRQ_WUP_ID (1 << 3) +/** Touchscreen controller Busy pin definition. */ +#define PIN_TCS_BUSY {PIO_PA5, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP} +#endif +#ifdef BOARD_REV_B +/** Touchscreen controller IRQ pin definition. */ +#define PIN_TCS_IRQ {PIO_PA16, PIOA, ID_PIOA, PIO_INPUT, PIO_DEBOUNCE | PIO_IT_AIME | PIO_IT_EDGE} +#define PIN_TCS_IRQ_WUP_ID (1 << 15) +/** Touchscreen controller Busy pin definition. */ +#define PIN_TCS_BUSY {PIO_PA17, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP} +#endif + +/** Base address of SPI peripheral connected to the touchscreen controller. */ +#define BOARD_TSC_SPI_BASE SPI +/** Identifier of SPI peripheral connected to the touchscreen controller. */ +#define BOARD_TSC_SPI_ID ID_SPI +/** Pins of the SPI peripheral connected to the touchscreen controller. */ +#define BOARD_TSC_SPI_PINS PINS_SPI +/** Chip select connected to the touchscreen controller. */ +#define BOARD_TSC_NPCS 0 +/** Chip select pin connected to the touchscreen controller. */ +#define BOARD_TSC_NPCS_PIN PIN_SPI_NPCS0_PA11 + +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \par sam3s_ek_mem "SAM3S-EK - Memories" +/// This page lists definitions related to internal & external on-board memories. +/// +/// !Embedded Flash +/// - BOARD_FLASH_EFC + +/// Internal SRAM address +#define AT91C_ISRAM AT91C_IRAM +#define AT91C_ISRAM_SIZE 0x00008000 + +#define AT91C_IFLASH_SIZE (0x40000) +#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH 0 Page Size: 256 bytes +#define AT91C_IFLASH_NB_OF_PAGES (1024) // Internal FLASH 0 Number of Pages: 512 +#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH 0 Lock Region Size: 16 Kbytes +#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH 0 Number of Lock Bits: 16 + +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +/// \section sam3s_ek_extcomp "SAM3S-EK - External components" +/// This page lists the definitions related to external on-board components +/// located in the board.h file for the SAM3S-EK. +/// +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \par sam3s_ek_chipdef "SAM3S-EK - Individual chip definition" +/// This page lists the definitions related to different chip's definition +/// located in the board.h file for the SAM3S-EK. + +/// DBGU +#define BOARD_DBGU_ID ID_DBGU + +/// Rtc +#define BOARD_RTC_ID ID_RTC + +/// Twi eeprom +#define BOARD_ID_TWI_EEPROM ID_TWI1 +#define BOARD_BASE_TWI_EEPROM TWI1 +#define BOARD_PINS_TWI_EEPROM PINS_TWI1 + +/// USART +#define BOARD_PIN_USART_RXD PIN_USART1_RXD +#define BOARD_PIN_USART_TXD PIN_USART1_TXD +#define BOARD_PIN_USART_CTS PIN_USART1_CTS +#define BOARD_PIN_USART_RTS PIN_USART1_RTS +#define BOARD_PIN_USART_EN PIN_USART1_EN +#define BOARD_USART_BASE USART1 +#define BOARD_ID_USART ID_USART1 + +//------------------------------------------------------------------------------ + + +#define PIN_EBI_NANDOE {1 << 9, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_NANDWE {1 << 10, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_NANDCLE {1 << 17, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_NANDALE {1 << 16, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_NANDIO {0x000000FF, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} + +/// Nandflash chip enable pin definition. +#define BOARD_NF_CE_PIN {1 << 14, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +/// Nandflash ready/busy pin definition. +#define BOARD_NF_RB_PIN {1 << 18, PIOC, ID_PIOC, PIO_INPUT, PIO_PULLUP} + +/// Nandflash controller peripheral pins definition. +#define PINS_NANDFLASH PIN_EBI_NANDIO, BOARD_NF_CE_PIN, BOARD_NF_RB_PIN, PIN_EBI_NANDOE, \ + PIN_EBI_NANDWE, PIN_EBI_NANDCLE, PIN_EBI_NANDALE + +/// Address for transferring command bytes to the nandflash. +#define BOARD_NF_COMMAND_ADDR 0x60400000 +/// Address for transferring address bytes to the nandflash. +#define BOARD_NF_ADDRESS_ADDR 0x60200000 +/// Address for transferring data bytes to the nandflash. +#define BOARD_NF_DATA_ADDR 0x60000000 + +extern uint32_t Cmd_A41_resp ; + +#define OCR_SD_CCS (1UL << 30) + +#define SD_CSD(csd, bitfield, bits) ((csd[3-(bitfield)/32] >> ((bitfield)%32)) & ((1 << (bits)) - 1)) + +#define SD_CSD_C_SIZE(pSd) ((SD_CSD(pSd, 72, 2) << 10) + \ + (SD_CSD(pSd, 64, 8) << 2) + \ + SD_CSD(pSd, 62, 2)) ///< Device size + +#define SD_CSD_C_SIZE_HC(csd) ((SD_CSD(csd, 64, 6) << 16) + \ + (SD_CSD(csd, 56, 8) << 8) + \ + SD_CSD(csd, 48, 8)) ///< Device size v2.0 High Capacity + +#define SD_CSD_C_SIZE_MULT(pSd) SD_CSD(pSd, 47, 3) ///< Device size multiplier + +#define SD_CSD_MULT(pSd) (1 << (SD_CSD_C_SIZE_MULT(pSd) + 2)) + +#define SD_CSD_BLKLEN(pSd) (1 << ( SD_CSD(pSd, 80, 4) - 9 ) ) + +#define SD_CSD_BLOCKNR(pSd) ((SD_CSD_C_SIZE(pSd) + 1) * SD_CSD_MULT(pSd)) * SD_CSD_BLKLEN(pSd) + +#define SD_CSD_BLOCKNR_HC(pSd) ((SD_CSD_C_SIZE_HC(pSd) + 1) * 1024) + +#if !defined(SIMU) +#define SD_IS_HC() (Cmd_A41_resp & OCR_SD_CCS) +#define SD_GET_BLOCKNR() (SD_IS_HC() ? (SD_CSD_BLOCKNR_HC(Card_CSD)) : (SD_CSD_BLOCKNR(Card_CSD))) + +#define SD_GET_SPEED() (transSpeed) + +#define SD_GET_SIZE_MB() (SD_GET_BLOCKNR() / 2048) +#endif + +#endif //#ifndef BOARD_H + diff --git a/radio/bootloader/include/chip.h b/radio/bootloader/include/chip.h new file mode 100644 index 000000000..8b6984086 --- /dev/null +++ b/radio/bootloader/include/chip.h @@ -0,0 +1,130 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// !Purpose +/// +/// Definition of AT91SAM3S4 characteristics and features +/// +/// !Usage +/// -# For ARM core feature, see "AT91SAM3S4 - ARM core features". +/// -# For IP features, see "AT91SAM3S4 - IP features". +/// -# For misc, see "AT91SAM3S4 - Misc". +//------------------------------------------------------------------------------ + +#ifndef CHIP_H +#define CHIP_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "AT91SAM3S4 - ARM core features" +/// This page lists several characteristics related to the ARM core +/// + +//ARM core features + +/// ARM core definition. +#define cortexm3 + +/// family definition. +#define at91sam3s + +//------------------------------------------------------------------------------ +/// \page "AT91SAM3S4 - IP features" +/// This page lists several characteristics related to the embedded IP +/// + +//IP FEATURES + +// EFC GPNVM number +#define CHIP_EFC_NUM_GPNVMS 3 + +/// Indicates chip has an Enhanced EFC. +#define CHIP_FLASH_EEFC + +// DMA channels number +#define CHIP_DMA_CHANNEL_NUM 4 + +// Indicate chip's MCI interface. +#define MCI2_INTERFACE + +// Indicate chip SSC has DMA interface. +#define CHIP_SSC_DMA + +// Indicate chip SPI has DMA interface. +#define CHIP_SPI_DMA + +/// Indicates chip has an UDP Full Speed. +#define CHIP_USB_UDP + +/// Indicates chip has an internal pull-up. +#define CHIP_USB_PULLUP_INTERNAL + +/// Number of USB endpoints +#define CHIP_USB_NUMENDPOINTS 8 + +/// Endpoints max paxcket size +#define CHIP_USB_ENDPOINTS_MAXPACKETSIZE(i) \ + ((i == 0) ? 64 : \ + ((i == 1) ? 64 : \ + ((i == 2) ? 64 : \ + ((i == 3) ? 64 : \ + ((i == 4) ? 512 : \ + ((i == 5) ? 512 : \ + ((i == 6) ? 64 : \ + ((i == 7) ? 64 : 0 )))))))) + +/// Endpoints Number of Bank +#define CHIP_USB_ENDPOINTS_BANKS(i) \ + ((i == 0) ? 1 : \ + ((i == 1) ? 2 : \ + ((i == 2) ? 2 : \ + ((i == 3) ? 1 : \ + ((i == 4) ? 2 : \ + ((i == 5) ? 2 : \ + ((i == 6) ? 2 : \ + ((i == 7) ? 2 : 0 )))))))) + +//------------------------------------------------------------------------------ +/// \page "AT91SAM3S4 - Misc " +/// This page lists misc features +/// + +//Misc + +#endif //#ifndef CHIP_H + diff --git a/radio/bootloader/include/core_cm3.h b/radio/bootloader/include/core_cm3.h new file mode 100644 index 000000000..4afe42cda --- /dev/null +++ b/radio/bootloader/include/core_cm3.h @@ -0,0 +1,1818 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V1.30 + * @date 30. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CM3_CORE_H__ +#define __CM3_CORE_H__ + +/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration + * + * List of Lint messages which will be suppressed and not shown: + * - Error 10: \n + * register uint32_t __regBasePri __asm("basepri"); \n + * Error 10: Expecting ';' + * . + * - Error 530: \n + * return(__regBasePri); \n + * Warning 530: Symbol '__regBasePri' (line 264) not initialized + * . + * - Error 550: \n + * __regBasePri = (basePri & 0x1ff); \n + * Warning 550: Symbol '__regBasePri' (line 271) not accessed + * . + * - Error 754: \n + * uint32_t RESERVED0[24]; \n + * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced + * . + * - Error 750: \n + * #define __CM3_CORE_H__ \n + * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced + * . + * - Error 528: \n + * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n + * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced + * . + * - Error 751: \n + * } InterruptType_Type; \n + * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced + * . + * Note: To re-enable a Message, insert a space before 'lint' * + * + */ + +/*lint -save */ +/*lint -e10 */ +/*lint -e530 */ +/*lint -e550 */ +/*lint -e754 */ +/*lint -e750 */ +/*lint -e528 */ +/*lint -e751 */ + + +/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core registers and bitfields + - Cortex-M core peripheral base address + @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex core */ + +#include /* Include standard types */ + +#if defined (__ICCARM__) + #include /* IAR Intrinsics */ +#endif + + +#ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ +#endif + + + + +/** + * IO definitions + * + * define access restrictions to peripheral registers + */ + +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register + @{ +*/ + + +/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC + memory mapped structure for Nested Vectored Interrupt Controller (NVIC) + @{ + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ +} NVIC_Type; +/*@}*/ /* end of group CMSIS_CM3_NVIC */ + + +/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB + memory mapped structure for System Control Block (SCB) + @{ + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (0x1ul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +/*@}*/ /* end of group CMSIS_CM3_SCB */ + + +/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick + memory mapped structure for SysTick + @{ + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ +/*@}*/ /* end of group CMSIS_CM3_SysTick */ + + +/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM + memory mapped structure for Instrumentation Trace Macrocell (ITM) + @{ + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ + __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ + __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +/*@}*/ /* end of group CMSIS_CM3_ITM */ + + +/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type + memory mapped structure for Interrupt Type + @{ + */ +typedef struct +{ + uint32_t RESERVED0; + __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ +#else + uint32_t RESERVED1; +#endif +} InterruptType_Type; + +/* Interrupt Controller Type Register Definitions */ +#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ +#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ +#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ + +#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ +#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ + +#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ +#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ +/*@}*/ /* end of group CMSIS_CM3_InterruptType */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) +/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU + memory mapped structure for Memory Protection Unit (MPU) + @{ + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ +#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ +#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ +#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ +#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ +#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ +#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@}*/ /* end of group CMSIS_CM3_MPU */ +#endif + + +/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug + memory mapped structure for Core Debug Register + @{ + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ + + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ + +#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ +#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_register */ + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#define __enable_fault_irq __enable_fiq +#define __disable_fault_irq __disable_fiq + +#define __NOP __nop +#define __WFI __wfi +#define __WFE __wfe +#define __SEV __sev +#define __ISB() __isb(0) +#define __DSB() __dsb(0) +#define __DMB() __dmb(0) +#define __REV __rev +#define __RBIT __rbit +#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) +#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) +#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) +#define __STREXB(value, ptr) __strex(value, ptr) +#define __STREXH(value, ptr) __strex(value, ptr) +#define __STREXW(value, ptr) __strex(value, ptr) + + +/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ +/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +extern int32_t __REVSH(int16_t value); + + +#if (__ARMCC_VERSION < 400000) + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +extern void __CLREX(void); + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +extern uint32_t __get_BASEPRI(void); + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +extern void __set_BASEPRI(uint32_t basePri); + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +extern uint32_t __get_PRIMASK(void); + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +extern void __set_PRIMASK(uint32_t priMask); + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +extern uint32_t __get_FAULTMASK(void); + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +extern void __set_FAULTMASK(uint32_t faultMask); + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +extern uint32_t __get_CONTROL(void); + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +extern void __set_CONTROL(uint32_t control); + +#else /* (__ARMCC_VERSION >= 400000) */ + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +#define __CLREX __clrex + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +static __INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & 1); +} + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +static __INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ +#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ + +static __INLINE void __enable_fault_irq( void ) { __ASM ("cpsie f"); } +static __INLINE void __disable_fault_irq( void ) { __ASM ("cpsid f"); } + +#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ +static __INLINE void __WFI( void ) { __ASM ("wfi"); } +static __INLINE void __WFE( void ) { __ASM ("wfe"); } +static __INLINE void __SEV( void ) { __ASM ("sev"); } +static __INLINE void __CLREX( void ) { __ASM ("clrex"); } + +/* intrinsic void __ISB(void) */ +/* intrinsic void __DSB(void) */ +/* intrinsic void __DMB(void) */ +/* intrinsic void __set_PRIMASK(); */ +/* intrinsic void __get_PRIMASK(); */ +/* intrinsic void __set_FAULTMASK(); */ +/* intrinsic void __get_FAULTMASK(); */ +/* intrinsic uint32_t __REV(uint32_t value); */ +/* intrinsic uint32_t __REVSH(uint32_t value); */ +/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ +/* intrinsic unsigned long __LDREX(unsigned long *); */ + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +extern uint32_t __RBIT(uint32_t value); + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit values) + */ +extern uint8_t __LDREXB(uint8_t *addr); + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +extern uint16_t __LDREXH(uint16_t *addr); + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +extern uint32_t __LDREXW(uint32_t *addr); + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +extern uint32_t __STREXB(uint8_t value, uint8_t *addr); + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +extern uint32_t __STREXH(uint16_t value, uint16_t *addr); + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +extern uint32_t __STREXW(uint32_t value, uint32_t *addr); + + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +static __INLINE void __enable_irq(void) { __ASM volatile ("cpsie i"); } +static __INLINE void __disable_irq(void) { __ASM volatile ("cpsid i"); } + +static __INLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f"); } +static __INLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f"); } + +static __INLINE void __NOP(void) { __ASM volatile ("nop"); } +static __INLINE void __WFI(void) { __ASM volatile ("wfi"); } +static __INLINE void __WFE(void) { __ASM volatile ("wfe"); } +static __INLINE void __SEV(void) { __ASM volatile ("sev"); } +static __INLINE void __ISB(void) { __ASM volatile ("isb"); } +static __INLINE void __DSB(void) { __ASM volatile ("dsb"); } +static __INLINE void __DMB(void) { __ASM volatile ("dmb"); } +static __INLINE void __CLREX(void) { __ASM volatile ("clrex"); } + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +extern uint32_t __get_BASEPRI(void); + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +extern void __set_BASEPRI(uint32_t basePri); + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +extern uint32_t __get_PRIMASK(void); + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +extern void __set_PRIMASK(uint32_t priMask); + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +extern uint32_t __get_FAULTMASK(void); + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +extern void __set_FAULTMASK(uint32_t faultMask); + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +extern uint32_t __get_CONTROL(void); + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +extern void __set_CONTROL(uint32_t control); + +/** + * @brief Reverse byte order in integer value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +extern uint32_t __REV(uint32_t value); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +extern int32_t __REVSH(int16_t value); + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +extern uint32_t __RBIT(uint32_t value); + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +extern uint8_t __LDREXB(uint8_t *addr); + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +extern uint16_t __LDREXH(uint16_t *addr); + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +extern uint32_t __LDREXW(uint32_t *addr); + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +extern uint32_t __STREXB(uint8_t value, uint8_t *addr); + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +extern uint32_t __STREXH(uint16_t value, uint16_t *addr); + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +extern uint32_t __STREXW(uint32_t value, uint32_t *addr); + + +#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + + +/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface + Core Function Interface containing: + - Core NVIC Functions + - Core SysTick Functions + - Core Reset Functions +*/ +/*@{*/ + +/* ########################## NVIC functions #################################### */ + +/** + * @brief Set the Priority Grouping in NVIC Interrupt Controller + * + * @param PriorityGroup is priority grouping field + * + * Set the priority grouping field using the required unlock sequence. + * The parameter priority_grouping is assigned to the field + * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + (0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + +/** + * @brief Get the Priority Grouping from NVIC Interrupt Controller + * + * @return priority grouping field + * + * Get the priority grouping from NVIC Interrupt Controller. + * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + +/** + * @brief Enable Interrupt in NVIC Interrupt Controller + * + * @param IRQn The positive number of the external interrupt to enable + * + * Enable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + +/** + * @brief Disable the interrupt line for external interrupt specified + * + * @param IRQn The positive number of the external interrupt to disable + * + * Disable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + +/** + * @brief Read the interrupt pending bit for a device specific interrupt source + * + * @param IRQn The number of the device specifc interrupt + * @return 1 = interrupt pending, 0 = interrupt not pending + * + * Read the pending register in NVIC and return 1 if its status is pending, + * otherwise it returns 0 + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + +/** + * @brief Set the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for set pending + * + * Set the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + +/** + * @brief Clear the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for clear pending + * + * Clear the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + +/** + * @brief Read the active bit for an external interrupt + * + * @param IRQn The number of the interrupt for read active bit + * @return 1 = interrupt active, 0 = interrupt not active + * + * Read the active register in NVIC and returns 1 if its status is active, + * otherwise it returns 0. + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + +/** + * @brief Set the priority for an interrupt + * + * @param IRQn The number of the interrupt for set priority + * @param priority The priority to set + * + * Set the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + +/** + * @brief Read the priority for an interrupt + * + * @param IRQn The number of the interrupt for get priority + * @return The priority for the interrupt + * + * Read the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * The returned priority value is automatically aligned to the implemented + * priority bits of the microcontroller. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** + * @brief Encode the priority for an interrupt + * + * @param PriorityGroup The used priority group + * @param PreemptPriority The preemptive priority value (starting from 0) + * @param SubPriority The sub priority value (starting from 0) + * @return The encoded priority for the interrupt + * + * Encode the priority for an interrupt with the given priority group, + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The returned priority value can be used for NVIC_SetPriority(...) function + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** + * @brief Decode the priority of an interrupt + * + * @param Priority The priority for the interrupt + * @param PriorityGroup The used priority group + * @param pPreemptPriority The preemptive priority value (starting from 0) + * @param pSubPriority The sub priority value (starting from 0) + * + * Decode an interrupt priority value with the given priority group to + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The priority value can be retrieved with NVIC_GetPriority(...) function + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + + +/* ################################## SysTick function ############################################ */ + +#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) + +/** + * @brief Initialize and start the SysTick counter and its interrupt. + * + * @param ticks number of ticks between two interrupts + * @return 1 = failed, 0 = successful + * + * Initialise the system tick timer and its interrupt and start the + * system tick timer / counter in free running mode to generate + * periodical interrupts. + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + + + + +/* ################################## Reset function ############################################ */ + +/** + * @brief Initiate a system reset request. + * + * Initiate a system reset request to reset the MCU + */ +static __INLINE void NVIC_SystemReset(void) +{ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ + + + +/* ##################################### Debug In/Output function ########################################### */ + +/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface + Core Debug Interface containing: + - Core Debug Receive / Transmit Functions + - Core Debug Defines + - Core Debug Variables +*/ +/*@{*/ + +extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ + + +/** + * @brief Outputs a character via the ITM channel 0 + * + * @param ch character to output + * @return character to output + * + * The function outputs a character via the ITM channel 0. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ + (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** + * @brief Inputs a character via variable ITM_RxBuffer + * + * @return received character, -1 = no character received + * + * The function inputs a character via variable ITM_RxBuffer. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE int ITM_ReceiveChar (void) { + int ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + * @brief Check if a character via variable ITM_RxBuffer is available + * + * @return 1 = character available, 0 = no character available + * + * The function checks variable ITM_RxBuffer whether a character is available or not. + * The function returns '1' if a character is available and '0' if no character is available. + */ +static __INLINE int ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_definitions */ + +#endif /* __CM3_CORE_H__ */ + +/*lint -restore */ diff --git a/radio/bootloader/include/debug.h b/radio/bootloader/include/debug.h new file mode 100644 index 000000000..57fb289cb --- /dev/null +++ b/radio/bootloader/include/debug.h @@ -0,0 +1,25 @@ +#include + +#define TRACE_DEBUG(...) { } +#define TRACE_DEBUG_WP(...) { } +#define TRACE_INFO(...) { } +#define TRACE_INFO_WP(...) { } +#define TRACE_WARNING(...) { } +#define TRACE_WARNING_WP(...) { } +#define TRACE_ERROR(...) { } + +extern void handle_serial( void* pdata ) ; +//extern uint32_t read_switch( enum EnumKeys enuk ) ; +extern void txmit( uint8_t c ) ; +//extern void disp_mem( register uint32_t address ) ; +//extern void disp_256( uint32_t address, uint32_t lines ) ; +#ifdef __cplusplus +extern "C" void utxmit( uint8_t c ) ; +extern "C" void up8hex( uint32_t value ) ; +#else +extern void utxmit( uint8_t c ) ; +extern void up8hex( uint32_t value ) ; +#endif + + + diff --git a/radio/bootloader/include/diskio.h b/radio/bootloader/include/diskio.h new file mode 100644 index 000000000..d36db188d --- /dev/null +++ b/radio/bootloader/include/diskio.h @@ -0,0 +1,179 @@ +/* + * Authors (alphabetical order) + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * open9x is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +/*----------------------------------------------------------------------- +/ Low level disk interface modlue include file (C)ChaN, 2010 +/-----------------------------------------------------------------------*/ + +#ifndef DEF_DISKIO +#define DEF_DISKIO + +#ifdef PCBSKY +#include "board.h" +#endif +#ifdef PCBX9D +#include "stm32f2xx.h" +#endif + +#if !defined(SIMU) +#include "core_cm3.h" +#endif +#include "integer.h" + +#define DN_MCI 0 /* Physical drive number for MCI */ +#define DN_NAND 1 /* Physical drive number for NAND flash */ + + +/* These functions are defined in asmfunc.S */ +void Copy_al2un (BYTE *dst, const DWORD *src, int count); /* Copy aligned to unaligned. */ +void Copy_un2al (DWORD *dst, const BYTE *src, int count); /* Copy unaligned to aligned. */ + + +/* Status of Disk Functions */ +typedef BYTE DSTATUS; + +/* Results of Disk Functions */ +typedef enum { + RES_OK = 0, /* 0: Successful */ + RES_ERROR, /* 1: R/W Error */ + RES_WRPRT, /* 2: Write Protected */ + RES_NOTRDY, /* 3: Not Ready */ + RES_PARERR /* 4: Invalid Parameter */ +} DRESULT; + + +/*---------------------------------------*/ +/* Prototypes for disk control functions */ + +DSTATUS disk_initialize (BYTE); +DSTATUS disk_status (BYTE); + +#ifdef __cplusplus +extern "C" { +#endif +DRESULT disk_read (BYTE, BYTE*, DWORD, BYTE); +DRESULT disk_write (BYTE, const BYTE*, DWORD, BYTE); +DRESULT disk_ioctl (BYTE, BYTE, BYTE*); +#ifdef __cplusplus +} +#endif + +void disk_timerproc (void); + + +/* Disk Status Bits (DSTATUS) */ + +#define STA_NOINIT 0x01 /* Drive not initialized */ +#define STA_NODISK 0x02 /* No medium in the drive */ +#define STA_PROTECT 0x04 /* Write protected */ + + +/* Command code for disk_ioctrl fucntion */ + +/* Generic ioctl command (defined for FatFs) */ +#define CTRL_SYNC 0 /* Flush disk cache (for write functions) */ +#define GET_SECTOR_COUNT 1 /* Get media size (for only f_mkfs()) */ +#define GET_SECTOR_SIZE 2 /* Get sector size (for multiple sector size (_MAX_SS >= 1024)) */ +#define GET_BLOCK_SIZE 3 /* Get erase block size (for only f_mkfs()) */ +#define CTRL_ERASE_SECTOR 4 /* Force erased a block of sectors (for only _USE_ERASE) */ + +/* Generic ioctl command */ +#define CTRL_POWER 5 /* Get/Set power status */ +#define CTRL_LOCK 6 /* Lock/Unlock media removal */ +#define CTRL_EJECT 7 /* Eject media */ + +/* MMC/SDC specific ioctl command */ +#define MMC_GET_TYPE 10 /* Get card type */ +#define MMC_GET_CSD 11 /* Get CSD */ +#define MMC_GET_CID 12 /* Get CID */ +#define MMC_GET_OCR 13 /* Get OCR */ +#define MMC_GET_SDSTAT 14 /* Get SD status */ + +/* ATA/CF specific ioctl command */ +#define ATA_GET_REV 20 /* Get F/W revision */ +#define ATA_GET_MODEL 21 /* Get model name */ +#define ATA_GET_SN 22 /* Get serial number */ + +/* NAND specific ioctl command */ +#define NAND_FORMAT 30 /* Create physical format */ + + + +#ifdef PCBSKY +volatile extern BYTE Timer1, Timer2; /* 100Hz decrement timer */ +#endif + +//#ifdef PCBX9D +//volatile extern DWORD Timer1, Timer2; /* 100Hz decrement timer */ +//#endif + +//------------------------------------------------------------------------------ +/// Detect if SD card is connected +//------------------------------------------------------------------------------ +#define CardIsConnected() ( (PIOB->PIO_PDSR & PIO_PB7) == 0 ) + +extern uint32_t Card_ID[4] ; +extern uint32_t Card_SCR[2] ; +extern uint32_t Card_CSD[4] ; +extern uint32_t Sd_128_resp[4] ; +extern uint32_t Sd_rca ; +//extern uint32_t Cmd_55_resp ; + +extern uint32_t SD_SetBusWidth( uint32_t busWidth) ; +extern void SD_EnableHsMode( uint8_t hsEnable) ; +extern uint32_t SD_SetSpeed( uint32_t mciSpeed ) ; +extern void SD_Reset( uint8_t keepSettings) ; +extern uint32_t sd_cmd55( void ) ; +extern uint32_t sd_acmd41( void ) ; +extern uint32_t sd_cmd2( void ) ; +extern uint32_t sd_cmd3( void ) ; +extern uint32_t sd_cmd7( void ) ; +extern uint32_t sd_cmd9( void ) ; +extern uint32_t sd_cmd16( void ) ; +extern uint32_t sd_acmd6( void ) ; +extern uint32_t sd_acmd51( uint32_t *presult ) ; +extern uint32_t sd_cmd13( uint32_t *status) ; +extern void sd_poll_10mS( void ) ; +#ifdef PCBX9D +extern void sdPoll10ms( void ) ; +extern void sdInit( void ) ; +#endif +extern uint32_t sd_card_ready( void ) ; +extern uint32_t sd_read_block( uint32_t block_no, uint32_t *data ) ; + +extern DWORD socket_is_empty( void ) ; + +extern int8_t SD_ReadSectors(uint8_t *buff, uint32_t sector, uint32_t count) ; +extern int8_t SD_WriteSectors(uint8_t *buff, uint32_t sector, uint32_t count) ; + +#endif diff --git a/radio/bootloader/include/drivers.h b/radio/bootloader/include/drivers.h new file mode 100644 index 000000000..bca87090c --- /dev/null +++ b/radio/bootloader/include/drivers.h @@ -0,0 +1,74 @@ +#ifndef drivers_h +#define drivers_h + + +extern volatile uint32_t Spi_complete ; + +extern void putEvent( register uint8_t evt) ; + +extern void per10ms( void ) ; +extern uint8_t getEvent( void ) ; +extern void pauseEvents(uint8_t event) ; +extern void killEvents(uint8_t event) ; +extern void init_spi( void ) ; +extern void end_spi( void ) ; + + +//------------------------------------------------------------------------------ +/// Detect if SD card is connected +//------------------------------------------------------------------------------ +#ifdef PCBSKY +#define CardIsConnected() ( (PIOB->PIO_PDSR & PIO_PB7) == 0 ) +#endif + +extern uint32_t Card_ID[4] ; +extern uint32_t Card_SCR[2] ; +extern uint32_t Card_CSD[4] ; +extern uint32_t Sd_128_resp[4] ; +extern uint32_t Sd_rca ; +//extern uint32_t Cmd_55_resp ; + +extern uint32_t Card_state ; + +extern uint32_t SD_SetBusWidth( uint32_t busWidth) ; +extern void SD_EnableHsMode( uint8_t hsEnable) ; +extern uint32_t SD_SetSpeed( uint32_t mciSpeed ) ; +extern void SD_Reset( uint8_t keepSettings) ; +extern uint32_t sd_cmd55( void ) ; +extern uint32_t sd_acmd41( void ) ; +extern uint32_t sd_cmd2( void ) ; +extern uint32_t sd_cmd3( void ) ; +extern uint32_t sd_cmd7( void ) ; +extern uint32_t sd_cmd9( void ) ; +extern uint32_t sd_cmd17( uint32_t address, uint32_t *presult ) ; +extern uint32_t sd_acmd6( void ) ; +extern uint32_t sd_acmd51( uint32_t *presult ) ; +extern void sd_poll_10mS( void ) ; +extern uint32_t sd_card_ready( void ) ; +extern uint32_t sd_read_block( uint32_t block_no, uint32_t *data ) ; + +class Key +{ +#define FILTERBITS 4 +#define FFVAL ((1< + * - Andreas Weitl + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Gabriel Birkus + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * opentx is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef eeprom_rlc_h +#define eeprom_rlc_h + +#include + +#if !defined(EESIZE) + #define EESIZE (32*1024) +#endif + +//uint32_t ee32_check_finished( void ) ; + +#endif diff --git a/radio/bootloader/include/ersky9x.h b/radio/bootloader/include/ersky9x.h new file mode 100644 index 000000000..207188b22 --- /dev/null +++ b/radio/bootloader/include/ersky9x.h @@ -0,0 +1,758 @@ +/* + * Author - Mike Blandford + * + * Based on er9x by Erez Raviv + * + * Based on th9x -> http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +// This version for ARM based ERSKY9X board + +#ifndef ersky9x_h +#define ersky9x_h + +#include + +#define FIX_MODE 1 + +#ifdef SIMU +#include "simpgmspace.h" +#else +// Items set to make things compile, will need to be sorted eventually +#define assert(x) +#ifdef PCBSKY +#define wdt_reset() (WDT->WDT_CR = 0xA5000001) +#endif +#ifdef PCBX9D +#define wdt_reset() (IWDG->KR = 0x0000AAAAL) +#endif +#endif + +#define VERSION "V0.26" + +#define GVARS 1 + +//#define DATE_STR "xx.xx.2012" +//#define TIME_STR "xx:xx:xx" +//#define SUB_VERS VERSION +//#define SVN_VERS "trunk-rxxx" +//#define MOD_VERS "Normal" + +//#define STR2(s) #s +//#define DEFNUMSTR(s) STR2(s) + +extern const char stamp1[] ; +extern const char stamp2[] ; +extern const char stamp3[] ; +extern const char stamp4[] ; +extern const char stamp5[] ; + +//extern const char *Str_OFF ; +//extern const char *Str_ON ; +//extern const char *Str_Switches ; +//extern const char *Str_Switch_warn ; + +#define CPU_INT int32_t +#define CPU_UINT uint32_t + +#define BITMASK(bit) (1<<(bit)) + +extern const char * const *Language ; +extern const char * const English[] ; +extern const char * const French[] ; +extern const char * const German[] ; +extern const char * const Norwegian[] ; +extern const char * const Swedish[] ; + +#define PSTR(a) Language[a] +#define XPSTR(a) (char *)a + +#define PROGMEM const unsigned char +#define strcpy_P(a,b) strcpy(a,b) +#define strncpy_P(a,b,c) strncpy(a,b,c) +#define pgm_read_byte(p) (*(p)) + + +#ifdef PCBX9D + #define NUMBER_ANALOG 9 +#else +#ifdef REVX +#define NUMBER_ANALOG 10 +#define CURRENT_ANALOG 8 +#else + #ifdef REVB + #define NUMBER_ANALOG 9 + #define CURRENT_ANALOG 8 + #else + #define NUMBER_ANALOG 8 + #endif +#endif +#endif + +#define DIM(arr) (sizeof((arr))/sizeof((arr)[0])) + +enum EnumKeys { + KEY_MENU , + KEY_EXIT , + KEY_DOWN , + KEY_UP , + KEY_RIGHT , + KEY_LEFT , + TRM_LH_DWN , + TRM_LH_UP , + TRM_LV_DWN , + TRM_LV_UP , + TRM_RV_DWN , + TRM_RV_UP , + TRM_RH_DWN , + TRM_RH_UP , + BTN_RE, + +#ifdef PCBSKY + //SW_NC , + //SW_ON , + SW_ThrCt , + SW_RuddDR , + SW_ElevDR , + SW_ID0 , + SW_ID1 , + SW_ID2 , + SW_AileDR , + SW_Gear , + SW_Trainer +#endif + +#ifdef PCBX9D + SW_SA0, + SW_SA1, + SW_SA2, + SW_SB0, + SW_SB1, + SW_SB2, + SW_SC0, + SW_SC1, + SW_SC2, + SW_SD0, + SW_SD1, + SW_SD2, + SW_SE0, + SW_SE1, + SW_SE2, + SW_SF0, + SW_SF2, + SW_SG0, + SW_SG1, + SW_SG2, + SW_SH0, + SW_SH2 +#endif +}; + +// c17-c24 added for timer mode A display +//#define CURV_STR "\003---x>0x<0|x|f>0f<0|f|c1 c2 c3 c4 c5 c6 c7 c8 c9 c10c11c12c13c14c15c16c17c18c19c20c21c22c23c24" +#define CURVE_BASE 7 + +//#define CSWITCH_STR "---- v>ofs vofs|v|v2 ""v1=v2 ""v1<=v2 TimeOff" +#define CSW_LEN_FUNC 7 + + +#define CS_OFF 0 +#define CS_VPOS 1 //v>offset +#define CS_VNEG 2 //voffset +#define CS_ANEG 4 //|v| inline t min(t a, t b){ return a inline t max(t a, t b){ return a>b?a:b; } +template inline t limit(t mi, t x, t ma){ return min(max(mi,x),ma); } + +// This doesn't need protection on this processor +#define get_tmr10ms() g_tmr10ms + +#define sysFLAG_OLD_EEPROM (0x01) +extern uint8_t sysFlags; +extern uint8_t StickScrollAllowed ; + +const char s_charTab[]=" ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789_-."; +#define NUMCHARS (sizeof(s_charTab)-1) + +///number of real input channels (1-9) plus virtual input channels X1-X4 +#define PPM_BASE MIX_CYC3 +#define CHOUT_BASE (PPM_BASE+NUM_PPM) + +//extern const char *Str_telemItems ; +extern const int8_t TelemIndex[] ; +extern int16_t convertTelemConstant( int8_t channel, int8_t value) ; +#define NUM_TELEM_ITEMS 35 + +#define NUM_XCHNRAW (CHOUT_BASE+NUM_CHNOUT) // NUMCH + P1P2P3+ AIL/RUD/ELE/THR + MAX/FULL + CYC1/CYC2/CYC3 +#define NUM_SKYXCHNRAW (CHOUT_BASE+NUM_SKYCHNOUT) // NUMCH + P1P2P3+ AIL/RUD/ELE/THR + MAX/FULL + CYC1/CYC2/CYC3 +///number of real output channels (CH1-CH8) plus virtual output channels X1-X4 +#define NUM_XCHNOUT (NUM_CHNOUT) //(NUM_CHNOUT)//+NUM_VIRT) +#define NUM_SKYXCHNOUT (NUM_SKYCHNOUT) //(NUM_CHNOUT)//+NUM_VIRT) + +#define MIX_3POS (NUM_SKYXCHNRAW+1) + +inline int32_t calc100toRESX(register int8_t x) +{ + return ((uint32_t)x*655)>>6 ; +} + +inline int16_t calc1000toRESX( register int32_t x) // improve calc time by Pat MacKenzie +{ + register int32_t y = x>>5; + x+=y; + y=y>>2; + x-=y; + return x+(y>>2); + // return x + x/32 - x/128 + x/512; +} + +extern uint32_t Current_used ; +extern uint16_t Current_max ; +extern uint16_t MAh_used ; +extern uint16_t Run_time ; + +#ifdef FIX_MODE +extern const char stickScramble[] ; +//extern const char modeFix[] ; +uint8_t modeFixValue( uint8_t value ) ; +#else +extern const char modn12x3[] ; +#endif + +extern const uint8_t bchout_ar[] ; + +//convert from mode 1 to mode g_eeGeneral.stickMode +//NOTICE! => 1..4 -> 1..4 +extern uint8_t convert_mode_helper(uint8_t x) ; + +#define CONVERT_MODE(x) (((x)<=4) ? convert_mode_helper(x) : (x)) +//#define CHANNEL_ORDER(x) (chout_ar[g_eeGeneral.templateSetup*4 + (x)-1]) +#define CHANNEL_ORDER(x) ( ( (bchout_ar[g_eeGeneral.templateSetup] >> (6-(x-1) * 2)) & 3 ) + 1 ) +#define THR_STICK (2-(g_eeGeneral.stickMode&1)) +#define ELE_STICK (1+(g_eeGeneral.stickMode&1)) +#define AIL_STICK ((g_eeGeneral.stickMode&2) ? 0 : 3) +#define RUD_STICK ((g_eeGeneral.stickMode&2) ? 3 : 0) + +#define STORE_MODELVARS_TRIM eeDirty(EE_MODEL|EE_TRIM) +#define STORE_MODELVARS eeDirty(EE_MODEL) +#define STORE_GENERALVARS eeDirty(EE_GENERAL) + +#ifdef PCBSKY +#define BACKLIGHT_ON (PWM->PWM_CH_NUM[0].PWM_CDTY = g_eeGeneral.bright) +#define BACKLIGHT_OFF (PWM->PWM_CH_NUM[0].PWM_CDTY = 100) +#endif + +#ifdef PCBX9D +extern void backlight_on( void ) ; +extern void backlight_off( void ) ; +#define BACKLIGHT_ON backlight_on() +#define BACKLIGHT_OFF backlight_off() +#endif + +// Options for mainSequence() +#define NO_MENU 1 +#define MENUS 0 + +extern uint16_t evalChkSum( void ) ; + +struct t_calib +{ + int16_t midVals[8]; + int16_t loVals[8]; + int16_t hiVals[8]; + uint8_t idxState; +} ; + +union t_xmem +{ +// struct MixTab s_mixTab[MAX_MIXERS+NUM_XCHNOUT+1] ; + struct t_calib Cal_data ; +#ifndef CPUARM + char buf[sizeof(g_model.name)+5]; +#endif +//#if defined(CPUM128) || defined(CPUM2561) +// uint8_t file_buffer[256]; +//#else +// uint8_t file_buffer[128]; +//#endif +} ; + +extern union t_xmem Xmem ; + + +typedef void (*MenuFuncP)(uint8_t event); + +typedef struct +{ + unsigned char second; //enter the current time, date, month, and year + unsigned char minute; + unsigned char hour; + unsigned char date; + unsigned char month; + unsigned int year; + } t_time ; + +extern t_time Time ; + +extern bool checkIncDec_Ret;//global helper vars +extern uint8_t s_editMode; //global editmode + +int16_t checkIncDec16(uint8_t event, int16_t i_pval, int16_t i_min, int16_t i_max, uint8_t i_flags); +int8_t checkIncDec(uint8_t event, int8_t i_val, int8_t i_min, int8_t i_max, uint8_t i_flags); +int8_t checkIncDec_hm(uint8_t event, int8_t i_val, int8_t i_min, int8_t i_max); +int8_t checkIncDec_vm(uint8_t event, int8_t i_val, int8_t i_min, int8_t i_max); +int8_t checkIncDec_hg(uint8_t event, int8_t i_val, int8_t i_min, int8_t i_max); + +#define CHECK_INCDEC_H_GENVAR( event, var, min, max) \ + var = checkIncDec_hg(event,var,min,max) + +#define CHECK_INCDEC_H_MODELVAR( event, var, min, max) \ + var = checkIncDec_hm(event,var,min,max) + +#define CHECK_INCDEC_MODELSWITCH(event, var, min, max) \ + var = checkIncDec(event,var,min,max,EE_MODEL|INCDEC_SWITCH) + +#define CHECK_INCDEC_GENERALSWITCH( event, var, min, max) \ + var = checkIncDec(event,var,min,max,EE_GENERAL|INCDEC_SWITCH) + + +extern uint8_t heartbeat ; +extern int16_t g_chans512[NUM_SKYCHNOUT]; +//extern uint8_t eeprom[4096] ; + +uint8_t char2idx(char c); +char idx2char(uint8_t idx); + +//extern volatile uint32_t Timer2_count ; // Modified in interrupt routine +extern volatile uint16_t g_tmr10ms ; +extern volatile uint8_t g_blinkTmr10ms; +extern volatile uint8_t tick10ms ; +extern uint32_t Master_frequency ; + +extern void alert(const char * s, bool defaults=false); +extern void message(const char * s); + +void resetTimer(); + + +//extern uint8_t Timer2_running ; +//extern uint16_t Timer2 ; +//void resetTimer2( void ) ; + +extern void putsTime(uint8_t x,uint8_t y,int16_t tme,uint8_t att,uint8_t att2) ; +extern void putsVolts(uint8_t x,uint8_t y, uint8_t volts, uint8_t att) ; +extern void putsVBat(uint8_t x,uint8_t y,uint8_t att) ; +extern void putsVBat(uint8_t x,uint8_t y,uint8_t att) ; +extern void putsChnRaw(uint8_t x,uint8_t y,uint8_t idx,uint8_t att) ; +extern void putsChn(uint8_t x,uint8_t y,uint8_t idx1,uint8_t att) ; +extern void putsDrSwitches(uint8_t x,uint8_t y,int8_t idx1,uint8_t att) ; //, bool nc) ; +extern void putsTmrMode(uint8_t x, uint8_t y, uint8_t attr, uint8_t timer, uint8_t type ) ; +extern const char *get_switches_string( void ) ; + +extern void interrupt5ms() ; + + +extern int16_t intpol(int16_t x, uint8_t idx); + +extern uint16_t anaIn(uint8_t chan) ; + +extern int8_t phyStick[4] ; +extern int16_t ex_chans[NUM_SKYCHNOUT]; + +extern void modelDefault( uint8_t id ) ; +extern uint8_t VoiceCheckFlag ; + +//void eeWaitComplete( void ) ; +void eeDirty(uint8_t msk); +//void eeCheck(bool immediately=false ) ; +void eeReadAll( void ) ; +//void eeLoadModelName(uint8_t id,char*buf,uint8_t len); +//uint16_t eeFileSize(uint8_t id); +//void eeLoadModel(uint8_t id); +//void eeSaveModel(uint8_t id); +bool eeDuplicateModel(uint8_t id); +//bool eeModelExists(uint8_t id); + +extern char idx2char(uint8_t idx) ; +extern uint8_t char2idx(char c) ; + +extern int16_t g_ppmIns[]; +extern uint8_t ppmInState ; //0=unsync 1..8= wait for value i-1 +extern uint8_t ppmInValid ; + +/// goto given Menu, but substitute current menu in menuStack +extern void chainMenu(MenuFuncP newMenu); +/// goto given Menu, store current menu in menuStack +extern void pushMenu(MenuFuncP newMenu); +///deliver address of last menu which was popped from +extern MenuFuncP lastPopMenu(); +/// return to last menu in menustack +/// if uppermost is set true, thenmenu return to uppermost menu in menustack +void popMenu(bool uppermost=false); + +#define NO_TRAINER 0x01 +#define NO_INPUT 0x02 + +// Timeout, in seconds, stick scroll remains active +#define STICK_SCROLL_TIMEOUT 5 + +extern bool getSwitch(int8_t swtch, bool nc, uint8_t level = 0 ) ; +extern int8_t getMovedSwitch( void ) ; +extern uint8_t g_vbat100mV ; +//extern uint16_t Timer2 ; +extern void doSplash( void ) ; +extern void mainSequence( uint32_t no_menu ) ; +#ifdef FRSKY +extern uint8_t putsTelemValue(uint8_t x, uint8_t y, uint8_t val, uint8_t channel, uint8_t att, uint8_t scale) ; +extern void telem_byte_to_bt( uint8_t data ) ; +extern uint16_t scale_telem_value( uint16_t val, uint8_t channel, uint8_t times2, uint8_t *p_att ) ; +#endif +uint8_t telemItemValid( uint8_t index ) ; + +extern int16_t get_telemetry_value( int8_t channel ) ; + +extern void putVoiceQueue( uint16_t value ) ; +void voice_numeric( int16_t value, uint8_t num_decimals, uint8_t units_index ) ; +extern void voice_telem_item( int8_t index ) ; +extern uint8_t *cpystr( uint8_t *dest, uint8_t *source ) ; +extern int16_t m_to_ft( int16_t metres ) ; + +uint8_t getCurrentSwitchStates( void ) ; + +extern uint32_t check_soft_power( void ) ; +extern uint32_t getFlightPhase( void ) ; +extern int16_t getRawTrimValue( uint8_t phase, uint8_t idx ) ; +extern int16_t getTrimValue( uint8_t phase, uint8_t idx ) ; +extern void setTrimValue(uint8_t phase, uint8_t idx, int16_t trim) ; + +extern void checkSwitches( void ) ; +extern void setLanguage( void ) ; + +struct t_timer +{ + uint16_t s_sum ; + uint8_t lastSwPos ; + uint8_t sw_toggled ; + uint16_t s_timeCumSw ; //laufzeit in 1/16 sec + uint8_t s_timerState ; + uint16_t s_timeCumThr ; //gewichtete laufzeit in 1/16 sec + uint16_t s_timeCum16ThrP ; //gewichtete laufzeit in 1/16 sec + int16_t s_timerVal ; +} ; + +extern struct t_timer s_timer[] ; + +// Rotary encoder movement states +#define ROTARY_MENU_LR 0 +#define ROTARY_MENU_UD 1 +#define ROTARY_SUBMENU_LR 2 +#define ROTARY_VALUE 3 + +extern uint8_t RotaryState ; // Defaults to ROTARY_MENU_LR + +#if GVARS +extern int8_t REG(int8_t x, int8_t min, int8_t max) ; +#endif + +enum PowerState +{ + e_power_on, + e_power_trainer, + e_power_usb, + e_power_off +} ; + +struct t_p1 +{ + int16_t p1val ; + int16_t p1valdiff ; + int16_t p1valprev ; + int16_t p2valprev ; + int16_t p3valprev ; +} ; + +extern struct t_p1 P1values ; + +#ifdef PCBSKY +extern uint16_t ResetReason ; +#endif +#ifdef PCBX9D +extern uint32_t ResetReason ; +#endif +extern uint8_t unexpectedShutdown ; +extern uint8_t SdMounted ; + +#ifdef PCBX9D +#include "stm32f2xx.h" +#include "rtc.h" +#include "stm32f2xx_rtc.h" +void rtcSetTime( t_time *t ) ; +void rtc_gettime( t_time *t ) ; +void rtcInit( void ) ; +#endif + +extern void setVolume( uint8_t value ) ; +extern uint8_t HoldVolume ; + +#ifdef PCBX9D +#define INTERNAL_MODULE 0 +#define EXTERNAL_MODULE 1 +#define TRAINER_MODULE 2 +#endif + +#endif diff --git a/radio/bootloader/include/ff.h b/radio/bootloader/include/ff.h new file mode 100644 index 000000000..6e1f260e2 --- /dev/null +++ b/radio/bootloader/include/ff.h @@ -0,0 +1,575 @@ +/* + * Authors (alphabetical order) + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * open9x is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +/*---------------------------------------------------------------------------/ +/ FatFs - FAT file system module include file R0.08a (C)ChaN, 2010 +/----------------------------------------------------------------------------/ +/ FatFs module is a generic FAT file system module for small embedded systems. +/ This is a free software that opened for education, research and commercial +/ developments under license policy of following trems. +/ +/ Copyright (C) 2010, ChaN, all right reserved. +/ +/ * The FatFs module is a free software and there is NO WARRANTY. +/ * No restriction on use. You can use, modify and redistribute it for +/ personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY. +/ * Redistributions of source code must retain the above copyright notice. +/ +/----------------------------------------------------------------------------*/ + +#ifndef _FATFS +#define _FATFS 8255 /* Revision ID */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "inttypes.h" +#include "integer.h" /* Basic integer types */ +#include "ffconf.h" /* FatFs configuration options */ + +#if _FATFS != _FFCONF +#error Wrong configuration file (ffconf.h). +#endif + + +/* DBCS code ranges and SBCS extend char conversion table */ + +#if _CODE_PAGE == 932 /* Japanese Shift-JIS */ +#define _DF1S 0x81 /* DBC 1st byte range 1 start */ +#define _DF1E 0x9F /* DBC 1st byte range 1 end */ +#define _DF2S 0xE0 /* DBC 1st byte range 2 start */ +#define _DF2E 0xFC /* DBC 1st byte range 2 end */ +#define _DS1S 0x40 /* DBC 2nd byte range 1 start */ +#define _DS1E 0x7E /* DBC 2nd byte range 1 end */ +#define _DS2S 0x80 /* DBC 2nd byte range 2 start */ +#define _DS2E 0xFC /* DBC 2nd byte range 2 end */ + +#elif _CODE_PAGE == 936 /* Simplified Chinese GBK */ +#define _DF1S 0x81 +#define _DF1E 0xFE +#define _DS1S 0x40 +#define _DS1E 0x7E +#define _DS2S 0x80 +#define _DS2E 0xFE + +#elif _CODE_PAGE == 949 /* Korean */ +#define _DF1S 0x81 +#define _DF1E 0xFE +#define _DS1S 0x41 +#define _DS1E 0x5A +#define _DS2S 0x61 +#define _DS2E 0x7A +#define _DS3S 0x81 +#define _DS3E 0xFE + +#elif _CODE_PAGE == 950 /* Traditional Chinese Big5 */ +#define _DF1S 0x81 +#define _DF1E 0xFE +#define _DS1S 0x40 +#define _DS1E 0x7E +#define _DS2S 0xA1 +#define _DS2E 0xFE + +#elif _CODE_PAGE == 437 /* U.S. (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F,0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 720 /* Arabic (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x45,0x41,0x84,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x49,0x49,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 737 /* Greek (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \ + 0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xE7,0xE8,0xF1,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 775 /* Baltic (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 850 /* Multilingual Latin 1 (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 852 /* Latin 2 (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F,0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0x9F, \ + 0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF} + +#elif _CODE_PAGE == 855 /* Cyrillic (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F,0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \ + 0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \ + 0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 857 /* Turkish (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x98,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \ + 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0x59,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 858 /* Multilingual Latin 1 + Euro (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 862 /* Hebrew (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 866 /* Russian (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x90,0x91,0x92,0x93,0x9d,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 874 /* Thai (OEM, Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 1250 /* Central Europe (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xA3,0xB4,0xB5,0xB6,0xB7,0xB8,0xA5,0xAA,0xBB,0xBC,0xBD,0xBC,0xAF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF} + +#elif _CODE_PAGE == 1251 /* Cyrillic (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x82,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x80,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \ + 0xA0,0xA2,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB2,0xA5,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xA3,0xBD,0xBD,0xAF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF} + +#elif _CODE_PAGE == 1252 /* Latin 1 (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0xAd,0x9B,0x8C,0x9D,0xAE,0x9F, \ + 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F} + +#elif _CODE_PAGE == 1253 /* Greek (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xA2,0xB8,0xB9,0xBA, \ + 0xE0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xFB,0xBC,0xFD,0xBF,0xFF} + +#elif _CODE_PAGE == 1254 /* Turkish (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x9D,0x9E,0x9F, \ + 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F} + +#elif _CODE_PAGE == 1255 /* Hebrew (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 1256 /* Arabic (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x8C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x41,0xE1,0x41,0xE3,0xE4,0xE5,0xE6,0x43,0x45,0x45,0x45,0x45,0xEC,0xED,0x49,0x49,0xF0,0xF1,0xF2,0xF3,0x4F,0xF5,0xF6,0xF7,0xF8,0x55,0xFA,0x55,0x55,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 1257 /* Baltic (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xBC,0xBD,0xBE,0xAF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF} + +#elif _CODE_PAGE == 1258 /* Vietnam (OEM, Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0xAC,0x9D,0x9E,0x9F, \ + 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xEC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xFE,0x9F} + +#elif _CODE_PAGE == 1 /* ASCII (for only non-LFN cfg) */ +#define _DF1S 0 + +#else +#error Unknown code page + +#endif + + + +/* Definitions of volume management */ + +#if _MULTI_PARTITION /* Multiple partition configuration */ +#define LD2PD(vol) (VolToPart[vol].pd) /* Get physical drive# */ +#define LD2PT(vol) (VolToPart[vol].pt) /* Get partition# */ +typedef struct { + BYTE pd; /* Physical drive# */ + BYTE pt; /* Partition # (0-3) */ +} PARTITION; +extern const PARTITION VolToPart[]; /* Volume - Physical location resolution table */ + +#else /* Single partition configuration */ +#define LD2PD(vol) (vol) /* Logical drive# is bound to the same physical drive# */ +#define LD2PT(vol) 0 /* Always mounts the 1st partition */ + +#endif + + + +/* Type of path name strings on FatFs API */ + +#if _LFN_UNICODE /* Unicode string */ +#if !_USE_LFN +#error _LFN_UNICODE must be 0 in non-LFN cfg. +#endif +#ifndef _INC_TCHAR +typedef WCHAR TCHAR; +#define _T(x) L ## x +#define _TEXT(x) L ## x +#endif + +#else /* ANSI/OEM string */ +#ifndef _INC_TCHAR +typedef char TCHAR; +#define _T(x) x +#define _TEXT(x) x +#endif + +#endif + + + +/* File system object structure (FATFS) */ + +typedef struct { + BYTE fs_type; /* FAT sub-type (0:Not mounted) */ + BYTE drv; /* Physical drive number */ + BYTE csize; /* Sectors per cluster (1,2,4...128) */ + BYTE n_fats; /* Number of FAT copies (1,2) */ + BYTE wflag; /* win[] dirty flag (1:must be written back) */ + BYTE fsi_flag; /* fsinfo dirty flag (1:must be written back) */ + WORD id; /* File system mount ID */ + WORD n_rootdir; /* Number of root directory entries (FAT12/16) */ +#if _MAX_SS != 512 + WORD ssize; /* Bytes per sector (512,1024,2048,4096) */ +#endif +#if _FS_REENTRANT + _SYNC_t sobj; /* Identifier of sync object */ +#endif +#if !_FS_READONLY + DWORD last_clust; /* Last allocated cluster */ + DWORD free_clust; /* Number of free clusters */ + DWORD fsi_sector; /* fsinfo sector (FAT32) */ +#endif +#if _FS_RPATH + DWORD cdir; /* Current directory start cluster (0:root) */ +#endif + DWORD n_fatent; /* Number of FAT entries (= number of clusters + 2) */ + DWORD fsize; /* Sectors per FAT */ + DWORD fatbase; /* FAT start sector */ + DWORD dirbase; /* Root directory start sector (FAT32:Cluster#) */ + DWORD database; /* Data start sector */ + DWORD winsect; /* Current sector appearing in the win[] */ + BYTE win[_MAX_SS]; /* Disk access window for Directory, FAT (and Data on tiny cfg) */ +} FATFS; + + + +/* File object structure (FIL) */ + +typedef struct { + FATFS* fs; /* Pointer to the owner file system object */ + WORD id; /* Owner file system mount ID */ + BYTE flag; /* File status flags */ + BYTE pad1; + DWORD fptr; /* File read/write pointer (0 on file open) */ + DWORD fsize; /* File size */ + DWORD org_clust; /* File start cluster (0 when fsize==0) */ + DWORD curr_clust; /* Current cluster */ + DWORD dsect; /* Current data sector */ +#if !_FS_READONLY + DWORD dir_sect; /* Sector containing the directory entry */ + BYTE* dir_ptr; /* Ponter to the directory entry in the window */ +#endif +#if _USE_FASTSEEK + DWORD* cltbl; /* Pointer to the cluster link map table (null on file open) */ +#endif +#if _FS_SHARE + UINT lockid; /* File lock ID (index of file semaphore table) */ +#endif +#if !_FS_TINY + BYTE buf[_MAX_SS]; /* File data read/write buffer */ +#endif +} FIL; + + + +/* Directory object structure (DIR) */ + +typedef struct { + FATFS* fs; /* Pointer to the owner file system object */ + WORD id; /* Owner file system mount ID */ + WORD index; /* Current read/write index number */ + DWORD sclust; /* Table start cluster (0:Root dir) */ + DWORD clust; /* Current cluster */ + DWORD sect; /* Current sector */ + BYTE* dir; /* Pointer to the current SFN entry in the win[] */ + BYTE* fn; /* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */ +#if _USE_LFN + WCHAR* lfn; /* Pointer to the LFN working buffer */ + WORD lfn_idx; /* Last matched LFN index number (0xFFFF:No LFN) */ +#endif +} DIR; + + + +/* File status structure (FILINFO) */ + +typedef struct { + DWORD fsize; /* File size */ + WORD fdate; /* Last modified date */ + WORD ftime; /* Last modified time */ + BYTE fattrib; /* Attribute */ + TCHAR fname[13]; /* Short file name (8.3 format) */ +#if _USE_LFN + TCHAR* lfname; /* Pointer to the LFN buffer */ + UINT lfsize; /* Size of LFN buffer in TCHAR */ +#endif +} FILINFO; + + + +/* File function return code (FRESULT) */ + +typedef enum { + FR_OK = 0, // (0) Succeeded + FR_DISK_ERR, // (1) A hard error occured in the low level disk I/O layer + FR_INT_ERR, // (2) Assertion failed + FR_NOT_READY, // (3) The physical drive cannot work + FR_NO_FILE, // (4) Could not find the file + FR_NO_PATH, // (5) Could not find the path + FR_INVALID_NAME, // (6) The path name format is invalid + FR_DENIED, // (7) Acces denied due to prohibited access or directory full + FR_EXIST, // (8) Acces denied due to prohibited access + FR_INVALID_OBJECT, // (9) The file/directory object is invalid + FR_WRITE_PROTECTED, // (10) The physical drive is write protected + FR_INVALID_DRIVE, // (11) The logical drive number is invalid + FR_NOT_ENABLED, // (12) The volume has no work area + FR_NO_FILESYSTEM, // (13) There is no valid FAT volume on the physical drive + FR_MKFS_ABORTED, // (14) The f_mkfs() aborted due to any parameter error + FR_TIMEOUT, // (15) Could not get a grant to access the volume within defined period + FR_LOCKED, // (16) The operation is rejected according to the file shareing policy + FR_NOT_ENOUGH_CORE, // (17) LFN working buffer could not be allocated + FR_TOO_MANY_OPEN_FILES // (18) Number of open files > _FS_SHARE +} FRESULT; + + + +/*--------------------------------------------------------------*/ +/* FatFs module application interface */ + +FRESULT f_mount (BYTE, FATFS*); /* Mount/Unmount a logical drive */ +FRESULT f_open (FIL*, const TCHAR*, BYTE); /* Open or create a file */ +FRESULT f_read (FIL*, BYTE*, UINT, UINT*); /* Read data from a file */ +FRESULT f_lseek (FIL*, DWORD); /* Move file pointer of a file object */ +FRESULT f_close (FIL*); /* Close an open file object */ +FRESULT f_opendir (DIR*, const TCHAR*); /* Open an existing directory */ +FRESULT f_readdir (DIR*, FILINFO*); /* Read a directory item */ +FRESULT f_stat (const TCHAR*, FILINFO*); /* Get file status */ + +#if !_FS_READONLY +FRESULT f_write (FIL*, const BYTE *, UINT, UINT*); /* Write data to a file */ +FRESULT f_getfree (const TCHAR*, DWORD*, FATFS**); /* Get number of free clusters on the drive */ +FRESULT f_truncate (FIL*); /* Truncate file */ +FRESULT f_sync (FIL*); /* Flush cached data of a writing file */ +FRESULT f_unlink (const TCHAR*); /* Delete an existing file or directory */ +FRESULT f_mkdir (const TCHAR*); /* Create a new directory */ +FRESULT f_chmod (const TCHAR*, BYTE, BYTE); /* Change attriburte of the file/dir */ +FRESULT f_utime (const TCHAR*, const FILINFO*); /* Change timestamp of the file/dir */ +FRESULT f_rename (const TCHAR *oldf, const TCHAR *newf); /* Rename/Move a file or directory */ +#endif + +#if _USE_FORWARD +FRESULT f_forward (FIL*, UINT(*)(const BYTE*,UINT), UINT, UINT*); /* Forward data to the stream */ +#endif + +#if _USE_MKFS +FRESULT f_mkfs (BYTE, BYTE, UINT); /* Create a file system on the drive */ +#endif + +#if _FS_RPATH +FRESULT f_chdrive (BYTE); /* Change current drive */ +FRESULT f_chdir (const TCHAR*); /* Change current directory */ +FRESULT f_getcwd (TCHAR*, UINT); /* Get current directory */ +#endif + +#if _USE_STRFUNC +int f_putc (TCHAR, FIL*); /* Put a character to the file */ +int f_puts (const TCHAR*, FIL*); /* Put a string to the file */ +int f_printf (FIL*, const TCHAR*, ...); /* Put a formatted string to the file */ +TCHAR* f_gets (TCHAR*, int, FIL*); /* Get a string from the file */ +#ifndef EOF +#define EOF (-1) +#endif +#endif + +#define f_eof(fp) (((fp)->fptr == (fp)->fsize) ? 1 : 0) +#define f_error(fp) (((fp)->flag & FA__ERROR) ? 1 : 0) +#define f_tell(fp) ((fp)->fptr) +#define f_size(fp) ((fp)->fsize) + + + +/*--------------------------------------------------------------*/ +/* Additional user defined functions */ + +/* RTC function */ +#if !_FS_READONLY +extern uint32_t o9x_get_fattime (void); /* Returns 32-bit packed date and time */ +#endif + +/* Unicode support functions */ +#if _USE_LFN /* Unicode - OEM code conversion */ +WCHAR ff_convert (WCHAR, UINT); /* OEM-Unicode bidirectional conversion */ +WCHAR ff_wtoupper (WCHAR); /* Unicode upper-case conversion */ +#if _USE_LFN == 3 /* Memory functions */ +void* ff_memalloc (UINT); /* Allocate memory block */ +void ff_memfree (void*); /* Free memory block */ +#endif +#endif + +/* Sync functions */ +#if _FS_REENTRANT +int ff_cre_syncobj (BYTE, _SYNC_t*);/* Create a sync object */ +int ff_del_syncobj (_SYNC_t); /* Delete a sync object */ +int ff_req_grant (_SYNC_t); /* Lock sync object */ +void ff_rel_grant (_SYNC_t); /* Unlock sync object */ +#endif + + + + +/*--------------------------------------------------------------*/ +/* Flags and offset address */ + + +/* File access control and file status flags (FIL.flag) */ + +#define FA_READ 0x01 +#define FA_OPEN_EXISTING 0x00 +#define FA__ERROR 0x80 + +#if !_FS_READONLY +#define FA_WRITE 0x02 +#define FA_CREATE_NEW 0x04 +#define FA_CREATE_ALWAYS 0x08 +#define FA_OPEN_ALWAYS 0x10 +#define FA__WRITTEN 0x20 +#define FA__DIRTY 0x40 +#endif + + +/* FAT sub type (FATFS.fs_type) */ + +#define FS_FAT12 1 +#define FS_FAT16 2 +#define FS_FAT32 3 + + +/* File attribute bits for directory entry */ + +#define AM_RDO 0x01 /* Read only */ +#define AM_HID 0x02 /* Hidden */ +#define AM_SYS 0x04 /* System */ +#define AM_VOL 0x08 /* Volume label */ +#define AM_LFN 0x0F /* LFN entry */ +#define AM_DIR 0x10 /* Directory */ +#define AM_ARC 0x20 /* Archive */ +#define AM_MASK 0x3F /* Mask of defined bits */ + + +/* Fast seek function */ +#define CREATE_LINKMAP 0xFFFFFFFF + + +/*--------------------------------*/ +/* Multi-byte word access macros */ + +#if _WORD_ACCESS == 1 /* Enable word access to the FAT structure */ +#define LD_WORD(ptr) (WORD)(*(WORD*)(BYTE*)(ptr)) +#define LD_DWORD(ptr) (DWORD)(*(DWORD*)(BYTE*)(ptr)) +#define ST_WORD(ptr,val) *(WORD*)(BYTE*)(ptr)=(WORD)(val) +#define ST_DWORD(ptr,val) *(DWORD*)(BYTE*)(ptr)=(DWORD)(val) +#else /* Use byte-by-byte access to the FAT structure */ +#define LD_WORD(ptr) (WORD)(((WORD)*(BYTE*)((ptr)+1)<<8)|(WORD)*(BYTE*)(ptr)) +#define LD_DWORD(ptr) (DWORD)(((DWORD)*(BYTE*)((ptr)+3)<<24)|((DWORD)*(BYTE*)((ptr)+2)<<16)|((WORD)*(BYTE*)((ptr)+1)<<8)|*(BYTE*)(ptr)) +#define ST_WORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *(BYTE*)((ptr)+1)=(BYTE)((WORD)(val)>>8) +#define ST_DWORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *(BYTE*)((ptr)+1)=(BYTE)((WORD)(val)>>8); *(BYTE*)((ptr)+2)=(BYTE)((DWORD)(val)>>16); *(BYTE*)((ptr)+3)=(BYTE)((DWORD)(val)>>24) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _FATFS */ diff --git a/radio/bootloader/include/ffconf.h b/radio/bootloader/include/ffconf.h new file mode 100644 index 000000000..8b21864ee --- /dev/null +++ b/radio/bootloader/include/ffconf.h @@ -0,0 +1,231 @@ +/* + * Authors (alphabetical order) + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * open9x is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +/*---------------------------------------------------------------------------/ +/ FatFs - FAT file system module configuration file R0.08a (C)ChaN, 2010 +/----------------------------------------------------------------------------/ +/ +/ CAUTION! Do not forget to make clean the project after any changes to +/ the configuration options. +/ +/----------------------------------------------------------------------------*/ +#ifndef _FFCONF +#define _FFCONF 8255 /* Revision ID */ + + +/*---------------------------------------------------------------------------/ +/ Function and Buffer Configurations +/----------------------------------------------------------------------------*/ + +#define _FS_TINY 1 /* 0:Normal or 1:Tiny */ +/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system +/ object instead of the sector buffer in the individual file object for file +/ data transfer. This reduces memory consumption 512 bytes each file object. */ + +#ifdef BOOT +#define _FS_READONLY 1 /* 0:Read/Write or 1:Read only */ +#else +#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */ +#endif +/* Setting _FS_READONLY to 1 defines read only configuration. This removes +/ writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename, +/ f_truncate and useless f_getfree. */ + +#ifdef BOOT +#define _FS_MINIMIZE 1 /* 0 to 3 */ +#else +#define _FS_MINIMIZE 0 /* 0 to 3 */ +#endif +/* The _FS_MINIMIZE option defines minimization level to remove some functions. +/ +/ 0: Full function. +/ 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename +/ are removed. +/ 2: f_opendir and f_readdir are removed in addition to 1. +/ 3: f_lseek is removed in addition to 2. */ + + +#ifdef BOOT +#define _USE_STRFUNC 0 /* 0:Disable or 1/2:Enable */ +#else +#define _USE_STRFUNC 1 /* 0:Disable or 1/2:Enable */ +#endif +/* To enable string functions, set _USE_STRFUNC to 1 or 2. */ + + +#define _USE_MKFS 1 /* 0:Disable or 1:Enable */ +/* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */ + + +#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */ +/* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */ + + +#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */ +/* To enable fast seek feature, set _USE_FASTSEEK to 1. */ + + + +/*---------------------------------------------------------------------------/ +/ Locale and Namespace Configurations +/----------------------------------------------------------------------------*/ + +#define _CODE_PAGE 437 +/* The _CODE_PAGE specifies the OEM code page to be used on the target system. +/ Incorrect setting of the code page can cause a file open failure. +/ +/ 932 - Japanese Shift-JIS (DBCS, OEM, Windows) +/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows) +/ 949 - Korean (DBCS, OEM, Windows) +/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows) +/ 1250 - Central Europe (Windows) +/ 1251 - Cyrillic (Windows) +/ 1252 - Latin 1 (Windows) +/ 1253 - Greek (Windows) +/ 1254 - Turkish (Windows) +/ 1255 - Hebrew (Windows) +/ 1256 - Arabic (Windows) +/ 1257 - Baltic (Windows) +/ 1258 - Vietnam (OEM, Windows) +/ 437 - U.S. (OEM) +/ 720 - Arabic (OEM) +/ 737 - Greek (OEM) +/ 775 - Baltic (OEM) +/ 850 - Multilingual Latin 1 (OEM) +/ 858 - Multilingual Latin 1 + Euro (OEM) +/ 852 - Latin 2 (OEM) +/ 855 - Cyrillic (OEM) +/ 866 - Russian (OEM) +/ 857 - Turkish (OEM) +/ 862 - Hebrew (OEM) +/ 874 - Thai (OEM, Windows) +/ 1 - ASCII only (Valid for non LFN cfg.) +*/ + + +#define _USE_LFN 2 /* 0 to 3 */ +#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */ +/* The _USE_LFN option switches the LFN support. +/ +/ 0: Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect. +/ 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant. +/ 2: Enable LFN with dynamic working buffer on the STACK. +/ 3: Enable LFN with dynamic working buffer on the HEAP. +/ +/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. To enable LFN, +/ Unicode handling functions ff_convert() and ff_wtoupper() must be added +/ to the project. When enable to use heap, memory control functions +/ ff_memalloc() and ff_memfree() must be added to the project. */ + + +#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */ +/* To switch the character code set on FatFs API to Unicode, +/ enable LFN feature and set _LFN_UNICODE to 1. */ + + +#define _FS_RPATH 2 /* 0 to 2 */ +/* The _FS_RPATH option configures relative path feature. +/ +/ 0: Disable relative path feature and remove related functions. +/ 1: Enable relative path. f_chdrive() and f_chdir() are available. +/ 2: f_getcwd() is available in addition to 1. +/ +/ Note that output of the f_readdir fnction is affected by this option. */ + + + +/*---------------------------------------------------------------------------/ +/ Physical Drive Configurations +/----------------------------------------------------------------------------*/ + +#define _VOLUMES 1 +/* Number of volumes (logical drives) to be used. */ + + +#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */ +/* Maximum sector size to be handled. +/ Always set 512 for memory card and hard disk but a larger value may be +/ required for floppy disk (512/1024) and optical disk (512/2048). +/ When _MAX_SS is larger than 512, GET_SECTOR_SIZE command must be implememted +/ to the disk_ioctl function. */ + + +#define _MULTI_PARTITION 0 /* 0:Single partition or 1:Multiple partition */ +/* When set to 0, each volume is bound to the same physical drive number and +/ it can mount only first primaly partition. When it is set to 1, each volume +/ is tied to the partitions listed in VolToPart[]. */ + + +#define _USE_ERASE 0 /* 0:Disable or 1:Enable */ +/* To enable sector erase feature, set _USE_ERASE to 1. */ + + + +/*---------------------------------------------------------------------------/ +/ System Configurations +/----------------------------------------------------------------------------*/ + +#define _WORD_ACCESS 0 /* 0 or 1 */ +/* Set 0 first and it is always compatible with all platforms. The _WORD_ACCESS +/ option defines which access method is used to the word data on the FAT volume. +/ +/ 0: Byte-by-byte access. +/ 1: Word access. Do not choose this unless following condition is met. +/ +/ When the byte order on the memory is big-endian or address miss-aligned word +/ access results incorrect behavior, the _WORD_ACCESS must be set to 0. +/ If it is not the case, the value can also be set to 1 to improve the +/ performance and code size. */ + + +/* Include a header file here to define sync object types on the O/S */ +/* #include , , or ohters. */ + +#define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */ +#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */ +#define _SYNC_t HANDLE /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */ + +/* The _FS_REENTRANT option switches the reentrancy of the FatFs module. +/ +/ 0: Disable reentrancy. _SYNC_t and _FS_TIMEOUT have no effect. +/ 1: Enable reentrancy. Also user provided synchronization handlers, +/ ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj +/ function must be added to the project. */ + + +#define _FS_SHARE 0 /* 0:Disable or >=1:Enable */ +/* To enable file shareing feature, set _FS_SHARE to 1 or greater. The value + defines how many files can be opened simultaneously. */ + + +#endif /* _FFCONFIG */ diff --git a/radio/bootloader/include/file.h b/radio/bootloader/include/file.h new file mode 100644 index 000000000..f72d8f47b --- /dev/null +++ b/radio/bootloader/include/file.h @@ -0,0 +1,116 @@ +/* + * Author - Erez Raviv + * + * Based on th9x -> http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef file_h +#define file_h + +#include +#include + + +extern void init_eeprom( void ) ; + +extern uint32_t ee32_check_finished( void ) ; +extern void ee32StoreGeneral( void ) ; +extern void ee32StoreModel( uint8_t modelNumber, uint8_t trim ) ; +extern bool ee32LoadGeneral( void ) ; +extern void ee32LoadModel(uint8_t id) ; +extern void ee32WaitLoadModel(uint8_t id) ; +extern void ee32_delete_model( uint8_t id ) ; +extern bool ee32ModelExists(uint8_t id) ; +extern void ee32_process( void ) ; +extern bool ee32CopyModel( uint8_t dst, uint8_t src ) ; +extern void ee32SwapModels( uint8_t id1, uint8_t id2 ) ; +extern uint32_t ee32_read_512( uint32_t sector, uint8_t *buffer ) ; + + +struct t_file_entry +{ + uint32_t block_no ; + uint32_t sequence_no ; + uint16_t size ; + uint8_t flags ; +} ; + +extern struct t_file_entry File_system[] ; +//extern unsigned char ModelNames[][sizeof(g_model.name)+1] ; // Allow for general + +//extern EEGeneral g_eeGeneral; +//extern ModelData g_model; + +extern uint8_t Spi_tx_buf[] ; +extern uint8_t Spi_rx_buf[] ; + +/// fileId of general file +//#define FILE_GENERAL 0 +/// convert model number 0..MAX_MODELS-1 int fileId +//#define FILE_MODEL(n) (1+n) +//#define FILE_TMP (1+16) + +//bool EeFsOpen(); +//int8_t EeFsck(); +//void EeFsFormat(); +//uint16_t EeFsGetFree(); +//#define ERR_NONE 0 +//#define ERR_FULL 1 +//#define ERR_TMO 2 +//class EFile +//{ +// uint8_t m_fileId; //index of file in directory = filename +// uint16_t m_pos; //over all filepos +// uint8_t m_currBlk; //current block.id +// uint8_t m_ofs; //offset inside of the current block +// uint8_t m_bRlc; //control byte for run length decoder +// uint8_t m_err; //error reasons +// uint16_t m_stopTime10ms; //maximum point of time for writing +//public: + ///remove contents of given file +// static void rm(uint8_t i_fileId); + + ///swap contents of file1 with them of file2 +// static void swap(uint8_t i_fileId1,uint8_t i_fileId2); + + ///return true if the file with given fileid exists +// static bool exists(uint8_t i_fileId); + + ///open file for reading, no close necessary + ///for writing use writeRlc() or create() +// uint8_t openRd(uint8_t i_fileId); + /// create a new file with given fileId, + /// !!! if this file already exists, then all blocks are reused + /// and all contents will be overwritten. + /// after writing closeTrunc has to be called +// void create(uint8_t i_fileId, uint8_t typ, uint16_t maxTme10ms); + /// close file and truncate the blockchain if to long. +// void closeTrunc(); + + ///open file, write to file and close it. + ///If file existed before, then contents is overwritten. + ///If file was larger before, then unused blocks are freed +// uint16_t writeRlc(uint8_t i_fileId, uint8_t typ,uint8_t*buf,uint16_t i_len, uint8_t maxTme10ms); + +// uint8_t read(uint8_t*buf,uint16_t i_len); +// uint8_t write(uint8_t*buf,uint8_t i_len); + + ///return size of compressed file without block overhead +// uint16_t size(); + ///read from opened file and decode rlc-coded data +// uint16_t readRlc(uint8_t*buf,uint16_t i_len); + ///deliver current errno, this is reset in open +// uint8_t errno(){return m_err;} +//}; + +#endif +/*eof*/ diff --git a/radio/bootloader/include/gtime.h b/radio/bootloader/include/gtime.h new file mode 100644 index 000000000..8126d8375 --- /dev/null +++ b/radio/bootloader/include/gtime.h @@ -0,0 +1,63 @@ +/* + * Authors (alphabetical order) + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * open9x is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef g9x_time_h +#define g9x_time_h + +#include +#include + +#undef CHAR_BIT +#define CHAR_BIT 8 + +typedef long int gtime_t; + +struct gtm +{ + int8_t tm_sec; /* Seconds. [0-60] (1 leap second) */ + int8_t tm_min; /* Minutes. [0-59] */ + int8_t tm_hour; /* Hours. [0-23] */ + int8_t tm_mday; /* Day. [1-31] */ + int8_t tm_mon; /* Month. [0-11] */ + int8_t tm_year; /* Year - 1900. Limited to the year 2115. Oh no! :P */ + int8_t tm_wday; /* Day of week. [0-6] */ + int16_t tm_yday; /* Day of year. [0-365] Needed internally for calculations */ +}; + +extern const unsigned short int __mon_yday[2][13]; + +extern gtime_t gmktime(struct gtm *tp); +extern gtime_t filltm(gtime_t *t, struct gtm *tp); + +#endif + diff --git a/radio/bootloader/include/hal.h b/radio/bootloader/include/hal.h new file mode 100644 index 000000000..8bad5aa6e --- /dev/null +++ b/radio/bootloader/include/hal.h @@ -0,0 +1,254 @@ +#ifndef _HAL_ +#define _HAL_ + +/* + * GPIOS + */ + +#define RCC_AHB1Periph_GPIOBUTTON (RCC_AHB1Periph_GPIOA|RCC_AHB1Periph_GPIOB|RCC_AHB1Periph_GPIOC|RCC_AHB1Periph_GPIOD|RCC_AHB1Periph_GPIOE) + +// Keys +#define PIN_BUTTON_PLUS GPIO_Pin_10 //SW3 PE.10 +#define PIN_BUTTON_MINUS GPIO_Pin_11 //SW2 PE.11 +#define PIN_BUTTON_ENTER GPIO_Pin_12 //SW1 PE.12 +#define PIN_BUTTON_MENU GPIO_Pin_7 //SW4 PD.07 +#define PIN_BUTTON_EXIT GPIO_Pin_2 //SW5 PD.02 +#define PIN_BUTTON_PAGE GPIO_Pin_3 //SW6 PD.03 + +// Trims +#define PIN_TRIM1_UP GPIO_Pin_3 //PC.03 +#define PIN_TRIM1_DN GPIO_Pin_2 //PC.02 +#define PIN_TRIM2_UP GPIO_Pin_1 //PC.01 +#define PIN_TRIM2_DN GPIO_Pin_13 //PC.13 +#define PIN_TRIM3_UP GPIO_Pin_4 //PE.04 +#define PIN_TRIM3_DN GPIO_Pin_3 //PE.03 +#define PIN_TRIM4_UP GPIO_Pin_6 //PE.06 +#define PIN_TRIM4_DN GPIO_Pin_5 //PE.05 + +// Switches +#if defined(REV3) +#define PIN_SW_A_L GPIO_Pin_14 //PE.14 +#define PIN_SW_B_H GPIO_Pin_3 //PB.03 +#define PIN_SW_B_L GPIO_Pin_4 //PB.04 +#define PIN_SW_C_H GPIO_Pin_5 //PB.05 +#define PIN_SW_C_L GPIO_Pin_6 //PB.06 +#define PIN_SW_D_H GPIO_Pin_7 //PB.07 +#define PIN_SW_D_L GPIO_Pin_2 //PE.02 +#define PIN_SW_E_H GPIO_Pin_0 //PB.00 +#define PIN_SW_E_L GPIO_Pin_5 //PA.05 +#define PIN_SW_F_H GPIO_Pin_7 //PE.07 +#define PIN_SW_F_L GPIO_Pin_1 //PB.01 +#define PIN_SW_G_H GPIO_Pin_9 //PE.09 +#define PIN_SW_G_L GPIO_Pin_8 //PE.08 +#define PIN_SW_H_L GPIO_Pin_13 //PE.13 +#else +#define PIN_SW_A_L GPIO_Pin_0 //PE.00 +#define PIN_SW_A_H GPIO_Pin_5 //PB.05 +#define PIN_SW_B_L GPIO_Pin_2 //PE.02 +#define PIN_SW_B_H GPIO_Pin_1 //PE.01 +#define PIN_SW_C_L GPIO_Pin_5 //PA.05 +#define PIN_SW_C_H GPIO_Pin_15 //PE.15 +#define PIN_SW_D_L GPIO_Pin_1 //PB.01 +#define PIN_SW_D_H GPIO_Pin_7 //PE.07 +#define PIN_SW_E_L GPIO_Pin_4 //PB.04 +#define PIN_SW_E_H GPIO_Pin_3 //PB.03 +#define PIN_SW_F GPIO_Pin_14 //PE.14 +#define PIN_SW_G_L GPIO_Pin_8 //PE.08 +#define PIN_SW_G_H GPIO_Pin_9 //PE.09 +#define PIN_SW_H GPIO_Pin_13 //PE.13 +#endif +// ADC +#define PIN_STK_J1 GPIO_Pin_0 //PA.00 +#define PIN_STK_J2 GPIO_Pin_1 //PA.01 +#define PIN_STK_J3 GPIO_Pin_2 //PA.02 +#define PIN_STK_J4 GPIO_Pin_3 //PA.03 +#define PIN_SLD_J1 GPIO_Pin_4 //PC.04 +#define PIN_SLD_J2 GPIO_Pin_5 //PC.05 +#define PIN_FLP_J1 GPIO_Pin_6 //PA.06 +#define PIN_FLP_J2 GPIO_Pin_0 //PB.00 +#define PIN_MVOLT GPIO_Pin_0 //PC.00 +#define RCC_AHB1Periph_GPIOADC RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOC + +// DAC +#define PIN_AUDIO_DAC GPIO_Pin_4 //PA.04 + +// Power_OFF Delay and LED +#define PIN_PWR_LED GPIO_Pin_6 //PC.06 +#define PIN_PWR_STATUS GPIO_Pin_1 //PD.01 +#define PIN_MCU_PWR GPIO_Pin_0 //PD.00 +#define RCC_AHB1Periph_GPIOPWR RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD +#define GPIOPWRLED GPIOC +#define GPIOPWR GPIOD +#define PIN_INT_RF_PWR GPIO_Pin_15 +#define PIN_EXT_RF_PWR GPIO_Pin_8 + + +// Smart-Port +#define PIN_SPORT_ON GPIO_Pin_4 //PD.04 +#define PIN_SPORT_TX GPIO_Pin_5 //PD.05 +#define PIN_SPORT_RX GPIO_Pin_6 //PD.06 + +// Trainer Port +#define GPIO_TR_INOUT GPIOC +#define PIN_TR_PPM_IN GPIO_Pin_8 //PC.08 +#define PIN_TR_PPM_OUT GPIO_Pin_9 //PC.09 +#define GPIOTRNDET GPIOA +#define PIN_TRNDET GPIO_Pin_8 + + + +// Cppm +#define RCC_AHB1Periph_GPIOCPPM RCC_AHB1Periph_GPIOA +#define RCC_AHB1Periph_GPIO_INTPPM RCC_AHB1Periph_GPIOA +#define PORT_INTPPM PIN_PORTA +#define GPIO_INTPPM GPIOA +#define PIN_INTPPM_OUT GPIO_Pin_10 //PA.10 +#define PIN_CPPM_OUT GPIO_Pin_8 //PA.08 +#define GPIOCPPM GPIOA +#define GPIO_PinSource_CPPM GPIO_PinSource8 +#define PIN_EXTPPM_OUT GPIO_Pin_7 //PA.07 +#define PORT_EXTPPM PIN_PORTA +#define GPIO_PinSource_EXTPPM GPIO_PinSource7 + +// Heart Beat +#define PIN_HEART_BEAT GPIO_Pin_7 //PC.07 + +// Update UART----RS232 ---UART3 +#define PIN_UPDATE_UART_TX GPIO_Pin_10 //PB.10 +#define PIN_UPDATE_UART_RX GPIO_Pin_11 //PB.11 + +// USB_OTG +#define PIN_FS_VBUS GPIO_Pin_9 //PA.09 +#define PIN_FS_ID GPIO_Pin_10 //PA.10 +#define PIN_FS_DM GPIO_Pin_11 //PA.11 +#define PIN_FS_DP GPIO_Pin_12 //PA.12 + +// BackLight PB8 +#define RCC_AHB1Periph_GPIOBL RCC_AHB1Periph_GPIOB +#define GPIO_Pin_BL GPIO_Pin_8 //PB.08 +#define GPIOBL GPIOB +#define GPIO_PinSource_BL GPIO_PinSource8 + +// LCD GPIOD 10-14 +#define RCC_AHB1Periph_LCD RCC_AHB1Periph_GPIOD +#define GPIO_LCD GPIOD +#define PIN_LCD_MOSI GPIO_Pin_10 //PD.10 +#define PIN_LCD_CLK GPIO_Pin_11 //PD.11 +#define PIN_LCD_NCS GPIO_Pin_14 //PD.14 +#define PIN_LCD_A0 GPIO_Pin_13 //PD.13 +#define PIN_LCD_RST GPIO_Pin_12 //pd12 test //RESET occurs when powered up,but should delay before initialize + +// Audio----I2S3 +//#define CODEC_I2S_ADDRESS 0x4000380C +#define CODEC_I2S SPI3 +#define CODEC_I2S_CLK RCC_APB1Periph_SPI3 +#define CODEC_I2S_GPIO_AF GPIO_AF_SPI3 +#define CODEC_I2S_IRQ SPI3_IRQn +#define CODEC_I2S_GPIO_CLOCK (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOC )//| RCC_AHB1Periph_GPIOE) +#define CODEC_I2S_WS_PIN GPIO_Pin_15 //PA.15 +#define CODEC_I2S_SCK_PIN GPIO_Pin_10 //PC.10 +#define CODEC_I2S_SD_PIN GPIO_Pin_12 //PC.12 +#define CODEC_I2S_MCK_PIN GPIO_Pin_6 //DISABLED +#define CODEC_I2S_WS_PINSRC GPIO_PinSource15 +#define CODEC_I2S_SCK_PINSRC GPIO_PinSource10 +#define CODEC_I2S_SD_PINSRC GPIO_PinSource12 +#define CODEC_I2S_MCK_PINSRC GPIO_PinSource6 +#define CODEC_I2S_GPIO GPIOC +#define CODEC_I2S_MCK_GPIO GPIOC +#define CODEC_I2S_WS_GPIO GPIOA +#define CODEC_I2S_MUTE GPIO_Pin_11 //PC.11 +//#define CODEC_I2S_FLT GPIO_Pin_ //IIR/FIR +//#define CODEC_I2S_MODE GPIO_Pin_ //Connect to GND=I2S_STANDARD + +// Eeprom 5137 +#define I2C_EE_GPIO GPIOB +#define I2C_EE_WP_GPIO GPIOB +#define I2C_EE_GPIO_CLK RCC_AHB1Periph_GPIOB +#define I2C_EE_SCL GPIO_Pin_6 //PB6 +#define I2C_EE_SDA GPIO_Pin_7 //PB7 +#define I2C_EE_WP GPIO_Pin_9 //PB9 + +// SD---spi2 +#define SPI_SD SPI2 +#define GPIO_AF_SD GPIO_AF_SPI2 +#define RCC_AHB1Periph_GPIO_CS RCC_AHB1Periph_GPIOB +#define GPIO_SPI_SD GPIOB +#define GPIO_Pin_SPI_SD_CS GPIO_Pin_12 //PB.12 +#define GPIO_Pin_SPI_SD_SCK GPIO_Pin_13 //PB.13 +#define GPIO_Pin_SPI_SD_MISO GPIO_Pin_14 //PB.14 +#define GPIO_Pin_SPI_SD_MOSI GPIO_Pin_15 //PB.15 +#define GPIO_PinSource_CS GPIO_PinSource12 +#define GPIO_PinSource_SCK GPIO_PinSource13 +#define GPIO_PinSource_MISO GPIO_PinSource14 +#define GPIO_PinSource_MOSI GPIO_PinSource15 +#define RCC_APBPeriphClockCmd_SPI_SD RCC_APB1PeriphClockCmd +#define RCC_APBPeriph_SPI_SD RCC_APB1Periph_SPI2 +#define RCC_AHBxPeriph_GPIO_WP RCC_AHB1Periph_GPIOD +#define RCC_AHBxPeriph_GPIO_CP RCC_AHB1Periph_GPIOD +#define GPIO_Mode_WP GPIO_Mode_OUT//lock? +#define GPIO_Mode_CP GPIO_Mode_IN // +#define GPIO_Pin_WP GPIO_Pin_8 //PD.08 +#define GPIO_Pin_CP GPIO_Pin_9 //PD.09 +#define GPIO_CTL_SD GPIOD + +// Audio----I2S3-----SPI3 +#define CODEC_MCLK_DISABLED +#define CODEC_USE_INT +//#define CODEC_USE_DMA +#define AudioFreq I2S_AudioFreq_44k + + +// EEPROM and CAT5137 +//#define EE_M24C08 /* Support the device: M24C08. */ +//#define EE_M24C64_32 /* Support the devices: M24C32 and M24C64 */ +#define I2C_Speed 200000 +#define I2C_FLASH_PAGESIZE 64 +#define I2C_EEPROM_ADDRESS 0xA2 +#define I2C_CAT5137_ADDRESS 0x5C //0101110 + +//#if defined (EE_M24C08) +// #define I2C_FLASH_PAGESIZE (16) +//#elif defined (EE_M24C64_32) +// #define I2C_FLASH_PAGESIZE (32) +//#endif + +//#ifdef EE_M24C64_32 +// #define EEPROM_HW_ADDRESS 0xA0 /* E0 = E1 = E2 = 0 */ +//#elif defined (EE_M24C08) +////#define EEPROM_Block0_ADDRESS 0xA0 /* 000*/ +//#define EEPROM_Block1_ADDRESS 0xA2 /* E3 E2 E1= 001 */ +////#define EEPROM_Block2_ADDRESS 0xA4 /* 010 */ +////#define EEPROM_Block3_ADDRESS 0xA6 /* 011 */ +//#endif + +//#define USE_CAT5137 /*Support the Volume Control*/ + +//#ifdef USE_CAT5137 +//#define I2C_CAT5137_ADDRESS 0x5C//0101110 +//#endif + +// SD card----SPI2 +// demo uses a command line option to define this (see Makefile): +// #define STM32_SD_USE_DMA +#ifdef STM32_SD_USE_DMA +// #warning "Information only: using DMA" +#pragma message "*** Using DMA ***" +#endif + +/* set to 1 to provide a disk_ioctrl function even if not needed by the FatFs */ +#define STM32_SD_DISK_IOCTRL_FORCE (0) + +#define CARD_SUPPLY_SWITCHABLE (0) //0power on not depend any IO +#define SOCKET_WP_CONNECTED (0) +#define SOCKET_CP_CONNECTED (0) + +#define SPI_BaudRatePrescaler_SPI_SD SPI_BaudRatePrescaler_4 // - for SPI1 and full-speed APB2: 60MHz/4 =15MHZ < 20MHZ + +// Selectable +// DMA +#define DMA_Channel_SPI_SD_RX DMA1_Channel2 +#define DMA_Channel_SPI_SD_TX DMA1_Channel3 +#define DMA_FLAG_SPI_SD_TC_RX DMA1_FLAG_TC2 +#define DMA_FLAG_SPI_SD_TC_TX DMA1_FLAG_TC3 + +#endif diff --git a/radio/bootloader/include/i2c_ee.h b/radio/bootloader/include/i2c_ee.h new file mode 100644 index 000000000..8e2f45d08 --- /dev/null +++ b/radio/bootloader/include/i2c_ee.h @@ -0,0 +1,52 @@ +/** + ****************************************************************************** + * @file Project/ee_drivers/i2c_ee.h + * @author X9D Application Team + * @version V 0.2 + * @date 12-JLY-2012 + * @brief Header for i2c_ee.c module + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef __I2C_EE_H +#define __I2C_EE_H + +#define EE_CMD_WRITE (0) +#define EE_CMD_READ (1) +//#define I2C_delay() //do { delayUsec(5); } while(0) + +#define SCL_H do{I2C_EE_GPIO->BSRRL = I2C_EE_SCL;}while(0) +#define SCL_L do{I2C_EE_GPIO->BSRRH = I2C_EE_SCL;}while(0) +#define SDA_H do{I2C_EE_GPIO->BSRRL = I2C_EE_SDA;}while(0) +#define SDA_L do{I2C_EE_GPIO->BSRRH = I2C_EE_SDA;}while(0) +#define SCL_read (I2C_EE_GPIO->IDR & I2C_EE_SCL) +#define SDA_read (I2C_EE_GPIO->IDR & I2C_EE_SDA) +#define WP_H do{I2C_EE_WP_GPIO->BSRRL = I2C_EE_WP;}while(0) +#define WP_L do{I2C_EE_WP_GPIO->BSRRH = I2C_EE_WP;}while(0) + + +/* Exported functions ------------------------------------------------------- */ +void I2C_EE_Init(void); +void I2C_EE_ByteWrite(uint8_t* pBuffer, uint16_t WriteAddr); +void I2C_EE_PageWrite(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t NumByteToWrite); +void I2C_EE_BufferWrite(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite); +void I2C_EE_BufferRead(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t NumByteToRead); +void I2C_EE_WaitEepromStandbyState(void); +void I2C_set_volume( uint8_t volume ) ; +uint8_t I2C_read_volume( void ) ; + +#endif /* __I2C_EE_H */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ + diff --git a/radio/bootloader/include/integer.h b/radio/bootloader/include/integer.h new file mode 100644 index 000000000..608873bdf --- /dev/null +++ b/radio/bootloader/include/integer.h @@ -0,0 +1,70 @@ +/* + * Authors (alphabetical order) + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * open9x is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +/*-------------------------------------------*/ +/* Integer type definitions for FatFs module */ +/*-------------------------------------------*/ + +#ifndef _INTEGER +#define _INTEGER + +#ifdef _WIN32 /* FatFs development platform */ + +#include +#include + +#else /* Embedded platform */ + +/* These types must be 16-bit, 32-bit or larger integer */ +typedef int INT; +typedef unsigned int UINT; + +/* These types must be 8-bit integer */ +typedef char CHAR; +typedef unsigned char UCHAR; +typedef unsigned char BYTE; + +/* These types must be 16-bit integer */ +typedef short SHORT; +typedef unsigned short USHORT; +typedef unsigned short WORD; +typedef unsigned short WCHAR; + +/* These types must be 32-bit integer */ +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long DWORD; + +#endif + +#endif diff --git a/radio/bootloader/include/lcd.h b/radio/bootloader/include/lcd.h new file mode 100644 index 000000000..cbea7fd2e --- /dev/null +++ b/radio/bootloader/include/lcd.h @@ -0,0 +1,122 @@ +/* + * Author - Mike Blandford + * + * Based on er9x by Erez Raviv + * + * which was Based on th9x -> http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +// This version for ARM based ERSKY9X board + +#ifndef lcd_h +#define lcd_h + +#ifdef PCBX9D +#define DISPLAY_W 212 +#define DISPLAY_H 64 +#endif + +#ifdef PCBSKY +#define DISPLAY_W 128 +#define DISPLAY_H 64 +#endif + +#define FW 6 +#define FWNUM 5 +#define FH 8 + +/* lcd common flags */ +#define INVERS 0x01 +#define BLINK 0x02 +#define DBLSIZE 0x04 +#define CONDENSED 0x08 + +// putsChnRaw flags +#define MIX_SOURCE 0x10 + +/* lcd outdez flags */ +#define LEADING0 0x10 +#define PREC1 0x20 +#define PREC2 0x30 /* 4 modes in 2bits! */ +#define LEFT 0x40 /* align left */ + +/* time & telemetry flags */ +#define NO_UNIT 0x80 + + + +extern uint8_t LcdLock ; +extern uint8_t LcdInputs ; + +extern uint8_t Lcd_lastPos; +extern uint8_t DisplayBuf[] ; + +extern const uint8_t font_se_extra[] ; +extern const uint8_t font_fr_extra[] ; +extern const uint8_t font_de_extra[] ; + +extern const uint8_t font_se_big_extra[] ; +extern const uint8_t font_fr_big_extra[] ; +extern const uint8_t font_de_big_extra[] ; + +extern const uint8_t *ExtraFont ; +extern const uint8_t *ExtraBigFont ; + +#define PLOT_XOR 0 +#define PLOT_BLACK 1 +#define PLOT_WHITE 2 + +extern uint8_t plotType ; + +extern void lcd_putc(uint8_t x,uint8_t y,const char c ) ; +extern uint8_t lcd_putcAtt( uint8_t x, uint8_t y, const char c, uint8_t mode ) ; +extern void lcd_putsAttIdx(uint8_t x,uint8_t y,const char * s,uint8_t idx,uint8_t att) ; +extern void lcd_putsnAtt(uint8_t x,uint8_t y,const char * s,uint8_t len,uint8_t mode) ; +extern void lcd_putsn_P(uint8_t x,uint8_t y,const char * s,uint8_t len) ; +extern void lcd_outhex4(uint8_t x,uint8_t y,uint16_t val) ; +extern void lcd_outhex2(uint8_t x,uint8_t y,uint8_t val) ; +extern void lcd_img( uint8_t i_x, uint8_t i_y, const unsigned char *imgdat, uint8_t idx, uint8_t mode ) ; +extern uint8_t lcd_putsAtt( uint8_t x, uint8_t y, const char *s, uint8_t mode ) ; +extern void lcd_puts_Pleft( uint8_t y, const char *s ) ; +extern void lcd_puts_P( uint8_t x, uint8_t y, const char *s ) ; +extern void lcd_outdez( uint8_t x, uint8_t y, int16_t val ) ; +extern void lcd_outdezAtt( uint8_t x, uint8_t y, int16_t val, uint8_t mode ) ; +extern void lcd_outdezNAtt( uint8_t x, uint8_t y, int32_t val, uint8_t mode, int8_t len ) ; + +extern void lcd_hbar( uint8_t x, uint8_t y, uint8_t w, uint8_t h, uint8_t percent ) ; +extern void lcd_rect(uint8_t x, uint8_t y, uint8_t w, uint8_t h ) ; +extern void lcd_char_inverse( uint8_t x, uint8_t y, uint8_t w, uint8_t blink ) ; +extern void lcd_plot( uint8_t x, uint8_t y ) ; +extern void lcd_hlineStip( unsigned char x, unsigned char y, signed char w, uint8_t pat ) ; +extern void lcd_hline( uint8_t x, uint8_t y, int8_t w ) ; +extern void lcd_vline( uint8_t x, uint8_t y, int8_t h ) ; +extern void lcd_clear( void ) ; +extern void lcd_init( void ) ; +extern void lcdSetRefVolt(uint8_t val) ; +extern void lcdSendCtl(uint8_t val) ; +extern void refreshDisplay( void ) ; + +extern void putsTime(uint8_t x,uint8_t y,int16_t tme,uint8_t att,uint8_t att2) ; +extern void putsVolts(uint8_t x,uint8_t y, uint8_t volts, uint8_t att) ; +extern void putsVBat(uint8_t x,uint8_t y,uint8_t att) ; + +#ifdef PCBX9D +extern void backlight_set( uint16_t brightness ) ; +#endif + +#define BLINK_ON_PHASE (g_blinkTmr10ms & (1<<6)) +#define BLINK_SYNC g_blinkTmr10ms = (3<<5) + +#endif + + diff --git a/radio/bootloader/include/logicio.h b/radio/bootloader/include/logicio.h new file mode 100644 index 000000000..aa2720a24 --- /dev/null +++ b/radio/bootloader/include/logicio.h @@ -0,0 +1,123 @@ +/**************************************************************************** +* Copyright (c) 2012 by Michael Blandford. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* +****************************************************************************/ + +#ifdef PCBX9D +#define PIN_MODE_MASK 0x0003 +#define PIN_INPUT 0x0000 +#define PIN_OUTPUT 0x0001 +#define PIN_PERIPHERAL 0x0002 +#define PIN_ANALOG 0x0003 +#define PIN_PULL_MASK 0x000C +#define PIN_PULLUP 0x0004 +#define PIN_NO_PULLUP 0x0000 +#define PIN_PULLDOWN 0x0008 +#define PIN_NO_PULLDOWN 0x0000 +#define PIN_NO_PULL 0x0000 +#define PIN_PERI_MASK 0x00F0 +//#define PIN_PERI_MASK_H 0x0020 +#define PIN_PER_0 0x0000 +#define PIN_PER_1 0x0010 +#define PIN_PER_2 0x0020 +#define PIN_PER_3 0x0030 +#define PIN_PER_4 0x0040 +#define PIN_PER_5 0x0050 +#define PIN_PER_6 0x0060 +#define PIN_PER_7 0x0070 +#define PIN_PER_8 0x0080 +#define PIN_PER_9 0x0090 +#define PIN_PER_10 0x00A0 +#define PIN_PER_11 0x00B0 +#define PIN_PER_12 0x00C0 +#define PIN_PER_13 0x00D0 +#define PIN_PER_14 0x00E0 +#define PIN_PER_15 0x00F0 +#define PIN_PORT_MASK 0x0700 +#define PIN_PORTA 0x0000 +#define PIN_PORTB 0x0100 +#define PIN_PORTC 0x0200 +#define PIN_PORTD 0x0300 +#define PIN_PORTE 0x0400 +#define PIN_LOW 0x0000 +#define PIN_HIGH 0x1000 +#define PIN_SPEED_MASK 0x6000 +#define PIN_OS2 0x0000 +#define PIN_OS25 0x2000 +#define PIN_OS50 0x4000 +#define PIN_OS100 0x6000 +#define PIN_PUSHPULL 0x0000 +#define PIN_ODRAIN 0x8000 + +#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ + +#endif + + +#ifdef PCBSKY +#define PIN_ENABLE 0x001 +#define PIN_PERIPHERAL 0x000 +#define PIN_INPUT 0x002 +#define PIN_OUTPUT 0x000 +#define PIN_PULLUP 0x004 +#define PIN_NO_PULLUP 0x000 +#define PIN_PULLDOWN 0x008 +#define PIN_NO_PULLDOWN 0x000 +#define PIN_PERI_MASK_L 0x010 +#define PIN_PERI_MASK_H 0x020 +#define PIN_PER_A 0x000 +#define PIN_PER_B 0x010 +#define PIN_PER_C 0x020 +#define PIN_PER_D 0x030 +#define PIN_PORT_MASK 0x0C0 +#define PIN_PORTA 0x000 +#define PIN_PORTB 0x040 +#define PIN_PORTC 0x080 +#define PIN_LOW 0x000 +#define PIN_HIGH 0x100 +#endif + + +extern void configure_pins( uint32_t pins, uint16_t config ) ; +extern void init_keys( void ) ; +extern uint32_t read_keys( void ) ; +extern uint32_t read_trims( void ) ; +extern uint32_t keyState( enum EnumKeys enuk) ; +extern void init_trims( void ) ; +extern void setup_switches( void ) ; +extern void config_free_pins( void ) ; + +#define GPIO_ResetBits( port, bits ) (port->BSRRH = bits) +#define GPIO_SetBits( port, bits ) (port->BSRRL = bits) +#define GPIO_ReadInputDataBit( port, bit) ( (port->IDR & bit) ? Bit_SET : Bit_RESET) + +#ifdef PCBX9D +uint32_t switchPosition( uint32_t swtch ) ; +#endif + diff --git a/radio/bootloader/include/misc.h b/radio/bootloader/include/misc.h new file mode 100644 index 000000000..ff3f1543e --- /dev/null +++ b/radio/bootloader/include/misc.h @@ -0,0 +1,178 @@ +/** + ****************************************************************************** + * @file misc.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the miscellaneous + * firmware library functions (add-on to CMSIS functions). + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MISC_H +#define __MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup MISC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief NVIC Init Structure definition + */ + +typedef struct +{ + uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. + This parameter can be an enumerator of @ref IRQn_Type + enumeration (For the complete STM32 Devices IRQ Channels + list, please refer to stm32f2xx.h file) */ + + uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel + specified in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table + A lower priority value indicates a higher priority */ + + uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified + in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table + A lower priority value indicates a higher priority */ + + FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel + will be enabled or disabled. + This parameter can be set either to ENABLE or DISABLE */ +} NVIC_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup MISC_Exported_Constants + * @{ + */ + +/** @defgroup MISC_Vector_Table_Base + * @{ + */ + +#define NVIC_VectTab_RAM ((uint32_t)0x20000000) +#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) +#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ + ((VECTTAB) == NVIC_VectTab_FLASH)) +/** + * @} + */ + +/** @defgroup MISC_System_Low_Power + * @{ + */ + +#define NVIC_LP_SEVONPEND ((uint8_t)0x10) +#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) +#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) +#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ + ((LP) == NVIC_LP_SLEEPDEEP) || \ + ((LP) == NVIC_LP_SLEEPONEXIT)) +/** + * @} + */ + +/** @defgroup MISC_Preemption_Priority_Group + * @{ + */ + +#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ + ((GROUP) == NVIC_PriorityGroup_1) || \ + ((GROUP) == NVIC_PriorityGroup_2) || \ + ((GROUP) == NVIC_PriorityGroup_3) || \ + ((GROUP) == NVIC_PriorityGroup_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) + +/** + * @} + */ + +/** @defgroup MISC_SysTick_clock_source + * @{ + */ + +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ + ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); + +#ifdef __cplusplus +} +#endif + +#endif /* __MISC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/include/myeeprom.h b/radio/bootloader/include/myeeprom.h new file mode 100644 index 000000000..269c29d99 --- /dev/null +++ b/radio/bootloader/include/myeeprom.h @@ -0,0 +1,527 @@ +/* + * Author - Erez Raviv + * + * Based on th9x -> http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef eeprom_h +#define eeprom_h + +#include + + +//eeprom data +//#define EE_VERSION 2 +#define MAX_MODELS 32 +#define MAX_MIXERS 32 +#define MAX_SKYMIXERS 48 +#define MAX_CURVE5 8 +#define MAX_CURVE9 8 +#define MDVERS_r9 1 +#define MDVERS_r14 2 +#define MDVERS_r22 3 +#define MDVERS_r77 4 +#define MDVERS_r85 5 +#define MDVERS_r261 6 +#define MDVERS_r352 7 +#define MDVERS_r365 8 +#define MDVERS_r668 9 +#define MDVERS_e119 10 +#define MDVERS 11 + +#define MDSKYVERS 2 + +#define NUM_VOICE 8 + +//OBSOLETE - USE ONLY MDVERS NOW +//#define GENERAL_MYVER_r261 3 +//#define GENERAL_MYVER_r365 4 +//#define GENERAL_MYVER 5 + + +// eeprom ver <9 => mdvers == 1 +// eeprom ver >9 => mdvers ==2 + +#define WARN_THR_BIT 0x01 +#define WARN_BEP_BIT 0x80 +#define WARN_SW_BIT 0x02 +#define WARN_MEM_BIT 0x04 +#define WARN_BVAL_BIT 0x38 + +#define WARN_THR (!(g_eeGeneral.warnOpts & WARN_THR_BIT)) +#define WARN_BEP (!(g_eeGeneral.warnOpts & WARN_BEP_BIT)) +#define WARN_SW (!(g_eeGeneral.warnOpts & WARN_SW_BIT)) +#define WARN_MEM (!(g_eeGeneral.warnOpts & WARN_MEM_BIT)) +#define BEEP_VAL ( (g_eeGeneral.warnOpts & WARN_BVAL_BIT) >>3 ) + +// Bits in stickGain +#define STICK_LV_GAIN 0x40 +#define STICK_LH_GAIN 0x10 +#define STICK_RV_GAIN 0x04 +#define STICK_RH_GAIN 0x01 + +#define GENERAL_OWNER_NAME_LEN 10 +#define MODEL_NAME_LEN 10 + +#define MAX_GVARS 7 + +#define MAX_PHASES 6 + +#ifndef PACK +#define PACK( __Declaration__ ) __Declaration__ __attribute__((__packed__)) +#endif + +PACK(typedef struct t_TrainerMix { + uint8_t srcChn:3; //0-7 = ch1-8 + int8_t swtch:5; + int8_t studWeight:6; + uint8_t mode:2; //off,add-mode,subst-mode +}) TrainerMix; // + +PACK(typedef struct t_TrainerData { + int16_t calib[4]; + TrainerMix mix[4]; +}) TrainerData; + +PACK(typedef struct t_EEGeneral { + uint8_t myVers; + int16_t calibMid[7]; + int16_t calibSpanNeg[7]; + int16_t calibSpanPos[7]; + uint16_t chkSum; + uint8_t currModel; //0..15 + uint8_t contrast; + uint8_t vBatWarn; + int8_t vBatCalib; + int8_t lightSw; + TrainerData trainer; + uint8_t view; + uint8_t disableThrottleWarning:1; + uint8_t disableSwitchWarning:1; + uint8_t disableMemoryWarning:1; + uint8_t beeperVal:3; + uint8_t reserveWarning:1; + uint8_t disableAlarmWarning:1; + uint8_t stickMode; + int8_t inactivityTimer; + uint8_t throttleReversed:1; + uint8_t minuteBeep:1; + uint8_t preBeep:1; + uint8_t flashBeep:1; + uint8_t disableSplashScreen:1; + uint8_t disablePotScroll:1; + uint8_t stickScroll:1 ; + uint8_t frskyinternalalarm:1; + uint8_t filterInput; + uint8_t lightAutoOff; + uint8_t templateSetup; //RETA order according to chout_ar array + int8_t PPM_Multiplier; + uint8_t FRSkyYellow:4; + uint8_t FRSkyOrange:4; + uint8_t FRSkyRed:4; //mike please check these are correct + uint8_t hideNameOnSplash:1; + uint8_t optrexDisplay:1; + uint8_t unexpectedShutdown:1; + uint8_t spare:1; + uint8_t speakerPitch; + uint8_t hapticStrength; + uint8_t speakerMode; + uint8_t lightOnStickMove; + char ownerName[GENERAL_OWNER_NAME_LEN]; + uint8_t switchWarningStates; + uint8_t volume ; + uint8_t bright ; // backlight + uint8_t stickGain; + uint8_t mAh_alarm ; + uint16_t mAh_used ; + uint16_t run_time ; + int8_t current_calib ; + uint8_t bt_baudrate ; + uint8_t rotaryDivisor ; + uint8_t crosstrim:1; + uint8_t spare9:7; + int8_t rtcCal ; + int16_t x9dcalibMid ; // X9D + int16_t x9dcalibSpanNeg ; // X9D + int16_t x9dcalibSpanPos ; // X9D + uint8_t stickReverse ; + uint8_t language ; +}) EEGeneral; + + + + + +//eeprom modelspec +//expo[3][2][2] //[Norm/Dr][expo/weight][R/L] + +PACK(typedef struct t_ExpoData { + int8_t expo[3][2][2]; + int8_t drSw1; + int8_t drSw2; +}) ExpoData; + + +PACK(typedef struct t_LimitData { + int8_t min; + int8_t max; + bool revert; + int16_t offset; +}) LimitData; + +#define MLTPX_ADD 0 +#define MLTPX_MUL 1 +#define MLTPX_REP 2 + +PACK(typedef struct t_MixData { + uint8_t destCh; // 1..NUM_CHNOUT + uint8_t srcRaw; // + int8_t weight; + int8_t swtch; + uint8_t curve; //0=symmetrisch 1=no neg 2=no pos + uint8_t delayUp:4; + uint8_t delayDown:4; + uint8_t speedUp:4; // Servogeschwindigkeit aus Tabelle (10ms Cycle) + uint8_t speedDown:4; // 0 nichts + uint8_t carryTrim:1; + uint8_t mltpx:3; // multiplex method 0=+ 1=* 2=replace + uint8_t mixWarn:2; // mixer warning + uint8_t enableFmTrim:1; + uint8_t mixres:1; + int8_t sOffset; + int8_t res; +}) MixData; + + +PACK(typedef struct t_CSwData { // Custom Switches data + int8_t v1; //input + int8_t v2; //offset + uint8_t func:4; + uint8_t andsw:4; +}) CSwData; + +PACK(typedef struct t_SafetySwData { // Custom Switches data + union opt + { + struct ss + { + int8_t swtch:6; + uint8_t mode:2; + int8_t val; + } ss ; + struct vs + { + uint8_t vswtch:5 ; + uint8_t vmode:3 ; // ON, OFF, BOTH, 15Secs, 30Secs, 60Secs, Varibl + uint8_t vval; + } vs ; + } opt ; +}) SafetySwData; + +PACK(typedef struct t_FrSkyChannelData { + uint8_t ratio; // 0.0 means not used, 0.1V steps EG. 6.6 Volts = 66. 25.1V = 251, etc. + uint8_t alarms_value[2]; // 0.1V steps EG. 6.6 Volts = 66. 25.1V = 251, etc. + uint8_t alarms_level:4; + uint8_t alarms_greater:2; // 0=LT(<), 1=GT(>) + uint8_t type:2; // 0=volts, 1=raw, 2=volts*2, 3=Amps +}) FrSkyChannelData; + +PACK(typedef struct t_FrSkyData { + FrSkyChannelData channels[2]; +}) FrSkyData; + +PACK(typedef struct t_FrSkyalarms +{ + uint8_t frskyAlarmType ; + uint8_t frskyAlarmLimit ; + uint8_t frskyAlarmSound ; +}) FrSkyAlData; + +PACK(typedef struct t_FrSkyAlarmData { + FrSkyAlData alarmData[8] ; +}) FrSkyAlarmData; + +PACK(typedef struct t_TimerMode +{ + uint8_t tmrModeA:7 ; // timer trigger source -> off, abs, stk, stk%, cx% + uint8_t tmrDir:1 ; // Timer direction + int8_t tmrModeB ; // timer trigger source -> !sw, none, sw, m_sw + uint16_t tmrVal ; +}) TimerMode ; + +//PACK(typedef struct t_swVoice { +// uint8_t swtch:5 ; +// uint8_t mode:3 ; // ON, OFF, BOTH, 15Secs, 30Secs, 60Secs +// uint8_t val ; +//}) old_voiceSwData ; + + +PACK(typedef struct t_ModelData { + char name[MODEL_NAME_LEN]; // 10 must be first for eeLoadModelName + uint8_t modelVoice ; // Index to model name voice (261+value) + uint8_t RxNum ; // was timer trigger source, now RxNum for model match + uint8_t sparex:1; // was tmrDir, now use tmrVal>0 => count down + uint8_t traineron:1; // 0 disable trainer, 1 allow trainer + uint8_t spare22:1 ; // Start timer2 using throttle + uint8_t FrSkyUsrProto:1 ; // Protocol in FrSky User Data, 0=FrSky Hub, 1=WS HowHigh + uint8_t FrSkyGpsAlt:1 ; // Use Gps Altitude as main altitude reading + uint8_t FrSkyImperial:1 ; // Convert FrSky values to imperial units + uint8_t FrSkyAltAlarm:2; + uint8_t version ; + uint8_t spare_u8 ; // Was timerval + uint8_t protocol; + int8_t ppmNCH; + uint8_t thrTrim:1; // Enable Throttle Trim + uint8_t numBlades:2; // RPM scaling + uint8_t spare10:1; + uint8_t thrExpo:1; // Enable Throttle Expo + uint8_t spare11:3; + int8_t trimInc; // Trim Increments + int8_t ppmDelay; + int8_t trimSw; + uint8_t beepANACenter; // 1<<0->A1.. 1<<6->A7 + uint8_t pulsePol:1; + uint8_t extendedLimits:1; + uint8_t swashInvertELE:1; + uint8_t swashInvertAIL:1; + uint8_t swashInvertCOL:1; + uint8_t swashType:3; + uint8_t swashCollectiveSource; + uint8_t swashRingValue; + int8_t ppmFrameLength; //0=22.5 (10msec-30msec) 0.5msec increments + MixData mixData[MAX_MIXERS]; + LimitData limitData[NUM_CHNOUT]; + ExpoData expoData[4]; + int8_t trim[4]; + int8_t curves5[MAX_CURVE5][5]; + int8_t curves9[MAX_CURVE9][9]; + CSwData customSw[NUM_CSW]; +// uint8_t rxnum; + uint8_t frSkyVoltThreshold ; + uint8_t bt_telemetry; + uint8_t numVoice; // 0-16, rest are Safety switches + SafetySwData safetySw[NUM_CHNOUT]; + FrSkyData frsky; + TimerMode timer[2] ; + FrSkyAlarmData frskyAlarms ; +// Add 6 bytes for custom telemetry screen + uint8_t customDisplayIndex[6] ; +}) ModelData; + +#define TOTAL_EEPROM_USAGE (sizeof(ModelData)*MAX_MODELS + sizeof(EEGeneral)) + + +extern EEGeneral g_eeGeneral; +extern ModelData g_oldmodel; + +PACK(typedef struct t_PhaseData { + int16_t trim[4]; // -500..500 => trim value, 501 => use trim of phase 0, 502, 503, 504 => use trim of phases 1|2|3|4 instead + int8_t swtch; // swtch of phase[0] is not used + char name[6]; + uint8_t fadeIn:4; + uint8_t fadeOut:4; + uint16_t spare ; // Future expansion +}) PhaseData; + +PACK(typedef struct te_MixData { + uint8_t destCh; // 1..NUM_CHNOUT + uint8_t srcRaw; // + int8_t weight; + int8_t swtch; + int8_t curve; //0=symmetrisch 1=no neg 2=no pos + uint8_t delayUp; + uint8_t delayDown; + uint8_t speedUp; // Servogeschwindigkeit aus Tabelle (10ms Cycle) + uint8_t speedDown; // 0 nichts + uint8_t carryTrim:1; + uint8_t mltpx:2; // multiplex method 0=+ 1=* 2=replace + uint8_t lateOffset:1; // Add offset later + uint8_t mixWarn:2; // mixer warning + uint8_t enableFmTrim:1; + uint8_t differential:1 ; + int8_t sOffset; + uint8_t res[4]; +}) SKYMixData; + +PACK(typedef struct te_CSwData { // Custom Switches data + int8_t v1; //input + int8_t v2; //offset + uint8_t func; + int8_t andsw; + uint8_t res ; +}) SKYCSwData; + +PACK(typedef struct te_SafetySwData { // Safety Switches data + union opt + { + struct ss + { + int8_t swtch ; + uint8_t mode ; + int8_t val ; + uint8_t res ; + } ss ; + struct vs + { + uint8_t vswtch ; + uint8_t vmode ; // ON, OFF, BOTH, 15Secs, 30Secs, 60Secs, Varibl + uint8_t vval; + uint8_t vres ; + } vs ; + } opt ; +}) SKYSafetySwData; + +PACK(typedef struct te_FrSkyChannelData { + uint8_t ratio ; // 0.0 means not used, 0.1V steps EG. 6.6 Volts = 66. 25.1V = 251, etc. + uint8_t offset ; // + uint8_t gain ; // + uint8_t alarms_value[2] ; // 0.1V steps EG. 6.6 Volts = 66. 25.1V = 251, etc. + uint8_t alarms_level ; + uint8_t alarms_greater ; // 0=LT(<), 1=GT(>) + uint8_t type ; // 0=volts, 1=raw, 2=volts*2, 3=Amps +}) SKYFrSkyChannelData; + +PACK(typedef struct te_FrSkyData { + SKYFrSkyChannelData channels[2]; +}) SKYFrSkyData; + +PACK(typedef struct te_swVoice { + uint8_t swtch ; + uint8_t mode ; // ON, OFF, BOTH, 15Secs, 30Secs, 60Secs + uint8_t val ; + uint8_t vres ; +}) voiceSwData ; + +PACK(typedef struct t_FunctionData { // Function data + int8_t swtch ; //input + uint8_t func ; + uint8_t param[6] ; + uint8_t spare1 ; + uint8_t spare2 ; +}) FunctionData; + +PACK(typedef struct t_Vario +{ + uint8_t varioSource ; + int8_t swtch ; + uint8_t sinkTones:1 ; + uint8_t spare:1 ; + uint8_t param:6 ; +}) VarioData ; + +PACK(typedef struct t_gvar { + int8_t gvar ; + uint8_t gvsource ; +// int8_t gvswitch ; +}) GvarData ; + +PACK(typedef struct te_ModelData { + char name[MODEL_NAME_LEN]; // 10 must be first for eeLoadModelName + uint8_t modelVoice ; // Index to model name voice (261+value) + uint8_t RxNum ; // was timer trigger source, now RxNum for model match + uint8_t telemetryRxInvert:1 ; // was tmrDir, now use tmrVal>0 => count down + uint8_t traineron:1; // 0 disable trainer, 1 allow trainer + uint8_t spare15:1 ; + uint8_t FrSkyUsrProto:1 ; // Protocol in FrSky User Data, 0=FrSky Hub, 1=WS HowHigh + uint8_t FrSkyGpsAlt:1 ; // Use Gps Altitude as main altitude reading + uint8_t FrSkyImperial:1 ; // Convert FrSky values to imperial units + uint8_t FrSkyAltAlarm:2; + uint8_t modelVersion ; + uint8_t protocol:4 ; + uint8_t country:2 ; + uint8_t sub_protocol:2 ; + int8_t ppmNCH; + uint8_t thrTrim:1; // Enable Throttle Trim + uint8_t xnumBlades:2; // RPM scaling, now elsewhere as uint8_t + uint8_t extendedTrims:1; // Only applies to phases + uint8_t thrExpo:1; // Enable Throttle Expo + uint8_t frskyComPort:1; + uint8_t spare11:2; + int8_t trimInc; // Trim Increments + int8_t ppmDelay; + int8_t trimSw; + uint8_t beepANACenter; // 1<<0->A1.. 1<<6->A7 + uint8_t pulsePol:1; + uint8_t extendedLimits:1; + uint8_t swashInvertELE:1; + uint8_t swashInvertAIL:1; + uint8_t swashInvertCOL:1; + uint8_t swashType:3; + uint8_t swashCollectiveSource; + uint8_t swashRingValue; + int8_t ppmFrameLength; //0=22.5 (10msec-30msec) 0.5msec increments + SKYMixData mixData[MAX_SKYMIXERS]; + LimitData limitData[NUM_SKYCHNOUT]; + ExpoData expoData[4]; + int8_t trim[4]; + int8_t curves5[MAX_CURVE5][5]; + int8_t curves9[MAX_CURVE9][9]; + int8_t curvexy[18]; + SKYCSwData customSw[NUM_SKYCSW]; +// uint8_t rxnum; + uint8_t frSkyVoltThreshold ; + uint8_t bt_telemetry; + uint8_t numVoice; // 0-16, rest are Safety switches + SKYSafetySwData safetySw[NUM_SKYCHNOUT]; + voiceSwData voiceSwitches[NUM_VOICE] ; + SKYFrSkyData frsky; + TimerMode timer[2] ; + FrSkyAlarmData frskyAlarms ; +// Add 6 bytes for custom telemetry screen + uint8_t customDisplayIndex[6] ; + FunctionData functionData[NUM_FSW]; + PhaseData phaseData[MAX_PHASES] ; + GvarData gvars[MAX_GVARS] ; + uint8_t numBlades ; // RPM scaling + uint8_t startChannel ; // for main output 0 = ch1 + uint8_t startPPM2channel ; // for PPM2 output 0 follow + int8_t ppm2NCH ; + uint8_t sub_trim_limit ; + uint8_t FASoffset ; // 0.0 to 1.5 + VarioData varioData ; + uint8_t anaVolume ; // analog volume control + int8_t pxxFailsafe[16] ; + int8_t logSwitch ; + uint8_t logRate ; + // X9D ext module + uint8_t xprotocol:4 ; + uint8_t xcountry:2 ; + uint8_t xsub_protocol:2 ; + int8_t xppmNCH ; + int8_t xppmDelay ; + uint8_t xpulsePol ; + int8_t xppmFrameLength; //0=22.5 (10msec-30msec) 0.5msec increments + uint8_t xstartChannel ; // for output 0 = ch1 + uint8_t pxxRxNum ; + int8_t dsmMode ; + uint8_t xPxxRxNum ; // For external module + uint16_t modelswitchWarningStates ; // Enough bits for Taranis + int8_t enRssiOrange:2 ; + int8_t rssiOrange:6 ; + uint8_t enRssiRed:2 ; + int8_t rssiRed:6 ; +// uint8_t spare24:6 ; +// uint8_t curentSource ; +// uint8_t altSource ; +}) SKYModelData; + + +extern SKYModelData g_model; + + + + +#endif +/*eof*/ + + + diff --git a/radio/bootloader/include/radio.h b/radio/bootloader/include/radio.h new file mode 100644 index 000000000..dc6e1993c --- /dev/null +++ b/radio/bootloader/include/radio.h @@ -0,0 +1,64 @@ + + +#include + +#ifdef PCBSKY +#define wdt_reset() (WDT->WDT_CR = 0xA5000001) +#endif +#ifdef PCBX9D +#define wdt_reset() (IWDG->KR = 0x0000AAAAL) +#endif + +#define POWER_OFF 0 +#define POWER_ON 1 + +#define DIM(arr) (sizeof((arr))/sizeof((arr)[0])) + +#define BITMASK(bit) (1<<(bit)) + +#define _MSK_KEY_REPT 0x40 +#define _MSK_KEY_DBL 0x10 +#define IS_KEY_BREAK(key) (((key)&0xf0) == 0x20) +#define EVT_KEY_BREAK(key) ((key)| 0x20) +#define EVT_KEY_FIRST(key) ((key)| _MSK_KEY_REPT|0x20) +#define EVT_KEY_REPT(key) ((key)| _MSK_KEY_REPT ) +#define EVT_KEY_LONG(key) ((key)|0x80) +#define EVT_KEY_DBL(key) ((key)|_MSK_KEY_DBL) +//#define EVT_KEY_DBL(key) ((key)|0x10) +#define EVT_ENTRY (0xff - _MSK_KEY_REPT) +#define EVT_ENTRY_UP (0xfe - _MSK_KEY_REPT) +#define EVT_KEY_MASK 0x0f + + +#define NUM_KEYS 6 + +#ifdef PCBSKY +enum EnumKeys { + KEY_MENU , + KEY_EXIT , + KEY_DOWN , + KEY_UP , + KEY_RIGHT , + KEY_LEFT +} ; +#endif + +#ifdef PCBX9D +enum EnumKeys { + KEY_MENU , + KEY_EXIT , + KEY_ENTER , + KEY_PAGE , + KEY_PLUS , + KEY_MINUS +} ; +#endif + +extern void init_SDcard( void ) ; +extern unsigned long Master_frequency ; + +extern void init_soft_power( void ) ; +extern uint32_t check_soft_power( void ) ; +extern void soft_power_off( void ) ; + + diff --git a/radio/bootloader/include/rtc.h b/radio/bootloader/include/rtc.h new file mode 100644 index 000000000..42557e411 --- /dev/null +++ b/radio/bootloader/include/rtc.h @@ -0,0 +1,71 @@ +/* + * Authors (alphabetical order) + * - Andre Bernet + * - Andreas Weitl + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Gabriel Birkus + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * opentx is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef RTC_H +#define RTC_H + +#include + +typedef long int gtime_t; + +struct gtm +{ + int8_t tm_sec; /* Seconds. [0-60] (1 leap second) */ + int8_t tm_min; /* Minutes. [0-59] */ + int8_t tm_hour; /* Hours. [0-23] */ + int8_t tm_mday; /* Day. [1-31] */ + int8_t tm_mon; /* Month. [0-11] */ + int8_t tm_year; /* Year - 1900. Limited to the year 2115. Oh no! :P */ + int8_t tm_wday; /* Day of week. [0-6] */ + int16_t tm_yday; /* Day of year. [0-365] Needed internally for calculations */ +}; + +extern gtime_t g_rtcTime; +extern uint8_t g_ms100; // global to allow time set function to reset to zero + +void rtcInit(); + +#ifdef __cplusplus +extern "C" { +#endif +void rtcSetTime(struct gtm * tm); +void gettime(struct gtm * tm); +gtime_t gmktime (struct gtm *tm); +#ifdef __cplusplus +} +#endif + +#endif diff --git a/radio/bootloader/include/stm32f2xx.h b/radio/bootloader/include/stm32f2xx.h new file mode 100644 index 000000000..d62d9396a --- /dev/null +++ b/radio/bootloader/include/stm32f2xx.h @@ -0,0 +1,6966 @@ +/** + ****************************************************************************** + * @file stm32f2xx.h + * @author MCD Application Team + * @version V1.1.3 + * @date 05-March-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F2xx devices. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The device used in the target application + * - To use or not the peripherals drivers in application code(i.e. + * code will be based on direct access to peripherals registers + * rather than drivers API), this option is controlled by + * "#define USE_STDPERIPH_DRIVER" + * - To change few application-specific parameters such as the HSE + * crystal frequency + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx + * @{ + */ + +#ifndef __STM32F2xx_H +#define __STM32F2xx_H + +// TODO added by BSS +#define assert_param(xx) + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F2XX) + #define STM32F2XX +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +#if !defined (STM32F2XX) + #error "Please select first the target STM32F2XX device used in your application (in stm32f2xx.h file)" +#endif + +#if !defined (USE_STDPERIPH_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif /* USE_STDPERIPH_DRIVER */ + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ +#endif /* HSE_STARTUP_TIMEOUT */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief STM32F2XX Standard Peripherals Library version number V1.1.3 + */ +#define __STM32F2XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F2XX_STDPERIPH_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ +#define __STM32F2XX_STDPERIPH_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ +#define __STM32F2XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F2XX_STDPERIPH_VERSION ((__STM32F2XX_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32F2XX_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32F2XX_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32F2XX_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ +#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */ +#define __MPU_PRESENT 1 /*!< STM32F2XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F2XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @brief STM32F2XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH_RNG_IRQn = 80 /*!< Hash and Rng global interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +#include "system_stm32f2xx.h" +#include + +/** @addtogroup Exported_types + * @{ + */ +/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/** + * @} + */ + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + __IO uint32_t RESERVED8; + __IO uint32_t PTPTSSR; /* added for STM32F2xx */ + uint32_t RESERVED9[565]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + __IO uint32_t DMARSWTR; /* added for STM32F2xx */ + uint32_t RESERVED10[8]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x14 */ +} FLASH_TypeDef; + +/** + * @brief Flexible Static Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FSMC_Bank1_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FSMC_Bank1E_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ +} FSMC_Bank2_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FSMC_Bank3_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank4 + */ + +typedef struct +{ + __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ + __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ + __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ + __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ + __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ +} FSMC_Bank4_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ + __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + uint32_t RESERVED3; /*!< Reserved, 0x38 */ + uint32_t RESERVED4; /*!< Reserved, 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + uint32_t RESERVED5; /*!< Reserved, 0x44 */ + uint32_t RESERVED6; /*!< Reserved, 0x48 */ + uint32_t RESERVED7; /*!< Reserved, 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ +} RTC_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ +} SPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + uint16_t RESERVED11; /*!< Reserved, 0x46 */ + __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + uint16_t RESERVED12; /*!< Reserved, 0x4A */ + __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint16_t RESERVED13; /*!< Reserved, 0x4E */ + __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ + uint16_t RESERVED14; /*!< Reserved, 0x52 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief Crypto Processor + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */ + __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ + __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ + __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ + __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ + __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ + __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ + __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ + __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ + __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ + __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ + __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ + __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ + __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ + __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ + __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ + __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ + __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ +} CRYP_TypeDef; + +/** + * @brief HASH + */ + +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[51]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1C0 */ +} HASH_TypeDef; + +/** + * @brief HASH + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ + +#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x0400) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2100) +#define ADC3_BASE (APB2PERIPH_BASE + 0x2200) +#define ADC_BASE (APB2PERIPH_BASE + 0x2300) +#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800) + +/*!< AHB1 peripherals */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) +#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) +#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) +#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) +#define BKPSRAM_BASE (AHB1PERIPH_BASE + 0x4000) +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) +#define ETH_BASE (AHB1PERIPH_BASE + 0x8000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) + +/*!< AHB2 peripherals */ +#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) +#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000) +#define HASH_BASE (AHB2PERIPH_BASE + 0x60400) +#define RNG_BASE (AHB2PERIPH_BASE + 0x60800) + +/*!< FSMC Bankx registers base address */ +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) +#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) +#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) +#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE ((uint32_t )0xE0042000) + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define CRYP ((CRYP_TypeDef *) CRYP_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) +#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) +#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) +#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((uint8_t)0x01) /*!*/ + +#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!
© COPYRIGHT 2012 STMicroelectronics
+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_FLASH_H +#define __STM32F2xx_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** + * @brief FLASH Status + */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PGS, + FLASH_ERROR_PGP, + FLASH_ERROR_PGA, + FLASH_ERROR_WRP, + FLASH_ERROR_PROGRAM, + FLASH_ERROR_OPERATION, + FLASH_COMPLETE +}FLASH_Status; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup FLASH_Exported_Constants + * @{ + */ + +/** @defgroup Flash_Latency + * @{ + */ +#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint8_t)0x0001) /*!< FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint8_t)0x0002) /*!< FLASH Two Latency cycles */ +#define FLASH_Latency_3 ((uint8_t)0x0003) /*!< FLASH Three Latency cycles */ +#define FLASH_Latency_4 ((uint8_t)0x0004) /*!< FLASH Four Latency cycles */ +#define FLASH_Latency_5 ((uint8_t)0x0005) /*!< FLASH Five Latency cycles */ +#define FLASH_Latency_6 ((uint8_t)0x0006) /*!< FLASH Six Latency cycles */ +#define FLASH_Latency_7 ((uint8_t)0x0007) /*!< FLASH Seven Latency cycles */ + +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ + ((LATENCY) == FLASH_Latency_1) || \ + ((LATENCY) == FLASH_Latency_2) || \ + ((LATENCY) == FLASH_Latency_3) || \ + ((LATENCY) == FLASH_Latency_4) || \ + ((LATENCY) == FLASH_Latency_5) || \ + ((LATENCY) == FLASH_Latency_6) || \ + ((LATENCY) == FLASH_Latency_7)) +/** + * @} + */ + +/** @defgroup FLASH_Voltage_Range + * @{ + */ +#define VoltageRange_1 ((uint8_t)0x00) /*!< Device operating range: 1.8V to 2.1V */ +#define VoltageRange_2 ((uint8_t)0x01) /*!= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\ + (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F))) +/** + * @} + */ + +/** @defgroup Option_Bytes_Write_Protection + * @{ + */ +#define OB_WRP_Sector_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */ +#define OB_WRP_Sector_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */ +#define OB_WRP_Sector_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */ +#define OB_WRP_Sector_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */ +#define OB_WRP_Sector_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */ +#define OB_WRP_Sector_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */ +#define OB_WRP_Sector_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */ +#define OB_WRP_Sector_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */ +#define OB_WRP_Sector_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */ +#define OB_WRP_Sector_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */ +#define OB_WRP_Sector_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */ +#define OB_WRP_Sector_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */ +#define OB_WRP_Sector_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */ + +#define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_Read_Protection + * @{ + */ +#define OB_RDP_Level_0 ((uint8_t)0xAA) +#define OB_RDP_Level_1 ((uint8_t)0x55) +/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2 + it's no more possible to go back to level 1 or 0 */ +#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\ + ((LEVEL) == OB_RDP_Level_1))/*||\ + ((LEVEL) == OB_RDP_Level_2))*/ +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_IWatchdog + * @{ + */ +#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */ +#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_nRST_STOP + * @{ + */ +#define OB_STOP_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) +/** + * @} + */ + + +/** @defgroup FLASH_Option_Bytes_nRST_STDBY + * @{ + */ +#define OB_STDBY_NoRST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) +/** + * @} + */ + +/** @defgroup FLASH_BOR_Reset_Level + * @{ + */ +#define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */ +#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */ +#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */ +#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */ +#define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\ + ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF)) +/** + * @} + */ + +/** @defgroup FLASH_Interrupts + * @{ + */ +#define FLASH_IT_EOP ((uint32_t)0x01000000) /*!< End of FLASH Operation Interrupt source */ +#define FLASH_IT_ERR ((uint32_t)0x02000000) /*!< Error Interrupt source */ +#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000)) +/** + * @} + */ + +/** @defgroup FLASH_Flags + * @{ + */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000001) /*!< FLASH End of Operation flag */ +#define FLASH_FLAG_OPERR ((uint32_t)0x00000002) /*!< FLASH operation Error flag */ +#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_PGAERR ((uint32_t)0x00000020) /*!< FLASH Programming Alignment error flag */ +#define FLASH_FLAG_PGPERR ((uint32_t)0x00000040) /*!< FLASH Programming Parallelism error flag */ +#define FLASH_FLAG_PGSERR ((uint32_t)0x00000080) /*!< FLASH Programming Sequence error flag */ +#define FLASH_FLAG_BSY ((uint32_t)0x00010000) /*!< FLASH Busy flag */ +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF0C) == 0x00000000) && ((FLAG) != 0x00000000)) +#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \ + ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \ + ((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \ + ((FLAG) == FLASH_FLAG_BSY)) +/** + * @} + */ + +/** @defgroup FLASH_Program_Parallelism + * @{ + */ +#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000) +#define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100) +#define FLASH_PSIZE_WORD ((uint32_t)0x00000200) +#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300) +#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF) +/** + * @} + */ + +/** @defgroup FLASH_Keys + * @{ + */ +#define RDP_KEY ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) +#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B) +#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F) +/** + * @} + */ + +/** + * @brief ACR register byte 0 (Bits[8:0]) base address + */ +#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00) +/** + * @brief OPTCR register byte 3 (Bits[24:16]) base address + */ +#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14) +#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15) +#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16) + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* FLASH Interface configuration functions ************************************/ +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_PrefetchBufferCmd(FunctionalState NewState); +void FLASH_InstructionCacheCmd(FunctionalState NewState); +void FLASH_DataCacheCmd(FunctionalState NewState); +void FLASH_InstructionCacheReset(void); +void FLASH_DataCacheReset(void); + +/* FLASH Memory Programming functions *****************************************/ +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange); +FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange); +FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data); +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); +FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data); + +/* Option Bytes Programming functions *****************************************/ +void FLASH_OB_Unlock(void); +void FLASH_OB_Lock(void); +void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState); +void FLASH_OB_RDPConfig(uint8_t OB_RDP); +void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); +void FLASH_OB_BORConfig(uint8_t OB_BOR); +FLASH_Status FLASH_OB_Launch(void); +uint8_t FLASH_OB_GetUser(void); +uint16_t FLASH_OB_GetWRP(void); +FlagStatus FLASH_OB_GetRDP(void); +uint8_t FLASH_OB_GetBOR(void); + +/* Interrupts and flags management functions **********************************/ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_FLASH_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/include/stm32f2xx_gpio.h b/radio/bootloader/include/stm32f2xx_gpio.h new file mode 100644 index 000000000..b0c6b5f7c --- /dev/null +++ b/radio/bootloader/include/stm32f2xx_gpio.h @@ -0,0 +1,411 @@ +/** + ****************************************************************************** + * @file stm32f2xx_gpio.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the GPIO firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_GPIO_H +#define __STM32F2xx_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ + ((PERIPH) == GPIOB) || \ + ((PERIPH) == GPIOC) || \ + ((PERIPH) == GPIOD) || \ + ((PERIPH) == GPIOE) || \ + ((PERIPH) == GPIOF) || \ + ((PERIPH) == GPIOG) || \ + ((PERIPH) == GPIOH) || \ + ((PERIPH) == GPIOI)) + +/** + * @brief GPIO Configuration Mode enumeration + */ +typedef enum +{ + GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */ + GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */ + GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */ + GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */ +}GPIOMode_TypeDef; +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \ + ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN)) + +/** + * @brief GPIO Output type enumeration + */ +typedef enum +{ + GPIO_OType_PP = 0x00, + GPIO_OType_OD = 0x01 +}GPIOOType_TypeDef; +#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD)) + + +/** + * @brief GPIO Output Maximum frequency enumeration + */ +typedef enum +{ + GPIO_Speed_2MHz = 0x00, /*!< Low speed */ + GPIO_Speed_25MHz = 0x01, /*!< Medium speed */ + GPIO_Speed_50MHz = 0x02, /*!< Fast speed */ + GPIO_Speed_100MHz = 0x03 /*!< High speed on 30 pF (80 MHz Output max speed on 15 pF) */ +}GPIOSpeed_TypeDef; +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_2MHz) || ((SPEED) == GPIO_Speed_25MHz) || \ + ((SPEED) == GPIO_Speed_50MHz)|| ((SPEED) == GPIO_Speed_100MHz)) + +/** + * @brief GPIO Configuration PullUp PullDown enumeration + */ +typedef enum +{ + GPIO_PuPd_NOPULL = 0x00, + GPIO_PuPd_UP = 0x01, + GPIO_PuPd_DOWN = 0x02 +}GPIOPuPd_TypeDef; +#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \ + ((PUPD) == GPIO_PuPd_DOWN)) + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +}BitAction; +#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) + + +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ + + GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIOOType_TypeDef */ + + GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIOPuPd_TypeDef */ +}GPIO_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Constants + * @{ + */ + +/** @defgroup GPIO_pins_define + * @{ + */ +#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ + +#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) +#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ + ((PIN) == GPIO_Pin_1) || \ + ((PIN) == GPIO_Pin_2) || \ + ((PIN) == GPIO_Pin_3) || \ + ((PIN) == GPIO_Pin_4) || \ + ((PIN) == GPIO_Pin_5) || \ + ((PIN) == GPIO_Pin_6) || \ + ((PIN) == GPIO_Pin_7) || \ + ((PIN) == GPIO_Pin_8) || \ + ((PIN) == GPIO_Pin_9) || \ + ((PIN) == GPIO_Pin_10) || \ + ((PIN) == GPIO_Pin_11) || \ + ((PIN) == GPIO_Pin_12) || \ + ((PIN) == GPIO_Pin_13) || \ + ((PIN) == GPIO_Pin_14) || \ + ((PIN) == GPIO_Pin_15)) +/** + * @} + */ + + +/** @defgroup GPIO_Pin_sources + * @{ + */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + +#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ + ((PINSOURCE) == GPIO_PinSource1) || \ + ((PINSOURCE) == GPIO_PinSource2) || \ + ((PINSOURCE) == GPIO_PinSource3) || \ + ((PINSOURCE) == GPIO_PinSource4) || \ + ((PINSOURCE) == GPIO_PinSource5) || \ + ((PINSOURCE) == GPIO_PinSource6) || \ + ((PINSOURCE) == GPIO_PinSource7) || \ + ((PINSOURCE) == GPIO_PinSource8) || \ + ((PINSOURCE) == GPIO_PinSource9) || \ + ((PINSOURCE) == GPIO_PinSource10) || \ + ((PINSOURCE) == GPIO_PinSource11) || \ + ((PINSOURCE) == GPIO_PinSource12) || \ + ((PINSOURCE) == GPIO_PinSource13) || \ + ((PINSOURCE) == GPIO_PinSource14) || \ + ((PINSOURCE) == GPIO_PinSource15)) +/** + * @} + */ + +/** @defgroup GPIO_Alternat_function_selection_define + * @{ + */ +/** + * @brief AF 0 selection + */ +#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ +#define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */ +#define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ + ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ + ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ + ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ + ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ + ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ + ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ + ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ + ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ + ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ + ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ + ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \ + ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \ + ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \ + ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ + ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_FSMC) || \ + ((AF) == GPIO_AF_OTG_HS_FS) || ((AF) == GPIO_AF_SDIO) || \ + ((AF) == GPIO_AF_DCMI) || ((AF) == GPIO_AF_EVENTOUT)) +/** + * @} + */ + +/** @defgroup GPIO_Legacy + * @{ + */ + +#define GPIO_Mode_AIN GPIO_Mode_AN + +#define GPIO_AF_OTG1_FS GPIO_AF_OTG_FS +#define GPIO_AF_OTG2_HS GPIO_AF_OTG_HS +#define GPIO_AF_OTG2_FS GPIO_AF_OTG_HS_FS + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the GPIO configuration to the default reset state ****/ +void GPIO_DeInit(GPIO_TypeDef* GPIOx); + +/* Initialization and Configuration functions *********************************/ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); + +/* GPIO Read and Write functions **********************************************/ +//uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); +//void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +//void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); +void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); + +/* GPIO Alternate functions configuration function ****************************/ +void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F2xx_GPIO_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/include/stm32f2xx_rcc.h b/radio/bootloader/include/stm32f2xx_rcc.h new file mode 100644 index 000000000..b87733e32 --- /dev/null +++ b/radio/bootloader/include/stm32f2xx_rcc.h @@ -0,0 +1,515 @@ +/** + ****************************************************************************** + * @file stm32f2xx_rcc.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the RCC firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_RCC_H +#define __STM32F2xx_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */ + uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */ + uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */ + uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */ +}RCC_ClocksTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Constants + * @{ + */ + +/** @defgroup RCC_HSE_configuration + * @{ + */ +#define RCC_HSE_OFF ((uint8_t)0x00) +#define RCC_HSE_ON ((uint8_t)0x01) +#define RCC_HSE_Bypass ((uint8_t)0x05) +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_Bypass)) +/** + * @} + */ + +/** @defgroup RCC_PLL_Clock_Source + * @{ + */ +#define RCC_PLLSource_HSI ((uint32_t)0x00000000) +#define RCC_PLLSource_HSE ((uint32_t)0x00400000) +#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \ + ((SOURCE) == RCC_PLLSource_HSE)) +#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63) +#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) +#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) +#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15)) + +#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) +#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source + * @{ + */ +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) +#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ + ((SOURCE) == RCC_SYSCLKSource_HSE) || \ + ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source + * @{ + */ +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ + ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ + ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ + ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ + ((HCLK) == RCC_SYSCLK_Div512)) +/** + * @} + */ + +/** @defgroup RCC_APB1_APB2_Clock_Source + * @{ + */ +#define RCC_HCLK_Div1 ((uint32_t)0x00000000) +#define RCC_HCLK_Div2 ((uint32_t)0x00001000) +#define RCC_HCLK_Div4 ((uint32_t)0x00001400) +#define RCC_HCLK_Div8 ((uint32_t)0x00001800) +#define RCC_HCLK_Div16 ((uint32_t)0x00001C00) +#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ + ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ + ((PCLK) == RCC_HCLK_Div16)) +/** + * @} + */ + +/** @defgroup RCC_Interrupt_Source + * @{ + */ +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_PLLI2SRDY ((uint8_t)0x20) +#define RCC_IT_CSS ((uint8_t)0x80) +#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00)) +#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ + ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ + ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ + ((IT) == RCC_IT_PLLI2SRDY)) +#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00)) +/** + * @} + */ + +/** @defgroup RCC_LSE_Configuration + * @{ + */ +#define RCC_LSE_OFF ((uint8_t)0x00) +#define RCC_LSE_ON ((uint8_t)0x01) +#define RCC_LSE_Bypass ((uint8_t)0x04) +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_Bypass)) +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source + * @{ + */ +#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) +#define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300) +#define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300) +#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300) +#define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300) +#define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300) +#define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300) +#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300) +#define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300) +#define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300) +#define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300) +#define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300) +#define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300) +#define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300) +#define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300) +#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300) +#define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300) +#define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300) +#define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300) +#define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300) +#define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300) +#define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300) +#define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300) +#define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300) +#define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300) +#define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300) +#define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300) +#define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300) +#define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300) +#define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300) +#define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300) +#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ + ((SOURCE) == RCC_RTCCLKSource_LSI) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div31)) +/** + * @} + */ + +/** @defgroup RCC_I2S_Clock_Source + * @{ + */ +#define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00) +#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01) + +#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext)) +/** + * @} + */ + +/** @defgroup RCC_AHB1_Peripherals + * @{ + */ +#define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001) +#define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002) +#define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004) +#define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008) +#define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010) +#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020) +#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040) +#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080) +#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100) +#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000) +#define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000) +#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000) +#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000) +#define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000) +#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000) +#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000) +#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000) +#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000) +#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000) +#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000) +#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000) +#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000) +#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x819BEE00) == 0x00) && ((PERIPH) != 0x00)) +#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00)) +#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81986E00) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup RCC_AHB2_Peripherals + * @{ + */ +#define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001) +#define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010) +#define RCC_AHB2Periph_HASH ((uint32_t)0x00000020) +#define RCC_AHB2Periph_RNG ((uint32_t)0x00000040) +#define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080) +#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup RCC_AHB3_Peripherals + * @{ + */ +#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001) +#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup RCC_APB1_Peripherals + * @{ + */ +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) +#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) +#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) +#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) +#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) +#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) +#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) +#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) +#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) +#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) +#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) +#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) +#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000) +#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) +#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) +#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) +#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC9013600) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup RCC_APB2_Peripherals + * @{ + */ +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001) +#define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002) +#define RCC_APB2Periph_USART1 ((uint32_t)0x00000010) +#define RCC_APB2Periph_USART6 ((uint32_t)0x00000020) +#define RCC_APB2Periph_ADC ((uint32_t)0x00000100) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100) +#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200) +#define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400) +#define RCC_APB2Periph_SDIO ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000) +#define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000) +#define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000) +#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000) +#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A0CC) == 0x00) && ((PERIPH) != 0x00)) +#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A6CC) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup RCC_MCO1_Clock_Source_Prescaler + * @{ + */ +#define RCC_MCO1Source_HSI ((uint32_t)0x00000000) +#define RCC_MCO1Source_LSE ((uint32_t)0x00200000) +#define RCC_MCO1Source_HSE ((uint32_t)0x00400000) +#define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000) +#define RCC_MCO1Div_1 ((uint32_t)0x00000000) +#define RCC_MCO1Div_2 ((uint32_t)0x04000000) +#define RCC_MCO1Div_3 ((uint32_t)0x05000000) +#define RCC_MCO1Div_4 ((uint32_t)0x06000000) +#define RCC_MCO1Div_5 ((uint32_t)0x07000000) +#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \ + ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK)) + +#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \ + ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \ + ((DIV) == RCC_MCO1Div_5)) +/** + * @} + */ + +/** @defgroup RCC_MCO2_Clock_Source_Prescaler + * @{ + */ +#define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000) +#define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000) +#define RCC_MCO2Source_HSE ((uint32_t)0x80000000) +#define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000) +#define RCC_MCO2Div_1 ((uint32_t)0x00000000) +#define RCC_MCO2Div_2 ((uint32_t)0x20000000) +#define RCC_MCO2Div_3 ((uint32_t)0x28000000) +#define RCC_MCO2Div_4 ((uint32_t)0x30000000) +#define RCC_MCO2Div_5 ((uint32_t)0x38000000) +#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \ + ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK)) + +#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \ + ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \ + ((DIV) == RCC_MCO2Div_5)) +/** + * @} + */ + +/** @defgroup RCC_Flag + * @{ + */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) +#define RCC_FLAG_LSERDY ((uint8_t)0x41) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_BORRST ((uint8_t)0x79) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) +#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \ + ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ + ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ + ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \ + ((FLAG) == RCC_FLAG_PLLI2SRDY)) +#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the RCC clock configuration to the default reset state */ +void RCC_DeInit(void); + +/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ +void RCC_HSEConfig(uint8_t RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_LSEConfig(uint8_t RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); + +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ); +void RCC_PLLCmd(FunctionalState NewState); +void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR); +void RCC_PLLI2SCmd(FunctionalState NewState); + +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div); +void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div); + +/* System, AHB and APB busses clocks configuration functions ******************/ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_PCLK1Config(uint32_t RCC_HCLK); +void RCC_PCLK2Config(uint32_t RCC_HCLK); +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); + +/* Peripheral clocks configuration functions **********************************/ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); +void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); + +void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); +void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); +void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); + +void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); +void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); +void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); + +void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); +void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); +void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); +void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_RCC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/include/stm32f2xx_rtc.h b/radio/bootloader/include/stm32f2xx_rtc.h new file mode 100644 index 000000000..677f9783b --- /dev/null +++ b/radio/bootloader/include/stm32f2xx_rtc.h @@ -0,0 +1,650 @@ +/** + ****************************************************************************** + * @file stm32f2xx_rtc.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the RTC firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_RTC_H +#define __STM32F2xx_RTC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +//#include "X9D/stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief RTC Init structures definition + */ +typedef struct +{ + uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format. + This parameter can be a value of @ref RTC_Hour_Formats */ + + uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. + This parameter must be set to a value lower than 0x7F */ + + uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. + This parameter must be set to a value lower than 0x1FFF */ +}RTC_InitTypeDef; + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour. + This parameter must be set to a value in the 0-12 range + if the RTC_HourFormat_12 is selected or 0-23 range if + the RTC_HourFormat_24 is selected. */ + + uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes. + This parameter must be set to a value in the 0-59 range. */ + + uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds. + This parameter must be set to a value in the 0-59 range. */ + + uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time. + This parameter can be a value of @ref RTC_AM_PM_Definitions */ +}RTC_TimeTypeDef; + +/** + * @brief RTC Date structure definition + */ +typedef struct +{ + uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay. + This parameter can be a value of @ref RTC_WeekDay_Definitions */ + + uint8_t RTC_Month; /*!< Specifies the RTC Date Month (in BCD format). + This parameter can be a value of @ref RTC_Month_Date_Definitions */ + + uint8_t RTC_Date; /*!< Specifies the RTC Date. + This parameter must be set to a value in the 1-31 range. */ + + uint8_t RTC_Year; /*!< Specifies the RTC Date Year. + This parameter must be set to a value in the 0-99 range. */ +}RTC_DateTypeDef; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct +{ + RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */ + + uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks. + This parameter can be a value of @ref RTC_AlarmMask_Definitions */ + + uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. + This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ + + uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. + If the Alarm Date is selected, this parameter + must be set to a value in the 1-31 range. + If the Alarm WeekDay is selected, this + parameter can be a value of @ref RTC_WeekDay_Definitions */ +}RTC_AlarmTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RTC_Exported_Constants + * @{ + */ + + +/** @defgroup RTC_Hour_Formats + * @{ + */ +#define RTC_HourFormat_24 ((uint32_t)0x00000000) +#define RTC_HourFormat_12 ((uint32_t)0x00000040) +#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \ + ((FORMAT) == RTC_HourFormat_24)) +/** + * @} + */ + +/** @defgroup RTC_Asynchronous_Predivider + * @{ + */ +#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F) + +/** + * @} + */ + + +/** @defgroup RTC_Synchronous_Predivider + * @{ + */ +#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x1FFF) + +/** + * @} + */ + +/** @defgroup RTC_Time_Definitions + * @{ + */ +#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12)) +#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23) +#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59) +#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59) + +/** + * @} + */ + +/** @defgroup RTC_AM_PM_Definitions + * @{ + */ +#define RTC_H12_AM ((uint8_t)0x00) +#define RTC_H12_PM ((uint8_t)0x40) +#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM)) + +/** + * @} + */ + +/** @defgroup RTC_Year_Date_Definitions + * @{ + */ +#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99) + +/** + * @} + */ + +/** @defgroup RTC_Month_Date_Definitions + * @{ + */ + +/* Coded in BCD format */ +#define RTC_Month_January ((uint8_t)0x01) +#define RTC_Month_February ((uint8_t)0x02) +#define RTC_Month_March ((uint8_t)0x03) +#define RTC_Month_April ((uint8_t)0x04) +#define RTC_Month_May ((uint8_t)0x05) +#define RTC_Month_June ((uint8_t)0x06) +#define RTC_Month_July ((uint8_t)0x07) +#define RTC_Month_August ((uint8_t)0x08) +#define RTC_Month_September ((uint8_t)0x09) +#define RTC_Month_October ((uint8_t)0x10) +#define RTC_Month_November ((uint8_t)0x11) +#define RTC_Month_December ((uint8_t)0x12) +#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12)) +#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31)) + +/** + * @} + */ + +/** @defgroup RTC_WeekDay_Definitions + * @{ + */ + +#define RTC_Weekday_Monday ((uint8_t)0x01) +#define RTC_Weekday_Tuesday ((uint8_t)0x02) +#define RTC_Weekday_Wednesday ((uint8_t)0x03) +#define RTC_Weekday_Thursday ((uint8_t)0x04) +#define RTC_Weekday_Friday ((uint8_t)0x05) +#define RTC_Weekday_Saturday ((uint8_t)0x06) +#define RTC_Weekday_Sunday ((uint8_t)0x07) +#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ + ((WEEKDAY) == RTC_Weekday_Tuesday) || \ + ((WEEKDAY) == RTC_Weekday_Wednesday) || \ + ((WEEKDAY) == RTC_Weekday_Thursday) || \ + ((WEEKDAY) == RTC_Weekday_Friday) || \ + ((WEEKDAY) == RTC_Weekday_Saturday) || \ + ((WEEKDAY) == RTC_Weekday_Sunday)) +/** + * @} + */ + + +/** @defgroup RTC_Alarm_Definitions + * @{ + */ +#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31)) +#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ + ((WEEKDAY) == RTC_Weekday_Tuesday) || \ + ((WEEKDAY) == RTC_Weekday_Wednesday) || \ + ((WEEKDAY) == RTC_Weekday_Thursday) || \ + ((WEEKDAY) == RTC_Weekday_Friday) || \ + ((WEEKDAY) == RTC_Weekday_Saturday) || \ + ((WEEKDAY) == RTC_Weekday_Sunday)) + +/** + * @} + */ + + +/** @defgroup RTC_AlarmDateWeekDay_Definitions + * @{ + */ +#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000) +#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000) + +#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \ + ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay)) + +/** + * @} + */ + + +/** @defgroup RTC_AlarmMask_Definitions + * @{ + */ +#define RTC_AlarmMask_None ((uint32_t)0x00000000) +#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000) +#define RTC_AlarmMask_Hours ((uint32_t)0x00800000) +#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000) +#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080) +#define RTC_AlarmMask_All ((uint32_t)0x80808080) +#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) + +/** + * @} + */ + +/** @defgroup RTC_Alarms_Definitions + * @{ + */ +#define RTC_Alarm_A ((uint32_t)0x00000100) +#define RTC_Alarm_B ((uint32_t)0x00000200) +#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B)) +#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET) + +/** + * @} + */ + +/** @defgroup RTC_Wakeup_Timer_Definitions + * @{ + */ +#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000) +#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001) +#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002) +#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003) +#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004) +#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006) +#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \ + ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \ + ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \ + ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \ + ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \ + ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits)) +#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) +/** + * @} + */ + +/** @defgroup RTC_Time_Stamp_Edges_definitions + * @{ + */ +#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000) +#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008) +#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \ + ((EDGE) == RTC_TimeStampEdge_Falling)) +/** + * @} + */ + +/** @defgroup RTC_Output_selection_Definitions + * @{ + */ +#define RTC_Output_Disable ((uint32_t)0x00000000) +#define RTC_Output_AlarmA ((uint32_t)0x00200000) +#define RTC_Output_AlarmB ((uint32_t)0x00400000) +#define RTC_Output_WakeUp ((uint32_t)0x00600000) + +#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \ + ((OUTPUT) == RTC_Output_AlarmA) || \ + ((OUTPUT) == RTC_Output_AlarmB) || \ + ((OUTPUT) == RTC_Output_WakeUp)) + +/** + * @} + */ + +/** @defgroup RTC_Output_Polarity_Definitions + * @{ + */ +#define RTC_OutputPolarity_High ((uint32_t)0x00000000) +#define RTC_OutputPolarity_Low ((uint32_t)0x00100000) +#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \ + ((POL) == RTC_OutputPolarity_Low)) +/** + * @} + */ + + +/** @defgroup RTC_Digital_Calibration_Definitions + * @{ + */ +#define RTC_CalibSign_Positive ((uint32_t)0x00000000) +#define RTC_CalibSign_Negative ((uint32_t)0x00000080) +#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \ + ((SIGN) == RTC_CalibSign_Negative)) +#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20) + +/** + * @} + */ + + +/** @defgroup RTC_DayLightSaving_Definitions + * @{ + */ +#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000) +#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000) +#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \ + ((SAVE) == RTC_DayLightSaving_ADD1H)) + +#define RTC_StoreOperation_Reset ((uint32_t)0x00000000) +#define RTC_StoreOperation_Set ((uint32_t)0x00040000) +#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \ + ((OPERATION) == RTC_StoreOperation_Set)) +/** + * @} + */ + +/** @defgroup RTC_Tamper_Trigger_Definitions + * @{ + */ +#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000) +#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001) +#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \ + ((TRIGGER) == RTC_TamperTrigger_FallingEdge)) + +/** + * @} + */ + +/** @defgroup RTC_Tamper_Pins_Definitions + * @{ + */ +#define RTC_Tamper_1 RTC_TAFCR_TAMP1E +#define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1)) + +/** + * @} + */ + +/** @defgroup RTC_Tamper_Pin_Selection + * @{ + */ +#define RTC_TamperPin_PC13 ((uint32_t)0x00000000) +#define RTC_TamperPin_PI8 ((uint32_t)0x00010000) +#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TamperPin_PC13) || \ + ((PIN) == RTC_TamperPin_PI8)) +/** + * @} + */ + +/** @defgroup RTC_TimeStamp_Pin_Selection + * @{ + */ +#define RTC_TimeStampPin_PC13 ((uint32_t)0x00000000) +#define RTC_TimeStampPin_PI8 ((uint32_t)0x00020000) +#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TimeStampPin_PC13) || \ + ((PIN) == RTC_TimeStampPin_PI8)) +/** + * @} + */ + +/** @defgroup RTC_Output_Type_ALARM_OUT + * @{ + */ +#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000) +#define RTC_OutputType_PushPull ((uint32_t)0x00040000) +#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \ + ((TYPE) == RTC_OutputType_PushPull)) + +/** + * @} + */ + +/** @defgroup RTC_Backup_Registers_Definitions + * @{ + */ + +#define RTC_BKP_DR0 ((uint32_t)0x00000000) +#define RTC_BKP_DR1 ((uint32_t)0x00000001) +#define RTC_BKP_DR2 ((uint32_t)0x00000002) +#define RTC_BKP_DR3 ((uint32_t)0x00000003) +#define RTC_BKP_DR4 ((uint32_t)0x00000004) +#define RTC_BKP_DR5 ((uint32_t)0x00000005) +#define RTC_BKP_DR6 ((uint32_t)0x00000006) +#define RTC_BKP_DR7 ((uint32_t)0x00000007) +#define RTC_BKP_DR8 ((uint32_t)0x00000008) +#define RTC_BKP_DR9 ((uint32_t)0x00000009) +#define RTC_BKP_DR10 ((uint32_t)0x0000000A) +#define RTC_BKP_DR11 ((uint32_t)0x0000000B) +#define RTC_BKP_DR12 ((uint32_t)0x0000000C) +#define RTC_BKP_DR13 ((uint32_t)0x0000000D) +#define RTC_BKP_DR14 ((uint32_t)0x0000000E) +#define RTC_BKP_DR15 ((uint32_t)0x0000000F) +#define RTC_BKP_DR16 ((uint32_t)0x00000010) +#define RTC_BKP_DR17 ((uint32_t)0x00000011) +#define RTC_BKP_DR18 ((uint32_t)0x00000012) +#define RTC_BKP_DR19 ((uint32_t)0x00000013) +#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \ + ((BKP) == RTC_BKP_DR1) || \ + ((BKP) == RTC_BKP_DR2) || \ + ((BKP) == RTC_BKP_DR3) || \ + ((BKP) == RTC_BKP_DR4) || \ + ((BKP) == RTC_BKP_DR5) || \ + ((BKP) == RTC_BKP_DR6) || \ + ((BKP) == RTC_BKP_DR7) || \ + ((BKP) == RTC_BKP_DR8) || \ + ((BKP) == RTC_BKP_DR9) || \ + ((BKP) == RTC_BKP_DR10) || \ + ((BKP) == RTC_BKP_DR11) || \ + ((BKP) == RTC_BKP_DR12) || \ + ((BKP) == RTC_BKP_DR13) || \ + ((BKP) == RTC_BKP_DR14) || \ + ((BKP) == RTC_BKP_DR15) || \ + ((BKP) == RTC_BKP_DR16) || \ + ((BKP) == RTC_BKP_DR17) || \ + ((BKP) == RTC_BKP_DR18) || \ + ((BKP) == RTC_BKP_DR19)) +/** + * @} + */ + +/** @defgroup RTC_Input_parameter_format_definitions + * @{ + */ +#define RTC_Format_BIN ((uint32_t)0x000000000) +#define RTC_Format_BCD ((uint32_t)0x000000001) +#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD)) + +/** + * @} + */ + +/** @defgroup RTC_Flags_Definitions + * @{ + */ +#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000) +#define RTC_FLAG_TSOVF ((uint32_t)0x00001000) +#define RTC_FLAG_TSF ((uint32_t)0x00000800) +#define RTC_FLAG_WUTF ((uint32_t)0x00000400) +#define RTC_FLAG_ALRBF ((uint32_t)0x00000200) +#define RTC_FLAG_ALRAF ((uint32_t)0x00000100) +#define RTC_FLAG_INITF ((uint32_t)0x00000040) +#define RTC_FLAG_RSF ((uint32_t)0x00000020) +#define RTC_FLAG_INITS ((uint32_t)0x00000010) +#define RTC_FLAG_WUTWF ((uint32_t)0x00000004) +#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002) +#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001) +#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \ + ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \ + ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \ + ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \ + ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \ + ((FLAG) == RTC_FLAG_TAMP1F)) +#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFFC0DF) == (uint32_t)RESET)) + +/** + * @} + */ + +/** @defgroup RTC_Interrupts_Definitions + * @{ + */ +#define RTC_IT_TS ((uint32_t)0x00008000) +#define RTC_IT_WUT ((uint32_t)0x00004000) +#define RTC_IT_ALRB ((uint32_t)0x00002000) +#define RTC_IT_ALRA ((uint32_t)0x00001000) +#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */ +#define RTC_IT_TAMP1 ((uint32_t)0x00020000) + +#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET)) +#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \ + ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \ + ((IT) == RTC_IT_TAMP1)) +#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFD0FFF) == (uint32_t)RESET)) + +/** + * @} + */ + +/** @defgroup RTC_Legacy + * @{ + */ +#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig +#define RTC_DigitalCalibCmd RTC_CoarseCalibCmd + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the RTC configuration to the default reset state *****/ +ErrorStatus RTC_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct); +void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct); +void RTC_WriteProtectionCmd(FunctionalState NewState); +ErrorStatus RTC_EnterInitMode(void); +void RTC_ExitInitMode(void); +ErrorStatus RTC_WaitForSynchro(void); +ErrorStatus RTC_RefClockCmd(FunctionalState NewState); + +/* Time and Date configuration functions **************************************/ +ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); +void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct); +void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); +ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); +void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct); +void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); + +/* Alarms (Alarm A and Alarm B) configuration functions **********************/ +void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); +void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct); +void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); +ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState); + +/* WakeUp Timer configuration functions ***************************************/ +void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock); +void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter); +uint32_t RTC_GetWakeUpCounter(void); +ErrorStatus RTC_WakeUpCmd(FunctionalState NewState); + +/* Daylight Saving configuration functions ************************************/ +void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation); +uint32_t RTC_GetStoreOperation(void); + +/* Output pin Configuration function ******************************************/ +void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity); + +/* Coarse Calibration configuration functions *********************************/ +ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value); +ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState); +void RTC_CalibOutputCmd(FunctionalState NewState); + +/* TimeStamp configuration functions ******************************************/ +void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState); +void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, + RTC_DateTypeDef* RTC_StampDateStruct); + +/* Tampers configuration functions ********************************************/ +void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger); +void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState); + +/* Backup Data Registers configuration functions ******************************/ +void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data); +uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR); + +/* RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration + functions ******************************************************************/ +void RTC_TamperPinSelection(uint32_t RTC_TamperPin); +void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin); +void RTC_OutputTypeConfig(uint32_t RTC_OutputType); + +/* Interrupts and flags management functions **********************************/ +void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState); +FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG); +void RTC_ClearFlag(uint32_t RTC_FLAG); +ITStatus RTC_GetITStatus(uint32_t RTC_IT); +void RTC_ClearITPendingBit(uint32_t RTC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F2xx_RTC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/include/stm32f2xx_spi.h b/radio/bootloader/include/stm32f2xx_spi.h new file mode 100644 index 000000000..7a56a23f9 --- /dev/null +++ b/radio/bootloader/include/stm32f2xx_spi.h @@ -0,0 +1,526 @@ +/** + ****************************************************************************** + * @file stm32f2xx_spi.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the SPI + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_SPI_H +#define __STM32F2xx_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +//#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief SPI Init structure definition + */ + +typedef struct +{ + uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint16_t SPI_DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ +}SPI_InitTypeDef; + +/** + * @brief I2S Init structure definition + */ + +typedef struct +{ + + uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_Mode */ + + uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_Standard */ + + uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_Data_Format */ + + uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_MCLK_Output */ + + uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + + uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_Clock_Polarity */ +}I2S_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SPI_Exported_Constants + * @{ + */ + +#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ + ((PERIPH) == SPI2) || \ + ((PERIPH) == SPI3)) + +#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ + ((PERIPH) == SPI3)) + +/** @defgroup SPI_data_direction + * @{ + */ + +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) +#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ + ((MODE) == SPI_Direction_2Lines_RxOnly) || \ + ((MODE) == SPI_Direction_1Line_Rx) || \ + ((MODE) == SPI_Direction_1Line_Tx)) +/** + * @} + */ + +/** @defgroup SPI_mode + * @{ + */ + +#define SPI_Mode_Master ((uint16_t)0x0104) +#define SPI_Mode_Slave ((uint16_t)0x0000) +#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ + ((MODE) == SPI_Mode_Slave)) +/** + * @} + */ + +/** @defgroup SPI_data_size + * @{ + */ + +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ + ((DATASIZE) == SPI_DataSize_8b)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity + * @{ + */ + +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) +#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ + ((CPOL) == SPI_CPOL_High)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase + * @{ + */ + +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) +#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ + ((CPHA) == SPI_CPHA_2Edge)) +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_management + * @{ + */ + +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ + ((NSS) == SPI_NSS_Hard)) +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler + * @{ + */ + +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_256)) +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_transmission + * @{ + */ + +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0080) +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ + ((BIT) == SPI_FirstBit_LSB)) +/** + * @} + */ + +/** @defgroup SPI_I2S_Mode + * @{ + */ + +#define I2S_Mode_SlaveTx ((uint16_t)0x0000) +#define I2S_Mode_SlaveRx ((uint16_t)0x0100) +#define I2S_Mode_MasterTx ((uint16_t)0x0200) +#define I2S_Mode_MasterRx ((uint16_t)0x0300) +#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ + ((MODE) == I2S_Mode_SlaveRx) || \ + ((MODE) == I2S_Mode_MasterTx)|| \ + ((MODE) == I2S_Mode_MasterRx)) +/** + * @} + */ + + +/** @defgroup SPI_I2S_Standard + * @{ + */ + +#define I2S_Standard_Phillips ((uint16_t)0x0000) +#define I2S_Standard_MSB ((uint16_t)0x0010) +#define I2S_Standard_LSB ((uint16_t)0x0020) +#define I2S_Standard_PCMShort ((uint16_t)0x0030) +#define I2S_Standard_PCMLong ((uint16_t)0x00B0) +#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ + ((STANDARD) == I2S_Standard_MSB) || \ + ((STANDARD) == I2S_Standard_LSB) || \ + ((STANDARD) == I2S_Standard_PCMShort) || \ + ((STANDARD) == I2S_Standard_PCMLong)) +/** + * @} + */ + +/** @defgroup SPI_I2S_Data_Format + * @{ + */ + +#define I2S_DataFormat_16b ((uint16_t)0x0000) +#define I2S_DataFormat_16bextended ((uint16_t)0x0001) +#define I2S_DataFormat_24b ((uint16_t)0x0003) +#define I2S_DataFormat_32b ((uint16_t)0x0005) +#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ + ((FORMAT) == I2S_DataFormat_16bextended) || \ + ((FORMAT) == I2S_DataFormat_24b) || \ + ((FORMAT) == I2S_DataFormat_32b)) +/** + * @} + */ + +/** @defgroup SPI_I2S_MCLK_Output + * @{ + */ + +#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) +#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) +#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ + ((OUTPUT) == I2S_MCLKOutput_Disable)) +/** + * @} + */ + +/** @defgroup SPI_I2S_Audio_Frequency + * @{ + */ + +#define I2S_AudioFreq_192k ((uint32_t)192000) +#define I2S_AudioFreq_96k ((uint32_t)96000) +#define I2S_AudioFreq_48k ((uint32_t)48000) +#define I2S_AudioFreq_44k ((uint32_t)44100) +#define I2S_AudioFreq_32k ((uint32_t)32000) +#define I2S_AudioFreq_22k ((uint32_t)22050) +#define I2S_AudioFreq_16k ((uint32_t)16000) +#define I2S_AudioFreq_11k ((uint32_t)11025) +#define I2S_AudioFreq_8k ((uint32_t)8000) +#define I2S_AudioFreq_Default ((uint32_t)2) + +#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ + ((FREQ) <= I2S_AudioFreq_192k)) || \ + ((FREQ) == I2S_AudioFreq_Default)) +/** + * @} + */ + +/** @defgroup SPI_I2S_Clock_Polarity + * @{ + */ + +#define I2S_CPOL_Low ((uint16_t)0x0000) +#define I2S_CPOL_High ((uint16_t)0x0008) +#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ + ((CPOL) == I2S_CPOL_High)) +/** + * @} + */ + +/** @defgroup SPI_I2S_DMA_transfer_requests + * @{ + */ + +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) +#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) +/** + * @} + */ + +/** @defgroup SPI_NSS_internal_software_management + * @{ + */ + +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) +#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ + ((INTERNAL) == SPI_NSSInternalSoft_Reset)) +/** + * @} + */ + +/** @defgroup SPI_CRC_Transmit_Receive + * @{ + */ + +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) +#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) +/** + * @} + */ + +/** @defgroup SPI_direction_transmit_receive + * @{ + */ + +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) +#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ + ((DIRECTION) == SPI_Direction_Tx)) +/** + * @} + */ + +/** @defgroup SPI_I2S_interrupts_definition + * @{ + */ + +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define I2S_IT_UDR ((uint8_t)0x53) +#define SPI_I2S_IT_TIFRFE ((uint8_t)0x58) + +#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ + ((IT) == SPI_I2S_IT_RXNE) || \ + ((IT) == SPI_I2S_IT_ERR)) + +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) + +#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) + +#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE)|| ((IT) == SPI_I2S_IT_TXE) || \ + ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \ + ((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\ + ((IT) == SPI_I2S_IT_TIFRFE)) +/** + * @} + */ + +/** @defgroup SPI_I2S_flags_definition + * @{ + */ + +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) +#define I2S_FLAG_UDR ((uint16_t)0x0008) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) +#define SPI_I2S_FLAG_TIFRFE ((uint16_t)0x0100) + +#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) +#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ + ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ + ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ + ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \ + ((FLAG) == SPI_I2S_FLAG_TIFRFE)) +/** + * @} + */ + +/** @defgroup SPI_CRC_polynomial + * @{ + */ + +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) +/** + * @} + */ + +/** @defgroup SPI_I2S_Legacy + * @{ + */ + +#define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx +#define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx +#define SPI_IT_TXE SPI_I2S_IT_TXE +#define SPI_IT_RXNE SPI_I2S_IT_RXNE +#define SPI_IT_ERR SPI_I2S_IT_ERR +#define SPI_IT_OVR SPI_I2S_IT_OVR +#define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE +#define SPI_FLAG_TXE SPI_I2S_FLAG_TXE +#define SPI_FLAG_OVR SPI_I2S_FLAG_OVR +#define SPI_FLAG_BSY SPI_I2S_FLAG_BSY +#define SPI_DeInit SPI_I2S_DeInit +#define SPI_ITConfig SPI_I2S_ITConfig +#define SPI_DMACmd SPI_I2S_DMACmd +#define SPI_SendData SPI_I2S_SendData +#define SPI_ReceiveData SPI_I2S_ReceiveData +#define SPI_GetFlagStatus SPI_I2S_GetFlagStatus +#define SPI_ClearFlag SPI_I2S_ClearFlag +#define SPI_GetITStatus SPI_I2S_GetITStatus +#define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the SPI configuration to the default reset state *****/ +void SPI_I2S_DeInit(SPI_TypeDef* SPIx); + +/* Initialization and Configuration functions *********************************/ +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); + +/* Data transfers functions ***************************************************/ +void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); + +/* Hardware CRC Calculation functions *****************************************/ +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_TransmitCRC(SPI_TypeDef* SPIx); +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); + +/* DMA transfers management functions *****************************************/ +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F2xx_SPI_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/include/system_stm32f2xx.h b/radio/bootloader/include/system_stm32f2xx.h new file mode 100644 index 000000000..eef082fcd --- /dev/null +++ b/radio/bootloader/include/system_stm32f2xx.h @@ -0,0 +1,105 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.h + * @author MCD Application Team + * @version V1.1.3 + * @date 05-March-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F2XX_H +#define __SYSTEM_STM32F2XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F2xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F2xx_System_Exported_types + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F2XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/include/timers.h b/radio/bootloader/include/timers.h new file mode 100644 index 000000000..9352f1c5a --- /dev/null +++ b/radio/bootloader/include/timers.h @@ -0,0 +1,45 @@ +/**************************************************************************** +* Copyright (c) 2012 by Michael Blandford. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* +****************************************************************************/ + + + + +void init5msTimer( void ) ; +void stop5msTimer( void ) ; + +#ifdef PCBSKY +extern void start_timer0( void ) ; +extern void stop_timer0( void ) ; +extern void init_pwm( void ) ; +#endif + +#ifdef PCBX9D +extern uint32_t Peri1_frequency ; +extern uint32_t Peri2_frequency ; +extern uint32_t Timer_mult1 ; +extern uint32_t Timer_mult2 ; +extern void init_hw_timer( void ) ; +extern void hw_delay( uint16_t time ) ; +extern void init_main_ppm( void ) ; +extern void disable_main_ppm( void ) ; +extern void init_trainer_ppm( void ) ; +extern void init_trainer_capture( void ) ; +extern void setupPulsesPXX(uint8_t module) ; +extern void setupPulses( unsigned int port ) ; +extern void setupPulsesPpm( void ) ; + +#endif + + diff --git a/radio/bootloader/include/usb_bsp.h b/radio/bootloader/include/usb_bsp.h new file mode 100644 index 000000000..4a60bcff6 --- /dev/null +++ b/radio/bootloader/include/usb_bsp.h @@ -0,0 +1,102 @@ +/** + ****************************************************************************** + * @file usb_bsp.h + * @author MCD Application Team + * @version V2.1.0 + * @date 19-March-2012 + * @brief Specific api's relative to the used hardware platform + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_BSP__H__ +#define __USB_BSP__H__ + +/* Includes ------------------------------------------------------------------*/ +#include "usb_core.h" + +/** @addtogroup USB_OTG_DRIVER + * @{ + */ + +/** @defgroup USB_BSP + * @brief This file is the + * @{ + */ + + +/** @defgroup USB_BSP_Exported_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup USB_BSP_Exported_Types + * @{ + */ +/** + * @} + */ + + +/** @defgroup USB_BSP_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USB_BSP_Exported_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup USB_BSP_Exported_FunctionsPrototype + * @{ + */ +void BSP_Init(void); + +void USB_OTG_BSP_Init (USB_OTG_CORE_HANDLE *pdev); +void USB_OTG_BSP_uDelay (const uint32_t usec); +void USB_OTG_BSP_mDelay (const uint32_t msec); +void USB_OTG_BSP_EnableInterrupt (USB_OTG_CORE_HANDLE *pdev); +#ifdef USE_HOST_MODE +void USB_OTG_BSP_ConfigVBUS(USB_OTG_CORE_HANDLE *pdev); +void USB_OTG_BSP_DriveVBUS(USB_OTG_CORE_HANDLE *pdev,uint8_t state); +#endif +/** + * @} + */ + +#endif //__USB_BSP__H__ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/bootloader/include/usb_conf.h b/radio/bootloader/include/usb_conf.h new file mode 100644 index 000000000..5e6d787a6 --- /dev/null +++ b/radio/bootloader/include/usb_conf.h @@ -0,0 +1,175 @@ +/** + ****************************************************************************** + * @file usb_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 19-March-2012 + * @brief General low level driver configuration + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_CONF__H__ +#define __USB_CONF__H__ + +#include "stm32f2xx.h" + +#define HID_IN_EP 0x81 +#define HID_OUT_EP 0x01 + +#define HID_IN_PACKET 4 +#define HID_OUT_PACKET 4 + +/* USB Core and PHY interface configuration. + Tip: To avoid modifying these defines each time you need to change the USB + configuration, you can declare the needed define in your toolchain + compiler preprocessor. + */ +/****************** USB OTG FS PHY CONFIGURATION ******************************* +* The USB OTG FS Core supports one on-chip Full Speed PHY. +* +* The USE_EMBEDDED_PHY symbol is defined in the project compiler preprocessor +* when FS core is used. +*******************************************************************************/ +#ifndef USE_USB_OTG_FS + #define USE_USB_OTG_FS +#endif /* USE_USB_OTG_FS */ + +#ifdef USE_USB_OTG_FS + #define USB_OTG_FS_CORE +#endif + +/******************************************************************************* +* FIFO Size Configuration in Device mode +* +* (i) Receive data FIFO size = RAM for setup packets + +* OUT endpoint control information + +* data OUT packets + miscellaneous +* Space = ONE 32-bits words +* --> RAM for setup packets = 10 spaces +* (n is the nbr of CTRL EPs the device core supports) +* --> OUT EP CTRL info = 1 space +* (one space for status information written to the FIFO along with each +* received packet) +* --> data OUT packets = (Largest Packet Size / 4) + 1 spaces +* (MINIMUM to receive packets) +* --> OR data OUT packets = at least 2*(Largest Packet Size / 4) + 1 spaces +* (if high-bandwidth EP is enabled or multiple isochronous EPs) +* --> miscellaneous = 1 space per OUT EP +* (one space for transfer complete status information also pushed to the +* FIFO with each endpoint's last packet) +* +* (ii)MINIMUM RAM space required for each IN EP Tx FIFO = MAX packet size for +* that particular IN EP. More space allocated in the IN EP Tx FIFO results +* in a better performance on the USB and can hide latencies on the AHB. +* +* (iii) TXn min size = 16 words. (n : Transmit FIFO index) +* (iv) When a TxFIFO is not used, the Configuration should be as follows: +* case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) +* --> Txm can use the space allocated for Txn. +* case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) +* --> Txn should be configured with the minimum space of 16 words +* (v) The FIFO is used optimally when used TxFIFOs are allocated in the top +* of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. +* (vi) In HS case12 FIFO locations should be reserved for internal DMA registers +* so total FIFO size should be 1012 Only instead of 1024 +*******************************************************************************/ + +/****************** USB OTG FS CONFIGURATION **********************************/ +#ifdef USB_OTG_FS_CORE + #define RX_FIFO_FS_SIZE 128 + #define TX0_FIFO_FS_SIZE 64 + #define TX1_FIFO_FS_SIZE 128 + #define TX2_FIFO_FS_SIZE 0 + #define TX3_FIFO_FS_SIZE 0 + +// #define USB_OTG_FS_LOW_PWR_MGMT_SUPPORT +// #define USB_OTG_FS_SOF_OUTPUT_ENABLED +#endif + +/****************** USB OTG MISC CONFIGURATION ********************************/ +#define VBUS_SENSING_ENABLED + +/****************** USB OTG MODE CONFIGURATION ********************************/ +//#define USE_HOST_MODE +#define USE_DEVICE_MODE +//#define USE_OTG_MODE + +#ifndef USB_OTG_FS_CORE + #ifndef USB_OTG_HS_CORE + #error "USB_OTG_HS_CORE or USB_OTG_FS_CORE should be defined" + #endif +#endif + +#ifndef USE_DEVICE_MODE + #ifndef USE_HOST_MODE + #error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" + #endif +#endif + +#ifndef USE_USB_OTG_HS + #ifndef USE_USB_OTG_FS + #error "USE_USB_OTG_HS or USE_USB_OTG_FS should be defined" + #endif +#else //USE_USB_OTG_HS + #ifndef USE_ULPI_PHY + #ifndef USE_EMBEDDED_PHY + #error "USE_ULPI_PHY or USE_EMBEDDED_PHY should be defined" + #endif + #endif +#endif + +/****************** C Compilers dependant keywords ****************************/ +/* In HS mode and when the DMA is used, all variables and data structures dealing + with the DMA during the transaction process should be 4-bytes aligned */ +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined (__GNUC__) /* GNU Compiler */ + #define __ALIGN_END __attribute__ ((aligned (4))) + #define __ALIGN_BEGIN + #else + #define __ALIGN_END + #if defined (__CC_ARM) /* ARM Compiler */ + #define __ALIGN_BEGIN __align(4) + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __ALIGN_BEGIN + #elif defined (__TASKING__) /* TASKING Compiler */ + #define __ALIGN_BEGIN __align(4) + #endif /* __CC_ARM */ + #endif /* __GNUC__ */ +#else + #define __ALIGN_BEGIN + #define __ALIGN_END +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ + +/* __packed keyword used to decrease the data type alignment to 1-byte */ +#if defined (__CC_ARM) /* ARM Compiler */ + #define __packed __packed +#elif defined (__ICCARM__) /* IAR Compiler */ + #define __packed __packed +#elif defined ( __GNUC__ ) /* GNU Compiler */ + #define __packed __attribute__ ((__packed__)) +#elif defined (__TASKING__) /* TASKING Compiler */ + #define __packed __unaligned +#endif /* __CC_ARM */ + +#endif //__USB_CONF__H__ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/bootloader/include/usb_core.h b/radio/bootloader/include/usb_core.h new file mode 100644 index 000000000..55e0fca82 --- /dev/null +++ b/radio/bootloader/include/usb_core.h @@ -0,0 +1,417 @@ +/** + ****************************************************************************** + * @file usb_core.h + * @author MCD Application Team + * @version V2.1.0 + * @date 19-March-2012 + * @brief Header of the Core Layer + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_CORE_H__ +#define __USB_CORE_H__ + +/* Includes ------------------------------------------------------------------*/ +#include "usb_conf.h" +#include "usb_regs.h" +#include "usb_defines.h" + + +/** @addtogroup USB_OTG_DRIVER + * @{ + */ + +/** @defgroup USB_CORE + * @brief usb otg driver core layer + * @{ + */ + + +/** @defgroup USB_CORE_Exported_Defines + * @{ + */ + +#define USB_OTG_EP0_IDLE 0 +#define USB_OTG_EP0_SETUP 1 +#define USB_OTG_EP0_DATA_IN 2 +#define USB_OTG_EP0_DATA_OUT 3 +#define USB_OTG_EP0_STATUS_IN 4 +#define USB_OTG_EP0_STATUS_OUT 5 +#define USB_OTG_EP0_STALL 6 + +#define USB_OTG_EP_TX_DIS 0x0000 +#define USB_OTG_EP_TX_STALL 0x0010 +#define USB_OTG_EP_TX_NAK 0x0020 +#define USB_OTG_EP_TX_VALID 0x0030 + +#define USB_OTG_EP_RX_DIS 0x0000 +#define USB_OTG_EP_RX_STALL 0x1000 +#define USB_OTG_EP_RX_NAK 0x2000 +#define USB_OTG_EP_RX_VALID 0x3000 +/** + * @} + */ +#define MAX_DATA_LENGTH 0x200 + +/** @defgroup USB_CORE_Exported_Types + * @{ + */ + + +typedef enum { + USB_OTG_OK = 0, + USB_OTG_FAIL +}USB_OTG_STS; + +typedef enum { + HC_IDLE = 0, + HC_XFRC, + HC_HALTED, + HC_NAK, + HC_NYET, + HC_STALL, + HC_XACTERR, + HC_BBLERR, + HC_DATATGLERR, +}HC_STATUS; + +typedef enum { + URB_IDLE = 0, + URB_DONE, + URB_NOTREADY, + URB_ERROR, + URB_STALL +}URB_STATE; + +typedef enum { + CTRL_START = 0, + CTRL_XFRC, + CTRL_HALTED, + CTRL_NAK, + CTRL_STALL, + CTRL_XACTERR, + CTRL_BBLERR, + CTRL_DATATGLERR, + CTRL_FAIL +}CTRL_STATUS; + + +typedef struct USB_OTG_hc +{ + uint8_t dev_addr ; + uint8_t ep_num; + uint8_t ep_is_in; + uint8_t speed; + uint8_t do_ping; + uint8_t ep_type; + uint16_t max_packet; + uint8_t data_pid; + uint8_t *xfer_buff; + uint32_t xfer_len; + uint32_t xfer_count; + uint8_t toggle_in; + uint8_t toggle_out; + uint32_t dma_addr; +} +USB_OTG_HC , *PUSB_OTG_HC; + +typedef struct USB_OTG_ep +{ + uint8_t num; + uint8_t is_in; + uint8_t is_stall; + uint8_t type; + uint8_t data_pid_start; + uint8_t even_odd_frame; + uint16_t tx_fifo_num; + uint32_t maxpacket; + /* transaction level variables*/ + uint8_t *xfer_buff; + uint32_t dma_addr; + uint32_t xfer_len; + uint32_t xfer_count; + /* Transfer level variables*/ + uint32_t rem_data_len; + uint32_t total_data_len; + uint32_t ctl_data_len; + +} + +USB_OTG_EP , *PUSB_OTG_EP; + + + +typedef struct USB_OTG_core_cfg +{ + uint8_t host_channels; + uint8_t dev_endpoints; + uint8_t speed; + uint8_t dma_enable; + uint16_t mps; + uint16_t TotalFifoSize; + uint8_t phy_itface; + uint8_t Sof_output; + uint8_t low_power; + uint8_t coreID; + +} +USB_OTG_CORE_CFGS, *PUSB_OTG_CORE_CFGS; + + + +typedef struct usb_setup_req { + + uint8_t bmRequest; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} USB_SETUP_REQ; + +typedef struct _Device_TypeDef +{ + uint8_t *(*GetDeviceDescriptor)( uint8_t speed , uint16_t *length); + uint8_t *(*GetLangIDStrDescriptor)( uint8_t speed , uint16_t *length); + uint8_t *(*GetManufacturerStrDescriptor)( uint8_t speed , uint16_t *length); + uint8_t *(*GetProductStrDescriptor)( uint8_t speed , uint16_t *length); + uint8_t *(*GetSerialStrDescriptor)( uint8_t speed , uint16_t *length); + uint8_t *(*GetConfigurationStrDescriptor)( uint8_t speed , uint16_t *length); + uint8_t *(*GetInterfaceStrDescriptor)( uint8_t speed , uint16_t *length); +} USBD_DEVICE, *pUSBD_DEVICE; + +//typedef struct USB_OTG_hPort +//{ +// void (*Disconnect) (void *phost); +// void (*Connect) (void *phost); +// uint8_t ConnStatus; +// uint8_t DisconnStatus; +// uint8_t ConnHandled; +// uint8_t DisconnHandled; +//} USB_OTG_hPort_TypeDef; + +typedef struct _Device_cb +{ + uint8_t (*Init) (void *pdev , uint8_t cfgidx); + uint8_t (*DeInit) (void *pdev , uint8_t cfgidx); + /* Control Endpoints*/ + uint8_t (*Setup) (void *pdev , USB_SETUP_REQ *req); + uint8_t (*EP0_TxSent) (void *pdev ); + uint8_t (*EP0_RxReady) (void *pdev ); + /* Class Specific Endpoints*/ + uint8_t (*DataIn) (void *pdev , uint8_t epnum); + uint8_t (*DataOut) (void *pdev , uint8_t epnum); + uint8_t (*SOF) (void *pdev); + uint8_t (*IsoINIncomplete) (void *pdev); + uint8_t (*IsoOUTIncomplete) (void *pdev); + + uint8_t *(*GetConfigDescriptor)( uint8_t speed , uint16_t *length); +#ifdef USB_OTG_HS_CORE + uint8_t *(*GetOtherConfigDescriptor)( uint8_t speed , uint16_t *length); +#endif + +#ifdef USB_SUPPORT_USER_STRING_DESC + uint8_t *(*GetUsrStrDescriptor)( uint8_t speed ,uint8_t index, uint16_t *length); +#endif + +} USBD_Class_cb_TypeDef; + + + +typedef struct _USBD_USR_PROP +{ + void (*Init)(void); + void (*DeviceReset)(uint8_t speed); + void (*DeviceConfigured)(void); + void (*DeviceSuspended)(void); + void (*DeviceResumed)(void); + + void (*DeviceConnected)(void); + void (*DeviceDisconnected)(void); + +} +USBD_Usr_cb_TypeDef; + +typedef struct _DCD +{ + uint8_t device_config; + uint8_t device_state; + uint8_t device_status; + uint8_t device_old_status; + uint8_t device_address; + uint8_t connection_status; + uint8_t test_mode; + uint32_t DevRemoteWakeup; + USB_OTG_EP in_ep [USB_OTG_MAX_TX_FIFOS]; + USB_OTG_EP out_ep [USB_OTG_MAX_TX_FIFOS]; + uint8_t setup_packet [8*3]; + USBD_Class_cb_TypeDef *class_cb; + USBD_Usr_cb_TypeDef *usr_cb; + USBD_DEVICE *usr_device; + uint8_t *pConfig_descriptor; + } +DCD_DEV , *DCD_PDEV; + + +typedef struct _HCD +{ + uint8_t Rx_Buffer [MAX_DATA_LENGTH]; + __IO uint32_t ConnSts; + __IO uint32_t ErrCnt[USB_OTG_MAX_TX_FIFOS]; + __IO uint32_t XferCnt[USB_OTG_MAX_TX_FIFOS]; + __IO HC_STATUS HC_Status[USB_OTG_MAX_TX_FIFOS]; + __IO URB_STATE URB_State[USB_OTG_MAX_TX_FIFOS]; + USB_OTG_HC hc [USB_OTG_MAX_TX_FIFOS]; + uint16_t channel [USB_OTG_MAX_TX_FIFOS]; +// USB_OTG_hPort_TypeDef *port_cb; +} +HCD_DEV , *USB_OTG_USBH_PDEV; + + +typedef struct _OTG +{ + uint8_t OTG_State; + uint8_t OTG_PrevState; + uint8_t OTG_Mode; +} +OTG_DEV , *USB_OTG_USBO_PDEV; + +typedef struct USB_OTG_handle +{ + USB_OTG_CORE_CFGS cfg; + USB_OTG_CORE_REGS regs; +#ifdef USE_DEVICE_MODE + DCD_DEV dev; +#endif +#ifdef USE_HOST_MODE + HCD_DEV host; +#endif +#ifdef USE_OTG_MODE + OTG_DEV otg; +#endif +} +USB_OTG_CORE_HANDLE , *PUSB_OTG_CORE_HANDLE; + +/** + * @} + */ + + +/** @defgroup USB_CORE_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USB_CORE_Exported_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup USB_CORE_Exported_FunctionsPrototype + * @{ + */ + + +USB_OTG_STS USB_OTG_CoreInit (USB_OTG_CORE_HANDLE *pdev); +USB_OTG_STS USB_OTG_SelectCore (USB_OTG_CORE_HANDLE *pdev, + USB_OTG_CORE_ID_TypeDef coreID); +USB_OTG_STS USB_OTG_EnableGlobalInt (USB_OTG_CORE_HANDLE *pdev); +USB_OTG_STS USB_OTG_DisableGlobalInt(USB_OTG_CORE_HANDLE *pdev); +void* USB_OTG_ReadPacket (USB_OTG_CORE_HANDLE *pdev , + uint8_t *dest, + uint16_t len); +USB_OTG_STS USB_OTG_WritePacket (USB_OTG_CORE_HANDLE *pdev , + uint8_t *src, + uint8_t ch_ep_num, + uint16_t len); +USB_OTG_STS USB_OTG_FlushTxFifo (USB_OTG_CORE_HANDLE *pdev , uint32_t num); +USB_OTG_STS USB_OTG_FlushRxFifo (USB_OTG_CORE_HANDLE *pdev); + +uint32_t USB_OTG_ReadCoreItr (USB_OTG_CORE_HANDLE *pdev); +uint32_t USB_OTG_ReadOtgItr (USB_OTG_CORE_HANDLE *pdev); +uint8_t USB_OTG_IsHostMode (USB_OTG_CORE_HANDLE *pdev); +uint8_t USB_OTG_IsDeviceMode (USB_OTG_CORE_HANDLE *pdev); +uint32_t USB_OTG_GetMode (USB_OTG_CORE_HANDLE *pdev); +USB_OTG_STS USB_OTG_PhyInit (USB_OTG_CORE_HANDLE *pdev); +USB_OTG_STS USB_OTG_SetCurrentMode (USB_OTG_CORE_HANDLE *pdev, + uint8_t mode); + +/*********************** HOST APIs ********************************************/ +#ifdef USE_HOST_MODE +USB_OTG_STS USB_OTG_CoreInitHost (USB_OTG_CORE_HANDLE *pdev); +USB_OTG_STS USB_OTG_EnableHostInt (USB_OTG_CORE_HANDLE *pdev); +USB_OTG_STS USB_OTG_HC_Init (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num); +USB_OTG_STS USB_OTG_HC_Halt (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num); +USB_OTG_STS USB_OTG_HC_StartXfer (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num); +USB_OTG_STS USB_OTG_HC_DoPing (USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num); +uint32_t USB_OTG_ReadHostAllChannels_intr (USB_OTG_CORE_HANDLE *pdev); +uint32_t USB_OTG_ResetPort (USB_OTG_CORE_HANDLE *pdev); +uint32_t USB_OTG_ReadHPRT0 (USB_OTG_CORE_HANDLE *pdev); +void USB_OTG_DriveVbus (USB_OTG_CORE_HANDLE *pdev, uint8_t state); +void USB_OTG_InitFSLSPClkSel (USB_OTG_CORE_HANDLE *pdev ,uint8_t freq); +uint8_t USB_OTG_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev) ; +void USB_OTG_StopHost (USB_OTG_CORE_HANDLE *pdev); +#endif +/********************* DEVICE APIs ********************************************/ +#ifdef USE_DEVICE_MODE +USB_OTG_STS USB_OTG_CoreInitDev (USB_OTG_CORE_HANDLE *pdev); +USB_OTG_STS USB_OTG_EnableDevInt (USB_OTG_CORE_HANDLE *pdev); +uint32_t USB_OTG_ReadDevAllInEPItr (USB_OTG_CORE_HANDLE *pdev); +enum USB_OTG_SPEED USB_OTG_GetDeviceSpeed (USB_OTG_CORE_HANDLE *pdev); +USB_OTG_STS USB_OTG_EP0Activate (USB_OTG_CORE_HANDLE *pdev); +USB_OTG_STS USB_OTG_EPActivate (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); +USB_OTG_STS USB_OTG_EPDeactivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); +USB_OTG_STS USB_OTG_EPStartXfer (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); +USB_OTG_STS USB_OTG_EP0StartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); +USB_OTG_STS USB_OTG_EPSetStall (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); +USB_OTG_STS USB_OTG_EPClearStall (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); +uint32_t USB_OTG_ReadDevAllOutEp_itr (USB_OTG_CORE_HANDLE *pdev); +uint32_t USB_OTG_ReadDevOutEP_itr (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); +uint32_t USB_OTG_ReadDevAllInEPItr (USB_OTG_CORE_HANDLE *pdev); +void USB_OTG_InitDevSpeed (USB_OTG_CORE_HANDLE *pdev , uint8_t speed); +uint8_t USBH_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev); +void USB_OTG_EP0_OutStart(USB_OTG_CORE_HANDLE *pdev); +void USB_OTG_ActiveRemoteWakeup(USB_OTG_CORE_HANDLE *pdev); +void USB_OTG_UngateClock(USB_OTG_CORE_HANDLE *pdev); +void USB_OTG_StopDevice(USB_OTG_CORE_HANDLE *pdev); +void USB_OTG_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep , uint32_t Status); +uint32_t USB_OTG_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,USB_OTG_EP *ep); +#endif +/** + * @} + */ + +#endif /* __USB_CORE_H__ */ + + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/bootloader/include/usb_dcd.h b/radio/bootloader/include/usb_dcd.h new file mode 100644 index 000000000..17e7f18ed --- /dev/null +++ b/radio/bootloader/include/usb_dcd.h @@ -0,0 +1,163 @@ +/** + ****************************************************************************** + * @file usb_dcd.h + * @author MCD Application Team + * @version V2.1.0 + * @date 19-March-2012 + * @brief Peripheral Driver Header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __DCD_H__ +#define __DCD_H__ + +/* Includes ------------------------------------------------------------------*/ +#include "usb_core.h" + +/** @addtogroup USB_OTG_DRIVER +* @{ +*/ + +/** @defgroup USB_DCD +* @brief This file is the +* @{ +*/ + + +/** @defgroup USB_DCD_Exported_Defines +* @{ +*/ +#define USB_OTG_EP_CONTROL 0 +#define USB_OTG_EP_ISOC 1 +#define USB_OTG_EP_BULK 2 +#define USB_OTG_EP_INT 3 +#define USB_OTG_EP_MASK 3 + +/* Device Status */ +#define USB_OTG_DEFAULT 1 +#define USB_OTG_ADDRESSED 2 +#define USB_OTG_CONFIGURED 3 +#define USB_OTG_SUSPENDED 4 + +/** +* @} +*/ + + +/** @defgroup USB_DCD_Exported_Types +* @{ +*/ +/******************************************************************************** +Data structure type +********************************************************************************/ +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint16_t wMaxPacketSize; + uint8_t bInterval; +} +EP_DESCRIPTOR , *PEP_DESCRIPTOR; + +/** +* @} +*/ + + +/** @defgroup USB_DCD_Exported_Macros +* @{ +*/ +/** +* @} +*/ + +/** @defgroup USB_DCD_Exported_Variables +* @{ +*/ +/** +* @} +*/ + +/** @defgroup USB_DCD_Exported_FunctionsPrototype +* @{ +*/ +/******************************************************************************** +EXPORTED FUNCTION FROM THE USB-OTG LAYER +********************************************************************************/ +void DCD_Init(USB_OTG_CORE_HANDLE *pdev , + USB_OTG_CORE_ID_TypeDef coreID); + +void DCD_DevConnect (USB_OTG_CORE_HANDLE *pdev); +void DCD_DevDisconnect (USB_OTG_CORE_HANDLE *pdev); +void DCD_EP_SetAddress (USB_OTG_CORE_HANDLE *pdev, + uint8_t address); +uint32_t DCD_EP_Open(USB_OTG_CORE_HANDLE *pdev , + uint8_t ep_addr, + uint16_t ep_mps, + uint8_t ep_type); + +uint32_t DCD_EP_Close (USB_OTG_CORE_HANDLE *pdev, + uint8_t ep_addr); + + +uint32_t DCD_EP_PrepareRx ( USB_OTG_CORE_HANDLE *pdev, + uint8_t ep_addr, + uint8_t *pbuf, + uint16_t buf_len); + +uint32_t DCD_EP_Tx (USB_OTG_CORE_HANDLE *pdev, + uint8_t ep_addr, + uint8_t *pbuf, + uint32_t buf_len); +uint32_t DCD_EP_Stall (USB_OTG_CORE_HANDLE *pdev, + uint8_t epnum); +uint32_t DCD_EP_ClrStall (USB_OTG_CORE_HANDLE *pdev, + uint8_t epnum); +uint32_t DCD_EP_Flush (USB_OTG_CORE_HANDLE *pdev, + uint8_t epnum); +uint32_t DCD_Handle_ISR(USB_OTG_CORE_HANDLE *pdev); + +uint32_t DCD_GetEPStatus(USB_OTG_CORE_HANDLE *pdev , + uint8_t epnum); + +void DCD_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , + uint8_t epnum , + uint32_t Status); + +/** +* @} +*/ + + +#endif //__DCD_H__ + + +/** +* @} +*/ + +/** +* @} +*/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/bootloader/include/usb_dcd_int.h b/radio/bootloader/include/usb_dcd_int.h new file mode 100644 index 000000000..69e525a26 --- /dev/null +++ b/radio/bootloader/include/usb_dcd_int.h @@ -0,0 +1,127 @@ +/** + ****************************************************************************** + * @file usb_dcd_int.h + * @author MCD Application Team + * @version V2.1.0 + * @date 19-March-2012 + * @brief Peripheral Device Interface Layer + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef USB_DCD_INT_H__ +#define USB_DCD_INT_H__ + +/* Includes ------------------------------------------------------------------*/ +#include "usb_dcd.h" + + + +/** @addtogroup USB_OTG_DRIVER + * @{ + */ + +/** @defgroup USB_DCD_INT + * @brief This file is the + * @{ + */ + + +/** @defgroup USB_DCD_INT_Exported_Defines + * @{ + */ + +typedef struct _USBD_DCD_INT +{ + uint8_t (* DataOutStage) (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); + uint8_t (* DataInStage) (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); + uint8_t (* SetupStage) (USB_OTG_CORE_HANDLE *pdev); + uint8_t (* SOF) (USB_OTG_CORE_HANDLE *pdev); + uint8_t (* Reset) (USB_OTG_CORE_HANDLE *pdev); + uint8_t (* Suspend) (USB_OTG_CORE_HANDLE *pdev); + uint8_t (* Resume) (USB_OTG_CORE_HANDLE *pdev); + uint8_t (* IsoINIncomplete) (USB_OTG_CORE_HANDLE *pdev); + uint8_t (* IsoOUTIncomplete) (USB_OTG_CORE_HANDLE *pdev); + + uint8_t (* DevConnected) (USB_OTG_CORE_HANDLE *pdev); + uint8_t (* DevDisconnected) (USB_OTG_CORE_HANDLE *pdev); + +}USBD_DCD_INT_cb_TypeDef; + +extern USBD_DCD_INT_cb_TypeDef *USBD_DCD_INT_fops; +/** + * @} + */ + + +/** @defgroup USB_DCD_INT_Exported_Types + * @{ + */ +/** + * @} + */ + +/** @defgroup USB_DCD_INT_Exported_Macros + * @{ + */ + +#define CLEAR_IN_EP_INTR(epnum,intr) \ + diepint.d32=0; \ + diepint.b.intr = 1; \ + USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[epnum]->DIEPINT,diepint.d32); + +#define CLEAR_OUT_EP_INTR(epnum,intr) \ + doepint.d32=0; \ + doepint.b.intr = 1; \ + USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[epnum]->DOEPINT,doepint.d32); + +/** + * @} + */ + +/** @defgroup USB_DCD_INT_Exported_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup USB_DCD_INT_Exported_FunctionsPrototype + * @{ + */ + +uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev); + +/** + * @} + */ + + +#endif // USB_DCD_INT_H__ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/bootloader/include/usb_defines.h b/radio/bootloader/include/usb_defines.h new file mode 100644 index 000000000..93c1bb010 --- /dev/null +++ b/radio/bootloader/include/usb_defines.h @@ -0,0 +1,249 @@ +/** + ****************************************************************************** + * @file usb_defines.h + * @author MCD Application Team + * @version V2.1.0 + * @date 19-March-2012 + * @brief Header of the Core Layer + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_DEF_H__ +#define __USB_DEF_H__ + +/* Includes ------------------------------------------------------------------*/ +#include "usb_conf.h" + +/** @addtogroup USB_OTG_DRIVER + * @{ + */ + +/** @defgroup USB_DEFINES + * @brief This file is the + * @{ + */ + + +/** @defgroup USB_DEFINES_Exported_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup _CORE_DEFINES_ + * @{ + */ + +#define USB_OTG_SPEED_PARAM_HIGH 0 +#define USB_OTG_SPEED_PARAM_HIGH_IN_FULL 1 +#define USB_OTG_SPEED_PARAM_FULL 3 + +#define USB_OTG_SPEED_HIGH 0 +#define USB_OTG_SPEED_FULL 1 + +#define USB_OTG_ULPI_PHY 1 +#define USB_OTG_EMBEDDED_PHY 2 + +/** + * @} + */ + + +/** @defgroup _GLOBAL_DEFINES_ + * @{ + */ +#define GAHBCFG_TXFEMPTYLVL_EMPTY 1 +#define GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 +#define GAHBCFG_GLBINT_ENABLE 1 +#define GAHBCFG_INT_DMA_BURST_SINGLE 0 +#define GAHBCFG_INT_DMA_BURST_INCR 1 +#define GAHBCFG_INT_DMA_BURST_INCR4 3 +#define GAHBCFG_INT_DMA_BURST_INCR8 5 +#define GAHBCFG_INT_DMA_BURST_INCR16 7 +#define GAHBCFG_DMAENABLE 1 +#define GAHBCFG_TXFEMPTYLVL_EMPTY 1 +#define GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 +#define GRXSTS_PKTSTS_IN 2 +#define GRXSTS_PKTSTS_IN_XFER_COMP 3 +#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5 +#define GRXSTS_PKTSTS_CH_HALTED 7 +/** + * @} + */ + + +/** @defgroup _OnTheGo_DEFINES_ + * @{ + */ +#define MODE_HNP_SRP_CAPABLE 0 +#define MODE_SRP_ONLY_CAPABLE 1 +#define MODE_NO_HNP_SRP_CAPABLE 2 +#define MODE_SRP_CAPABLE_DEVICE 3 +#define MODE_NO_SRP_CAPABLE_DEVICE 4 +#define MODE_SRP_CAPABLE_HOST 5 +#define MODE_NO_SRP_CAPABLE_HOST 6 +#define A_HOST 1 +#define A_SUSPEND 2 +#define A_PERIPHERAL 3 +#define B_PERIPHERAL 4 +#define B_HOST 5 +#define DEVICE_MODE 0 +#define HOST_MODE 1 +#define OTG_MODE 2 +/** + * @} + */ + + +/** @defgroup __DEVICE_DEFINES_ + * @{ + */ +#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 +#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 +#define DSTS_ENUMSPD_LS_PHY_6MHZ 2 +#define DSTS_ENUMSPD_FS_PHY_48MHZ 3 + +#define DCFG_FRAME_INTERVAL_80 0 +#define DCFG_FRAME_INTERVAL_85 1 +#define DCFG_FRAME_INTERVAL_90 2 +#define DCFG_FRAME_INTERVAL_95 3 + +#define DEP0CTL_MPS_64 0 +#define DEP0CTL_MPS_32 1 +#define DEP0CTL_MPS_16 2 +#define DEP0CTL_MPS_8 3 + +#define EP_SPEED_LOW 0 +#define EP_SPEED_FULL 1 +#define EP_SPEED_HIGH 2 + +#define EP_TYPE_CTRL 0 +#define EP_TYPE_ISOC 1 +#define EP_TYPE_BULK 2 +#define EP_TYPE_INTR 3 +#define EP_TYPE_MSK 3 + +#define STS_GOUT_NAK 1 +#define STS_DATA_UPDT 2 +#define STS_XFER_COMP 3 +#define STS_SETUP_COMP 4 +#define STS_SETUP_UPDT 6 +/** + * @} + */ + + +/** @defgroup __HOST_DEFINES_ + * @{ + */ +#define HC_PID_DATA0 0 +#define HC_PID_DATA2 1 +#define HC_PID_DATA1 2 +#define HC_PID_SETUP 3 + +#define HPRT0_PRTSPD_HIGH_SPEED 0 +#define HPRT0_PRTSPD_FULL_SPEED 1 +#define HPRT0_PRTSPD_LOW_SPEED 2 + +#define HCFG_30_60_MHZ 0 +#define HCFG_48_MHZ 1 +#define HCFG_6_MHZ 2 + +#define HCCHAR_CTRL 0 +#define HCCHAR_ISOC 1 +#define HCCHAR_BULK 2 +#define HCCHAR_INTR 3 + +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) + +/** + * @} + */ + + +/** @defgroup USB_DEFINES_Exported_Types + * @{ + */ + +typedef enum +{ + USB_OTG_HS_CORE_ID = 0, + USB_OTG_FS_CORE_ID = 1 +}USB_OTG_CORE_ID_TypeDef; +/** + * @} + */ + + +/** @defgroup USB_DEFINES_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USB_DEFINES_Exported_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup USB_DEFINES_Exported_FunctionsPrototype + * @{ + */ +/** + * @} + */ + + +/** @defgroup Internal_Macro's + * @{ + */ +#define USB_OTG_READ_REG32(reg) (*(__IO uint32_t *)reg) +#define USB_OTG_WRITE_REG32(reg,value) (*(__IO uint32_t *)reg = value) +#define USB_OTG_MODIFY_REG32(reg,clear_mask,set_mask) \ + USB_OTG_WRITE_REG32(reg, (((USB_OTG_READ_REG32(reg)) & ~clear_mask) | set_mask ) ) + +/******************************************************************************** + ENUMERATION TYPE +********************************************************************************/ +enum USB_OTG_SPEED { + USB_SPEED_UNKNOWN = 0, + USB_SPEED_LOW, + USB_SPEED_FULL, + USB_SPEED_HIGH +}; + +#endif //__USB_DEFINES__H__ + + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/bootloader/include/usb_regs.h b/radio/bootloader/include/usb_regs.h new file mode 100644 index 000000000..7befb51d2 --- /dev/null +++ b/radio/bootloader/include/usb_regs.h @@ -0,0 +1,1188 @@ +/** + ****************************************************************************** + * @file usb_regs.h + * @author MCD Application Team + * @version V2.1.0 + * @date 19-March-2012 + * @brief hardware registers + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_OTG_REGS_H__ +#define __USB_OTG_REGS_H__ + +/* Includes ------------------------------------------------------------------*/ +#include "usb_conf.h" + + +/** @addtogroup USB_OTG_DRIVER + * @{ + */ + +/** @defgroup USB_REGS + * @brief This file is the + * @{ + */ + + +/** @defgroup USB_REGS_Exported_Defines + * @{ + */ + +#define USB_OTG_HS_BASE_ADDR 0x40040000 +#define USB_OTG_FS_BASE_ADDR 0x50000000 + +#define USB_OTG_CORE_GLOBAL_REGS_OFFSET 0x000 +#define USB_OTG_DEV_GLOBAL_REG_OFFSET 0x800 +#define USB_OTG_DEV_IN_EP_REG_OFFSET 0x900 +#define USB_OTG_EP_REG_OFFSET 0x20 +#define USB_OTG_DEV_OUT_EP_REG_OFFSET 0xB00 +#define USB_OTG_HOST_GLOBAL_REG_OFFSET 0x400 +#define USB_OTG_HOST_PORT_REGS_OFFSET 0x440 +#define USB_OTG_HOST_CHAN_REGS_OFFSET 0x500 +#define USB_OTG_CHAN_REGS_OFFSET 0x20 +#define USB_OTG_PCGCCTL_OFFSET 0xE00 +#define USB_OTG_DATA_FIFO_OFFSET 0x1000 +#define USB_OTG_DATA_FIFO_SIZE 0x1000 + + +#define USB_OTG_MAX_TX_FIFOS 15 + +#define USB_OTG_HS_MAX_PACKET_SIZE 512 +#define USB_OTG_FS_MAX_PACKET_SIZE 64 +#define USB_OTG_MAX_EP0_SIZE 64 +/** + * @} + */ + +/** @defgroup USB_REGS_Exported_Types + * @{ + */ + +/** @defgroup __USB_OTG_Core_register + * @{ + */ +typedef struct _USB_OTG_GREGS //000h +{ + __IO uint32_t GOTGCTL; /* USB_OTG Control and Status Register 000h*/ + __IO uint32_t GOTGINT; /* USB_OTG Interrupt Register 004h*/ + __IO uint32_t GAHBCFG; /* Core AHB Configuration Register 008h*/ + __IO uint32_t GUSBCFG; /* Core USB Configuration Register 00Ch*/ + __IO uint32_t GRSTCTL; /* Core Reset Register 010h*/ + __IO uint32_t GINTSTS; /* Core Interrupt Register 014h*/ + __IO uint32_t GINTMSK; /* Core Interrupt Mask Register 018h*/ + __IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch*/ + __IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h*/ + __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /* EP0 / Non Periodic Tx FIFO Size Register 028h*/ + __IO uint32_t HNPTXSTS; /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/ + uint32_t Reserved30[2]; /* Reserved 030h*/ + __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/ + __IO uint32_t CID; /* User ID Register 03Ch*/ + uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/ + __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/ + __IO uint32_t DIEPTXF[USB_OTG_MAX_TX_FIFOS];/* dev Periodic Transmit FIFO */ +} +USB_OTG_GREGS; +/** + * @} + */ + + +/** @defgroup __device_Registers + * @{ + */ +typedef struct _USB_OTG_DREGS // 800h +{ + __IO uint32_t DCFG; /* dev Configuration Register 800h*/ + __IO uint32_t DCTL; /* dev Control Register 804h*/ + __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/ + uint32_t Reserved0C; /* Reserved 80Ch*/ + __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/ + __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/ + __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/ + __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/ + uint32_t Reserved20; /* Reserved 820h*/ + uint32_t Reserved9; /* Reserved 824h*/ + __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/ + __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/ + __IO uint32_t DTHRCTL; /* dev thr 830h*/ + __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ + __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/ + __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/ + uint32_t Reserved40; /* dedicated EP mask 840h*/ + __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ + uint32_t Reserved44[15]; /* Reserved 844-87Ch*/ + __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ +} +USB_OTG_DREGS; +/** + * @} + */ + + +/** @defgroup __IN_Endpoint-Specific_Register + * @{ + */ +typedef struct _USB_OTG_INEPREGS +{ + __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ + uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/ + __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ + uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/ + __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ + __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/ + __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ + uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ +} +USB_OTG_INEPREGS; +/** + * @} + */ + + +/** @defgroup __OUT_Endpoint-Specific_Registers + * @{ + */ +typedef struct _USB_OTG_OUTEPREGS +{ + __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ + uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ + __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ + uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ + __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ + __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ + uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ +} +USB_OTG_OUTEPREGS; +/** + * @} + */ + + +/** @defgroup __Host_Mode_Register_Structures + * @{ + */ +typedef struct _USB_OTG_HREGS +{ + __IO uint32_t HCFG; /* Host Configuration Register 400h*/ + __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ + __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ + uint32_t Reserved40C; /* Reserved 40Ch*/ + __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ + __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ + __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ +} +USB_OTG_HREGS; +/** + * @} + */ + + +/** @defgroup __Host_Channel_Specific_Registers + * @{ + */ +typedef struct _USB_OTG_HC_REGS +{ + __IO uint32_t HCCHAR; + __IO uint32_t HCSPLT; + __IO uint32_t HCINT; + __IO uint32_t HCINTMSK; + __IO uint32_t HCTSIZ; + __IO uint32_t HCDMA; + uint32_t Reserved[2]; +} +USB_OTG_HC_REGS; +/** + * @} + */ + + +/** @defgroup __otg_Core_registers + * @{ + */ +typedef struct USB_OTG_core_regs //000h +{ + USB_OTG_GREGS *GREGS; + USB_OTG_DREGS *DREGS; + USB_OTG_HREGS *HREGS; + USB_OTG_INEPREGS *INEP_REGS[USB_OTG_MAX_TX_FIFOS]; + USB_OTG_OUTEPREGS *OUTEP_REGS[USB_OTG_MAX_TX_FIFOS]; + USB_OTG_HC_REGS *HC_REGS[USB_OTG_MAX_TX_FIFOS]; + __IO uint32_t *HPRT0; + __IO uint32_t *DFIFO[USB_OTG_MAX_TX_FIFOS]; + __IO uint32_t *PCGCCTL; +} +USB_OTG_CORE_REGS , *PUSB_OTG_CORE_REGS; +typedef union _USB_OTG_GOTGCTL_TypeDef +{ + uint32_t d32; + struct + { +uint32_t sesreqscs : + 1; +uint32_t sesreq : + 1; +uint32_t Reserved2_7 : + 6; +uint32_t hstnegscs : + 1; +uint32_t hnpreq : + 1; +uint32_t hstsethnpen : + 1; +uint32_t devhnpen : + 1; +uint32_t Reserved12_15 : + 4; +uint32_t conidsts : + 1; +uint32_t dbct : + 1; +uint32_t asesvld : + 1; +uint32_t bsesvld : + 1; +uint32_t Reserved20_31 : + 12; + } + b; +} USB_OTG_GOTGCTL_TypeDef ; + +typedef union _USB_OTG_GOTGINT_TypeDef +{ + uint32_t d32; + struct + { +uint32_t Reserved0_1 : + 2; +uint32_t sesenddet : + 1; +uint32_t Reserved3_7 : + 5; +uint32_t sesreqsucstschng : + 1; +uint32_t hstnegsucstschng : + 1; +uint32_t reserver10_16 : + 7; +uint32_t hstnegdet : + 1; +uint32_t adevtoutchng : + 1; +uint32_t debdone : + 1; +uint32_t Reserved31_20 : + 12; + } + b; +} USB_OTG_GOTGINT_TypeDef ; +typedef union _USB_OTG_GAHBCFG_TypeDef +{ + uint32_t d32; + struct + { +uint32_t glblintrmsk : + 1; +uint32_t hburstlen : + 4; +uint32_t dmaenable : + 1; +uint32_t Reserved : + 1; +uint32_t nptxfemplvl_txfemplvl : + 1; +uint32_t ptxfemplvl : + 1; +uint32_t Reserved9_31 : + 23; + } + b; +} USB_OTG_GAHBCFG_TypeDef ; +typedef union _USB_OTG_GUSBCFG_TypeDef +{ + uint32_t d32; + struct + { +uint32_t toutcal : + 3; +uint32_t Reserved3_5 : + 3; +uint32_t physel : + 1; +uint32_t Reserved7 : + 1; +uint32_t srpcap : + 1; +uint32_t hnpcap : + 1; +uint32_t usbtrdtim : + 4; +uint32_t Reserved14 : + 1; +uint32_t phylpwrclksel : + 1; +uint32_t Reserved16 : + 1; +uint32_t ulpi_fsls : + 1; +uint32_t ulpi_auto_res : + 1; +uint32_t ulpi_clk_sus_m : + 1; +uint32_t ulpi_ext_vbus_drv : + 1; +uint32_t ulpi_int_vbus_ind : + 1; +uint32_t term_sel_dl_pulse : + 1; +uint32_t ulpi_ind_cpl : + 1; +uint32_t ulpi_passthrough : + 1; +uint32_t ulpi_protect_disable : + 1; +uint32_t Reserved26_28 : + 3; +uint32_t force_host : + 1; +uint32_t force_dev : + 1; +uint32_t corrupt_tx : + 1; + } + b; +} USB_OTG_GUSBCFG_TypeDef ; +typedef union _USB_OTG_GRSTCTL_TypeDef +{ + uint32_t d32; + struct + { +uint32_t csftrst : + 1; +uint32_t hsftrst : + 1; +uint32_t hstfrm : + 1; +uint32_t Reserved3 : + 1; +uint32_t rxfflsh : + 1; +uint32_t txfflsh : + 1; +uint32_t txfnum : + 5; +uint32_t Reserved11_29 : + 19; +uint32_t dmareq : + 1; +uint32_t ahbidle : + 1; + } + b; +} USB_OTG_GRSTCTL_TypeDef ; +typedef union _USB_OTG_GINTMSK_TypeDef +{ + uint32_t d32; + struct + { +uint32_t Reserved0 : + 1; +uint32_t modemismatch : + 1; +uint32_t otgintr : + 1; +uint32_t sofintr : + 1; +uint32_t rxstsqlvl : + 1; +uint32_t nptxfempty : + 1; +uint32_t ginnakeff : + 1; +uint32_t goutnakeff : + 1; +uint32_t Reserved8_9 : + 2; +uint32_t erlysuspend : + 1; +uint32_t usbsuspend : + 1; +uint32_t usbreset : + 1; +uint32_t enumdone : + 1; +uint32_t isooutdrop : + 1; +uint32_t eopframe : + 1; +uint32_t Reserved16 : + 1; +uint32_t epmismatch : + 1; +uint32_t inepintr : + 1; +uint32_t outepintr : + 1; +uint32_t incomplisoin : + 1; +uint32_t incomplisoout : + 1; +uint32_t Reserved22_23 : + 2; +uint32_t portintr : + 1; +uint32_t hcintr : + 1; +uint32_t ptxfempty : + 1; +uint32_t Reserved27 : + 1; +uint32_t conidstschng : + 1; +uint32_t disconnect : + 1; +uint32_t sessreqintr : + 1; +uint32_t wkupintr : + 1; + } + b; +} USB_OTG_GINTMSK_TypeDef ; +typedef union _USB_OTG_GINTSTS_TypeDef +{ + uint32_t d32; + struct + { +uint32_t curmode : + 1; +uint32_t modemismatch : + 1; +uint32_t otgintr : + 1; +uint32_t sofintr : + 1; +uint32_t rxstsqlvl : + 1; +uint32_t nptxfempty : + 1; +uint32_t ginnakeff : + 1; +uint32_t goutnakeff : + 1; +uint32_t Reserved8_9 : + 2; +uint32_t erlysuspend : + 1; +uint32_t usbsuspend : + 1; +uint32_t usbreset : + 1; +uint32_t enumdone : + 1; +uint32_t isooutdrop : + 1; +uint32_t eopframe : + 1; +uint32_t Reserved16_17 : + 2; +uint32_t inepint: + 1; +uint32_t outepintr : + 1; +uint32_t incomplisoin : + 1; +uint32_t incomplisoout : + 1; +uint32_t Reserved22_23 : + 2; +uint32_t portintr : + 1; +uint32_t hcintr : + 1; +uint32_t ptxfempty : + 1; +uint32_t Reserved27 : + 1; +uint32_t conidstschng : + 1; +uint32_t disconnect : + 1; +uint32_t sessreqintr : + 1; +uint32_t wkupintr : + 1; + } + b; +} USB_OTG_GINTSTS_TypeDef ; +typedef union _USB_OTG_DRXSTS_TypeDef +{ + uint32_t d32; + struct + { +uint32_t epnum : + 4; +uint32_t bcnt : + 11; +uint32_t dpid : + 2; +uint32_t pktsts : + 4; +uint32_t fn : + 4; +uint32_t Reserved : + 7; + } + b; +} USB_OTG_DRXSTS_TypeDef ; +typedef union _USB_OTG_GRXSTS_TypeDef +{ + uint32_t d32; + struct + { +uint32_t chnum : + 4; +uint32_t bcnt : + 11; +uint32_t dpid : + 2; +uint32_t pktsts : + 4; +uint32_t Reserved : + 11; + } + b; +} USB_OTG_GRXFSTS_TypeDef ; +typedef union _USB_OTG_FSIZ_TypeDef +{ + uint32_t d32; + struct + { +uint32_t startaddr : + 16; +uint32_t depth : + 16; + } + b; +} USB_OTG_FSIZ_TypeDef ; +typedef union _USB_OTG_HNPTXSTS_TypeDef +{ + uint32_t d32; + struct + { + uint32_t nptxfspcavail : + 16; + uint32_t nptxqspcavail : + 8; + struct + { + uint32_t terminate : + 1; + uint32_t token : + 2; + uint32_t chnum : + 4; + } nptxqtop; + uint32_t Reserved : + 1; + } + b; +} USB_OTG_HNPTXSTS_TypeDef ; +typedef union _USB_OTG_DTXFSTSn_TypeDef +{ + uint32_t d32; + struct + { +uint32_t txfspcavail : + 16; +uint32_t Reserved : + 16; + } + b; +} USB_OTG_DTXFSTSn_TypeDef ; + +typedef union _USB_OTG_GCCFG_TypeDef +{ + uint32_t d32; + struct + { +uint32_t Reserved_in : + 16; +uint32_t pwdn : + 1; +uint32_t Reserved_17 : + 1; +uint32_t vbussensingA : + 1; +uint32_t vbussensingB : + 1; +uint32_t sofouten : + 1; +uint32_t disablevbussensing : + 1; +uint32_t Reserved_out : + 10; + } + b; +} USB_OTG_GCCFG_TypeDef ; + +typedef union _USB_OTG_DCFG_TypeDef +{ + uint32_t d32; + struct + { +uint32_t devspd : + 2; +uint32_t nzstsouthshk : + 1; +uint32_t Reserved3 : + 1; +uint32_t devaddr : + 7; +uint32_t perfrint : + 2; +uint32_t Reserved12_31 : + 19; + } + b; +} USB_OTG_DCFG_TypeDef ; +typedef union _USB_OTG_DCTL_TypeDef +{ + uint32_t d32; + struct + { +uint32_t rmtwkupsig : + 1; +uint32_t sftdiscon : + 1; +uint32_t gnpinnaksts : + 1; +uint32_t goutnaksts : + 1; +uint32_t tstctl : + 3; +uint32_t sgnpinnak : + 1; +uint32_t cgnpinnak : + 1; +uint32_t sgoutnak : + 1; +uint32_t cgoutnak : + 1; +uint32_t poprg_done : + 1; +uint32_t Reserved : + 20; + } + b; +} USB_OTG_DCTL_TypeDef ; +typedef union _USB_OTG_DSTS_TypeDef +{ + uint32_t d32; + struct + { +uint32_t suspsts : + 1; +uint32_t enumspd : + 2; +uint32_t errticerr : + 1; +uint32_t Reserved4_7: + 4; +uint32_t soffn : + 14; +uint32_t Reserved22_31 : + 10; + } + b; +} USB_OTG_DSTS_TypeDef ; +typedef union _USB_OTG_DIEPINTn_TypeDef +{ + uint32_t d32; + struct + { +uint32_t xfercompl : + 1; +uint32_t epdisabled : + 1; +uint32_t Reserved2 : + 1; +uint32_t timeout : + 1; +uint32_t intktxfemp : + 1; +uint32_t Reserved5 : + 1; +uint32_t inepnakeff : + 1; +uint32_t emptyintr : + 1; +uint32_t txfifoundrn : + 1; +uint32_t Reserved14_31 : + 23; + } + b; +} USB_OTG_DIEPINTn_TypeDef ; +typedef union _USB_OTG_DIEPINTn_TypeDef USB_OTG_DIEPMSK_TypeDef ; +typedef union _USB_OTG_DOEPINTn_TypeDef +{ + uint32_t d32; + struct + { +uint32_t xfercompl : + 1; +uint32_t epdisabled : + 1; +uint32_t Reserved2 : + 1; +uint32_t setup : + 1; +uint32_t Reserved04_31 : + 28; + } + b; +} USB_OTG_DOEPINTn_TypeDef ; +typedef union _USB_OTG_DOEPINTn_TypeDef USB_OTG_DOEPMSK_TypeDef ; + +typedef union _USB_OTG_DAINT_TypeDef +{ + uint32_t d32; + struct + { +uint32_t in : + 16; +uint32_t out : + 16; + } + ep; +} USB_OTG_DAINT_TypeDef ; + +typedef union _USB_OTG_DTHRCTL_TypeDef +{ + uint32_t d32; + struct + { +uint32_t non_iso_thr_en : + 1; +uint32_t iso_thr_en : + 1; +uint32_t tx_thr_len : + 9; +uint32_t Reserved11_15 : + 5; +uint32_t rx_thr_en : + 1; +uint32_t rx_thr_len : + 9; +uint32_t Reserved26 : + 1; +uint32_t arp_en : + 1; +uint32_t Reserved28_31 : + 4; + } + b; +} USB_OTG_DTHRCTL_TypeDef ; +typedef union _USB_OTG_DEPCTL_TypeDef +{ + uint32_t d32; + struct + { +uint32_t mps : + 11; +uint32_t reserved : + 4; +uint32_t usbactep : + 1; +uint32_t dpid : + 1; +uint32_t naksts : + 1; +uint32_t eptype : + 2; +uint32_t snp : + 1; +uint32_t stall : + 1; +uint32_t txfnum : + 4; +uint32_t cnak : + 1; +uint32_t snak : + 1; +uint32_t setd0pid : + 1; +uint32_t setd1pid : + 1; +uint32_t epdis : + 1; +uint32_t epena : + 1; + } + b; +} USB_OTG_DEPCTL_TypeDef ; +typedef union _USB_OTG_DEPXFRSIZ_TypeDef +{ + uint32_t d32; + struct + { +uint32_t xfersize : + 19; +uint32_t pktcnt : + 10; +uint32_t mc : + 2; +uint32_t Reserved : + 1; + } + b; +} USB_OTG_DEPXFRSIZ_TypeDef ; +typedef union _USB_OTG_DEP0XFRSIZ_TypeDef +{ + uint32_t d32; + struct + { +uint32_t xfersize : + 7; +uint32_t Reserved7_18 : + 12; +uint32_t pktcnt : + 2; +uint32_t Reserved20_28 : + 9; +uint32_t supcnt : + 2; + uint32_t Reserved31; + } + b; +} USB_OTG_DEP0XFRSIZ_TypeDef ; +typedef union _USB_OTG_HCFG_TypeDef +{ + uint32_t d32; + struct + { +uint32_t fslspclksel : + 2; +uint32_t fslssupp : + 1; + } + b; +} USB_OTG_HCFG_TypeDef ; +typedef union _USB_OTG_HFRMINTRVL_TypeDef +{ + uint32_t d32; + struct + { +uint32_t frint : + 16; +uint32_t Reserved : + 16; + } + b; +} USB_OTG_HFRMINTRVL_TypeDef ; + +typedef union _USB_OTG_HFNUM_TypeDef +{ + uint32_t d32; + struct + { +uint32_t frnum : + 16; +uint32_t frrem : + 16; + } + b; +} USB_OTG_HFNUM_TypeDef ; +typedef union _USB_OTG_HPTXSTS_TypeDef +{ + uint32_t d32; + struct + { +uint32_t ptxfspcavail : + 16; +uint32_t ptxqspcavail : + 8; + struct + { + uint32_t terminate : + 1; + uint32_t token : + 2; + uint32_t chnum : + 4; + uint32_t odd_even : + 1; + } ptxqtop; + } + b; +} USB_OTG_HPTXSTS_TypeDef ; +typedef union _USB_OTG_HPRT0_TypeDef +{ + uint32_t d32; + struct + { +uint32_t prtconnsts : + 1; +uint32_t prtconndet : + 1; +uint32_t prtena : + 1; +uint32_t prtenchng : + 1; +uint32_t prtovrcurract : + 1; +uint32_t prtovrcurrchng : + 1; +uint32_t prtres : + 1; +uint32_t prtsusp : + 1; +uint32_t prtrst : + 1; +uint32_t Reserved9 : + 1; +uint32_t prtlnsts : + 2; +uint32_t prtpwr : + 1; +uint32_t prttstctl : + 4; +uint32_t prtspd : + 2; +uint32_t Reserved19_31 : + 13; + } + b; +} USB_OTG_HPRT0_TypeDef ; +typedef union _USB_OTG_HAINT_TypeDef +{ + uint32_t d32; + struct + { +uint32_t chint : + 16; +uint32_t Reserved : + 16; + } + b; +} USB_OTG_HAINT_TypeDef ; +typedef union _USB_OTG_HAINTMSK_TypeDef +{ + uint32_t d32; + struct + { +uint32_t chint : + 16; +uint32_t Reserved : + 16; + } + b; +} USB_OTG_HAINTMSK_TypeDef ; +typedef union _USB_OTG_HCCHAR_TypeDef +{ + uint32_t d32; + struct + { +uint32_t mps : + 11; +uint32_t epnum : + 4; +uint32_t epdir : + 1; +uint32_t Reserved : + 1; +uint32_t lspddev : + 1; +uint32_t eptype : + 2; +uint32_t multicnt : + 2; +uint32_t devaddr : + 7; +uint32_t oddfrm : + 1; +uint32_t chdis : + 1; +uint32_t chen : + 1; + } + b; +} USB_OTG_HCCHAR_TypeDef ; +typedef union _USB_OTG_HCSPLT_TypeDef +{ + uint32_t d32; + struct + { +uint32_t prtaddr : + 7; +uint32_t hubaddr : + 7; +uint32_t xactpos : + 2; +uint32_t compsplt : + 1; +uint32_t Reserved : + 14; +uint32_t spltena : + 1; + } + b; +} USB_OTG_HCSPLT_TypeDef ; +typedef union _USB_OTG_HCINTn_TypeDef +{ + uint32_t d32; + struct + { +uint32_t xfercompl : + 1; +uint32_t chhltd : + 1; +uint32_t ahberr : + 1; +uint32_t stall : + 1; +uint32_t nak : + 1; +uint32_t ack : + 1; +uint32_t nyet : + 1; +uint32_t xacterr : + 1; +uint32_t bblerr : + 1; +uint32_t frmovrun : + 1; +uint32_t datatglerr : + 1; +uint32_t Reserved : + 21; + } + b; +} USB_OTG_HCINTn_TypeDef ; +typedef union _USB_OTG_HCTSIZn_TypeDef +{ + uint32_t d32; + struct + { +uint32_t xfersize : + 19; +uint32_t pktcnt : + 10; +uint32_t pid : + 2; +uint32_t dopng : + 1; + } + b; +} USB_OTG_HCTSIZn_TypeDef ; +typedef union _USB_OTG_HCINTMSK_TypeDef +{ + uint32_t d32; + struct + { +uint32_t xfercompl : + 1; +uint32_t chhltd : + 1; +uint32_t ahberr : + 1; +uint32_t stall : + 1; +uint32_t nak : + 1; +uint32_t ack : + 1; +uint32_t nyet : + 1; +uint32_t xacterr : + 1; +uint32_t bblerr : + 1; +uint32_t frmovrun : + 1; +uint32_t datatglerr : + 1; +uint32_t Reserved : + 21; + } + b; +} USB_OTG_HCINTMSK_TypeDef ; + +typedef union _USB_OTG_PCGCCTL_TypeDef +{ + uint32_t d32; + struct + { +uint32_t stoppclk : + 1; +uint32_t gatehclk : + 1; +uint32_t Reserved2_3 : + 2; +uint32_t phy_susp : + 1; +uint32_t Reserved5_31 : + 27; + } + b; +} USB_OTG_PCGCCTL_TypeDef ; + +/** + * @} + */ + + +/** @defgroup USB_REGS_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USB_REGS_Exported_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup USB_REGS_Exported_FunctionsPrototype + * @{ + */ +/** + * @} + */ + + +#endif //__USB_OTG_REGS_H__ + + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/bootloader/include/usbd_conf.h b/radio/bootloader/include/usbd_conf.h new file mode 100644 index 000000000..34e07e811 --- /dev/null +++ b/radio/bootloader/include/usbd_conf.h @@ -0,0 +1,54 @@ +/** + ****************************************************************************** + * @file usbd_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 19-March-2012 + * @brief USB Device configuration file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_CONF__H__ +#define __USBD_CONF__H__ + +/* Includes ------------------------------------------------------------------*/ +#include "usb_conf.h" + +#define USBD_CFG_MAX_NUM 1 +#define USBD_ITF_MAX_NUM 1 +#define USB_MAX_STR_DESC_SIZ 64 + +#define USBD_SELF_POWERED + +/* Class Layer Parameter */ + +#define MSC_IN_EP 0x81 +#define MSC_OUT_EP 0x01 +#define MSC_MAX_PACKET 64 + +#define MSC_MEDIA_PACKET 4096 + + +#endif //__USBD_CONF__H__ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/bootloader/include/usbd_core.h b/radio/bootloader/include/usbd_core.h new file mode 100644 index 000000000..1ba845c5a --- /dev/null +++ b/radio/bootloader/include/usbd_core.h @@ -0,0 +1,120 @@ +/** + ****************************************************************************** + * @file usbd_core.h + * @author MCD Application Team + * @version V1.1.0 + * @date 19-March-2012 + * @brief Header file for usbd_core.c + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_CORE_H +#define __USBD_CORE_H + +/* Includes ------------------------------------------------------------------*/ +#include "usb_dcd.h" +#include "usbd_def.h" +#include "usbd_conf.h" + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_CORE + * @brief This file is the Header file for usbd_core.c file + * @{ + */ + + +/** @defgroup USBD_CORE_Exported_Defines + * @{ + */ + +typedef enum { + USBD_OK = 0, + USBD_BUSY, + USBD_FAIL, +}USBD_Status; +/** + * @} + */ + + +/** @defgroup USBD_CORE_Exported_TypesDefinitions + * @{ + */ + + +/** + * @} + */ + + + +/** @defgroup USBD_CORE_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_FunctionsPrototype + * @{ + */ +void USBD_Init(USB_OTG_CORE_HANDLE *pdev, + USB_OTG_CORE_ID_TypeDef coreID, + USBD_DEVICE *pDevice, + USBD_Class_cb_TypeDef *class_cb, + USBD_Usr_cb_TypeDef *usr_cb); + +USBD_Status USBD_DeInit(USB_OTG_CORE_HANDLE *pdev); + +USBD_Status USBD_ClrCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx); + +USBD_Status USBD_SetCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx); + +/** + * @} + */ + +#endif /* __USBD_CORE_H */ + +/** + * @} + */ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + + + diff --git a/radio/bootloader/include/usbd_def.h b/radio/bootloader/include/usbd_def.h new file mode 100644 index 000000000..2aa132543 --- /dev/null +++ b/radio/bootloader/include/usbd_def.h @@ -0,0 +1,156 @@ +/** + ****************************************************************************** + * @file usbd_def.h + * @author MCD Application Team + * @version V1.1.0 + * @date 19-March-2012 + * @brief general defines for the usb device library + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ + +#ifndef __USBD_DEF_H +#define __USBD_DEF_H + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_conf.h" + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USB_DEF + * @brief general defines for the usb device library file + * @{ + */ + +/** @defgroup USB_DEF_Exported_Defines + * @{ + */ + +#ifndef NULL +#define NULL 0 +#endif + +#define USB_LEN_DEV_QUALIFIER_DESC 0x0A +#define USB_LEN_DEV_DESC 0x12 +#define USB_LEN_CFG_DESC 0x09 +#define USB_LEN_IF_DESC 0x09 +#define USB_LEN_EP_DESC 0x07 +#define USB_LEN_OTG_DESC 0x03 + +#define USBD_IDX_LANGID_STR 0x00 +#define USBD_IDX_MFC_STR 0x01 +#define USBD_IDX_PRODUCT_STR 0x02 +#define USBD_IDX_SERIAL_STR 0x03 +#define USBD_IDX_CONFIG_STR 0x04 +#define USBD_IDX_INTERFACE_STR 0x05 + +#define USB_REQ_TYPE_STANDARD 0x00 +#define USB_REQ_TYPE_CLASS 0x20 +#define USB_REQ_TYPE_VENDOR 0x40 +#define USB_REQ_TYPE_MASK 0x60 + +#define USB_REQ_RECIPIENT_DEVICE 0x00 +#define USB_REQ_RECIPIENT_INTERFACE 0x01 +#define USB_REQ_RECIPIENT_ENDPOINT 0x02 +#define USB_REQ_RECIPIENT_MASK 0x03 + +#define USB_REQ_GET_STATUS 0x00 +#define USB_REQ_CLEAR_FEATURE 0x01 +#define USB_REQ_SET_FEATURE 0x03 +#define USB_REQ_SET_ADDRESS 0x05 +#define USB_REQ_GET_DESCRIPTOR 0x06 +#define USB_REQ_SET_DESCRIPTOR 0x07 +#define USB_REQ_GET_CONFIGURATION 0x08 +#define USB_REQ_SET_CONFIGURATION 0x09 +#define USB_REQ_GET_INTERFACE 0x0A +#define USB_REQ_SET_INTERFACE 0x0B +#define USB_REQ_SYNCH_FRAME 0x0C + +#define USB_DESC_TYPE_DEVICE 1 +#define USB_DESC_TYPE_CONFIGURATION 2 +#define USB_DESC_TYPE_STRING 3 +#define USB_DESC_TYPE_INTERFACE 4 +#define USB_DESC_TYPE_ENDPOINT 5 +#define USB_DESC_TYPE_DEVICE_QUALIFIER 6 +#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 7 + + +#define USB_CONFIG_REMOTE_WAKEUP 2 +#define USB_CONFIG_SELF_POWERED 1 + +#define USB_FEATURE_EP_HALT 0 +#define USB_FEATURE_REMOTE_WAKEUP 1 +#define USB_FEATURE_TEST_MODE 2 + +/** + * @} + */ + + +/** @defgroup USBD_DEF_Exported_TypesDefinitions + * @{ + */ +/** + * @} + */ + + + +/** @defgroup USBD_DEF_Exported_Macros + * @{ + */ +#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ + (((uint16_t)(*(((uint8_t *)(addr)) + 1))) << 8)) + +#define LOBYTE(x) ((uint8_t)(x & 0x00FF)) +#define HIBYTE(x) ((uint8_t)((x & 0xFF00) >>8)) +/** + * @} + */ + +/** @defgroup USBD_DEF_Exported_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_DEF_Exported_FunctionsPrototype + * @{ + */ + +/** + * @} + */ + +#endif /* __USBD_DEF_H */ + +/** + * @} + */ + +/** +* @} +*/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/include/usbd_desc.h b/radio/bootloader/include/usbd_desc.h new file mode 100644 index 000000000..75b694e76 --- /dev/null +++ b/radio/bootloader/include/usbd_desc.h @@ -0,0 +1,120 @@ +/** + ****************************************************************************** + * @file usbd_desc.h + * @author MCD Application Team + * @version V1.1.0 + * @date 19-March-2012 + * @brief header file for the usbd_desc.c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ + +#ifndef __USB_DESC_H +#define __USB_DESC_H + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_def.h" + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USB_DESC + * @brief general defines for the usb device library file + * @{ + */ + +/** @defgroup USB_DESC_Exported_Defines + * @{ + */ +#define USB_DEVICE_DESCRIPTOR_TYPE 0x01 +#define USB_CONFIGURATION_DESCRIPTOR_TYPE 0x02 +#define USB_STRING_DESCRIPTOR_TYPE 0x03 +#define USB_INTERFACE_DESCRIPTOR_TYPE 0x04 +#define USB_ENDPOINT_DESCRIPTOR_TYPE 0x05 +#define USB_SIZ_DEVICE_DESC 18 +#define USB_SIZ_STRING_LANGID 4 + +/** + * @} + */ + + +/** @defgroup USBD_DESC_Exported_TypesDefinitions + * @{ + */ +/** + * @} + */ + + + +/** @defgroup USBD_DESC_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USBD_DESC_Exported_Variables + * @{ + */ +extern uint8_t USBD_DeviceDesc [USB_SIZ_DEVICE_DESC]; +extern uint8_t USBD_StrDesc[USB_MAX_STR_DESC_SIZ]; +extern uint8_t USBD_OtherSpeedCfgDesc[USB_LEN_CFG_DESC]; +extern uint8_t USBD_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC]; +extern uint8_t USBD_LangIDDesc[USB_SIZ_STRING_LANGID]; +extern USBD_DEVICE USR_desc; +/** + * @} + */ + +/** @defgroup USBD_DESC_Exported_FunctionsPrototype + * @{ + */ + + +uint8_t * USBD_USR_DeviceDescriptor( uint8_t speed , uint16_t *length); +uint8_t * USBD_USR_LangIDStrDescriptor( uint8_t speed , uint16_t *length); +uint8_t * USBD_USR_ManufacturerStrDescriptor ( uint8_t speed , uint16_t *length); +uint8_t * USBD_USR_ProductStrDescriptor ( uint8_t speed , uint16_t *length); +uint8_t * USBD_USR_SerialStrDescriptor( uint8_t speed , uint16_t *length); +uint8_t * USBD_USR_ConfigStrDescriptor( uint8_t speed , uint16_t *length); +uint8_t * USBD_USR_InterfaceStrDescriptor( uint8_t speed , uint16_t *length); + +#ifdef USB_SUPPORT_USER_STRING_DESC +uint8_t * USBD_USR_USRStringDesc (uint8_t speed, uint8_t idx , uint16_t *length); +#endif /* USB_SUPPORT_USER_STRING_DESC */ + +/** + * @} + */ + +#endif /* __USBD_DESC_H */ + +/** + * @} + */ + +/** +* @} +*/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/include/usbd_ioreq.h b/radio/bootloader/include/usbd_ioreq.h new file mode 100644 index 000000000..b385b31ca --- /dev/null +++ b/radio/bootloader/include/usbd_ioreq.h @@ -0,0 +1,121 @@ +/** + ****************************************************************************** + * @file usbd_ioreq.h + * @author MCD Application Team + * @version V1.1.0 + * @date 19-March-2012 + * @brief header file for the usbd_ioreq.c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ + +#ifndef __USBD_IOREQ_H_ +#define __USBD_IOREQ_H_ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_def.h" +#include "usbd_core.h" + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_IOREQ + * @brief header file for the usbd_ioreq.c file + * @{ + */ + +/** @defgroup USBD_IOREQ_Exported_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Exported_Types + * @{ + */ + + +/** + * @} + */ + + + +/** @defgroup USBD_IOREQ_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_IOREQ_Exported_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_IOREQ_Exported_FunctionsPrototype + * @{ + */ + +USBD_Status USBD_CtlSendData (USB_OTG_CORE_HANDLE *pdev, + uint8_t *buf, + uint16_t len); + +USBD_Status USBD_CtlContinueSendData (USB_OTG_CORE_HANDLE *pdev, + uint8_t *pbuf, + uint16_t len); + +USBD_Status USBD_CtlPrepareRx (USB_OTG_CORE_HANDLE *pdev, + uint8_t *pbuf, + uint16_t len); + +USBD_Status USBD_CtlContinueRx (USB_OTG_CORE_HANDLE *pdev, + uint8_t *pbuf, + uint16_t len); + +USBD_Status USBD_CtlSendStatus (USB_OTG_CORE_HANDLE *pdev); + +USBD_Status USBD_CtlReceiveStatus (USB_OTG_CORE_HANDLE *pdev); + +uint16_t USBD_GetRxCount (USB_OTG_CORE_HANDLE *pdev , + uint8_t epnum); + +/** + * @} + */ + +#endif /* __USBD_IOREQ_H_ */ + +/** + * @} + */ + +/** +* @} +*/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/include/usbd_msc_bot.h b/radio/bootloader/include/usbd_msc_bot.h new file mode 100644 index 000000000..fe85b5170 --- /dev/null +++ b/radio/bootloader/include/usbd_msc_bot.h @@ -0,0 +1,153 @@ +/** + ****************************************************************************** + * @file usbd_msc_bot.h + * @author MCD Application Team + * @version V1.1.0 + * @date 19-March-2012 + * @brief header for the usbd_msc_bot.c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ + +#include "usbd_core.h" + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_MSC_BOT_H +#define __USBD_MSC_BOT_H + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup MSC_BOT + * @brief This file is the Header file for usbd_bot.c + * @{ + */ + + +/** @defgroup USBD_CORE_Exported_Defines + * @{ + */ +#define BOT_IDLE 0 /* Idle state */ +#define BOT_DATA_OUT 1 /* Data Out state */ +#define BOT_DATA_IN 2 /* Data In state */ +#define BOT_LAST_DATA_IN 3 /* Last Data In Last */ +#define BOT_SEND_DATA 4 /* Send Immediate data */ + +#define BOT_CBW_SIGNATURE 0x43425355 +#define BOT_CSW_SIGNATURE 0x53425355 +#define BOT_CBW_LENGTH 31 +#define BOT_CSW_LENGTH 13 + +/* CSW Status Definitions */ +#define CSW_CMD_PASSED 0x00 +#define CSW_CMD_FAILED 0x01 +#define CSW_PHASE_ERROR 0x02 + +/* BOT Status */ +#define BOT_STATE_NORMAL 0 +#define BOT_STATE_RECOVERY 1 +#define BOT_STATE_ERROR 2 + + +#define DIR_IN 0 +#define DIR_OUT 1 +#define BOTH_DIR 2 + +/** + * @} + */ + +/** @defgroup MSC_CORE_Private_TypesDefinitions + * @{ + */ + +typedef struct _MSC_BOT_CBW +{ + uint32_t dSignature; + uint32_t dTag; + uint32_t dDataLength; + uint8_t bmFlags; + uint8_t bLUN; + uint8_t bCBLength; + uint8_t CB[16]; +} +MSC_BOT_CBW_TypeDef; + + +typedef struct _MSC_BOT_CSW +{ + uint32_t dSignature; + uint32_t dTag; + uint32_t dDataResidue; + uint8_t bStatus; +} +MSC_BOT_CSW_TypeDef; + +/** + * @} + */ + + +/** @defgroup USBD_CORE_Exported_Types + * @{ + */ + +extern uint8_t MSC_BOT_Data[]; +extern uint16_t MSC_BOT_DataLen; +extern uint8_t MSC_BOT_State; +extern uint8_t MSC_BOT_BurstMode; +extern MSC_BOT_CBW_TypeDef MSC_BOT_cbw; +extern MSC_BOT_CSW_TypeDef MSC_BOT_csw; +/** + * @} + */ +/** @defgroup USBD_CORE_Exported_FunctionsPrototypes + * @{ + */ +void MSC_BOT_Init (USB_OTG_CORE_HANDLE *pdev); +void MSC_BOT_Reset (USB_OTG_CORE_HANDLE *pdev); +void MSC_BOT_DeInit (USB_OTG_CORE_HANDLE *pdev); +void MSC_BOT_DataIn (USB_OTG_CORE_HANDLE *pdev, + uint8_t epnum); + +void MSC_BOT_DataOut (USB_OTG_CORE_HANDLE *pdev, + uint8_t epnum); + +void MSC_BOT_SendCSW (USB_OTG_CORE_HANDLE *pdev, + uint8_t CSW_Status); + +void MSC_BOT_CplClrFeature (USB_OTG_CORE_HANDLE *pdev, + uint8_t epnum); +/** + * @} + */ + +#endif /* __USBD_MSC_BOT_H */ +/** + * @} + */ + +/** +* @} +*/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/bootloader/include/usbd_msc_core.h b/radio/bootloader/include/usbd_msc_core.h new file mode 100644 index 000000000..5662465cc --- /dev/null +++ b/radio/bootloader/include/usbd_msc_core.h @@ -0,0 +1,77 @@ +/** + ****************************************************************************** + * @file usbd_msc_core.h + * @author MCD Application Team + * @version V1.1.0 + * @date 19-March-2012 + * @brief header for the usbd_msc_core.c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _USB_MSC_CORE_H_ +#define _USB_MSC_CORE_H_ + +#include "usbd_ioreq.h" + +/** @addtogroup USBD_MSC_BOT + * @{ + */ + +/** @defgroup USBD_MSC + * @brief This file is the Header file for USBD_msc.c + * @{ + */ + + +/** @defgroup USBD_BOT_Exported_Defines + * @{ + */ + + +#define BOT_GET_MAX_LUN 0xFE +#define BOT_RESET 0xFF +#define USB_MSC_CONFIG_DESC_SIZ 32 + +#define MSC_EPIN_SIZE MSC_MAX_PACKET +#define MSC_EPOUT_SIZE MSC_MAX_PACKET + +/** + * @} + */ + +/** @defgroup USB_CORE_Exported_Types + * @{ + */ + +extern USBD_Class_cb_TypeDef USBD_MSC_cb; +/** + * @} + */ + +/** + * @} + */ +#endif // _USB_MSC_CORE_H_ +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/include/usbd_msc_data.h b/radio/bootloader/include/usbd_msc_data.h new file mode 100644 index 000000000..3fb21185a --- /dev/null +++ b/radio/bootloader/include/usbd_msc_data.h @@ -0,0 +1,104 @@ +/** + ****************************************************************************** + * @file usbd_msc_data.h + * @author MCD Application Team + * @version V1.1.0 + * @date 19-March-2012 + * @brief header for the usbd_msc_data.c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ + +#ifndef _USBD_MSC_DATA_H_ +#define _USBD_MSC_DATA_H_ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_conf.h" + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USB_INFO + * @brief general defines for the usb device library file + * @{ + */ + +/** @defgroup USB_INFO_Exported_Defines + * @{ + */ +#define MODE_SENSE6_LEN 8 +#define MODE_SENSE10_LEN 8 +#define LENGTH_INQUIRY_PAGE00 7 +#define LENGTH_FORMAT_CAPACITIES 20 + +/** + * @} + */ + + +/** @defgroup USBD_INFO_Exported_TypesDefinitions + * @{ + */ +/** + * @} + */ + + + +/** @defgroup USBD_INFO_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_INFO_Exported_Variables + * @{ + */ +extern const uint8_t MSC_Page00_Inquiry_Data[]; +extern const uint8_t MSC_Mode_Sense6_data[]; +extern const uint8_t MSC_Mode_Sense10_data[] ; + +/** + * @} + */ + +/** @defgroup USBD_INFO_Exported_FunctionsPrototype + * @{ + */ + +/** + * @} + */ + +#endif /* _USBD_MSC_DATA_H_ */ + +/** + * @} + */ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/include/usbd_msc_mem.h b/radio/bootloader/include/usbd_msc_mem.h new file mode 100644 index 000000000..6b1378f7c --- /dev/null +++ b/radio/bootloader/include/usbd_msc_mem.h @@ -0,0 +1,112 @@ +/** + ****************************************************************************** + * @file usbd_msc_mem.h + * @author MCD Application Team + * @version V1.1.0 + * @date 19-March-2012 + * @brief header for the STORAGE DISK file file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ + +#ifndef __USBD_MEM_H +#define __USBD_MEM_H +/* Includes ------------------------------------------------------------------*/ +#include "usbd_def.h" + + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_MEM + * @brief header file for the storage disk file + * @{ + */ + +/** @defgroup USBD_MEM_Exported_Defines + * @{ + */ +#define USBD_STD_INQUIRY_LENGTH 36 +/** + * @} + */ + + +/** @defgroup USBD_MEM_Exported_TypesDefinitions + * @{ + */ + +typedef struct _USBD_STORAGE +{ + int8_t (* Init) (uint8_t lun); + int8_t (* GetCapacity) (uint8_t lun, uint32_t *block_num, uint32_t *block_size); + int8_t (* IsReady) (uint8_t lun); + int8_t (* IsWriteProtected) (uint8_t lun); + int8_t (* Read) (uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len); + int8_t (* Write)(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len); + int8_t (* GetMaxLun)(void); + int8_t *pInquiry; + +}USBD_STORAGE_cb_TypeDef; +/** + * @} + */ + + + +/** @defgroup USBD_MEM_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_MEM_Exported_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_MEM_Exported_FunctionsPrototype + * @{ + */ +extern USBD_STORAGE_cb_TypeDef *USBD_STORAGE_fops; +/** + * @} + */ + +#endif /* __USBD_MEM_H */ +/** + * @} + */ + +/** + * @} + */ + +/** +* @} +*/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/include/usbd_msc_scsi.h b/radio/bootloader/include/usbd_msc_scsi.h new file mode 100644 index 000000000..71b8250d3 --- /dev/null +++ b/radio/bootloader/include/usbd_msc_scsi.h @@ -0,0 +1,195 @@ +/** + ****************************************************************************** + * @file usbd_msc_scsi.h + * @author MCD Application Team + * @version V1.1.0 + * @date 19-March-2012 + * @brief header for the usbd_msc_scsi.c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_MSC_SCSI_H +#define __USBD_MSC_SCSI_H + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_def.h" + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_SCSI + * @brief header file for the storage disk file + * @{ + */ + +/** @defgroup USBD_SCSI_Exported_Defines + * @{ + */ + +#define SENSE_LIST_DEEPTH 4 + +/* SCSI Commands */ +#define SCSI_FORMAT_UNIT 0x04 +#define SCSI_INQUIRY 0x12 +#define SCSI_MODE_SELECT6 0x15 +#define SCSI_MODE_SELECT10 0x55 +#define SCSI_MODE_SENSE6 0x1A +#define SCSI_MODE_SENSE10 0x5A +#define SCSI_ALLOW_MEDIUM_REMOVAL 0x1E +#define SCSI_READ6 0x08 +#define SCSI_READ10 0x28 +#define SCSI_READ12 0xA8 +#define SCSI_READ16 0x88 + +#define SCSI_READ_CAPACITY10 0x25 +#define SCSI_READ_CAPACITY16 0x9E + +#define SCSI_REQUEST_SENSE 0x03 +#define SCSI_START_STOP_UNIT 0x1B +#define SCSI_TEST_UNIT_READY 0x00 +#define SCSI_WRITE6 0x0A +#define SCSI_WRITE10 0x2A +#define SCSI_WRITE12 0xAA +#define SCSI_WRITE16 0x8A + +#define SCSI_VERIFY10 0x2F +#define SCSI_VERIFY12 0xAF +#define SCSI_VERIFY16 0x8F + +#define SCSI_SEND_DIAGNOSTIC 0x1D +#define SCSI_READ_FORMAT_CAPACITIES 0x23 + +#define NO_SENSE 0 +#define RECOVERED_ERROR 1 +#define NOT_READY 2 +#define MEDIUM_ERROR 3 +#define HARDWARE_ERROR 4 +#define ILLEGAL_REQUEST 5 +#define UNIT_ATTENTION 6 +#define DATA_PROTECT 7 +#define BLANK_CHECK 8 +#define VENDOR_SPECIFIC 9 +#define COPY_ABORTED 10 +#define ABORTED_COMMAND 11 +#define VOLUME_OVERFLOW 13 +#define MISCOMPARE 14 + + +#define INVALID_CDB 0x20 +#define INVALID_FIELED_IN_COMMAND 0x24 +#define PARAMETER_LIST_LENGTH_ERROR 0x1A +#define INVALID_FIELD_IN_PARAMETER_LIST 0x26 +#define ADDRESS_OUT_OF_RANGE 0x21 +#define MEDIUM_NOT_PRESENT 0x3A +#define MEDIUM_HAVE_CHANGED 0x28 +#define WRITE_PROTECTED 0x27 +#define UNRECOVERED_READ_ERROR 0x11 +#define WRITE_FAULT 0x03 + +#define READ_FORMAT_CAPACITY_DATA_LEN 0x0C +#define READ_CAPACITY10_DATA_LEN 0x08 +#define MODE_SENSE10_DATA_LEN 0x08 +#define MODE_SENSE6_DATA_LEN 0x04 +#define REQUEST_SENSE_DATA_LEN 0x12 +#define STANDARD_INQUIRY_DATA_LEN 0x24 +#define BLKVFY 0x04 + +extern uint8_t Page00_Inquiry_Data[]; +extern uint8_t Standard_Inquiry_Data[]; +extern uint8_t Standard_Inquiry_Data2[]; +extern uint8_t Mode_Sense6_data[]; +extern uint8_t Mode_Sense10_data[]; +extern uint8_t Scsi_Sense_Data[]; +extern uint8_t ReadCapacity10_Data[]; +extern uint8_t ReadFormatCapacity_Data []; +/** + * @} + */ + + +/** @defgroup USBD_SCSI_Exported_TypesDefinitions + * @{ + */ + +typedef struct _SENSE_ITEM { + char Skey; + union { + struct _ASCs { + char ASC; + char ASCQ; + }b; + unsigned int ASC; + char *pData; + } w; +} SCSI_Sense_TypeDef; +/** + * @} + */ + +/** @defgroup USBD_SCSI_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_SCSI_Exported_Variables + * @{ + */ +extern SCSI_Sense_TypeDef SCSI_Sense [SENSE_LIST_DEEPTH]; +extern uint8_t SCSI_Sense_Head; +extern uint8_t SCSI_Sense_Tail; + +/** + * @} + */ +/** @defgroup USBD_SCSI_Exported_FunctionsPrototype + * @{ + */ +int8_t SCSI_ProcessCmd(USB_OTG_CORE_HANDLE *pdev, + uint8_t lun, + uint8_t *cmd); + +void SCSI_SenseCode(uint8_t lun, + uint8_t sKey, + uint8_t ASC); + +/** + * @} + */ + +#endif /* __USBD_MSC_SCSI_H */ +/** + * @} + */ + +/** + * @} + */ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/bootloader/include/usbd_req.h b/radio/bootloader/include/usbd_req.h new file mode 100644 index 000000000..e16593739 --- /dev/null +++ b/radio/bootloader/include/usbd_req.h @@ -0,0 +1,108 @@ +/** + ****************************************************************************** + * @file usbd_req.h + * @author MCD Application Team + * @version V1.1.0 + * @date 19-March-2012 + * @brief header file for the usbd_req.c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ + +#ifndef __USB_REQUEST_H_ +#define __USB_REQUEST_H_ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_def.h" +#include "usbd_core.h" +#include "usbd_conf.h" + + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_REQ + * @brief header file for the usbd_ioreq.c file + * @{ + */ + +/** @defgroup USBD_REQ_Exported_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_REQ_Exported_Types + * @{ + */ +/** + * @} + */ + + + +/** @defgroup USBD_REQ_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USBD_REQ_Exported_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup USBD_REQ_Exported_FunctionsPrototype + * @{ + */ + +USBD_Status USBD_StdDevReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req); +USBD_Status USBD_StdItfReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req); +USBD_Status USBD_StdEPReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req); +void USBD_ParseSetupRequest( USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req); + +void USBD_CtlError( USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req); + +void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len); +/** + * @} + */ + +#endif /* __USB_REQUEST_H_ */ + +/** + * @} + */ + +/** +* @} +*/ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/include/usbd_usr.h b/radio/bootloader/include/usbd_usr.h new file mode 100644 index 000000000..428cf68e6 --- /dev/null +++ b/radio/bootloader/include/usbd_usr.h @@ -0,0 +1,141 @@ +/** + ****************************************************************************** + * @file usbd_usr.h + * @author MCD Application Team + * @version V1.1.0 + * @date 19-March-2012 + * @brief Header file for usbd_usr.c + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_USR_H__ +#define __USBD_USR_H__ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_core.h" + + +/** @addtogroup USBD_USER + * @{ + */ + +/** @addtogroup USBD_MSC_DEMO_USER_CALLBACKS + * @{ + */ + +/** @defgroup USBD_USR + * @brief This file is the Header file for usbd_usr.c + * @{ + */ + + +/** @defgroup USBD_USR_Exported_Types + * @{ + */ + +extern USBD_Usr_cb_TypeDef USR_cb; +extern USBD_Usr_cb_TypeDef USR_FS_cb; +extern USBD_Usr_cb_TypeDef USR_HS_cb; + + + +/** + * @} + */ + + + +/** @defgroup USBD_USR_Exported_Defines + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_USR_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USBD_USR_Exported_Variables + * @{ + */ + +void USBD_USR_Init(void); +void USBD_USR_DeviceReset (uint8_t speed); +void USBD_USR_DeviceConfigured (void); +void USBD_USR_DeviceSuspended(void); +void USBD_USR_DeviceResumed(void); + +void USBD_USR_DeviceConnected(void); +void USBD_USR_DeviceDisconnected(void); + +void USBD_USR_FS_Init(void); +void USBD_USR_FS_DeviceReset (uint8_t speed); +void USBD_USR_FS_DeviceConfigured (void); +void USBD_USR_FS_DeviceSuspended(void); +void USBD_USR_FS_DeviceResumed(void); + +void USBD_USR_FS_DeviceConnected(void); +void USBD_USR_FS_DeviceDisconnected(void); + +void USBD_USR_HS_Init(void); +void USBD_USR_HS_DeviceReset (uint8_t speed); +void USBD_USR_HS_DeviceConfigured (void); +void USBD_USR_HS_DeviceSuspended(void); +void USBD_USR_HS_DeviceResumed(void); + +void USBD_USR_HS_DeviceConnected(void); +void USBD_USR_HS_DeviceDisconnected(void); + +/** + * @} + */ + +/** @defgroup USBD_USR_Exported_FunctionsPrototype + * @{ + */ +/** + * @} + */ + +#endif /*__USBD_USR_H__*/ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + + + + diff --git a/radio/bootloader/lcd_driver.cpp b/radio/bootloader/lcd_driver.cpp new file mode 100644 index 000000000..839c9a5cc --- /dev/null +++ b/radio/bootloader/lcd_driver.cpp @@ -0,0 +1,314 @@ +/** + ****************************************************************************** + * @file Project/lcd/lcd.c + * @author X9D Application Team + * @Hardware version V0.2 + * @date 11-July-2012 + * @brief This file provides LCD Init and botom drivers. + * * + ****************************************************************************** +*/ + +#include "radio.h" + +#include "stm32f2xx.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_rcc.h" +#include "hal.h" +#include "aspi.h" + +#include "timers.h" +#include "lcd.h" +#include "logicio.h" + +#define WriteData(x) AspiData(x) +#define WriteCommand(x) AspiCmd(x) +#define CONTRAST_OFS 5 + +#define __no_operation __NOP + + +extern uint8_t DisplayBuf[] ; + +void Set_Address(uint8_t x, uint8_t y) +{ + WriteCommand(x&0x0F); //Set Column Address LSB CA[3:0] + WriteCommand((x>>4)|0x10); //Set Column Address MSB CA[7:4] + + WriteCommand((y&0x0F)|0x60); //Set Row Address LSB RA [3:0] + WriteCommand(((y>>4)&0x0F)|0x70); //Set Row Address MSB RA [7:4] +} + +void refreshDisplay() +{ + for (uint32_t y=0; y>3)*DISPLAY_W]; + uint8_t mask = (1 << (y%8)); + GPIO_TypeDef *gpiod = GPIOD ; + Set_Address(0, y); + AspiCmd(0xAF); + + gpiod->BSRRL = PIN_LCD_CLK ; // Clock high + gpiod->BSRRL = PIN_LCD_A0 ; // A0 high + gpiod->BSRRH = PIN_LCD_NCS ; // CS low + + for (uint32_t x=0; xBSRRL = PIN_LCD_MOSI ; + } + else + { + gpiod->BSRRH = PIN_LCD_MOSI ; + } + gpiod->BSRRH = PIN_LCD_CLK ; // Clock low + + if(data&0x40) + { + gpiod->BSRRL = PIN_LCD_MOSI | PIN_LCD_CLK ; + } + else + { + *(uint32_t *)&gpiod->BSRRL = (PIN_LCD_MOSI<<16) | PIN_LCD_CLK ; + } + __no_operation() ; + gpiod->BSRRH = PIN_LCD_CLK ; // Clock low + + if(data&0x20) + { + gpiod->BSRRL = PIN_LCD_MOSI | PIN_LCD_CLK ; + } + else + { + *(uint32_t *)&gpiod->BSRRL = (PIN_LCD_MOSI<<16) | PIN_LCD_CLK ; + } + __no_operation() ; + gpiod->BSRRH = PIN_LCD_CLK ; // Clock low + + if(data&0x10) + { + gpiod->BSRRL = PIN_LCD_MOSI | PIN_LCD_CLK ; + } + else + { + *(uint32_t *)&gpiod->BSRRL = (PIN_LCD_MOSI<<16) | PIN_LCD_CLK ; + } + __no_operation() ; + gpiod->BSRRH = PIN_LCD_CLK ; // Clock low + + if(data&0x08) + { + gpiod->BSRRL = PIN_LCD_MOSI | PIN_LCD_CLK ; + } + else + { + *(uint32_t *)&gpiod->BSRRL = (PIN_LCD_MOSI<<16) | PIN_LCD_CLK ; + } + __no_operation() ; + gpiod->BSRRH = PIN_LCD_CLK ; // Clock low + + if(data&0x04) + { + gpiod->BSRRL = PIN_LCD_MOSI | PIN_LCD_CLK ; + } + else + { + *(uint32_t *)&gpiod->BSRRL = (PIN_LCD_MOSI<<16) | PIN_LCD_CLK ; + } + __no_operation() ; + gpiod->BSRRH = PIN_LCD_CLK ; // Clock low + + if(data&0x02) + { + gpiod->BSRRL = PIN_LCD_MOSI | PIN_LCD_CLK ; + } + else + { + *(uint32_t *)&gpiod->BSRRL = (PIN_LCD_MOSI<<16) | PIN_LCD_CLK ; + } + __no_operation() ; + gpiod->BSRRH = PIN_LCD_CLK ; // Clock low + + if(data&0x01) + { + gpiod->BSRRL = PIN_LCD_MOSI | PIN_LCD_CLK ; + } + else + { + *(uint32_t *)&gpiod->BSRRL = (PIN_LCD_MOSI<<16) | PIN_LCD_CLK ; + } + __no_operation() ; + gpiod->BSRRH = PIN_LCD_CLK ; // Clock low + __no_operation() ; + gpiod->BSRRL = PIN_LCD_CLK ; // Clock high + + } + gpiod->BSRRL = PIN_LCD_NCS ; + gpiod->BSRRL = PIN_LCD_A0 ; + WriteData(0); + } +} + +uint16_t BacklightBrightness ; + +void backlight_on() +{ + TIM10->CCR1 = 100 - BacklightBrightness ; +} + +void backlight_off() +{ + TIM10->CCR1 = 0 ; +} + +void backlight_set( uint16_t brightness ) +{ + BacklightBrightness = brightness ; + TIM10->CCR1 = 100 - BacklightBrightness ; +} + + +/**Init the Backlight GPIO */ +static void LCD_BL_Config() +{ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOBL, ENABLE); + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin =GPIO_Pin_BL; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOBL, &GPIO_InitStructure); + + GPIO_PinAFConfig(GPIOBL, GPIO_PinSource_BL ,GPIO_AF_TIM10); + + RCC->APB2ENR |= RCC_APB2ENR_TIM10EN ; // Enable clock + TIM10->ARR = 100 ; + TIM10->PSC = (Peri2_frequency*Timer_mult2) / 10000 - 1 ; // 100uS from 30MHz + TIM10->CCMR1 = 0x60 ; // PWM + TIM10->CCER = 1 ; + + BacklightBrightness = 80 ; + TIM10->CCR1 = BacklightBrightness ; + TIM10->EGR = 0 ; + TIM10->CR1 = 1 ; +} + +/** Init the anolog spi gpio +*/ +static void LCD_Hardware_Init() +{ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_LCD, ENABLE); + + GPIO_InitTypeDef GPIO_InitStructure; + + /*!< Configure lcd CLK\ MOSI\ A0pin in output pushpull mode *************/ + GPIO_InitStructure.GPIO_Pin =PIN_LCD_MOSI | PIN_LCD_CLK | PIN_LCD_A0; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIO_LCD, &GPIO_InitStructure); + + /*!< Configure lcd NCS pin in output pushpull mode ,PULLUP *************/ + GPIO_InitStructure.GPIO_Pin = PIN_LCD_NCS | PIN_LCD_RST ; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + + GPIO_Init(GPIO_LCD, &GPIO_InitStructure); +} + +static void LCD_Init() +{ + LCD_BL_Config() ; + /*Hardware Reset need delay*/ + /*LCD_RST_LOW(); + Delay(50); + LCD_RST_HIGH();*/ + + AspiCmd(0x25); //Temperature compensation curve definition: 0x25 = -0.05%/oC + AspiCmd(0x2b); //Panel loading set ,Internal VLCD. + AspiCmd(0xEA); //set bias=1/10 :Command table NO.27 + AspiCmd(0x81); //Set Vop + AspiCmd(25+CONTRAST_OFS); //0--255 + AspiCmd(0xA6); //inverse display off + AspiCmd(0xD1); //SET RGB:Command table NO.21 .SET RGB or BGR. D1=RGB + AspiCmd(0xD5); //set color mode 4K and 12bits :Command table NO.22 + AspiCmd(0xA0); //line rates,25.2 Klps + AspiCmd(0xC8); //SET N-LINE INVERSION + AspiCmd(0x1D); //Disable NIV + AspiCmd(0xF1); //Set CEN + AspiCmd(0x3F); // 1/64DUTY + AspiCmd(0x84); //Disable Partial Display + AspiCmd(0xC4); //MY=1,MX=0 + AspiCmd(0x89); //WA=1,column (CA) increment (+1) first until CA reaches CA boundary, then RA will increment by (+1). + + AspiCmd(0xF8); //Set Window Program Enable ,inside modle + AspiCmd(0xF4); //starting column address of RAM program window. + AspiCmd(0x00); + AspiCmd(0xF5); //starting row address of RAM program window. + AspiCmd(0x60); + AspiCmd(0xF6); //ending column address of RAM program window. + AspiCmd(0x47); + AspiCmd(0xF7); //ending row address of RAM program window. + AspiCmd(0x9F); + + AspiCmd(0xAF); //dc2=1,IC into exit SLEEP MODE, dc3=1 gray=ON ҽ ,dc4=1 Green Enhanc mode disabled ɫǿģʽ + +} + +static void Delay(volatile unsigned int ms) +{ + volatile u8 i; + while(ms != 0) + { + for(i=0;i<250;i++) {} + for(i=0;i<75;i++) {} + ms--; + } +} + +void lcd_init() +{ + GPIO_TypeDef *gpiod = GPIOD ; + + LCD_BL_Config(); + LCD_Hardware_Init(); + + gpiod->BSRRL = PIN_LCD_RST ; // RST high + Delay(5); + + gpiod->BSRRH = PIN_LCD_RST ; // RST low + Delay(120); //11ms + + gpiod->BSRRL = PIN_LCD_RST ; // RST high + Delay(2500); + + AspiCmd(0xE2); + Delay(2500); + + LCD_Init(); + Delay(120); + AspiCmd(0xAF); //dc2=1, IC into exit SLEEP MODE, dc3=1 gray=ON, dc4=1 Green Enhanc mode disabled +} + +void lcdSetRefVolt(uint8_t val) +{ + AspiCmd(0x81); //Set Vop + AspiCmd(val+CONTRAST_OFS); //0--255 +} diff --git a/radio/bootloader/lcdboot.cpp b/radio/bootloader/lcdboot.cpp new file mode 100644 index 000000000..741f80002 --- /dev/null +++ b/radio/bootloader/lcdboot.cpp @@ -0,0 +1,618 @@ +/* + * Author - Mike Blandford + * + * Based on er9x by Erez Raviv + * + * Based on th9x -> http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +// This version for ARM based ERSKY9X board + +#include +#include +#include + +#ifdef PCBSKY +#include "AT91SAM3S4.h" +#include "radio.h" +//#include "myeeprom.h" +#endif + +#ifdef PCBX9D + #include "radio.h" +#endif + +#include "lcd.h" +#include "drivers.h" +#include "logicio.h" + +#include "font.lbm" +#define font_5x8_x20_x7f (font) + +#include "font_dblsize.lbm" +#define font_10x16_x20_x7f (font_dblsize) + +// Local data +uint8_t OptrexDisplay = 0 ; +uint8_t Lcd_lastPos ; +uint8_t DisplayBuf[DISPLAY_W*DISPLAY_H/8] ; +#define DISPLAY_END (DisplayBuf+sizeof(DisplayBuf)) + +#ifdef PCBX9D +#define X9D_OFFSET 0 +#define DISPLAY_START (DisplayBuf + X9D_OFFSET) +#else +#define DISPLAY_START (DisplayBuf + 0) +#endif + + + +/// invers: 0 no 1=yes 2=blink +void lcd_putc(uint8_t x,uint8_t y,const char c ) +{ + lcd_putcAtt(x,y,c,0); +} + +uint8_t lcd_putcAtt(uint8_t x,uint8_t y,const char c,uint8_t mode) +{ + register int32_t i ; + register uint8_t *p = &DISPLAY_START[ y / 8 * DISPLAY_W + x ]; + //uint8_t *pmax = &displayBuf[ DISPLAY_H/8 * DISPLAY_W ]; + if ( c < 22 ) // Move to specific x position (c)*FW + { + x = c*FW ; + if(mode&DBLSIZE) + { + x += x ; + } + return x ; + } + x += FW ; + register uint8_t *q ; + if( c < 0xC0 ) + { + q = (uint8_t *) &font_5x8_x20_x7f[(c-0x20)*5] ; + } + else + { + q = (uint8_t *) &font_5x8_x20_x7f[0] ; + } + register bool inv = (mode & INVERS) ? true : false ; + + if(mode&DBLSIZE) + { + if ( (c!=0x2E)) x+=FW; //check for decimal point + /* each letter consists of ten top bytes followed by + * five bottom by ten bottom bytes (20 bytes per + * char) */ + unsigned char c_mapped ; + if( c < 0xC0 ) + { + if ( c == 'B' ) + { + c_mapped = 1 ; + } + else if ( c == 'S' ) + { + c_mapped = 2 ; + } + else if ( c == 'U' ) + { + c_mapped = 3 ; + } + else + { + c_mapped = 0 ; + } + q = (uint8_t *) &font_10x16_x20_x7f[(c_mapped)*20] ; +// q = (uint8_t *) &font_10x16_x20_x7f[(c-0x20)*10 + ((c-0x20)/16)*160]; + } + else + { + q = (uint8_t *) &font_10x16_x20_x7f[0] ; + } + for( i=5 ; i>=0 ; i-- ) + { + uint8_t b1 ; + uint8_t b3 ; + uint8_t b2 ; + uint8_t b4 ; + + if( c < 0xC0 ) + { + /*top byte*/ + b1 = i>0 ? *q : 0; + /*bottom byte*/ + b3 = i>0 ? *(q+10) : 0; + /*top byte*/ + b2 = i>0 ? *(++q) : 0; + /*bottom byte*/ + b4 = i>0 ? *(q+10) : 0; + q++; + } + else + { + /*top byte*/ + b1 = i>0 ? *q++ : 0 ; + /*bottom byte*/ + b3 = i>0 ? *q++ : 0 ; + /*top byte*/ + b2 = i>0 ? *q++ : 0 ; + /*bottom byte*/ + b4 = i>0 ? *q++ : 0 ; + } + if(inv) + { + b1=~b1; + b2=~b2; + b3=~b3; + b4=~b4; + } + + if(&p[DISPLAY_W+1] < DISPLAY_END) + { + p[0]=b1; + p[1]=b2; + p[DISPLAY_W] = b3; + p[DISPLAY_W+1] = b4; + p+=2; + } + } + } + else + { + uint8_t condense=0; + + if (mode & CONDENSED) + { + *p++ = inv ? ~0 : 0; + condense=1; + x += FWNUM-FW ; + } + + for( i=5 ; i!=0 ; i-- ) + { + uint8_t b = *q++ ; + if (condense && i==4) + { + /*condense the letter by skipping column 4 */ + continue; + } + if(p9 ? c+'A'-10 : c+'0'; + lcd_putcAtt(x,y,c,c>='A'?CONDENSED:0); + val>>=4; + } +} +uint8_t plotType = PLOT_XOR ; + +void lcd_write_bits( uint8_t *p, uint8_t mask ) +{ + if(p=DISPLAY_END) + { + break ; + } + if(pat&1) + { + lcd_write_bits( p, msk ) ; + pat = (pat >> 1) | 0x80; + } + else + { + pat = pat >> 1; + } + w--; + p++; + } +} + + +// Reverse video 8 pixels high, w pixels wide +// Vertically on an 8 pixel high boundary +void lcd_char_inverse( uint8_t x, uint8_t y, uint8_t w, uint8_t blink ) +{ +// if ( blink && BLINK_ON_PHASE ) +// { +// return ; +// } + uint8_t end = x + w ; + uint8_t *p = &DISPLAY_START[ y / 8 * DISPLAY_W + x ]; + + while ( x < end ) + { + *p++ ^= 0xFF ; + x += 1 ; + } +} + +void lcd_hline( uint8_t x, uint8_t y, int8_t w ) +{ + lcd_hlineStip(x,y,w,0xff); +} + +void lcd_vline( uint8_t x, uint8_t y, int8_t h ) +{ + if (h<0) { y+=h; h=-h; } + register uint8_t *p = &DISPLAY_START[ y / 8 * DISPLAY_W + x ]; + + y &= 0x07 ; + if ( y ) + { + uint8_t msk = ~(BITMASK(y)-1) ; + h -= 8-y ; + if (h < 0) + msk -= ~(BITMASK(8+h)-1) ; + lcd_write_bits( p, msk ) ; + p += DISPLAY_W ; + } + + while( h >= 8 ) + { + h -= 8 ; + lcd_write_bits( p, 0xFF ) ; + p += DISPLAY_W ; + } + if ( h > 0 ) + { + lcd_write_bits( p, (BITMASK(h)-1) ) ; + } +} + +#ifdef SIMU +bool lcd_refresh = true; +uint8_t lcd_buf[DISPLAY_W*DISPLAY_H/8]; +#endif + + +void lcd_clear() +{ + //for(unsigned i=0; iPIO_PDSR << 1 ; // 6 LEFT, 5 RIGHT, 4 DOWN, 3 UP () + LcdLock = 1 ; +// pioptr = PIOA ; +// pioptr->PIO_PER = LCD_A0 ; // Enable bit 7 (LCD-A0) +// pioptr->PIO_CODR = LCD_A0 ; +// pioptr->PIO_OER = LCD_A0 ; // Set bit 7 output + pioptr = PIOC ; + +#ifdef REVX + pioptr->PIO_PER = PIO_PC27 | PIO_PC12 | 0xFF ; // Enable bits 27,26,13,12,7-0 +#else + pioptr->PIO_PER = PIO_PC27 | PIO_PC26 | PIO_PC13 | PIO_PC12 | 0xFF ; // Enable bits 27,26,13,12,7-0 +#endif // REVX + +//#ifndef REVX +// pioptr->PIO_CODR = LCD_E | LCD_RnW ; +// pioptr->PIO_SODR = LCD_RES | LCD_CS1 ; +//#else +#ifdef REVX + pioptr->PIO_CODR = LCD_E ; + pioptr->PIO_CODR = LCD_RnW | LCD_CS1 ; // No longer needed, used elsewhere +#else + pioptr->PIO_CODR = LCD_E | LCD_RnW | LCD_CS1 ; +#endif // REVX + pioptr->PIO_SODR = LCD_RES ; +//#endif + pioptr->PIO_OER = PIO_PC27 | PIO_PC26 | PIO_PC13 | PIO_PC12 | 0xFF ; // Set bits 27,26,13,12,7-0 output + pioptr->PIO_OWER = 0x000000FFL ; // Allow write to ls 8 bits in ODSR + + pioptr->PIO_CODR = LCD_RES ; // Reset LCD + TC0->TC_CHANNEL[0].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) + while ( TC0->TC_CHANNEL[0].TC_CV < 200 ) // >10 uS, Value depends on MCK/2 (used 18MHz) + { + // Wait + } + pioptr->PIO_SODR = LCD_RES ; // Remove LCD reset + TC0->TC_CHANNEL[0].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) + while ( TC0->TC_CHANNEL[0].TC_CV < 27000 ) // 1500 uS, Value depends on MCK/2 (used 18MHz) + { + // Wait + } + for ( i = 0 ; i < 12 ; i += 1 ) + { + lcdSendCtl( Lcdinit[i] ) ; + } + + pioptr->PIO_ODR = 0x0000003AL ; // Set bits 1, 3, 4, 5 input + pioptr->PIO_PUER = 0x0000003AL ; // Set bits 1, 3, 4, 5 with pullups + pioptr->PIO_ODSR = 0 ; // Drive D0 low + LcdLock = 0 ; + +#ifdef REVX + lcdSetRefVolt( 23 ) ; +#else + lcdSetRefVolt( 30 ) ; +#endif + +} + + +void lcdSetRefVolt(uint8_t val) +{ +#ifndef SIMU + register Pio *pioptr ; + pioptr = PIOC ; + +// read the inputs, and lock the LCD lines + LcdInputs = PIOC->PIO_PDSR << 1 ; // 6 LEFT, 5 RIGHT, 4 DOWN, 3 UP () + LcdLock = 1 ; + + pioptr->PIO_OER = 0x0C00B0FFL ; // Set bits 27,26,15,13,12,7-0 output + + lcdSendCtl(0x81); + if ( val == 0 ) + { + val = 0x22 ; + } + lcdSendCtl(val); + + pioptr->PIO_ODR = 0x0000003AL ; // Set bits 1, 3, 4, 5 input + pioptr->PIO_PUER = 0x0000003AL ; // Set bits 1, 3, 4, 5 with pullups + pioptr->PIO_ODSR = 0 ; // Drive D0 low +#endif // SIMU + LcdLock = 0 ; +} + + + +void lcdSendCtl(uint8_t val) +{ + register Pio *pioptr ; + + pioptr = PIOC ; +#ifndef REVX + pioptr->PIO_CODR = LCD_CS1 ; // Select LCD +#endif + PIOA->PIO_CODR = LCD_A0 ; +#ifndef REVX + pioptr->PIO_CODR = LCD_RnW ; // Write +#endif + pioptr->PIO_ODSR = val ; + + pioptr->PIO_SODR = LCD_E ; // Start E pulse + // Need a delay here (250nS) + TC0->TC_CHANNEL[0].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) + while ( TC0->TC_CHANNEL[0].TC_CV < 9 ) // Value depends on MCK/2 (used 18MHz) + { + // Wait + } + pioptr->PIO_CODR = LCD_E ; // End E pulse + PIOA->PIO_SODR = LCD_A0 ; // Data +} + +#ifdef SIMU +void refreshDisplay() +{ + memcpy(lcd_buf, DisplayBuf, sizeof(DisplayBuf)); + lcd_refresh = true; +} +#else +void refreshDisplay() +{ + register Pio *pioptr ; + register uint8_t *p=DisplayBuf; + register uint32_t y ; + register uint32_t x ; + register uint32_t z ; + register uint32_t ebit ; + + ebit = LCD_E ; + + pioptr = PIOA ; + pioptr->PIO_PER = 0x00000080 ; // Enable bit 7 (LCD-A0) + pioptr->PIO_OER = 0x00000080 ; // Set bit 7 output + +// read the inputs, and lock the LCD lines + LcdInputs = PIOC->PIO_PDSR << 1 ; // 6 LEFT, 5 RIGHT, 4 DOWN, 3 UP () + LcdLock = 1 ; + + pioptr = PIOC ; + pioptr->PIO_OER = 0x0C0030FFL ; // Set bits 27,26,15,13,12,7-0 output + for( y=0; y < 8; y++) { + lcdSendCtl( OptrexDisplay ? 0 : 0x04 ) ; + lcdSendCtl(0x10); //column addr 0 + lcdSendCtl( y | 0xB0); //page addr y + +#ifndef REVX + pioptr->PIO_CODR = LCD_CS1 ; // Select LCD +#endif // REVX + + PIOA->PIO_SODR = LCD_A0 ; // Data +#ifndef REVX + pioptr->PIO_CODR = LCD_RnW ; // Write +#endif // REVX + + x = *p ; + for( z=0; z<128; z+=1) + { + pioptr->PIO_ODSR = x ; + pioptr->PIO_SODR = ebit ; // Start E pulse + // Need a delay here (250nS) + p += 1 ; + x = *p ; + pioptr->PIO_CODR = ebit ; // End E pulse + } + } + pioptr->PIO_ODSR = 0xFF ; // Drive lines high + pioptr->PIO_PUER = 0x0000003AL ; // Set bits 1, 3, 4, 5 with pullups + pioptr->PIO_ODR = 0x0000003AL ; // Set bits 1, 3, 4, 5 input + pioptr->PIO_ODSR = 0xFE ; // Drive D0 low + + LcdLock = 0 ; + +} + +#endif // PCBSKY +#endif // PCBSKY + +#ifdef PCBSKY +// This specially for the 9XR +extern void start_timer0( void ) ; +extern void stop_timer0( void ) ; + +extern "C" void dispUSB( void ) ; +void dispUSB() +{ + // Put USB on display here? + start_timer0() ; + lcd_init() ; + OptrexDisplay = 1 ; + lcd_clear() ; + refreshDisplay() ; + OptrexDisplay = 0 ; + lcd_clear() ; + lcd_putcAtt( 48, 24, 'U', DBLSIZE ) ; + lcd_putcAtt( 60, 24, 'S', DBLSIZE ) ; + lcd_putcAtt( 72, 24, 'B', DBLSIZE ) ; + refreshDisplay() ; + stop_timer0() ; +} + +#endif + diff --git a/radio/bootloader/logicioboot.cpp b/radio/bootloader/logicioboot.cpp new file mode 100644 index 000000000..cc6be1b84 --- /dev/null +++ b/radio/bootloader/logicioboot.cpp @@ -0,0 +1,457 @@ +/**************************************************************************** +* Copyright (c) 2012 by Michael Blandford. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* +****************************************************************************/ + +#include +#include +#include +#include + + +#ifdef PCBSKY +#include "AT91SAM3S4.h" +#include "radio.h" +#include "drivers.h" +#endif + +#ifdef PCBX9D +#include "stm32f2xx.h" +#include "stm32f2xx_gpio.h" +#include "radio.h" +#include "hal.h" +#endif + + +#ifndef SIMU +#include "core_cm3.h" +#endif + +#include "logicio.h" + +#ifdef PCBSKY +#include "lcd.h" +#endif + + +#ifndef SIMU +#ifdef PCBSKY +void configure_pins( uint32_t pins, uint16_t config ) +{ + register Pio *pioptr ; + + pioptr = PIOA + ( ( config & PIN_PORT_MASK ) >> 6) ; + if ( config & PIN_PULLUP ) + { + pioptr->PIO_PPDDR = pins ; + pioptr->PIO_PUER = pins ; + } + else + { + pioptr->PIO_PUDR = pins ; + } + + if ( config & PIN_PULLDOWN ) + { + pioptr->PIO_PUDR = pins ; + pioptr->PIO_PPDER = pins ; + } + else + { + pioptr->PIO_PPDDR = pins ; + } + + if ( config & PIN_HIGH ) + { + pioptr->PIO_SODR = pins ; + } + else + { + pioptr->PIO_CODR = pins ; + } + + if ( config & PIN_INPUT ) + { + pioptr->PIO_ODR = pins ; + } + else + { + pioptr->PIO_OER = pins ; + } + + if ( config & PIN_PERI_MASK_L ) + { + pioptr->PIO_ABCDSR[0] |= pins ; + } + else + { + pioptr->PIO_ABCDSR[0] &= ~pins ; + } + if ( config & PIN_PERI_MASK_H ) + { + pioptr->PIO_ABCDSR[1] |= pins ; + } + else + { + pioptr->PIO_ABCDSR[1] &= ~pins ; + } + + if ( config & PIN_ENABLE ) + { + pioptr->PIO_PER = pins ; + } + else + { + pioptr->PIO_PDR = pins ; + } +} +#endif + + +#ifdef PCBX9D +void configure_pins( uint32_t pins, uint16_t config ) +{ + uint32_t address ; + GPIO_TypeDef *pgpio ; + uint32_t thispin ; + uint32_t pos ; + + address = ( config & PIN_PORT_MASK ) >> 8 ; + address *= (GPIOB_BASE-GPIOA_BASE) ; + address += GPIOA_BASE ; + pgpio = (GPIO_TypeDef* ) address ; + + /* -------------------------Configure the port pins---------------- */ + /*-- GPIO Mode Configuration --*/ + for (thispin = 0x0001, pos = 0; thispin < 0x10000; thispin <<= 1, pos +=1 ) + { + if ( pins & thispin) + { + pgpio->MODER &= ~(GPIO_MODER_MODER0 << (pos * 2)) ; + pgpio->MODER |= (config & PIN_MODE_MASK) << (pos * 2) ; + + if ( ( (config & PIN_MODE_MASK ) == PIN_OUTPUT) || ( (config & PIN_MODE_MASK) == PIN_PERIPHERAL) ) + { + /* Speed mode configuration */ + pgpio->OSPEEDR &= ~GPIO_OSPEEDER_OSPEEDR0 << (pos * 2) ; + pgpio->OSPEEDR |= ((config & PIN_SPEED_MASK) >> 13 ) << (pos * 2) ; + + /* Output mode configuration*/ + pgpio->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pos)) ; + if ( config & PIN_ODRAIN ) + { + pgpio->OTYPER |= (GPIO_OTYPER_OT_0) << pos ; + } + } + /* Pull-up Pull down resistor configuration*/ + pgpio->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pos * 2)); + pgpio->PUPDR |= ((config & PIN_PULL_MASK) >> 2) << (pos * 2) ; + + pgpio->AFR[pos >> 3] &= ~(0x000F << ((pos & 7)*4)) ; + pgpio->AFR[pos >> 3] |= ((config & PIN_PERI_MASK) >> 4) << ((pos & 7)*4) ; + } + } +} + +#endif + + + +#ifdef PCBSKY + +void init_keys() +{ + register Pio *pioptr ; + + pioptr = PIOC ; + // Next section configures the key inputs on the LCD data + pioptr->PIO_PER = 0x0000003BL ; // Enable bits 1,3,4,5, 0 + pioptr->PIO_OER = PIO_PC0 ; // Set bit 0 output + pioptr->PIO_ODR = 0x0000003AL ; // Set bits 1, 3, 4, 5 input + pioptr->PIO_PUER = 0x0000003AL ; // Set bits 1, 3, 4, 5 with pullups + + pioptr = PIOB ; + pioptr->PIO_PUER = PIO_PB5 ; // Enable pullup on bit B5 (MENU) + pioptr->PIO_PER = PIO_PB5 ; // Enable bit B5 +} + +// Assumes PMC has already enabled clocks to ports +void setup_switches() +{ + configure_pins( 0x01808087, PIN_ENABLE | PIN_INPUT | PIN_PORTA | PIN_PULLUP ) ; + configure_pins( 0x00000030, PIN_ENABLE | PIN_INPUT | PIN_PORTB | PIN_PULLUP ) ; + configure_pins( 0x91114900, PIN_ENABLE | PIN_INPUT | PIN_PORTC | PIN_PULLUP ) ; +} + + +// Switch input pins +// Needs updating for REVB board ******** +// AIL-DR PA2 +// TRIM_LH_DOWN PA7 (PA23) +// ELE_DR PA8 (PC31) +// RUN_DR PA15 +// TRIM_LV_DOWN PA27 (PA24) +// SW_TCUT PA28 (PC20) +// TRIM_RH_DOWN PA29 (PA0) +// TRIM_RV_UP PA30 (PA1) +// TRIM_LH_UP //PB4 +// SW-TRAIN PC8 +// TRIM_RH_UP PC9 +// TRIM_RV_DOWN PC10 +// SW_IDL2 PC11 +// SW_IDL1 PC14 +// SW_GEAR PC16 +// TRIM_LV_UP PC28 + +// KEY_MENU PB6 (PB5) +// KEY_EXIT PA31 (PC24) +// Shared with LCD data +// KEY_DOWN LCD5 PC3 +// KEY_UP LCD6 PC2 +// KEY_RIGHT LCD4 PC4 +// KEY_LEFT LCD3 PC5 + +// PORTA 1111 1000 0000 0000 1000 0001 1000 0100 = 0xF8008184 proto +// PORTA 0000 0001 1000 0000 1000 0000 0000 0111 = 0x01808087 REVB +// PORTB 0000 0000 0001 0000 = 0x0010 proto +// PORTB 0000 0000 0010 0000 = 0x0030 REVB +// PORTC 0001 0000 0000 0001 0100 1001 0000 0000 = 0x10014900 proto +// PORTC 1001 0001 0001 0001 0100 1001 0000 0000 = 0x91114900 REVB + + +// Prototype +// Free pins (PA16 is stock buzzer) +// PA23, PA24, PA25, PB7, PB13 +// PC20, PC21(labelled 17), PC22, PC24 +// REVB +// PA25, use for stock buzzer +// PB14, PB6 +// PC21, PC19, PC15 (PPM2 output) +void config_free_pins() +{ + + configure_pins( PIO_PB14, PIN_ENABLE | PIN_INPUT | PIN_PORTB | PIN_PULLUP ) ; + +} + +#endif + +#endif // ndef BOOT + +// keys: +// KEY_EXIT PA31 (PC24) +// KEY_MENU PB6 (PB5) +// KEY_DOWN LCD5 PC3 (PC5) +// KEY_UP LCD6 PC2 (PC1) +// KEY_RIGHT LCD4 PC4 (PC4) +// KEY_LEFT LCD3 PC5 (PC3) +// Reqd. bit 6 LEFT, 5 RIGHT, 4 UP, 3 DOWN 2 EXIT 1 MENU +// LCD pins 5 DOWN, 4 RIGHT, 3 LEFT, 1 UP +#ifdef PCBSKY +uint32_t read_keys() +{ + register uint32_t x ; + register uint32_t y ; + + x = LcdLock ? LcdInputs : PIOC->PIO_PDSR << 1 ; // 6 LEFT, 5 RIGHT, 4 DOWN, 3 UP () + + y = x & 0x00000020 ; // RIGHT + if ( x & 0x00000004 ) + { + y |= 0x00000010 ; // UP + } + if ( x & 0x00000010 ) + { + y |= 0x00000040 ; // LEFT + } + if ( x & 0x00000040 ) + { + y |= 0x00000008 ; // DOWN + } + + if ( PIOC->PIO_PDSR & 0x01000000 ) + { + y |= 4 ; // EXIT + } + if ( PIOB->PIO_PDSR & 0x000000020 ) + { + y |= 2 ; // MENU + } + return y ; +} +#endif + +#ifdef PCBSKY +uint32_t read_trims() +{ + uint32_t trims ; + uint32_t trima ; + + trims = 0 ; + + trima = PIOA->PIO_PDSR ; +// TRIM_LH_DOWN PA7 (PA23) +#ifndef REVX + if ( ( trima & 0x00800000 ) == 0 ) +#else + if ( ( PIOB->PIO_PDSR & 0x10 ) == 0 ) +#endif + { + trims |= 1 ; + } + +// TRIM_LV_DOWN PA27 (PA24) + if ( ( trima & 0x01000000 ) == 0 ) + { + trims |= 4 ; + } + +// TRIM_RV_UP PA30 (PA1) +#ifndef REVX + if ( ( trima & 0x00000002 ) == 0 ) +#else + if ( ( PIOC->PIO_PDSR & 0x00000400 ) == 0 ) +#endif + { + trims |= 0x20 ; + } + +// TRIM_RH_DOWN PA29 (PA0) + if ( ( trima & 0x00000001 ) == 0 ) + { + trims |= 0x40 ; + } + +// TRIM_LH_UP PB4 +#ifndef REVX + if ( ( PIOB->PIO_PDSR & 0x10 ) == 0 ) +#else + if ( ( trima & 0x00800000 ) == 0 ) +#endif + { + trims |= 2 ; + } + + trima = PIOC->PIO_PDSR ; +// TRIM_LV_UP PC28 + if ( ( trima & 0x10000000 ) == 0 ) + { + trims |= 8 ; + } + +// TRIM_RV_DOWN PC10 +#ifndef REVX + if ( ( trima & 0x00000400 ) == 0 ) +#else + if ( ( PIOA->PIO_PDSR & 0x00000002 ) == 0 ) +#endif + { + trims |= 0x10 ; + } + +// TRIM_RH_UP PC9 + if ( ( trima & 0x00000200 ) == 0 ) + { + trims |= 0x80 ; + } + + return trims ; +} + +#endif + +#ifdef PCBSKY +extern "C" uint32_t initReadTrims( void ) ; + +uint32_t initReadTrims( void ) +{ + PMC->PMC_PCER0 = (1<AHB1ENR |= RCC_AHB1ENR_GPIOEEN ; // Enable portE clock + configure_pins( 0x1C00, PIN_INPUT | PIN_PULLUP | PIN_PORTE ) ; + configure_pins( 0x008C, PIN_INPUT | PIN_PULLUP | PIN_PORTD ) ; +} + +// Reqd. bit 6 LEFT, 5 RIGHT, 4 UP, 3 DOWN 2 EXIT 1 MENU +uint32_t read_keys() +{ + register uint32_t x ; + register uint32_t y ; + + x = GPIOD->IDR ; // 7 MENU, 3 PAGE(UP), 2 EXIT + + y = 0 ; + if ( x & PIN_BUTTON_MENU ) + { + y |= 0x02 << KEY_MENU ; // up +// y |= 0x02 << KEY_MENU ; // MENU + } + if ( x & PIN_BUTTON_PAGE ) + { + y |= 0x02 << KEY_PAGE ; // LEFT + } + if ( x & PIN_BUTTON_EXIT ) + { + y |= 0x02 << KEY_EXIT ; // DOWN +// y |= 0x02 << KEY_EXIT ; // EXIT + } + + x = GPIOE->IDR ; // 10 RIGHT(+), 11 LEFT(-), 12 ENT(DOWN) + if ( x & PIN_BUTTON_PLUS ) + { + y |= 0x02 << KEY_PLUS ; // MENU +// y |= 0x02 << KEY_UP ; // up + } + if ( x & PIN_BUTTON_MINUS ) + { + y |= 0x02 << KEY_MINUS ; // RIGHT +// y |= 0x02 << KEY_DOWN ; // DOWN + } + if ( x & PIN_BUTTON_ENTER ) + { + y |= 0x02 << KEY_ENTER ; // EXIT +// y |= 0x02 << KEY_RIGHT ; // RIGHT + } + return y ; +} + +// +void setup_switches() +{ + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ; // Enable portA clock + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN ; // Enable portB clock + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOEEN ; // Enable portE clock + configure_pins( 0x0020, PIN_INPUT | PIN_PULLUP | PIN_PORTA ) ; + configure_pins( 0x003A, PIN_INPUT | PIN_PULLUP | PIN_PORTB ) ; + configure_pins( 0xE307, PIN_INPUT | PIN_PULLUP | PIN_PORTE ) ; + +} + +#endif // PCBX9D + diff --git a/radio/bootloader/makefile b/radio/bootloader/makefile new file mode 100644 index 000000000..bfcfe11aa --- /dev/null +++ b/radio/bootloader/makefile @@ -0,0 +1,378 @@ +# +# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! +# +############################################################################################## +# +# On command line: +# +# make all = Create project +# +# make clean = Clean project files. +# +# To rebuild project do "make clean" and "make all". +# + +############################################################################################## +# Start of default section +# + +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CP = $(TRGT)objcopy +CLSS = $(TRGT)objdump +AS = $(TRGT)as +#gcc -x assembler-with-cpp +BIN = $(CP) -O ihex +BINX = $(CP) -O binary + +OBJDIR = obj + +MCU = cortex-m3 + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +MEMORIES = sram + +EXT = STD + +# +# End of default section +############################################################################################## + +############################################################################################## +# Start of user section +# + +# +# Define project name and Ram/Flash mode here +PROJECT = bootloader + +ifeq ($(PCB), TARANIS) +RUN_FROM_FLASH = 0 + else + ifeq ($(PCB), X9D) + RUN_FROM_FLASH = 0 + else + RUN_FROM_FLASH = 1 + endif +endif + +EXTRAINCDIRS = + +# +# Define linker script file here +# +ifeq ($(RUN_FROM_FLASH), 1) + ifeq ($(REVX), 1) + LDSCRIPT = sam3s8c_boot.ld + FULL_PRJ = $(PROJECT)_flash8 + EXTRAINCDIRS += include +# EXTRAINCDIRS += ../ + else + LDSCRIPT = sam3s4c_boot.ld + FULL_PRJ = $(PROJECT)_flash4 + EXTRAINCDIRS += include +# EXTRAINCDIRS += ../ + endif + TRGT = arm-none-eabi- + CPPDEFS += -DPCBSKY + UDEFS = -Dat91sam3s8 +else + ifeq ($(PCB), X9D) + ARCH = ARM + LDSCRIPT = stm32_ramBoot.ld + TRGT = arm-none-eabi- + CPPDEFS += -DHSE_VALUE=12000000 + CPPDEFS += -DPCBX9D + FULL_PRJ = $(PROJECT)_ramBoot + EXTRAINCDIRS += include +# EXTRAINCDIRS += ../x9d + else + ifeq ($(PCB), TARANIS) + ARCH = ARM + LDSCRIPT = stm32_ramBoot.ld + TRGT = arm-none-eabi- + CPPDEFS += -DHSE_VALUE=12000000 + CPPDEFS += -DPCBX9D + CPPDEFS += -DPCBTARANIS + FULL_PRJ = $(PROJECT)_ramBoot + EXTRAINCDIRS += include +# EXTRAINCDIRS += ../targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include + endif + endif +endif + + + +# List all user C define here, like -D_DEBUG=1 + +# Define ASM defines here +UADEFS = + +ifeq ($(PCB), TARANIS) +SRC = system_stm32f2xx.c \ + stm32f2xx_rcc.c \ + stm32f2xx_gpio.c \ + stm32f2xx_spi.c \ + misc.c \ + ccsbcs.c \ + usb/usb_core.c \ + usb/usb_dcd.c \ + usb/usb_dcd_int.c \ + usb/usbd_core.c \ + usb/usbd_ioreq.c \ + usb/usbd_req.c \ + usb/usbd_msc_data.c \ + usb/usbd_msc_scsi.c \ + usb/usbd_msc_bot.c \ + usb/usbd_msc_core.c \ + usb/usbd_desc.c \ + usb/usb_bsp.c + +CPPSRC = aspi.cpp \ + lcd_driver.cpp \ + driversboot.cpp \ + logicioboot.cpp \ + ff.cpp \ + x9ddiskio.cpp \ + usbd_usr.cpp \ + usbd_storage_msd.cpp \ + i2c_ee.cpp \ + lcdboot.cpp \ + power.cpp \ + boot.cpp + +# List ASM source files here +ASRC = startup_stm32f2xx.s + +else + + +ifeq ($(PCB), X9D) +SRC = system_stm32f2xx.c \ + stm32f2xx_rcc.c \ + stm32f2xx_gpio.c \ + stm32f2xx_spi.c \ + misc.c \ + usb/usb_core.c \ + usb/usb_dcd.c \ + usb/usb_dcd_int.c \ + usb/usbd_core.c \ + usb/usbd_ioreq.c \ + usb/usbd_req.c \ + usb/usbd_msc_data.c \ + usb/usbd_msc_scsi.c \ + usb/usbd_msc_bot.c \ + usb/usbd_msc_core.c \ + usb/usbd_desc.c \ + usb/usb_bsp.c + +CPPSRC = lcdboot.cpp \ + ff.cpp \ + aspi.cpp \ + x9ddiskio.cpp \ + lcd_driver.cpp \ + i2c_ee.cpp \ + driversboot.cpp \ + logicioboot.cpp \ + ff_lfn.cpp \ + usbd_usr.cpp \ + usbd_storage_msd.cpp \ + power.cpp \ + boot.cpp + + +# List ASM source files here +ASRC = x9d/startup_stm32f2xx.s + +else + +# List C source files here +SRC = core_cm3.c \ + board_lowlevel.c \ + crt.c \ + usb/device/core/USBD_UDP.c usb/device/core/USBDDriver.c usb/device/core/USBDCallbacks.c \ + usb/device/massstorage/MSDDriver.c usb/device/massstorage/MSDDStateMachine.c \ + usb/device/massstorage/MSDLun.c usb/device/massstorage/MSDDriverDescriptors.c usb/device/massstorage/SBCMethods.c \ + usb/common/core/USBEndpointDescriptor.c usb/common/core/USBGenericRequest.c \ + usb/common/core/USBFeatureRequest.c usb/common/core/USBInterfaceRequest.c usb/common/core/USBGetDescriptorRequest.c \ + usb/common/core/USBSetAddressRequest.c usb/common/core/USBSetConfigurationRequest.c \ + usb/common/core/USBConfigurationDescriptor.c usb/common/core/USBGenericDescriptor.c \ + MEDSdcard.c \ + vectors_sam3s.c + +CPPSRC = lcdboot.cpp \ + ff.cpp \ + diskio.cpp \ + driversboot.cpp \ + logicioboot.cpp \ + sdcard_driver.cpp \ + massstorage.cpp \ + bootsamEeprom.cpp \ + ff_lfn.cpp \ + power.cpp \ + boot.cpp + +# List ASM source files here +ASRC = + +endif +endif + +# List all user directories here +UINCDIR = ./inc +# \ +# ./cmsis/core \ +# ./cmsis/device + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# Define optimisation level here +OPT = -Os + +# +# End of user defines +############################################################################################## + + +VPATH = $(DIRS) + +INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) +LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) + +ifeq ($(RUN_FROM_FLASH), 0) +DEFS = $(DDEFS) $(UDEFS) -DRUN_FROM_FLASH=0 +else +DEFS = $(DDEFS) $(UDEFS) -DRUN_FROM_FLASH=1 +endif + +ADEFS = $(DADEFS) $(UADEFS) + +AXOBJS = $(ASRC:%.s=%.o) +CXOBJS = $(SRC:%.c=%.o) +CPPXOBJS = $(CPPSRC:%.cpp=%.o) + +LIBS = $(DLIBS) $(ULIBS) +MCFLAGS = -mcpu=$(MCU) + +#ASFLAGS = $(MCFLAGS) -g -gdwarf-2 -Wa,-amhls=$(OBJDIR)/$(notdir $(<:.s=.lst)) $(ADEFS) +CPFLAGS = $(MCFLAGS) $(OPT) -gdwarf-2 -mthumb -fomit-frame-pointer -Wall -Wstrict-prototypes -fverbose-asm $(DEFS) +LDFLAGS = $(MCFLAGS) -mthumb -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(FULL_PRJ).map,--cref,--no-warn-mismatch $(LIBDIR) +CPPFLAGS = $(MCFLAGS) $(OPT) -gdwarf-2 -mthumb -fomit-frame-pointer -Wall -fverbose-asm $(DEFS) + +CPPFLAGS += $(CPPDEFS) +CPFLAGS += $(CPPDEFS) +CPFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) + +AOBJS = $(patsubst %,$(OBJDIR)/%,$(notdir $(AXOBJS) )) +COBJS = $(patsubst %,$(OBJDIR)/%,$(notdir $(CXOBJS) )) +CPPOBJS = $(patsubst %,$(OBJDIR)/%,$(notdir $(CPPXOBJS) )) +DIRS = $(sort $(dir $(AXOBJS) $(CXOBJS) $(CPPXOBJS) ) ) + +# If REVX board +ifeq ($(REVX), 1) + CPPDEFS += -DREVX + EXT_MOD=REVB-X +endif + +CPPDEFS += -DCPUARM + +CPPDEFS += -DREVB + +# If serial Debug required +ifeq ($(DEBUG), 1) + CPPDEFS += -DDEBUG +endif + +CPPDEFS += -DBOOT + +# Generate dependency information +CPFLAGS += -MD -MP -MF .dep/$(@F).d +CPPFLAGS += -MD -MP -MF .dep/$(@F).d +CPPFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) + +# +# makefile rules +# + +all: size_before $(OBJS) $(COBJS) $(CPPOBJS) $(FULL_PRJ).elf $(FULL_PRJ).hex $(FULL_PRJ).lss $(FULL_PRJ).bin size + +#begin: +# @echo $(AXOBJS) $(CXOBJS) $(CPPXOBJS) +# @echo +# @echo $(OBJS) $(COBJS) $(CPPOBJS) +# @echo +# @echo $(DIRS) + +size_before: +# arm-none-eabi-size $(FULL_PRJ).elf + @if test -f $(FULL_PRJ).elf; then arm-none-eabi-size $(FULL_PRJ).elf; fi + +size: +# arm-none-eabi-size $(FULL_PRJ).elf + @if test -f $(FULL_PRJ).elf; then arm-none-eabi-size $(FULL_PRJ).elf; fi + +$(CPPOBJS) : $(OBJDIR)/%.o : %.cpp + $(CC) -c $(CPPFLAGS) -fno-exceptions -I . $(INCDIR) $< -o $@ + +$(COBJS) : $(OBJDIR)/%.o : %.c + $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@ + + +$(AOBJS) : $(OBJDIR)/%.o : %.s + $(AS) -c $(ASFLAGS) $< -o $@ + +%elf: $(AOBJS) $(COBJS) $(CPPOBJS) + $(CC) $(AOBJS) $(COBJS) $(CPPOBJS) $(LDFLAGS) $(LIBS) -o $@ + +# Create extended listing file from ELF output file. +%.lss: %.elf + $(CLSS) -h -S $< > $@ + +%hex: %elf + $(BIN) $< $@ + +%bin: %elf + $(BINX) $< $@ + +# $(PROJECT)_flash8 +# $(PROJECT)_flash4 +# $(PROJECT)_ramBootS +# $(PROJECT)_ramBootT + +clean: + -rm -f obj/*.o + -rm -f xobj/*.o + -rm -f robj/*.o + -rm -f tobj/*.o + -rm -f *.elf + -rm -f *.map + -rm -f *.hex + -rm -f *.bin + -rm -f *.lss + -rm -fR .dep + + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/radio/bootloader/massstorage.cpp b/radio/bootloader/massstorage.cpp new file mode 100644 index 000000000..92d80ddf3 --- /dev/null +++ b/radio/bootloader/massstorage.cpp @@ -0,0 +1,233 @@ +/* + * Authors (alphabetical order) + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * open9x is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "radio.h" +#include "board.h" +//#include "debug.h" +//#include "Audio.h" + +//#ifndef SIMU +//#include "CoOS.h" +//#endif + +#ifndef SIMU + +extern "C" { +#include "MSDDriver.h" +extern unsigned char MEDSdcard_Initialize(Media *media, unsigned char mciID); +} + +/** Size of one block in bytes. */ +#define BLOCK_SIZE 512 + +/** Size of the MSD IO buffer in bytes (6K, more the better). */ +#define MSD_BUFFER_SIZE (12*BLOCK_SIZE) + +/** LUN read/write buffer. */ +unsigned char msdBuffer[MSD_BUFFER_SIZE]; + +unsigned int msdReadTotal=0, msdWriteTotal=0; + +static void ConfigureUsbClock(void) +{ + /* Enable PLLB for USB */ + PMC->CKGR_PLLBR = CKGR_PLLBR_DIVB(1) + | CKGR_PLLBR_MULB(7) + | CKGR_PLLBR_PLLBCOUNT; + while((PMC->PMC_SR & PMC_SR_LOCKB) == 0); // TODO && (timeout++ < CLOCK_TIMEOUT)); + /* USB Clock uses PLLB */ + PMC->PMC_USB = PMC_USB_USBDIV(1) /* /2 */ + | PMC_USB_USBS; /* PLLB */ +} + +/** Maximum number of LUNs which can be defined. */ +#define MAX_LUNS 2 + +/** Media index for different disks */ +#define DRV_SDMMC 0 /** SD card */ +#define DRV_EEPROM 1 /** EEPROM */ + +Media medias[MAX_LUNS]; + + +/*---------------------------------------------------------------------------- + * Local variables + *----------------------------------------------------------------------------*/ + +#ifdef HID + +uint8_t hid_iBuffer[64] ; +uint8_t hid_oBuffer[64] ; + +static void hid_transfer() +{ + uint32_t dwCnt=0 ; + uint32_t dwLen ; + + dwLen = HIDDTransferDriver_Read( hid_iBuffer, 64 ) ; + if ( dwLen ) + { +// printf( "Data In(%u):", (unsigned int)dwLen ) ; +// _ShowBuffer( iBuffer, dwLen ) ; + +// bmLEDs = iBuffer[0] ; +// update = 1 ; + } + + dwLen = HIDDTransferDriver_ReadReport( iBuffer, 64 ) ; + if ( dwLen ) + { +// printf( "Report In(%u):", (unsigned int)dwLen ) ; +// _ShowBuffer( iBuffer, dwLen ) ; + +// bmLEDs = iBuffer[0] ; +// update = 1 ; + } + + oBuffer[0] = 0x80 ; + if ( PIO_Get( &pinsButtons[PUSHBUTTON_BP1]) == 0 ) + { + oBuffer[0] |= 0x01 ; + } + if ( PIO_Get( &pinsButtons[PUSHBUTTON_BP2] ) == 0 ) + { + oBuffer[0] |= 0x02 ; + } + + sprintf( (char*)&oBuffer[5], ":%04x:%05u!", (unsigned int)dwCnt, (unsigned int)dwCnt ) ; + oBuffer[1] = (uint8_t)(dwCnt) ; + oBuffer[2] = (uint8_t)(dwCnt >> 8) ; + oBuffer[3] = (uint8_t)(dwCnt >> 16) ; + oBuffer[4] = (uint8_t)(dwCnt >> 24) ; + if ( USBD_STATUS_SUCCESS == HIDDTransferDriver_Write( oBuffer, 64, 0, 0 ) ) + { + dwCnt ++ ; + } +} + +#endif + + + + +/** Device LUNs. */ +MSDLun luns[MAX_LUNS]; + +static void MSDCallbacks_Data( unsigned char flowDirection, unsigned int dataLength, + unsigned int fifoNullCount, unsigned int fifoFullCount ) +{ +#if 0 + if (flowDirection) + msdReadTotal += dataLength; + else + msdWriteTotal += dataLength; +#endif +} + +extern "C" unsigned char EEPROM_Initialize(Media *media, unsigned char mciID) ; +extern uint32_t sd_card_ready( void ) ; + +void usbMassStorage() +{ + static bool initialized = false ; + static bool active = false ; + + if ( PIOC->PIO_PDSR & 0x02000000 ) + { + // TRACE_DEBUG("usbMassStorage\n\r"); + + if (!initialized) + { + ConfigureUsbClock(); + /* Initialize LUN */ + MEDSdcard_Initialize(&(medias[DRV_SDMMC]), 0); + EEPROM_Initialize(&(medias[DRV_EEPROM]), 0); + LUN_Init(&(luns[DRV_SDMMC]), sd_card_ready() ? &(medias[DRV_SDMMC]) : 0 , + msdBuffer, MSD_BUFFER_SIZE, + 0, 0, 0, 0, + MSDCallbacks_Data); + + LUN_Init(&(luns[DRV_EEPROM]), &(medias[DRV_EEPROM]), + msdBuffer, MSD_BUFFER_SIZE, + 0, 0, 0, 0, + MSDCallbacks_Data); + + /* BOT driver initialization */ + MSDDriver_Initialize( luns, 2 ) ; + // VBus_Configure(); + USBD_Connect(); + initialized = true; + } + + if ( active == false ) + { +#ifndef BOOT + CoSchedLock() ; + if ( Voice.VoiceLock == 0 ) + { + Voice.VoiceLock = 1 ; +#endif + active = true ; +#ifndef BOOT + } + CoSchedUnlock() ; +#endif + } + if ( active ) + { + /* Mass storage state machine */ + for (uint8_t i=0; i<50; i++) + { +#ifdef HID + hid_transfer() ; +#endif + MSDDriver_StateMachine() ; + } + } + } + else + { + if ( active ) + { + active = false ; +#ifndef BOOT + Voice.VoiceLock = 0 ; +#endif + } + + msdReadTotal = 0; + msdWriteTotal = 0; + } +} + +#endif diff --git a/radio/bootloader/misc.c b/radio/bootloader/misc.c new file mode 100644 index 000000000..7d011629b --- /dev/null +++ b/radio/bootloader/misc.c @@ -0,0 +1,249 @@ +/** + ****************************************************************************** + * @file misc.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides all the miscellaneous firmware functions (add-on + * to CMSIS functions). + * + * @verbatim + * + * =================================================================== + * How to configure Interrupts using driver + * =================================================================== + * + * This section provide functions allowing to configure the NVIC interrupts (IRQ). + * The Cortex-M3 exceptions are managed by CMSIS functions. + * + * 1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig() + * function according to the following table. + + * The table below gives the allowed values of the pre-emption priority and subpriority according + * to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function + * ========================================================================================================================== + * NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description + * ========================================================================================================================== + * NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority + * | | | 4 bits for subpriority + * -------------------------------------------------------------------------------------------------------------------------- + * NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority + * | | | 3 bits for subpriority + * -------------------------------------------------------------------------------------------------------------------------- + * NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority + * | | | 2 bits for subpriority + * -------------------------------------------------------------------------------------------------------------------------- + * NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority + * | | | 1 bits for subpriority + * -------------------------------------------------------------------------------------------------------------------------- + * NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority + * | | | 0 bits for subpriority + * ========================================================================================================================== + * + * 2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init() + * + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * + * @note IRQ priority order (sorted by highest to lowest priority): + * - Lowest pre-emption priority + * - Lowest subpriority + * - Lowest hardware priority (IRQ number) + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "misc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup MISC + * @brief MISC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup MISC_Private_Functions + * @{ + */ + +/** + * @brief Configures the priority grouping: pre-emption priority and subpriority. + * @param NVIC_PriorityGroup: specifies the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority + * 4 bits for subpriority + * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority + * 3 bits for subpriority + * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority + * 2 bits for subpriority + * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority + * 1 bits for subpriority + * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority + * 0 bits for subpriority + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ + SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; +} + +/** + * @brief Initializes the NVIC peripheral according to the specified + * parameters in the NVIC_InitStruct. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains + * the configuration information for the specified NVIC peripheral. + * @retval None + */ +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) +{ + uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); + assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); + + if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + /* Compute the Corresponding IRQ Priority --------------------------------*/ + tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; + tmppre = (0x4 - tmppriority); + tmpsub = tmpsub >> tmppriority; + + tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; + tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub); + + tmppriority = tmppriority << 0x04; + + NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; + + /* Enable the Selected IRQ Channels --------------------------------------*/ + NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } + else + { + /* Disable the Selected IRQ Channels -------------------------------------*/ + NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } +} + +/** + * @brief Sets the vector table location and Offset. + * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. + * This parameter can be one of the following values: + * @arg NVIC_VectTab_RAM: Vector Table in internal SRAM. + * @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH. + * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200. + * @retval None + */ +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) +{ + /* Check the parameters */ + assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); + assert_param(IS_NVIC_OFFSET(Offset)); + + SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); +} + +/** + * @brief Selects the condition for the system to enter low power mode. + * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. + * This parameter can be one of the following values: + * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend. + * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request. + * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit. + * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_NVIC_LP(LowPowerMode)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + SCB->SCR |= LowPowerMode; + } + else + { + SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); + } +} + +/** + * @brief Configures the SysTick clock source. + * @param SysTick_CLKSource: specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); + if (SysTick_CLKSource == SysTick_CLKSource_HCLK) + { + SysTick->CTRL |= SysTick_CLKSource_HCLK; + } + else + { + SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/power.cpp b/radio/bootloader/power.cpp new file mode 100644 index 000000000..9d3ef80ef --- /dev/null +++ b/radio/bootloader/power.cpp @@ -0,0 +1,117 @@ +/* + * Authors (alphabetical order) + * - Andre Bernet + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * open9x is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#ifdef PCBSKY +#include "AT91SAM3S4.h" +#endif + + +#ifdef PCBX9D +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_rcc.h" +#include "hal.h" +#endif + +#include "radio.h" +#include "logicio.h" + +#ifdef PCBSKY + + +void init_soft_power() +{ + // Configure RF_power (PC17) + configure_pins( PIO_PC17, PIN_ENABLE | PIN_INPUT | PIN_PORTC | PIN_NO_PULLUP | PIN_PULLDOWN ) ; + + configure_pins( PIO_PA8, PIN_ENABLE | PIN_INPUT | PIN_PORTA | PIN_PULLUP ) ; +} + + +// Returns zero if power is switched off +// 1 if power switch is on +// 2 if power switch off, trainer power on +uint32_t check_soft_power() +{ + if ( PIOC->PIO_PDSR & PIO_PC17 ) // Power on + { + return POWER_ON ; + } + return POWER_OFF ; +} + + +// turn off soft power +void soft_power_off() +{ + configure_pins( PIO_PA8, PIN_ENABLE | PIN_OUTPUT | PIN_LOW | PIN_PORTA | PIN_NO_PULLUP ) ; +} + +#endif + +#ifdef PCBX9D + +void soft_power_off() +{ + GPIO_ResetBits(GPIOPWR,PIN_MCU_PWR); +} + +uint32_t check_soft_power() +{ + if (GPIO_ReadInputDataBit(GPIOPWR, PIN_PWR_STATUS) == Bit_RESET) + return POWER_ON; + else + return POWER_OFF; +} + +void init_soft_power() +{ + RCC->AHB1ENR |= RCC_AHB1ENR_GPIODEN ; // Enable portD clock + GPIO_ResetBits(GPIOPWR, PIN_INT_RF_PWR | PIN_EXT_RF_PWR); + + /* GPIO Configuration*/ + configure_pins( PIN_INT_RF_PWR | PIN_EXT_RF_PWR | PIN_MCU_PWR, PIN_OUTPUT | PIN_PUSHPULL | PIN_OS25 | PIN_PORTD ) ; + + configure_pins( PIN_PWR_STATUS, PIN_INPUT | PIN_PULLUP | PIN_PORTD ) ; + + configure_pins( PIN_TRNDET, PIN_INPUT | PIN_PULLUP | PIN_PORTA ) ; + + // Soft power ON + + GPIO_SetBits(GPIOPWR,PIN_MCU_PWR); + +} + +#endif + diff --git a/radio/bootloader/sam3s4c_boot.ld b/radio/bootloader/sam3s4c_boot.ld new file mode 100644 index 000000000..ffda73521 --- /dev/null +++ b/radio/bootloader/sam3s4c_boot.ld @@ -0,0 +1,144 @@ +/**************************************************************************** +* Copyright (c) 2011 by Michael Fischer. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. Neither the name of the author nor the names of its contributors may +* be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +* SUCH DAMAGE. +* +***************************************************************************** +* History: +* +* 22.05.2011 mifi First Version +****************************************************************************/ + + +/* + * In this linker script there is no heap available. + * The stack start at the end of the ram segment. + */ + + +/* + * Take a look in the "The GNU linker" manual, here you get + * the following information about the "MEMORY": + * + * "The MEMORY command describes the location and size of + * blocks of memory in the target." + */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00400000, LENGTH = 256K + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 48K +} + + +/* + * And the "SECTION" is used for: + * + * "The SECTIONS command tells the linker how to map input + * sections into output sections, and how to place the output + * sections in memory. + */ +SECTIONS +{ + + /* + * The ".text" section is used for the code, and + * read only (.rodata) data. Even the vectors (.vectors) + * MUST be saved at the start of this section. + */ + .text : + { + _stext = .; /* Provide the name for the start of this section */ + + CREATE_OBJECT_SYMBOLS + KEEP(*(.vectors)) + + *(.text) + *(.text.*) + + . = ALIGN(4); /* Align the start of the exidx part */ + *(.ARM.exidx) + *(.ARM.exidx.*) + + . = ALIGN(4); /* Align the start of the rodata part */ + *(.rodata) + *(.rodata.*) + + . = ALIGN(4); /* Align the end of the section */ + } > FLASH + _etext = .; /* Provide the name for the end of this section */ + + + /* + * The ".data" section is used for initialized data + * and for functions (.fastrun) which should be copied + * from flash to ram. This functions will later be + * executed from ram instead of flash. + */ + .data : AT (_etext) + { + . = ALIGN(4); /* Align the start of the section */ + _sdata = .; /* Provide the name for the start of this section */ + + *(.data) + *(.data.*) + + . = ALIGN(4); /* Align the start of the fastrun part */ + *(.fastrun) + *(.fastrun.*) + + . = ALIGN(4); /* Align the end of the section */ + } > RAM + _edata = .; /* Provide the name for the end of this section */ + + + /* + * The ".bss" section is used for uninitialized data. + * This section will be cleared by the startup code. + */ + .bss : + { + . = ALIGN(4); /* Align the start of the section */ + _sbss = .; /* Provide the name for the start of this section */ + + *(.bss) + *(.bss.*) + + . = ALIGN(4); /* Align the end of the section */ + } > RAM = 0 + _ebss = .; /* Provide the name for the end of this section */ + + + /* + * The ".stack" section is our stack. + * Here this section starts at the end of the ram segment. + */ + _estack = ORIGIN(RAM) + LENGTH(RAM); + +} + +/*** EOF **/ + diff --git a/radio/bootloader/sam3s8c_boot.ld b/radio/bootloader/sam3s8c_boot.ld new file mode 100644 index 000000000..1a8584c77 --- /dev/null +++ b/radio/bootloader/sam3s8c_boot.ld @@ -0,0 +1,144 @@ +/**************************************************************************** +* Copyright (c) 2011 by Michael Fischer. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. Neither the name of the author nor the names of its contributors may +* be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +* SUCH DAMAGE. +* +***************************************************************************** +* History: +* +* 22.05.2011 mifi First Version +****************************************************************************/ + + +/* + * In this linker script there is no heap available. + * The stack start at the end of the ram segment. + */ + + +/* + * Take a look in the "The GNU linker" manual, here you get + * the following information about the "MEMORY": + * + * "The MEMORY command describes the location and size of + * blocks of memory in the target." + */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00400000, LENGTH = 512K + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 48K +} + + +/* + * And the "SECTION" is used for: + * + * "The SECTIONS command tells the linker how to map input + * sections into output sections, and how to place the output + * sections in memory. + */ +SECTIONS +{ + + /* + * The ".text" section is used for the code, and + * read only (.rodata) data. Even the vectors (.vectors) + * MUST be saved at the start of this section. + */ + .text : + { + _stext = .; /* Provide the name for the start of this section */ + + CREATE_OBJECT_SYMBOLS + KEEP(*(.vectors)) + + *(.text) + *(.text.*) + + . = ALIGN(4); /* Align the start of the exidx part */ + *(.ARM.exidx) + *(.ARM.exidx.*) + + . = ALIGN(4); /* Align the start of the rodata part */ + *(.rodata) + *(.rodata.*) + + . = ALIGN(4); /* Align the end of the section */ + } > FLASH + _etext = .; /* Provide the name for the end of this section */ + + + /* + * The ".data" section is used for initialized data + * and for functions (.fastrun) which should be copied + * from flash to ram. This functions will later be + * executed from ram instead of flash. + */ + .data : AT (_etext) + { + . = ALIGN(4); /* Align the start of the section */ + _sdata = .; /* Provide the name for the start of this section */ + + *(.data) + *(.data.*) + + . = ALIGN(4); /* Align the start of the fastrun part */ + *(.fastrun) + *(.fastrun.*) + + . = ALIGN(4); /* Align the end of the section */ + } > RAM + _edata = .; /* Provide the name for the end of this section */ + + + /* + * The ".bss" section is used for uninitialized data. + * This section will be cleared by the startup code. + */ + .bss : + { + . = ALIGN(4); /* Align the start of the section */ + _sbss = .; /* Provide the name for the start of this section */ + + *(.bss) + *(.bss.*) + + . = ALIGN(4); /* Align the end of the section */ + } > RAM = 0 + _ebss = .; /* Provide the name for the end of this section */ + + + /* + * The ".stack" section is our stack. + * Here this section starts at the end of the ram segment. + */ + _estack = ORIGIN(RAM) + LENGTH(RAM); + +} + +/*** EOF **/ + diff --git a/radio/bootloader/sdcard_driver.cpp b/radio/bootloader/sdcard_driver.cpp new file mode 100644 index 000000000..c437a7f8b --- /dev/null +++ b/radio/bootloader/sdcard_driver.cpp @@ -0,0 +1,71 @@ +/* + * Authors (alphabetical order) + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * open9x is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include "diskio.h" +#include "radio.h" +#include "drivers.h" +#include "logicio.h" + +// SD Card routines + +#define MCI_INITIAL_SPEED 400000 + +void init_SDcard() +{ +#ifndef SIMU + configure_pins( 0xFC000000, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_C | PIN_PORTA | PIN_NO_PULLUP ) ; + configure_pins( PIO_PB7, PIN_INPUT | PIN_PORTB | PIN_NO_PULLUP | PIN_NO_PULLDOWN ) ; + + unsigned short clkDiv; + Hsmci *pMciHw = HSMCI ; + + /* Enable the MCI peripheral */ + PMC->PMC_PCER0 |= 1 << ID_HSMCI ; // Enable peripheral clock to HSMCI + pMciHw->HSMCI_CR = HSMCI_CR_SWRST; /* Reset the MCI */ + pMciHw->HSMCI_CR = HSMCI_CR_MCIDIS | HSMCI_CR_PWSDIS; /* Disable the MCI */ + pMciHw->HSMCI_IDR = 0xFFFFFFFF; /* Disable all the interrupts */ + pMciHw->HSMCI_DTOR = HSMCI_DTOR_DTOCYC_Msk | HSMCI_DTOR_DTOMUL_Msk ; /* Set the Data Timeout Register */ + pMciHw->HSMCI_CSTOR = HSMCI_CSTOR_CSTOCYC_Msk | HSMCI_CSTOR_CSTOMUL_Msk ; /* CSTOR ? */ + /* Set the Mode Register: 400KHz for MCK = 48MHz (CLKDIV = 58) */ + clkDiv = (Master_frequency / (MCI_INITIAL_SPEED * 2)) - 1; + pMciHw->HSMCI_MR = clkDiv | (7 << 8) ; + + /* Set the SDCard Register 1-bit, slot A */ + pMciHw->HSMCI_SDCR = HSMCI_SDCR_SDCSEL_SLOTA | HSMCI_SDCR_SDCBUS_1 ; + /* Enable the MCI and the Power Saving */ + pMciHw->HSMCI_CR = HSMCI_CR_MCIEN | HSMCI_CR_PWSEN ; + /* Configure MCI */ + pMciHw->HSMCI_CFG = HSMCI_CFG_FIFOMODE | ((1 << 4) & HSMCI_CFG_FERRCTRL); +#endif +} diff --git a/radio/bootloader/startup_stm32f2xx.s b/radio/bootloader/startup_stm32f2xx.s new file mode 100644 index 000000000..320550516 --- /dev/null +++ b/radio/bootloader/startup_stm32f2xx.s @@ -0,0 +1,512 @@ +/** + ****************************************************************************** + * @file startup_stm32f2xx.s + * @author MCD Application Team + * @version V1.1.3 + * @date 05-March-2012 + * @brief STM32F2xx Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the system clock and the external SRAM mounted on + * STM322xG-EVAL board to be used as data memory (optional, + * to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FSMC_IRQHandler /* FSMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word CRYP_IRQHandler /* CRYP crypto */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak CRYP_IRQHandler + .thumb_set CRYP_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/stm32_ramBoot.ld b/radio/bootloader/stm32_ramBoot.ld new file mode 100644 index 000000000..d8a0b2e1f --- /dev/null +++ b/radio/bootloader/stm32_ramBoot.ld @@ -0,0 +1,153 @@ +/* +***************************************************************************** +** +** File : stm32_flashboot.ld +** +** Abstract : Linker script for STM32F205 Device with +** 0.5MByte FLASH, 128KByte SRAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20020000; /* end of 128K SRAM */ + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0; /* required amount of heap */ +_Min_Stack_Size = 0x200; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K + MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >RAM + + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >RAM + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >RAM + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >RAM + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(.fini_array*)) + KEEP (*(SORT(.fini_array.*))) + PROVIDE_HIDDEN (__fini_array_end = .); + } >RAM + + /* used by the startup to initialize data */ + _sidata = .; + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : AT ( _sidata ) + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + PROVIDE ( end = _ebss ); + PROVIDE ( _end = _ebss ); + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(4); + } >RAM + + /* MEMORY_bank1 section, code must be located here explicitly */ + /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */ + .memory_b1_text : + { + *(.mb1text) /* .mb1text sections (code) */ + *(.mb1text*) /* .mb1text* sections (code) */ + *(.mb1rodata) /* read-only data (constants) */ + *(.mb1rodata*) + } >MEMORY_B1 + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/radio/bootloader/stm32f2xx_gpio.c b/radio/bootloader/stm32f2xx_gpio.c new file mode 100644 index 000000000..c53371e3d --- /dev/null +++ b/radio/bootloader/stm32f2xx_gpio.c @@ -0,0 +1,566 @@ +/** + ****************************************************************************** + * @file stm32f2xx_gpio.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the GPIO peripheral: + * - Initialization and Configuration + * - GPIO Read and Write + * - GPIO Alternate functions configuration + * + * @verbatim + * + * =================================================================== + * How to use this driver + * =================================================================== + * 1. Enable the GPIO AHB clock using the following function + * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + * + * 2. Configure the GPIO pin(s) using GPIO_Init() + * Four possible configuration are available for each pin: + * - Input: Floating, Pull-up, Pull-down. + * - Output: Push-Pull (Pull-up, Pull-down or no Pull) + * Open Drain (Pull-up, Pull-down or no Pull). + * In output mode, the speed is configurable: 2 MHz, 25 MHz, + * 50 MHz or 100 MHz. + * - Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) + * Open Drain (Pull-up, Pull-down or no Pull). + * - Analog: required mode when a pin is to be used as ADC channel + * or DAC output. + * + * 3- Peripherals alternate function: + * - For ADC and DAC, configure the desired pin in analog mode using + * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN; + * - For other peripherals (TIM, USART...): + * - Connect the pin to the desired peripherals' Alternate + * Function (AF) using GPIO_PinAFConfig() function + * - Configure the desired pin in alternate function mode using + * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + * - Select the type, pull-up/pull-down and output speed via + * GPIO_PuPd, GPIO_OType and GPIO_Speed members + * - Call GPIO_Init() function + * + * 4. To get the level of a pin configured in input mode use GPIO_ReadInputDataBit() + * + * 5. To set/reset the level of a pin configured in output mode use + * GPIO_SetBits()/GPIO_ResetBits() + * + * 6. During and just after reset, the alternate functions are not + * active and the GPIO pins are configured in input floating mode + * (except JTAG pins). + * + * 7. The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as + * general-purpose (PC14 and PC15, respectively) when the LSE + * oscillator is off. The LSE has priority over the GPIO function. + * + * 8. The HSE oscillator pins OSC_IN/OSC_OUT can be used as + * general-purpose PH0 and PH1, respectively, when the HSE + * oscillator is off. The HSE has priority over the GPIO function. + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup GPIO + * @brief GPIO driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup GPIO_Private_Functions + * @{ + */ + +/** @defgroup GPIO_Group1 Initialization and Configuration + * @brief Initialization and Configuration + * +@verbatim + =============================================================================== + Initialization and Configuration + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the GPIOx peripheral registers to their default reset values. + * @note By default, The GPIO pins are configured in input floating mode (except JTAG pins). + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @retval None + */ +void GPIO_DeInit(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + if (GPIOx == GPIOA) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE); + } + else if (GPIOx == GPIOB) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE); + } + else if (GPIOx == GPIOC) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE); + } + else if (GPIOx == GPIOD) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE); + } + else if (GPIOx == GPIOE) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE); + } + else if (GPIOx == GPIOF) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE); + } + else if (GPIOx == GPIOG) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE); + } + else if (GPIOx == GPIOH) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE); + } + else + { + if (GPIOx == GPIOI) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE); + } + } +} + +/** + * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); + assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); + assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); + + /* -------------------------Configure the port pins---------------- */ + /*-- GPIO Mode Configuration --*/ + for (pinpos = 0x00; pinpos < 0x10; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + /* Get the port pins position */ + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + + if (currentpin == pos) + { + GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2)); + GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2)); + + if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF)) + { + /* Check Speed mode parameters */ + assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); + + /* Speed mode configuration */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2)); + GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2)); + + /* Check Output mode parameters */ + assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType)); + + /* Output mode configuration*/ + GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ; + GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos)); + } + + /* Pull-up Pull down resistor configuration*/ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2)); + GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2)); + } + } +} + +/** + * @brief Fills each GPIO_InitStruct member with its default value. + * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized. + * @retval None + */ +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStruct->GPIO_OType = GPIO_OType_PP; + GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL; +} + +/** + * @brief Locks GPIO Pins configuration registers. + * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + * @note The configuration of the locked GPIO pins can no longer be modified + * until the next reset. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be locked. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = 0x00010000; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + tmp |= GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Reset LCKK bit */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; +} + +/** + * @} + */ + +/** @defgroup GPIO_Group2 GPIO Read and Write + * @brief GPIO Read and Write + * +@verbatim + =============================================================================== + GPIO Read and Write + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Reads the specified input port pin. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @retval The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO input data port. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @retval GPIO input data port value. + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->IDR); +} + +/** + * @brief Reads the specified output data port bit. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @retval The output port pin value. + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO output data port. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @retval GPIO output data port value. + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->ODR); +} + +/** + * @brief Sets the selected data port bits. + * @note This functions uses GPIOx_BSRR register to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BSRRL = GPIO_Pin; +} + +/** + * @brief Clears the selected data port bits. + * @note This functions uses GPIOx_BSRR register to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BSRRH = GPIO_Pin; +} + +/** + * @brief Sets or clears the selected data port bit. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..15). + * @param BitVal: specifies the value to be written to the selected bit. + * This parameter can be one of the BitAction enum values: + * @arg Bit_RESET: to clear the port pin + * @arg Bit_SET: to set the port pin + * @retval None + */ +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_BIT_ACTION(BitVal)); + + if (BitVal != Bit_RESET) + { + GPIOx->BSRRL = GPIO_Pin; + } + else + { + GPIOx->BSRRH = GPIO_Pin ; + } +} + +/** + * @brief Writes data to the specified GPIO data port. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param PortVal: specifies the value to be written to the port output data register. + * @retval None + */ +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + GPIOx->ODR = PortVal; +} + +/** + * @brief Toggles the specified GPIO pins.. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_Pin: Specifies the pins to be toggled. + * @retval None + */ +void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + GPIOx->ODR ^= GPIO_Pin; +} + +/** + * @} + */ + +/** @defgroup GPIO_Group3 GPIO Alternate functions configuration function + * @brief GPIO Alternate functions configuration function + * +@verbatim + =============================================================================== + GPIO Alternate functions configuration function + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Changes the mapping of the specified pin. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_PinSource: specifies the pin for the Alternate function. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * @param GPIO_AFSelection: selects the pin to used as Alternate function. + * This parameter can be one of the following values: + * @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset) + * @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset) + * @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset) + * @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset) + * @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset) + * @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1 + * @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1 + * @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2 + * @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2 + * @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2 + * @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3 + * @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3 + * @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3 + * @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3 + * @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4 + * @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4 + * @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4 + * @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5 + * @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5 + * @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6 + * @arg GPIO_AF_USART1: Connect USART1 pins to AF7 + * @arg GPIO_AF_USART2: Connect USART2 pins to AF7 + * @arg GPIO_AF_USART3: Connect USART3 pins to AF7 + * @arg GPIO_AF_UART4: Connect UART4 pins to AF8 + * @arg GPIO_AF_UART5: Connect UART5 pins to AF8 + * @arg GPIO_AF_USART6: Connect USART6 pins to AF8 + * @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9 + * @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9 + * @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9 + * @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9 + * @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9 + * @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10 + * @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10 + * @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11 + * @arg GPIO_AF_FSMC: Connect FSMC pins to AF12 + * @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12 + * @arg GPIO_AF_SDIO: Connect SDIO pins to AF12 + * @arg GPIO_AF_DCMI: Connect DCMI pins to AF13 + * @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15 + * @retval None + */ +void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF) +{ + uint32_t temp = 0x00; + uint32_t temp_2 = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + assert_param(IS_GPIO_AF(GPIO_AF)); + + temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; + GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; + temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp; + GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/stm32f2xx_rcc.c b/radio/bootloader/stm32f2xx_rcc.c new file mode 100644 index 000000000..0376f7f55 --- /dev/null +++ b/radio/bootloader/stm32f2xx_rcc.c @@ -0,0 +1,1817 @@ +/** + ****************************************************************************** + * @file stm32f2xx_rcc.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Reset and clock control (RCC) peripheral: + * - Internal/external clocks, PLL, CSS and MCO configuration + * - System, AHB and APB busses clocks configuration + * - Peripheral clocks configuration + * - Interrupts and flags management + * + * @verbatim + * + * =================================================================== + * RCC specific features + * =================================================================== + * + * After reset the device is running from Internal High Speed oscillator + * (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache + * and I-Cache are disabled, and all peripherals are off except internal + * SRAM, Flash and JTAG. + * - There is no prescaler on High speed (AHB) and Low speed (APB) busses; + * all peripherals mapped on these busses are running at HSI speed. + * - The clock for all peripherals is switched off, except the SRAM and FLASH. + * - All GPIOs are in input floating state, except the JTAG pins which + * are assigned to be used for debug purpose. + * + * Once the device started from reset, the user application has to: + * - Configure the clock source to be used to drive the System clock + * (if the application needs higher frequency/performance) + * - Configure the System clock frequency and Flash settings + * - Configure the AHB and APB busses prescalers + * - Enable the clock for the peripheral(s) to be used + * - Configure the clock source(s) for peripherals which clocks are not + * derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup RCC + * @brief RCC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ------------ RCC registers bit address in the alias region ----------- */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) +/* --- CR Register ---*/ +/* Alias word address of HSION bit */ +#define CR_OFFSET (RCC_OFFSET + 0x00) +#define HSION_BitNumber 0x00 +#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) +/* Alias word address of CSSON bit */ +#define CSSON_BitNumber 0x13 +#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) +/* Alias word address of PLLON bit */ +#define PLLON_BitNumber 0x18 +#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) +/* Alias word address of PLLI2SON bit */ +#define PLLI2SON_BitNumber 0x1A +#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4)) + +/* --- CFGR Register ---*/ +/* Alias word address of I2SSRC bit */ +#define CFGR_OFFSET (RCC_OFFSET + 0x08) +#define I2SSRC_BitNumber 0x17 +#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4)) + +/* --- BDCR Register ---*/ +/* Alias word address of RTCEN bit */ +#define BDCR_OFFSET (RCC_OFFSET + 0x70) +#define RTCEN_BitNumber 0x0F +#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) +/* Alias word address of BDRST bit */ +#define BDRST_BitNumber 0x10 +#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) +/* --- CSR Register ---*/ +/* Alias word address of LSION bit */ +#define CSR_OFFSET (RCC_OFFSET + 0x74) +#define LSION_BitNumber 0x00 +#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) +/* ---------------------- RCC registers bit mask ------------------------ */ +/* CFGR register bit mask */ +#define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF) +#define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF) + +/* RCC Flag Mask */ +#define FLAG_MASK ((uint8_t)0x1F) + +/* CR register byte 3 (Bits[23:16]) base address */ +#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802) + +/* CIR register byte 2 (Bits[15:8]) base address */ +#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01)) + +/* CIR register byte 3 (Bits[23:16]) base address */ +#define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) + +/* BDCR register base address */ +#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RCC_Private_Functions + * @{ + */ + +/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions + * @brief Internal and external clocks, PLL, CSS and MCO configuration functions + * +@verbatim + =============================================================================== + Internal/external clocks, PLL, CSS and MCO configuration functions + =============================================================================== + + This section provide functions allowing to configure the internal/external clocks, + PLLs, CSS and MCO pins. + + 1. HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + + 2. LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC + clock source. + + 3. HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also as RTC clock source. + + 4. LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + + 5. PLL (clocked by HSI or HSE), featuring two different output clocks: + - The first output is used to generate the high speed system clock (up to 120 MHz) + - The second output is used to generate the clock for the USB OTG FS (48 MHz), + the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). + + 6. PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve + high-quality audio performance on the I2S interface. + + 7. CSS (Clock security system), once enable and if a HSE clock failure occurs + (HSE used directly or through PLL as System clock source), the System clock + is automatically switched to HSI and an interrupt is generated if enabled. + The interrupt is linked to the Cortex-M3 NMI (Non-Maskable Interrupt) + exception vector. + + 8. MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL + clock (through a configurable prescaler) on PA8 pin. + + 9. MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S + clock (through a configurable prescaler) on PC9 pin. + +@endverbatim + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE, PLL and PLLI2S OFF + * - AHB, APB1 and APB2 prescaler set to 1. + * - CSS, MCO1 and MCO2 OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @param None + * @retval None + */ +void RCC_DeInit(void) +{ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; +} + +/** + * @brief Configures the External High Speed oscillator (HSE). + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function reset the CSSON bit, so if the Clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param RCC_HSE: specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg RCC_HSE_ON: turn ON the HSE oscillator + * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock + * @retval None + */ +void RCC_HSEConfig(uint8_t RCC_HSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_HSE)); + + /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ + *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF; + + /* Set the new HSE configuration -------------------------------------------*/ + *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE; +} + +/** + * @brief Waits for HSE start-up. + * @note This functions waits on HSERDY flag to be set and return SUCCESS if + * this flag is set, otherwise returns ERROR if the timeout is reached + * and this flag is not set. The timeout value is defined by the constant + * HSE_STARTUP_TIMEOUT in stm32f2xx.h file. You can tailor it depending + * on the HSE crystal used in your application. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: HSE oscillator is stable and ready to use + * - ERROR: HSE oscillator not yet ready + */ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t startupcounter = 0; + ErrorStatus status = ERROR; + FlagStatus hsestatus = RESET; + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + startupcounter++; + } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET)); + + if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param HSICalibrationValue: specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * @retval None + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); + + tmpreg = RCC->CR; + + /* Clear HSITRIM[4:0] bits */ + tmpreg &= ~RCC_CR_HSITRIM; + + /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ + tmpreg |= (uint32_t)HSICalibrationValue << 3; + + /* Store the new value */ + RCC->CR = tmpreg; +} + +/** + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after startup + * from Reset, wakeup from STOP and STANDBY mode, or in case of failure + * of the HSE used directly or indirectly as system clock (if the Clock + * Security System CSS is enabled). + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * @param NewState: new state of the HSI. + * This parameter can be: ENABLE or DISABLE. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + * @retval None + */ +void RCC_HSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the External Low Speed oscillator (LSE). + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param RCC_LSE: specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg RCC_LSE_ON: turn ON the LSE oscillator + * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock + * @retval None + */ +void RCC_LSEConfig(uint8_t RCC_LSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_LSE)); + + /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ + /* Reset LSEON bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; + + /* Reset LSEBYP bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; + + /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ + switch (RCC_LSE) + { + case RCC_LSE_ON: + /* Set LSEON bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; + break; + case RCC_LSE_Bypass: + /* Set LSEBYP and LSEON bits */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; + break; + default: + break; + } +} + +/** + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + * @note LSI can not be disabled if the IWDG is running. + * @param NewState: new state of the LSI. + * This parameter can be: ENABLE or DISABLE. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + * @retval None + */ +void RCC_LSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * + * @param RCC_PLLSource: specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry + * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. + * + * @param PLLM: specifies the division factor for PLL VCO input clock + * This parameter must be a number between 0 and 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * + * @param PLLN: specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between 192 and 432. + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 192 and 432 MHz. + * + * @param PLLP: specifies the division factor for main system clock (SYSCLK) + * This parameter must be a number in the range {2, 4, 6, or 8}. + * @note You have to set the PLLP parameter correctly to not exceed 120 MHz on + * the System clock frequency. + * + * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks + * This parameter must be a number between 4 and 15. + * @note If the USB OTG FS is used in your application, you have to set the + * PLLQ parameter correctly to have 48 MHz clock for the USB. However, + * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work + * correctly. + * + * @retval None + */ +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); + assert_param(IS_RCC_PLLM_VALUE(PLLM)); + assert_param(IS_RCC_PLLN_VALUE(PLLN)); + assert_param(IS_RCC_PLLP_VALUE(PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(PLLQ)); + + RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) | + (PLLQ << 24); +} + +/** + * @brief Enables or disables the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL can not be disabled if it is used as system clock source + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + * @param NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLLCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the PLLI2S clock multiplication and division factors. + * + * @note PLLI2S is available only in Silicon RevisionB and RevisionY. + * @note This function must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * RCC_PLLConfig function ) + * + * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock + * This parameter must be a number between 192 and 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between 192 and 432 MHz. + * + * @param PLLI2SR: specifies the division factor for I2S clock + * This parameter must be a number between 2 and 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + * + * @retval None + */ +void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN)); + assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR)); + + RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28); +} + +/** + * @brief Enables or disables the PLLI2S. + * @note PLLI2S is available only in RevisionB and RevisionY + * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. + * @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLLI2SCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. + * @param NewState: new state of the Clock Security System. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; +} + +/** + * @brief Selects the clock source to output on MCO1 pin(PA8). + * @note PA8 should be configured in alternate function mode. + * @param RCC_MCO1Source: specifies the clock source to output. + * This parameter can be one of the following values: + * @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source + * @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source + * @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source + * @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source + * @param RCC_MCO1Div: specifies the MCO1 prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCO1Div_1: no division applied to MCO1 clock + * @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock + * @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock + * @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock + * @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock + * @retval None + */ +void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source)); + assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div)); + + tmpreg = RCC->CFGR; + + /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */ + tmpreg &= CFGR_MCO1_RESET_MASK; + + /* Select MCO1 clock source and prescaler */ + tmpreg |= RCC_MCO1Source | RCC_MCO1Div; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Selects the clock source to output on MCO2 pin(PC9). + * @note PC9 should be configured in alternate function mode. + * @param RCC_MCO2Source: specifies the clock source to output. + * This parameter can be one of the following values: + * @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source + * @arg RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source + * @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source + * @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source + * @param RCC_MCO2Div: specifies the MCO2 prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCO2Div_1: no division applied to MCO2 clock + * @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock + * @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock + * @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock + * @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock + * @retval None + */ +void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source)); + assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div)); + + tmpreg = RCC->CFGR; + + /* Clear MCO2 and MCO2PRE[2:0] bits */ + tmpreg &= CFGR_MCO2_RESET_MASK; + + /* Select MCO2 clock source and prescaler */ + tmpreg |= RCC_MCO2Source | RCC_MCO2Div; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @} + */ + +/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions + * @brief System, AHB and APB busses clocks configuration functions + * +@verbatim + =============================================================================== + System, AHB and APB busses clocks configuration functions + =============================================================================== + + This section provide functions allowing to configure the System, AHB, APB1 and + APB2 busses clocks. + + 1. Several clock sources can be used to drive the System clock (SYSCLK): HSI, + HSE and PLL. + The AHB clock (HCLK) is derived from System clock through configurable prescaler + and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA, GPIO...). + APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through + configurable prescalers and used to clock the peripherals mapped on these busses. + You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks. + +@note All the peripheral clocks are derived from the System clock (SYSCLK) except: + - I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or + from an external clock mapped on the I2S_CKIN pin. + You have to use RCC_I2SCLKConfig() function to configure this clock. + - RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock + divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd() + functions to configure this clock. + - USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz + to work correctly, while the SDIO require a frequency equal or lower than + to 48. This clock is derived of the main PLL through PLLQ divider. + - IWDG clock which is always the LSI clock. + + 2. The maximum frequency of the SYSCLK and HCLK is 120 MHz, PCLK2 60 MHz and PCLK1 30 MHz. + Depending on the device voltage range, the maximum frequency should be + adapted accordingly: + +-------------------------------------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |---------------------------------------------------------------------| + | | voltage range | voltage range | voltage range | voltage range | + | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | + |---------------|----------------|----------------|-----------------|-----------------| + |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 | + |---------------|----------------|----------------|-----------------|-----------------| + |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 | + |---------------|----------------|----------------|-----------------|-----------------| + |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 | + |---------------|----------------|----------------|-----------------|-----------------| + |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 | + |---------------|----------------|----------------|-----------------|-----------------| + |4WS(5CPU cycle)| NA |96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 | + |---------------|----------------|----------------|-----------------|-----------------| + |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 108 |80 < HCLK <= 96 | + |---------------|----------------|----------------|-----------------|-----------------| + |6WS(7CPU cycle)| NA | NA |108 < HCLK <= 120|96 < HCLK <= 112 | + |---------------|----------------|----------------|-----------------|-----------------| + |7WS(8CPU cycle)| NA | NA | NA |112 < HCLK <= 120| + +-------------------------------------------------------------------------------------+ + + +@endverbatim + * @{ + */ + +/** + * @brief Configures the system clock (SYSCLK). + * @note The HSI is used (enabled by hardware) as system clock source after + * startup from Reset, wake-up from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after startup delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source will be ready. + * You can use RCC_GetSYSCLKSource() function to know which clock is + * currently used as system clock source. + * @param RCC_SYSCLKSource: specifies the clock source used as system clock. + * This parameter can be one of the following values: + * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source + * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source + * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source + * @retval None + */ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); + + tmpreg = RCC->CFGR; + + /* Clear SW[1:0] bits */ + tmpreg &= ~RCC_CFGR_SW; + + /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ + tmpreg |= RCC_SYSCLKSource; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Returns the clock source used as system clock. + * @param None + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * - 0x00: HSI used as system clock + * - 0x04: HSE used as system clock + * - 0x08: PLL used as system clock + */ +uint8_t RCC_GetSYSCLKSource(void) +{ + return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS)); +} + +/** + * @brief Configures the AHB clock (HCLK). + * @note Depending on the device voltage range, the software has to set correctly + * these bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above + * "CPU, AHB and APB busses clocks configuration functions") + * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * This parameter can be one of the following values: + * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK + * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 + * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 + * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 + * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 + * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 + * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 + * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 + * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 + * @retval None + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_HCLK(RCC_SYSCLK)); + + tmpreg = RCC->CFGR; + + /* Clear HPRE[3:0] bits */ + tmpreg &= ~RCC_CFGR_HPRE; + + /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ + tmpreg |= RCC_SYSCLK; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + + +/** + * @brief Configures the Low Speed APB clock (PCLK1). + * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_Div1: APB1 clock = HCLK + * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 + * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 + * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 + * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 + * @retval None + */ +void RCC_PCLK1Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + + tmpreg = RCC->CFGR; + + /* Clear PPRE1[2:0] bits */ + tmpreg &= ~RCC_CFGR_PPRE1; + + /* Set PPRE1[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Configures the High Speed APB clock (PCLK2). + * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_Div1: APB2 clock = HCLK + * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 + * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 + * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 + * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 + * @retval None + */ +void RCC_PCLK2Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + + tmpreg = RCC->CFGR; + + /* Clear PPRE2[2:0] bits */ + tmpreg &= ~RCC_CFGR_PPRE2; + + /* Set PPRE2[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK << 3; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK, + * PCLK1 and PCLK2. + * + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) + * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * @note (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * + * @note This function can be used by the user application to compute the + * baudrate for the communication peripherals or configure other parameters. + * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function + * must be called to update the structure's field. Otherwise, any + * configuration based on this function will be incorrect. + * + * @retval None + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) +{ + uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLP + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + RCC_Clocks->SYSCLK_Frequency = pllvco/pllp; + break; + default: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + } + /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/ + + /* Get HCLK prescaler */ + tmp = RCC->CFGR & RCC_CFGR_HPRE; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + + /* Get PCLK1 prescaler */ + tmp = RCC->CFGR & RCC_CFGR_PPRE1; + tmp = tmp >> 10; + presc = APBAHBPrescTable[tmp]; + /* PCLK1 clock frequency */ + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + + /* Get PCLK2 prescaler */ + tmp = RCC->CFGR & RCC_CFGR_PPRE2; + tmp = tmp >> 13; + presc = APBAHBPrescTable[tmp]; + /* PCLK2 clock frequency */ + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; +} + +/** + * @} + */ + +/** @defgroup RCC_Group3 Peripheral clocks configuration functions + * @brief Peripheral clocks configuration functions + * +@verbatim + =============================================================================== + Peripheral clocks configuration functions + =============================================================================== + + This section provide functions allowing to configure the Peripheral clocks. + + 1. The RTC clock which is derived from the LSI, LSE or HSE clock divided by 2 to 31. + + 2. After restart from Reset or wakeup from STANDBY, all peripherals are off + except internal SRAM, Flash and JTAG. Before to start using a peripheral you + have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd() + , RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions. + + 3. To reset the peripherals configuration (to the default state after device reset) + you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and + RCC_APB1PeriphResetCmd() functions. + + 4. To further reduce power consumption in SLEEP mode the peripheral clocks can + be disabled prior to executing the WFI or WFE instructions. You can do this + using RCC_AHBPeriphClockLPModeCmd(), RCC_APB2PeriphClockLPModeCmd() and + RCC_APB1PeriphClockLPModeCmd() functions. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using PWR_BackupAccessCmd(ENABLE) function before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it can't be changed unless the + * Backup domain is reset using RCC_BackupResetCmd() function, or by + * a Power On Reset (POR). + * + * @param RCC_RTCCLKSource: specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock + * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock + * @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected + * as RTC clock, where x:[2,31] + * + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as + * RTC clock source). + * + * @retval None + */ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); + + if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300) + { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */ + tmpreg = RCC->CFGR; + + /* Clear RTCPRE[4:0] bits */ + tmpreg &= ~RCC_CFGR_RTCPRE; + + /* Configure HSE division factor for RTC clock */ + tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF); + + /* Store the new value */ + RCC->CFGR = tmpreg; + } + + /* Select the RTC clock source */ + RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF); +} + +/** + * @brief Enables or disables the RTC clock. + * @note This function must be used only after the RTC clock source was selected + * using the RCC_RTCCLKConfig function. + * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; +} + +/** + * @brief Forces or releases the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_CSR register. + * @note The BKPSRAM is not affected by this reset. + * @param NewState: new state of the Backup domain reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_BackupResetCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the I2S clock source (I2SCLK). + * + * @note This function must be called before enabling the I2S APB clock. + * @note This function applies only to Silicon RevisionB and RevisionY. + * + * @param RCC_I2SCLKSource: specifies the I2S clock source. + * This parameter can be one of the following values: + * @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source + * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin + * used as I2S clock source + * @retval None + */ +void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource)); + + *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource; +} + +/** + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_AHB1Periph_GPIOA: GPIOA clock + * @arg RCC_AHB1Periph_GPIOB: GPIOB clock + * @arg RCC_AHB1Periph_GPIOC: GPIOC clock + * @arg RCC_AHB1Periph_GPIOD: GPIOD clock + * @arg RCC_AHB1Periph_GPIOE: GPIOE clock + * @arg RCC_AHB1Periph_GPIOF: GPIOF clock + * @arg RCC_AHB1Periph_GPIOG: GPIOG clock + * @arg RCC_AHB1Periph_GPIOG: GPIOG clock + * @arg RCC_AHB1Periph_GPIOI: GPIOI clock + * @arg RCC_AHB1Periph_CRC: CRC clock + * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock + * @arg RCC_AHB1Periph_DMA1: DMA1 clock + * @arg RCC_AHB1Periph_DMA2: DMA2 clock + * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock + * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock + * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock + * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock + * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock + * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph)); + + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->AHB1ENR |= RCC_AHB1Periph; + } + else + { + RCC->AHB1ENR &= ~RCC_AHB1Periph; + } +} + +/** + * @brief Enables or disables the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_AHB2Periph_DCMI: DCMI clock + * @arg RCC_AHB2Periph_CRYP: CRYP clock + * @arg RCC_AHB2Periph_HASH: HASH clock + * @arg RCC_AHB2Periph_RNG: RNG clock + * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB2ENR |= RCC_AHB2Periph; + } + else + { + RCC->AHB2ENR &= ~RCC_AHB2Periph; + } +} + +/** + * @brief Enables or disables the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. + * This parameter must be: RCC_AHB3Periph_FSMC + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB3ENR |= RCC_AHB3Periph; + } + else + { + RCC->AHB3ENR &= ~RCC_AHB3Periph; + } +} + +/** + * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2: TIM2 clock + * @arg RCC_APB1Periph_TIM3: TIM3 clock + * @arg RCC_APB1Periph_TIM4: TIM4 clock + * @arg RCC_APB1Periph_TIM5: TIM5 clock + * @arg RCC_APB1Periph_TIM6: TIM6 clock + * @arg RCC_APB1Periph_TIM7: TIM7 clock + * @arg RCC_APB1Periph_TIM12: TIM12 clock + * @arg RCC_APB1Periph_TIM13: TIM13 clock + * @arg RCC_APB1Periph_TIM14: TIM14 clock + * @arg RCC_APB1Periph_WWDG: WWDG clock + * @arg RCC_APB1Periph_SPI2: SPI2 clock + * @arg RCC_APB1Periph_SPI3: SPI3 clock + * @arg RCC_APB1Periph_USART2: USART2 clock + * @arg RCC_APB1Periph_USART3: USART3 clock + * @arg RCC_APB1Periph_UART4: UART4 clock + * @arg RCC_APB1Periph_UART5: UART5 clock + * @arg RCC_APB1Periph_I2C1: I2C1 clock + * @arg RCC_APB1Periph_I2C2: I2C2 clock + * @arg RCC_APB1Periph_I2C3: I2C3 clock + * @arg RCC_APB1Periph_CAN1: CAN1 clock + * @arg RCC_APB1Periph_CAN2: CAN2 clock + * @arg RCC_APB1Periph_PWR: PWR clock + * @arg RCC_APB1Periph_DAC: DAC clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB1ENR |= RCC_APB1Periph; + } + else + { + RCC->APB1ENR &= ~RCC_APB1Periph; + } +} + +/** + * @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_TIM1: TIM1 clock + * @arg RCC_APB2Periph_TIM8: TIM8 clock + * @arg RCC_APB2Periph_USART1: USART1 clock + * @arg RCC_APB2Periph_USART6: USART6 clock + * @arg RCC_APB2Periph_ADC1: ADC1 clock + * @arg RCC_APB2Periph_ADC2: ADC2 clock + * @arg RCC_APB2Periph_ADC3: ADC3 clock + * @arg RCC_APB2Periph_SDIO: SDIO clock + * @arg RCC_APB2Periph_SPI1: SPI1 clock + * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock + * @arg RCC_APB2Periph_TIM9: TIM9 clock + * @arg RCC_APB2Periph_TIM10: TIM10 clock + * @arg RCC_APB2Periph_TIM11: TIM11 clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB2ENR |= RCC_APB2Periph; + } + else + { + RCC->APB2ENR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Forces or releases AHB1 peripheral reset. + * @param RCC_AHB1Periph: specifies the AHB1 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_AHB1Periph_GPIOA: GPIOA clock + * @arg RCC_AHB1Periph_GPIOB: GPIOB clock + * @arg RCC_AHB1Periph_GPIOC: GPIOC clock + * @arg RCC_AHB1Periph_GPIOD: GPIOD clock + * @arg RCC_AHB1Periph_GPIOE: GPIOE clock + * @arg RCC_AHB1Periph_GPIOF: GPIOF clock + * @arg RCC_AHB1Periph_GPIOG: GPIOG clock + * @arg RCC_AHB1Periph_GPIOG: GPIOG clock + * @arg RCC_AHB1Periph_GPIOI: GPIOI clock + * @arg RCC_AHB1Periph_CRC: CRC clock + * @arg RCC_AHB1Periph_DMA1: DMA1 clock + * @arg RCC_AHB1Periph_DMA2: DMA2 clock + * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock + * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock + * + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB1RSTR |= RCC_AHB1Periph; + } + else + { + RCC->AHB1RSTR &= ~RCC_AHB1Periph; + } +} + +/** + * @brief Forces or releases AHB2 peripheral reset. + * @param RCC_AHB2Periph: specifies the AHB2 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_AHB2Periph_DCMI: DCMI clock + * @arg RCC_AHB2Periph_CRYP: CRYP clock + * @arg RCC_AHB2Periph_HASH: HASH clock + * @arg RCC_AHB2Periph_RNG: RNG clock + * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB2RSTR |= RCC_AHB2Periph; + } + else + { + RCC->AHB2RSTR &= ~RCC_AHB2Periph; + } +} + +/** + * @brief Forces or releases AHB3 peripheral reset. + * @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset. + * This parameter must be: RCC_AHB3Periph_FSMC + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB3RSTR |= RCC_AHB3Periph; + } + else + { + RCC->AHB3RSTR &= ~RCC_AHB3Periph; + } +} + +/** + * @brief Forces or releases Low Speed APB (APB1) peripheral reset. + * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2: TIM2 clock + * @arg RCC_APB1Periph_TIM3: TIM3 clock + * @arg RCC_APB1Periph_TIM4: TIM4 clock + * @arg RCC_APB1Periph_TIM5: TIM5 clock + * @arg RCC_APB1Periph_TIM6: TIM6 clock + * @arg RCC_APB1Periph_TIM7: TIM7 clock + * @arg RCC_APB1Periph_TIM12: TIM12 clock + * @arg RCC_APB1Periph_TIM13: TIM13 clock + * @arg RCC_APB1Periph_TIM14: TIM14 clock + * @arg RCC_APB1Periph_WWDG: WWDG clock + * @arg RCC_APB1Periph_SPI2: SPI2 clock + * @arg RCC_APB1Periph_SPI3: SPI3 clock + * @arg RCC_APB1Periph_USART2: USART2 clock + * @arg RCC_APB1Periph_USART3: USART3 clock + * @arg RCC_APB1Periph_UART4: UART4 clock + * @arg RCC_APB1Periph_UART5: UART5 clock + * @arg RCC_APB1Periph_I2C1: I2C1 clock + * @arg RCC_APB1Periph_I2C2: I2C2 clock + * @arg RCC_APB1Periph_I2C3: I2C3 clock + * @arg RCC_APB1Periph_CAN1: CAN1 clock + * @arg RCC_APB1Periph_CAN2: CAN2 clock + * @arg RCC_APB1Periph_PWR: PWR clock + * @arg RCC_APB1Periph_DAC: DAC clock + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB1RSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1RSTR &= ~RCC_APB1Periph; + } +} + +/** + * @brief Forces or releases High Speed APB (APB2) peripheral reset. + * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_TIM1: TIM1 clock + * @arg RCC_APB2Periph_TIM8: TIM8 clock + * @arg RCC_APB2Periph_USART1: USART1 clock + * @arg RCC_APB2Periph_USART6: USART6 clock + * @arg RCC_APB2Periph_ADC1: ADC1 clock + * @arg RCC_APB2Periph_ADC2: ADC2 clock + * @arg RCC_APB2Periph_ADC3: ADC3 clock + * @arg RCC_APB2Periph_SDIO: SDIO clock + * @arg RCC_APB2Periph_SPI1: SPI1 clock + * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock + * @arg RCC_APB2Periph_TIM9: TIM9 clock + * @arg RCC_APB2Periph_TIM10: TIM10 clock + * @arg RCC_APB2Periph_TIM11: TIM11 clock + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB2RSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2RSTR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_AHB1Periph_GPIOA: GPIOA clock + * @arg RCC_AHB1Periph_GPIOB: GPIOB clock + * @arg RCC_AHB1Periph_GPIOC: GPIOC clock + * @arg RCC_AHB1Periph_GPIOD: GPIOD clock + * @arg RCC_AHB1Periph_GPIOE: GPIOE clock + * @arg RCC_AHB1Periph_GPIOF: GPIOF clock + * @arg RCC_AHB1Periph_GPIOG: GPIOG clock + * @arg RCC_AHB1Periph_GPIOG: GPIOG clock + * @arg RCC_AHB1Periph_GPIOI: GPIOI clock + * @arg RCC_AHB1Periph_CRC: CRC clock + * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock + * @arg RCC_AHB1Periph_DMA1: DMA1 clock + * @arg RCC_AHB1Periph_DMA2: DMA2 clock + * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock + * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock + * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock + * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock + * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock + * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->AHB1LPENR |= RCC_AHB1Periph; + } + else + { + RCC->AHB1LPENR &= ~RCC_AHB1Periph; + } +} + +/** + * @brief Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_AHB2Periph_DCMI: DCMI clock + * @arg RCC_AHB2Periph_CRYP: CRYP clock + * @arg RCC_AHB2Periph_HASH: HASH clock + * @arg RCC_AHB2Periph_RNG: RNG clock + * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->AHB2LPENR |= RCC_AHB2Periph; + } + else + { + RCC->AHB2LPENR &= ~RCC_AHB2Periph; + } +} + +/** + * @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. + * This parameter must be: RCC_AHB3Periph_FSMC + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->AHB3LPENR |= RCC_AHB3Periph; + } + else + { + RCC->AHB3LPENR &= ~RCC_AHB3Periph; + } +} + +/** + * @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2: TIM2 clock + * @arg RCC_APB1Periph_TIM3: TIM3 clock + * @arg RCC_APB1Periph_TIM4: TIM4 clock + * @arg RCC_APB1Periph_TIM5: TIM5 clock + * @arg RCC_APB1Periph_TIM6: TIM6 clock + * @arg RCC_APB1Periph_TIM7: TIM7 clock + * @arg RCC_APB1Periph_TIM12: TIM12 clock + * @arg RCC_APB1Periph_TIM13: TIM13 clock + * @arg RCC_APB1Periph_TIM14: TIM14 clock + * @arg RCC_APB1Periph_WWDG: WWDG clock + * @arg RCC_APB1Periph_SPI2: SPI2 clock + * @arg RCC_APB1Periph_SPI3: SPI3 clock + * @arg RCC_APB1Periph_USART2: USART2 clock + * @arg RCC_APB1Periph_USART3: USART3 clock + * @arg RCC_APB1Periph_UART4: UART4 clock + * @arg RCC_APB1Periph_UART5: UART5 clock + * @arg RCC_APB1Periph_I2C1: I2C1 clock + * @arg RCC_APB1Periph_I2C2: I2C2 clock + * @arg RCC_APB1Periph_I2C3: I2C3 clock + * @arg RCC_APB1Periph_CAN1: CAN1 clock + * @arg RCC_APB1Periph_CAN2: CAN2 clock + * @arg RCC_APB1Periph_PWR: PWR clock + * @arg RCC_APB1Periph_DAC: DAC clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB1LPENR |= RCC_APB1Periph; + } + else + { + RCC->APB1LPENR &= ~RCC_APB1Periph; + } +} + +/** + * @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_TIM1: TIM1 clock + * @arg RCC_APB2Periph_TIM8: TIM8 clock + * @arg RCC_APB2Periph_USART1: USART1 clock + * @arg RCC_APB2Periph_USART6: USART6 clock + * @arg RCC_APB2Periph_ADC1: ADC1 clock + * @arg RCC_APB2Periph_ADC2: ADC2 clock + * @arg RCC_APB2Periph_ADC3: ADC3 clock + * @arg RCC_APB2Periph_SDIO: SDIO clock + * @arg RCC_APB2Periph_SPI1: SPI1 clock + * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock + * @arg RCC_APB2Periph_TIM9: TIM9 clock + * @arg RCC_APB2Periph_TIM10: TIM10 clock + * @arg RCC_APB2Periph_TIM11: TIM11 clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB2LPENR |= RCC_APB2Periph; + } + else + { + RCC->APB2LPENR &= ~RCC_APB2Periph; + } +} + +/** + * @} + */ + +/** @defgroup RCC_Group4 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified RCC interrupts. + * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt + * @param NewState: new state of the specified RCC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_IT(RCC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */ + *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; + } + else + { + /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */ + *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; + } +} + +/** + * @brief Checks whether the specified RCC flag is set or not. + * @param RCC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCC_FLAG_PLLRDY: main PLL clock ready + * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset + * @arg RCC_FLAG_PINRST: Pin reset + * @arg RCC_FLAG_PORRST: POR/PDR reset + * @arg RCC_FLAG_SFTRST: Software reset + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset + * @arg RCC_FLAG_LPWRRST: Low Power reset + * @retval The new state of RCC_FLAG (SET or RESET). + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_FLAG(RCC_FLAG)); + + /* Get the RCC register index */ + tmp = RCC_FLAG >> 5; + if (tmp == 1) /* The flag to check is in CR register */ + { + statusreg = RCC->CR; + } + else if (tmp == 2) /* The flag to check is in BDCR register */ + { + statusreg = RCC->BDCR; + } + else /* The flag to check is in CSR register */ + { + statusreg = RCC->CSR; + } + + /* Get the flag position */ + tmp = RCC_FLAG & FLAG_MASK; + if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the RCC reset flags. + * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + * @param None + * @retval None + */ +void RCC_ClearFlag(void) +{ + /* Set RMVF bit to clear the reset flags */ + RCC->CSR |= RCC_CSR_RMVF; +} + +/** + * @brief Checks whether the specified RCC interrupt has occurred or not. + * @param RCC_IT: specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * @retval The new state of RCC_IT (SET or RESET). + */ +ITStatus RCC_GetITStatus(uint8_t RCC_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_GET_IT(RCC_IT)); + + /* Check the status of the specified RCC interrupt */ + if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the RCC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the RCC's interrupt pending bits. + * @param RCC_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * @retval None + */ +void RCC_ClearITPendingBit(uint8_t RCC_IT) +{ + /* Check the parameters */ + assert_param(IS_RCC_CLEAR_IT(RCC_IT)); + + /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt + pending bits */ + *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/stm32f2xx_spi.c b/radio/bootloader/stm32f2xx_spi.c new file mode 100644 index 000000000..de0bc99a2 --- /dev/null +++ b/radio/bootloader/stm32f2xx_spi.c @@ -0,0 +1,1185 @@ +/** + ****************************************************************************** + * @file stm32f2xx_spi.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Serial peripheral interface (SPI): + * - Initialization and Configuration + * - Data transfers functions + * - Hardware CRC Calculation + * - DMA transfers management + * - Interrupts and flags management + * + * @verbatim + * + * + * =================================================================== + * How to use this driver + * =================================================================== + * 1. Enable peripheral clock using the following functions + * RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) for SPI1 + * RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) for SPI2 + * RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI3. + * + * 2. Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHB1PeriphClockCmd() + * function. + * In I2S mode, if an external clock source is used then the I2S CKIN pin GPIO + * clock should also be enabled. + * + * 3. Peripherals alternate function: + * - Connect the pin to the desired peripherals' Alternate + * Function (AF) using GPIO_PinAFConfig() function + * - Configure the desired pin in alternate function by: + * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + * - Select the type, pull-up/pull-down and output speed via + * GPIO_PuPd, GPIO_OType and GPIO_Speed members + * - Call GPIO_Init() function + * In I2S mode, if an external clock source is used then the I2S CKIN pin + * should be also configured in Alternate function Push-pull pull-up mode. + * + * 4. Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave + * Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() + * function. + * In I2S mode, program the Mode, Standard, Data Format, MCLK Output, Audio + * frequency and Polarity using I2S_Init() function. + * For I2S mode, make sure that either: + * - I2S PLL is configured using the functions RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S), + * RCC_PLLI2SCmd(ENABLE) and RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY). + * or + * - External clock source is configured using the function + * RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly the define constant + * I2S_EXTERNAL_CLOCK_VAL in the stm32f2xx_conf.h file. + * + * 5. Enable the NVIC and the corresponding interrupt using the function + * SPI_ITConfig() if you need to use interrupt mode. + * + * 6. When using the DMA mode + * - Configure the DMA using DMA_Init() function + * - Active the needed channel Request using SPI_I2S_DMACmd() function + * + * 7. Enable the SPI using the SPI_Cmd() function or enable the I2S using + * I2S_Cmd(). + * + * 8. Enable the DMA using the DMA_Cmd() function when using DMA mode. + * + * 9. Optionally, you can enable/configure the following parameters without + * re-initialization (i.e there is no need to call again SPI_Init() function): + * - When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx) + * is programmed as Data direction parameter using the SPI_Init() function + * it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx + * using the SPI_BiDirectionalLineConfig() function. + * - When SPI_NSS_Soft is selected as Slave Select Management parameter + * using the SPI_Init() function it can be possible to manage the + * NSS internal signal using the SPI_NSSInternalSoftwareConfig() function. + * - Reconfigure the data size using the SPI_DataSizeConfig() function + * - Enable or disable the SS output using the SPI_SSOutputCmd() function + * + * 10. To use the CRC Hardware calculation feature refer to the Peripheral + * CRC hardware Calculation subsection. + * + * + * @note This driver supports only the I2S clock scheme available in Silicon + * RevisionB and RevisionY. + * + * @note In I2S mode: if an external clock is used as source clock for the I2S, + * then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f2xx_conf.h should + * be enabled and set to the value of the source clock frequency (in Hz). + * + * @note In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd() + * just after calling the function SPI_Init(). + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include +#include "stm32f2xx.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup SPI + * @brief SPI driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* SPI registers Masks */ +#define CR1_CLEAR_MASK ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_MASK ((uint16_t)0xF040) + +/* RCC PLLs masks */ +#define PLLCFGR_PPLR_MASK ((uint32_t)0x70000000) +#define PLLCFGR_PPLN_MASK ((uint32_t)0x00007FC0) + +#define SPI_CR2_FRF ((uint16_t)0x0010) +#define SPI_SR_TIFRFE ((uint16_t)0x0100) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup SPI_Private_Functions + * @{ + */ + +/** @defgroup SPI_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + Initialization and Configuration functions + =============================================================================== + + This section provides a set of functions allowing to initialize the SPI Direction, + SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud + Rate Prescaler, SPI First Bit and SPI CRC Polynomial. + + The SPI_Init() function follows the SPI configuration procedures for Master mode + and Slave mode (details for these procedures are available in reference manual + (RM0033)). + +@endverbatim + * @{ + */ + +/** + * @brief Deinitialize the SPIx peripheral registers to their default reset values. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * in SPI mode or 2 or 3 in I2S mode. + * @retval None + */ +void SPI_I2S_DeInit(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + if (SPIx == SPI1) + { + /* Enable SPI1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); + /* Release SPI1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); + } + else if (SPIx == SPI2) + { + /* Enable SPI2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); + /* Release SPI2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); + } + else + { + if (SPIx == SPI3) + { + /* Enable SPI3 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); + /* Release SPI3 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); + } + } +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral. + * @retval None + */ +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) +{ + uint16_t tmpreg = 0; + + /* check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Check the SPI parameters */ + assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); + assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); + assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); + assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); + assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); + assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); + assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); + +/*---------------------------- SPIx CR1 Configuration ------------------------*/ + /* Get the SPIx CR1 value */ + tmpreg = SPIx->CR1; + /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ + tmpreg &= CR1_CLEAR_MASK; + /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler + master/salve mode, CPOL and CPHA */ + /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ + /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ + /* Set LSBFirst bit according to SPI_FirstBit value */ + /* Set BR bits according to SPI_BaudRatePrescaler value */ + /* Set CPOL bit according to SPI_CPOL value */ + /* Set CPHA bit according to SPI_CPHA value */ + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | + SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | + SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); + /* Write to SPIx CR1 */ + SPIx->CR1 = tmpreg; + + /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ + SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD); +/*---------------------------- SPIx CRCPOLY Configuration --------------------*/ + /* Write to SPIx CRCPOLY */ + SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the I2S_InitStruct. + * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (configured in I2S mode). + * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral + * configured in I2S mode. + * + * @note The function calculates the optimal prescaler needed to obtain the most + * accurate audio frequency (depending on the I2S clock source, the PLL values + * and the product configuration). But in case the prescaler value is greater + * than 511, the default value (0x02) will be configured instead. + * + * @note if an external clock is used as source clock for the I2S, then the define + * I2S_EXTERNAL_CLOCK_VAL in file stm32f2xx_conf.h should be enabled and set + * to the value of the the source clock frequency (in Hz). + * + * @retval None + */ +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) +{ + uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; + uint32_t tmp = 0, i2sclk = 0; +#ifndef I2S_EXTERNAL_CLOCK_VAL + uint32_t pllm = 0, plln = 0, pllr = 0; +#endif /* I2S_EXTERNAL_CLOCK_VAL */ + + /* Check the I2S parameters */ + assert_param(IS_SPI_23_PERIPH(SPIx)); + assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); + assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); + assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); + assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); + assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); + assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); + +/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK; + SPIx->I2SPR = 0x0002; + + /* Get the I2SCFGR register value */ + tmpreg = SPIx->I2SCFGR; + + /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ + if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) + { + i2sodd = (uint16_t)0; + i2sdiv = (uint16_t)2; + } + /* If the requested audio frequency is not the default, compute the prescaler */ + else + { + /* Check the frame length (For the Prescaler computing) *******************/ + if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) + { + /* Packet length is 16 bits */ + packetlength = 1; + } + else + { + /* Packet length is 32 bits */ + packetlength = 2; + } + + /* Get I2S source Clock frequency (only in Silicon RevisionB and RevisionY) */ + + /* If an external I2S clock has to be used, this define should be set + in the project configuration or in the stm32f2xx_conf.h file */ + #ifdef I2S_EXTERNAL_CLOCK_VAL + /* Set external clock as I2S clock source */ + if ((RCC->CFGR & RCC_CFGR_I2SSRC) == 0) + { + RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC; + } + + /* Set the I2S clock to the external clock value */ + i2sclk = I2S_EXTERNAL_CLOCK_VAL; + + #else /* There is no define for External I2S clock source */ + /* Set PLLI2S as I2S clock source */ + if ((RCC->CFGR & RCC_CFGR_I2SSRC) != 0) + { + RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC; + } + + /* Get the PLLI2SN value */ + plln = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & \ + (RCC_PLLI2SCFGR_PLLI2SN >> 6)); + + /* Get the PLLI2SR value */ + pllr = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & \ + (RCC_PLLI2SCFGR_PLLI2SR >> 28)); + + /* Get the PLLM value */ + pllm = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); + + /* Get the I2S source clock value */ + i2sclk = (uint32_t)(((HSE_VALUE / pllm) * plln) / pllr); + #endif /* I2S_EXTERNAL_CLOCK_VAL */ + + /* Compute the Real divider depending on the MCLK output state, with a floating point */ + if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) + { + /* MCLK output is enabled */ + tmp = (uint16_t)(((((i2sclk / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + else + { + /* MCLK output is disabled */ + tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + + /* Remove the flatting point */ + tmp = tmp / 10; + + /* Check the parity of the divider */ + i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); + + /* Compute the i2sdiv prescaler */ + i2sdiv = (uint16_t)((tmp - i2sodd) / 2); + + /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ + i2sodd = (uint16_t) (i2sodd << 8); + } + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2) || (i2sdiv > 0xFF)) + { + /* Set the default values */ + i2sdiv = 2; + i2sodd = 0; + } + + /* Write to SPIx I2SPR register the computed value */ + SPIx->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); + + /* Configure the I2S with the SPI_InitStruct values */ + tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \ + (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ + (uint16_t)I2S_InitStruct->I2S_CPOL)))); + + /* Write to SPIx I2SCFGR */ + SPIx->I2SCFGR = tmpreg; +} + +/** + * @brief Fills each SPI_InitStruct member with its default value. + * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized. + * @retval None + */ +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) +{ +/*--------------- Reset SPI init structure parameters values -----------------*/ + /* Initialize the SPI_Direction member */ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + /* initialize the SPI_Mode member */ + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + /* initialize the SPI_DataSize member */ + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + /* Initialize the SPI_CPOL member */ + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + /* Initialize the SPI_CPHA member */ + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + /* Initialize the SPI_NSS member */ + SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; + /* Initialize the SPI_BaudRatePrescaler member */ + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + /* Initialize the SPI_FirstBit member */ + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + /* Initialize the SPI_CRCPolynomial member */ + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/** + * @brief Fills each I2S_InitStruct member with its default value. + * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized. + * @retval None + */ +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) +{ +/*--------------- Reset I2S init structure parameters values -----------------*/ + /* Initialize the I2S_Mode member */ + I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; + + /* Initialize the I2S_Standard member */ + I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; + + /* Initialize the I2S_DataFormat member */ + I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; + + /* Initialize the I2S_MCLKOutput member */ + I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; + + /* Initialize the I2S_AudioFreq member */ + I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; + + /* Initialize the I2S_CPOL member */ + I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; +} + +/** + * @brief Enables or disables the specified SPI peripheral. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral */ + SPIx->CR1 |= SPI_CR1_SPE; + } + else + { + /* Disable the selected SPI peripheral */ + SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE); + } +} + +/** + * @brief Enables or disables the specified SPI peripheral (in I2S mode). + * @param SPIx: where x can be 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_23_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral (in I2S mode) */ + SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE; + } + else + { + /* Disable the selected SPI peripheral in I2S mode */ + SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE); + } +} + +/** + * @brief Configures the data size for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_DataSize: specifies the SPI data size. + * This parameter can be one of the following values: + * @arg SPI_DataSize_16b: Set data frame format to 16bit + * @arg SPI_DataSize_8b: Set data frame format to 8bit + * @retval None + */ +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DATASIZE(SPI_DataSize)); + /* Clear DFF bit */ + SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b; + /* Set new DFF bit value */ + SPIx->CR1 |= SPI_DataSize; +} + +/** + * @brief Selects the data transfer direction in bidirectional mode for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_Direction: specifies the data transfer direction in bidirectional mode. + * This parameter can be one of the following values: + * @arg SPI_Direction_Tx: Selects Tx transmission direction + * @arg SPI_Direction_Rx: Selects Rx receive direction + * @retval None + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DIRECTION(SPI_Direction)); + if (SPI_Direction == SPI_Direction_Tx) + { + /* Set the Tx only mode */ + SPIx->CR1 |= SPI_Direction_Tx; + } + else + { + /* Set the Rx only mode */ + SPIx->CR1 &= SPI_Direction_Rx; + } +} + +/** + * @brief Configures internally by software the NSS pin for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. + * This parameter can be one of the following values: + * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally + * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally + * @retval None + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); + if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + /* Set NSS pin internally by software */ + SPIx->CR1 |= SPI_NSSInternalSoft_Set; + } + else + { + /* Reset NSS pin internally by software */ + SPIx->CR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/** + * @brief Enables or disables the SS output for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx SS output. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI SS output */ + SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE; + } + else + { + /* Disable the selected SPI SS output */ + SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE); + } +} + +/** + * @brief Enables or disables the SPIx/I2Sx DMA interface. + * + * @note This function can be called only after the SPI_Init() function has + * been called. + * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA + * are not taken into consideration and are configured by hardware + * respectively to the TI mode requirements. + * + * @param SPIx: where x can be 1, 2 or 3 + * @param NewState: new state of the selected SPI TI communication mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TI mode for the selected SPI peripheral */ + SPIx->CR2 |= SPI_CR2_FRF; + } + else + { + /* Disable the TI mode for the selected SPI peripheral */ + SPIx->CR2 &= (uint16_t)~SPI_CR2_FRF; + } +} + +/** + * @} + */ + +/** @defgroup SPI_Group2 Data transfers functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + Data transfers functions + =============================================================================== + + This section provides a set of functions allowing to manage the SPI data transfers + + In reception, data are received and then stored into an internal Rx buffer while + In transmission, data are first stored into an internal Tx buffer before being + transmitted. + + The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData() + function and returns the Rx buffered value. Whereas a write access to the SPI_DR + can be done using SPI_I2S_SendData() function and stores the written data into + Tx buffer. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * in SPI mode or 2 or 3 in I2S mode. + * @retval The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Return the data in the DR register */ + return SPIx->DR; +} + +/** + * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * in SPI mode or 2 or 3 in I2S mode. + * @param Data: Data to be transmitted. + * @retval None + */ +void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Write in the DR register the data to be sent */ + SPIx->DR = Data; +} + +/** + * @} + */ + +/** @defgroup SPI_Group3 Hardware CRC Calculation functions + * @brief Hardware CRC Calculation functions + * +@verbatim + =============================================================================== + Hardware CRC Calculation functions + =============================================================================== + + This section provides a set of functions allowing to manage the SPI CRC hardware + calculation + + SPI communication using CRC is possible through the following procedure: + 1. Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, + Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() + function. + 2. Enable the CRC calculation using the SPI_CalculateCRC() function. + 3. Enable the SPI using the SPI_Cmd() function + 4. Before writing the last data to the TX buffer, set the CRCNext bit using the + SPI_TransmitCRC() function to indicate that after transmission of the last + data, the CRC should be transmitted. + 5. After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT + bit is reset. The CRC is also received and compared against the SPI_RXCRCR + value. + If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt + can be generated when the SPI_I2S_IT_ERR interrupt is enabled. + +@note It is advised not to read the calculated CRC values during the communication. + +@note When the SPI is in slave mode, be careful to enable CRC calculation only + when the clock is stable, that is, when the clock is in the steady state. + If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive + to the SCK slave input clock as soon as CRCEN is set, and this, whatever + the value of the SPE bit. + +@note With high bitrate frequencies, be careful when transmitting the CRC. + As the number of used CPU cycles has to be as low as possible in the CRC + transfer phase, it is forbidden to call software functions in the CRC + transmission sequence to avoid errors in the last data and CRC reception. + In fact, CRCNEXT bit has to be written before the end of the transmission/reception + of the last data. + +@note For high bit rate frequencies, it is advised to use the DMA mode to avoid the + degradation of the SPI speed performance due to CPU accesses impacting the + SPI bandwidth. + +@note When the STM32F2xx is configured as slave and the NSS hardware mode is + used, the NSS pin needs to be kept low between the data phase and the CRC + phase. + +@note When the SPI is configured in slave mode with the CRC feature enabled, CRC + calculation takes place even if a high level is applied on the NSS pin. + This may happen for example in case of a multi-slave environment where the + communication master addresses slaves alternately. + +@note Between a slave de-selection (high level on NSS) and a new slave selection + (low level on NSS), the CRC value should be cleared on both master and slave + sides in order to resynchronize the master and slave for their respective + CRC calculation. + +@note To clear the CRC, follow the procedure below: + 1. Disable SPI using the SPI_Cmd() function + 2. Disable the CRC calculation using the SPI_CalculateCRC() function. + 3. Enable the CRC calculation using the SPI_CalculateCRC() function. + 4. Enable SPI using the SPI_Cmd() function. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the CRC value calculation of the transferred bytes. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx CRC value calculation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI CRC calculation */ + SPIx->CR1 |= SPI_CR1_CRCEN; + } + else + { + /* Disable the selected SPI CRC calculation */ + SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN); + } +} + +/** + * @brief Transmit the SPIx CRC value. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @retval None + */ +void SPI_TransmitCRC(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Enable the selected SPI CRC transmission */ + SPIx->CR1 |= SPI_CR1_CRCNEXT; +} + +/** + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_CRC: specifies the CRC register to be read. + * This parameter can be one of the following values: + * @arg SPI_CRC_Tx: Selects Tx CRC register + * @arg SPI_CRC_Rx: Selects Rx CRC register + * @retval The selected CRC register value.. + */ +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CRC(SPI_CRC)); + if (SPI_CRC != SPI_CRC_Rx) + { + /* Get the Tx CRC register */ + crcreg = SPIx->TXCRCR; + } + else + { + /* Get the Rx CRC register */ + crcreg = SPIx->RXCRCR; + } + /* Return the selected CRC register */ + return crcreg; +} + +/** + * @brief Returns the CRC Polynomial register value for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @retval The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Return the CRC polynomial register */ + return SPIx->CRCPR; +} + +/** + * @} + */ + +/** @defgroup SPI_Group4 DMA transfers management functions + * @brief DMA transfers management functions + * +@verbatim + =============================================================================== + DMA transfers management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the SPIx/I2Sx DMA interface. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * in SPI mode or 2 or 3 in I2S mode. + * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request + * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request + * @param NewState: new state of the selected SPI DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI DMA requests */ + SPIx->CR2 |= SPI_I2S_DMAReq; + } + else + { + /* Disable the selected SPI DMA requests */ + SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/** + * @} + */ + +/** @defgroup SPI_Group5 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + + This section provides a set of functions allowing to configure the SPI Interrupts + sources and check or clear the flags or pending bits status. + The user should identify which mode will be used in his application to manage + the communication: Polling mode, Interrupt mode or DMA mode. + + Polling Mode + ============= + In Polling Mode, the SPI/I2S communication can be managed by 9 flags: + 1. SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register + 2. SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register + 3. SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI. + 4. SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur + 5. SPI_FLAG_MODF : to indicate if a Mode Fault error occur + 6. SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur + 7. I2S_FLAG_TIFRFE: to indicate a Frame Format error occurs. + 8. I2S_FLAG_UDR: to indicate an Underrun error occurs. + 9. I2S_FLAG_CHSIDE: to indicate Channel Side. + +@note Do not use the BSY flag to handle each data transmission or reception. It is + better to use the TXE and RXNE flags instead. + + In this Mode it is advised to use the following functions: + - FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); + - void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); + + Interrupt Mode + =============== + In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources + and 7 pending bits: + Pending Bits: + ------------- + 1. SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register + 2. SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register + 3. SPI_IT_CRCERR : to indicate if a CRC Calculation error occur (available in SPI mode only) + 4. SPI_IT_MODF : to indicate if a Mode Fault error occur (available in SPI mode only) + 5. SPI_I2S_IT_OVR : to indicate if an Overrun error occur + 6. I2S_IT_UDR : to indicate an Underrun Error occurs (available in I2S mode only). + 7. I2S_FLAG_TIFRFE : to indicate a Frame Format error occurs (available in TI mode only). + + Interrupt Source: + ----------------- + 1. SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty + interrupt. + 2. SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not + empty interrupt. + 3. SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt. + + In this Mode it is advised to use the following functions: + - void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); + - ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); + - void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); + + DMA Mode + ======== + In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests: + 1. SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request + 2. SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request + + In this Mode it is advised to use the following function: + - void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified SPI/I2S interrupts. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * in SPI mode or 2 or 3 in I2S mode. + * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. + * This parameter can be one of the following values: + * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask + * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask + * @arg SPI_I2S_IT_ERR: Error interrupt mask + * @param NewState: new state of the specified SPI interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) +{ + uint16_t itpos = 0, itmask = 0 ; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); + + /* Get the SPI IT index */ + itpos = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = (uint16_t)1 << (uint16_t)itpos; + + if (NewState != DISABLE) + { + /* Enable the selected SPI interrupt */ + SPIx->CR2 |= itmask; + } + else + { + /* Disable the selected SPI interrupt */ + SPIx->CR2 &= (uint16_t)~itmask; + } +} + +/** + * @brief Checks whether the specified SPIx/I2Sx flag is set or not. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * in SPI mode or 2 or 3 in I2S mode. + * @param SPI_I2S_FLAG: specifies the SPI flag to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. + * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. + * @arg SPI_I2S_FLAG_BSY: Busy flag. + * @arg SPI_I2S_FLAG_OVR: Overrun flag. + * @arg SPI_FLAG_MODF: Mode Fault flag. + * @arg SPI_FLAG_CRCERR: CRC Error flag. + * @arg SPI_I2S_FLAG_TIFRFE: Format Error. + * @arg I2S_FLAG_UDR: Underrun Error flag. + * @arg I2S_FLAG_CHSIDE: Channel Side flag. + * @retval The new state of SPI_I2S_FLAG (SET or RESET). + */ +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); + + /* Check the status of the specified SPI flag */ + if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) + { + /* SPI_I2S_FLAG is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_FLAG is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * in SPI mode or 2 or 3 in I2S mode. + * @param SPI_I2S_FLAG: specifies the SPI flag to clear. + * This function clears only CRCERR flag. + * @arg SPI_FLAG_CRCERR: CRC Error flag. + * + * @note OVR (OverRun error) flag is cleared by software sequence: a read + * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read + * operation to SPI_SR register (SPI_I2S_GetFlagStatus()). + * @note UDR (UnderRun error) flag is cleared by a read operation to + * SPI_SR register (SPI_I2S_GetFlagStatus()). + * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write + * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a + * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). + * + * @retval None + */ +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG)); + + /* Clear the selected SPI CRC Error (CRCERR) flag */ + SPIx->SR = (uint16_t)~SPI_I2S_FLAG; +} + +/** + * @brief Checks whether the specified SPIx/I2Sx interrupt has occurred or not. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * in SPI mode or 2 or 3 in I2S mode. + * @param SPI_I2S_IT: specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. + * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. + * @arg SPI_I2S_IT_OVR: Overrun interrupt. + * @arg SPI_IT_MODF: Mode Fault interrupt. + * @arg SPI_IT_CRCERR: CRC Error interrupt. + * @arg I2S_IT_UDR: Underrun interrupt. + * @arg SPI_I2S_IT_TIFRFE: Format Error interrupt. + * @retval The new state of SPI_I2S_IT (SET or RESET). + */ +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); + + /* Get the SPI_I2S_IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Get the SPI_I2S_IT IT mask */ + itmask = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = 0x01 << itmask; + + /* Get the SPI_I2S_IT enable bit status */ + enablestatus = (SPIx->CR2 & itmask) ; + + /* Check the status of the specified SPI interrupt */ + if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) + { + /* SPI_I2S_IT is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_IT is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_IT status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * in SPI mode or 2 or 3 in I2S mode. + * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. + * This function clears only CRCERR interrupt pending bit. + * @arg SPI_IT_CRCERR: CRC Error interrupt. + * + * @note OVR (OverRun Error) interrupt pending bit is cleared by software + * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) + * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()). + * @note UDR (UnderRun Error) interrupt pending bit is cleared by a read + * operation to SPI_SR register (SPI_I2S_GetITStatus()). + * @note MODF (Mode Fault) interrupt pending bit is cleared by software sequence: + * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) + * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable + * the SPI). + * @retval None + */ +void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos = 0; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT)); + + /* Get the SPI_I2S IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ + SPIx->SR = (uint16_t)~itpos; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/system_stm32f2xx.c b/radio/bootloader/system_stm32f2xx.c new file mode 100644 index 000000000..687b6fd3d --- /dev/null +++ b/radio/bootloader/system_stm32f2xx.c @@ -0,0 +1,559 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.3 + * @date 05-March-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +// Gives 60MHz +#define PLL_M 12 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 4 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 60000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +extern uint32_t Master_frequency ; +uint32_t Peri1_frequency ; +uint32_t Peri2_frequency ; +uint32_t Timer_mult1 ; +uint32_t Timer_mult2 ; + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else +// SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +extern uint32_t g_pfnVectors ; + SCB->VTOR = (uint32_t) &g_pfnVectors ; /* Vector Table Relocation in Internal FLASH */ + +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + + Master_frequency = 60000000 ; + Peri1_frequency = 15000000 ; + Peri2_frequency = 30000000 ; + Timer_mult1 = 2 ; + Timer_mult2 = 2 ; + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/usb/common/core/USBConfigurationDescriptor.c b/radio/bootloader/usb/common/core/USBConfigurationDescriptor.c new file mode 100644 index 000000000..7dd995c62 --- /dev/null +++ b/radio/bootloader/usb/common/core/USBConfigurationDescriptor.c @@ -0,0 +1,162 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: USBConfigurationDescriptor implementation + + About: Purpose + Implementation of the USBConfigurationDescriptor class. +*/ + +//----------------------------------------------------------------------------- +// Headers +//----------------------------------------------------------------------------- + +#include "USBConfigurationDescriptor.h" + +//----------------------------------------------------------------------------- +// Exported functions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +/// Returns the total length of a configuration, i.e. including the +/// descriptors following it. +/// \param configuration Pointer to a USBConfigurationDescriptor instance. +/// \return Total length (in bytes) of the configuration. +//----------------------------------------------------------------------------- +unsigned int USBConfigurationDescriptor_GetTotalLength( + const USBConfigurationDescriptor *configuration) +{ + return configuration->wTotalLength; +} + +//----------------------------------------------------------------------------- +/// Returns the number of interfaces in a configuration. +/// \param configuration Pointer to a USBConfigurationDescriptor instance. +/// \return Number of interfaces in configuration. +//----------------------------------------------------------------------------- +unsigned char USBConfigurationDescriptor_GetNumInterfaces( + const USBConfigurationDescriptor *configuration) +{ + return configuration->bNumInterfaces; +} + +//----------------------------------------------------------------------------- +/// Indicates if the device is self-powered when in a given configuration. +/// \param configuration Pointer to a USBConfigurationDescriptor instance. +/// \return 1 if the device is self-powered when in the given configuration; +/// otherwise 0. +//----------------------------------------------------------------------------- +unsigned char USBConfigurationDescriptor_IsSelfPowered( + const USBConfigurationDescriptor *configuration) +{ + if ((configuration->bmAttributes & (1 << 6)) != 0) { + + return 1; + } + else { + + return 0; + } +} + +//----------------------------------------------------------------------------- +/// Parses the given Configuration descriptor (followed by relevant +/// interface, endpoint and class-specific descriptors) into three arrays. +/// *Each array must have its size equal or greater to the number of +/// descriptors it stores plus one*. A null-value is inserted after the last +/// descriptor of each type to indicate the array end. +/// +/// Note that if the pointer to an array is null (0), nothing is stored in +/// it. +/// \param configuration Pointer to the start of the whole Configuration +/// descriptor. +/// \param interfaces Pointer to the Interface descriptor array. +/// \param endpoints Pointer to the Endpoint descriptor array. +/// \param others Pointer to the class-specific descriptor array. +//----------------------------------------------------------------------------- +void USBConfigurationDescriptor_Parse( + const USBConfigurationDescriptor *configuration, + USBInterfaceDescriptor **interfaces, + USBEndpointDescriptor **endpoints, + USBGenericDescriptor **others) +{ + // Get size of configuration to parse + int size = USBConfigurationDescriptor_GetTotalLength(configuration); + size -= sizeof(USBConfigurationDescriptor); + + // Start parsing descriptors + USBGenericDescriptor *descriptor = (USBGenericDescriptor *) configuration; + while (size > 0) { + + // Get next descriptor + descriptor = USBGenericDescriptor_GetNextDescriptor(descriptor); + size -= USBGenericDescriptor_GetLength(descriptor); + + // Store descriptor in correponding array + if (USBGenericDescriptor_GetType(descriptor) + == USBGenericDescriptor_INTERFACE) { + + if (interfaces) { + + *interfaces = (USBInterfaceDescriptor *) descriptor; + interfaces++; + } + } + else if (USBGenericDescriptor_GetType(descriptor) + == USBGenericDescriptor_ENDPOINT) { + + if (endpoints) { + + *endpoints = (USBEndpointDescriptor *) descriptor; + endpoints++; + } + } + else if (others) { + + *others = descriptor; + others++; + } + } + + // Null-terminate arrays + if (interfaces) { + + *interfaces = 0; + } + if (endpoints) { + + *endpoints = 0; + } + if (others) { + + *others = 0; + } +} + diff --git a/radio/bootloader/usb/common/core/USBConfigurationDescriptor.h b/radio/bootloader/usb/common/core/USBConfigurationDescriptor.h new file mode 100644 index 000000000..b7a867d64 --- /dev/null +++ b/radio/bootloader/usb/common/core/USBConfigurationDescriptor.h @@ -0,0 +1,150 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + !!!Purpose + + Definitions and methods for USB configuration descriptor structures + described by the USB specification. + + !!!Usage + + -# Declare USBConfigurationDescriptor instance as a part + of the configuration descriptors of a USB device. + -# To get useful information (field values) from the defined USB device + configuration descriptor, use + - USBConfigurationDescriptor_GetTotalLength + - USBConfigurationDescriptor_GetNumInterfaces + - USBConfigurationDescriptor_IsSelfPowered + -# To pase the defined USB device configuration descriptor, use + - USBConfigurationDescriptor_Parse +*/ + +#ifndef USBCONFIGURATIONDESCRIPTOR_H +#define USBCONFIGURATIONDESCRIPTOR_H + +//----------------------------------------------------------------------------- +// Headers +//----------------------------------------------------------------------------- + +#include "USBGenericDescriptor.h" +#include "USBInterfaceDescriptor.h" +#include "USBEndpointDescriptor.h" + +//----------------------------------------------------------------------------- +// Definitions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +/// \page "USB device Attributes" +/// +/// This page lists the codes of the usb attributes. +/// +/// !Attributes +/// - USBConfigurationDescriptor_BUSPOWERED_NORWAKEUP +/// - USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP +/// - USBConfigurationDescriptor_BUSPOWERED_RWAKEUP +/// - USBConfigurationDescriptor_SELFPOWERED_RWAKEUP +/// - USBConfigurationDescriptor_POWER + +/// Device is bus-powered and not support remote wake-up. +#define USBConfigurationDescriptor_BUSPOWERED_NORWAKEUP 0x80 +/// Device is self-powered and not support remote wake-up. +#define USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP 0xC0 +/// Device is bus-powered and supports remote wake-up. +#define USBConfigurationDescriptor_BUSPOWERED_RWAKEUP 0xA0 +/// Device is self-powered and supports remote wake-up. +#define USBConfigurationDescriptor_SELFPOWERED_RWAKEUP 0xE0 + +/// Calculates the value of the power consumption field given the value in mA. +/// \param power The power consumption value in mA +/// \return The value that should be set to the field in descriptor +#define USBConfigurationDescriptor_POWER(power) (power / 2) +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Types +//----------------------------------------------------------------------------- + +#ifdef __ICCARM__ // IAR +#pragma pack(1) // IAR +#define __attribute__(...) // IAR +#endif // IAR + +//----------------------------------------------------------------------------- +/// USB standard configuration descriptor structure. +//----------------------------------------------------------------------------- +typedef struct { + + /// Size of the descriptor in bytes. + unsigned char bLength; + /// Descriptor type (USBDESC_CONFIGURATION of "USB Descriptor types"). + unsigned char bDescriptorType; + /// Length of all descriptors returned along with this configuration + /// descriptor. + unsigned short wTotalLength; + /// Number of interfaces in this configuration. + unsigned char bNumInterfaces; + /// Value for selecting this configuration. + unsigned char bConfigurationValue; + /// Index of the configuration string descriptor. + unsigned char iConfiguration; + /// Configuration characteristics. + unsigned char bmAttributes; + /// Maximum power consumption of the device when in this configuration. + unsigned char bMaxPower; + +} __attribute__ ((packed)) USBConfigurationDescriptor; // GCC + +#ifdef __ICCARM__ // IAR +#pragma pack() // IAR +#endif // IAR + +//----------------------------------------------------------------------------- +// Exported functions +//----------------------------------------------------------------------------- + +extern unsigned int USBConfigurationDescriptor_GetTotalLength( + const USBConfigurationDescriptor *configuration); + +extern unsigned char USBConfigurationDescriptor_GetNumInterfaces( + const USBConfigurationDescriptor *configuration); + +extern unsigned char USBConfigurationDescriptor_IsSelfPowered( + const USBConfigurationDescriptor *configuration); + +extern void USBConfigurationDescriptor_Parse( + const USBConfigurationDescriptor *configuration, + USBInterfaceDescriptor **interfaces, + USBEndpointDescriptor **endpoints, + USBGenericDescriptor **others); + +#endif //#ifndef USBCONFIGURATIONDESCRIPTOR_H + diff --git a/radio/bootloader/usb/common/core/USBDeviceDescriptor.h b/radio/bootloader/usb/common/core/USBDeviceDescriptor.h new file mode 100644 index 000000000..6b633fe99 --- /dev/null +++ b/radio/bootloader/usb/common/core/USBDeviceDescriptor.h @@ -0,0 +1,125 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + !!!Purpose + + Class for manipulating USB device descriptors. + + !!!Usage + + - Declare a USBDeviceDescriptor instance as the device descriptor of a + USB device. +*/ + +#ifndef USBDEVICEDESCRIPTOR_H +#define USBDEVICEDESCRIPTOR_H + +#include +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB release numbers" +/// +/// This page lists the codes of USB release numbers. +/// +/// !Code +/// - USBDeviceDescriptor_USB2_00 + +/// The device supports USB 2.00. +#define USBDeviceDescriptor_USB2_00 0x0200 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +#ifdef __ICCARM__ // IAR +#pragma pack(1) // IAR +#define __attribute__(...) // IAR +#endif // IAR + +//------------------------------------------------------------------------------ +/// USB standard device descriptor structure. +//------------------------------------------------------------------------------ +typedef struct { + + /// Size of this descriptor in bytes. + unsigned char bLength; + /// Descriptor type (USBGenericDescriptor_DEVICE). + unsigned char bDescriptorType; + /// USB specification release number in BCD format. + unsigned short bcdUSB; + /// Device class code. + unsigned char bDeviceClass; + /// Device subclass code. + unsigned char bDeviceSubClass; + /// Device protocol code. + unsigned char bDeviceProtocol; + /// Maximum packet size of endpoint 0 (in bytes). + unsigned char bMaxPacketSize0; + /// Vendor ID. + unsigned short idVendor; + /// Product ID. + unsigned short idProduct; + /// Device release number in BCD format. + unsigned short bcdDevice; + /// Index of the manufacturer string descriptor. + unsigned char iManufacturer; + /// Index of the product string descriptor. + unsigned char iProduct; + /// Index of the serial number string descriptor. + unsigned char iSerialNumber; + /// Number of possible configurations for the device. + unsigned char bNumConfigurations; + +} __attribute__ ((packed)) USBDeviceDescriptor; // GCC + +#if defined(CHIP_USB_OTGHS) +typedef struct { + + /// Size of this descriptor in bytes. + unsigned char bLength; + /// Descriptor type (USBGenericDescriptor_OTG). + unsigned char bDescriptorType; + /// Attribute Fields D72: Reserved D1: HNP support D0: SRP support + unsigned char bmAttributes; + +} __attribute__ ((packed)) USBOtgDescriptor; // GCC +#endif + +#ifdef __ICCARM__ // IAR +#pragma pack() // IAR +#endif // IAR + +#endif //#ifndef USBDEVICEDESCRIPTOR_H + diff --git a/radio/bootloader/usb/common/core/USBDeviceQualifierDescriptor.h b/radio/bootloader/usb/common/core/USBDeviceQualifierDescriptor.h new file mode 100644 index 000000000..5632e18c5 --- /dev/null +++ b/radio/bootloader/usb/common/core/USBDeviceQualifierDescriptor.h @@ -0,0 +1,89 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Class for manipulating USB device qualifier descriptors. + + !!!Usage + + - Declare a USBDeviceQualifierDescriptor instance as the device qualifier + descriptor of a USB device. +*/ + +#ifndef USBDEVICEQUALIFIERDESCRIPTOR_H +#define USBDEVICEQUALIFIERDESCRIPTOR_H + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +#ifdef __ICCARM__ // IAR +#pragma pack(1) // IAR +#define __attribute__(...) // IAR +#endif // IAR + +//------------------------------------------------------------------------------ +/// Alternate device descriptor indicating the capabilities of the device +/// in full-speed, if currently in high-speed; or in high-speed, if it is +/// currently in full-speed. Only relevant for devices supporting the +/// high-speed mode. +//------------------------------------------------------------------------------ +typedef struct { + + /// Size of the descriptor in bytes. + unsigned char bLength; + /// Descriptor type (USBDESC_DEVICE_QUALIFIER or "USB device types"). + unsigned char bDescriptorType; + /// USB specification release number (in BCD format). + unsigned short bcdUSB; + /// Device class code. + unsigned char bDeviceClass; + /// Device subclass code. + unsigned char bDeviceSubClass; + /// Device protocol code. + unsigned char bDeviceProtocol; + /// Maximum packet size of endpoint 0. + unsigned char bMaxPacketSize0; + /// Number of possible configurations for the device. + unsigned char bNumConfigurations; + /// Reserved. + unsigned char bReserved; + +} __attribute__ ((packed)) USBDeviceQualifierDescriptor; // GCC + +#ifdef __ICCARM__ // IAR +#pragma pack() // IAR +#endif // IAR + +#endif //#ifndef USBDEVICEQUALIFIERDESCRIPTOR_H + diff --git a/radio/bootloader/usb/common/core/USBEndpointDescriptor.c b/radio/bootloader/usb/common/core/USBEndpointDescriptor.c new file mode 100644 index 000000000..c60be2ac1 --- /dev/null +++ b/radio/bootloader/usb/common/core/USBEndpointDescriptor.c @@ -0,0 +1,109 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: USBEndpointDescriptor implementation + + About: Purpose + Implementation of the USBEndpointDescriptor class. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBEndpointDescriptor.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Returns the number of an endpoint given its descriptor. +/// \param endpoint Pointer to a USBEndpointDescriptor instance. +/// \return Endpoint number. +//------------------------------------------------------------------------------ +unsigned char USBEndpointDescriptor_GetNumber( + const USBEndpointDescriptor *endpoint) +{ + return endpoint->bEndpointAddress & 0xF; +} + +//------------------------------------------------------------------------------ +/// Returns the direction of an endpoint given its descriptor. +/// \param endpoint Pointer to a USBEndpointDescriptor instance. +/// \return Endpoint direction (see ). +//------------------------------------------------------------------------------ +unsigned char USBEndpointDescriptor_GetDirection( + const USBEndpointDescriptor *endpoint) +{ + if ((endpoint->bEndpointAddress & 0x80) != 0) { + + return USBEndpointDescriptor_IN; + } + else { + + return USBEndpointDescriptor_OUT; + } +} + +//------------------------------------------------------------------------------ +/// Returns the type of an endpoint given its descriptor. +/// \param endpoint Pointer to a USBEndpointDescriptor instance. +/// \return Endpoint type (see ). +//------------------------------------------------------------------------------ +unsigned char USBEndpointDescriptor_GetType( + const USBEndpointDescriptor *endpoint) +{ + return endpoint->bmAttributes & 0x3; +} + +//------------------------------------------------------------------------------ +/// Returns the maximum size of a packet (in bytes) on an endpoint given +/// its descriptor. +/// \param endpoint - Pointer to a USBEndpointDescriptor instance. +/// \return Maximum packet size of endpoint. +//------------------------------------------------------------------------------ +unsigned short USBEndpointDescriptor_GetMaxPacketSize( + const USBEndpointDescriptor *endpoint) +{ + return endpoint->wMaxPacketSize; +} + +//------------------------------------------------------------------------------ +/// Returns the polling interval on an endpoint given its descriptor. +/// \param endpoint - Pointer to a USBEndpointDescriptor instance. +/// \return Polling interval of endpoint. +//------------------------------------------------------------------------------ +unsigned char USBEndpointDescriptor_GetInterval( + const USBEndpointDescriptor *endpoint) +{ + return endpoint->bInterval; +} + diff --git a/radio/bootloader/usb/common/core/USBEndpointDescriptor.h b/radio/bootloader/usb/common/core/USBEndpointDescriptor.h new file mode 100644 index 000000000..8a691eec2 --- /dev/null +++ b/radio/bootloader/usb/common/core/USBEndpointDescriptor.h @@ -0,0 +1,224 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of a class for handling USB endpoint descriptors. + + !!!Usage + + -# Declare USBEndpointDescriptor instance as a part of the + configuration descriptors of a USB device. + -# To get useful information (field values) from the defined USB device + endpoint descriptor (to configure hardware for endpoints, etc), use + - USBEndpointDescriptor_GetNumber + - USBEndpointDescriptor_GetDirection + - USBEndpointDescriptor_GetType + - USBEndpointDescriptor_GetMaxPacketSize +*/ + +#ifndef USBENDPOINTDESCRIPTOR_H +#define USBENDPOINTDESCRIPTOR_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Endpoint definitions" +/// +/// This page lists definitions and macro for endpoint descriptors. +/// +/// - USB Endpoint directions +/// - USBEndpointDescriptor_OUT +/// - USBEndpointDescriptor_IN +/// +/// - USB Endpoint types +/// - USBEndpointDescriptor_CONTROL +/// - USBEndpointDescriptor_ISOCHRONOUS +/// - USBEndpointDescriptor_BULK +/// - USBEndpointDescriptor_INTERRUPT +/// +/// - USB Endpoint maximun sizes +/// - USBEndpointDescriptor_MAXCTRLSIZE_FS +/// - USBEndpointDescriptor_MAXCTRLSIZE_HS +/// - USBEndpointDescriptor_MAXBULKSIZE_FS +/// - USBEndpointDescriptor_MAXBULKSIZE_HS +/// - USBEndpointDescriptor_MAXINTERRUPTSIZE_FS +/// - USBEndpointDescriptor_MAXINTERRUPTSIZE_HS +/// - USBEndpointDescriptor_MAXISOCHRONOUSSIZE_FS +/// - USBEndpointDescriptor_MAXISOCHRONOUSSIZE_HS +/// +/// - USB Endpoint address define +/// - USBEndpointDescriptor_ADDRESS +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Endpoint directions" +/// +/// This page lists definitions of USB endpoint directions. +/// +/// !Directions +/// - USBEndpointDescriptor_OUT +/// - USBEndpointDescriptor_IN + +/// Endpoint receives data from the host. +#define USBEndpointDescriptor_OUT 0 +/// Endpoint sends data to the host. +#define USBEndpointDescriptor_IN 1 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Endpoint types" +/// +/// This page lists definitions of USB endpoint types. +/// +/// !Types +/// - USBEndpointDescriptor_CONTROL +/// - USBEndpointDescriptor_ISOCHRONOUS +/// - USBEndpointDescriptor_BULK +/// - USBEndpointDescriptor_INTERRUPT + +/// Control endpoint type. +#define USBEndpointDescriptor_CONTROL 0 +/// Isochronous endpoint type. +#define USBEndpointDescriptor_ISOCHRONOUS 1 +/// Bulk endpoint type. +#define USBEndpointDescriptor_BULK 2 +/// Interrupt endpoint type. +#define USBEndpointDescriptor_INTERRUPT 3 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Endpoint maximun sizes" +/// +/// This page lists definitions of USB endpoint maximun sizes. +/// +/// !Sizes +/// - USBEndpointDescriptor_MAXCTRLSIZE_FS +/// - USBEndpointDescriptor_MAXCTRLSIZE_HS +/// - USBEndpointDescriptor_MAXBULKSIZE_FS +/// - USBEndpointDescriptor_MAXBULKSIZE_HS +/// - USBEndpointDescriptor_MAXINTERRUPTSIZE_FS +/// - USBEndpointDescriptor_MAXINTERRUPTSIZE_HS +/// - USBEndpointDescriptor_MAXISOCHRONOUSSIZE_FS +/// - USBEndpointDescriptor_MAXISOCHRONOUSSIZE_HS + +/// Maximum size for a full-speed control endpoint. +#define USBEndpointDescriptor_MAXCTRLSIZE_FS 64 +/// Maximum size for a high-speed control endpoint. +#define USBEndpointDescriptor_MAXCTRLSIZE_HS 64 +/// Maximum size for a full-speed bulk endpoint. +#define USBEndpointDescriptor_MAXBULKSIZE_FS 64 +/// Maximum size for a high-speed bulk endpoint. +#define USBEndpointDescriptor_MAXBULKSIZE_HS 512 +/// Maximum size for a full-speed interrupt endpoint. +#define USBEndpointDescriptor_MAXINTERRUPTSIZE_FS 64 +/// Maximum size for a high-speed interrupt endpoint. +#define USBEndpointDescriptor_MAXINTERRUPTSIZE_HS 1024 +/// Maximum size for a full-speed isochronous endpoint. +#define USBEndpointDescriptor_MAXISOCHRONOUSSIZE_FS 1023 +/// Maximum size for a high-speed isochronous endpoint. +#define USBEndpointDescriptor_MAXISOCHRONOUSSIZE_HS 1024 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Endpoint address define" +/// +/// This page lists macro for USB endpoint address definition. +/// +/// !Macro +/// - USBEndpointDescriptor_ADDRESS + +/// Calculates the address of an endpoint given its number and direction +/// \param direction USB endpoint direction definition +/// \param number USB endpoint number +/// \return The value used to set the endpoint descriptor based on input number +/// and direction +#define USBEndpointDescriptor_ADDRESS(direction, number) \ + (((direction & 0x01) << 7) | (number & 0xF)) +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +#ifdef __ICCARM__ // IAR +#pragma pack(1) // IAR +#define __attribute__(...) // IAR +#endif // IAR + +//------------------------------------------------------------------------------ +/// USB standard endpoint descriptor structure. +//------------------------------------------------------------------------------ +typedef struct { + + /// Size of the descriptor in bytes. + unsigned char bLength; + /// Descriptor type (). + unsigned char bDescriptorType; + /// Address and direction of the endpoint. + unsigned char bEndpointAddress; + /// Endpoint type and additional characteristics (for isochronous endpoints). + unsigned char bmAttributes; + /// Maximum packet size (in bytes) of the endpoint. + unsigned short wMaxPacketSize; + /// Polling rate of the endpoint. + unsigned char bInterval; + +} __attribute__ ((packed)) USBEndpointDescriptor; // GCC + +#ifdef __ICCARM__ // IAR +#pragma pack() // IAR +#endif // IAR + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern unsigned char USBEndpointDescriptor_GetNumber( + const USBEndpointDescriptor *endpoint); + +extern unsigned char USBEndpointDescriptor_GetDirection( + const USBEndpointDescriptor *endpoint); + +extern unsigned char USBEndpointDescriptor_GetType( + const USBEndpointDescriptor *endpoint); + +extern unsigned short USBEndpointDescriptor_GetMaxPacketSize( + const USBEndpointDescriptor *endpoint); + +extern unsigned char USBEndpointDescriptor_GetInterval( + const USBEndpointDescriptor *endpoint); + +#endif //#ifndef USBENDPOINTDESCRIPTOR_H + diff --git a/radio/bootloader/usb/common/core/USBFeatureRequest.c b/radio/bootloader/usb/common/core/USBFeatureRequest.c new file mode 100644 index 000000000..6276f6d5a --- /dev/null +++ b/radio/bootloader/usb/common/core/USBFeatureRequest.c @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: USBFeatureRequest implementation + + About: Purpose + Implementation of the USBFeatureRequest class. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBFeatureRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Returns the feature selector of a given CLEAR_FEATURE or SET_FEATURE +/// request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return Feature selector. +//------------------------------------------------------------------------------ +unsigned char USBFeatureRequest_GetFeatureSelector( + const USBGenericRequest *request) +{ + return USBGenericRequest_GetValue(request); +} + +//------------------------------------------------------------------------------ +/// Indicates the test that the device must undertake following a +/// SET_FEATURE request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return Test selector. +//------------------------------------------------------------------------------ +unsigned char USBFeatureRequest_GetTestSelector( + const USBGenericRequest *request) +{ + return (USBGenericRequest_GetIndex(request) >> 8) & 0xFF; +} + diff --git a/radio/bootloader/usb/common/core/USBFeatureRequest.h b/radio/bootloader/usb/common/core/USBFeatureRequest.h new file mode 100644 index 000000000..49493c732 --- /dev/null +++ b/radio/bootloader/usb/common/core/USBFeatureRequest.h @@ -0,0 +1,146 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of a class for manipulating CLEAR_FEATURE and SET_FEATURE + requests. + + !!!Usage + + - To get USB feature request information (field values) from the + USBGenericRequest instance, use + - USBFeatureRequest_GetFeatureSelector + - USBFeatureRequest_GetTestSelector +*/ + +#ifndef USBFEATUREREQUEST_H +#define USBFEATUREREQUEST_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBGenericRequest.h" + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Feature Request definitions" +/// +/// This page lists codes of USB Feature Request +/// +/// - USB Feature selectors +/// - USBFeatureRequest_ENDPOINTHALT +/// - USBFeatureRequest_DEVICEREMOTEWAKEUP +/// - USBFeatureRequest_TESTMODE +/// +/// - USB Test mode selectors +/// - USBFeatureRequest_TESTJ +/// - USBFeatureRequest_TESTK +/// - USBFeatureRequest_TESTSE0NAK +/// - USBFeatureRequest_TESTPACKET +/// - USBFeatureRequest_TESTFORCEENABLE +/// - USBFeatureRequest_TESTSENDZLP +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Feature selectors" +/// +/// This page lists codes of USB feature selectors. +/// +/// !Selectors +/// - USBFeatureRequest_ENDPOINTHALT +/// - USBFeatureRequest_DEVICEREMOTEWAKEUP +/// - USBFeatureRequest_TESTMODE + +/// Halt feature of an endpoint. +#define USBFeatureRequest_ENDPOINTHALT 0 +/// Remote wake-up feature of the device. +#define USBFeatureRequest_DEVICEREMOTEWAKEUP 1 +/// Test mode of the device. +#define USBFeatureRequest_TESTMODE 2 +/// OTG set feature +#define USBFeatureRequest_OTG 0x0B +//------------------------------------------------------------------------------ + +/// On The Go Feature Selectors +/// b_hnp_enable 3 +/// a_hnp_support 4 +/// a_alt_hnp_support 5 +#define USBFeatureRequest_OTG_B_HNP_ENABLE 3 +#define USBFeatureRequest_OTG_A_HNP_SUPPORT 4 +#define USBFeatureRequest_OTG_A_ALT_HNP_SUPPORT 5 + +//------------------------------------------------------------------------------ +/// \page "USB Test mode selectors" +/// +/// This page lists codes of USB high speed test mode selectors. +/// +/// !Selectors +/// - USBFeatureRequest_TESTJ +/// - USBFeatureRequest_TESTK +/// - USBFeatureRequest_TESTSE0NAK +/// - USBFeatureRequest_TESTPACKET +/// - USBFeatureRequest_TESTFORCEENABLE +/// - USBFeatureRequest_TESTSENDZLP + +/// Tests the high-output drive level on the D+ line. +#define USBFeatureRequest_TESTJ 1 +/// Tests the high-output drive level on the D- line. +#define USBFeatureRequest_TESTK 2 +/// Tests the output impedance, low-level output voltage and loading +/// characteristics. +#define USBFeatureRequest_TESTSE0NAK 3 +/// Tests rise and fall times, eye patterns and jitter. +#define USBFeatureRequest_TESTPACKET 4 +/// Tests the hub disconnect detection. +#define USBFeatureRequest_TESTFORCEENABLE 5 +/// Send a ZLP in Test Mode. +#define USBFeatureRequest_TESTSENDZLP 6 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern unsigned char USBFeatureRequest_GetFeatureSelector( + const USBGenericRequest *request); + + +extern unsigned char USBFeatureRequest_GetTestSelector( + const USBGenericRequest *request); + +#endif //#ifndef USBFEATUREREQUEST_H + diff --git a/radio/bootloader/usb/common/core/USBGenericDescriptor.c b/radio/bootloader/usb/common/core/USBGenericDescriptor.c new file mode 100644 index 000000000..298bad6c5 --- /dev/null +++ b/radio/bootloader/usb/common/core/USBGenericDescriptor.c @@ -0,0 +1,80 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: USBGenericDescriptor implementation + + About: Purpose + Implementation of the USBGenericDescriptor class. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBGenericDescriptor.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Returns the length of a descriptor. +/// \param descriptor Pointer to a USBGenericDescriptor instance. +/// \return Length of descriptor in bytes. +//------------------------------------------------------------------------------ +unsigned int USBGenericDescriptor_GetLength( + const USBGenericDescriptor *descriptor) +{ + return descriptor->bLength; +} + +//------------------------------------------------------------------------------ +/// Returns the type of a descriptor. +/// \param descriptor Pointer to a USBGenericDescriptor instance. +/// \return Type of descriptor. +//------------------------------------------------------------------------------ +unsigned char USBGenericDescriptor_GetType( + const USBGenericDescriptor *descriptor) +{ + return descriptor->bDescriptorType; +} + +//------------------------------------------------------------------------------ +/// Returns a pointer to the descriptor right after the given one, when +/// parsing a Configuration descriptor. +/// \param descriptor - Pointer to a USBGenericDescriptor instance. +/// \return Pointer to the next descriptor. +//------------------------------------------------------------------------------ +USBGenericDescriptor *USBGenericDescriptor_GetNextDescriptor( + const USBGenericDescriptor *descriptor) +{ + return (USBGenericDescriptor *) + (((char *) descriptor) + USBGenericDescriptor_GetLength(descriptor)); +} diff --git a/radio/bootloader/usb/common/core/USBGenericDescriptor.h b/radio/bootloader/usb/common/core/USBGenericDescriptor.h new file mode 100644 index 000000000..01318f431 --- /dev/null +++ b/radio/bootloader/usb/common/core/USBGenericDescriptor.h @@ -0,0 +1,133 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// +/// !!!Purpose +/// +/// Definition of a generic USB descriptor class. +/// +/// !!!Usage +/// +/// -# Declare or access USB descriptors by USBGenericDescriptor instance. +/// -# To get usful information (field values) from the USB descriptors, use +/// - USBGenericDescriptor_GetLength +/// - USBGenericDescriptor_GetType +/// -# To scan the descriptors, use +/// - USBGenericDescriptor_GetNextDescriptor +//------------------------------------------------------------------------------ + +#ifndef USBGENERICDESCRIPTOR_H +#define USBGENERICDESCRIPTOR_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Descriptor types" +/// +/// This page lists the codes of the usb descriptor types +/// +/// !Types +/// - USBGenericDescriptor_DEVICE +/// - USBGenericDescriptor_CONFIGURATION +/// - USBGenericDescriptor_STRING +/// - USBGenericDescriptor_INTERFACE +/// - USBGenericDescriptor_ENDPOINT +/// - USBGenericDescriptor_DEVICEQUALIFIER +/// - USBGenericDescriptor_OTHERSPEEDCONFIGURATION +/// - USBGenericDescriptor_INTERFACEPOWER +/// - USBGenericDescriptor_OTG +/// - USBGenericDescriptor_DEBUG +/// - USBGenericDescriptor_INTERFACEASSOCIATION + +/// Device descriptor type. +#define USBGenericDescriptor_DEVICE 1 +/// Configuration descriptor type. +#define USBGenericDescriptor_CONFIGURATION 2 +/// String descriptor type. +#define USBGenericDescriptor_STRING 3 +/// Interface descriptor type. +#define USBGenericDescriptor_INTERFACE 4 +/// Endpoint descriptor type. +#define USBGenericDescriptor_ENDPOINT 5 +/// Device qualifier descriptor type. +#define USBGenericDescriptor_DEVICEQUALIFIER 6 +/// Other speed configuration descriptor type. +#define USBGenericDescriptor_OTHERSPEEDCONFIGURATION 7 +/// Interface power descriptor type. +#define USBGenericDescriptor_INTERFACEPOWER 8 +/// On-The-Go descriptor type. +#define USBGenericDescriptor_OTG 9 +/// Debug descriptor type. +#define USBGenericDescriptor_DEBUG 10 +/// Interface association descriptor type. +#define USBGenericDescriptor_INTERFACEASSOCIATION 11 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +#ifdef __ICCARM__ // IAR +#pragma pack(1) // IAR +#define __attribute__(...) // IAR +#endif // IAR + +/// Holds the few fields shared by all USB descriptors. +typedef struct { + + /// Length of the descriptor in bytes. + unsigned char bLength; + /// Descriptor type. + unsigned char bDescriptorType; + +} __attribute__ ((packed)) USBGenericDescriptor; // GCC + +#ifdef __ICCARM__ // IAR +#pragma pack() // IAR +#endif // IAR + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern unsigned int USBGenericDescriptor_GetLength( + const USBGenericDescriptor *descriptor); + +extern unsigned char USBGenericDescriptor_GetType( + const USBGenericDescriptor *descriptor); + +extern USBGenericDescriptor *USBGenericDescriptor_GetNextDescriptor( + const USBGenericDescriptor *descriptor); + +#endif //#ifndef USBGENERICDESCRIPTOR_H + diff --git a/radio/bootloader/usb/common/core/USBGenericRequest.c b/radio/bootloader/usb/common/core/USBGenericRequest.c new file mode 100644 index 000000000..9e902422a --- /dev/null +++ b/radio/bootloader/usb/common/core/USBGenericRequest.c @@ -0,0 +1,138 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: USBGenericRequest implementation + + About: Purpose + Implementation of the USBGenericRequest class. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBGenericRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +/// Returns the type of the given request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return "USB Request Types" +//------------------------------------------------------------------------------ +extern unsigned char USBGenericRequest_GetType(const USBGenericRequest *request) +{ + return ((request->bmRequestType >> 5) & 0x3); +} + +//------------------------------------------------------------------------------ +/// Returns the request code of the given request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return Request code. +/// \sa "USB Request Codes" +//------------------------------------------------------------------------------ +unsigned char USBGenericRequest_GetRequest(const USBGenericRequest *request) +{ + return request->bRequest; +} + +//------------------------------------------------------------------------------ +/// Returns the wValue field of the given request. +/// \param request - Pointer to a USBGenericRequest instance. +/// \return Request value. +//------------------------------------------------------------------------------ +unsigned short USBGenericRequest_GetValue(const USBGenericRequest *request) +{ + return request->wValue; +} + +//------------------------------------------------------------------------------ +/// Returns the wIndex field of the given request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return Request index; +//------------------------------------------------------------------------------ +unsigned short USBGenericRequest_GetIndex(const USBGenericRequest *request) +{ + return request->wIndex; +} + +//------------------------------------------------------------------------------ +/// Returns the expected length of the data phase following a request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return Length of data phase. +//------------------------------------------------------------------------------ +unsigned short USBGenericRequest_GetLength(const USBGenericRequest *request) +{ + return request->wLength; +} + +//------------------------------------------------------------------------------ +/// Returns the endpoint number targetted by a given request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return Endpoint number. +//------------------------------------------------------------------------------ +unsigned char USBGenericRequest_GetEndpointNumber( + const USBGenericRequest *request) +{ + return USBGenericRequest_GetIndex(request) & 0xF; +} + +//------------------------------------------------------------------------------ +/// Returns the intended recipient of a given request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return Request recipient. +/// \sa "USB Request Recipients" +//------------------------------------------------------------------------------ +unsigned char USBGenericRequest_GetRecipient(const USBGenericRequest *request) +{ + // Recipient is in bits [0..4] of the bmRequestType field + return request->bmRequestType & 0xF; +} + +//------------------------------------------------------------------------------ +/// Returns the direction of the data transfer following the given request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return Transfer direction. +/// \sa "USB Request Directions" +//------------------------------------------------------------------------------ +unsigned char USBGenericRequest_GetDirection(const USBGenericRequest *request) +{ + // Transfer direction is located in bit D7 of the bmRequestType field + if ((request->bmRequestType & 0x80) != 0) { + + return USBGenericRequest_IN; + } + else { + + return USBGenericRequest_OUT; + } +} + diff --git a/radio/bootloader/usb/common/core/USBGenericRequest.h b/radio/bootloader/usb/common/core/USBGenericRequest.h new file mode 100644 index 000000000..0e7895436 --- /dev/null +++ b/radio/bootloader/usb/common/core/USBGenericRequest.h @@ -0,0 +1,244 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of the USBGenericRequest class and its methods. + + !!!Usage + + -# Declare or access USB requests by USBGenericRequest instance. + -# To get usful information (field values) from the USB requests, use + - USBGenericRequest_GetType + - USBGenericRequest_GetRequest + - USBGenericRequest_GetValue + - USBGenericRequest_GetIndex + - USBGenericRequest_GetLength + - USBGenericRequest_GetEndpointNumber + - USBGenericRequest_GetRecipient + - USBGenericRequest_GetDirection +*/ + +#ifndef USBGENERICREQUEST_H +#define USBGENERICREQUEST_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Generic Request definitions" +/// +/// This page lists the codes of USB generic request. +/// +/// - USB Request codes +/// - USBGenericRequest_GETSTATUS +/// - USBGenericRequest_CLEARFEATURE +/// - USBGenericRequest_SETFEATURE +/// - USBGenericRequest_SETADDRESS +/// - USBGenericRequest_GETDESCRIPTOR +/// - USBGenericRequest_SETDESCRIPTOR +/// - USBGenericRequest_GETCONFIGURATION +/// - USBGenericRequest_SETCONFIGURATION +/// - USBGenericRequest_GETINTERFACE +/// - USBGenericRequest_SETINTERFACE +/// - USBGenericRequest_SYNCHFRAME +/// +/// - USB Request Recipients +/// - USBGenericRequest_DEVICE +/// - USBGenericRequest_INTERFACE +/// - USBGenericRequest_ENDPOINT +/// - USBGenericRequest_OTHER +/// +/// - USB Request Types +/// - USBGenericRequest_STANDARD +/// - USBGenericRequest_CLASS +/// - USBGenericRequest_VENDOR +/// +/// - USB Request Directions +/// - USBGenericRequest_IN +/// - USBGenericRequest_OUT +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Request codes" +/// +/// This page lists the USB generic request codes. +/// +/// !Codes +/// - USBGenericRequest_GETSTATUS +/// - USBGenericRequest_CLEARFEATURE +/// - USBGenericRequest_SETFEATURE +/// - USBGenericRequest_SETADDRESS +/// - USBGenericRequest_GETDESCRIPTOR +/// - USBGenericRequest_SETDESCRIPTOR +/// - USBGenericRequest_GETCONFIGURATION +/// - USBGenericRequest_SETCONFIGURATION +/// - USBGenericRequest_GETINTERFACE +/// - USBGenericRequest_SETINTERFACE +/// - USBGenericRequest_SYNCHFRAME + +/// GET_STATUS request code. +#define USBGenericRequest_GETSTATUS 0 +/// CLEAR_FEATURE request code. +#define USBGenericRequest_CLEARFEATURE 1 +/// SET_FEATURE request code. +#define USBGenericRequest_SETFEATURE 3 +/// SET_ADDRESS request code. +#define USBGenericRequest_SETADDRESS 5 +/// GET_DESCRIPTOR request code. +#define USBGenericRequest_GETDESCRIPTOR 6 +/// SET_DESCRIPTOR request code. +#define USBGenericRequest_SETDESCRIPTOR 7 +/// GET_CONFIGURATION request code. +#define USBGenericRequest_GETCONFIGURATION 8 +/// SET_CONFIGURATION request code. +#define USBGenericRequest_SETCONFIGURATION 9 +/// GET_INTERFACE request code. +#define USBGenericRequest_GETINTERFACE 10 +/// SET_INTERFACE request code. +#define USBGenericRequest_SETINTERFACE 11 +/// SYNCH_FRAME request code. +#define USBGenericRequest_SYNCHFRAME 12 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Request Recipients" +/// +/// This page lists codes of USB request recipients. +/// +/// !Recipients +/// - USBGenericRequest_DEVICE +/// - USBGenericRequest_INTERFACE +/// - USBGenericRequest_ENDPOINT +/// - USBGenericRequest_OTHER + +/// Recipient is the whole device. +#define USBGenericRequest_DEVICE 0 +/// Recipient is an interface. +#define USBGenericRequest_INTERFACE 1 +/// Recipient is an endpoint. +#define USBGenericRequest_ENDPOINT 2 +/// Recipient is another entity. +#define USBGenericRequest_OTHER 3 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Request Types" +/// +/// This page lists codes of USB request types. +/// +/// !Types +/// - USBGenericRequest_STANDARD +/// - USBGenericRequest_CLASS +/// - USBGenericRequest_VENDOR + +/// Request is standard. +#define USBGenericRequest_STANDARD 0 +/// Request is class-specific. +#define USBGenericRequest_CLASS 1 +/// Request is vendor-specific. +#define USBGenericRequest_VENDOR 2 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Request Directions" +/// +/// This page lists codes of USB request directions. +/// +/// !Directions +/// - USBGenericRequest_IN +/// - USBGenericRequest_OUT + +/// Transfer occurs from device to the host. +#define USBGenericRequest_OUT 0 +/// Transfer occurs from the host to the device. +#define USBGenericRequest_IN 1 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Generic USB SETUP request sent over Control endpoints. +//------------------------------------------------------------------------------ +typedef struct { + + /// Type of request + /// \sa "USB Request Recipients" + /// \sa "USB Request Types" + /// \sa "USB Request Directions" + unsigned char bmRequestType:8; + /// Request code + /// \sa "USB Request Codes" + unsigned char bRequest:8; + /// Request-specific value parameter. + unsigned short wValue:16; + /// Request-specific index parameter. + unsigned short wIndex:16; + /// Expected length (in bytes) of the data phase. + unsigned short wLength:16; + +} USBGenericRequest; + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern unsigned char USBGenericRequest_GetType( + const USBGenericRequest *request); + + +extern unsigned char USBGenericRequest_GetRequest( + const USBGenericRequest *request); + +extern unsigned short USBGenericRequest_GetValue( + const USBGenericRequest *request); + +extern unsigned short USBGenericRequest_GetIndex( + const USBGenericRequest *request); + +extern unsigned short USBGenericRequest_GetLength( + const USBGenericRequest *request); + +extern unsigned char USBGenericRequest_GetEndpointNumber( + const USBGenericRequest *request); + +extern unsigned char USBGenericRequest_GetRecipient( + const USBGenericRequest *request); + +extern unsigned char USBGenericRequest_GetDirection( + const USBGenericRequest *request); + +#endif //#ifndef USBGENERICREQUEST_H + diff --git a/radio/bootloader/usb/common/core/USBGetDescriptorRequest.c b/radio/bootloader/usb/common/core/USBGetDescriptorRequest.c new file mode 100644 index 000000000..39c4127c7 --- /dev/null +++ b/radio/bootloader/usb/common/core/USBGetDescriptorRequest.c @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: USBGetDescriptorRequest implementation + + About: Purpose + Implementation of the USBGetDescriptorRequest class. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBGetDescriptorRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Returns the type of the descriptor requested by the host given the +/// corresponding GET_DESCRIPTOR request. +/// \param request Pointer to a USBGenericDescriptor instance. +/// \return Type of the requested descriptor. +//------------------------------------------------------------------------------ +unsigned char USBGetDescriptorRequest_GetDescriptorType( + const USBGenericRequest *request) +{ + // Requested descriptor type is in the high-byte of the wValue field + return (USBGenericRequest_GetValue(request) >> 8) & 0xFF; +} + +//------------------------------------------------------------------------------ +/// Returns the index of the requested descriptor, given the corresponding +/// GET_DESCRIPTOR request. +/// \param request Pointer to a USBGenericDescriptor instance. +/// \return Index of the requested descriptor. +//------------------------------------------------------------------------------ +unsigned char USBGetDescriptorRequest_GetDescriptorIndex( + const USBGenericRequest *request) +{ + // Requested descriptor index if in the low byte of the wValue field + return USBGenericRequest_GetValue(request) & 0xFF; +} + diff --git a/radio/bootloader/usb/common/core/USBGetDescriptorRequest.h b/radio/bootloader/usb/common/core/USBGetDescriptorRequest.h new file mode 100644 index 000000000..5aef6320a --- /dev/null +++ b/radio/bootloader/usb/common/core/USBGetDescriptorRequest.h @@ -0,0 +1,67 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of the USBGetDescriptorRequest class. + + !!!Usage + + - After a GET_DESCRIPTOR request has been received, retrive the useful + values with following functions: + - USBGetDescriptorRequest_GetDescriptorType: the descriptor type + - USBGetDescriptorRequest_GetDescriptorIndex: the index of the requested + descriptor + +*/ + +#ifndef USBGETDESCRIPTORREQUEST_H +#define USBGETDESCRIPTORREQUEST_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBGenericRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern unsigned char USBGetDescriptorRequest_GetDescriptorType( + const USBGenericRequest *request); + +extern unsigned char USBGetDescriptorRequest_GetDescriptorIndex( + const USBGenericRequest *request); + +#endif //#ifndef USBGETDESCRIPTORREQUEST_H + diff --git a/radio/bootloader/usb/common/core/USBInterfaceAssociationDescriptor.h b/radio/bootloader/usb/common/core/USBInterfaceAssociationDescriptor.h new file mode 100644 index 000000000..7f3376d01 --- /dev/null +++ b/radio/bootloader/usb/common/core/USBInterfaceAssociationDescriptor.h @@ -0,0 +1,86 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \page USBInterfaceAssociateDescriptor + * !!!Purpose + * + * Class for manipulating USB IAD descriptors. + * + * !!!Usage + * + * -# Test + */ + +#ifndef USBDIADDESCRIPTOR_H +#define USBDIADDESCRIPTOR_H + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +#ifdef __ICCARM__ // IAR +#pragma pack(1) // IAR +#define __attribute__(...) // IAR +#endif // IAR + +/* + Type: USBDeviceDescriptor + USB standard device descriptor structure. + + Variables: + bLength - Size of this descriptor in bytes. + bDescriptorType - Descriptor type (). + bFirstInterface - Interface number of the first interface that is + associated with this function. + bInterfaceCount - Number of contiguous interfaces that are + associated with this function. + bFunctionClass - Class code (assigned by USB-IF). + bFunctionSubClass - Subclass code (assigned by USB-IF). + bFunctionProtocol - Protocol code (assigned by USB-IF) + iFunction - Index of string descriptor describing this function. +*/ +typedef struct { + + unsigned char bLength; + unsigned char bDescriptorType; + unsigned char bFirstInterface; + unsigned char bInterfaceCount; + unsigned char bFunctionClass; + unsigned char bFunctionSubClass; + unsigned char bFunctionProtocol; + unsigned char iFunction; +} __attribute__ ((packed)) USBInterfaceAssociationDescriptor; // GCC + +#ifdef __ICCARM__ // IAR +#pragma pack() // IAR +#endif // IAR + +#endif //#ifndef USBDIADDESCRIPTOR_H + diff --git a/radio/bootloader/usb/common/core/USBInterfaceDescriptor.h b/radio/bootloader/usb/common/core/USBInterfaceDescriptor.h new file mode 100644 index 000000000..0d897a865 --- /dev/null +++ b/radio/bootloader/usb/common/core/USBInterfaceDescriptor.h @@ -0,0 +1,87 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of a class for manipulating USB interface descriptors. + + !!!Usage + + - Declare USBInterfaceDescriptor instance as a part of the configuration + descriptors of a USB device. + +*/ + +#ifndef USBINTERFACEDESCRIPTOR_H +#define USBINTERFACEDESCRIPTOR_H + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +#ifdef __ICCARM__ // IAR +#pragma pack(1) // IAR +#define __attribute__(...) // IAR +#endif // IAR + +//------------------------------------------------------------------------------ +/// USB standard interface descriptor structure. +//------------------------------------------------------------------------------ +typedef struct { + + /// Size of the descriptor in bytes. + unsigned char bLength; + /// Descriptor type (USBGenericDescriptor_INTERFACE). + unsigned char bDescriptorType; + /// Number of the interface in its configuration. + unsigned char bInterfaceNumber; + /// Value to select this alternate interface setting. + unsigned char bAlternateSetting; + /// Number of endpoints used by the inteface (excluding endpoint 0). + unsigned char bNumEndpoints; + /// Interface class code. + unsigned char bInterfaceClass; + /// Interface subclass code. + unsigned char bInterfaceSubClass; + /// Interface protocol code. + unsigned char bInterfaceProtocol; + /// Index of the interface string descriptor. + unsigned char iInterface; + +} __attribute__ ((packed)) USBInterfaceDescriptor; // GCC + +#ifdef __ICCARM__ // IAR +#pragma pack() // IAR +#endif // IAR + +#endif //#ifndef USBINTERFACEDESCRIPTOR_H + diff --git a/radio/bootloader/usb/common/core/USBInterfaceRequest.c b/radio/bootloader/usb/common/core/USBInterfaceRequest.c new file mode 100644 index 000000000..837e5f6d9 --- /dev/null +++ b/radio/bootloader/usb/common/core/USBInterfaceRequest.c @@ -0,0 +1,69 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: USBInterfaceRequest + + About: Purpose + Implementation of USBInterfaceRequest class methods. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBInterfaceRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Indicates which interface is targetted by a GET_INTERFACE or +/// SET_INTERFACE request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return Interface number. +//------------------------------------------------------------------------------ +unsigned char USBInterfaceRequest_GetInterface(const USBGenericRequest *request) +{ + return (USBGenericRequest_GetIndex(request) & 0xFF); +} + +//------------------------------------------------------------------------------ +/// Indicates the new alternate setting that the interface targetted by a +/// SET_INTERFACE request should use. +/// \param request Pointer to a USBGenericRequest instance. +/// \return New active setting for the interface. +//------------------------------------------------------------------------------ +unsigned char USBInterfaceRequest_GetAlternateSetting( + const USBGenericRequest *request) +{ + return (USBGenericRequest_GetValue(request) & 0xFF); +} + diff --git a/radio/bootloader/usb/common/core/USBInterfaceRequest.h b/radio/bootloader/usb/common/core/USBInterfaceRequest.h new file mode 100644 index 000000000..dff2bdf8f --- /dev/null +++ b/radio/bootloader/usb/common/core/USBInterfaceRequest.h @@ -0,0 +1,68 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definitions for manipulating SET_INTERFACE and GET_INTERFACE request. + + !!!Usage + + -# After a SET_INTERFACE request has been received, retrieve the + target interface using USBInterfaceRequest_GetInterface and its + new alternate setting with USBInterfaceRequest_GetAlternateSetting. + -# After a GET_INTERFACE request has been received, retrieve the target + interface using USBInterfaceRequest_GetInterface. + +*/ + +#ifndef USBINTERFACEREQUEST_H +#define USBINTERFACEREQUEST_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBGenericRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern unsigned char USBInterfaceRequest_GetInterface( + const USBGenericRequest *request); + + +extern unsigned char USBInterfaceRequest_GetAlternateSetting( + const USBGenericRequest *request); + +#endif //#ifndef USBINTERFACEREQUEST_H + diff --git a/radio/bootloader/usb/common/core/USBIrqHandler.c b/radio/bootloader/usb/common/core/USBIrqHandler.c new file mode 100644 index 000000000..b5f54f2ad --- /dev/null +++ b/radio/bootloader/usb/common/core/USBIrqHandler.c @@ -0,0 +1,62 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: USBIrqHandler implementation + + About: Purpose + Implementation of the USB Interrupt Handler. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ +#include +#include + +#include + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +/// Call Arbitrer, device and host interrupt handler. +/// The IRQ functions are defined with weak and can be surcharged if needed. +//------------------------------------------------------------------------------ +void USB_IrqHandler( void ) +{ + // Most arbitrer interrupt + usb_general_interrupt(); + // Device interrupt + USBD_IrqHandler(); + // Host interrupt + usb_pipe_interrupt(); +} + + diff --git a/radio/bootloader/usb/common/core/USBIrqHandler.h b/radio/bootloader/usb/common/core/USBIrqHandler.h new file mode 100644 index 000000000..3e6771ddc --- /dev/null +++ b/radio/bootloader/usb/common/core/USBIrqHandler.h @@ -0,0 +1,52 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Implementation of the USB Interrupt Handler. + + !!!Usage + + -# The IRQ functions are defined with weak and can be surcharged if needed. + +*/ + +#ifndef USBIRQHANDLER_H +#define USBIRQHANDLER_H + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +extern void USB_IrqHandler( void ); + +#endif //#ifndef USBIRQHANDLER_H + diff --git a/radio/bootloader/usb/common/core/USBSetAddressRequest.c b/radio/bootloader/usb/common/core/USBSetAddressRequest.c new file mode 100644 index 000000000..d955d7a87 --- /dev/null +++ b/radio/bootloader/usb/common/core/USBSetAddressRequest.c @@ -0,0 +1,56 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: USBSetAddressRequest implementation + + About: Purpose + Implementation of the USBSetAddressRequest class. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBSetAddressRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +/// Returns the address that the device must take in response to a +/// SET_ADDRESS request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return New device address. +//------------------------------------------------------------------------------ +unsigned char USBSetAddressRequest_GetAddress(const USBGenericRequest *request) +{ + return USBGenericRequest_GetValue(request) & 0x7F; +} + diff --git a/radio/bootloader/usb/common/core/USBSetAddressRequest.h b/radio/bootloader/usb/common/core/USBSetAddressRequest.h new file mode 100644 index 000000000..2a73d7939 --- /dev/null +++ b/radio/bootloader/usb/common/core/USBSetAddressRequest.h @@ -0,0 +1,60 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of a class for manipulating SET_ADDRESS USB requests. + + !!!Usage + + - After a SET_ADDRESS request has been received, retrive the new address + value with USBSetAddressRequest_GetAddress. +*/ + +#ifndef USBSETADDRESSREQUEST_H +#define USBSETADDRESSREQUEST_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBGenericRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern unsigned char USBSetAddressRequest_GetAddress( + const USBGenericRequest *request); + +#endif //#ifndef USBSETADDRESSREQUEST_H + diff --git a/radio/bootloader/usb/common/core/USBSetConfigurationRequest.c b/radio/bootloader/usb/common/core/USBSetConfigurationRequest.c new file mode 100644 index 000000000..4910739bb --- /dev/null +++ b/radio/bootloader/usb/common/core/USBSetConfigurationRequest.c @@ -0,0 +1,58 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: USBSetConfigurationRequest implementation + + About: Purpose + Implementation of the USBSetConfigurationRequest class. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBSetConfigurationRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Returns the number of the configuration that should be set in response +/// to the given SET_CONFIGURATION request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return Number of the requested configuration. +//------------------------------------------------------------------------------ +unsigned char USBSetConfigurationRequest_GetConfiguration( + const USBGenericRequest *request) +{ + return USBGenericRequest_GetValue(request); +} + diff --git a/radio/bootloader/usb/common/core/USBSetConfigurationRequest.h b/radio/bootloader/usb/common/core/USBSetConfigurationRequest.h new file mode 100644 index 000000000..f70ad8aef --- /dev/null +++ b/radio/bootloader/usb/common/core/USBSetConfigurationRequest.h @@ -0,0 +1,61 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of a class for the Set Configuration request. + + !!!Usage + + - After a SET_CONFIGURATION request has been received, retrive the new + configuration value with USBSetConfigurationRequest_GetConfiguration. + +*/ + +#ifndef USBSETCONFIGURATIONREQUEST_H +#define USBSETCONFIGURATIONREQUEST_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBGenericRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern unsigned char USBSetConfigurationRequest_GetConfiguration( + const USBGenericRequest *request); + +#endif //#ifndef USBSETCONFIGURATIONREQUEST_H + diff --git a/radio/bootloader/usb/common/core/USBStringDescriptor.h b/radio/bootloader/usb/common/core/USBStringDescriptor.h new file mode 100644 index 000000000..e3da4b405 --- /dev/null +++ b/radio/bootloader/usb/common/core/USBStringDescriptor.h @@ -0,0 +1,74 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// +/// !!!Purpose +/// +/// Definition of a class for manipulating String descriptors. +//------------------------------------------------------------------------------ + +#ifndef USBSTRINGDESCRIPTOR_H +#define USBSTRINGDESCRIPTOR_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB String Descriptor definitions" +/// +/// This page lists the codes and macros for USB string descriptor definition. +/// +/// !Language IDs +/// - USBStringDescriptor_ENGLISH_US +/// +/// !String Descriptor Length +/// - USBStringDescriptor_LENGTH +/// +/// !ASCII to UNICODE convertion +/// - USBStringDescriptor_UNICODE + +/// Language ID for US english. +#define USBStringDescriptor_ENGLISH_US 0x09, 0x04 + +/// Calculates the length of a string descriptor given the number of ascii +/// characters/language IDs in it. +/// \param length The ascii format string length. +/// \return The actual data length in bytes. +#define USBStringDescriptor_LENGTH(length) ((length) * 2 + 2) +/// Converts an ascii character to its unicode representation. +/// \param ascii The ASCII character to convert +/// \return A 2-byte-array for the UNICODE based on given ASCII +#define USBStringDescriptor_UNICODE(ascii) (ascii), 0 +//------------------------------------------------------------------------------ + +#endif //#ifndef USBSTRINGDESCRIPTOR_H + diff --git a/radio/bootloader/usb/common/massstorage/MSDeviceDescriptor.h b/radio/bootloader/usb/common/massstorage/MSDeviceDescriptor.h new file mode 100644 index 000000000..f85833ee0 --- /dev/null +++ b/radio/bootloader/usb/common/massstorage/MSDeviceDescriptor.h @@ -0,0 +1,73 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// !Purpose +/// +/// Declaration of constants for using Device Descriptors with a Mass Storage +/// driver. +/// +/// !Usage +/// +/// - For a USB device: +/// -# When declaring a USBDeviceDescriptor instance, use the Mass Storage +/// codes defined in this file (see "MS device codes"). +//------------------------------------------------------------------------------ + +#ifndef MSDEVICEDESCRIPTOR_H +#define MSDEVICEDESCRIPTOR_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "MS device codes" +/// This page lists the class, subclass & protocol codes used by a device with +/// a Mass Storage driver. +/// +/// !Codes +/// +/// - MSDeviceDescriptor_CLASS +/// - MSDeviceDescriptor_SUBCLASS +/// - MSDeviceDescriptor_PROTOCOL + +/// Class code for a Mass Storage device. +#define MSDeviceDescriptor_CLASS 0 + +/// Subclass code for a Mass Storage device. +#define MSDeviceDescriptor_SUBCLASS 0 + +/// Protocol code for a Mass Storage device. +#define MSDeviceDescriptor_PROTOCOL 0 +//------------------------------------------------------------------------------ + +#endif //#ifndef MSDEVICEDESCRIPTOR_H + diff --git a/radio/bootloader/usb/common/massstorage/MSInterfaceDescriptor.h b/radio/bootloader/usb/common/massstorage/MSInterfaceDescriptor.h new file mode 100644 index 000000000..b5033e24e --- /dev/null +++ b/radio/bootloader/usb/common/massstorage/MSInterfaceDescriptor.h @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// !Purpose +/// +/// Definition of several constants used when manipulating Mass Storage interface +/// descriptors. +/// +/// !Usage +/// +/// - For a USB device: +/// -# When declaring an interface descriptor for a Mass Storage device, use +/// the class, subclass and protocol codes defined here (see +/// "MS interface codes"). +//------------------------------------------------------------------------------ + +#ifndef MSINTERFACEDESCRIPTOR_H +#define MSINTERFACEDESCRIPTOR_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "MS interface codes" +/// This page lists the available class, subclass & protocol codes for a Mass +/// Storage interface. +/// +/// !Codes +/// +/// - MSInterfaceDescriptor_CLASS +/// - MSInterfaceDescriptor_SCSI +/// - MSInterfaceDescriptor_BULKONLY + +/// Class code for a Mass Storage interface. +#define MSInterfaceDescriptor_CLASS 0x08 + +/// Subclass code for a Mass Storage interface using the SCSI protocol. +#define MSInterfaceDescriptor_SCSI 0x06 + +/// Protocol code for a Mass Storage interface using Bulk-Only Transport. +#define MSInterfaceDescriptor_BULKONLY 0x50 +//------------------------------------------------------------------------------ + + +#endif //#ifndef MSINTERFACEDESCRIPTOR_H + diff --git a/radio/bootloader/usb/device/core/USBD.h b/radio/bootloader/usb/device/core/USBD.h new file mode 100644 index 000000000..27c26f229 --- /dev/null +++ b/radio/bootloader/usb/device/core/USBD.h @@ -0,0 +1,275 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// +/// !!!Purpose +/// +/// Collection of methods for using the USB device controller on AT91 +/// microcontrollers. +/// +/// !!!Usage +/// +/// Please refer to the corresponding application note. +/// - "AT91 USB device framework" +/// - "USBD API" . "USBD API Methods" +//------------------------------------------------------------------------------ + +#ifndef USBD_H +#define USBD_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +// #include +#include +#include + +//------------------------------------------------------------------------------ +// Compile Options +//------------------------------------------------------------------------------ + +/// Compile option for HS or OTG, use DMA. Remove this define for not use DMA. +#if defined(CHIP_USB_OTGHS) || defined(CHIP_USB_UDPHS) +#define DMA +#endif + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB device API return values" +/// +/// This page lists the return values of the USB %device driver API +/// +/// !Return codes +/// - USBD_STATUS_SUCCESS +/// - USBD_STATUS_LOCKED +/// - USBD_STATUS_ABORTED +/// - USBD_STATUS_RESET + +/// Indicates the operation was successful. +#define USBD_STATUS_SUCCESS 0 +/// Endpoint/device is already busy. +#define USBD_STATUS_LOCKED 1 +/// Operation has been aborted. +#define USBD_STATUS_ABORTED 2 +/// Operation has been aborted because the device has been reset. +#define USBD_STATUS_RESET 3 +/// Part ot operation successfully done. +#define USBD_STATUS_PARTIAL_DONE 4 +/// Operation failed because parameter error +#define USBD_STATUS_INVALID_PARAMETER 5 +/// Operation failed because in unexpected state +#define USBD_STATUS_WRONG_STATE 6 +/// Operation failed because HW not supported +#define USBD_STATUS_HW_NOT_SUPPORTED 0xFE +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB device states" +/// +/// This page lists the %device states of the USB %device driver. +/// +/// !States +/// - USBD_STATE_SUSPENDED +/// - USBD_STATE_ATTACHED +/// - USBD_STATE_POWERED +/// - USBD_STATE_DEFAULT +/// - USBD_STATE_ADDRESS +/// - USBD_STATE_CONFIGURED + +/// The device is currently suspended. +#define USBD_STATE_SUSPENDED 0 +/// USB cable is plugged into the device. +#define USBD_STATE_ATTACHED 1 +/// Host is providing +5V through the USB cable. +#define USBD_STATE_POWERED 2 +/// Device has been reset. +#define USBD_STATE_DEFAULT 3 +/// The device has been given an address on the bus. +#define USBD_STATE_ADDRESS 4 +/// A valid configuration has been selected. +#define USBD_STATE_CONFIGURED 5 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB device LEDs" +/// +/// This page lists the LEDs used in the USB %device driver. +/// +/// !LEDs +/// - USBD_LEDPOWER +/// - USBD_LEDUSB +/// - USBD_LEDOTHER + +/// LED for indicating that the device is powered. +#define USBD_LEDPOWER 0 +/// LED for indicating USB activity. +#define USBD_LEDUSB 1 +/// LED for custom usage. +#define USBD_LEDOTHER 2 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Buffer struct used for multi-buffer-listed transfer. +/// The driver can process 255 bytes of buffers or buffer list window. +//------------------------------------------------------------------------------ +typedef struct _USBDTransferBuffer { + /// Pointer to frame buffer + unsigned char * pBuffer; + /// Size of the frame (up to 64K-1) + unsigned short size; + /// Bytes transferred + unsigned short transferred; + /// Bytes in FIFO + unsigned short buffered; + /// Bytes remaining + unsigned short remaining; +} USBDTransferBuffer; + +#ifdef __ICCARM__ // IAR +#define __attribute__(...) // IAR +#endif // IAR + +//------------------------------------------------------------------------------ +/// Struct used for USBD DMA Link List Transfer Descriptor, must be 16-bytes +/// aligned. +/// (For USB, DMA transfer is linked to EPs and FIFO address is EP defined) +//------------------------------------------------------------------------------ +typedef struct _USBDDmaDescriptor { + /// Pointer to Next Descriptor + void* pNxtDesc; + /// Pointer to data buffer address + void* pDataAddr; + /// DMA Control setting register value + unsigned int ctrlSettings:8, /// Control settings + reserved:8, /// Not used + bufferLength:16; /// Length of buffer + /// Loaded to DMA register, OK to modify + unsigned int used; +} __attribute__((aligned(16))) USBDDmaDescriptor; + +#ifdef __ICCARM__ // IAR +#pragma pack() // IAR +#endif // IAR + +//------------------------------------------------------------------------------ +/// Callback used by transfer functions (USBD_Read & USBD_Write) to notify +/// that a transaction is complete. +//------------------------------------------------------------------------------ +typedef void (*TransferCallback)(void *pArg, + unsigned char status, + unsigned int transferred, + unsigned int remaining); + +//------------------------------------------------------------------------------ +/// Callback used by MBL transfer functions (USBD_Read & USBD_Write) to notify +/// that a transaction is complete. +/// \param pArg Pointer to callback arguments. +/// \param status USBD status. +/// \param nbFreed Number of buffers that is freed since last callback. +//------------------------------------------------------------------------------ +typedef void (*MblTransferCallback)(void *pArg, + unsigned char status, + unsigned int nbFreed); + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern void USBD_IrqHandler(void); + +extern void USBD_Init(void); + +extern void USBD_ConfigureSpeed(unsigned char forceFS); + +extern void USBD_Connect(void); + +extern void USBD_Disconnect(void); + +extern char USBD_Write( + unsigned char bEndpoint, + const void *pData, + unsigned int size, + TransferCallback callback, + void *pArg); + +extern char USBD_MblWrite( + unsigned char bEndpoint, + void * pMbl, + unsigned short wListSize, + unsigned char bCircList, + unsigned short wStartNdx, + MblTransferCallback fCallback, + void * pArgument); + +extern char USBD_MblReuse( + unsigned char bEndpoint, + unsigned char * pNewBuffer, + unsigned short wNewSize); + +extern char USBD_Read( + unsigned char bEndpoint, + void *pData, + unsigned int dLength, + TransferCallback fCallback, + void *pArg); + +extern unsigned char USBD_Stall(unsigned char bEndpoint); + +extern void USBD_Halt(unsigned char bEndpoint); + +extern void USBD_Unhalt(unsigned char bEndpoint); + +extern void USBD_ConfigureEndpoint(const USBEndpointDescriptor *pDescriptor); + +extern unsigned char USBD_IsHalted(unsigned char bEndpoint); + +extern void USBD_RemoteWakeUp(void); + +extern void USBD_SetAddress(unsigned char address); + +extern void USBD_SetConfiguration(unsigned char cfgnum); + +extern unsigned char USBD_GetState(void); + +extern unsigned char USBD_IsHighSpeed(void); + +extern void USBD_Test(unsigned char bIndex); + +#endif //#ifndef USBD_H + diff --git a/radio/bootloader/usb/device/core/USBDCallbacks.c b/radio/bootloader/usb/device/core/USBDCallbacks.c new file mode 100644 index 000000000..cc0463a2e --- /dev/null +++ b/radio/bootloader/usb/device/core/USBDCallbacks.c @@ -0,0 +1,81 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBDCallbacks.h" +#include "USBD.h" +#include +#include +#include "debug.h" + +void USBDCallbacks_Initialized(void) +{ + UDP->UDP_ICR = 0x00000200 ; // CLear RXRSM flag + NVIC_EnableIRQ(UDP_IRQn); +} + +#if 0 +void USBDCallbacks_RequestReceived(const USBGenericRequest *pRequest) +{ + // Does nothing +} +#endif + +void USBDCallbacks_Reset(void) +{ + // Does nothing +} + +void USBDCallbacks_Resumed(void) +{ + // Does nothing +} + +void USBDCallbacks_Suspended(void) +{ + // Does nothing +} + +#if 0 +void USBDDriverCallbacks_ConfigurationChanged(unsigned char cfgnum) +{ + TRACE_INFO_WP("ConfigurationChanged "); +} +#endif + +void USBDDriverCallbacks_InterfaceSettingChanged( + unsigned char interface, + unsigned char setting) +{ + // TRACE_INFO_WP("InterfaceSettingChanged "); +} + diff --git a/radio/bootloader/usb/device/core/USBDCallbacks.h b/radio/bootloader/usb/device/core/USBDCallbacks.h new file mode 100644 index 000000000..e18bece3e --- /dev/null +++ b/radio/bootloader/usb/device/core/USBDCallbacks.h @@ -0,0 +1,65 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definitions of callbacks used by the USBD API to notify the user + application of incoming events. These functions are declared as 'weak', + so they can be re-implemented elsewhere in the application in a + transparent way. +*/ + +#ifndef USBDCALLBACKS_H +#define USBDCALLBACKS_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern void USBDCallbacks_Initialized(void); + +extern void USBDCallbacks_Reset(void); + +extern void USBDCallbacks_Suspended(void); + +extern void USBDCallbacks_Resumed(void); + +extern void USBDCallbacks_RequestReceived(const USBGenericRequest *request); + +#endif //#ifndef USBDCALLBACKS_H + diff --git a/radio/bootloader/usb/device/core/USBDDriver.c b/radio/bootloader/usb/device/core/USBDDriver.c new file mode 100644 index 000000000..7e826435c --- /dev/null +++ b/radio/bootloader/usb/device/core/USBDDriver.c @@ -0,0 +1,753 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBDDriver.h" +#include "USBDDriverCallbacks.h" +#include "USBD.h" +#include +#include "debug.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +//------------------------------------------------------------------------------ +// Local functions +//------------------------------------------------------------------------------ +#if defined(CHIP_USB_OTGHS) +static unsigned char otg_features_supported = 0; +#endif + +//------------------------------------------------------------------------------ +/// Send a NULL packet +//------------------------------------------------------------------------------ +static void TerminateCtrlInWithNull(void *pArg, + unsigned char status, + unsigned int transferred, + unsigned int remaining) +{ + USBD_Write(0, // Endpoint #0 + 0, // No data buffer + 0, // No data buffer + (TransferCallback) 0, + (void *) 0); +} + +//------------------------------------------------------------------------------ +/// Configures the device by setting it into the Configured state and +/// initializing all endpoints. +/// \param pDriver Pointer to a USBDDriver instance. +/// \param cfgnum Configuration number to set. +//------------------------------------------------------------------------------ +static void SetConfiguration(USBDDriver *pDriver, unsigned char cfgnum) +{ + USBEndpointDescriptor *pEndpoints[CHIP_USB_NUMENDPOINTS+1]; + const USBConfigurationDescriptor *pConfiguration; + + // Use different descriptor depending on device speed + if (USBD_IsHighSpeed()) { + + pConfiguration = pDriver->pDescriptors->pHsConfiguration; + } + else { + + pConfiguration = pDriver->pDescriptors->pFsConfiguration; + } + + // Set & save the desired configuration + USBD_SetConfiguration(cfgnum); + pDriver->cfgnum = cfgnum; + + // If the configuration is not 0, configure endpoints + if (cfgnum != 0) { + + // Parse configuration to get endpoint descriptors + USBConfigurationDescriptor_Parse(pConfiguration, 0, pEndpoints, 0); + + // Configure endpoints + int i = 0; + while (pEndpoints[i] != 0) { + + USBD_ConfigureEndpoint(pEndpoints[i]); + i++; + } + } + // Should be done before send the ZLP + USBDDriverCallbacks_ConfigurationChanged(cfgnum); + + // Acknowledge the request + USBD_Write(0, // Endpoint #0 + 0, // No data buffer + 0, // No data buffer + (TransferCallback) 0, + (void *) 0); +} + +//------------------------------------------------------------------------------ +/// Sends the current configuration number to the host. +/// \param pDriver Pointer to a USBDDriver instance. +//------------------------------------------------------------------------------ +static void GetConfiguration(const USBDDriver *pDriver) +{ + USBD_Write(0, &(pDriver->cfgnum), 1, 0, 0); +} + +//------------------------------------------------------------------------------ +/// Sends the current status of the device to the host. +/// \param pDriver Pointer to a USBDDriver instance. +//------------------------------------------------------------------------------ +static void GetDeviceStatus(const USBDDriver *pDriver) +{ + static unsigned short data; + const USBConfigurationDescriptor *pConfiguration; + + data = 0; + // Use different configuration depending on device speed + if (USBD_IsHighSpeed()) { + + pConfiguration = pDriver->pDescriptors->pHsConfiguration; + } + else { + + pConfiguration = pDriver->pDescriptors->pFsConfiguration; + } + + // Check current configuration for power mode (if device is configured) + if (pDriver->cfgnum != 0) { + + if (USBConfigurationDescriptor_IsSelfPowered(pConfiguration)) { + + data |= 1; + } + } + + // Check if remote wake-up is enabled + if (pDriver->isRemoteWakeUpEnabled) { + + data |= 2; + } + + // Send the device status + USBD_Write(0, &data, 2, 0, 0); +} + +//------------------------------------------------------------------------------ +/// Sends the current status of an endpoints to the USB host. +/// \param bEndpoint Endpoint number. +//------------------------------------------------------------------------------ +static void GetEndpointStatus(unsigned char bEndpoint) +{ + static unsigned short data; + + data = 0; + // Check if the endpoint exists + if (bEndpoint > CHIP_USB_NUMENDPOINTS) { + + USBD_Stall(0); + } + else { + + // Check if the endpoint if currently halted + if (USBD_IsHalted(bEndpoint)) { + + data = 1; + } + + // Send the endpoint status + USBD_Write(0, &data, 2, 0, 0); + } +} + +//------------------------------------------------------------------------------ +/// Sends the requested USB descriptor to the host if available, or STALLs the +/// request. +/// \param pDriver Pointer to a USBDDriver instance. +/// \param type Type of the requested descriptor +/// \param index Index of the requested descriptor. +/// \param length Maximum number of bytes to return. +//------------------------------------------------------------------------------ +static void GetDescriptor( + const USBDDriver *pDriver, + unsigned char type, + unsigned char indexRDesc, + unsigned int length) +{ + const USBDeviceDescriptor *pDevice; + const USBConfigurationDescriptor *pConfiguration; + const USBDeviceQualifierDescriptor *pQualifier; + const USBConfigurationDescriptor *pOtherSpeed; + const USBGenericDescriptor **pStrings = + (const USBGenericDescriptor **) pDriver->pDescriptors->pStrings; + const USBGenericDescriptor *pString; + unsigned char numStrings = pDriver->pDescriptors->numStrings; + unsigned char terminateWithNull = 0; + + // Use different set of descriptors depending on device speed + if (USBD_IsHighSpeed()) { + + TRACE_DEBUG("HS "); + pDevice = pDriver->pDescriptors->pHsDevice; + pConfiguration = pDriver->pDescriptors->pHsConfiguration; + pQualifier = pDriver->pDescriptors->pHsQualifier; + pOtherSpeed = pDriver->pDescriptors->pHsOtherSpeed; + } + else { + + TRACE_DEBUG("FS "); + pDevice = pDriver->pDescriptors->pFsDevice; + pConfiguration = pDriver->pDescriptors->pFsConfiguration; + pQualifier = pDriver->pDescriptors->pFsQualifier; + pOtherSpeed = pDriver->pDescriptors->pFsOtherSpeed; + } + + // Check the descriptor type + switch (type) { + + case USBGenericDescriptor_DEVICE: + TRACE_INFO_WP("Dev "); + + // Adjust length and send descriptor + if (length > USBGenericDescriptor_GetLength((USBGenericDescriptor *) pDevice)) { + + length = USBGenericDescriptor_GetLength((USBGenericDescriptor *) pDevice); + } + USBD_Write(0, pDevice, length, 0, 0); + break; + + case USBGenericDescriptor_CONFIGURATION: + TRACE_INFO_WP("Cfg "); + + // Adjust length and send descriptor + if (length > USBConfigurationDescriptor_GetTotalLength(pConfiguration)) { + + length = USBConfigurationDescriptor_GetTotalLength(pConfiguration); + terminateWithNull = ((length % pDevice->bMaxPacketSize0) == 0); + } + USBD_Write(0, + pConfiguration, + length, + terminateWithNull ? TerminateCtrlInWithNull : 0, + 0); + break; + + case USBGenericDescriptor_DEVICEQUALIFIER: + TRACE_INFO_WP("Qua "); + + // Check if descriptor exists + if (!pQualifier) { + + USBD_Stall(0); + } + else { + + // Adjust length and send descriptor + if (length > USBGenericDescriptor_GetLength((USBGenericDescriptor *) pQualifier)) { + + length = USBGenericDescriptor_GetLength((USBGenericDescriptor *) pQualifier); + } + USBD_Write(0, pQualifier, length, 0, 0); + } + break; + + case USBGenericDescriptor_OTHERSPEEDCONFIGURATION: + TRACE_INFO_WP("OSC "); + + // Check if descriptor exists + if (!pOtherSpeed) { + + USBD_Stall(0); + } + else { + + // Adjust length and send descriptor + if (length > USBConfigurationDescriptor_GetTotalLength(pOtherSpeed)) { + + length = USBConfigurationDescriptor_GetTotalLength(pOtherSpeed); + terminateWithNull = ((length % pDevice->bMaxPacketSize0) == 0); + } + USBD_Write(0, + pOtherSpeed, + length, + terminateWithNull ? TerminateCtrlInWithNull : 0, + 0); + } + break; + + case USBGenericDescriptor_STRING: + TRACE_INFO_WP("Str%d ", indexRDesc); + + // Check if descriptor exists + if (indexRDesc > numStrings) { + + USBD_Stall(0); + } + else { + + pString = pStrings[indexRDesc]; + + // Adjust length and send descriptor + if (length > USBGenericDescriptor_GetLength(pString)) { + + length = USBGenericDescriptor_GetLength(pString); + terminateWithNull = ((length % pDevice->bMaxPacketSize0) == 0); + } + USBD_Write(0, + pString, + length, + terminateWithNull ? TerminateCtrlInWithNull : 0, + 0); + } + break; + + default: + TRACE_WARNING( + "USBDDriver_GetDescriptor: Unknown descriptor type (%d)\n\r", + type); + USBD_Stall(0); + } +} + +//------------------------------------------------------------------------------ +/// Sets the active setting of the given interface if the configuration supports +/// it; otherwise, the control pipe is STALLed. If the setting of an interface +/// changes. +/// \parma pDriver Pointer to a USBDDriver instance. +/// \parma infnum Interface number. +/// \parma setting New active setting for the interface. +//------------------------------------------------------------------------------ +static void SetInterface( + USBDDriver *pDriver, + unsigned char infnum, + unsigned char setting) +{ + // Make sure alternate settings are supported + if (!pDriver->pInterfaces) { + + USBD_Stall(0); + } + else { + + // Change the current setting of the interface and trigger the callback + // if necessary + if (pDriver->pInterfaces[infnum] != setting) { + + pDriver->pInterfaces[infnum] = setting; + USBDDriverCallbacks_InterfaceSettingChanged(infnum, setting); + } + + // Acknowledge the request + USBD_Write(0, 0, 0, 0, 0); + } +} + +//------------------------------------------------------------------------------ +/// Sends the currently active setting of the given interface to the USB +/// host. If alternate settings are not supported, this function STALLs the +/// control pipe. +/// \param pDriver Pointer to a USBDDriver instance. +/// \param infnum Interface number. +//------------------------------------------------------------------------------ +static void GetInterface( + const USBDDriver *pDriver, + unsigned char infnum) +{ + // Make sure alternate settings are supported, or STALL the control pipe + if (!pDriver->pInterfaces) { + + USBD_Stall(0); + } + else { + + // Sends the current interface setting to the host + USBD_Write(0, &(pDriver->pInterfaces[infnum]), 1, 0, 0); + } +} + +#if defined(CHIP_USB_UDPHS) || defined(CHIP_USB_OTGHS) +//------------------------------------------------------------------------------ +// Performs the selected test on the USB device (high-speed only). +// \param test Test selector value. +//------------------------------------------------------------------------------ +static void USBDDriver_Test(unsigned char test) +{ + TRACE_DEBUG("UDPHS_Test\n\r"); + + // the lower byte of wIndex must be zero + // the most significant byte of wIndex is used to specify the specific test mode + switch (test) { + case USBFeatureRequest_TESTPACKET: + //Test mode Test_Packet: + //Upon command, a port must repetitively transmit the following test packet until + //the exit action is taken. This enables the testing of rise and fall times, eye + //patterns, jitter, and any other dynamic waveform specifications. + //The test packet is made up by concatenating the following strings. + //(Note: For J/K NRZI data, and for NRZ data, the bit on the left is the first one + //transmitted. S indicates that a bit stuff occurs, which inserts an extra NRZI data bit. + //* N is used to indicate N occurrences of a string of bits or symbols.) + //A port in Test_Packet mode must send this packet repetitively. The inter-packet timing + //must be no less than the minimum allowable inter-packet gap as defined in Section 7.1.18 and + //no greater than 125 us. + // Send ZLP + USBD_Test(USBFeatureRequest_TESTSENDZLP); + // Tst PACKET + USBD_Test(USBFeatureRequest_TESTPACKET); + while (1); + //break; not reached + + case USBFeatureRequest_TESTJ: + //Test mode Test_J: + //Upon command, a ports transceiver must enter the high-speed J state and remain in that + //state until the exit action is taken. This enables the testing of the high output drive + //level on the D+ line. + // Send ZLP + USBD_Test(USBFeatureRequest_TESTSENDZLP); + // Tst J + USBD_Test(USBFeatureRequest_TESTJ); + while (1); + //break; not reached + + case USBFeatureRequest_TESTK: + //Test mode Test_K: + //Upon command, a ports transceiver must enter the high-speed K state and remain in + //that state until the exit action is taken. This enables the testing of the high output drive + //level on the D- line. + // Send a ZLP + USBD_Test(USBFeatureRequest_TESTSENDZLP); + USBD_Test(USBFeatureRequest_TESTK); + while (1); + //break; not reached + + case USBFeatureRequest_TESTSE0NAK: + //Test mode Test_SE0_NAK: + //Upon command, a ports transceiver must enter the high-speed receive mode + //and remain in that mode until the exit action is taken. This enables the testing + //of output impedance, low level output voltage, and loading characteristics. + //In addition, while in this mode, upstream facing ports (and only upstream facing ports) + //must respond to any IN token packet with a NAK handshake (only if the packet CRC is + //determined to be correct) within the normal allowed device response time. This enables testing of + //the device squelch level circuitry and, additionally, provides a general purpose stimulus/response + //test for basic functional testing. + // Send a ZLP + USBD_Test(USBFeatureRequest_TESTSENDZLP); + // Test SE0_NAK + USBD_Test(USBFeatureRequest_TESTSE0NAK); + while (1); + //break; not reached + + default: + USBD_Stall(0); + break; + + } + // The exit action is to power cycle the device. + // The device must be disconnected from the host +} +#endif + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Initializes a USBDDriver instance with a list of descriptors. If +/// interfaces can have multiple alternate settings, an array to store the +/// current setting for each interface must be provided. +/// \param pDriver Pointer to a USBDDriver instance. +/// \param pDescriptors Pointer to a USBDDriverDescriptors instance. +/// \param pInterfaces Pointer to an array for storing the current alternate +/// setting of each interface (optional). +//------------------------------------------------------------------------------ +void USBDDriver_Initialize( + USBDDriver *pDriver, + const USBDDriverDescriptors *pDescriptors, + unsigned char *pInterfaces) +{ + + pDriver->cfgnum = 0; +#if (BOARD_USB_BMATTRIBUTES == USBConfigurationDescriptor_SELFPOWERED_RWAKEUP) \ + || (BOARD_USB_BMATTRIBUTES == USBConfigurationDescriptor_BUSPOWERED_RWAKEUP) + pDriver->isRemoteWakeUpEnabled = 1; +#else + pDriver->isRemoteWakeUpEnabled = 0; +#endif + + pDriver->pDescriptors = pDescriptors; + pDriver->pInterfaces = pInterfaces; + + // Initialize interfaces array if not null + if (pInterfaces != 0) { + + memset(pInterfaces, sizeof(pInterfaces), 0); + } +} + +//------------------------------------------------------------------------------ +/// Handles the given request if it is standard, otherwise STALLs it. +/// \param pDriver Pointer to a USBDDriver instance. +/// \param pRequest Pointer to a USBGenericRequest instance. +//------------------------------------------------------------------------------ +void USBDDriver_RequestHandler( + USBDDriver *pDriver, + const USBGenericRequest *pRequest) +{ + unsigned char cfgnum; + unsigned char infnum; + unsigned char eptnum; + unsigned char setting; + unsigned char type; + unsigned char indexDesc; + unsigned int length; + unsigned int address; + + TRACE_INFO_WP("Std "); + + // Check request code + switch (USBGenericRequest_GetRequest(pRequest)) { + + case USBGenericRequest_GETDESCRIPTOR: + TRACE_INFO_WP("gDesc "); + + // Send the requested descriptor + type = USBGetDescriptorRequest_GetDescriptorType(pRequest); + indexDesc = USBGetDescriptorRequest_GetDescriptorIndex(pRequest); + length = USBGenericRequest_GetLength(pRequest); + GetDescriptor(pDriver, type, indexDesc, length); + break; + + case USBGenericRequest_SETADDRESS: + TRACE_INFO_WP("sAddr "); + + // Sends a zero-length packet and then set the device address + address = USBSetAddressRequest_GetAddress(pRequest); + USBD_Write(0, 0, 0, (TransferCallback) USBD_SetAddress, (void *) address); + break; + + case USBGenericRequest_SETCONFIGURATION: + TRACE_INFO_WP("sCfg "); + + // Set the requested configuration + cfgnum = USBSetConfigurationRequest_GetConfiguration(pRequest); + SetConfiguration(pDriver, cfgnum); + break; + + case USBGenericRequest_GETCONFIGURATION: + TRACE_INFO_WP("gCfg "); + + // Send the current configuration number + GetConfiguration(pDriver); + break; + + case USBGenericRequest_GETSTATUS: + TRACE_INFO_WP("gSta "); + + // Check who is the recipient + switch (USBGenericRequest_GetRecipient(pRequest)) { + + case USBGenericRequest_DEVICE: + TRACE_INFO_WP("Dev "); + + // Send the device status + GetDeviceStatus(pDriver); + break; + + case USBGenericRequest_ENDPOINT: + TRACE_INFO_WP("Ept "); + + // Send the endpoint status + eptnum = USBGenericRequest_GetEndpointNumber(pRequest); + GetEndpointStatus(eptnum); + break; + + default: + TRACE_WARNING( + "USBDDriver_RequestHandler: Unknown recipient (%d)\n\r", + USBGenericRequest_GetRecipient(pRequest)); + USBD_Stall(0); + } + break; + + case USBGenericRequest_CLEARFEATURE: + TRACE_INFO_WP("cFeat "); + + // Check which is the requested feature + switch (USBFeatureRequest_GetFeatureSelector(pRequest)) { + + case USBFeatureRequest_ENDPOINTHALT: + TRACE_INFO_WP("Hlt "); + + // Unhalt endpoint and send a zero-length packet + USBD_Unhalt(USBGenericRequest_GetEndpointNumber(pRequest)); + USBD_Write(0, 0, 0, 0, 0); + break; + + case USBFeatureRequest_DEVICEREMOTEWAKEUP: + TRACE_INFO_WP("RmWU "); + + // Disable remote wake-up and send a zero-length packet + pDriver->isRemoteWakeUpEnabled = 0; + USBD_Write(0, 0, 0, 0, 0); + break; + + default: + TRACE_WARNING( + "USBDDriver_RequestHandler: Unknown feature selector (%d)\n\r", + USBFeatureRequest_GetFeatureSelector(pRequest)); + USBD_Stall(0); + } + break; + + case USBGenericRequest_SETFEATURE: + TRACE_INFO_WP("sFeat "); + + // Check which is the selected feature + switch (USBFeatureRequest_GetFeatureSelector(pRequest)) { + + case USBFeatureRequest_DEVICEREMOTEWAKEUP: + TRACE_INFO_WP("RmWU "); + + // Enable remote wake-up and send a ZLP + pDriver->isRemoteWakeUpEnabled = 1; + USBD_Write(0, 0, 0, 0, 0); + break; + + case USBFeatureRequest_ENDPOINTHALT: + TRACE_INFO_WP("Halt "); + // Halt endpoint + USBD_Halt(USBGenericRequest_GetEndpointNumber(pRequest)); + USBD_Write(0, 0, 0, 0, 0); + break; + +#if defined(CHIP_USB_UDPHS) || defined(CHIP_USB_OTGHS) + + case USBFeatureRequest_TESTMODE: + // 7.1.20 Test Mode Support + if ((USBGenericRequest_GetType(pRequest) == USBGenericRequest_DEVICE) + && ((USBGenericRequest_GetIndex(pRequest) & 0x000F) == 0)) { + + // Handle test request + USBDDriver_Test(USBFeatureRequest_GetTestSelector(pRequest)); + } + else { + + USBD_Stall(0); + } + break; +#endif +#if defined(CHIP_USB_OTGHS) + case USBFeatureRequest_OTG_B_HNP_ENABLE: + TRACE_INFO_WP("OTG_B_HNP_ENABLE "); + otg_features_supported |= 1<isRemoteWakeUpEnabled; +} + +#if defined(CHIP_USB_OTGHS) +//------------------------------------------------------------------------------ +/// Return OTG features supported +/// \return the OTG features +//------------------------------------------------------------------------------ +unsigned char USBDDriver_returnOTGFeatures(void) +{ + return otg_features_supported; +} + +//------------------------------------------------------------------------------ +/// Clear OTG features supported +/// \return none +//------------------------------------------------------------------------------ +void USBDDriver_clearOTGFeatures(void) +{ + otg_features_supported = 0; +} +#endif + diff --git a/radio/bootloader/usb/device/core/USBDDriver.h b/radio/bootloader/usb/device/core/USBDDriver.h new file mode 100644 index 000000000..7f5a0b693 --- /dev/null +++ b/radio/bootloader/usb/device/core/USBDDriver.h @@ -0,0 +1,101 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + USB Device Driver class definition. + + !!!Usage + + -# Instanciate a USBDDriver object and initialize it using + USBDDriver_Initialize. + -# When a USB SETUP request is received, forward it to the standard + driver using USBDDriver_RequestHandler. + -# Check the Remote Wakeup setting via USBDDriver_IsRemoteWakeUpEnabled. +*/ + +#ifndef USBDDRIVER_H +#define USBDDRIVER_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBDDriverDescriptors.h" +#include + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// USB device driver structure, holding a list of descriptors identifying +/// the device as well as the driver current state. +//------------------------------------------------------------------------------ +typedef struct { + + /// List of descriptors used by the device. + const USBDDriverDescriptors *pDescriptors; + /// Current setting for each interface. + unsigned char *pInterfaces; + /// Current configuration number (0 -> device is not configured). + unsigned char cfgnum; + /// Indicates if remote wake up has been enabled by the host. + unsigned char isRemoteWakeUpEnabled; +#if defined(CHIP_USB_OTGHS) + /// Features supported by OTG + unsigned char otg_features_supported; +#endif +} USBDDriver; + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern void USBDDriver_Initialize( + USBDDriver *pDriver, + const USBDDriverDescriptors *pDescriptors, + unsigned char *pInterfaces); + +extern void USBDDriver_RequestHandler( + USBDDriver *pDriver, + const USBGenericRequest *pRequest); + +extern unsigned char USBDDriver_IsRemoteWakeUpEnabled(const USBDDriver *pDriver); + +#if defined(CHIP_USB_OTGHS) +extern unsigned char USBDDriver_returnOTGFeatures(void); +extern void USBDDriver_clearOTGFeatures(void); +#endif + +#endif //#ifndef USBDDRIVER_H + diff --git a/radio/bootloader/usb/device/core/USBDDriverCallbacks.h b/radio/bootloader/usb/device/core/USBDDriverCallbacks.h new file mode 100644 index 000000000..9393dcc51 --- /dev/null +++ b/radio/bootloader/usb/device/core/USBDDriverCallbacks.h @@ -0,0 +1,61 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of several callbacks which are triggered by the USB software + driver after receiving specific requests. + + !!!Usage + + -# Re-implement the USBDDriverCallbacks_ConfigurationChanged + callback to know when the hosts changes the active configuration of + the device. + -# Re-implement the USBDDriverCallbacks_InterfaceSettingChanged + callback to get notified whenever the active setting of an interface + is changed by the host. +*/ + +#ifndef USBDDRIVERCALLBACKS_H +#define USBDDRIVERCALLBACKS_H + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern void USBDDriverCallbacks_ConfigurationChanged(unsigned char cfgnum); + +extern void USBDDriverCallbacks_InterfaceSettingChanged(unsigned char interface, + unsigned char setting); + +#endif //#ifndef USBDDRIVERCALLBACKS_H + diff --git a/radio/bootloader/usb/device/core/USBDDriverDescriptors.h b/radio/bootloader/usb/device/core/USBDDriverDescriptors.h new file mode 100644 index 000000000..e75197bec --- /dev/null +++ b/radio/bootloader/usb/device/core/USBDDriverDescriptors.h @@ -0,0 +1,86 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of a class for declaring USB descriptors required by the + device driver. +*/ + +#ifndef USBDDRIVERDESCRIPTORS_H +#define USBDDRIVERDESCRIPTORS_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include +#include +#include + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// List of all descriptors used by a USB device driver. Each descriptor can +/// be provided in two versions: full-speed and high-speed. Devices which are +/// not high-speed capable do not need to provided high-speed descriptors and +/// the full-speed qualifier & other speed descriptors. +//------------------------------------------------------------------------------ +typedef struct { + + /// Pointer to the full-speed device descriptor. + const USBDeviceDescriptor *pFsDevice; + /// Pointer to the full-speed configuration descriptor. + const USBConfigurationDescriptor *pFsConfiguration; + /// Pointer to the full-speed qualifier descriptor. + const USBDeviceQualifierDescriptor *pFsQualifier; + /// Pointer to the full-speed other speed configuration descriptor. + const USBConfigurationDescriptor *pFsOtherSpeed; + /// Pointer to the high-speed device descriptor. + const USBDeviceDescriptor *pHsDevice; + /// Pointer to the high-speed configuration descriptor. + const USBConfigurationDescriptor *pHsConfiguration; + /// Pointer to the high-speed qualifier descriptor. + const USBDeviceQualifierDescriptor *pHsQualifier; + /// Pointer to the high-speed other speed configuration descriptor. + const USBConfigurationDescriptor *pHsOtherSpeed; + /// Pointer to the list of string descriptors. + const unsigned char **pStrings; + /// Number of string descriptors in list. + unsigned char numStrings; + +} USBDDriverDescriptors; + +#endif //#ifndef USBDDRIVERDESCRIPTORS_H + diff --git a/radio/bootloader/usb/device/core/USBD_UDP.c b/radio/bootloader/usb/device/core/USBD_UDP.c new file mode 100644 index 000000000..c525e35bf --- /dev/null +++ b/radio/bootloader/usb/device/core/USBD_UDP.c @@ -0,0 +1,1734 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Implementation of USB device functions on a UDP controller. + + See "USBD API Methods". +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBD.h" +#include "USBDCallbacks.h" +#include +//#include +#include "debug.h" +//#include +//#include +#include +#include + + +//------------------------------------------------------------------------------ +// Local definitions +//------------------------------------------------------------------------------ +#define MASK_STATUS0 0xFFFFFFFC +#define MASK_STATUS1 0xFFFFFFFF + + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Enables the clock of a peripheral. The peripheral ID is used + * to identify which peripheral is targetted. + * \note The ID must NOT be shifted (i.e. 1 << ID_xxx). + * \param id Peripheral ID (ID_xxx). + */ +void PMC_EnablePeripheral(unsigned int id) +{ + // SANITY_CHECK(id < 35); + + if (id < 32) { + if ((PMC->PMC_PCSR0 & (1 << id)) == (1 << id)) { + + TRACE_DEBUG("PMC_EnablePeripheral: clock of peripheral" " %u is already enabled\n\r", id); + } + else { + PMC->PMC_PCER0 = 1 << id; + } + } + else { + id -= 32; + if ((PMC->PMC_PCSR1 & (1 << id)) == (1 << id)) { + + TRACE_DEBUG("PMC_EnablePeripheral: clock of peripheral" " %u is already enabled\n\r", id + 32); + } + else { + PMC->PMC_PCER1 = 1 << id; + } + } +} + +/** + * \brief Disables the clock of a peripheral. The peripheral ID is used + * to identify which peripheral is targetted. + * \note The ID must NOT be shifted (i.e. 1 << ID_xxx). + * \param id Peripheral ID (ID_xxx). + */ +void PMC_DisablePeripheral(unsigned int id) +{ + // SANITY_CHECK(id < 35); + if (id < 32) { + if ((PMC->PMC_PCSR0 & (1 << id)) != (1 << id)) { + TRACE_DEBUG("PMC_DisablePeripheral: clock of peripheral" " %u is not enabled\n\r", id); + } + else { + PMC->PMC_PCDR0 = 1 << id; + } + } + else { + id -= 32; + if ((PMC->PMC_PCSR1 & (1 << id)) != (1 << id)) { + TRACE_DEBUG("PMC_DisablePeripheral: clock of peripheral" " %u is not enabled\n\r", id + 32); + } + else { + PMC->PMC_PCDR1 = 1 << id; + } + } +} + +/** + * \brief Enable all the periph clock via PMC + */ +void PMC_EnableAllPeripherals(void) +{ + PMC->PMC_PCER0 = MASK_STATUS0; + while( (PMC->PMC_PCSR0 & MASK_STATUS0) != MASK_STATUS0); + PMC->PMC_PCER1 = MASK_STATUS1; + while( (PMC->PMC_PCSR1 & MASK_STATUS1) != MASK_STATUS1); + TRACE_DEBUG("Enable all periph clocks\n\r"); +} +/** + * \brief Disable all the periph clock via PMC + */ +void PMC_DisableAllPeripherals(void) +{ + PMC->PMC_PCDR0 = MASK_STATUS0; + while((PMC->PMC_PCSR0 & MASK_STATUS0) != 0); + PMC->PMC_PCDR1 = MASK_STATUS1; + while((PMC->PMC_PCSR1 & MASK_STATUS1) != 0); + TRACE_DEBUG("Disable all periph clocks\n\r"); +} + +/** + * \brief Get Periph Status for the given peripheral ID. + * \param id Peripheral ID (ID_xxx). + */ +unsigned int PMC_IsPeriphEnabled(unsigned int id) +{ + // SANITY_CHECK(id < 35); + + if (id < 32) { + return (PMC->PMC_PCSR0 & (1 << id)); + } + else { + return (PMC->PMC_PCSR1 & (1 << (id - 32))); + } +} + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "UDP register field values" +/// +/// This page lists the initialize values of UDP registers. +/// +/// !Values +/// - UDP_RXDATA + +/// Bit mask for both banks of the UDP_CSR register. +#define UDP_CSR_RXDATA_BK (UDP_CSR_RX_DATA_BK0 | UDP_CSR_RX_DATA_BK1) +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "Endpoint states" +/// +/// This page lists the endpoint states. +/// +/// !States +// - UDP_ENDPOINT_DISABLED +// - UDP_ENDPOINT_HALTED +// - UDP_ENDPOINT_IDLE +// - UDP_ENDPOINT_SENDING +// - UDP_ENDPOINT_RECEIVING +// - UDP_ENDPOINT_SENDINGM +// - UDP_ENDPOINT_RECEIVINGM + +/// Endpoint states: Endpoint is disabled +#define UDP_ENDPOINT_DISABLED 0 +/// Endpoint states: Endpoint is halted (i.e. STALLs every request) +#define UDP_ENDPOINT_HALTED 1 +/// Endpoint states: Endpoint is idle (i.e. ready for transmission) +#define UDP_ENDPOINT_IDLE 2 +/// Endpoint states: Endpoint is sending data +#define UDP_ENDPOINT_SENDING 3 +/// Endpoint states: Endpoint is receiving data +#define UDP_ENDPOINT_RECEIVING 4 +/// Endpoint states: Endpoint is sending MBL +#define UDP_ENDPOINT_SENDINGM 5 +/// Endpoint states: Endpoint is receiving MBL +#define UDP_ENDPOINT_RECEIVINGM 6 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "UDP_CSR register access" +/// +/// This page lists the macroes to access UDP CSR register. +/// +/// !Macros +/// - CLEAR_CSR +/// - SET_CSR + +/// Bitmap for all status bits in CSR. +#define REG_NO_EFFECT_1_ALL UDP_CSR_RX_DATA_BK0 | UDP_CSR_RX_DATA_BK1 \ + |UDP_CSR_STALLSENTISOERROR | UDP_CSR_RXSETUP \ + |UDP_CSR_TXCOMP + +/// Clears the specified bit(s) in the UDP_CSR register. +/// \param endpoint The endpoint number of the CSR to process. +/// \param flags The bitmap to set to 1. +#define SET_CSR(endpoint, flags) \ + { \ + volatile unsigned int reg; \ + int timeOut = 200; \ + reg = UDP->UDP_CSR[endpoint] ; \ + reg |= REG_NO_EFFECT_1_ALL; \ + reg |= (flags); \ + UDP->UDP_CSR[endpoint] = reg; \ + while ( (UDP->UDP_CSR[endpoint] & (flags)) != (flags)) \ + { \ + if (-- timeOut <= 0) break; \ + } \ + } + +/// Sets the specified bit(s) in the UDP_CSR register. +/// \param endpoint The endpoint number of the CSR to process. +/// \param flags The bitmap to clear to 0. +#define CLEAR_CSR(endpoint, flags) \ + { \ + volatile unsigned int reg; \ + reg = UDP->UDP_CSR[endpoint]; \ + reg |= REG_NO_EFFECT_1_ALL; \ + reg &= ~(flags); \ + UDP->UDP_CSR[endpoint] = reg; \ + while ( (UDP->UDP_CSR[endpoint] & (flags)) == (flags)); \ + } +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +/// Describes an ongoing transfer on a UDP endpoint. +typedef struct { + + /// Pointer to a data buffer used for emission/reception. + char *pData; + /// Number of bytes which have been written into the UDP internal FIFO + /// buffers. + volatile int buffered; + /// Number of bytes which have been sent/received. + volatile int transferred; + /// Number of bytes which have not been buffered/transferred yet. + volatile int remaining; + /// Optional callback to invoke when the transfer completes. + volatile TransferCallback fCallback; + /// Optional argument to the callback function. + void *pArgument; +} Transfer; + +/// Describes Multi Buffer List transfer on a UDP endpoint. +typedef struct { + /// Pointer to frame list + USBDTransferBuffer *pMbl; + /// Pointer to last loaded buffer + USBDTransferBuffer *pLastLoaded; + /// List size + unsigned short listSize; + /// Current processing frame + unsigned short currBuffer; + /// First freed frame to re-use + unsigned short freedBuffer; + /// Frame setting, circle frame list + unsigned char circList; + /// All buffer listed is used + unsigned char allUsed; + /// Optional callback to invoke when the transfer completes. + MblTransferCallback fCallback; + /// Optional argument to the callback function. + void *pArgument; +} MblTransfer; + +//------------------------------------------------------------------------------ +/// Describes the state of an endpoint of the UDP controller. +//------------------------------------------------------------------------------ +typedef struct { + + /// Current endpoint state. + volatile unsigned char state; + /// Current reception bank (0 or 1). + volatile unsigned char bank; + /// Maximum packet size for the endpoint. + volatile unsigned short size; + /// Describes an ongoing transfer (if current state is either + /// or ) + union { + Transfer singleTransfer; + MblTransfer mblTransfer; + } transfer; +} Endpoint; + +//------------------------------------------------------------------------------ +// Internal variables +//------------------------------------------------------------------------------ + +/// Holds the internal state for each endpoint of the UDP. +static Endpoint endpoints[CHIP_USB_NUMENDPOINTS]; + +/// Device current state. +static unsigned char deviceState; +/// Indicates the previous device state +static unsigned char previousDeviceState; + +//------------------------------------------------------------------------------ +// Internal Functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Enables the clock of the UDP peripheral. +/// \return 1 if peripheral status changed. +//------------------------------------------------------------------------------ +static unsigned char UDP_EnablePeripheralClock(void) +{ + if (!PMC_IsPeriphEnabled(ID_UDP)) { + PMC_EnablePeripheral(ID_UDP); + return 1; + } + return 0; +} + +//------------------------------------------------------------------------------ +/// Disables the UDP peripheral clock. +//------------------------------------------------------------------------------ +static inline void UDP_DisablePeripheralClock(void) +{ + PMC_DisablePeripheral(ID_UDP); +} + +//------------------------------------------------------------------------------ +/// Enables the 48MHz USB clock. +//------------------------------------------------------------------------------ +static inline void UDP_EnableUsbClock(void) +{ + REG_PMC_SCER = PMC_SCER_UDP; +} + +//------------------------------------------------------------------------------ +/// Disables the 48MHz USB clock. +//------------------------------------------------------------------------------ +static inline void UDP_DisableUsbClock(void) +{ + REG_PMC_SCDR = PMC_SCER_UDP; +} + +//------------------------------------------------------------------------------ +/// Enables the UDP transceiver. +//------------------------------------------------------------------------------ +static inline void UDP_EnableTransceiver(void) +{ + UDP->UDP_TXVC &= ~UDP_TXVC_TXVDIS; +} + +//------------------------------------------------------------------------------ +/// Disables the UDP transceiver. +//------------------------------------------------------------------------------ +static inline void UDP_DisableTransceiver(void) +{ + UDP->UDP_TXVC |= UDP_TXVC_TXVDIS; +} + +//------------------------------------------------------------------------------ +/// Handles a completed transfer on the given endpoint, invoking the +/// configured callback if any. +/// \param bEndpoint Number of the endpoint for which the transfer has completed. +/// \param bStatus Status code returned by the transfer operation +//------------------------------------------------------------------------------ +static void UDP_EndOfTransfer(unsigned char bEndpoint, char bStatus) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + + // Check that endpoint was sending or receiving data + if( (pEndpoint->state == UDP_ENDPOINT_RECEIVING) + || (pEndpoint->state == UDP_ENDPOINT_SENDING)) { + + Transfer *pTransfer = (Transfer *)&(pEndpoint->transfer); + + TRACE_DEBUG_WP("EoT "); + + // Endpoint returns in Idle state + pEndpoint->state = UDP_ENDPOINT_IDLE; + + // Invoke callback is present + if (pTransfer->fCallback != 0) { + + ((TransferCallback) pTransfer->fCallback) + (pTransfer->pArgument, + bStatus, + pTransfer->transferred, + pTransfer->remaining + pTransfer->buffered); + } + else { + TRACE_DEBUG_WP("NoCB "); + } + } + else if ( (pEndpoint->state == UDP_ENDPOINT_RECEIVINGM) + || (pEndpoint->state == UDP_ENDPOINT_SENDINGM) ) { + + MblTransfer *pTransfer = (MblTransfer*)&(pEndpoint->transfer); + + TRACE_DEBUG_WP("EoMT "); + + // Endpoint returns in Idle state + pEndpoint->state = UDP_ENDPOINT_IDLE; + // Invoke callback + if (pTransfer->fCallback != 0) { + + ((MblTransferCallback) pTransfer->fCallback) + (pTransfer->pArgument, + bStatus, + 0); + } + else { + TRACE_DEBUG_WP("NoCB "); + } + } +} + +//------------------------------------------------------------------------------ +/// Clears the correct reception flag (bank 0 or bank 1) of an endpoint +/// \param bEndpoint Index of endpoint +//------------------------------------------------------------------------------ +static void UDP_ClearRxFlag(unsigned char bEndpoint) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + + // Clear flag and change banks + if (pEndpoint->bank == 0) { + + CLEAR_CSR(bEndpoint, UDP_CSR_RX_DATA_BK0); + // Swap bank if in dual-fifo mode + if (CHIP_USB_ENDPOINTS_BANKS(bEndpoint) > 1) { + + pEndpoint->bank = 1; + } + } + else { + + CLEAR_CSR(bEndpoint, UDP_CSR_RX_DATA_BK1); + pEndpoint->bank = 0; + } +} + +//------------------------------------------------------------------------------ +/// Update multi-buffer-transfer descriptors. +/// \param pTransfer Pointer to instance MblTransfer. +/// \param size Size of bytes that processed. +/// \param forceEnd Force the buffer END. +/// \return 1 if current buffer ended. +//------------------------------------------------------------------------------ +static char UDP_MblUpdate(MblTransfer *pTransfer, + USBDTransferBuffer * pBi, + unsigned short size, + unsigned char forceEnd) +{ + // Update transfer descriptor + pBi->remaining -= size; + // Check if current buffer ended + if (pBi->remaining == 0 || forceEnd) { + + // Process to next buffer + if ((++ pTransfer->currBuffer) == pTransfer->listSize) { + if (pTransfer->circList) { + pTransfer->currBuffer = 0; + } + else { + pTransfer->allUsed = 1; + } + } + // All buffer in the list is processed + if (pTransfer->currBuffer == pTransfer->freedBuffer) { + pTransfer->allUsed = 1; + } + // Continue transfer, prepare for next operation + if (pTransfer->allUsed == 0) { + pBi = &pTransfer->pMbl[pTransfer->currBuffer]; + pBi->buffered = 0; + pBi->transferred = 0; + pBi->remaining = pBi->size; + } + return 1; + } + return 0; +} + +//------------------------------------------------------------------------------ +/// Transfers a data payload from the current tranfer buffer to the endpoint +/// FIFO +/// \param bEndpoint Number of the endpoint which is sending data. +//------------------------------------------------------------------------------ +static char UDP_MblWriteFifo(unsigned char bEndpoint) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + MblTransfer *pTransfer = (MblTransfer*)&(pEndpoint->transfer); + USBDTransferBuffer *pBi = &(pTransfer->pMbl[pTransfer->currBuffer]); + signed int size; + + volatile unsigned char * pBytes; + volatile char bufferEnd = 1; + + // Get the number of bytes to send + size = pEndpoint->size; + if (size > pBi->remaining) { + + size = pBi->remaining; + } + + TRACE_DEBUG_WP("w%d.%d ", pTransfer->currBuffer, size); + if (size == 0) { + + return 1; + } + + pTransfer->pLastLoaded = pBi; + pBytes = &(pBi->pBuffer[pBi->transferred + pBi->buffered]); + pBi->buffered += size; + bufferEnd = UDP_MblUpdate(pTransfer, pBi, size, 0); + + // Write packet in the FIFO buffer + if (size) { + signed int c8 = size >> 3; + signed int c1 = size & 0x7; + //printf("%d[%x] ", pBi->transferred, pBytes); + for (; c8; c8 --) { + UDP->UDP_FDR[bEndpoint] = *(pBytes ++); + UDP->UDP_FDR[bEndpoint] = *(pBytes ++); + UDP->UDP_FDR[bEndpoint] = *(pBytes ++); + UDP->UDP_FDR[bEndpoint] = *(pBytes ++); + + UDP->UDP_FDR[bEndpoint] = *(pBytes ++); + UDP->UDP_FDR[bEndpoint] = *(pBytes ++); + UDP->UDP_FDR[bEndpoint] = *(pBytes ++); + UDP->UDP_FDR[bEndpoint] = *(pBytes ++); + } + for (; c1; c1 --) { + UDP->UDP_FDR[bEndpoint] = *(pBytes ++); + } + } + return bufferEnd; +} +/* +//------------------------------------------------------------------------------ +/// Transfers a data payload from an endpoint FIFO to the current transfer +/// buffer, if NULL packet received, the current buffer is ENDed. +/// \param bEndpoint Endpoint number. +/// \param wPacketSize Size of received data packet +/// \return 1 if the buffer ENDed. +//------------------------------------------------------------------------------ +static char UDP_MblReadFifo(unsigned char bEndpoint, unsigned short wPacketSize) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + MblTransfer *pTransfer = (MblTransfer*)&(pEndpoint->transfer); + USBDTransferBuffer *pBi = &(pTransfer->pMbl[pTransfer->currBuffer]); + char bufferEnd; + + // Check that the requested size is not bigger than the remaining transfer + if (wPacketSize > pTransfer->remaining) { + + pTransfer->buffered += wPacketSize - pTransfer->remaining; + wPacketSize = pTransfer->remaining; + } + + // Update transfer descriptor information + pBi->transferred += wPacketSize; + bufferEnd = UDP_MblUpdate(pTransfer, + wPacketSize, + (wPacketSize < pEndpoint->size)); + + // Retrieve packet + if (wPacketSize) { + unsigned char * pBytes = &pBi->pBuffer[pBi->transferred]; + signed int c8 = wPacketSize >> 3; + signed int c1 = wPacketSize & 0x7; + for (; c8; c8 --) { + *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; + *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; + *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; + *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; + + *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; + *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; + *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; + *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; + } + for (; c1; c1 --) { + *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; + } + } + return bufferEnd; +} +*/ +//------------------------------------------------------------------------------ +/// Transfers a data payload from the current tranfer buffer to the endpoint +/// FIFO +/// \param bEndpoint Number of the endpoint which is sending data. +//------------------------------------------------------------------------------ +static void UDP_WritePayload(unsigned char bEndpoint) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + Transfer *pTransfer = (Transfer*)&(pEndpoint->transfer); + signed int size; + + // Get the number of bytes to send + size = pEndpoint->size; + if (size > pTransfer->remaining) { + + size = pTransfer->remaining; + } + + // Update transfer descriptor information + pTransfer->buffered += size; + pTransfer->remaining -= size; + + // Write packet in the FIFO buffer + while (size > 0) { + + UDP->UDP_FDR[bEndpoint] = *(pTransfer->pData); + pTransfer->pData++; + size--; + } +} + + +//------------------------------------------------------------------------------ +/// Transfers a data payload from an endpoint FIFO to the current transfer buffer +/// \param bEndpoint Endpoint number. +/// \param wPacketSize Size of received data packet +//------------------------------------------------------------------------------ +static void UDP_ReadPayload(unsigned char bEndpoint, int wPacketSize) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + Transfer *pTransfer = (Transfer*)&(pEndpoint->transfer); + + // Check that the requested size is not bigger than the remaining transfer + if (wPacketSize > pTransfer->remaining) { + + pTransfer->buffered += wPacketSize - pTransfer->remaining; + wPacketSize = pTransfer->remaining; + } + + // Update transfer descriptor information + pTransfer->remaining -= wPacketSize; + pTransfer->transferred += wPacketSize; + + // Retrieve packet + while (wPacketSize > 0) { + + *(pTransfer->pData) = (char) UDP->UDP_FDR[bEndpoint]; + pTransfer->pData++; + wPacketSize--; + } +} + +//------------------------------------------------------------------------------ +/// Received SETUP packet from endpoint 0 FIFO +/// \param pRequest Generic USB SETUP request sent over Control endpoints +//------------------------------------------------------------------------------ +static void UDP_ReadRequest(USBGenericRequest *pRequest) +{ + unsigned char *pData = (unsigned char *)pRequest; + unsigned int i; + + // Copy packet + for (i = 0; i < 8; i++) { + + *pData = (unsigned char) UDP->UDP_FDR[0]; + pData++; + } +} + +//------------------------------------------------------------------------------ +/// Reset all endpoint transfer descriptors +//------------------------------------------------------------------------------ +static void UDP_ResetEndpoints( void ) +{ + Endpoint *pEndpoint; + Transfer *pTransfer; + unsigned char bEndpoint; + + // Reset the transfer descriptor of every endpoint + for (bEndpoint = 0; bEndpoint < CHIP_USB_NUMENDPOINTS; bEndpoint++) { + + pEndpoint = &(endpoints[bEndpoint]); + pTransfer = (Transfer*)&(pEndpoint->transfer); + + // Reset endpoint transfer descriptor + pTransfer->pData = 0; + pTransfer->transferred = -1; + pTransfer->buffered = -1; + pTransfer->remaining = -1; + pTransfer->fCallback = 0; + pTransfer->pArgument = 0; + + // Reset endpoint state + pEndpoint->bank = 0; + pEndpoint->state = UDP_ENDPOINT_DISABLED; + } +} + +//------------------------------------------------------------------------------ +/// Disable all endpoints (except control endpoint 0), aborting current +/// transfers if necessary +//------------------------------------------------------------------------------ +static void UDP_DisableEndpoints( void ) + +{ + unsigned char bEndpoint; + + // Disable each endpoint, terminating any pending transfer + // Control endpoint 0 is not disabled + for (bEndpoint = 1; bEndpoint < CHIP_USB_NUMENDPOINTS; bEndpoint++) { + + UDP_EndOfTransfer(bEndpoint, USBD_STATUS_ABORTED); + endpoints[bEndpoint].state = UDP_ENDPOINT_DISABLED; + } +} + +//------------------------------------------------------------------------------ +/// Checks if an ongoing transfer on an endpoint has been completed. +/// \param bEndpoint Endpoint number. +/// \return 1 if the current transfer on the given endpoint is complete; +/// otherwise 0. +//------------------------------------------------------------------------------ +static unsigned char UDP_IsTransferFinished(unsigned char bEndpoint) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + Transfer *pTransfer = (Transfer*)&(pEndpoint->transfer); + + // Check if it is a Control endpoint + // -> Control endpoint must always finish their transfer with a zero-length + // packet + if ((UDP->UDP_CSR[bEndpoint] & UDP_CSR_EPTYPE) + == UDP_CSR_EPTYPE_CTRL) { + + return (pTransfer->buffered < pEndpoint->size); + } + // Other endpoints only need to transfer all the data + else { + + return (pTransfer->buffered <= pEndpoint->size) + && (pTransfer->remaining == 0); + } +} + +//------------------------------------------------------------------------------ +/// Endpoint interrupt handler. +/// Handle IN/OUT transfers, received SETUP packets and STALLing +/// \param bEndpoint Index of endpoint +//------------------------------------------------------------------------------ +static void UDP_EndpointHandler(unsigned char bEndpoint) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + Transfer *pTransfer = (Transfer*)&(pEndpoint->transfer); + MblTransfer *pMblt = (MblTransfer*)&(pEndpoint->transfer); + unsigned int status = UDP->UDP_CSR[bEndpoint]; + unsigned short wPacketSize; + USBGenericRequest request; + + TRACE_DEBUG_WP("E%d ", bEndpoint); + TRACE_DEBUG_WP("st:0x%X ", status); + + // Handle interrupts + // IN packet sent + if ((status & UDP_CSR_TXCOMP) != 0) { + + TRACE_DEBUG_WP("Wr "); + + // Check that endpoint was in MBL Sending state + if (pEndpoint->state == UDP_ENDPOINT_SENDINGM) { + + USBDTransferBuffer * pMbli = pMblt->pLastLoaded; + unsigned char bufferEnd = 0; + + TRACE_DEBUG_WP("TxM%d.%d ", pMblt->allUsed, pMbli->buffered); + + // End of transfer ? + if (pMblt->allUsed && pMbli->buffered == 0) { + + pMbli->transferred += pMbli->buffered; + pMbli->buffered = 0; + + // Disable interrupt + UDP->UDP_IDR = 1 << bEndpoint; + UDP_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); + CLEAR_CSR(bEndpoint, UDP_CSR_TXCOMP); + } + else { + + // Transfer remaining data + TRACE_DEBUG_WP("%d ", pEndpoint->size); + + if (pMbli->buffered > pEndpoint->size) { + pMbli->transferred += pEndpoint->size; + pMbli->buffered -= pEndpoint->size; + } + else { + pMbli->transferred += pMbli->buffered; + pMbli->buffered = 0; + } + + // Send next packet + if (CHIP_USB_ENDPOINTS_BANKS(bEndpoint) == 1) { + + // No double buffering + bufferEnd = UDP_MblWriteFifo(bEndpoint); + SET_CSR(bEndpoint, UDP_CSR_TXPKTRDY); + CLEAR_CSR(bEndpoint, UDP_CSR_TXCOMP); + } + else { + // Double buffering + SET_CSR(bEndpoint, UDP_CSR_TXPKTRDY); + CLEAR_CSR(bEndpoint, UDP_CSR_TXCOMP); + bufferEnd = UDP_MblWriteFifo(bEndpoint); + } + + if (bufferEnd && pMblt->fCallback) { + ((MblTransferCallback) pTransfer->fCallback) + (pTransfer->pArgument, + USBD_STATUS_PARTIAL_DONE, + 1); + } + } + } + // Check that endpoint was in Sending state + else if (pEndpoint->state == UDP_ENDPOINT_SENDING) { + + // End of transfer ? + if (UDP_IsTransferFinished(bEndpoint)) { + + pTransfer->transferred += pTransfer->buffered; + pTransfer->buffered = 0; + + // Disable interrupt if this is not a control endpoint + if ((status & UDP_CSR_EPTYPE) != UDP_CSR_EPTYPE_CTRL) { + + UDP->UDP_IDR = 1 << bEndpoint; + } + + UDP_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); + CLEAR_CSR(bEndpoint, UDP_CSR_TXCOMP); + } + else { + + // Transfer remaining data + TRACE_DEBUG_WP(" %d ", pEndpoint->size); + + pTransfer->transferred += pEndpoint->size; + pTransfer->buffered -= pEndpoint->size; + + // Send next packet + if (CHIP_USB_ENDPOINTS_BANKS(bEndpoint) == 1) { + + // No double buffering + UDP_WritePayload(bEndpoint); + SET_CSR(bEndpoint, UDP_CSR_TXPKTRDY); + CLEAR_CSR(bEndpoint, UDP_CSR_TXCOMP); + } + else { + // Double buffering + SET_CSR(bEndpoint, UDP_CSR_TXPKTRDY); + CLEAR_CSR(bEndpoint, UDP_CSR_TXCOMP); + UDP_WritePayload(bEndpoint); + } + } + } + else { + // Acknowledge interrupt + TRACE_ERROR("Error Wr"); + CLEAR_CSR(bEndpoint, UDP_CSR_TXCOMP); + } + } + + // OUT packet received + if ((status & UDP_CSR_RXDATA_BK) != 0) { + + TRACE_DEBUG_WP("Rd "); + + // Check that the endpoint is in Receiving state + if (pEndpoint->state != UDP_ENDPOINT_RECEIVING) { + + // Check if an ACK has been received on a Control endpoint + if (((status & UDP_CSR_EPTYPE) == UDP_CSR_EPTYPE_CTRL) + && ((status & UDP_CSR_RXBYTECNT) == 0)) { + + // Acknowledge the data and finish the current transfer + UDP_ClearRxFlag(bEndpoint); + UDP_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); + } + // Check if the data has been STALLed + else if ((status & UDP_CSR_FORCESTALL) != 0) { + + // Discard STALLed data + TRACE_DEBUG_WP("Discard "); + UDP_ClearRxFlag(bEndpoint); + } + // NAK the data + else { + + TRACE_DEBUG_WP("Nak "); + UDP->UDP_IDR = 1 << bEndpoint; + } + } + // Endpoint is in Read state + else { + + // Retrieve data and store it into the current transfer buffer + wPacketSize = (unsigned short) (status >> 16); + TRACE_DEBUG_WP("%d ", wPacketSize); + UDP_ReadPayload(bEndpoint, wPacketSize); + UDP_ClearRxFlag(bEndpoint); + + // Check if the transfer is finished + if ((pTransfer->remaining == 0) || (wPacketSize < pEndpoint->size)) { + + // Disable interrupt if this is not a control endpoint + if ((status & UDP_CSR_EPTYPE) != UDP_CSR_EPTYPE_CTRL) { + + UDP->UDP_IDR = 1 << bEndpoint; + } + UDP_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); + } + } + } + + // STALL sent + if ((status & UDP_CSR_STALLSENTISOERROR) != 0) { + + TRACE_WARNING( "Sta 0x%X [%d] ", status, bEndpoint); + + // If the endpoint is not halted, clear the STALL condition + CLEAR_CSR(bEndpoint, UDP_CSR_STALLSENTISOERROR); + if (pEndpoint->state != UDP_ENDPOINT_HALTED) { + + TRACE_WARNING( "_ " ); + CLEAR_CSR(bEndpoint, UDP_CSR_FORCESTALL); + } + } + + // SETUP packet received + if ((status & UDP_CSR_RXSETUP) != 0) { + + TRACE_DEBUG_WP("Stp "); + + // If a transfer was pending, complete it + // Handles the case where during the status phase of a control write + // transfer, the host receives the device ZLP and ack it, but the ack + // is not received by the device + if ((pEndpoint->state == UDP_ENDPOINT_RECEIVING) + || (pEndpoint->state == UDP_ENDPOINT_SENDING)) { + + UDP_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); + } + // Copy the setup packet + UDP_ReadRequest(&request); + + // Set the DIR bit before clearing RXSETUP in Control IN sequence + if (USBGenericRequest_GetDirection(&request) == USBGenericRequest_IN) { + + SET_CSR(bEndpoint, UDP_CSR_DIR); + } + // Acknowledge setup packet + CLEAR_CSR(bEndpoint, UDP_CSR_RXSETUP); + + // Forward the request to the upper layer + USBDCallbacks_RequestReceived(&request); + } + +} + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +/// USB device interrupt handler +/// Manages device resume, suspend, end of bus reset. +/// Forwards endpoint interrupts to the appropriate handler. +//------------------------------------------------------------------------------ +void USBD_IRQHandler(void) +{ + unsigned int status; + int eptnum = 0; + + // Get interrupt status + // Some interrupts may get masked depending on the device state + status = UDP->UDP_ISR; + status &= UDP->UDP_IMR; + + if (deviceState < USBD_STATE_POWERED) { + + status &= UDP_ICR_WAKEUP | UDP_ICR_RXRSM; + UDP->UDP_ICR = ~status; + } + + // Return immediately if there is no interrupt to service + if (status == 0) { + + TRACE_DEBUG_WP(".\n\r"); + return; + } + + // Toggle USB LED if the device is active + if (deviceState >= USBD_STATE_POWERED) { + + // LED_Set(USBD_LEDUSB); + } + + // Service interrupts + + //// Start Of Frame (SOF) + //if (ISSET(dStatus, UDP_ISR_SOFINT)) { + // + // TRACE_DEBUG("SOF"); + // + // // Invoke the SOF callback + // USB_StartOfFrameCallback(pUsb); + // + // // Acknowledge interrupt + // UDP->UDP_ICR = UDP_ICR_SOFINT; + // dStatus &= ~UDP_ISR_SOFINT; + //} + + // Suspend + // This interrupt is always treated last (hence the '==') + if (status == UDP_ISR_RXSUSP) { + + TRACE_INFO_WP("Susp "); + + // Don't do anything if the device is already suspended + if (deviceState != USBD_STATE_SUSPENDED) { + + // The device enters the Suspended state + // Enable wakeup + UDP->UDP_IER = UDP_IER_WAKEUP | UDP_IER_RXRSM; + + // Acknowledge interrupt + UDP->UDP_ICR = UDP_ICR_RXSUSP; + + // Switch to the Suspended state + previousDeviceState = deviceState; + deviceState = USBD_STATE_SUSPENDED; + // Invoke the Suspended callback + USBDCallbacks_Suspended(); + UDP_DisableTransceiver(); + UDP_DisablePeripheralClock(); + UDP_DisableUsbClock(); + } + } + // Resume + else if ((status & (UDP_ISR_WAKEUP | UDP_ISR_RXRSM)) != 0) { + + TRACE_INFO_WP("Res "); + + // Don't do anything if the device was not suspended + if (deviceState == USBD_STATE_SUSPENDED) { + + // The device enters its previous state + UDP_EnablePeripheralClock(); + UDP_EnableUsbClock(); + + // Enable the transceiver if the device was past the Default + // state + deviceState = previousDeviceState; + if (deviceState >= USBD_STATE_DEFAULT) { + + UDP_EnableTransceiver(); + + // Invoke the Resume callback + USBDCallbacks_Resumed(); + } + } + + // Clear and disable resume interrupts + UDP->UDP_ICR = UDP_ICR_WAKEUP | UDP_ICR_RXRSM | UDP_ICR_RXSUSP; + UDP->UDP_IDR = UDP_IDR_WAKEUP | UDP_IDR_RXRSM; + } + // End of bus reset + else if ((status & UDP_ISR_ENDBUSRES) != 0) { + + TRACE_INFO_WP("EoBRes "); + + // The device enters the Default state + deviceState = USBD_STATE_DEFAULT; + UDP_EnableTransceiver(); + UDP_ResetEndpoints(); + UDP_DisableEndpoints(); + USBD_ConfigureEndpoint(0); + + // Flush and enable the Suspend interrupt + UDP->UDP_ICR = UDP_ICR_WAKEUP | UDP_ICR_RXRSM | UDP_ICR_RXSUSP; + UDP->UDP_IER = UDP_IER_RXSUSP; + + //// Enable the Start Of Frame (SOF) interrupt if needed + //if (pUsb->pCallbacks->startOfFrame != 0) { + // + // UDP->UDP_IER = UDP_IER_SOFINT; + //} + + // Invoke the Reset callback + USBDCallbacks_Reset(); + + // Acknowledge end of bus reset interrupt + UDP->UDP_ICR = UDP_ICR_ENDBUSRES; + } + // Endpoint interrupts + else { + + while (status != 0) { + + // Check if endpoint has a pending interrupt + if ((status & (1 << eptnum)) != 0) { + + UDP_EndpointHandler(eptnum); + status &= ~(1 << eptnum); + + if (status != 0) { + + TRACE_INFO_WP("\n\r - "); + } + } + eptnum++; + } + } + + // Toggle LED back to its previous state + TRACE_DEBUG_WP("!"); + TRACE_INFO_WP("\n\r"); + if (deviceState >= USBD_STATE_POWERED) { + + // LED_Clear(USBD_LEDUSB); + } +} + +//------------------------------------------------------------------------------ +/// Configures an endpoint according to its Endpoint Descriptor. +/// \param pDescriptor Pointer to an Endpoint descriptor. +//------------------------------------------------------------------------------ +void USBD_ConfigureEndpoint(const USBEndpointDescriptor *pDescriptor) +{ + Endpoint *pEndpoint; + unsigned char bEndpoint; + unsigned char bType; + unsigned char bEndpointDir; + + // NULL descriptor -> Control endpoint 0 + if (pDescriptor == 0) { + + bEndpoint = 0; + pEndpoint = &(endpoints[bEndpoint]); + bType= USBEndpointDescriptor_CONTROL; + bEndpointDir = 0; + pEndpoint->size = CHIP_USB_ENDPOINTS_MAXPACKETSIZE(0); + } + else { + + bEndpoint = USBEndpointDescriptor_GetNumber(pDescriptor); + pEndpoint = &(endpoints[bEndpoint]); + bType = USBEndpointDescriptor_GetType(pDescriptor); + bEndpointDir = USBEndpointDescriptor_GetDirection(pDescriptor); + pEndpoint->size = USBEndpointDescriptor_GetMaxPacketSize(pDescriptor); + } + + // Abort the current transfer is the endpoint was configured and in + // Write or Read state + if ((pEndpoint->state == UDP_ENDPOINT_RECEIVING) + || (pEndpoint->state == UDP_ENDPOINT_SENDING) + || (pEndpoint->state == UDP_ENDPOINT_RECEIVINGM) + || (pEndpoint->state == UDP_ENDPOINT_SENDINGM)) { + + UDP_EndOfTransfer(bEndpoint, USBD_STATUS_RESET); + } + pEndpoint->state = UDP_ENDPOINT_IDLE; + + // Reset Endpoint Fifos + UDP->UDP_RST_EP |= (1 << bEndpoint); + UDP->UDP_RST_EP &= ~(1 << bEndpoint); + + // Configure endpoint + SET_CSR(bEndpoint, (unsigned int)UDP_CSR_EPEDS + | (bType << 8) | (bEndpointDir << 10)); + if (bType != USBEndpointDescriptor_CONTROL) { + + } + else { + + UDP->UDP_IER = (1 << bEndpoint); + } + + TRACE_INFO_WP("CfgEpt%d ", bEndpoint); +} + +//------------------------------------------------------------------------------ +/// Sends data through a USB endpoint. Sets up the transfer descriptor, +/// writes one or two data payloads (depending on the number of FIFO bank +/// for the endpoint) and then starts the actual transfer. The operation is +/// complete when all the data has been sent. +/// +/// *If the size of the buffer is greater than the size of the endpoint +/// (or twice the size if the endpoint has two FIFO banks), then the buffer +/// must be kept allocated until the transfer is finished*. This means that +/// it is not possible to declare it on the stack (i.e. as a local variable +/// of a function which returns after starting a transfer). +/// +/// \param bEndpoint Endpoint number. +/// \param pData Pointer to a buffer with the data to send. +/// \param dLength Size of the data buffer. +/// \param fCallback Optional callback function to invoke when the transfer is +/// complete. +/// \param pArgument Optional argument to the callback function. +/// \return USBD_STATUS_SUCCESS if the transfer has been started; +/// otherwise, the corresponding error status code. +//------------------------------------------------------------------------------ +char USBD_Write( unsigned char bEndpoint, + const void *pData, + unsigned int dLength, + TransferCallback fCallback, + void *pArgument ) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + Transfer *pTransfer = (Transfer*)&(pEndpoint->transfer); + + // Check that the endpoint is in Idle state + if (pEndpoint->state != UDP_ENDPOINT_IDLE) { + + return USBD_STATUS_LOCKED; + } + TRACE_DEBUG_WP("Write%d(%d) ", bEndpoint, dLength); + + // Setup the transfer descriptor + pTransfer->pData = (void *) pData; + pTransfer->remaining = dLength; + pTransfer->buffered = 0; + pTransfer->transferred = 0; + pTransfer->fCallback = fCallback; + pTransfer->pArgument = pArgument; + + // Send the first packet + pEndpoint->state = UDP_ENDPOINT_SENDING; + while((UDP->UDP_CSR[bEndpoint]&UDP_CSR_TXPKTRDY)==UDP_CSR_TXPKTRDY); + UDP_WritePayload(bEndpoint); + SET_CSR(bEndpoint, UDP_CSR_TXPKTRDY); + + // If double buffering is enabled and there is data remaining, + // prepare another packet + if ((CHIP_USB_ENDPOINTS_BANKS(bEndpoint) > 1) && (pTransfer->remaining > 0)) { + + UDP_WritePayload(bEndpoint); + } + + // Enable interrupt on endpoint + UDP->UDP_IER = 1 << bEndpoint; + + return USBD_STATUS_SUCCESS; +} + +//------------------------------------------------------------------------------ +/// Sends data frames through a USB endpoint. Sets up the transfer descriptor +/// list, writes one or two data payloads (depending on the number of FIFO bank +/// for the endpoint) and then starts the actual transfer. The operation is +/// complete when all the data has been sent. +/// +/// *If the size of the frame is greater than the size of the endpoint +/// (or twice the size if the endpoint has two FIFO banks), then the buffer +/// must be kept allocated until the frame is finished*. This means that +/// it is not possible to declare it on the stack (i.e. as a local variable +/// of a function which returns after starting a transfer). +/// +/// \param bEndpoint Endpoint number. +/// \param pMbl Pointer to a frame (USBDTransferBuffer) list that describes +/// the buffer list to send. +/// \param wListSize Size of the frame list. +/// \param bCircList Circle the list. +/// \param wStartNdx For circled list only, the first buffer index to transfer. +/// \param fCallback Optional callback function to invoke when the transfer is +/// complete. +/// \param pArgument Optional argument to the callback function. +/// \return USBD_STATUS_SUCCESS if the transfer has been started; +/// otherwise, the corresponding error status code. +/// \see USBDTransferBuffer, MblTransferCallback, USBD_MblReuse +//------------------------------------------------------------------------------ +char USBD_MblWrite( unsigned char bEndpoint, + void *pMbl, + unsigned short wListSize, + unsigned char bCircList, + unsigned short wStartNdx, + MblTransferCallback fCallback, + void *pArgument ) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + MblTransfer *pTransfer = (MblTransfer*)&(pEndpoint->transfer); + unsigned short i; + + // EP0 is not suitable for Mbl + if (bEndpoint == 0) { + + return USBD_STATUS_INVALID_PARAMETER; + } + + // Check that the endpoint is in Idle state + if (pEndpoint->state != UDP_ENDPOINT_IDLE) { + + return USBD_STATUS_LOCKED; + } + pEndpoint->state = UDP_ENDPOINT_SENDINGM; + + TRACE_DEBUG_WP("WriteM%d(0x%x,%d) ", bEndpoint, pMbl, wListSize); + + // Start from first if not circled list + if (!bCircList) wStartNdx = 0; + + // Setup the transfer descriptor + pTransfer->pMbl = (USBDTransferBuffer*)pMbl; + pTransfer->listSize = wListSize; + pTransfer->fCallback = fCallback; + pTransfer->pArgument = pArgument; + pTransfer->currBuffer = wStartNdx; + pTransfer->freedBuffer = 0; + pTransfer->pLastLoaded = &(((USBDTransferBuffer*)pMbl)[wStartNdx]); + pTransfer->circList = bCircList; + pTransfer->allUsed = 0; + + // Clear all buffer + for (i = 0; i < wListSize; i ++) { + + pTransfer->pMbl[i].transferred = 0; + pTransfer->pMbl[i].buffered = 0; + pTransfer->pMbl[i].remaining = pTransfer->pMbl[i].size; + } + + // Send the first packet + while((UDP->UDP_CSR[bEndpoint]&UDP_CSR_TXPKTRDY)==UDP_CSR_TXPKTRDY); + UDP_MblWriteFifo(bEndpoint); + SET_CSR(bEndpoint, UDP_CSR_TXPKTRDY); + + // If double buffering is enabled and there is data remaining, + // prepare another packet + if ((CHIP_USB_ENDPOINTS_BANKS(bEndpoint) > 1) + && (pTransfer->pMbl[pTransfer->currBuffer].remaining > 0)) { + + UDP_MblWriteFifo(bEndpoint); + } + + // Enable interrupt on endpoint + UDP->UDP_IER = 1 << bEndpoint; + + return USBD_STATUS_SUCCESS; +} + +//------------------------------------------------------------------------------ +/// Reads incoming data on an USB endpoint This methods sets the transfer +/// descriptor and activate the endpoint interrupt. The actual transfer is +/// then carried out by the endpoint interrupt handler. The Read operation +/// finishes either when the buffer is full, or a short packet (inferior to +/// endpoint maximum size) is received. +/// +/// *The buffer must be kept allocated until the transfer is finished*. +/// \param bEndpoint Endpoint number. +/// \param pData Pointer to a data buffer. +/// \param dLength Size of the data buffer in bytes. +/// \param fCallback Optional end-of-transfer callback function. +/// \param pArgument Optional argument to the callback function. +/// \return USBD_STATUS_SUCCESS if the read operation has been started; +/// otherwise, the corresponding error code. +//------------------------------------------------------------------------------ +char USBD_Read(unsigned char bEndpoint, + void *pData, + unsigned int dLength, + TransferCallback fCallback, + void *pArgument) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + Transfer *pTransfer = (Transfer*)&(pEndpoint->transfer); + + // Return if the endpoint is not in IDLE state + if (pEndpoint->state != UDP_ENDPOINT_IDLE) { + + return USBD_STATUS_LOCKED; + } + + // Endpoint enters Receiving state + pEndpoint->state = UDP_ENDPOINT_RECEIVING; + TRACE_DEBUG_WP("Read%d(%d) ", bEndpoint, dLength); + + // Set the transfer descriptor + pTransfer->pData = pData; + pTransfer->remaining = dLength; + pTransfer->buffered = 0; + pTransfer->transferred = 0; + pTransfer->fCallback = fCallback; + pTransfer->pArgument = pArgument; + + // Enable interrupt on endpoint + UDP->UDP_IER = 1 << bEndpoint; + + return USBD_STATUS_SUCCESS; +} + +//------------------------------------------------------------------------------ +/// Reuse first used/released buffer with new buffer address and size to be used +/// in transfer again. Only valid when frame list is ringed. Can be used for +/// both read & write. +/// \param bEndpoint Endpoint number. +/// \param pNewBuffer Pointer to new buffer with data to send (0 to keep last). +/// \param wNewSize Size of the data buffer +//------------------------------------------------------------------------------ +char USBD_MblReuse( unsigned char bEndpoint, + unsigned char *pNewBuffer, + unsigned short wNewSize ) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + MblTransfer *pTransfer = (MblTransfer*)&(pEndpoint->transfer); + USBDTransferBuffer *pBi = &(pTransfer->pMbl[pTransfer->freedBuffer]); + + TRACE_DEBUG_WP("MblReuse(%d), st%x, circ%d\n\r", + bEndpoint, pEndpoint->state, pTransfer->circList); + + // Only for Multi-buffer-circle list + if (bEndpoint != 0 + && (pEndpoint->state == UDP_ENDPOINT_RECEIVINGM + || pEndpoint->state == UDP_ENDPOINT_SENDINGM) + && pTransfer->circList) { + } + else { + + return USBD_STATUS_WRONG_STATE; + } + + // Check if there is freed buffer + if (pTransfer->freedBuffer == pTransfer->currBuffer + && !pTransfer->allUsed) { + + return USBD_STATUS_LOCKED; + } + + // Update transfer information + if ((++ pTransfer->freedBuffer) == pTransfer->listSize) + pTransfer->freedBuffer = 0; + if (pNewBuffer) { + pBi->pBuffer = pNewBuffer; + pBi->size = wNewSize; + } + pBi->buffered = 0; + pBi->transferred = 0; + pBi->remaining = pBi->size; + + // At least one buffer is not processed + pTransfer->allUsed = 0; + return USBD_STATUS_SUCCESS; +} + +//------------------------------------------------------------------------------ +/// Sets the HALT feature on the given endpoint (if not already in this state). +/// \param bEndpoint Endpoint number. +//------------------------------------------------------------------------------ +void USBD_Halt(unsigned char bEndpoint) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + + // Check that endpoint is enabled and not already in Halt state + if ((pEndpoint->state != UDP_ENDPOINT_DISABLED) + && (pEndpoint->state != UDP_ENDPOINT_HALTED)) { + + TRACE_DEBUG_WP("Halt%d ", bEndpoint); + + // Abort the current transfer if necessary + UDP_EndOfTransfer(bEndpoint, USBD_STATUS_ABORTED); + + // Put endpoint into Halt state + SET_CSR(bEndpoint, UDP_CSR_FORCESTALL); + pEndpoint->state = UDP_ENDPOINT_HALTED; + + // Enable the endpoint interrupt + UDP->UDP_IER = 1 << bEndpoint; + } +} + +//------------------------------------------------------------------------------ +/// Clears the Halt feature on the given endpoint. +/// \param bEndpoint Index of endpoint +//------------------------------------------------------------------------------ +void USBD_Unhalt(unsigned char bEndpoint) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + + // Check if the endpoint is enabled + if (pEndpoint->state != UDP_ENDPOINT_DISABLED) { + + TRACE_DEBUG_WP("Unhalt%d ", bEndpoint); + + // Return endpoint to Idle state + pEndpoint->state = UDP_ENDPOINT_IDLE; + + // Clear FORCESTALL flag + CLEAR_CSR(bEndpoint, UDP_CSR_FORCESTALL); + + // Reset Endpoint Fifos, beware this is a 2 steps operation + UDP->UDP_RST_EP |= 1 << bEndpoint; + UDP->UDP_RST_EP &= ~(1 << bEndpoint); + } +} + +//------------------------------------------------------------------------------ +/// Returns the current Halt status of an endpoint. +/// \param bEndpoint Index of endpoint +/// \return 1 if the endpoint is currently halted; otherwise 0 +//------------------------------------------------------------------------------ +unsigned char USBD_IsHalted(unsigned char bEndpoint) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + unsigned char status = 0; + + if (pEndpoint->state == UDP_ENDPOINT_HALTED) { + + status = 1; + } + return( status ); +} + +//------------------------------------------------------------------------------ +/// Indicates if the device is running in high or full-speed. Always returns 0 +/// since UDP does not support high-speed mode. +//------------------------------------------------------------------------------ +unsigned char USBD_IsHighSpeed(void) +{ + return 0; +} + +//------------------------------------------------------------------------------ +/// Causes the given endpoint to acknowledge the next packet it receives +/// with a STALL handshake. +/// \param bEndpoint Endpoint number. +/// \return USBD_STATUS_SUCCESS or USBD_STATUS_LOCKED. +//------------------------------------------------------------------------------ +unsigned char USBD_Stall(unsigned char bEndpoint) + +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + + // Check that endpoint is in Idle state + if (pEndpoint->state != UDP_ENDPOINT_IDLE) { + + TRACE_WARNING("UDP_Stall: Endpoint%d locked\n\r", bEndpoint); + return USBD_STATUS_LOCKED; + } + + TRACE_DEBUG_WP("Stall%d ", bEndpoint); + SET_CSR(bEndpoint, UDP_CSR_FORCESTALL); + + return USBD_STATUS_SUCCESS; +} + +//------------------------------------------------------------------------------ +/// Starts a remote wake-up procedure. +//------------------------------------------------------------------------------ +void USBD_RemoteWakeUp(void) +{ + // Device is NOT suspended + if (deviceState != USBD_STATE_SUSPENDED) { + + TRACE_WARNING("USBD_RemoteWakeUp: Device is not suspended\n\r"); + return; + } + + + UDP_EnablePeripheralClock(); + UDP_EnableUsbClock(); + UDP_EnableTransceiver(); + + TRACE_INFO_WP("RWUp "); + + // Activates a remote wakeup (edge on ESR), then clear ESR + UDP->UDP_GLB_STAT |= UDP_GLB_STAT_ESR; + UDP->UDP_GLB_STAT &= ~UDP_GLB_STAT_ESR; +} + +//------------------------------------------------------------------------------ +/// Sets the device address to the given value. +/// \param address New device address. +//------------------------------------------------------------------------------ +void USBD_SetAddress(unsigned char address) +{ + TRACE_INFO_WP("SetAddr(%d) ", address); + + // Set address + UDP->UDP_FADDR = UDP_FADDR_FEN | (address & UDP_FADDR_FADD); + + // If the address is 0, the device returns to the Default state + if (address == 0) { + + UDP->UDP_GLB_STAT = 0; + deviceState = USBD_STATE_DEFAULT; + } + // If the address is non-zero, the device enters the Address state + else { + + UDP->UDP_GLB_STAT = UDP_GLB_STAT_FADDEN; + deviceState = USBD_STATE_ADDRESS; + } +} + +//------------------------------------------------------------------------------ +/// Sets the current device configuration. +/// \param cfgnum - Configuration number to set. +//------------------------------------------------------------------------------ +void USBD_SetConfiguration(unsigned char cfgnum) +{ + TRACE_INFO_WP("SetCfg(%d) ", cfgnum); + + // If the configuration number if non-zero, the device enters the + // Configured state + if (cfgnum != 0) { + + // Enter Configured state + deviceState = USBD_STATE_CONFIGURED; + UDP->UDP_GLB_STAT |= UDP_GLB_STAT_CONFG; + } + // If the configuration number is zero, the device goes back to the Address + // state + else { + + deviceState = USBD_STATE_ADDRESS; + UDP->UDP_GLB_STAT = UDP_FADDR_FEN; + + // Abort all transfers + UDP_DisableEndpoints(); + } +} + +//------------------------------------------------------------------------------ +/// Connects the pull-up on the D+ line of the USB. +//------------------------------------------------------------------------------ +void USBD_Connect(void) +{ + unsigned char dis = UDP_EnablePeripheralClock(); + + TRACE_DEBUG("Conn "); + UDP->UDP_TXVC |= UDP_TXVC_PUON; + + if (dis) UDP_DisablePeripheralClock(); +} + +//------------------------------------------------------------------------------ +/// Disconnects the pull-up from the D+ line of the USB. +//------------------------------------------------------------------------------ +void USBD_Disconnect(void) +{ + unsigned char dis = UDP_EnablePeripheralClock(); + + TRACE_DEBUG("Disc "); + UDP->UDP_TXVC &= ~UDP_TXVC_PUON; + + if (dis) UDP_DisablePeripheralClock(); + + // Device returns to the Powered state + if (deviceState > USBD_STATE_POWERED) { + + deviceState = USBD_STATE_POWERED; + } + + if (previousDeviceState > USBD_STATE_POWERED) { + + previousDeviceState = USBD_STATE_POWERED; + } +} + +//------------------------------------------------------------------------------ +/// Initializes the USB driver. +//------------------------------------------------------------------------------ +void USBD_Init(void) +{ + TRACE_INFO_WP("USBD_Init\n\r"); + // Reset endpoint structures + UDP_ResetEndpoints(); + + // Must before TXVC access! + UDP_EnablePeripheralClock(); + + // Configure the pull-up on D+ and disconnect it + UDP->UDP_TXVC &= ~UDP_TXVC_PUON; + + // Device is in the Attached state + deviceState = USBD_STATE_SUSPENDED; + previousDeviceState = USBD_STATE_POWERED; + UDP_EnableUsbClock(); + + UDP->UDP_IDR = 0xFE; + + UDP->UDP_IER = UDP_IER_WAKEUP; + + // Configure interrupts + USBDCallbacks_Initialized(); +} + +//------------------------------------------------------------------------------ +/// Configure USB Speed, should be invoked before USB attachment. +/// \param forceFS Force to use FS mode. +//------------------------------------------------------------------------------ +void USBD_ConfigureSpeed(unsigned char forceFS) +{ +} + +//------------------------------------------------------------------------------ +/// Returns the current state of the USB device. +/// \return Device current state. +//------------------------------------------------------------------------------ +unsigned char USBD_GetState(void) +{ + return deviceState; +} + diff --git a/radio/bootloader/usb/device/massstorage/MSD.h b/radio/bootloader/usb/device/massstorage/MSD.h new file mode 100644 index 000000000..23a934d35 --- /dev/null +++ b/radio/bootloader/usb/device/massstorage/MSD.h @@ -0,0 +1,233 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// !Purpose +/// +/// Mass Storage class definitions. +/// +/// See +/// - +/// USB Mass Storage Class Spec. Overview +/// - +/// USB Mass Storage Class Bulk-Only Transport +/// +/// !Usage +/// +/// -# Uses "MSD Requests" to check incoming requests from USB Host. +/// -# Uses "MSD Subclass Codes" and "MSD Protocol Codes" to fill %device +/// interface descriptors for a MSD %device. +/// -# Handle the incoming Bulk data with "MSD CBW Definitions" and MSCbw +/// structure. +/// -# Prepare the outgoing Bulk data with "MSD CSW Definitions" and MSCsw +/// structure. +//------------------------------------------------------------------------------ + +#ifndef MSD_H +#define MSD_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "MSD Requests" +/// This page lists MSD-specific requests ( Actually for Bulk-only protocol ). +/// +/// !Requests +/// - MSD_BULK_ONLY_RESET +/// - MSD_GET_MAX_LUN + +/// Reset the mass storage %device and its associated interface. +#define MSD_BULK_ONLY_RESET 0xFF +/// Return the maximum LUN number supported by the %device. +#define MSD_GET_MAX_LUN 0xFE +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "MSD Subclass Codes" +/// This page lists the Subclass Codes for bInterfaceSubClass field. +/// (Table 2.1, USB Mass Storage Class Spec. Overview) +/// +/// !SubClasses +/// - MSD_SUBCLASS_RBC +/// - MSD_SUBCLASS_SFF_MCC +/// - MSD_SUBCLASS_QIC +/// - MSD_SUBCLASS_UFI +/// - MSD_SUBCLASS_SFF +/// - MSD_SUBCLASS_SCSI + +/// Reduced Block Commands (RBC) T10 +#define MSD_SUBCLASS_RBC 0x01 +/// C/DVD devices +#define MSD_SUBCLASS_SFF_MCC 0x02 +/// Tape device +#define MSD_SUBCLASS_QIC 0x03 +/// Floppy disk drive (FDD) device +#define MSD_SUBCLASS_UFI 0x04 +/// Floppy disk drive (FDD) device +#define MSD_SUBCLASS_SFF 0x05 +/// SCSI transparent command set +#define MSD_SUBCLASS_SCSI 0x06 +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +/// \page "MSD Protocol Codes" +/// This page lists the Transport Protocol codes for MSD. +/// (Table 3.1, USB Mass Storage Class Spec. Overview) +/// +/// !Protocols +/// - MSD_PROTOCOL_CBI_COMPLETION +/// - MSD_PROTOCOL_CBI +/// - MSD_PROTOCOL_BULK_ONLY + +/// Control/Bulk/Interrupt (CBI) Transport (with command complete interrupt) +#define MSD_PROTOCOL_CBI_COMPLETION 0x00 +/// Control/Bulk/Interrupt (CBI) Transport (no command complete interrupt) +#define MSD_PROTOCOL_CBI 0x01 +/// Bulk-Only Transport +#define MSD_PROTOCOL_BULK_ONLY 0x50 +//------------------------------------------------------------------------------ + +/// Test unit control: +#define CTRL_NOT_READY 0x00 +#define CTRL_GOOD 0x01 +#define CTRL_BUSY 0x02 + +//------------------------------------------------------------------------------ +/// \page "MSD CBW Definitions" +/// This page lists the Command Block Wrapper (CBW) definitions. +/// +/// !Constants +/// - MSD_CBW_SIZE +/// - MSD_CBW_SIGNATURE +/// +/// !Fields +/// - MSD_CBW_DEVICE_TO_HOST + +/// Command Block Wrapper Size +#define MSD_CBW_SIZE 31 +/// 'USBC' 0x43425355 +#define MSD_CBW_SIGNATURE 0x43425355 + +/// CBW bmCBWFlags field +#define MSD_CBW_DEVICE_TO_HOST (1 << 7) +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "MSD CSW Definitions" +/// This page lists the Command Status Wrapper (CSW) definitions. +/// +/// !Constants +/// - MSD_CSW_SIZE +/// - MSD_CSW_SIGNATURE +/// +/// !Command Block Status Values +/// (Table 5.3 , USB Mass Storage Class Bulk-Only Transport) +/// - MSD_CSW_COMMAND_PASSED +/// - MSD_CSW_COMMAND_FAILED +/// - MSD_CSW_PHASE_ERROR + +/// Command Status Wrapper Size +#define MSD_CSW_SIZE 13 +/// 'USBS' 0x53425355 +#define MSD_CSW_SIGNATURE 0x53425355 + +/// Command Passed (good status) +#define MSD_CSW_COMMAND_PASSED 0 +/// Command Failed +#define MSD_CSW_COMMAND_FAILED 1 +/// Phase Error +#define MSD_CSW_PHASE_ERROR 2 +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Structures +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Command Block Wrapper (CBW), +/// See Table 5.1, USB Mass Storage Class Bulk-Only Transport. +/// +/// The CBW shall start on a packet boundary and shall end as a +/// short packet with exactly 31 (1Fh) bytes transferred. +//------------------------------------------------------------------------------ +typedef struct { + + /// 'USBC' 0x43425355 (little endian) + unsigned int dCBWSignature; + /// Must be the same as dCSWTag + unsigned int dCBWTag; + /// Number of bytes transfer + unsigned int dCBWDataTransferLength; + /// Indicates the directin of the transfer: + /// 0x80=IN=device-to-host, + /// 0x00=OUT=host-to-device + unsigned char bmCBWFlags; + /// bits 0->3: bCBWLUN + unsigned char bCBWLUN :4, + bReserved1:4; /// reserved + /// bits 0->4: bCBWCBLength + unsigned char bCBWCBLength:5, + bReserved2 :3; /// reserved + /// Command block + unsigned char pCommand[16]; + +} MSCbw; + +//------------------------------------------------------------------------------ +/// Command Status Wrapper (CSW), +/// See Table 5.2, USB Mass Storage Class Bulk-Only Transport. +//------------------------------------------------------------------------------ +typedef struct +{ + /// 'USBS' 0x53425355 (little endian) + unsigned int dCSWSignature; + /// Must be the same as dCBWTag + unsigned int dCSWTag; + /// For Data-Out the device shall report in the dCSWDataResidue the + /// difference between the amount of data expected as stated in the + /// dCBWDataTransferLength, and the actual amount of data processed by + /// the device. For Data-In the device shall report in the dCSWDataResidue + /// the difference between the amount of data expected as stated in the + /// dCBWDataTransferLength and the actual amount of relevant data sent by + /// the device. The dCSWDataResidue shall not exceed the value sent in the + /// dCBWDataTransferLength. + unsigned int dCSWDataResidue; + /// Indicates the success or failure of the command. + unsigned char bCSWStatus; + +} MSCsw; + +#endif //#ifndef MSD_H + diff --git a/radio/bootloader/usb/device/massstorage/MSDDStateMachine.c b/radio/bootloader/usb/device/massstorage/MSDDStateMachine.c new file mode 100644 index 000000000..849440730 --- /dev/null +++ b/radio/bootloader/usb/device/massstorage/MSDDStateMachine.c @@ -0,0 +1,609 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- + +#include "SBCMethods.h" +#include "MSDDStateMachine.h" + +//----------------------------------------------------------------------------- +// Internal functions +//----------------------------------------------------------------------------- +//----------------------------------------------------------------------------- +/// Returns the expected transfer length and direction (IN, OUT or don't care) +/// from the host point-of-view. +/// \param cbw Pointer to the CBW to examinate +/// \param pLength Expected length of command +/// \param pType Expected direction of command +//----------------------------------------------------------------------------- +static void MSDD_GetCommandInformation(MSCbw *cbw, + unsigned int *length, + unsigned char *type) +{ + // Expected host transfer direction and length + (*length) = cbw->dCBWDataTransferLength; + + if (*length == 0) { + + (*type) = MSDD_NO_TRANSFER; + } + else if ((cbw->bmCBWFlags & MSD_CBW_DEVICE_TO_HOST) != 0) { + + (*type) = MSDD_DEVICE_TO_HOST; + } + else { + + (*type) = MSDD_HOST_TO_DEVICE; + } +} + +//----------------------------------------------------------------------------- +/// Pre-processes a command by checking the differences between the host and +/// device expectations in term of transfer type and length. +/// Once one of the thirteen cases is identified, the actions to do during the +/// post-processing phase are stored in the dCase variable of the command +/// state. +/// \param pMsdDriver Pointer to a MSDDriver instance +/// \return 1 if the command is supported, false otherwise +//----------------------------------------------------------------------------- +static unsigned char MSDD_PreProcessCommand(MSDDriver *pMsdDriver) +{ + unsigned int hostLength = 0; + unsigned int deviceLength = 0; + unsigned char hostType; + unsigned char deviceType; + unsigned char isCommandSupported; + MSDCommandState *commandState = &(pMsdDriver->commandState); + MSCsw *csw = &(commandState->csw); + MSCbw *cbw = &(commandState->cbw); + MSDLun *lun = &(pMsdDriver->luns[(unsigned char) cbw->bCBWLUN]); + + // Get information about the command + // Host-side + MSDD_GetCommandInformation(cbw, &hostLength, &hostType); + + // Device-side + isCommandSupported = SBC_GetCommandInformation(cbw->pCommand, + &deviceLength, + &deviceType, + lun); + + // Initialize data residue and result status + csw->dCSWDataResidue = 0; + csw->bCSWStatus = MSD_CSW_COMMAND_PASSED; + + // Check if the command is supported + if (isCommandSupported) { + + // Identify the command case + if(hostType == MSDD_NO_TRANSFER) { + + // Case 1 (Hn = Dn) + if(deviceType == MSDD_NO_TRANSFER) { + + //TRACE_WARNING("Case 1\n\r"); + commandState->postprocess = 0; + commandState->length = 0; + } + else if(deviceType == MSDD_DEVICE_TO_HOST) { + + // Case 2 (Hn < Di) + TRACE_WARNING( + "MSDD_PreProcessCommand: Case 2\n\r"); + commandState->postprocess = MSDD_CASE_PHASE_ERROR; + commandState->length = 0; + } + else { //if(deviceType == MSDD_HOST_TO_DEVICE) { + + // Case 3 (Hn < Do) + TRACE_WARNING( + "MSDD_PreProcessCommand: Case 3\n\r"); + commandState->postprocess = MSDD_CASE_PHASE_ERROR; + commandState->length = 0; + } + } + + // Case 4 (Hi > Dn) + else if(hostType == MSDD_DEVICE_TO_HOST) { + + if(deviceType == MSDD_NO_TRANSFER) { + + TRACE_WARNING( + "MSDD_PreProcessCommand: Case 4\n\r"); + commandState->postprocess = MSDD_CASE_STALL_IN; + commandState->length = 0; + csw->dCSWDataResidue = hostLength; + } + else if(deviceType == MSDD_DEVICE_TO_HOST) { + + TRACE_ERROR("cmd=0x%0x h=%d d=%d", cbw->pCommand[0], hostLength, deviceLength); + + if(hostLength > deviceLength) { + + // Case 5 (Hi > Di) + TRACE_WARNING( + "MSDD_PreProcessCommand: Case 5\n\r"); + commandState->postprocess = MSDD_CASE_STALL_IN; + commandState->length = deviceLength; + csw->dCSWDataResidue = hostLength - deviceLength; + } + else if(hostLength == deviceLength) { + + // Case 6 (Hi = Di) + commandState->postprocess = 0; + commandState->length = deviceLength; + } + else { //if(hostLength < deviceLength) { + + // Case 7 (Hi < Di) + TRACE_WARNING( + "MSDD_PreProcessCommand: Case 7\n\r"); + commandState->postprocess = MSDD_CASE_PHASE_ERROR; + commandState->length = hostLength; + } + } + else { //if(deviceType == MSDD_HOST_TO_DEVICE) { + + // Case 8 (Hi <> Do) + TRACE_WARNING( + "MSDD_PreProcessCommand: Case 8\n\r"); + commandState->postprocess = + MSDD_CASE_STALL_IN | MSDD_CASE_PHASE_ERROR; + commandState->length = 0; + } + } + else if(hostType == MSDD_HOST_TO_DEVICE) { + + if(deviceType == MSDD_NO_TRANSFER) { + + // Case 9 (Ho > Dn) + TRACE_WARNING( + "MSDD_PreProcessCommand: Case 9\n\r"); + commandState->postprocess = MSDD_CASE_STALL_OUT; + commandState->length = 0; + csw->dCSWDataResidue = hostLength; + } + else if(deviceType == MSDD_DEVICE_TO_HOST) { + + // Case 10 (Ho <> Di) + TRACE_WARNING( + "MSDD_PreProcessCommand: Case 10\n\r"); + commandState->postprocess = + MSDD_CASE_STALL_OUT | MSDD_CASE_PHASE_ERROR; + commandState->length = 0; + } + else { //if(deviceType == MSDD_HOST_TO_DEVICE) { + + if(hostLength > deviceLength) { + + // Case 11 (Ho > Do) + TRACE_WARNING( + "MSDD_PreProcessCommand: Case 11\n\r"); + commandState->postprocess = MSDD_CASE_STALL_OUT; +// commandState->length = deviceLength; +// csw->dCSWDataResidue = hostLength - deviceLength; + commandState->length = 0; + csw->dCSWDataResidue = deviceLength; + } + else if(hostLength == deviceLength) { + + // Case 12 (Ho = Do) + //TRACE_WARNING( + // "MSDD_PreProcessCommand: Case 12\n\r"); + commandState->postprocess = 0; + commandState->length = deviceLength; + } + else { //if(hostLength < deviceLength) { + + // Case 13 (Ho < Do) + TRACE_WARNING( + "MSDD_PreProcessCommand: Case 13\n\r"); + commandState->postprocess = MSDD_CASE_PHASE_ERROR; + commandState->length = hostLength; + } + } + } + } + + return isCommandSupported; +} + +//----------------------------------------------------------------------------- +/// Post-processes a command given the case identified during the +/// pre-processing step. +/// Depending on the case, one of the following actions can be done: +/// - Bulk IN endpoint is stalled +/// - Bulk OUT endpoint is stalled +/// - CSW status set to phase error +/// \param pMsdDriver Pointer to a MSDDriver instance +/// \return If the device is halted +//----------------------------------------------------------------------------- +static unsigned char MSDD_PostProcessCommand(MSDDriver *pMsdDriver) +{ + MSDCommandState *commandState = &(pMsdDriver->commandState); + MSCsw *csw = &(commandState->csw); + unsigned char haltStatus = 0; + + // STALL Bulk IN endpoint ? + if ((commandState->postprocess & MSDD_CASE_STALL_IN) != 0) { + + TRACE_INFO_WP("StallIn "); + MSDD_Halt(MSDD_CASE_STALL_IN); + haltStatus = 1; + } + + // STALL Bulk OUT endpoint ? + if ((commandState->postprocess & MSDD_CASE_STALL_OUT) != 0) { + + TRACE_INFO_WP("StallOut "); + MSDD_Halt(MSDD_CASE_STALL_OUT); + haltStatus = 1; + } + + // Set CSW status code to phase error ? + if ((commandState->postprocess & MSDD_CASE_PHASE_ERROR) != 0) { + + TRACE_INFO_WP("PhaseErr "); + csw->bCSWStatus = MSD_CSW_PHASE_ERROR; + } + + return haltStatus; +} + +//----------------------------------------------------------------------------- +/// Processes the latest command received by the %device. +/// \param pMsdDriver Pointer to a MSDDriver instance +/// \return 1 if the command has been completed, false otherwise. +//----------------------------------------------------------------------------- +static unsigned char MSDD_ProcessCommand(MSDDriver * pMsdDriver) +{ + unsigned char status; + MSDCommandState *commandState = &(pMsdDriver->commandState); + MSCbw *cbw = &(commandState->cbw); + MSCsw *csw = &(commandState->csw); + MSDLun *lun = &(pMsdDriver->luns[(unsigned char) cbw->bCBWLUN]); + unsigned char isCommandComplete = 0; + + // Check if LUN is valid + if (cbw->bCBWLUN > pMsdDriver->maxLun) { + + TRACE_WARNING( + "MSDD_ProcessCommand: LUN %d not exist\n\r", cbw->bCBWLUN); + status = MSDD_STATUS_ERROR; + } + else { + + // Process command + if (pMsdDriver->maxLun > 0) { + + TRACE_INFO_WP("LUN%d ", cbw->bCBWLUN); + } + + status = SBC_ProcessCommand(lun, commandState); + } + + // Check command result code + if (status == MSDD_STATUS_PARAMETER) { + + TRACE_WARNING( + "MSDD_ProcessCommand: Unknown cmd 0x%02X\n\r", + cbw->pCommand[0]); + + // Update sense data + SBC_UpdateSenseData(&(lun->requestSenseData), + SBC_SENSE_KEY_ILLEGAL_REQUEST, + SBC_ASC_INVALID_FIELD_IN_CDB, + 0); + + // Result codes + csw->bCSWStatus = MSD_CSW_COMMAND_FAILED; + isCommandComplete = 1; + + // stall the request, IN or OUT + if (((cbw->bmCBWFlags & MSD_CBW_DEVICE_TO_HOST) == 0) + && (cbw->dCBWDataTransferLength > 0)) { + + // Stall the OUT endpoint : host to device + // MSDD_Halt(MSDD_CASE_STALL_OUT); + commandState->postprocess = MSDD_CASE_STALL_OUT; + TRACE_INFO_WP("StaOUT "); + } + else { + + // Stall the IN endpoint : device to host + // MSDD_Halt(MSDD_CASE_STALL_IN); + commandState->postprocess = MSDD_CASE_STALL_IN; + TRACE_INFO_WP("StaIN "); + } + } + else if (status == MSDD_STATUS_ERROR) { + + TRACE_WARNING("MSD_ProcessCommand: Cmd %x fail\n\r", + ((SBCCommand*)commandState->cbw.pCommand)->bOperationCode); + + // Update sense data + SBC_UpdateSenseData(&(lun->requestSenseData), + SBC_SENSE_KEY_MEDIUM_ERROR, + SBC_ASC_INVALID_FIELD_IN_CDB, + 0); + + // Result codes + csw->bCSWStatus = MSD_CSW_COMMAND_FAILED; + isCommandComplete = 1; + } + else if (status == MSDD_STATUS_RW) { + + csw->bCSWStatus = MSD_CSW_COMMAND_FAILED; + isCommandComplete = 1; + } + else { + + // Update sense data + SBC_UpdateSenseData(&(lun->requestSenseData), + SBC_SENSE_KEY_NO_SENSE, + 0, + 0); + + // Is command complete ? + if (status == MSDD_STATUS_SUCCESS) { + + isCommandComplete = 1; + } + } + + // Check if command has been completed + if (isCommandComplete) { + + TRACE_INFO_WP("Cplt "); + + // Adjust data residue + if (commandState->length != 0) { + + csw->dCSWDataResidue += commandState->length; + + // STALL the endpoint waiting for data + if ((cbw->bmCBWFlags & MSD_CBW_DEVICE_TO_HOST) == 0) { + + // Stall the OUT endpoint : host to device + // MSDD_Halt(MSDD_CASE_STALL_OUT); + commandState->postprocess = MSDD_CASE_STALL_OUT; + TRACE_INFO_WP("StaOUT "); + } + else { + + // Stall the IN endpoint : device to host + // MSDD_Halt(MSDD_CASE_STALL_IN); + commandState->postprocess = MSDD_CASE_STALL_IN; + TRACE_INFO_WP("StaIN "); + } + } + + // Reset command state + commandState->state = 0; + } + + return isCommandComplete; +} + +//----------------------------------------------------------------------------- +/// State machine for the MSD %device driver +/// \param pMsdDriver Pointer to a MSDDriver instance +//----------------------------------------------------------------------------- +void MSDD_StateMachine(MSDDriver * pMsdDriver) +{ + MSDCommandState *commandState = &(pMsdDriver->commandState); + MSCbw *cbw = &(commandState->cbw); + MSCsw *csw = &(commandState->csw); + MSDTransfer *transfer = &(commandState->transfer); + unsigned char status; + + // Identify current driver state + switch (pMsdDriver->state) { + //---------------------- + case MSDD_STATE_READ_CBW: + //---------------------- + // Start the CBW read operation + transfer->semaphore = 0; + status = MSDD_Read(cbw, + MSD_CBW_SIZE, + (TransferCallback) MSDDriver_Callback, + (void *) transfer); + + // Check operation result code + if (status == USBD_STATUS_SUCCESS) { + + // If the command was successful, wait for transfer + pMsdDriver->state = MSDD_STATE_WAIT_CBW; + } + break; + + //---------------------- + case MSDD_STATE_WAIT_CBW: + //---------------------- + // Check transfer semaphore + if (transfer->semaphore > 0) { + + // Take semaphore and terminate transfer + transfer->semaphore--; + + // Check if transfer was successful + if (transfer->status == USBD_STATUS_SUCCESS) { + + TRACE_INFO_WP("------------------------------\n\r"); + + // Process received command + pMsdDriver->state = MSDD_STATE_PROCESS_CBW; + } + else if (transfer->status == USBD_STATUS_RESET) { + + TRACE_INFO("MSDD_StateMachine: EP resetted\n\r"); + pMsdDriver->state = MSDD_STATE_READ_CBW; + } + else { + + TRACE_WARNING( + "MSDD_StateMachine: Failed to read CBW\n\r"); + pMsdDriver->state = MSDD_STATE_READ_CBW; + } + } + break; + + //------------------------- + case MSDD_STATE_PROCESS_CBW: + //------------------------- + // Check if this is a new command + if (commandState->state == 0) { + + // Copy the CBW tag + csw->dCSWTag = cbw->dCBWTag; + + // Check that the CBW is 31 bytes long + if ((transfer->transferred != MSD_CBW_SIZE) || + (transfer->remaining != 0)) { + + TRACE_WARNING( + "MSDD_StateMachine: Invalid CBW (len %d)\n\r", + (int)transfer->transferred); + + // Wait for a reset recovery + pMsdDriver->waitResetRecovery = 1; + + // Halt the Bulk-IN and Bulk-OUT pipes + MSDD_Halt(MSDD_CASE_STALL_OUT | MSDD_CASE_STALL_IN); + + csw->bCSWStatus = MSD_CSW_COMMAND_FAILED; + pMsdDriver->state = MSDD_STATE_READ_CBW; + + } + // Check the CBW Signature + else if (cbw->dCBWSignature != MSD_CBW_SIGNATURE) { + + TRACE_WARNING( + "MSD_BOTStateMachine: Invalid CBW (Bad signature)\n\r"); + + // Wait for a reset recovery + pMsdDriver->waitResetRecovery = 1; + + // Halt the Bulk-IN and Bulk-OUT pipes + MSDD_Halt(MSDD_CASE_STALL_OUT | MSDD_CASE_STALL_IN); + + csw->bCSWStatus = MSD_CSW_COMMAND_FAILED; + pMsdDriver->state = MSDD_STATE_READ_CBW; + } + else { + + // Pre-process command + MSDD_PreProcessCommand(pMsdDriver); + } + } + + // Process command + if (csw->bCSWStatus == MSDD_STATUS_SUCCESS) { + + if (MSDD_ProcessCommand(pMsdDriver)) { + + // Post-process command if it is finished + if (MSDD_PostProcessCommand(pMsdDriver)) { + + TRACE_INFO_WP("WaitHALT "); + pMsdDriver->state = MSDD_STATE_WAIT_HALT; + } + else { + + pMsdDriver->state = MSDD_STATE_SEND_CSW; + } + } + TRACE_INFO_WP("\n\r"); + } + + break; + + //---------------------- + case MSDD_STATE_SEND_CSW: + //---------------------- + // Set signature + csw->dCSWSignature = MSD_CSW_SIGNATURE; + + // Start the CSW write operation + status = MSDD_Write(csw, + MSD_CSW_SIZE, + (TransferCallback) MSDDriver_Callback, + (void *) transfer); + + // Check operation result code + if (status == USBD_STATUS_SUCCESS) { + + TRACE_INFO_WP("SendCSW "); + + // Wait for end of transfer + pMsdDriver->state = MSDD_STATE_WAIT_CSW; + } + break; + + //---------------------- + case MSDD_STATE_WAIT_CSW: + //---------------------- + // Check transfer semaphore + if (transfer->semaphore > 0) { + + // Take semaphore and terminate transfer + transfer->semaphore--; + + // Check if transfer was successful + if (transfer->status == USBD_STATUS_RESET) { + + TRACE_INFO("MSDD_StateMachine: EP resetted\n\r"); + } + else if (transfer->status == USBD_STATUS_ABORTED) { + + TRACE_WARNING( + "MSDD_StateMachine: Failed to send CSW\n\r"); + } + else { + + TRACE_INFO_WP("ok"); + } + + // Read new CBW + pMsdDriver->state = MSDD_STATE_READ_CBW; + } + break; + + //---------------------- + case MSDD_STATE_WAIT_HALT: + //---------------------- + if (MSDD_IsHalted() == 0) { + + pMsdDriver->state = MSDD_STATE_SEND_CSW; + } + break; + } +} diff --git a/radio/bootloader/usb/device/massstorage/MSDDStateMachine.h b/radio/bootloader/usb/device/massstorage/MSDDStateMachine.h new file mode 100644 index 000000000..ad096d83d --- /dev/null +++ b/radio/bootloader/usb/device/massstorage/MSDDStateMachine.h @@ -0,0 +1,264 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//----------------------------------------------------------------------------- +/// \unit +/// !Purpose +/// +/// Definitions, structs, functions required by a Mass Storage device driver +/// state machine.. +/// +/// !Usage +/// +/// - For a USB device: +/// -# MSDD_Write, MSDD_Read, MSDD_Halt should be defined for +/// usage in the state machine procedure. +/// +/// -# MSDD_StateMachine is invoked to run the MSD state machine. +/// +//----------------------------------------------------------------------------- + +#ifndef MSDDSTATEMACHINE_H +#define MSDDSTATEMACHINE_H + +//----------------------------------------------------------------------------- +// Headers +//----------------------------------------------------------------------------- + +#include "MSD.h" +#include "MSDLun.h" +#include "debug.h" + +//----------------------------------------------------------------------------- +// Definitions +//----------------------------------------------------------------------------- + +//------------------------------------------------------------------------------ +/// \page "MSD Driver Possible states" +/// ... +/// +/// !States +/// - MSDD_STATE_READ_CBW +/// - MSDD_STATE_WAIT_CBW +/// - MSDD_STATE_PROCESS_CBW +/// - MSDD_STATE_WAIT_HALT +/// - MSDD_STATE_SEND_CSW +/// - MSDD_STATE_WAIT_CSW +/// - MSDD_STATE_WAIT_RESET + +//! \brief Driver is expecting a command block wrapper +#define MSDD_STATE_READ_CBW (1 << 0) + +//! \brief Driver is waiting for the transfer to finish +#define MSDD_STATE_WAIT_CBW (1 << 1) + +//! \brief Driver is processing the received command +#define MSDD_STATE_PROCESS_CBW (1 << 2) + +//! \brief Driver is halted because pipe halt or wait reset +#define MSDD_STATE_WAIT_HALT (1 << 3) + +//! \brief Driver is starting the transmission of a command status wrapper +#define MSDD_STATE_SEND_CSW (1 << 4) + +//! \brief Driver is waiting for the CSW transmission to finish +#define MSDD_STATE_WAIT_CSW (1 << 5) + +//! \brief Driver is waiting for the MassStorageReset +#define MSDD_STATE_WAIT_RESET (1 << 6) +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "MSD Driver Result Codes" +/// This page lists result codes for MSD functions. +/// +/// !Codes +/// - MSDD_STATUS_SUCCESS +/// - MSDD_STATUS_ERROR +/// - MSDD_STATUS_INCOMPLETE +/// - MSDD_STATUS_PARAMETER +/// - MSDD_STATUS_RW + +//! \brief Method was successful +#define MSDD_STATUS_SUCCESS 0x00 + +//! \brief There was an error when trying to perform a method +#define MSDD_STATUS_ERROR 0x01 + +//! \brief No error was encountered but the application should call the +//! method again to continue the operation +#define MSDD_STATUS_INCOMPLETE 0x02 + +//! \brief A wrong parameter has been passed to the method +#define MSDD_STATUS_PARAMETER 0x03 + +//! \brief An error when reading/writing disk (protected or not present) +#define MSDD_STATUS_RW 0x04 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "MSD Driver Action Cases" +/// This page lists actions to perform during the post-processing phase of a +/// command. +/// +/// !Actions +/// - MSDD_CASE_PHASE_ERROR +/// - MSDD_CASE_STALL_IN +/// - MSDD_CASE_STALL_OUT + +//! \brief Indicates that the CSW should report a phase error +#define MSDD_CASE_PHASE_ERROR (1 << 0) + +//! \brief The driver should halt the Bulk IN pipe after the transfer +#define MSDD_CASE_STALL_IN (1 << 1) + +//! \brief The driver should halt the Bulk OUT pipe after the transfer +#define MSDD_CASE_STALL_OUT (1 << 2) + +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "MSD Driver Xfr Directions" +/// This page lists possible direction values for a data transfer +/// +/// !Directions +/// - MSDD_DEVICE_TO_HOST +/// - MSDD_HOST_TO_DEVICE +/// - MSDD_NO_TRANSFER + +#define MSDD_DEVICE_TO_HOST 0 +#define MSDD_HOST_TO_DEVICE 1 +#define MSDD_NO_TRANSFER 2 +//------------------------------------------------------------------------------ + +//----------------------------------------------------------------------------- +// Types +//----------------------------------------------------------------------------- + +//------------------------------------------------------------------------------ +//! \brief Structure for holding the result of a USB transfer +//! \see MSDDriver_Callback +//------------------------------------------------------------------------------ +typedef struct { + + volatile unsigned int transferred; /// Number of bytes transferred + volatile unsigned int remaining; /// Number of bytes not transferred + volatile unsigned short semaphore; /// Semaphore to indicate transfer completion + volatile unsigned short status; /// Operation result code + +} MSDTransfer; + +//------------------------------------------------------------------------------ +//! \brief Status of an executing command +//! \see MSDCbw +//! \see MSDCsw +//! \see MSDTransfer +//------------------------------------------------------------------------------ +typedef struct { + + MSDTransfer transfer; /// Current transfer status (USB) + MSDTransfer disktransfer;/// Current transfer status (Disk) + unsigned int length; /// Remaining length of command + MSCbw cbw; /// Received CBW (31 bytes) + unsigned char state; /// Current command state + MSCsw csw; /// CSW to send (13 bytes) + unsigned char postprocess; /// Actions to perform when command is complete + +} MSDCommandState; + +//------------------------------------------------------------------------------ +/// \brief MSD driver state variables +/// \see MSDCommandState +/// \see MSDLun +//------------------------------------------------------------------------------ +typedef struct { + + /// LUN list for the %device. + MSDLun *luns; + /// State of the currently executing command + MSDCommandState commandState; + /// Maximum LUN index + unsigned char maxLun; + /// Current state of the driver + unsigned char state; + /// Indicates if the driver is waiting for a reset recovery + unsigned char waitResetRecovery; + +} MSDDriver; + +//----------------------------------------------------------------------------- +// Inline functions +//----------------------------------------------------------------------------- +//----------------------------------------------------------------------------- +/// This function is to be used as a callback for USB or LUN transfers. +/// \param transfer Pointer to the transfer structure to update +/// \param status Operation result code +/// \param transferred Number of bytes transferred by the command +/// \param remaining Number of bytes not transferred +//----------------------------------------------------------------------------- +static inline void MSDDriver_Callback(MSDTransfer *transfer, + unsigned char status, + unsigned int transferred, + unsigned int remaining) +{ + TRACE_DEBUG("Cbk "); + transfer->semaphore++; + transfer->status = status; + transfer->transferred = transferred; + transfer->remaining = remaining; +} + +//----------------------------------------------------------------------------- +// Driver functions +//----------------------------------------------------------------------------- +//- MSD General support function +extern char MSDD_Read( + void* pData, + unsigned int dLength, + TransferCallback fCallback, + void* pArgument); + +extern char MSDD_Write( + void* pData, + unsigned int dLength, + TransferCallback fCallback, + void* pArgument); + +extern void MSDD_Halt(unsigned int stallCase); + +extern unsigned int MSDD_IsHalted(void); + +//----------------------------------------------------------------------------- +// Exported functions +//----------------------------------------------------------------------------- + +extern void MSDD_StateMachine(MSDDriver * pMsdDriver); + +#endif // #define MSDDSTATEMACHINE_H + diff --git a/radio/bootloader/usb/device/massstorage/MSDDriver.c b/radio/bootloader/usb/device/massstorage/MSDDriver.c new file mode 100644 index 000000000..a93c85f94 --- /dev/null +++ b/radio/bootloader/usb/device/massstorage/MSDDriver.c @@ -0,0 +1,343 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include +#include "MSDDriver.h" +#include "MSDDriverDescriptors.h" +#include "SBCMethods.h" +#include "debug.h" +#include +#include +#include +#include +#include +#include + +//----------------------------------------------------------------------------- +// Internal variables +//----------------------------------------------------------------------------- + +/// Mass storage device driver instance. +static MSDDriver msdDriver; + +/// Standard device driver instance. +static USBDDriver usbdDriver; + +//----------------------------------------------------------------------------- +// Internal functions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +/// Resets the state of the MSD driver +//----------------------------------------------------------------------------- +static void MSDDriver_Reset(void) +{ + TRACE_INFO_WP("MSDReset "); + + msdDriver.state = MSDD_STATE_READ_CBW; + msdDriver.waitResetRecovery = 0; + msdDriver.commandState.state = 0; +} + +//----------------------------------------------------------------------------- +// Callback re-implementation +//----------------------------------------------------------------------------- +//----------------------------------------------------------------------------- +/// Invoked when a new SETUP request is received from the host. Forwards the +/// request to the Mass Storage device driver handler function. +/// \param request Pointer to a USBGenericRequest instance. +//----------------------------------------------------------------------------- +void USBDCallbacks_RequestReceived(const USBGenericRequest *request) +{ + MSDDriver_RequestHandler(request); +} + +//----------------------------------------------------------------------------- +/// Invoked when the configuration of the device changes. Resets the mass +/// storage driver. +/// \param cfgnum New configuration number. +//----------------------------------------------------------------------------- +void USBDDriverCallbacks_ConfigurationChanged(unsigned char cfgnum) +{ + if (cfgnum > 0) { + + MSDDriver_Reset(); + } +} + +//----------------------------------------------------------------------------- +// Driver functions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +/// Reads from host through MSD defined bulk OUT pipe. Act as USBD_Read but by +/// a fixed OUT endpoint. +/// \param data Pointer to the data buffer that contains data read from host. +/// \param size The number of bytes should be read (buffer size). +/// \param callback Pointer to the function invoked on end of reading. +/// \param argument Pointer to additional argument data struct. +//----------------------------------------------------------------------------- +char MSDD_Read(void *data, + unsigned int size, + TransferCallback callback, + void *argument) + +{ + return USBD_Read(MSDDriverDescriptors_BULKOUT, + data, + size, + callback, + argument); +} + +//----------------------------------------------------------------------------- +/// Writes to host through MSD defined bulk IN pipe. Act as USBD_Write but by +/// a fixed IN endpoint. +/// \param data Pointer to the data that writes to the host. +/// \param size The number of bytes should be write. +/// \param callback Pointer to the function invoked on end of writing. +/// \param argument Pointer to additional argument data struct. +//----------------------------------------------------------------------------- +char MSDD_Write(void *data, + unsigned int size, + TransferCallback callback, + void *argument) +{ + return USBD_Write(MSDDriverDescriptors_BULKIN, + data, + size, + callback, + argument); +} + +//----------------------------------------------------------------------------- +/// HALT Specified USB pipe. +/// \param stallCASE Case of the stall condition (Bulk In/Out/Both). +//----------------------------------------------------------------------------- +void MSDD_Halt(unsigned int stallCASE) +{ + if (stallCASE & MSDD_CASE_STALL_OUT) { + + USBD_Halt(MSDDriverDescriptors_BULKOUT); + } + + if (stallCASE & MSDD_CASE_STALL_IN) { + + USBD_Halt(MSDDriverDescriptors_BULKIN); + } +} + +//----------------------------------------------------------------------------- +/// Return halted status +/// \return stallCASE bitmap, case of the stall condition +/// (bit: MSDD_CASE_STALL_OUT or MSDD_CASE_STALL_IN) +//----------------------------------------------------------------------------- +unsigned int MSDD_IsHalted(void) +{ + unsigned int stallCASE = 0; + if (USBD_IsHalted(MSDDriverDescriptors_BULKOUT)) { + + stallCASE |= MSDD_CASE_STALL_OUT; + } + if (USBD_IsHalted(MSDDriverDescriptors_BULKIN)) { + + stallCASE |= MSDD_CASE_STALL_IN; + } + return stallCASE; +} + +//----------------------------------------------------------------------------- +// Exported functions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +/// Initializes the MSD driver and the associated USB driver. +/// \param luns Pointer to a list of LUNs +/// \param numLuns Number of LUN in list +/// \see MSDLun +//----------------------------------------------------------------------------- +void MSDDriver_Initialize(MSDLun *defLuns, unsigned char numLuns) +{ + + TRACE_INFO("MSD init\n\r"); + + // Command state initialization + msdDriver.commandState.state = 0; + msdDriver.commandState.postprocess = 0; + msdDriver.commandState.length = 0; + msdDriver.commandState.transfer.semaphore = 0; + + // LUNs + msdDriver.luns = defLuns; + msdDriver.maxLun = (unsigned char) (numLuns - 1); + + // Reset BOT driver + MSDDriver_Reset(); + + // Init the USB driver + USBDDriver_Initialize(&usbdDriver, &msdDriverDescriptors, 0); + USBD_Init(); +} + +//----------------------------------------------------------------------------- +/// Handler for incoming SETUP requests on default Control endpoint 0. +/// +/// Standard requests are forwarded to the USBDDriver_RequestHandler +/// method. +/// \param request Pointer to a USBGenericRequest instance +//----------------------------------------------------------------------------- +void MSDDriver_RequestHandler(const USBGenericRequest *request) +{ + TRACE_INFO_WP("NewReq "); + + // Handle requests + switch (USBGenericRequest_GetRequest(request)) { + //--------------------- + case USBGenericRequest_CLEARFEATURE: + //--------------------- + TRACE_INFO_WP("ClrFeat "); + + switch (USBFeatureRequest_GetFeatureSelector(request)) { + + //--------------------- + case USBFeatureRequest_ENDPOINTHALT: + //--------------------- + TRACE_INFO_WP("Hlt "); + + // Do not clear the endpoint halt status if the device is waiting + // for a reset recovery sequence + if (!msdDriver.waitResetRecovery) { + + // Forward the request to the standard handler + USBDDriver_RequestHandler(&usbdDriver, request); + } + else { + + TRACE_INFO_WP("No "); + } + + USBD_Write(0, 0, 0, 0, 0); + break; + + //------ + default: + //------ + // Forward the request to the standard handler + USBDDriver_RequestHandler(&usbdDriver, request); + } + break; + + //------------------- + case MSD_GET_MAX_LUN: + //------------------- + TRACE_INFO_WP("gMaxLun "); + + // Check request parameters + if ((request->wValue == 0) + && (request->wIndex == 0) + && (request->wLength == 1)) { + + USBD_Write(0, &(msdDriver.maxLun), 1, 0, 0); + + } + else { + + TRACE_WARNING( + "MSDDriver_RequestHandler: GetMaxLUN(%d,%d,%d)\n\r", + request->wValue, request->wIndex, request->wLength); + USBD_Stall(0); + } + break; + + //----------------------- + case MSD_BULK_ONLY_RESET: + //----------------------- + TRACE_INFO_WP("Rst "); + + // Check parameters + if ((request->wValue == 0) + && (request->wIndex == 0) + && (request->wLength == 0)) { + + // Reset the MSD driver + MSDDriver_Reset(); + USBD_Write(0, 0, 0, 0, 0); + } + else { + + TRACE_WARNING( + "MSDDriver_RequestHandler: Reset(%d,%d,%d)\n\r", + request->wValue, request->wIndex, request->wLength); + USBD_Stall(0); + } + break; + + //------ + default: + //------ + // Forward request to standard handler + USBDDriver_RequestHandler(&usbdDriver, request); + + break; + } +} + +//----------------------------------------------------------------------------- +/// State machine for the MSD driver +//----------------------------------------------------------------------------- +void MSDDriver_StateMachine(void) +{ + if (USBD_GetState() < USBD_STATE_CONFIGURED){} + else MSDD_StateMachine(&msdDriver); + +} + +//----------------------------------------------------------------------------- +/// Starts a remote wake-up sequence if the host has explicitely enabled it +/// by sending the appropriate SET_FEATURE request. +//----------------------------------------------------------------------------- +void MSDDriver_RemoteWakeUp(void) +{ + // Remote wake-up has been enabled + if (USBDDriver_IsRemoteWakeUpEnabled(&usbdDriver)) { + + USBD_RemoteWakeUp(); + } + // Remote wake-up NOT enabled + else { + + TRACE_WARNING( + "MSD..RemoteWakeUp: Host has not enabled remote wake-up\n\r"); + } +} + diff --git a/radio/bootloader/usb/device/massstorage/MSDDriver.h b/radio/bootloader/usb/device/massstorage/MSDDriver.h new file mode 100644 index 000000000..30e6b087c --- /dev/null +++ b/radio/bootloader/usb/device/massstorage/MSDDriver.h @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// !Purpose +/// +/// Mass storage %device driver implementation. +/// +/// !Usage +/// +/// -# Enable and setup USB related pins (see pio & board.h). +/// -# Configure the memory interfaces used for Mass Storage LUNs +/// (see memories, MSDLun.h). +/// -# Configure the USB MSD %driver using MSDDriver_Initialize. +/// -# Invoke MSDDriver_StateMachine in main loop to handle all Mass Storage +/// operations. +//------------------------------------------------------------------------------ + +#ifndef MSDDRIVER_H +#define MSDDRIVER_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "MSD.h" +#include "MSDLun.h" +// #include + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +extern void MSDDriver_Initialize(MSDLun *luns, unsigned char numLuns); + +extern void MSDDriver_RequestHandler(const USBGenericRequest *request); + +extern void MSDDriver_StateMachine(void); + +extern void MSDDriver_RemoteWakeUp(void); + +extern void MSDDriver_DataCallback(unsigned char isRead, + unsigned int dataLength, + unsigned int nullCnt, + unsigned int fullCnt); + +#endif // #ifndef MSDDRIVER_H + diff --git a/radio/bootloader/usb/device/massstorage/MSDDriverDescriptors.c b/radio/bootloader/usb/device/massstorage/MSDDriverDescriptors.c new file mode 100644 index 000000000..b37653bc5 --- /dev/null +++ b/radio/bootloader/usb/device/massstorage/MSDDriverDescriptors.c @@ -0,0 +1,395 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "MSDDriverDescriptors.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include + +//------------------------------------------------------------------------------ +// Internal definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "MSD Device Descriptor IDs" +/// ... +/// !IDs +/// - MSDDriverDescriptors_VENDORID +/// - MSDDriverDescriptors_PRODUCTID +/// - MSDDriverDescriptors_RELEASE + +/// Vendor ID for the Mass Storage device driver. +#define MSDDriverDescriptors_VENDORID 0x03EB +/// Product ID for the Mass Storage device driver. +#ifdef HID +#define HIDMSDDDriverDescriptors_PRODUCTID 0x6135 +#else +#define MSDDriverDescriptors_PRODUCTID 0x6129 +#endif +/// Device release number for the Mass Storage device driver. +#define MSDDriverDescriptors_RELEASE 0x0100 + +#ifdef HID +/** Address of the HID interrupt IN endpoint. */ +#define HIDD_Descriptors_INTERRUPTIN 1 +/** Address of the HID interrupt OUT endpoint. */ +#define HIDD_Descriptors_INTERRUPTOUT 2 +/** Address of the Mass Storage bulk-out endpoint. */ +#define MSDD_Descriptors_BULKOUT 4 +/** Address of the Mass Storage bulk-in endpoint. */ +#define MSDD_Descriptors_BULKIN 5 +#endif + +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Macros +//------------------------------------------------------------------------------ + +/// Returns the minimum between two values. +#define MIN(a, b) ((a < b) ? a : b) + +//------------------------------------------------------------------------------ +// Internal types +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// List of configuration descriptors used by a Mass Storage device driver. +//------------------------------------------------------------------------------ +#ifndef HID +typedef struct { + + /// Standard configuration descriptor. + USBConfigurationDescriptor configuration; + /// Mass storage interface descriptor. + USBInterfaceDescriptor interface; + /// Bulk-out endpoint descriptor. + USBEndpointDescriptor bulkOut; + /// Bulk-in endpoint descriptor. + USBEndpointDescriptor bulkIn; + +} __attribute__ ((packed)) MSDConfigurationDescriptors; +#endif + +//------------------------------------------------------------------------------ +// Local variables +//------------------------------------------------------------------------------ + +#ifdef HID +/** Standard USB device descriptor for the composite device driver */ +static const USBDeviceDescriptor deviceDescriptor = +{ + + sizeof(USBDeviceDescriptor), + USBGenericDescriptor_DEVICE, + USBDeviceDescriptor_USB2_00, + 0x00, + 0x00, + 0x00, + CHIP_USB_ENDPOINTS_MAXPACKETSIZE(0), + HIDMSDDDriverDescriptors_VENDORID, + HIDMSDDDriverDescriptors_PRODUCTID, + HIDMSDDDriverDescriptors_RELEASE, +// 0, /* No string descriptor for manufacturer */ +// 1, /* Index of product string descriptor is #1 */ +// 0, /* No string descriptor for serial number */ + 1, // Manufacturer string descriptor index. + 2, // Product string descriptor index. + 3, // Serial number string descriptor index. + 1 /* Device has 1 possible configuration */ +}; +#else +/// Mass storage driver device descriptor. +static const USBDeviceDescriptor deviceDescriptor = { + + sizeof(USBDeviceDescriptor), + USBGenericDescriptor_DEVICE, + USBDeviceDescriptor_USB2_00, + MSDeviceDescriptor_CLASS, + MSDeviceDescriptor_SUBCLASS, + MSDeviceDescriptor_PROTOCOL, + CHIP_USB_ENDPOINTS_MAXPACKETSIZE(0), + MSDDriverDescriptors_VENDORID, + MSDDriverDescriptors_PRODUCTID, + MSDDriverDescriptors_RELEASE, + 1, // Manufacturer string descriptor index. + 2, // Product string descriptor index. + 3, // Serial number string descriptor index. + 1 // Device has one possible configuration. +}; +#endif + +#ifdef HID +/** USB FS configuration descriptors for the composite device driver */ +static const HidMsdDriverConfigurationDescriptors configurationDescriptorsFS = +{ + + /* Standard configuration descriptor */ + { + sizeof(USBConfigurationDescriptor), + USBGenericDescriptor_CONFIGURATION, + sizeof(HidMsdDriverConfigurationDescriptors), + HIDMSDDriverDescriptors_NUMINTERFACE, + 1, /* This is configuration #1 */ + 0, /* No string descriptor for this configuration */ + BOARD_USB_BMATTRIBUTES, + USBConfigurationDescriptor_POWER(100) + }, + + /* Interface descriptor */ + { + sizeof(USBInterfaceDescriptor), + USBGenericDescriptor_INTERFACE, + HIDMSDDriverDescriptors_HID_INTERFACE, + 0, /* This is alternate setting #0 */ + 2, /* Two endpoints used */ + HIDInterfaceDescriptor_CLASS, + HIDInterfaceDescriptor_SUBCLASS_NONE, + HIDInterfaceDescriptor_PROTOCOL_NONE, + 0 /* No associated string descriptor */ + }, + /* HID descriptor */ + { + sizeof(HIDDescriptor1), + HIDGenericDescriptor_HID, + HIDDescriptor_HID1_11, + 0, /* Device is not localized, no country code */ + 1, /* One HID-specific descriptor (apart from this one) */ + HIDGenericDescriptor_REPORT, + HIDDKeyboard_REPORTDESCRIPTORSIZE + }, + /* Interrupt IN endpoint descriptor */ + { + sizeof(USBEndpointDescriptor), + USBGenericDescriptor_ENDPOINT, + USBEndpointDescriptor_ADDRESS( + USBEndpointDescriptor_IN, + HIDD_Descriptors_INTERRUPTIN), + USBEndpointDescriptor_INTERRUPT, + sizeof(HIDDKeyboardInputReport), + HIDDKeyboardDescriptors_INTERRUPTIN_POLLING_FS + }, + /* Interrupt OUT endpoint descriptor */ + { + sizeof(USBEndpointDescriptor), + USBGenericDescriptor_ENDPOINT, + USBEndpointDescriptor_ADDRESS( + USBEndpointDescriptor_OUT, + HIDD_Descriptors_INTERRUPTOUT), + USBEndpointDescriptor_INTERRUPT, + sizeof(HIDDKeyboardOutputReport), + HIDDKeyboardDescriptors_INTERRUPTIN_POLLING_FS + }, + + /* Mass Storage interface descriptor. */ + { + sizeof(USBInterfaceDescriptor), + USBGenericDescriptor_INTERFACE, + HIDMSDDriverDescriptors_MSD_INTERFACE, + 0, /* This is alternate setting #0. */ + 2, /* Interface uses two endpoints. */ + MSInterfaceDescriptor_CLASS, + MSInterfaceDescriptor_SCSI, + MSInterfaceDescriptor_BULKONLY, + 0 /* No string descriptor for interface. */ + }, + /* Bulk-OUT endpoint descriptor */ + { + sizeof(USBEndpointDescriptor), + USBGenericDescriptor_ENDPOINT, + USBEndpointDescriptor_ADDRESS( + USBEndpointDescriptor_OUT, + MSDD_Descriptors_BULKOUT), //MSDDriverDescriptors_BULKOUT + USBEndpointDescriptor_BULK, + MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDD_Descriptors_BULKOUT),//MSDDriverDescriptors_BULKOUT + USBEndpointDescriptor_MAXBULKSIZE_FS), + 0 /* No string descriptor for endpoint. */ + }, + /* Bulk-IN endpoint descriptor */ + { + sizeof(USBEndpointDescriptor), + USBGenericDescriptor_ENDPOINT, + USBEndpointDescriptor_ADDRESS( + USBEndpointDescriptor_IN, + MSDD_Descriptors_BULKIN), //MSDDriverDescriptors_BULKIN + USBEndpointDescriptor_BULK, + MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDD_Descriptors_BULKIN),//MSDDriverDescriptors_BULKIN + USBEndpointDescriptor_MAXBULKSIZE_FS), + 0 /* No string descriptor for endpoint. */ + } + +}; + +#else +/// Full-speed configuration descriptor. +static const MSDConfigurationDescriptors configurationDescriptorsFS = { + + // Standard configuration descriptor. + { + sizeof(USBConfigurationDescriptor), + USBGenericDescriptor_CONFIGURATION, + sizeof(MSDConfigurationDescriptors), + 1, // Configuration has one interface. + 1, // This is configuration #1. + 0, // No string descriptor for configuration. + BOARD_USB_BMATTRIBUTES, + USBConfigurationDescriptor_POWER(100) + }, + // Mass Storage interface descriptor. + { + sizeof(USBInterfaceDescriptor), + USBGenericDescriptor_INTERFACE, + 0, // This is interface #0. + 0, // This is alternate setting #0. + 2, // Interface uses two endpoints. + MSInterfaceDescriptor_CLASS, + MSInterfaceDescriptor_SCSI, + MSInterfaceDescriptor_BULKONLY, + 0 // No string descriptor for interface. + }, + // Bulk-OUT endpoint descriptor + { + sizeof(USBEndpointDescriptor), + USBGenericDescriptor_ENDPOINT, + USBEndpointDescriptor_ADDRESS( + USBEndpointDescriptor_OUT, + MSDDriverDescriptors_BULKOUT), + USBEndpointDescriptor_BULK, + MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDDriverDescriptors_BULKOUT), + USBEndpointDescriptor_MAXBULKSIZE_FS), + 0 // Must be 0 for full-speed Bulk endpoints. + }, + // Bulk-IN endpoint descriptor + { + sizeof(USBEndpointDescriptor), + USBGenericDescriptor_ENDPOINT, + USBEndpointDescriptor_ADDRESS( + USBEndpointDescriptor_IN, + MSDDriverDescriptors_BULKIN), + USBEndpointDescriptor_BULK, + MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDDriverDescriptors_BULKIN), + USBEndpointDescriptor_MAXBULKSIZE_FS), + 0 // Must be 0 for full-speed Bulk endpoints. + } +}; +#endif + +/// Language ID string descriptor. +static const unsigned char languageIdDescriptor[] = { + + USBStringDescriptor_LENGTH(1), + USBGenericDescriptor_STRING, + USBStringDescriptor_ENGLISH_US +}; + +/// Manufacturer string descriptor. +static const unsigned char manufacturerDescriptor[] = { + + USBStringDescriptor_LENGTH(7), + USBGenericDescriptor_STRING, + USBStringDescriptor_UNICODE('9'), + USBStringDescriptor_UNICODE('X'), + USBStringDescriptor_UNICODE(' '), + USBStringDescriptor_UNICODE('T'), + USBStringDescriptor_UNICODE('E'), + USBStringDescriptor_UNICODE('A'), + USBStringDescriptor_UNICODE('M'), +}; + +/// Product string descriptor. +static const unsigned char productDescriptor[] = { + + USBStringDescriptor_LENGTH(5), + USBGenericDescriptor_STRING, + USBStringDescriptor_UNICODE('S'), + USBStringDescriptor_UNICODE('K'), + USBStringDescriptor_UNICODE('Y'), + USBStringDescriptor_UNICODE('9'), + USBStringDescriptor_UNICODE('X'), +}; + +/// Serial number string descriptor. The serial number must be at least 12 +/// characters long and made up of only letters & numbers to be compliant with +/// the MSD specification. +static const unsigned char serialNumberDescriptor[] = { + + USBStringDescriptor_LENGTH(12), + USBGenericDescriptor_STRING, + USBStringDescriptor_UNICODE('0'), + USBStringDescriptor_UNICODE('1'), + USBStringDescriptor_UNICODE('2'), + USBStringDescriptor_UNICODE('3'), + USBStringDescriptor_UNICODE('4'), + USBStringDescriptor_UNICODE('5'), + USBStringDescriptor_UNICODE('6'), + USBStringDescriptor_UNICODE('7'), + USBStringDescriptor_UNICODE('8'), + USBStringDescriptor_UNICODE('9'), + USBStringDescriptor_UNICODE('A'), + USBStringDescriptor_UNICODE('B') +}; + +/// List of all string descriptors used. +static const unsigned char *stringDescriptors[] = { + + languageIdDescriptor, + manufacturerDescriptor, + productDescriptor, + serialNumberDescriptor +}; + +//------------------------------------------------------------------------------ +// Global variables +//------------------------------------------------------------------------------ + +/// List of the standard descriptors used by the Mass Storage driver. +const USBDDriverDescriptors msdDriverDescriptors = { + + &deviceDescriptor, + (USBConfigurationDescriptor *) &configurationDescriptorsFS, + 0, // No full-speed device qualifier descriptor + 0, // No full-speed other speed configuration + 0, // No high-speed device descriptor + 0, // No high-speed configuration descriptor + 0, // No high-speed device qualifier descriptor + 0, // No high-speed other speed configuration descriptor + stringDescriptors, + 4 // Four string descriptors in array +}; + diff --git a/radio/bootloader/usb/device/massstorage/MSDDriverDescriptors.h b/radio/bootloader/usb/device/massstorage/MSDDriverDescriptors.h new file mode 100644 index 000000000..6f1f151f5 --- /dev/null +++ b/radio/bootloader/usb/device/massstorage/MSDDriverDescriptors.h @@ -0,0 +1,83 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// !Purpose +/// +/// Definitions of the descriptors required by a Mass Storage device driver. +/// +/// !Usage +/// +/// - For a USB %device: +/// -# When initializing a USBDDriver instance, use msdDriverDescriptors as +/// the list of standard descriptors. +//------------------------------------------------------------------------------ + +#ifndef MSDDRIVERDESCRIPTORS_H +#define MSDDRIVERDESCRIPTORS_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "MSD endpoint addresses" +/// This page lists the addresses used by the Mass Storage driver %endpoints. +/// +/// !Addresses +/// +/// - MSDDriverDescriptors_BULKOUT +/// - MSDDriverDescriptors_BULKIN + +/// Address of the Mass Storage bulk-out endpoint. +#define MSDDriverDescriptors_BULKOUT 1 + +/// Address of the Mass Storage bulk-in endpoint. +#if defined(at91sam9m10) + #define MSDDriverDescriptors_BULKIN 6 +#else + #define MSDDriverDescriptors_BULKIN 2 +#endif +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Exported variables +//------------------------------------------------------------------------------ + +extern const USBDDriverDescriptors msdDriverDescriptors; + +#endif //#ifndef MSDDRIVERDESCRIPTORS_H + diff --git a/radio/bootloader/usb/device/massstorage/MSDIOFifo.h b/radio/bootloader/usb/device/massstorage/MSDIOFifo.h new file mode 100644 index 000000000..5f7b7fba5 --- /dev/null +++ b/radio/bootloader/usb/device/massstorage/MSDIOFifo.h @@ -0,0 +1,135 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _MSDIOFIFO_H +#define _MSDIOFIFO_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +/// Idle state, do nothing +#define MSDIO_IDLE 0 +/// Start, to start IO operation +#define MSDIO_START 1 +/// Wait, waiting for IO operation done +#define MSDIO_WAIT 2 +/// Next, to check if the next block can be performed +#define MSDIO_NEXT 3 +/// Pause, to pause the process for buffer full or null +#define MSDIO_PAUSE 4 +/// Abort, to abort the process +#define MSDIO_ABORT 5 +/// Done, finish without error +#define MSDIO_DONE 6 +/// Error, any error happens +#define MSDIO_ERROR 7 + +/// FIFO offset before USB transmit start +//#define MSDIO_FIFO_OFFSET (4*512) + +/// FIFO trunk size (in each transfer, large amount of data) +#if !defined(MSD_OP_BUFFER) +#define MSDIO_READ10_CHUNK_SIZE (4*512) +#define MSDIO_WRITE10_CHUNK_SIZE (4*512) +#endif + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +/// FIFO buffer for READ/WRITE (disk) operation of a mass storage device +typedef struct _MSDIOFifo { + + /// Pointer to the ring buffer allocated for read/write + unsigned char * pBuffer; + /// The size of the buffer allocated + unsigned int bufferSize; +#ifdef MSDIO_FIFO_OFFSET + /// The offset to start USB transfer (READ10) + unsigned int bufferOffset; +#endif + /// The index of input data (loaded to fifo buffer) + unsigned int inputNdx; + /// The total size of the loaded data + unsigned int inputTotal; + /// The index of output data (sent from the fifo buffer) + unsigned int outputNdx; + /// The total size of the output data + unsigned int outputTotal; + + /// The total size of the data + unsigned int dataTotal; + /// The size of the block in bytes + unsigned short blockSize; +#if defined(MSDIO_READ10_CHUNK_SIZE) || defined(MSDIO_WRITE10_CHUNK_SIZE) + /// The size of one chunk + /// (1 block, or several blocks for large amount data R/W) + unsigned int chunkSize; +#endif + /// State of input & output + unsigned char inputState; + unsigned char outputState; + + //- Statistics + /// Times when fifo has no data to send + unsigned short nullCnt; + /// Times when fifo can not load more input data + unsigned short fullCnt; +} MSDIOFifo, *PMSDIOFifo; + +//------------------------------------------------------------------------------ +// MACROS +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Increase the index, by defined block size, in the ring buffer +/// \param ndx The index to be increased +/// \param sectSize The defined block size +/// \param bufSize The ring buffer size +//------------------------------------------------------------------------------ +#define MSDIOFifo_IncNdx(ndx, sectSize, bufSize) \ + if ((ndx) >= (bufSize) - (sectSize)) (ndx) = 0; \ + else (ndx) += (sectSize) + + +//------------------------------------------------------------------------------ +// Exported Functions +//------------------------------------------------------------------------------ + + +extern void MSDIOFifo_Init(MSDIOFifo *pFifo, + void * pBuffer, unsigned short bufferSize); + +#endif // _MSDIOFIFO_H + diff --git a/radio/bootloader/usb/device/massstorage/MSDLun.c b/radio/bootloader/usb/device/massstorage/MSDLun.c new file mode 100644 index 000000000..6b649b4d2 --- /dev/null +++ b/radio/bootloader/usb/device/massstorage/MSDLun.c @@ -0,0 +1,368 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + + +#include "MSDLun.h" +#include "debug.h" +#include + +#include "usb/device/massstorage/MSDDriver.h" + + +//------------------------------------------------------------------------------ +// Constants +//------------------------------------------------------------------------------ + +/// Default LUN block size in bytes +#define DEFAULT_LUN_BLOCK_SIZE 512 + +//------------------------------------------------------------------------------ +// Internal variables +//------------------------------------------------------------------------------ + +/// Inquiry data to return to the host for the Lun. +static SBCInquiryData inquiryData = { + + SBC_DIRECT_ACCESS_BLOCK_DEVICE, // Direct-access block device + SBC_PERIPHERAL_DEVICE_CONNECTED,// Peripheral device is connected + 0x00, // Reserved bits + 0x01, // Media is removable + SBC_SPC_VERSION_4, // SPC-4 supported + 0x2, // Response data format, must be 0x2 + 0, // Hierarchical addressing not supported + 0, // ACA not supported + 0x0, // Obsolete bits + sizeof(SBCInquiryData) - 5, // Additional length + 0, // No embedded SCC + 0, // No access control coordinator + SBC_TPGS_NONE, // No target port support group + 0, // Third-party copy not supported + 0x0, // Reserved bits + 0, // Protection information not supported + 0x0, // Obsolete bit + 0, // No embedded enclosure service component + 0x0, // ??? + 0, // Device is not multi-port + 0x0, // Obsolete bits + 0x0, // Unused feature + 0x0, // Unused features + 0, // Task management model not supported + 0x0, // ??? + {'E','R','S','K','Y','9','X',' '}, + {'M','a','s','s',' ', + 'S','t','o','r','a','g','e',' ', + 'M','S','D'}, + {'0','.','0','1'}, + {'M','a','s','s',' ', + 'S','t','o','r','a','g','e',' ', + 'E','x','a','m','p','l','e'}, + 0x00, // Unused features + 0x00, // Reserved bits + {SBC_VERSION_DESCRIPTOR_SBC_3}, // SBC-3 compliant device + {0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0} // Reserved +}; + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +//! \brief Initializes a LUN instance. Must be invoked at least once even no +//! Media is linked. +//! \param lun Pointer to the MSDLun instance to initialize +//! \param media Media on which the LUN is constructed, set to 0 to +//! disconnect the Media or initialize an ejected LUN. +//! \param ioBuffer Pointer to a buffer used for read/write operation and +//! which must be blockSize bytes long. +//! \param ioBufferSize Size of the allocated IO buffer. +//! \param baseAddress Base address of the LUN in number of media blocks +//! \param size Total size of the LUN in number of media blocks +//! \param blockSize One block of the LUN in number of media blocks +//! \param protected The LUN area is forced to readonly even the media +//! is writable +//! \param dataMonitor Pointer to a Monitor Function to analyze the flow of +//! this LUN. +//------------------------------------------------------------------------------ +void LUN_Init(MSDLun *lun, + Media *media, + unsigned char *ioBuffer, + unsigned int ioBufferSize, + unsigned int baseAddress, + unsigned int size, + unsigned short blockSize, + unsigned char protected, + void (*dataMonitor)(unsigned char flowDirection, + unsigned int dataLength, + unsigned int fifoNullCount, + unsigned int fifoFullCount)) +{ + unsigned int logicalBlockAddress; + TRACE_INFO("LUN init\n\r"); + + // Initialize inquiry data + lun->inquiryData = &inquiryData; + + // Initialize request sense data + lun->requestSenseData.bResponseCode = SBC_SENSE_DATA_FIXED_CURRENT; + lun->requestSenseData.isValid = 1; + lun->requestSenseData.bObsolete1 = 0; + lun->requestSenseData.bSenseKey = SBC_SENSE_KEY_NO_SENSE; + lun->requestSenseData.bReserved1 = 0; + lun->requestSenseData.isILI = 0; + lun->requestSenseData.isEOM = 0; + lun->requestSenseData.isFilemark = 0; + lun->requestSenseData.pInformation[0] = 0; + lun->requestSenseData.pInformation[1] = 0; + lun->requestSenseData.pInformation[2] = 0; + lun->requestSenseData.pInformation[3] = 0; + lun->requestSenseData.bAdditionalSenseLength + = sizeof(SBCRequestSenseData) - 8; + lun->requestSenseData.bAdditionalSenseCode = 0; + lun->requestSenseData.bAdditionalSenseCodeQualifier = 0; + lun->requestSenseData.bFieldReplaceableUnitCode = 0; + lun->requestSenseData.bSenseKeySpecific = 0; + lun->requestSenseData.pSenseKeySpecific[0] = 0; + lun->requestSenseData.pSenseKeySpecific[0] = 0; + lun->requestSenseData.isSKSV = 0; + + STORE_DWORDB(0, lun->readCapacityData.pLogicalBlockAddress); + STORE_DWORDB(0, lun->readCapacityData.pLogicalBlockLength); + + // Initialize LUN + lun->media = media; + if (media == 0) { + lun->status = LUN_NOT_PRESENT; + return; + } + + lun->baseAddress = baseAddress; + + // Customized block size + if (blockSize) { + lun->blockSize = blockSize; + } + else { + if (media->blockSize < DEFAULT_LUN_BLOCK_SIZE) + lun->blockSize = DEFAULT_LUN_BLOCK_SIZE / media->blockSize; + else + lun->blockSize = 1; + } + + if (size) { + lun->size = size; + } + else { + lun->size = media->size; + //if (blockSize) + // lun->size = media->size / blockSize; + //else { + // if (media->blockSize < DEFAULT_LUN_BLOCK_SIZE) + // lun->size = media->size / lun->blockSize; + // else + // lun->size = media->size; + //} + } + + TRACE_INFO("LUN: blkSize %d, size %d\n\r", (int)lun->blockSize, (int)lun->size); + if (protected) lun->protected = 1; + else lun->protected = media->protected; + + lun->ioFifo.pBuffer = ioBuffer; + lun->ioFifo.bufferSize = ioBufferSize; + + lun->dataMonitor = dataMonitor; + + // Initialize read capacity data + logicalBlockAddress = lun->size / lun->blockSize - 1; + STORE_DWORDB(logicalBlockAddress, + lun->readCapacityData.pLogicalBlockAddress); + STORE_DWORDB(lun->blockSize * media->blockSize, + lun->readCapacityData.pLogicalBlockLength); + + // Indicate media change + lun->status = LUN_CHANGED; +} + +//------------------------------------------------------------------------------ +//! \brief Eject the media from a LUN +//! \param lun Pointer to the MSDLun instance to initialize +//! \return Operation result code +//------------------------------------------------------------------------------ +unsigned char LUN_Eject(MSDLun *lun) +{ + if (lun->media) { + + // Avoid any LUN R/W in progress + if (lun->media->state == MED_STATE_BUSY) { + + return USBD_STATUS_LOCKED; + } + + // Remove the link of the media + lun->media = 0; + } + // LUN is removed + lun->status = LUN_NOT_PRESENT; + + return USBD_STATUS_SUCCESS; +} + +//------------------------------------------------------------------------------ +//! \brief Writes data on the a LUN starting at the specified block address. +//! \param lun Pointer to a MSDLun instance +//! \param blockAddress First block address to write +//! \param data Pointer to the data to write +//! \param length Number of blocks to write +//! \param callback Optional callback to invoke when the write finishes +//! \return Operation result code +//------------------------------------------------------------------------------ +unsigned char LUN_Write(MSDLun *lun, + unsigned int blockAddress, + void *data, + unsigned int length, + TransferCallback callback, + void *argument) +{ + unsigned int medBlk, medLen; + unsigned char status; + + TRACE_INFO_WP("LUNWrite(%u) ", blockAddress); + + // Check that the data is not too big + if ((length + blockAddress) * lun->blockSize > lun->size) { + + TRACE_WARNING("LUN_Write: Data too big\n\r"); + status = USBD_STATUS_ABORTED; + } + else if (lun->media == 0 || lun->status != LUN_READY) { + + TRACE_WARNING("LUN_Write: Media not ready\n\r"); + status = USBD_STATUS_ABORTED; + } + else if (lun->protected) { + TRACE_WARNING("LUN_Write: LUN is readonly\n\r"); + status = USBD_STATUS_ABORTED; + } + else { + + // Compute write start address + medBlk = lun->baseAddress + blockAddress * lun->blockSize; + medLen = length * lun->blockSize; + + // Start write operation + status = MED_Write(lun->media, + medBlk, + data, + medLen, + (MediaCallback) callback, + argument); + + // Check operation result code + if (status == MED_STATUS_SUCCESS) { + + status = USBD_STATUS_SUCCESS; + } + else { + + TRACE_WARNING("LUN_Write: Cannot write media\n\r"); + status = USBD_STATUS_ABORTED; + } + } + + return status; +} + +//------------------------------------------------------------------------------ +//! \brief Reads data from a LUN, starting at the specified block address. +//! \param lun Pointer to a MSDLun instance +//! \param blockAddress First block address to read +//! \param data Pointer to a data buffer in which to store the data +//! \param length Number of blocks to read +//! \param callback Optional callback to invoke when the read finishes +//! \return Operation result code +//------------------------------------------------------------------------------ +unsigned char LUN_Read(MSDLun *lun, + unsigned int blockAddress, + void *data, + unsigned int length, + TransferCallback callback, + void *argument) +{ + unsigned int medBlk, medLen; + unsigned char status; + + // Check that the data is not too big + if ((length + blockAddress) * lun->blockSize > lun->size) { + TRACE_WARNING("LUN_Read: Area: (%d + %d)*%d > %d\n\r", + (int)length, (int)blockAddress, (int)lun->blockSize, (int)lun->size); + status = USBD_STATUS_ABORTED; + } + else if (lun->media == 0 || lun->status != LUN_READY) { + + TRACE_WARNING("LUN_Read: Media not present\n\r"); + status = USBD_STATUS_ABORTED; + } + else { + + TRACE_INFO_WP("LUNRead(%u) ", blockAddress); + + // Compute read start address + medBlk = lun->baseAddress + (blockAddress * lun->blockSize); + medLen = length * lun->blockSize; + + // Start write operation + status = MED_Read(lun->media, + medBlk, + data, + medLen, + (MediaCallback) callback, + argument); + + // Check result code + if (status == MED_STATUS_SUCCESS) { + + status = USBD_STATUS_SUCCESS; + } + else { + + TRACE_WARNING("LUN_Read: Cannot read media\n\r"); + status = USBD_STATUS_ABORTED; + } + } + + return status; +} diff --git a/radio/bootloader/usb/device/massstorage/MSDLun.h b/radio/bootloader/usb/device/massstorage/MSDLun.h new file mode 100644 index 000000000..799775541 --- /dev/null +++ b/radio/bootloader/usb/device/massstorage/MSDLun.h @@ -0,0 +1,161 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// !Purpose +/// +/// Logical Unit Number (LUN) used by the Mass Storage driver and the SCSI +/// protocol. Represents a logical hard-drive. +/// +/// !Usage +/// -# Initialize Memory related pins (see pio & board.h). +/// -# Initialize a Media instance for the LUN (see memories). +/// -# Initlalize the LUN with LUN_Init, and link to the initialized Media. +/// -# To read data from the LUN linked media, uses LUN_Read. +/// -# To write data to the LUN linked media, uses LUN_Write. +/// -# To unlink the media, uses LUN_Eject. +//------------------------------------------------------------------------------ + +#ifndef MSDLUN_H +#define MSDLUN_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "SBC.h" +#include +#include +#include + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +/// LUN RC: success +#define LUN_STATUS_SUCCESS 0x00 +/// LUN RC: error +#define LUN_STATUS_ERROR 0x02 + +/// Media of LUN is removed +#define LUN_NOT_PRESENT 0x00 +/// LUN is ejected by host +#define LUN_EJECTED 0x01 +/// Media of LUN is changed +#define LUN_CHANGED 0x10 +/// LUN Not Ready to Ready transition +#define LUN_TRANS_READY LUN_CHANGED +/// Media of LUN is ready +#define LUN_READY 0x11 + +//------------------------------------------------------------------------------ +// Structures +//------------------------------------------------------------------------------ + +/// LUN structure +typedef struct { + + /// Pointer to a SBCInquiryData instance. + SBCInquiryData *inquiryData; + /// Fifo for USB transfer, must be assigned. + MSDIOFifo ioFifo; + /// Pointer to Media instance for the LUN. + Media *media; + /// Pointer to a Monitor Function to analyze the flow of LUN. + /// \param flowDirection 1 - device to host (READ10) + /// 0 - host to device (WRITE10) + /// \param dataLength Length of data transferred in bytes. + /// \param fifoNullCount Times that FIFO is NULL to wait + /// \param fifoFullCount Times that FIFO is filled to wait + void (*dataMonitor)(unsigned char flowDirection, + unsigned int dataLength, + unsigned int fifoNullCount, + unsigned int fifoFullCount); + /// The start position of the media (blocks) allocated to the LUN. + unsigned int baseAddress; + /// The size of the media (blocks) allocated to the LUN. + unsigned int size; + /// Sector size of the media in number of media blocks + unsigned short blockSize; + /// The LUN can be readonly even the media is writable +#ifdef __cplusplus + unsigned char protectd; +#else + unsigned char protected; +#endif + + /// The LUN status (Ejected/Changed/) + unsigned char status; + + /// Data for the RequestSense command. + SBCRequestSenseData requestSenseData; + /// Data for the ReadCapacity command. + SBCReadCapacity10Data readCapacityData; + +} MSDLun; + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +extern void LUN_Init(MSDLun *lun, + Media *media, + unsigned char *ioBuffer, + unsigned int ioBufferSize, + unsigned int baseAddress, + unsigned int size, + unsigned short blockSize, +#ifdef __cplusplus + unsigned char protectd, +#else + unsigned char protected, +#endif + void (*dataMonitor)(unsigned char flowDirection, + unsigned int dataLength, + unsigned int fifoNullCount, + unsigned int fifoFullCount)); + +extern unsigned char LUN_Eject(MSDLun *lun); + +extern unsigned char LUN_Write(MSDLun *lun, + unsigned int blockAddress, + void *data, + unsigned int length, + TransferCallback callback, + void *argument); + +extern unsigned char LUN_Read(MSDLun *lun, + unsigned int blockAddress, + void *data, + unsigned int length, + TransferCallback callback, + void *argument); + +#endif //#ifndef MSDLUN_H + diff --git a/radio/bootloader/usb/device/massstorage/SBC.h b/radio/bootloader/usb/device/massstorage/SBC.h new file mode 100644 index 000000000..3c3f93c69 --- /dev/null +++ b/radio/bootloader/usb/device/massstorage/SBC.h @@ -0,0 +1,653 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// !Purpose +/// +/// SCSI definitions. +/// +/// !Usage +/// +/// -# After command block received, Access and decode the SCSI command block +/// with SBCCommand structure. +//------------------------------------------------------------------------------ + +#ifndef SBC_H +#define SBC_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SBC Operation Codes" +/// This page lists operation codes of commands described in the SBC-3 +/// standard. +/// +/// \note That most commands are actually defined in other standards, +/// like SPC-4. Optional commands are not included here. +/// +/// \see sbc3r07.pdf - Section 5.1 - Table 12 +/// \see spc4r06.pdf +/// \see SBCCommand +/// +/// !Codes +/// - SBC_INQUIRY +/// - SBC_READ_10 +/// - SBC_READ_CAPACITY_10 +/// - SBC_REQUEST_SENSE +/// - SBC_TEST_UNIT_READY +/// - SBC_WRITE_10 +/// +/// !Optional Codes but required by Windows +/// - SBC_PREVENT_ALLOW_MEDIUM_REMOVAL +/// - SBC_MODE_SENSE_6 +/// - SBC_VERIFY_10 +/// - SBC_READ_FORMAT_CAPACITIES + +/// Request information regarding parameters of the target and Logical Unit. +#define SBC_INQUIRY 0x12 +/// Request the transfer data to the host. +#define SBC_READ_10 0x28 +/// Request capacities of the currently installed medium. +#define SBC_READ_CAPACITY_10 0x25 +/// Request that the device server transfer sense data. +#define SBC_REQUEST_SENSE 0x03 +/// Check if the LUN is ready +#define SBC_TEST_UNIT_READY 0x00 +/// Request that the device write the data transferred by the host. +#define SBC_WRITE_10 0x2A + +/// Request that the target enable or disable the removal of the medium in +/// the Logical Unit. +#define SBC_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E +/// Report parameters. +#define SBC_MODE_SENSE_6 0x1A +/// Request that the %device verify the data on the medium. +#define SBC_VERIFY_10 0x2F +/// Request a list of the possible capacities that can be formatted on medium +#define SBC_READ_FORMAT_CAPACITIES 0x23 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SBC Periph. Qualifiers" +/// This page lists the peripheral qualifier values specified in the INQUIRY +/// data +/// \see spc4r06.pdf - Section 6.4.2 - Table 83 +/// \see SBCInquiryData +/// +/// !Qualifiers +/// - SBC_PERIPHERAL_DEVICE_CONNECTED +/// - SBC_PERIPHERAL_DEVICE_NOT_CONNECTED +/// - SBC_PERIPHERAL_DEVICE_NOT_SUPPORTED + +#define SBC_PERIPHERAL_DEVICE_CONNECTED 0x00 +#define SBC_PERIPHERAL_DEVICE_NOT_CONNECTED 0x01 +#define SBC_PERIPHERAL_DEVICE_NOT_SUPPORTED 0x03 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SBC Periph. Types" +/// This page lists peripheral device types specified in the INQUIRY data +/// \see spc4r06.pdf - Section 6.4.2 - Table 84 +/// \see SBCInquiryData +/// +/// !Types +/// - SBC_DIRECT_ACCESS_BLOCK_DEVICE +/// - SBC_SEQUENTIAL_ACCESS_DEVICE +/// - SBC_PRINTER_DEVICE +/// - SBC_PROCESSOR_DEVICE +/// - SBC_WRITE_ONCE_DEVICE +/// - SBC_CD_DVD_DEVICE +/// - SBC_SCANNER_DEVICE +/// - SBC_OPTICAL_MEMORY_DEVICE +/// - SBC_MEDIA_CHANGER_DEVICE +/// - SBC_COMMUNICATION_DEVICE +/// - SBC_STORAGE_ARRAY_CONTROLLER_DEVICE +/// - SBC_ENCLOSURE_SERVICES_DEVICE +/// - SBC_SIMPLIFIED_DIRECT_ACCESS_DEVICE +/// - SBC_OPTICAL_CARD_READER_WRITER_DEVICE +/// - SBC_BRIDGE_CONTROLLER_COMMANDS +/// - SBC_OBJECT_BASED_STORAGE_DEVICE + +#define SBC_DIRECT_ACCESS_BLOCK_DEVICE 0x00 +#define SBC_SEQUENTIAL_ACCESS_DEVICE 0x01 +#define SBC_PRINTER_DEVICE 0x02 +#define SBC_PROCESSOR_DEVICE 0x03 +#define SBC_WRITE_ONCE_DEVICE 0x04 +#define SBC_CD_DVD_DEVICE 0x05 +#define SBC_SCANNER_DEVICE 0x06 +#define SBC_OPTICAL_MEMORY_DEVICE 0x07 +#define SBC_MEDIA_CHANGER_DEVICE 0x08 +#define SBC_COMMUNICATION_DEVICE 0x09 +#define SBC_STORAGE_ARRAY_CONTROLLER_DEVICE 0x0C +#define SBC_ENCLOSURE_SERVICES_DEVICE 0x0D +#define SBC_SIMPLIFIED_DIRECT_ACCESS_DEVICE 0x0E +#define SBC_OPTICAL_CARD_READER_WRITER_DEVICE 0x0F +#define SBC_BRIDGE_CONTROLLER_COMMANDS 0x10 +#define SBC_OBJECT_BASED_STORAGE_DEVICE 0x11 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \brief Version value for the SBC-3 specification +/// \see spc4r06.pdf - Section 6.4.2 - Table 85 +#define SBC_SPC_VERSION_4 0x06 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \brief Values for the TPGS field returned in INQUIRY data +/// \see spc4r06.pdf - Section 6.4.2 - Table 86 +#define SBC_TPGS_NONE 0x0 +#define SBC_TPGS_ASYMMETRIC 0x1 +#define SBC_TPGS_SYMMETRIC 0x2 +#define SBC_TPGS_BOTH 0x3 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \brief Version descriptor value for the SBC-3 specification +/// \see spc4r06.pdf - Section 6.4.2 - Table 87 +#define SBC_VERSION_DESCRIPTOR_SBC_3 0x04C0 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SBC Sense Response Codes" +/// This page lists sense data response codes returned in REQUEST SENSE data +/// \see spc4r06.pdf - Section 4.5.1 - Table 12 +/// +/// !Codes +/// - SBC_SENSE_DATA_FIXED_CURRENT +/// - SBC_SENSE_DATA_FIXED_DEFERRED +/// - SBC_SENSE_DATA_DESCRIPTOR_CURRENT +/// - SBC_SENSE_DATA_DESCRIPTOR_DEFERRED + +#define SBC_SENSE_DATA_FIXED_CURRENT 0x70 +#define SBC_SENSE_DATA_FIXED_DEFERRED 0x71 +#define SBC_SENSE_DATA_DESCRIPTOR_CURRENT 0x72 +#define SBC_SENSE_DATA_DESCRIPTOR_DEFERRED 0x73 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SBC Sense Keys" +/// This page lists sense key values returned in the REQUEST SENSE data +/// \see spc4r06.pdf - Section 4.5.6 - Table 27 +/// +/// !Keys +/// - SBC_SENSE_KEY_NO_SENSE +/// - SBC_SENSE_KEY_RECOVERED_ERROR +/// - SBC_SENSE_KEY_NOT_READY +/// - SBC_SENSE_KEY_MEDIUM_ERROR +/// - SBC_SENSE_KEY_HARDWARE_ERROR +/// - SBC_SENSE_KEY_ILLEGAL_REQUEST +/// - SBC_SENSE_KEY_UNIT_ATTENTION +/// - SBC_SENSE_KEY_DATA_PROTECT +/// - SBC_SENSE_KEY_BLANK_CHECK +/// - SBC_SENSE_KEY_VENDOR_SPECIFIC +/// - SBC_SENSE_KEY_COPY_ABORTED +/// - SBC_SENSE_KEY_ABORTED_COMMAND +/// - SBC_SENSE_KEY_VOLUME_OVERFLOW +/// - SBC_SENSE_KEY_MISCOMPARE + +/// No specific sense key. Successful command. +#define SBC_SENSE_KEY_NO_SENSE 0x00 +/// Command completed succesfully with some recovery action by the %device. +#define SBC_SENSE_KEY_RECOVERED_ERROR 0x01 +/// The device can not be accessed. +#define SBC_SENSE_KEY_NOT_READY 0x02 +/// Command terminated with a error condition that was probably caused by a +/// flaw in the medium or an error in the recorded data. +#define SBC_SENSE_KEY_MEDIUM_ERROR 0x03 +/// Hardware failure while performing the command or during a self test. +#define SBC_SENSE_KEY_HARDWARE_ERROR 0x04 +/// Illegal parameter found in the command or additional parameters. +#define SBC_SENSE_KEY_ILLEGAL_REQUEST 0x05 +/// Removable medium may have been changed or the %device has been reset. +#define SBC_SENSE_KEY_UNIT_ATTENTION 0x06 +/// Write on a block that is protected. +#define SBC_SENSE_KEY_DATA_PROTECT 0x07 +/// Indicates that a write-once device or a sequential-access device +/// encountered blank medium or format-defined end-of-data indication while +/// reading or a write-once device encountered a non-blank medium while writing. +#define SBC_SENSE_KEY_BLANK_CHECK 0x08 +/// Reporting vendor specific conditions. +#define SBC_SENSE_KEY_VENDOR_SPECIFIC 0x09 +/// EXTENDED COPY command was aborted. +#define SBC_SENSE_KEY_COPY_ABORTED 0x0A +/// Device aborted the command. +#define SBC_SENSE_KEY_ABORTED_COMMAND 0x0B +/// A buffered peripheral device is overflow. +#define SBC_SENSE_KEY_VOLUME_OVERFLOW 0x0D +/// The source data did not match the data read from the medium. +#define SBC_SENSE_KEY_MISCOMPARE 0x0E +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SBC Sense Additionals" +/// This page lists additional sense code values returned in REQUEST SENSE data +/// \see spc4r06.pdf - Section 4.5.6 - Table 28 +/// +/// !Additional Codes +/// - SBC_ASC_LOGICAL_UNIT_NOT_READY +/// - SBC_ASC_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE +/// - SBC_ASC_INVALID_FIELD_IN_CDB +/// - SBC_ASC_WRITE_PROTECTED +/// - SBC_ASC_FORMAT_CORRUPTED +/// - SBC_ASC_INVALID_COMMAND_OPERATION_CODE +/// - SBC_ASC_TOO_MUCH_WRITE_DATA +/// - SBC_ASC_NOT_READY_TO_READY_CHANGE +/// - SBC_ASC_MEDIUM_NOT_PRESENT + +#define SBC_ASC_LOGICAL_UNIT_NOT_READY 0x04 +#define SBC_ASC_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE 0x21 +#define SBC_ASC_INVALID_FIELD_IN_CDB 0x24 +#define SBC_ASC_WRITE_PROTECTED 0x27 +#define SBC_ASC_FORMAT_CORRUPTED 0x31 +#define SBC_ASC_INVALID_COMMAND_OPERATION_CODE 0x20 +#define SBC_ASC_TOO_MUCH_WRITE_DATA 0x26 +#define SBC_ASC_NOT_READY_TO_READY_CHANGE 0x28 +#define SBC_ASC_MEDIUM_NOT_PRESENT 0x3A +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \brief MEDIUM TYPE field value for direct-access block devices +/// \see sbc3r06.pdf - Section 6.3.1 +#define SBC_MEDIUM_TYPE_DIRECT_ACCESS_BLOCK_DEVICE 0x00 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \brief MRIE field values +/// \see sbc3r06.pdf - Section 7.4.11 - Table 286 +#define SBC_MRIE_NO_REPORTING 0x00 +#define SBC_MRIE_ASYNCHRONOUS 0x01 +#define SBC_MRIE_GENERATE_UNIT_ATTENTION 0x02 +#define SBC_MRIE_COND_GENERATE_RECOVERED_ERROR 0x03 +#define SBC_MRIE_UNCOND_GENERATE_RECOVERED_ERROR 0x04 +#define SBC_MRIE_GENERATE_NO_SENSE 0x05 +#define SBC_MRIE_ON_REQUEST 0x06 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \brief Supported mode pages +/// \see sbc3r06.pdf - Section 6.3.1 - Table 115 +#define SBC_PAGE_READ_WRITE_ERROR_RECOVERY 0x01 +#define SBC_PAGE_INFORMATIONAL_EXCEPTIONS_CONTROL 0x1C +#define SBC_PAGE_RETURN_ALL 0x3F +#define SBC_PAGE_VENDOR_SPECIFIC 0x00 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "MSD Endian Macros" +/// This page lists the macros for endianness conversion. +/// +/// !Macros +/// - WORDB +/// - DWORDB +/// - STORE_DWORDB +/// - STORE_WORDB +/// \brief Converts a byte array to a word value using the big endian format +#define WORDB(bytes) ((unsigned short) ((bytes[0] << 8) | bytes[1])) + +/// \brief Converts a byte array to a dword value using the big endian format +#define DWORDB(bytes) ((unsigned int) ((bytes[0] << 24) | (bytes[1] << 16) \ + | (bytes[2] << 8) | bytes[3])) + +/// \brief Stores a dword value in a byte array, in big endian format +#define STORE_DWORDB(dword, bytes) \ + bytes[0] = (unsigned char) (((dword) >> 24) & 0xFF); \ + bytes[1] = (unsigned char) (((dword) >> 16) & 0xFF); \ + bytes[2] = (unsigned char) (((dword) >> 8) & 0xFF); \ + bytes[3] = (unsigned char) ((dword) & 0xFF); + +/// \brief Stores a word value in a byte array, in big endian format +#define STORE_WORDB(word, bytes) \ + bytes[0] = (unsigned char) (((word) >> 8) & 0xFF); \ + bytes[1] = (unsigned char) ((word) & 0xFF); +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Structures +//------------------------------------------------------------------------------ + +#ifdef __ICCARM__ // IAR +#pragma pack(1) // IAR +#define __attribute__(...) // IAR +#endif // IAR + +//------------------------------------------------------------------------------ +/// \brief Structure for the INQUIRY command +/// \see spc4r06.pdf - Section 6.4.1 - Table 81 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bOperationCode; //!< 0x12 : SBC_INQUIRY + unsigned char isEVPD:1, //!< Type of requested data + bReserved1:7; //!< Reserved bits + unsigned char bPageCode; //!< Specifies the VPD to return + unsigned char pAllocationLength[2]; //!< Size of host buffer + unsigned char bControl; //!< 0x00 + +} __attribute__ ((packed)) SBCInquiry; // GCC + +//------------------------------------------------------------------------------ +/// \brief Standard INQUIRY data format returned by the device +/// \see spc4r06.pdf - Section 6.4.2 - Table 82 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bPeripheralDeviceType:5, //!< Peripheral device type + bPeripheralQualifier :3; //!< Peripheral qualifier + unsigned char bReserved1:7, //!< Reserved bits + isRMB :1; //!< Is media removable ? + unsigned char bVersion; //!< SPC version used + unsigned char bResponseDataFormat:4, //!< Must be 0x2 + isHIGHSUP :1, //!< Hierarchical addressing used ? + isNORMACA :1, //!< ACA attribute supported ? + bObsolete1 :2; //!< Obsolete bits + unsigned char bAdditionalLength; //!< Length of remaining INQUIRY data + unsigned char isSCCS :1, //!< Embedded SCC ? + isACC :1, //!< Access control coordinator ? + bTPGS :2, //!< Target port support group + is3PC :1, //!< Third-party copy supported ? + bReserved2:2, //!< Reserved bits + isProtect :1; //!< Protection info supported ? + unsigned char bObsolete2:1, //!< Obsolete bit + isEncServ :1, //!< Embedded enclosure service comp? + isVS :1, //!< ??? + isMultiP :1, //!< Multi-port device ? + bObsolete3:3, //!< Obsolete bits + bUnused1 :1; //!< Unused feature + unsigned char bUnused2:6, //!< Unused features + isCmdQue:1, //!< Task management model supported ? + isVS2 :1; //!< ??? + unsigned char pVendorID[8]; //!< T10 vendor identification + unsigned char pProductID[16]; //!< Vendor-defined product ID + unsigned char pProductRevisionLevel[4];//!< Vendor-defined product revision + unsigned char pVendorSpecific[20]; //!< Vendor-specific data + unsigned char bUnused3; //!< Unused features + unsigned char bReserved3; //!< Reserved bits + unsigned short pVersionDescriptors[8]; //!< Standards the device complies to + unsigned char pReserved4[22]; //!< Reserved bytes + +} __attribute__ ((packed)) SBCInquiryData; // GCC + +//------------------------------------------------------------------------------ +/// \brief Data structure for the READ (10) command +/// \see sbc3r07.pdf - Section 5.7 - Table 34 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bOperationCode; //!< 0x28 : SBC_READ_10 + unsigned char bObsolete1:1, //!< Obsolete bit + isFUA_NV:1, //!< Cache control bit + bReserved1:1, //!< Reserved bit + isFUA:1, //!< Cache control bit + isDPO:1, //!< Cache control bit + bRdProtect:3; //!< Protection information to send + unsigned char pLogicalBlockAddress[4]; //!< Index of first block to read + unsigned char bGroupNumber:5, //!< Information grouping + bReserved2:3; //!< Reserved bits + unsigned char pTransferLength[2]; //!< Number of blocks to transmit + unsigned char bControl; //!< 0x00 + +} __attribute__ ((packed)) SBCRead10; // GCC + +//------------------------------------------------------------------------------ +/// \brief Structure for the READ CAPACITY (10) command +/// \see sbc3r07.pdf - Section 5.11.1 - Table 40 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bOperationCode; //!< 0x25 : RBC_READ_CAPACITY + unsigned char bObsolete1:1, //!< Obsolete bit + bReserved1:7; //!< Reserved bits + unsigned char pLogicalBlockAddress[4]; //!< Block to evaluate if PMI is set + unsigned char pReserved2[2]; //!< Reserved bytes + unsigned char isPMI:1, //!< Partial medium indicator bit + bReserved3:7; //!< Reserved bits + unsigned char bControl; //!< 0x00 + +} __attribute__ ((packed)) SBCReadCapacity10; + +//------------------------------------------------------------------------------ +/// \brief Data returned by the device after a READ CAPACITY (10) command +/// \see sbc3r07.pdf - Section 5.11.2 - Table 41 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char pLogicalBlockAddress[4]; //!< Address of last logical block + unsigned char pLogicalBlockLength[4]; //!< Length of each logical block + +} __attribute__ ((packed)) SBCReadCapacity10Data; + +//------------------------------------------------------------------------------ +/// \brief Structure for the REQUEST SENSE command +/// \see spc4r06.pdf - Section 6.26 - Table 170 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bOperationCode; //!< 0x03 : SBC_REQUEST_SENSE + unsigned char isDesc :1, //!< Type of information expected + bReserved1:7; //!< Reserved bits + unsigned char pReserved2[2]; //!< Reserved bytes + unsigned char bAllocationLength; //!< Size of host buffer + unsigned char bControl; //!< 0x00 + +} __attribute__ ((packed)) SBCRequestSense; + +//------------------------------------------------------------------------------ +/// \brief Fixed format sense data returned after a REQUEST SENSE command has +/// been received with a DESC bit cleared. +/// \see spc4r06.pdf - Section 4.5.3 - Table 26 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bResponseCode:7, //!< Sense data format + isValid :1; //!< Information field is standard + unsigned char bObsolete1; //!< Obsolete byte + unsigned char bSenseKey :4, //!< Generic error information + bReserved1:1, //!< Reserved bit + isILI :1, //!< SSC + isEOM :1, //!< SSC + isFilemark:1; //!< SSC + unsigned char pInformation[4]; //!< Command-specific + unsigned char bAdditionalSenseLength; //!< sizeof(SBCRequestSense_data)-8 + unsigned char pCommandSpecificInformation[4]; //!< Command-specific + unsigned char bAdditionalSenseCode; //!< Additional error information + unsigned char bAdditionalSenseCodeQualifier; //!< Further error information + unsigned char bFieldReplaceableUnitCode; //!< Specific component code + unsigned char bSenseKeySpecific:7, //!< Additional exception info + isSKSV :1; //!< Is sense key specific valid? + unsigned char pSenseKeySpecific[2]; //!< Additional exception info + +} __attribute__ ((packed)) SBCRequestSenseData; + +//------------------------------------------------------------------------------ +/// \brief Data structure for the TEST UNIT READY command +/// \see spc4r06.pdf - Section 6.34 - Table 192 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bOperationCode; //!< 0x00 : SBC_TEST_UNIT_READY + unsigned char pReserved1[4]; //!< Reserved bits + unsigned char bControl; //!< 0x00 + +} __attribute__ ((packed)) SBCTestUnitReady; // GCC + +//------------------------------------------------------------------------------ +/// \brief Structure for the WRITE (10) command +/// \see sbc3r07.pdf - Section 5.26 - Table 70 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bOperationCode; //!< 0x2A : SBC_WRITE_10 + unsigned char bObsolete1:1, //!< Obsolete bit + isFUA_NV:1, //!< Cache control bit + bReserved1:1, //!< Reserved bit + isFUA:1, //!< Cache control bit + isDPO:1, //!< Cache control bit + bWrProtect:3; //!< Protection information to send + unsigned char pLogicalBlockAddress[4]; //!< First block to write + unsigned char bGroupNumber:5, //!< Information grouping + bReserved2:3; //!< Reserved bits + unsigned char pTransferLength[2]; //!< Number of blocks to write + unsigned char bControl; //!< 0x00 + +} __attribute__ ((packed)) SBCWrite10; + +//------------------------------------------------------------------------------ +/// \brief Structure for the PREVENT/ALLOW MEDIUM REMOVAL command +/// \see sbc3r07.pdf - Section 5.5 - Table 30 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bOperationCode; //!< 0x1E : SBC_PREVENT_ALLOW_MEDIUM_REMOVAL + unsigned char pReserved1[3]; //!< Reserved bytes + unsigned char bPrevent:2, //!< Accept/prohibit removal + bReserved2:6; //!< Reserved bits + unsigned char bControl; //!< 0x00 + +} __attribute__ ((packed)) SBCMediumRemoval; // GCC + +//------------------------------------------------------------------------------ +/// \brief Structure for the MODE SENSE (6) command +/// \see spc4r06 - Section 6.9.1 - Table 98 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bOperationCode; //!< 0x1A : SBC_MODE_SENSE_6 + unsigned char bReserved1:3, //!< Reserved bits + isDBD:1, //!< Disable block descriptors bit + bReserved2:4; //!< Reserved bits + unsigned char bPageCode:6, //!< Mode page to return + bPC:2; //!< Type of parameter values to return + unsigned char bSubpageCode; //!< Mode subpage to return + unsigned char bAllocationLength; //!< Host buffer allocated size + unsigned char bControl; //!< 0x00 + +} __attribute__ ((packed)) SBCModeSense6; // GCC + +//------------------------------------------------------------------------------ +/// \brief Header for the data returned after a MODE SENSE (6) command +/// \see spc4r06.pdf - Section 7.4.3 - Table 268 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bModeDataLength; //!< Length of mode data to follow + unsigned char bMediumType; //!< Type of medium (SBC_MEDIUM_TYPE_DIRECT_ACCESS_BLOCK_DEVICE) + unsigned char bReserved1:4, //!< Reserved bits + isDPOFUA:1, //!< DPO/FUA bits supported ? + bReserved2:2, //!< Reserved bits + isWP:1; //!< Is medium write-protected ? + unsigned char bBlockDescriptorLength; //!< Length of all block descriptors + +} __attribute__ ((packed)) SBCModeParameterHeader6; // GCC + +//------------------------------------------------------------------------------ +/// \brief Informational exceptions control mode page +/// \see spc4r06.pdf - Section 7.4.11 - Table 285 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bPageCode:6, //!< 0x1C : SBC_PAGE_INFORMATIONAL_EXCEPTIONS_CONTROL + isSPF:1, //!< Page or subpage data format + isPS:1; //!< Parameters saveable ? + unsigned char bPageLength; //!< Length of page data (0x0A) + unsigned char isLogErr:1, //!< Should informational exceptions be logged ? + isEBackErr:1, //!< Enable background error bit + isTest:1, //!< Create a device test failure ? + isDExcpt:1, //!< Disable exception control bit + isEWasc:1, //!< Report warnings ? + isEBF:1, //!< Enable background function bit + bReserved1:1, //!< Reserved bit + isPerf:1; //!< Delay acceptable when treating exceptions ? + unsigned char bMRIE:4, //!< Method of reporting informational exceptions + bReserved2:4; //!< Reserved bits + unsigned char pIntervalTimer[4]; //!< Error reporting period + unsigned char pReportCount[4]; //!< Maximum number of time a report can be issued + +} __attribute__ ((packed)) SBCInformationalExceptionsControl; // GCC + +//------------------------------------------------------------------------------ +/// \brief Read/write error recovery mode page +/// \see sbc3r07.pdf - Section 6.3.5 - Table 122 +//------------------------------------------------------------------------------ +typedef struct { + + unsigned char bPageCode:6, //!< 0x01 : SBC_PAGE_READ_WRITE_ERROR_RECOVERY + isSPF:1, //!< Page or subpage data format + isPS:1; //!< Parameters saveable ? + unsigned char bPageLength; //!< Length of page data (0x0A) + unsigned char isDCR:1, //!< Disable correction bit + isDTE:1, //!< Data terminate on error bit + isPER:1, //!< Post error bit + isEER:1, //!< Enable early recovery bit + isRC:1, //!< Read continuous bit + isTB:1, //!< Transfer block bit + isARRE:1, //!< Automatic read reallocation enabled bit + isAWRE:1; //!< Automatic write reallocation enabled bit + unsigned char bReadRetryCount; //!< Number of retries when reading + unsigned char pObsolete1[3]; //!< Obsolete bytes + unsigned char bReserved1; //!< Reserved byte + unsigned char bWriteRetryCount; //!< Number of retries when writing + unsigned char bReserved2; //!< Reserved byte + unsigned char pRecoveryTimeLimit[2]; //!< Maximum time duration for error recovery + +} __attribute__ ((packed)) SBCReadWriteErrorRecovery; // GCC + +//------------------------------------------------------------------------------ +/// \brief Generic structure for holding information about SBC commands +/// \see SBCInquiry +/// \see SBCRead10 +/// \see SBCReadCapacity10 +/// \see SBCRequestSense +/// \see SBCTestUnitReady +/// \see SBCWrite10 +/// \see SBCMediumRemoval +/// \see SBCModeSense6 +//------------------------------------------------------------------------------ +typedef union { + + unsigned char bOperationCode; //!< Operation code of the command + SBCInquiry inquiry; //!< INQUIRY command + SBCRead10 read10; //!< READ (10) command + SBCReadCapacity10 readCapacity10; //!< READ CAPACITY (10) command + SBCRequestSense requestSense; //!< REQUEST SENSE command + SBCTestUnitReady testUnitReady; //!< TEST UNIT READY command + SBCWrite10 write10; //!< WRITE (10) command + SBCMediumRemoval mediumRemoval; //!< PREVENT/ALLOW MEDIUM REMOVAL command + SBCModeSense6 modeSense6; //!< MODE SENSE (6) command + +} SBCCommand; + +#ifdef __ICCARM__ // IAR +#pragma pack() // IAR +#endif // IAR + +#endif //#ifndef SBC_H + diff --git a/radio/bootloader/usb/device/massstorage/SBCMethods.c b/radio/bootloader/usb/device/massstorage/SBCMethods.c new file mode 100644 index 000000000..26c85eedf --- /dev/null +++ b/radio/bootloader/usb/device/massstorage/SBCMethods.c @@ -0,0 +1,1624 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "SBCMethods.h" +#include "MSDDStateMachine.h" +#include + +#include "MSDIOFifo.h" + +//------------------------------------------------------------------------------ +// Global variables +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Macros +//------------------------------------------------------------------------------ + +#ifdef MSDIO_READ10_CHUNK_SIZE +/// READ10 - Read data from specific LUN to FIFO +#define SBC_READ_CHUNK(pLun, lba, pFifo, pCb, pArg) \ + LUN_Read((pLun), (lba), \ + &(pFifo)->pBuffer[(pFifo)->inputNdx], \ + ((pFifo)->chunkSize/(pFifo)->blockSize), \ + (TransferCallback)(pCb), (void*)pArg) +/// READ10 - Transfer data from FIFO to USB +#define SBC_TX_CHUNK(pFifo, pCb, pArg) \ + MSDD_Write(&(pFifo)->pBuffer[(pFifo)->outputNdx], \ + (pFifo)->chunkSize, \ + (TransferCallback)(pCb), (void*)(pArg)) +#endif + +#ifdef MSDIO_WRITE10_CHUNK_SIZE +/// WRITE10 - Read data from USB to FIFO +#define SBC_RX_CHUNK(pFifo,pCb,pArg) \ + MSDD_Read(&(pFifo)->pBuffer[(pFifo)->inputNdx], \ + (pFifo)->chunkSize, \ + (TransferCallback)(pCb), (void*)(pArg)) +/// WRITE10 - Write data from FIFO to LUN +#define SBC_WRITE_CHUNK(pLun, lba, pFifo, pCb, pArg) \ + LUN_Write((pLun), (lba), \ + &(pFifo)->pBuffer[(pFifo)->outputNdx], \ + ((pFifo)->chunkSize/(pFifo)->blockSize), \ + (TransferCallback)(pCb), (void*)(pArg)) +#endif + + +//------------------------------------------------------------------------------ +//! \brief Header for the mode pages data +//! \see SBCModeParameterHeader6 +//------------------------------------------------------------------------------ +static const SBCModeParameterHeader6 modeParameterHeader6 = { + + sizeof(SBCModeParameterHeader6) - 1, //! Length is 0x03 + SBC_MEDIUM_TYPE_DIRECT_ACCESS_BLOCK_DEVICE, //! Direct-access block device + 0, //! Reserved bits + 0, //! DPO/FUA not supported + 0, //! Reserved bits + 0, //! not write-protected + 0 //! No block descriptor +}; + +//------------------------------------------------------------------------------ +// Internal functions +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +//! \brief Check if the LUN is ready. +//! \param lun Pointer to the LUN affected by the command +//! \return 1 if the LUN is ready to be written +//! \see MSDLun +//------------------------------------------------------------------------------ +static unsigned char SBCLunIsReady(MSDLun *lun) +{ + unsigned char lunIsReady = 0; + Media *media = lun->media; + + if (media == 0 || lun->status < LUN_CHANGED) { + TRACE_INFO("SBCLunIsReady: Not Present!\n\r"); + SBC_UpdateSenseData(&(lun->requestSenseData), + SBC_SENSE_KEY_NOT_READY, + SBC_ASC_MEDIUM_NOT_PRESENT, + 0); + + } + else if (lun->status < LUN_READY) { + TRACE_INFO("SBCLunIsReady: Changing!\n\r"); + SBC_UpdateSenseData(&(lun->requestSenseData), + SBC_SENSE_KEY_UNIT_ATTENTION, + SBC_ASC_NOT_READY_TO_READY_CHANGE, + 0); + lun->status = LUN_READY; + } + else { + + lunIsReady = 1; + } + + return lunIsReady; +} +//------------------------------------------------------------------------------ +//! \brief Check if the LUN can write. +//! \param lun Pointer to the LUN affected by the command +//! \return 1 if the LUN is ready to be written +//! \see MSDLun +//------------------------------------------------------------------------------ +static unsigned char SBCLunCanBeWritten(MSDLun *lun) +{ + unsigned char canBeWritten = 0; + + if (!SBCLunIsReady(lun)) { + + TRACE_WARNING("SBCLunCanBeWritten: Not Ready!\n\r"); + } + else if (lun->protected) { + + TRACE_WARNING("SBCLunCanBeWritten: Protected!\n\r"); + SBC_UpdateSenseData(&(lun->requestSenseData), + SBC_SENSE_KEY_DATA_PROTECT, + SBC_ASC_WRITE_PROTECTED, + 0); + } + else { + + canBeWritten = 1; + } + + return canBeWritten; +} + +//------------------------------------------------------------------------------ +//! \brief Performs a WRITE (10) command on the specified LUN. +//! +//! The data to write is first received from the USB host and then +//! actually written on the media. +//! This function operates asynchronously and must be called multiple +//! times to complete. A result code of MSDDriver_STATUS_INCOMPLETE +//! indicates that at least another call of the method is necessary. +//! \param lun Pointer to the LUN affected by the command +//! \param commandState Current state of the command +//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) +//! \see MSDLun +//! \see MSDCommandState +//------------------------------------------------------------------------------ +static unsigned char SBC_Write10(MSDLun *lun, + MSDCommandState *commandState) +{ + unsigned char status; + unsigned char result = MSDD_STATUS_INCOMPLETE; + SBCRead10 *command = (SBCRead10 *) commandState->cbw.pCommand; + MSDTransfer *transfer = &(commandState->transfer); + MSDTransfer *disktransfer = &(commandState->disktransfer); + MSDIOFifo *fifo = &lun->ioFifo; + Media *media = lun->media; + + // Init command state + if (commandState->state == 0) { + + commandState->state = SBC_STATE_WRITE; + + // The command should not be proceeded if READONLY + if (!SBCLunCanBeWritten(lun)) { + + return MSDD_STATUS_RW; + } + else { + + + // Initialize FIFO + fifo->dataTotal = commandState->length; + fifo->blockSize = lun->blockSize * media->blockSize; + #ifdef MSDIO_WRITE10_CHUNK_SIZE + if ( fifo->dataTotal >= 64 * 1024 + && fifo->blockSize < MSDIO_WRITE10_CHUNK_SIZE) + fifo->chunkSize = MSDIO_WRITE10_CHUNK_SIZE; + else + fifo->chunkSize = fifo->blockSize; + #endif + fifo->fullCnt = 0; + fifo->nullCnt = 0; + + // Initialize FIFO output (Disk) + fifo->outputNdx = 0; + fifo->outputTotal = 0; + fifo->outputState = MSDIO_IDLE; + transfer->semaphore = 0; + + // Initialize FIFO input (USB) + fifo->inputNdx = 0; + fifo->inputTotal = 0; + fifo->inputState = MSDIO_START; + disktransfer->semaphore = 0; + } + + } + + if (commandState->length == 0) { + + // Perform the callback! + if (lun->dataMonitor) { + + lun->dataMonitor(0, fifo->dataTotal, fifo->nullCnt, fifo->fullCnt); + } + return MSDD_STATUS_SUCCESS; + } + + // USB receive task + switch(fifo->inputState) { + + //------------------ + case MSDIO_IDLE: + //------------------ + if (fifo->inputTotal < fifo->dataTotal && + fifo->inputTotal - fifo->outputTotal < fifo->bufferSize) { + + fifo->inputState = MSDIO_START; + } + break; + + //------------------ + case MSDIO_START: + //------------------ + // Should not start if there is any disk error + if (fifo->outputState == MSDIO_ERROR) { + + TRACE_INFO_WP("udErr "); + fifo->inputState = MSDIO_ERROR; + break; + } + + // Read one block of data sent by the host + if (media->mappedWR) { + + // Directly read to memory + status = MSDD_Read((void*) + ((media->baseAddress + + (lun->baseAddress + + DWORDB(command->pLogicalBlockAddress) + * lun->blockSize + ) + ) * media->blockSize + ), + fifo->dataTotal, + (TransferCallback) MSDDriver_Callback, + (void *) transfer); + } + else { + #ifdef MSDIO_WRITE10_CHUNK_SIZE + status = SBC_RX_CHUNK(fifo, MSDDriver_Callback, transfer); + #else + // Read block to buffer + status = MSDD_Read((void*)&fifo->pBuffer[fifo->inputNdx], + fifo->blockSize, + (TransferCallback) MSDDriver_Callback, + (void *) transfer); + #endif + } + + // Check operation result code + if (status != USBD_STATUS_SUCCESS) { + + TRACE_WARNING( + "RBC_Write10: Failed to start receiving\n\r"); + SBC_UpdateSenseData(&(lun->requestSenseData), + SBC_SENSE_KEY_HARDWARE_ERROR, + 0, + 0); + result = MSDD_STATUS_ERROR; + } + else { + + TRACE_INFO_WP("uRx "); + + // Prepare next device state + fifo->inputState = MSDIO_WAIT; + } + break; // MSDIO_START + + //------------------ + case MSDIO_WAIT: + //------------------ + TRACE_INFO_WP("uWait "); + + // Check semaphore + if (transfer->semaphore > 0) { + + transfer->semaphore--; + fifo->inputState = MSDIO_NEXT; + } + break; + + //------------------ + case MSDIO_NEXT: + //------------------ + // Check the result code of the read operation + if (transfer->status != USBD_STATUS_SUCCESS) { + + TRACE_WARNING( + "RBC_Write10: Failed to received\n\r"); + SBC_UpdateSenseData(&(lun->requestSenseData), + SBC_SENSE_KEY_HARDWARE_ERROR, + 0, + 0); + result = MSDD_STATUS_ERROR; + } + else { + + TRACE_INFO_WP("uNxt "); + + // Mapped read, all data done + if (media->mappedWR) { + + fifo->inputTotal = fifo->dataTotal; + fifo->inputState = MSDIO_IDLE; + } + else { + + // Update input index + #ifdef MSDIO_WRITE10_CHUNK_SIZE + MSDIOFifo_IncNdx(fifo->inputNdx, + fifo->chunkSize, + fifo->bufferSize); + fifo->inputTotal += fifo->chunkSize; + #else + MSDIOFifo_IncNdx(fifo->inputNdx, + fifo->blockSize, + fifo->bufferSize); + fifo->inputTotal += fifo->blockSize; + #endif + + // Start Next block + // - All Data done? + if (fifo->inputTotal >= fifo->dataTotal) { + + fifo->inputState = MSDIO_IDLE; + } + // - Buffer full? + else if (fifo->inputNdx == fifo->outputNdx) { + fifo->inputState = MSDIO_IDLE; + fifo->fullCnt ++; + + TRACE_DEBUG_WP("ufFull%d ", fifo->inputNdx); + } + // - More data to transfer? + else if (fifo->inputTotal < fifo->dataTotal) { + fifo->inputState = MSDIO_START; + + TRACE_INFO_WP("uStart "); + } + // never executed ! + //else { + // fifo->inputState = MSDIO_IDLE; + // TRACE_INFO_WP("uDone "); + //} + } + + } + break; // MSDIO_NEXT + + //------------------ + case MSDIO_ERROR: + //------------------ + + TRACE_WARNING_WP("uErr "); + commandState->length -= fifo->inputTotal; + return MSDD_STATUS_RW; + + } + + // Disk write task + switch(fifo->outputState) { + + //------------------ + case MSDIO_IDLE: + //------------------ + if (fifo->outputTotal < fifo->inputTotal) { + + fifo->outputState = MSDIO_START; + } + break; + + //------------------ + case MSDIO_START: + //------------------ + + // Write the block to the media + if (media->mappedWR) { + + MSDDriver_Callback(disktransfer, MED_STATUS_SUCCESS, 0, 0); + status = LUN_STATUS_SUCCESS; + } + else { + #ifdef MSDIO_WRITE10_CHUNK_SIZE + status = SBC_WRITE_CHUNK(lun, DWORDB(command->pLogicalBlockAddress), + fifo, MSDDriver_Callback, disktransfer); + #else + status = LUN_Write(lun, + DWORDB(command->pLogicalBlockAddress), + &fifo->pBuffer[fifo->outputNdx], + 1, + (TransferCallback) MSDDriver_Callback, + (void *) disktransfer); + #endif + } + + // Check operation result code + if (status != USBD_STATUS_SUCCESS) { + + TRACE_WARNING( + "RBC_Write10: Failed to start write - "); + + if (!SBCLunCanBeWritten(lun)) { + + TRACE_WARNING("?\n\r"); + SBC_UpdateSenseData(&(lun->requestSenseData), + SBC_SENSE_KEY_NOT_READY, + 0, + 0); + } + + fifo->outputState = MSDIO_ERROR; + } + else { + + // Prepare next state + fifo->outputState = MSDIO_WAIT; + } + break; // MSDIO_START + + //------------------ + case MSDIO_WAIT: + //------------------ + TRACE_INFO_WP("dWait "); + + // Check semaphore value + if (disktransfer->semaphore > 0) { + + // Take semaphore and move to next state + disktransfer->semaphore--; + fifo->outputState = MSDIO_NEXT; + } + break; + + //------------------ + case MSDIO_NEXT: + //------------------ + // Check operation result code + if (transfer->status != USBD_STATUS_SUCCESS) { + + TRACE_WARNING( + "RBC_Write10: Failed to write\n\r"); + SBC_UpdateSenseData(&(lun->requestSenseData), + SBC_SENSE_KEY_RECOVERED_ERROR, + SBC_ASC_TOO_MUCH_WRITE_DATA, + 0); + result = MSDD_STATUS_ERROR; + } + else { + + TRACE_INFO_WP("dNxt "); + + // Update transfer length and block address + + // Mapped memory, done + if (media->mappedWR) { + + commandState->length = 0; + fifo->outputState = MSDIO_IDLE; + } + else { + + // Update output index + #ifdef MSDIO_WRITE10_CHUNK_SIZE + STORE_DWORDB(DWORDB(command->pLogicalBlockAddress) + + fifo->chunkSize/fifo->blockSize, + command->pLogicalBlockAddress); + MSDIOFifo_IncNdx(fifo->outputNdx, + fifo->chunkSize, + fifo->bufferSize); + fifo->outputTotal += fifo->chunkSize; + #else + STORE_DWORDB(DWORDB(command->pLogicalBlockAddress) + 1, + command->pLogicalBlockAddress); + MSDIOFifo_IncNdx(fifo->outputNdx, + fifo->blockSize, + fifo->bufferSize); + fifo->outputTotal += fifo->blockSize; + #endif + + // Start Next block + // - All data done? + if (fifo->outputTotal >= fifo->dataTotal) { + + fifo->outputState = MSDIO_IDLE; + commandState->length = 0; + TRACE_INFO_WP("dDone "); + } + // - Send next? + else if (fifo->outputTotal < fifo->inputTotal) { + + fifo->outputState = MSDIO_START; + TRACE_INFO_WP("dStart "); + } + // - Buffer Null? + else { + fifo->outputState = MSDIO_IDLE; + fifo->nullCnt ++; + + TRACE_DEBUG_WP("dfNull%d ", fifo->outputNdx); + } + } + } + break; // MSDIO_NEXT + + //------------------ + case MSDIO_ERROR: + //------------------ + break; + } + + return result; +} + +//------------------------------------------------------------------------------ +//! \brief Performs a READ (10) command on specified LUN. +//! +//! The data is first read from the media and then sent to the USB host. +//! This function operates asynchronously and must be called multiple +//! times to complete. A result code of MSDDriver_STATUS_INCOMPLETE +//! indicates that at least another call of the method is necessary. +//! \param lun Pointer to the LUN affected by the command +//! \param commandState Current state of the command +//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) +//! \see MSDLun +//! \see MSDCommandState +//------------------------------------------------------------------------------ +static unsigned char SBC_Read10(MSDLun *lun, + MSDCommandState *commandState) +{ + unsigned char status; + unsigned char result = MSDD_STATUS_INCOMPLETE; + SBCRead10 *command = (SBCRead10 *) commandState->cbw.pCommand; + MSDTransfer *transfer = &(commandState->transfer); + MSDTransfer *disktransfer = &(commandState->disktransfer); + MSDIOFifo *fifo = &lun->ioFifo; + Media *media = lun->media; + + // Init command state + if (commandState->state == 0) { + + commandState->state = SBC_STATE_READ; + + if (!SBCLunIsReady(lun)) { + + return MSDD_STATUS_RW; + } + else { + + // Initialize FIFO + fifo->dataTotal = commandState->length; + fifo->blockSize = lun->blockSize * media->blockSize; + #ifdef MSDIO_READ10_CHUNK_SIZE + if ( fifo->dataTotal >= 64*1024 + && fifo->blockSize < MSDIO_READ10_CHUNK_SIZE) + fifo->chunkSize = MSDIO_READ10_CHUNK_SIZE; + else + fifo->chunkSize = fifo->blockSize; + #endif + fifo->fullCnt = 0; + fifo->nullCnt = 0; + + #ifdef MSDIO_FIFO_OFFSET + // Enable offset if total size >= 2*bufferSize + if (fifo->dataTotal / fifo->bufferSize >= 2) + fifo->bufferOffset = MSDIO_FIFO_OFFSET; + else + fifo->bufferOffset = 0; + #endif + + // Initialize FIFO output (USB) + fifo->outputNdx = 0; + fifo->outputTotal = 0; + fifo->outputState = MSDIO_IDLE; + transfer->semaphore = 0; + + // Initialize FIFO input (Disk) + fifo->inputNdx = 0; + fifo->inputTotal = 0; + fifo->inputState = MSDIO_START; + disktransfer->semaphore = 0; + } + } + + // Check length + if (commandState->length == 0) { + + // Perform the callback! + if (lun->dataMonitor) { + + lun->dataMonitor(1, fifo->dataTotal, fifo->nullCnt, fifo->fullCnt); + } + return MSDD_STATUS_SUCCESS; + } + + // Disk reading task + switch(fifo->inputState) { + + //------------------ + case MSDIO_IDLE: + //------------------ + if (fifo->inputTotal < fifo->dataTotal && + fifo->inputTotal - fifo->outputTotal < fifo->bufferSize) { + + fifo->inputState = MSDIO_START; + } + break; + + //------------------ + case MSDIO_START: + //------------------ + // Read one block of data from the media + if (media->mappedRD) { + + // Directly write, no read needed + MSDDriver_Callback(disktransfer, MED_STATUS_SUCCESS, 0, 0); + status = LUN_STATUS_SUCCESS; + } + else { + #ifdef MSDIO_READ10_CHUNK_SIZE + status = SBC_READ_CHUNK(lun, DWORDB(command->pLogicalBlockAddress), + fifo, MSDDriver_Callback, disktransfer); + #else + status = LUN_Read(lun, + DWORDB(command->pLogicalBlockAddress), + &fifo->pBuffer[fifo->inputNdx], + 1, + (TransferCallback) MSDDriver_Callback, + (void *)disktransfer); + #endif + } + + // Check operation result code + if (status != LUN_STATUS_SUCCESS) { + + TRACE_WARNING("RBC_Read10: Failed to start reading\n\r"); + + if (SBCLunIsReady(lun)) { + + SBC_UpdateSenseData(&(lun->requestSenseData), + SBC_SENSE_KEY_NOT_READY, + SBC_ASC_LOGICAL_UNIT_NOT_READY, + 0); + } + + fifo->inputState = MSDIO_ERROR; + } + else { + + TRACE_INFO_WP("dRd "); + + // Move to next command state + fifo->inputState = MSDIO_WAIT; + } + break; // MSDIO_START + + //------------------ + case MSDIO_WAIT: + //------------------ + // Check semaphore value + if (disktransfer->semaphore > 0) { + + TRACE_INFO_WP("dOk "); + + // Take semaphore and move to next state + disktransfer->semaphore--; + fifo->inputState = MSDIO_NEXT; + } + break; + + //------------------ + case MSDIO_NEXT: + //------------------ + // Check the operation result code + if (disktransfer->status != USBD_STATUS_SUCCESS) { + + TRACE_WARNING( + "RBC_Read10: Failed to read media\n\r"); + SBC_UpdateSenseData(&(lun->requestSenseData), + SBC_SENSE_KEY_RECOVERED_ERROR, + SBC_ASC_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, + 0); + result = MSDD_STATUS_ERROR; + } + else { + + TRACE_INFO_WP("dNxt "); + + if (media->mappedRD) { + + // All data is ready + fifo->inputState = MSDIO_IDLE; + fifo->inputTotal = fifo->dataTotal; + } + else { + + // Update block address + #ifdef MSDIO_READ10_CHUNK_SIZE + STORE_DWORDB(DWORDB(command->pLogicalBlockAddress) + + fifo->chunkSize/fifo->blockSize, + command->pLogicalBlockAddress); + + // Update input index + MSDIOFifo_IncNdx(fifo->inputNdx, + fifo->chunkSize, + fifo->bufferSize); + fifo->inputTotal += fifo->chunkSize; + #else + // Update block address + STORE_DWORDB(DWORDB(command->pLogicalBlockAddress) + 1, + command->pLogicalBlockAddress); + + // Update input index + MSDIOFifo_IncNdx(fifo->inputNdx, + fifo->blockSize, + fifo->bufferSize); + fifo->inputTotal += fifo->blockSize; + #endif + + // Start Next block + // - All Data done? + if (fifo->inputTotal >= fifo->dataTotal) { + + TRACE_INFO_WP("dDone "); + fifo->inputState = MSDIO_IDLE; + } + // - Buffer full? + else if (fifo->inputNdx == fifo->outputNdx) { + + TRACE_INFO_WP("dfFull%d ", (int)fifo->inputNdx); + fifo->inputState = MSDIO_IDLE; + fifo->fullCnt ++; + } + // - More data to transfer? + else if (fifo->inputTotal < fifo->dataTotal) { + + TRACE_DEBUG_WP("dStart "); + fifo->inputState = MSDIO_START; + } + } + + } + + break; + + //------------------ + case MSDIO_ERROR: + //------------------ + break; + } + + // USB sending task + switch(fifo->outputState) { + + //------------------ + case MSDIO_IDLE: + //------------------ + if (fifo->outputTotal < fifo->inputTotal) { + + #ifdef MSDIO_FIFO_OFFSET + // Offset buffer the input data + if (fifo->bufferOffset) { + if (fifo->inputTotal < fifo->bufferOffset) { + break; + } + fifo->bufferOffset = 0; + } + #endif + fifo->outputState = MSDIO_START; + } + break; + + //------------------ + case MSDIO_START: + //------------------ + // Should not start if there is any disk error + if (fifo->outputState == MSDIO_ERROR) { + + fifo->inputState = MSDIO_ERROR; + break; + } + + // Send the block to the host + if (media->mappedRD) { + + status = MSDD_Write((void*) + ((media->baseAddress + + (lun->baseAddress + + DWORDB(command->pLogicalBlockAddress) + * lun->blockSize + ) + ) * media->blockSize + ), + commandState->length, + (TransferCallback) MSDDriver_Callback, + (void *) transfer); + } + else { + #ifdef MSDIO_READ10_CHUNK_SIZE + status = SBC_TX_CHUNK(fifo, MSDDriver_Callback, transfer); + #else + status = MSDD_Write(&fifo->pBuffer[fifo->outputNdx], + fifo->blockSize, + (TransferCallback) MSDDriver_Callback, + (void *) transfer); + #endif + } + // Check operation result code + if (status != USBD_STATUS_SUCCESS) { + + TRACE_WARNING( + "RBC_Read10: Failed to start to send\n\r"); + SBC_UpdateSenseData(&(lun->requestSenseData), + SBC_SENSE_KEY_HARDWARE_ERROR, + 0, + 0); + result = MSDD_STATUS_ERROR; + } + else { + + TRACE_INFO_WP("uTx "); + + // Move to next command state + fifo->outputState = MSDIO_WAIT; + } + break; // MSDIO_START + + //------------------ + case MSDIO_WAIT: + //------------------ + // Check semaphore value + if (transfer->semaphore > 0) { + + TRACE_INFO_WP("uOk "); + + // Take semaphore and move to next state + transfer->semaphore--; + fifo->outputState = MSDIO_NEXT; + } + break; + + //------------------ + case MSDIO_NEXT: + //------------------ + // Check operation result code + if (transfer->status != USBD_STATUS_SUCCESS) { + + TRACE_WARNING( + "RBC_Read10: Failed to send data\n\r"); + SBC_UpdateSenseData(&(lun->requestSenseData), + SBC_SENSE_KEY_HARDWARE_ERROR, + 0, + 0); + result = MSDD_STATUS_ERROR; + } + else { + + TRACE_INFO_WP("uNxt "); + + if (media->mappedRD) { + + commandState->length = 0; + } + else { + + // Update output index + #ifdef MSDIO_READ10_CHUNK_SIZE + MSDIOFifo_IncNdx(fifo->outputNdx, + fifo->chunkSize, + fifo->bufferSize); + fifo->outputTotal += fifo->chunkSize; + #else + MSDIOFifo_IncNdx(fifo->outputNdx, + fifo->blockSize, + fifo->bufferSize); + fifo->outputTotal += fifo->blockSize; + #endif + + // Start Next block + // - All data done? + if (fifo->outputTotal >= fifo->dataTotal) { + + fifo->outputState = MSDIO_IDLE; + commandState->length = 0; + TRACE_INFO_WP("uDone "); + } + // - Buffer Null? + else if (fifo->inputNdx == fifo->outputNdx) { + + TRACE_INFO_WP("ufNull%d ", (int)fifo->outputNdx); + fifo->outputState = MSDIO_IDLE; + fifo->nullCnt ++; + } + // - Send next? + else if (fifo->outputTotal < fifo->inputTotal) { + + TRACE_DEBUG_WP("uStart "); + fifo->outputState = MSDIO_START; + } + } + + } + break; + + //------------------ + case MSDIO_ERROR: + //------------------ + break; + } + + return result; +} + +//------------------------------------------------------------------------------ +//! \brief Performs a READ CAPACITY (10) command. +//! +//! This function operates asynchronously and must be called multiple +//! times to complete. A result code of MSDD_STATUS_INCOMPLETE +//! indicates that at least another call of the method is necessary. +//! \param lun Pointer to the LUN affected by the command +//! \param commandState Current state of the command +//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) +//! \see MSDLun +//! \see MSDCommandState +//------------------------------------------------------------------------------ +static unsigned char SBC_ReadCapacity10(MSDLun *lun, + MSDCommandState *commandState) +{ + unsigned char result = MSDD_STATUS_INCOMPLETE; + unsigned char status; + MSDTransfer *transfer = &(commandState->transfer); + + if (!SBCLunIsReady(lun)) { + + TRACE_INFO("SBC_ReadCapacity10: Not Ready!\n\r"); + return MSDD_STATUS_RW; + } + + // Initialize command state if needed + if (commandState->state == 0) { + + commandState->state = SBC_STATE_WRITE; + } + + // Identify current command state + switch (commandState->state) { + //------------------- + case SBC_STATE_WRITE: + //------------------- + // Start the write operation + status = MSDD_Write(&(lun->readCapacityData), + commandState->length, + (TransferCallback) MSDDriver_Callback, + (void *) transfer); + + // Check operation result code + if (status != USBD_STATUS_SUCCESS) { + + TRACE_WARNING( + "RBC_ReadCapacity: Cannot start sending data\n\r"); + result = MSDD_STATUS_ERROR; + } + else { + + // Proceed to next command state + TRACE_INFO_WP("Sending "); + commandState->state = SBC_STATE_WAIT_WRITE; + } + break; + + //------------------------ + case SBC_STATE_WAIT_WRITE: + //------------------------ + // Check semaphore value + if (transfer->semaphore > 0) { + + // Take semaphore and terminate command + transfer->semaphore--; + + if (transfer->status != USBD_STATUS_SUCCESS) { + + TRACE_WARNING("RBC_ReadCapacity: Cannot send data\n\r"); + result = MSDD_STATUS_ERROR; + } + else { + + TRACE_INFO_WP("Sent "); + result = MSDD_STATUS_SUCCESS; + } + commandState->length -= transfer->transferred; + } + break; + } + + return result; +} + +//------------------------------------------------------------------------------ +//! \brief Handles an INQUIRY command. +//! +//! This function operates asynchronously and must be called multiple +//! times to complete. A result code of MSDDriver_STATUS_INCOMPLETE +//! indicates that at least another call of the method is necessary. +//! \param lun Pointer to the LUN affected by the command +//! \param commandState Current state of the command +//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) +//! \see MSDLun +//! \see MSDCommandState +//------------------------------------------------------------------------------ +static unsigned char SBC_Inquiry(MSDLun *lun, + MSDCommandState *commandState) +{ + unsigned char result = MSDD_STATUS_INCOMPLETE; + unsigned char status; + MSDTransfer *transfer = &(commandState->transfer); + + // Check if required length is 0 + if (commandState->length == 0) { + + // Nothing to do + result = MSDD_STATUS_SUCCESS; + } + // Initialize command state if needed + else if (commandState->state == 0) { + + commandState->state = SBC_STATE_WRITE; + + // Change additional length field of inquiry data + lun->inquiryData->bAdditionalLength + = (unsigned char) (commandState->length - 5); + } + + // Identify current command state + switch (commandState->state) { + //------------------- + case SBC_STATE_WRITE: + //------------------- + // Start write operation + status = MSDD_Write((void *) lun->inquiryData, + commandState->length, + (TransferCallback) MSDDriver_Callback, + (void *) transfer); + + // Check operation result code + if (status != USBD_STATUS_SUCCESS) { + + TRACE_WARNING( + "SPC_Inquiry: Cannot start sending data\n\r"); + result = MSDD_STATUS_ERROR; + } + else { + + // Proceed to next state + TRACE_INFO_WP("Sending "); + commandState->state = SBC_STATE_WAIT_WRITE; + } + break; + + //------------------------ + case SBC_STATE_WAIT_WRITE: + //------------------------ + // Check the semaphore value + if (transfer->semaphore > 0) { + + // Take semaphore and terminate command + transfer->semaphore--; + + if (transfer->status != USBD_STATUS_SUCCESS) { + + TRACE_WARNING( + "SPC_Inquiry: Data transfer failed\n\r"); + result = MSDD_STATUS_ERROR; + } + else { + + TRACE_INFO_WP("Sent "); + result = MSDD_STATUS_SUCCESS; + } + + // Update length field + commandState->length -= transfer->transferred; + } + break; + } + + return result; +} + +//------------------------------------------------------------------------------ +//! \brief Performs a REQUEST SENSE command. +//! +//! This function operates asynchronously and must be called multiple +//! times to complete. A result code of MSDDriver_STATUS_INCOMPLETE +//! indicates that at least another call of the method is necessary. +//! \param lun Pointer to the LUN affected by the command +//! \param commandState Current state of the command +//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) +//! \see MSDLun +//! \see MSDCommandState +//------------------------------------------------------------------------------ +static unsigned char SBC_RequestSense(MSDLun *lun, + MSDCommandState *commandState) +{ + unsigned char result = MSDD_STATUS_INCOMPLETE; + unsigned char status; + MSDTransfer *transfer = &(commandState->transfer); + + // Check if requested length is zero + if (commandState->length == 0) { + + // Nothing to do + result = MSDD_STATUS_SUCCESS; + } + // Initialize command state if needed + else if (commandState->state == 0) { + + commandState->state = SBC_STATE_WRITE; + } + + // Identify current command state + switch (commandState->state) { + //------------------- + case SBC_STATE_WRITE: + //------------------- + // Start transfer + status = MSDD_Write(&(lun->requestSenseData), + commandState->length, + (TransferCallback) MSDDriver_Callback, + (void *) transfer); + + // Check result code + if (status != USBD_STATUS_SUCCESS) { + + TRACE_WARNING( + "RBC_RequestSense: Cannot start sending data\n\r"); + result = MSDD_STATUS_ERROR; + } + else { + + // Change state + commandState->state = SBC_STATE_WAIT_WRITE; + } + break; + + //------------------------ + case SBC_STATE_WAIT_WRITE: + //------------------------ + // Check the transfer semaphore + if (transfer->semaphore > 0) { + + // Take semaphore and finish command + transfer->semaphore--; + + if (transfer->status != USBD_STATUS_SUCCESS) { + + result = MSDD_STATUS_ERROR; + } + else { + + result = MSDD_STATUS_SUCCESS; + } + + // Update length + commandState->length -= transfer->transferred; + } + break; + } + + return result; +} + +//------------------------------------------------------------------------------ +//! \brief Performs a MODE SENSE (6) command. +//! +//! This function operates asynchronously and must be called multiple +//! times to complete. A result code of MSDDriver_STATUS_INCOMPLETE +//! indicates that at least another call of the method is necessary. +//! \param lun Pointer to the LUN affected by the command +//! \param commandState Current state of the command +//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) +//! \see MSDLun +//! \see MSDCommandState +//------------------------------------------------------------------------------ +static unsigned char SBC_ModeSense6(MSDLun *lun, MSDCommandState *commandState) +{ + unsigned char result = MSDD_STATUS_INCOMPLETE; + unsigned char status; + MSDTransfer *transfer = &(commandState->transfer); + + if (!SBCLunIsReady(lun)) { + + TRACE_INFO("SBC_ModeSense6: Not Ready!\n\r"); + return MSDD_STATUS_RW; + } + + // Check if mode page is supported + if (((SBCCommand *) commandState->cbw.pCommand)->modeSense6.bPageCode + != SBC_PAGE_RETURN_ALL) { + + return MSDD_STATUS_PARAMETER; + } + + // Initialize command state if needed + if (commandState->state == 0) { + + commandState->state = SBC_STATE_WRITE; + } + + // Check current command state + switch (commandState->state) { + //------------------- + case SBC_STATE_WRITE: + //------------------- + // Start transfer + status = MSDD_Write((void *) &modeParameterHeader6, + commandState->length, + (TransferCallback) MSDDriver_Callback, + (void *) transfer); + + // Check operation result code + if (status != USBD_STATUS_SUCCESS) { + + TRACE_WARNING( + "SPC_ModeSense6: Cannot start data transfer\n\r"); + result = MSDD_STATUS_ERROR; + } + else { + + // Proceed to next state + commandState->state = SBC_STATE_WAIT_WRITE; + } + break; + + //------------------------ + case SBC_STATE_WAIT_WRITE: + //------------------------ + TRACE_INFO_WP("Wait "); + + // Check semaphore value + if (transfer->semaphore > 0) { + + // Take semaphore and terminate command + transfer->semaphore--; + + if (transfer->status != USBD_STATUS_SUCCESS) { + + TRACE_WARNING( + "SPC_ModeSense6: Data transfer failed\n\r"); + result = MSDD_STATUS_ERROR; + } + else { + + result = MSDD_STATUS_SUCCESS; + } + + // Update length field + commandState->length -= transfer->transferred; + + } + break; + } + + return result; +} + +//------------------------------------------------------------------------------ +//! \brief Performs a TEST UNIT READY COMMAND command. +//! \param lun Pointer to the LUN affected by the command +//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) +//! \see MSDLun +//------------------------------------------------------------------------------ +static unsigned char SBC_TestUnitReady(MSDLun *lun) +{ + unsigned char result = MSDD_STATUS_RW; + unsigned char senseKey = SBC_SENSE_KEY_NO_SENSE, + addSenseCode = 0, + addSenseCodeQual = 0; + Media *media = lun->media; + + // Check current media state + if (lun->status < LUN_CHANGED) { + + TRACE_INFO_WP("Ejc "); + senseKey = SBC_SENSE_KEY_NOT_READY; + addSenseCode = SBC_ASC_MEDIUM_NOT_PRESENT; + } + else if (lun->status == LUN_CHANGED) { + + TRACE_INFO_WP("Chg "); + senseKey = SBC_SENSE_KEY_UNIT_ATTENTION; + addSenseCode = SBC_ASC_NOT_READY_TO_READY_CHANGE; + lun->status = LUN_READY; + } + else { + + switch(media->state) { + //------------------- + case MED_STATE_READY: + //------------------- + // Nothing to do + TRACE_INFO_WP("Rdy "); + result = MSDD_STATUS_SUCCESS; + break; + + //------------------ + case MED_STATE_BUSY: + //------------------ + TRACE_INFO_WP("Bsy "); + senseKey = SBC_SENSE_KEY_NOT_READY; + break; + + //------ + default: + //------ + TRACE_INFO_WP("? "); + senseKey = SBC_SENSE_KEY_NOT_READY; + addSenseCode = SBC_ASC_MEDIUM_NOT_PRESENT; + break; + } + } + SBC_UpdateSenseData(&(lun->requestSenseData), + senseKey, + addSenseCode, + addSenseCodeQual); + + return result; +} + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +//! \brief Updates the sense data of a LUN with the given key and codes +//! \param requestSenseData Pointer to the sense data to update +//! \param senseKey Sense key +//! \param additionalSenseCode Additional sense code +//! \param additionalSenseCodeQualifier Additional sense code qualifier +//------------------------------------------------------------------------------ +void SBC_UpdateSenseData(SBCRequestSenseData *requestSenseData, + unsigned char senseKey, + unsigned char additionalSenseCode, + unsigned char additionalSenseCodeQualifier) +{ + requestSenseData->bSenseKey = senseKey; + requestSenseData->bAdditionalSenseCode = additionalSenseCode; + requestSenseData->bAdditionalSenseCodeQualifier + = additionalSenseCodeQualifier; +} + +//------------------------------------------------------------------------------ +//! \brief Return information about the transfer length and direction expected +//! by the device for a particular command. +//! \param command Pointer to a buffer holding the command to evaluate +//! \param length Expected length of the data transfer +//! \param type Expected direction of data transfer +//! \param lun Pointer to the LUN affected by the command +//------------------------------------------------------------------------------ +unsigned char SBC_GetCommandInformation(void *command, + unsigned int *length, + unsigned char *type, + MSDLun *lun) +{ + SBCCommand *sbcCommand = (SBCCommand *) command; + unsigned char isCommandSupported = 1; + Media *media = lun->media; + + // Identify command + switch (sbcCommand->bOperationCode) { + //--------------- + case SBC_INQUIRY: + //--------------- + (*type) = MSDD_DEVICE_TO_HOST; + + // Allocation length is stored in big-endian format + (*length) = WORDB(sbcCommand->inquiry.pAllocationLength); + break; + + //-------------------- + case SBC_MODE_SENSE_6: + //-------------------- + (*type) = MSDD_DEVICE_TO_HOST; + if (sbcCommand->modeSense6.bAllocationLength > + sizeof(SBCModeParameterHeader6)) { + + *length = sizeof(SBCModeParameterHeader6); + } + else { + + *length = sbcCommand->modeSense6.bAllocationLength; + } + break; + + //------------------------------------ + case SBC_PREVENT_ALLOW_MEDIUM_REMOVAL: + case 0x1B: + //------------------------------------ + (*type) = MSDD_NO_TRANSFER; + break; + + //--------------------- + case SBC_REQUEST_SENSE: + //--------------------- + (*type) = MSDD_DEVICE_TO_HOST; + (*length) = sbcCommand->requestSense.bAllocationLength; + break; + + //----------------------- + case SBC_TEST_UNIT_READY: + //----------------------- + (*type) = MSDD_NO_TRANSFER; + break; + + //--------------------- + case SBC_READ_CAPACITY_10: + //--------------------- + (*type) = MSDD_DEVICE_TO_HOST; + (*length) = sizeof(SBCReadCapacity10Data); + break; + + //--------------- + case SBC_READ_10: + //--------------- + (*type) = MSDD_DEVICE_TO_HOST; + (*length) = WORDB(sbcCommand->read10.pTransferLength) + * lun->blockSize * media->blockSize; + break; + + //---------------- + case SBC_WRITE_10: + //---------------- + (*type) = MSDD_HOST_TO_DEVICE; + (*length) = WORDB(sbcCommand->write10.pTransferLength) + * lun->blockSize * media->blockSize; + break; + + //----------------- + case SBC_VERIFY_10: + //----------------- + (*type) = MSDD_NO_TRANSFER; + break; + #if 0 + //--------------------- + case SBC_READ_FORMAT_CAPACITIES: + //--------------------- + (*type) = MSDD_DEVICE_TO_HOST; + (*length) = 1; + break; + #endif + //------ + default: + //------ + isCommandSupported = 0; + } + + // If length is 0, no transfer is expected + if ((*length) == 0) { + + (*type) = MSDD_NO_TRANSFER; + } + + return isCommandSupported; +} + +//------------------------------------------------------------------------------ +//! \brief Processes a SBC command by dispatching it to a subfunction. +//! \param lun Pointer to the affected LUN +//! \param commandState Pointer to the current command state +//! \return Operation result code +//------------------------------------------------------------------------------ +unsigned char SBC_ProcessCommand(MSDLun *lun, + MSDCommandState *commandState) +{ + unsigned char result = MSDD_STATUS_INCOMPLETE; + SBCCommand *command = (SBCCommand *) commandState->cbw.pCommand; + Media *media = lun->media; + + // Identify command + switch (command->bOperationCode) { + //--------------- + case SBC_READ_10: + //--------------- + TRACE_DEBUG_WP("Read(10) "); + + // Perform the Read10 command + result = SBC_Read10(lun, commandState); + break; + + //---------------- + case SBC_WRITE_10: + //---------------- + TRACE_DEBUG_WP("Write(10) "); + + // Perform the Write10 command + result = SBC_Write10(lun, commandState); + break; + + //--------------------- + case SBC_READ_CAPACITY_10: + //--------------------- + TRACE_INFO_WP("RdCapacity(10) "); + + // Perform the ReadCapacity command + result = SBC_ReadCapacity10(lun, commandState); + break; + + //--------------------- + case SBC_VERIFY_10: + //--------------------- + TRACE_INFO_WP("Verify(10) "); + + // Flush media + MED_Flush(media); + result = MSDD_STATUS_SUCCESS; + break; + + //--------------- + case SBC_INQUIRY: + //--------------- + TRACE_INFO_WP("Inquiry "); + + // Process Inquiry command + result = SBC_Inquiry(lun, commandState); + break; + + //-------------------- + case SBC_MODE_SENSE_6: + //-------------------- + TRACE_INFO_WP("ModeSense(6) "); + + // Process ModeSense6 command + result = SBC_ModeSense6(lun, commandState); + break; + + //----------------------- + case SBC_TEST_UNIT_READY: + //----------------------- + TRACE_INFO_WP("TstUnitRdy "); + + // Process TestUnitReady command + //MED_Flush(media); + result = SBC_TestUnitReady(lun); + break; + + //--------------------- + case SBC_REQUEST_SENSE: + //--------------------- + TRACE_INFO_WP("ReqSense "); + + // Perform the RequestSense command + result = SBC_RequestSense(lun, commandState); + break; + + //------------------------------------ + case SBC_PREVENT_ALLOW_MEDIUM_REMOVAL: + case 0x1B: + //------------------------------------ + TRACE_INFO_WP("PrevAllowRem "); + + // Check parameter + result = command->mediumRemoval.bPrevent ? + MSDD_STATUS_PARAMETER : MSDD_STATUS_SUCCESS; + result = MSDD_STATUS_SUCCESS; + break; + + #if 0 + //------------------------------------ + case SBC_READ_FORMAT_CAPACITIES: + //------------------------------------ + TRACE_INFO_WP("RdFmtCap "); + result = MSDD_STATUS_RW; + break; + /* TODO BSS Added if (!SBCLunIsReady(lun)) { + + result = MSDD_STATUS_RW; + break; + } */ + #endif + //------ + default: + //------ + result = MSDD_STATUS_PARAMETER; + } + + return result; +} diff --git a/radio/bootloader/usb/device/massstorage/SBCMethods.h b/radio/bootloader/usb/device/massstorage/SBCMethods.h new file mode 100644 index 000000000..7ba794e67 --- /dev/null +++ b/radio/bootloader/usb/device/massstorage/SBCMethods.h @@ -0,0 +1,111 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// !Purpose +/// +/// SCSI commands implementation. +/// +/// !Usage +/// +/// -# After a CBW is received from host, use SBC_GetCommandInformation to check +/// if the command is supported, and get the command length and type +/// information before processing it. +/// -# Then SBC_ProcessCommand can be used to handle a valid command, to +/// perform the command operations. +/// -# SBC_UpdateSenseData is used to update the sense data that will be sent +/// to host. +//------------------------------------------------------------------------------ + +#ifndef SBCMETHODS_H +#define SBCMETHODS_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "SBC.h" +// #include +#include "MSDDStateMachine.h" + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SBC Command States" +/// This page lists the possible states of a SBC command. +/// +/// !States +/// - SBC_STATE_READ +/// - SBC_STATE_WAIT_READ +/// - SBC_STATE_WRITE +/// - SBC_STATE_WAIT_WRITE +/// - SBC_STATE_NEXT_BLOCK + +/// Start of reading bulk data +#define SBC_STATE_READ 0x01 +/// Waiting for the bulk data reading complete +#define SBC_STATE_WAIT_READ 0x02 +/// Read error state +#define SBC_STATE_READ_ERROR 0x03 +/// Start next read block +#define SBC_STATE_NEXT_READ 0x04 +/// Start writing bulk data to host +#define SBC_STATE_WRITE 0x05 +/// Waiting for the bulk data sending complete +#define SBC_STATE_WAIT_WRITE 0x06 +/// Write error state +#define SBC_STATE_WRITE_ERROR 0x07 +/// Start next write block +#define SBC_STATE_NEXT_WRITE 0x08 +/// Start next command block +#define SBC_STATE_NEXT_BLOCK 0x09 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +void SBC_UpdateSenseData(SBCRequestSenseData *requestSenseData, + unsigned char senseKey, + unsigned char additionalSenseCode, + unsigned char additionalSenseCodeQualifier); + +unsigned char SBC_GetCommandInformation(void *command, + unsigned int *length, + unsigned char *type, + MSDLun *lun); + +unsigned char SBC_ProcessCommand(MSDLun *lun, + MSDCommandState *commandState); + +#endif //#ifndef SBCMETHODS_H + diff --git a/radio/bootloader/usb/usb_bsp.c b/radio/bootloader/usb/usb_bsp.c new file mode 100644 index 000000000..bd43c8a0f --- /dev/null +++ b/radio/bootloader/usb/usb_bsp.c @@ -0,0 +1,135 @@ +/** + ****************************************************************************** + * @file usb_bsp.c + * @author MCD Application Team + * @version V1.1.0 + * @date 19-March-2012 + * @brief This file is responsible to offer board support package and is + * configurable by user. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_gpio.h" +#include "misc.h" +#include "usb_bsp.h" +#include "usbd_conf.h" + +extern uint32_t SystemCoreClock; + +/** +* @brief USB_OTG_BSP_Init +* Initilizes BSP configurations +* @param None +* @retval None +*/ + +void USB_OTG_BSP_Init(USB_OTG_CORE_HANDLE *pdev) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + RCC_AHB1PeriphClockCmd( RCC_AHB1Periph_GPIOA , ENABLE); + + /* Configure SOF ID DM DP Pins */ + GPIO_InitStructure.GPIO_Pin = // GPIO_Pin_8 | + GPIO_Pin_11 | + GPIO_Pin_12; + + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + //GPIO_PinAFConfig(GPIOA,GPIO_PinSource8,GPIO_AF_OTG1_FS) ; + GPIO_PinAFConfig(GPIOA,GPIO_PinSource11,GPIO_AF_OTG1_FS) ; + GPIO_PinAFConfig(GPIOA,GPIO_PinSource12,GPIO_AF_OTG1_FS) ; + + /* Configure VBUS Pin */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ; + GPIO_Init(GPIOA, &GPIO_InitStructure); + +/* // Configure ID pin + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; + GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_PinAFConfig(GPIOA,GPIO_PinSource10,GPIO_AF_OTG1_FS) ; +*/ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); + RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_OTG_FS, ENABLE) ; +} +/** +* @brief USB_OTG_BSP_EnableInterrupt +* Enabele USB Global interrupt +* @param None +* @retval None +*/ +void USB_OTG_BSP_EnableInterrupt(USB_OTG_CORE_HANDLE *pdev) +{ + NVIC_InitTypeDef NVIC_InitStructure; + + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1); + NVIC_InitStructure.NVIC_IRQChannel = OTG_FS_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); +} +/** +* @brief USB_OTG_BSP_uDelay +* This function provides delay time in micro sec +* @param usec : Value of delay required in micro sec +* @retval None +*/ +void USB_OTG_BSP_uDelay (const uint32_t usec) +{ + uint32_t count = 0; + const uint32_t utime = ((SystemCoreClock/1000000) * usec); + do + { + if ( ++count > utime ) + { + return ; + } + } + while (1); +} + + +/** +* @brief USB_OTG_BSP_mDelay +* This function provides delay time in milli sec +* @param msec : Value of delay required in milli sec +* @retval None +*/ +void USB_OTG_BSP_mDelay (const uint32_t msec) +{ + USB_OTG_BSP_uDelay(msec * 1000); +} + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/usb/usb_core.c b/radio/bootloader/usb/usb_core.c new file mode 100644 index 000000000..12a207d81 --- /dev/null +++ b/radio/bootloader/usb/usb_core.c @@ -0,0 +1,2162 @@ +/** + ****************************************************************************** + * @file usb_core.c + * @author MCD Application Team + * @version V2.1.0 + * @date 19-March-2012 + * @brief USB-OTG Core Layer + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usb_core.h" +#include "usb_bsp.h" + + +/** @addtogroup USB_OTG_DRIVER +* @{ +*/ + +/** @defgroup USB_CORE +* @brief This file includes the USB-OTG Core Layer +* @{ +*/ + + +/** @defgroup USB_CORE_Private_Defines +* @{ +*/ + +/** +* @} +*/ + + +/** @defgroup USB_CORE_Private_TypesDefinitions +* @{ +*/ +/** +* @} +*/ + + + +/** @defgroup USB_CORE_Private_Macros +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USB_CORE_Private_Variables +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USB_CORE_Private_FunctionPrototypes +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USB_CORE_Private_Functions +* @{ +*/ + +/** +* @brief USB_OTG_EnableCommonInt +* Initializes the commmon interrupts, used in both device and modes +* @param pdev : Selected device +* @retval None +*/ +static void USB_OTG_EnableCommonInt(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_GINTMSK_TypeDef int_mask; + + int_mask.d32 = 0; + /* Clear any pending USB_OTG Interrupts */ +#ifndef USE_OTG_MODE + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GOTGINT, 0xFFFFFFFF); +#endif + /* Clear any pending interrupts */ + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, 0xBFFFFFFF); + /* Enable the interrupts in the INTMSK */ + int_mask.b.wkupintr = 1; + int_mask.b.usbsuspend = 1; + +#ifdef USE_OTG_MODE + int_mask.b.otgintr = 1; + int_mask.b.sessreqintr = 1; + int_mask.b.conidstschng = 1; +#endif + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTMSK, int_mask.d32); +} + +/** +* @brief USB_OTG_CoreReset : Soft reset of the core +* @param pdev : Selected device +* @retval USB_OTG_STS : status +*/ +static USB_OTG_STS USB_OTG_CoreReset(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_STS status = USB_OTG_OK; + __IO USB_OTG_GRSTCTL_TypeDef greset; + uint32_t count = 0; + + greset.d32 = 0; + /* Wait for AHB master IDLE state. */ + do + { + USB_OTG_BSP_uDelay(3); + greset.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRSTCTL); + if (++count > 200000) + { + return USB_OTG_OK; + } + } + while (greset.b.ahbidle == 0); + /* Core Soft Reset */ + count = 0; + greset.b.csftrst = 1; + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRSTCTL, greset.d32 ); + do + { + greset.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRSTCTL); + if (++count > 200000) + { + break; + } + } + while (greset.b.csftrst == 1); + /* Wait for 3 PHY Clocks*/ + USB_OTG_BSP_uDelay(3); + return status; +} + +/** +* @brief USB_OTG_WritePacket : Writes a packet into the Tx FIFO associated +* with the EP +* @param pdev : Selected device +* @param src : source pointer +* @param ch_ep_num : end point number +* @param bytes : No. of bytes +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_WritePacket(USB_OTG_CORE_HANDLE *pdev, + uint8_t *src, + uint8_t ch_ep_num, + uint16_t len) +{ + USB_OTG_STS status = USB_OTG_OK; + if (pdev->cfg.dma_enable == 0) + { + uint32_t count32b= 0 , i= 0; + __IO uint32_t *fifo; + + count32b = (len + 3) / 4; + fifo = pdev->regs.DFIFO[ch_ep_num]; + for (i = 0; i < count32b; i++, src+=4) + { + USB_OTG_WRITE_REG32( fifo, *((__packed uint32_t *)src) ); + } + } + return status; +} + + +/** +* @brief USB_OTG_ReadPacket : Reads a packet from the Rx FIFO +* @param pdev : Selected device +* @param dest : Destination Pointer +* @param bytes : No. of bytes +* @retval None +*/ +void *USB_OTG_ReadPacket(USB_OTG_CORE_HANDLE *pdev, + uint8_t *dest, + uint16_t len) +{ + uint32_t i=0; + uint32_t count32b = (len + 3) / 4; + + __IO uint32_t *fifo = pdev->regs.DFIFO[0]; + + for ( i = 0; i < count32b; i++, dest += 4 ) + { + *(__packed uint32_t *)dest = USB_OTG_READ_REG32(fifo); + + } + return ((void *)dest); +} + +/** +* @brief USB_OTG_SelectCore +* Initialize core registers address. +* @param pdev : Selected device +* @param coreID : USB OTG Core ID +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_SelectCore(USB_OTG_CORE_HANDLE *pdev, + USB_OTG_CORE_ID_TypeDef coreID) +{ + uint32_t i , baseAddress = 0; + USB_OTG_STS status = USB_OTG_OK; + + pdev->cfg.dma_enable = 0; + + /* at startup the core is in FS mode */ + pdev->cfg.speed = USB_OTG_SPEED_FULL; + pdev->cfg.mps = USB_OTG_FS_MAX_PACKET_SIZE ; + + /* initialize device cfg following its address */ + if (coreID == USB_OTG_FS_CORE_ID) + { + baseAddress = USB_OTG_FS_BASE_ADDR; + pdev->cfg.coreID = USB_OTG_FS_CORE_ID; + pdev->cfg.host_channels = 8 ; + pdev->cfg.dev_endpoints = 4 ; + pdev->cfg.TotalFifoSize = 320; /* in 32-bits */ + pdev->cfg.phy_itface = USB_OTG_EMBEDDED_PHY; + +#ifdef USB_OTG_FS_SOF_OUTPUT_ENABLED + pdev->cfg.Sof_output = 1; +#endif + +#ifdef USB_OTG_FS_LOW_PWR_MGMT_SUPPORT + pdev->cfg.low_power = 1; +#endif + } + else if (coreID == USB_OTG_HS_CORE_ID) + { + baseAddress = USB_OTG_HS_BASE_ADDR; + pdev->cfg.coreID = USB_OTG_HS_CORE_ID; + pdev->cfg.host_channels = 12 ; + pdev->cfg.dev_endpoints = 6 ; + pdev->cfg.TotalFifoSize = 1280;/* in 32-bits */ + +#ifdef USB_OTG_ULPI_PHY_ENABLED + pdev->cfg.phy_itface = USB_OTG_ULPI_PHY; +#else +#ifdef USB_OTG_EMBEDDED_PHY_ENABLED + pdev->cfg.phy_itface = USB_OTG_EMBEDDED_PHY; +#endif +#endif + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + pdev->cfg.dma_enable = 1; +#endif + +#ifdef USB_OTG_HS_SOF_OUTPUT_ENABLED + pdev->cfg.Sof_output = 1; +#endif + +#ifdef USB_OTG_HS_LOW_PWR_MGMT_SUPPORT + pdev->cfg.low_power = 1; +#endif + + } + + pdev->regs.GREGS = (USB_OTG_GREGS *)(baseAddress + \ + USB_OTG_CORE_GLOBAL_REGS_OFFSET); + pdev->regs.DREGS = (USB_OTG_DREGS *) (baseAddress + \ + USB_OTG_DEV_GLOBAL_REG_OFFSET); + + for (i = 0; i < pdev->cfg.dev_endpoints; i++) + { + pdev->regs.INEP_REGS[i] = (USB_OTG_INEPREGS *) \ + (baseAddress + USB_OTG_DEV_IN_EP_REG_OFFSET + \ + (i * USB_OTG_EP_REG_OFFSET)); + pdev->regs.OUTEP_REGS[i] = (USB_OTG_OUTEPREGS *) \ + (baseAddress + USB_OTG_DEV_OUT_EP_REG_OFFSET + \ + (i * USB_OTG_EP_REG_OFFSET)); + } + pdev->regs.HREGS = (USB_OTG_HREGS *)(baseAddress + \ + USB_OTG_HOST_GLOBAL_REG_OFFSET); + pdev->regs.HPRT0 = (uint32_t *)(baseAddress + USB_OTG_HOST_PORT_REGS_OFFSET); + + for (i = 0; i < pdev->cfg.host_channels; i++) + { + pdev->regs.HC_REGS[i] = (USB_OTG_HC_REGS *)(baseAddress + \ + USB_OTG_HOST_CHAN_REGS_OFFSET + \ + (i * USB_OTG_CHAN_REGS_OFFSET)); + } + for (i = 0; i < pdev->cfg.host_channels; i++) + { + pdev->regs.DFIFO[i] = (uint32_t *)(baseAddress + USB_OTG_DATA_FIFO_OFFSET +\ + (i * USB_OTG_DATA_FIFO_SIZE)); + } + pdev->regs.PCGCCTL = (uint32_t *)(baseAddress + USB_OTG_PCGCCTL_OFFSET); + + return status; +} + + +/** +* @brief USB_OTG_CoreInit +* Initializes the USB_OTG controller registers and prepares the core +* device mode or host mode operation. +* @param pdev : Selected device +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_CoreInit(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_GUSBCFG_TypeDef usbcfg; + USB_OTG_GCCFG_TypeDef gccfg; + USB_OTG_GAHBCFG_TypeDef ahbcfg; + + usbcfg.d32 = 0; + gccfg.d32 = 0; + ahbcfg.d32 = 0; + + + + if (pdev->cfg.phy_itface == USB_OTG_ULPI_PHY) + { + gccfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GCCFG); + gccfg.b.pwdn = 0; + + if (pdev->cfg.Sof_output) + { + gccfg.b.sofouten = 1; + } + USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GCCFG, gccfg.d32); + + /* Init The ULPI Interface */ + usbcfg.d32 = 0; + usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); + + usbcfg.b.physel = 0; /* HS Interface */ +#ifdef USB_OTG_INTERNAL_VBUS_ENABLED + usbcfg.b.ulpi_ext_vbus_drv = 0; /* Use internal VBUS */ +#else +#ifdef USB_OTG_EXTERNAL_VBUS_ENABLED + usbcfg.b.ulpi_ext_vbus_drv = 1; /* Use external VBUS */ +#endif +#endif + usbcfg.b.term_sel_dl_pulse = 0; /* Data line pulsing using utmi_txvalid */ + + usbcfg.b.ulpi_fsls = 0; + usbcfg.b.ulpi_clk_sus_m = 0; + USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); + + /* Reset after a PHY select */ + USB_OTG_CoreReset(pdev); + + if(pdev->cfg.dma_enable == 1) + { + + ahbcfg.b.hburstlen = 5; /* 64 x 32-bits*/ + ahbcfg.b.dmaenable = 1; + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32); + + } + } + else /* FS interface (embedded Phy) */ + { + + usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);; + usbcfg.b.physel = 1; /* FS Interface */ + USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); + /* Reset after a PHY select and set Host mode */ + USB_OTG_CoreReset(pdev); + /* Deactivate the power down*/ + gccfg.d32 = 0; + gccfg.b.pwdn = 1; + + gccfg.b.vbussensingA = 1 ; + gccfg.b.vbussensingB = 1 ; +#ifndef VBUS_SENSING_ENABLED + gccfg.b.disablevbussensing = 1; +#endif + + if(pdev->cfg.Sof_output) + { + gccfg.b.sofouten = 1; + } + + USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GCCFG, gccfg.d32); + USB_OTG_BSP_mDelay(20); + } + /* case the HS core is working in FS mode */ + if(pdev->cfg.dma_enable == 1) + { + + ahbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GAHBCFG); + ahbcfg.b.hburstlen = 5; /* 64 x 32-bits*/ + ahbcfg.b.dmaenable = 1; + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32); + + } + /* initialize OTG features */ +#ifdef USE_OTG_MODE + usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); + usbcfg.b.hnpcap = 1; + usbcfg.b.srpcap = 1; + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); + USB_OTG_EnableCommonInt(pdev); +#endif + return status; +} +/** +* @brief USB_OTG_EnableGlobalInt +* Enables the controller's Global Int in the AHB Config reg +* @param pdev : Selected device +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_EnableGlobalInt(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_GAHBCFG_TypeDef ahbcfg; + + ahbcfg.d32 = 0; + ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ + USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GAHBCFG, 0, ahbcfg.d32); + return status; +} + + +/** +* @brief USB_OTG_DisableGlobalInt +* Enables the controller's Global Int in the AHB Config reg +* @param pdev : Selected device +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_DisableGlobalInt(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_GAHBCFG_TypeDef ahbcfg; + ahbcfg.d32 = 0; + ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ + USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32, 0); + return status; +} + + +/** +* @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO +* @param pdev : Selected device +* @param num : FO num +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_FlushTxFifo (USB_OTG_CORE_HANDLE *pdev , uint32_t num ) +{ + USB_OTG_STS status = USB_OTG_OK; + __IO USB_OTG_GRSTCTL_TypeDef greset; + + uint32_t count = 0; + greset.d32 = 0; + greset.b.txfflsh = 1; + greset.b.txfnum = num; + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GRSTCTL, greset.d32 ); + do + { + greset.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRSTCTL); + if (++count > 200000) + { + break; + } + } + while (greset.b.txfflsh == 1); + /* Wait for 3 PHY Clocks*/ + USB_OTG_BSP_uDelay(3); + return status; +} + + +/** +* @brief USB_OTG_FlushRxFifo : Flush a Rx FIFO +* @param pdev : Selected device +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_FlushRxFifo( USB_OTG_CORE_HANDLE *pdev ) +{ + USB_OTG_STS status = USB_OTG_OK; + __IO USB_OTG_GRSTCTL_TypeDef greset; + uint32_t count = 0; + + greset.d32 = 0; + greset.b.rxfflsh = 1; + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GRSTCTL, greset.d32 ); + do + { + greset.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRSTCTL); + if (++count > 200000) + { + break; + } + } + while (greset.b.rxfflsh == 1); + /* Wait for 3 PHY Clocks*/ + USB_OTG_BSP_uDelay(3); + return status; +} + + +/** +* @brief USB_OTG_SetCurrentMode : Set ID line +* @param pdev : Selected device +* @param mode : (Host/device) +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_SetCurrentMode(USB_OTG_CORE_HANDLE *pdev , uint8_t mode) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_GUSBCFG_TypeDef usbcfg; + + usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); + + usbcfg.b.force_host = 0; + usbcfg.b.force_dev = 0; + + if ( mode == HOST_MODE) + { + usbcfg.b.force_host = 1; + } + else if ( mode == DEVICE_MODE) + { + usbcfg.b.force_dev = 1; + } + + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); + USB_OTG_BSP_mDelay(50); + return status; +} + + +/** +* @brief USB_OTG_GetMode : Get current mode +* @param pdev : Selected device +* @retval current mode +*/ +uint32_t USB_OTG_GetMode(USB_OTG_CORE_HANDLE *pdev) +{ + return (USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS ) & 0x1); +} + + +/** +* @brief USB_OTG_IsDeviceMode : Check if it is device mode +* @param pdev : Selected device +* @retval num_in_ep +*/ +uint8_t USB_OTG_IsDeviceMode(USB_OTG_CORE_HANDLE *pdev) +{ + return (USB_OTG_GetMode(pdev) != HOST_MODE); +} + + +/** +* @brief USB_OTG_IsHostMode : Check if it is host mode +* @param pdev : Selected device +* @retval num_in_ep +*/ +uint8_t USB_OTG_IsHostMode(USB_OTG_CORE_HANDLE *pdev) +{ + return (USB_OTG_GetMode(pdev) == HOST_MODE); +} + + +/** +* @brief USB_OTG_ReadCoreItr : returns the Core Interrupt register +* @param pdev : Selected device +* @retval Status +*/ +uint32_t USB_OTG_ReadCoreItr(USB_OTG_CORE_HANDLE *pdev) +{ + uint32_t v = 0; + v = USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS); + v &= USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTMSK); + return v; +} + + +/** +* @brief USB_OTG_ReadOtgItr : returns the USB_OTG Interrupt register +* @param pdev : Selected device +* @retval Status +*/ +uint32_t USB_OTG_ReadOtgItr (USB_OTG_CORE_HANDLE *pdev) +{ + return (USB_OTG_READ_REG32 (&pdev->regs.GREGS->GOTGINT)); +} + +#ifdef USE_HOST_MODE +/** +* @brief USB_OTG_CoreInitHost : Initializes USB_OTG controller for host mode +* @param pdev : Selected device +* @retval status +*/ +USB_OTG_STS USB_OTG_CoreInitHost(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_FSIZ_TypeDef nptxfifosize; + USB_OTG_FSIZ_TypeDef ptxfifosize; + USB_OTG_HCFG_TypeDef hcfg; + +#ifdef USE_OTG_MODE + USB_OTG_OTGCTL_TypeDef gotgctl; +#endif + + uint32_t i = 0; + + nptxfifosize.d32 = 0; + ptxfifosize.d32 = 0; +#ifdef USE_OTG_MODE + gotgctl.d32 = 0; +#endif + hcfg.d32 = 0; + + + /* configure charge pump IO */ + USB_OTG_BSP_ConfigVBUS(pdev); + + /* Restart the Phy Clock */ + USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0); + + /* Initialize Host Configuration Register */ + if (pdev->cfg.phy_itface == USB_OTG_ULPI_PHY) + { + USB_OTG_InitFSLSPClkSel(pdev , HCFG_30_60_MHZ); + } + else + { + USB_OTG_InitFSLSPClkSel(pdev , HCFG_48_MHZ); + } + USB_OTG_ResetPort(pdev); + + hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG); + hcfg.b.fslssupp = 0; + USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HCFG, hcfg.d32); + + /* Configure data FIFO sizes */ + /* Rx FIFO */ +#ifdef USB_OTG_FS_CORE + if(pdev->cfg.coreID == USB_OTG_FS_CORE_ID) + { + /* set Rx FIFO size */ + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_FS_SIZE); + nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE; + nptxfifosize.b.depth = TXH_NP_FS_FIFOSIZ; + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32); + + ptxfifosize.b.startaddr = RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ; + ptxfifosize.b.depth = TXH_P_FS_FIFOSIZ; + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32); + } +#endif +#ifdef USB_OTG_HS_CORE + if (pdev->cfg.coreID == USB_OTG_HS_CORE_ID) + { + /* set Rx FIFO size */ + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_HS_SIZE); + nptxfifosize.b.startaddr = RX_FIFO_HS_SIZE; + nptxfifosize.b.depth = TXH_NP_HS_FIFOSIZ; + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32); + + ptxfifosize.b.startaddr = RX_FIFO_HS_SIZE + TXH_NP_HS_FIFOSIZ; + ptxfifosize.b.depth = TXH_P_HS_FIFOSIZ; + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32); + } +#endif + +#ifdef USE_OTG_MODE + /* Clear Host Set HNP Enable in the USB_OTG Control Register */ + gotgctl.b.hstsethnpen = 1; + USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GOTGCTL, gotgctl.d32, 0); +#endif + + /* Make sure the FIFOs are flushed. */ + USB_OTG_FlushTxFifo(pdev, 0x10 ); /* all Tx FIFOs */ + USB_OTG_FlushRxFifo(pdev); + + + /* Clear all pending HC Interrupts */ + for (i = 0; i < pdev->cfg.host_channels; i++) + { + USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCINT, 0xFFFFFFFF ); + USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCINTMSK, 0 ); + } +#ifndef USE_OTG_MODE + USB_OTG_DriveVbus(pdev, 1); +#endif + + USB_OTG_EnableHostInt(pdev); + return status; +} + +/** +* @brief USB_OTG_IsEvenFrame +* This function returns the frame number for sof packet +* @param pdev : Selected device +* @retval Frame number +*/ +uint8_t USB_OTG_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev) +{ + return !(USB_OTG_READ_REG32(&pdev->regs.HREGS->HFNUM) & 0x1); +} + +/** +* @brief USB_OTG_DriveVbus : set/reset vbus +* @param pdev : Selected device +* @param state : VBUS state +* @retval None +*/ +void USB_OTG_DriveVbus (USB_OTG_CORE_HANDLE *pdev, uint8_t state) +{ + USB_OTG_HPRT0_TypeDef hprt0; + + hprt0.d32 = 0; + + /* enable disable the external charge pump */ + USB_OTG_BSP_DriveVBUS(pdev, state); + + /* Turn on the Host port power. */ + hprt0.d32 = USB_OTG_ReadHPRT0(pdev); + if ((hprt0.b.prtpwr == 0 ) && (state == 1 )) + { + hprt0.b.prtpwr = 1; + USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); + } + if ((hprt0.b.prtpwr == 1 ) && (state == 0 )) + { + hprt0.b.prtpwr = 0; + USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); + } + + USB_OTG_BSP_mDelay(200); +} +/** +* @brief USB_OTG_EnableHostInt: Enables the Host mode interrupts +* @param pdev : Selected device +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_EnableHostInt(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_GINTMSK_TypeDef intmsk; + intmsk.d32 = 0; + /* Disable all interrupts. */ + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTMSK, 0); + + /* Clear any pending interrupts. */ + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, 0xFFFFFFFF); + + /* Enable the common interrupts */ + USB_OTG_EnableCommonInt(pdev); + + if (pdev->cfg.dma_enable == 0) + { + intmsk.b.rxstsqlvl = 1; + } + intmsk.b.portintr = 1; + intmsk.b.hcintr = 1; + intmsk.b.disconnect = 1; + intmsk.b.sofintr = 1; + intmsk.b.incomplisoout = 1; + USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, intmsk.d32, intmsk.d32); + return status; +} + +/** +* @brief USB_OTG_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the +* HCFG register on the PHY type +* @param pdev : Selected device +* @param freq : clock frequency +* @retval None +*/ +void USB_OTG_InitFSLSPClkSel(USB_OTG_CORE_HANDLE *pdev , uint8_t freq) +{ + USB_OTG_HCFG_TypeDef hcfg; + + hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG); + hcfg.b.fslspclksel = freq; + USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HCFG, hcfg.d32); +} + + +/** +* @brief USB_OTG_ReadHPRT0 : Reads HPRT0 to modify later +* @param pdev : Selected device +* @retval HPRT0 value +*/ +uint32_t USB_OTG_ReadHPRT0(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_HPRT0_TypeDef hprt0; + + hprt0.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0); + hprt0.b.prtena = 0; + hprt0.b.prtconndet = 0; + hprt0.b.prtenchng = 0; + hprt0.b.prtovrcurrchng = 0; + return hprt0.d32; +} + + +/** +* @brief USB_OTG_ReadHostAllChannels_intr : Register PCD Callbacks +* @param pdev : Selected device +* @retval Status +*/ +uint32_t USB_OTG_ReadHostAllChannels_intr (USB_OTG_CORE_HANDLE *pdev) +{ + return (USB_OTG_READ_REG32 (&pdev->regs.HREGS->HAINT)); +} + + +/** +* @brief USB_OTG_ResetPort : Reset Host Port +* @param pdev : Selected device +* @retval status +* @note : (1)The application must wait at least 10 ms (+ 10 ms security) +* before clearing the reset bit. +*/ +uint32_t USB_OTG_ResetPort(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_HPRT0_TypeDef hprt0; + + hprt0.d32 = USB_OTG_ReadHPRT0(pdev); + hprt0.b.prtrst = 1; + USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); + USB_OTG_BSP_mDelay (10); /* See Note #1 */ + hprt0.b.prtrst = 0; + USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); + USB_OTG_BSP_mDelay (20); + return 1; +} + + +/** +* @brief USB_OTG_HC_Init : Prepares a host channel for transferring packets +* @param pdev : Selected device +* @param hc_num : channel number +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_HC_Init(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) +{ + USB_OTG_STS status = USB_OTG_OK; + uint32_t intr_enable = 0; + USB_OTG_HCINTMSK_TypeDef hcintmsk; + USB_OTG_GINTMSK_TypeDef gintmsk; + USB_OTG_HCCHAR_TypeDef hcchar; + USB_OTG_HCINTn_TypeDef hcint; + + + gintmsk.d32 = 0; + hcintmsk.d32 = 0; + hcchar.d32 = 0; + + /* Clear old interrupt conditions for this host channel. */ + hcint.d32 = 0xFFFFFFFF; + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINT, hcint.d32); + + /* Enable channel interrupts required for this transfer. */ + hcintmsk.d32 = 0; + + if (pdev->cfg.dma_enable == 1) + { + hcintmsk.b.ahberr = 1; + } + + switch (pdev->host.hc[hc_num].ep_type) + { + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + hcintmsk.b.xfercompl = 1; + hcintmsk.b.stall = 1; + hcintmsk.b.xacterr = 1; + hcintmsk.b.datatglerr = 1; + hcintmsk.b.nak = 1; + if (pdev->host.hc[hc_num].ep_is_in) + { + hcintmsk.b.bblerr = 1; + } + else + { + hcintmsk.b.nyet = 1; + if (pdev->host.hc[hc_num].do_ping) + { + hcintmsk.b.ack = 1; + } + } + break; + case EP_TYPE_INTR: + hcintmsk.b.xfercompl = 1; + hcintmsk.b.nak = 1; + hcintmsk.b.stall = 1; + hcintmsk.b.xacterr = 1; + hcintmsk.b.datatglerr = 1; + hcintmsk.b.frmovrun = 1; + + if (pdev->host.hc[hc_num].ep_is_in) + { + hcintmsk.b.bblerr = 1; + } + + break; + case EP_TYPE_ISOC: + hcintmsk.b.xfercompl = 1; + hcintmsk.b.frmovrun = 1; + hcintmsk.b.ack = 1; + + if (pdev->host.hc[hc_num].ep_is_in) + { + hcintmsk.b.xacterr = 1; + hcintmsk.b.bblerr = 1; + } + break; + } + + + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, hcintmsk.d32); + + + /* Enable the top level host channel interrupt. */ + intr_enable = (1 << hc_num); + USB_OTG_MODIFY_REG32(&pdev->regs.HREGS->HAINTMSK, 0, intr_enable); + + /* Make sure host channel interrupts are enabled. */ + gintmsk.b.hcintr = 1; + USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, 0, gintmsk.d32); + + /* Program the HCCHAR register */ + hcchar.d32 = 0; + hcchar.b.devaddr = pdev->host.hc[hc_num].dev_addr; + hcchar.b.epnum = pdev->host.hc[hc_num].ep_num; + hcchar.b.epdir = pdev->host.hc[hc_num].ep_is_in; + hcchar.b.lspddev = (pdev->host.hc[hc_num].speed == HPRT0_PRTSPD_LOW_SPEED); + hcchar.b.eptype = pdev->host.hc[hc_num].ep_type; + hcchar.b.mps = pdev->host.hc[hc_num].max_packet; + if (pdev->host.hc[hc_num].ep_type == HCCHAR_INTR) + { + hcchar.b.oddfrm = 1; + } + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); + return status; +} + + +/** +* @brief USB_OTG_HC_StartXfer : Start transfer +* @param pdev : Selected device +* @param hc_num : channel number +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_HC_StartXfer(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_HCCHAR_TypeDef hcchar; + USB_OTG_HCTSIZn_TypeDef hctsiz; + USB_OTG_HNPTXSTS_TypeDef hnptxsts; + USB_OTG_HPTXSTS_TypeDef hptxsts; + USB_OTG_GINTMSK_TypeDef intmsk; + uint16_t len_words = 0; + + uint16_t num_packets; + uint16_t max_hc_pkt_count; + + max_hc_pkt_count = 256; + hctsiz.d32 = 0; + hcchar.d32 = 0; + intmsk.d32 = 0; + + /* Compute the expected number of packets associated to the transfer */ + if (pdev->host.hc[hc_num].xfer_len > 0) + { + num_packets = (pdev->host.hc[hc_num].xfer_len + \ + pdev->host.hc[hc_num].max_packet - 1) / pdev->host.hc[hc_num].max_packet; + + if (num_packets > max_hc_pkt_count) + { + num_packets = max_hc_pkt_count; + pdev->host.hc[hc_num].xfer_len = num_packets * \ + pdev->host.hc[hc_num].max_packet; + } + } + else + { + num_packets = 1; + } + if (pdev->host.hc[hc_num].ep_is_in) + { + pdev->host.hc[hc_num].xfer_len = num_packets * \ + pdev->host.hc[hc_num].max_packet; + } + /* Initialize the HCTSIZn register */ + hctsiz.b.xfersize = pdev->host.hc[hc_num].xfer_len; + hctsiz.b.pktcnt = num_packets; + hctsiz.b.pid = pdev->host.hc[hc_num].data_pid; + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCTSIZ, hctsiz.d32); + + if (pdev->cfg.dma_enable == 1) + { + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCDMA, (unsigned int)pdev->host.hc[hc_num].xfer_buff); + } + + + hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR); + hcchar.b.oddfrm = USB_OTG_IsEvenFrame(pdev); + + /* Set host channel enable */ + hcchar.b.chen = 1; + hcchar.b.chdis = 0; + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); + + if (pdev->cfg.dma_enable == 0) /* Slave mode */ + { + if((pdev->host.hc[hc_num].ep_is_in == 0) && + (pdev->host.hc[hc_num].xfer_len > 0)) + { + switch(pdev->host.hc[hc_num].ep_type) + { + /* Non periodic transfer */ + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + + hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS); + len_words = (pdev->host.hc[hc_num].xfer_len + 3) / 4; + + /* check if there is enough space in FIFO space */ + if(len_words > hnptxsts.b.nptxfspcavail) + { + /* need to process data in nptxfempty interrupt */ + intmsk.b.nptxfempty = 1; + USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, intmsk.d32); + } + + break; + /* Periodic transfer */ + case EP_TYPE_INTR: + case EP_TYPE_ISOC: + hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS); + len_words = (pdev->host.hc[hc_num].xfer_len + 3) / 4; + /* check if there is enough space in FIFO space */ + if(len_words > hptxsts.b.ptxfspcavail) /* split the transfer */ + { + /* need to process data in ptxfempty interrupt */ + intmsk.b.ptxfempty = 1; + USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, intmsk.d32); + } + break; + + default: + break; + } + + /* Write packet into the Tx FIFO. */ + USB_OTG_WritePacket(pdev, + pdev->host.hc[hc_num].xfer_buff , + hc_num, pdev->host.hc[hc_num].xfer_len); + } + } + return status; +} + + +/** +* @brief USB_OTG_HC_Halt : Halt channel +* @param pdev : Selected device +* @param hc_num : channel number +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_HC_Halt(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_HNPTXSTS_TypeDef nptxsts; + USB_OTG_HPTXSTS_TypeDef hptxsts; + USB_OTG_HCCHAR_TypeDef hcchar; + + nptxsts.d32 = 0; + hptxsts.d32 = 0; + hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR); + hcchar.b.chen = 1; + hcchar.b.chdis = 1; + + /* Check for space in the request queue to issue the halt. */ + if (hcchar.b.eptype == HCCHAR_CTRL || hcchar.b.eptype == HCCHAR_BULK) + { + nptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS); + if (nptxsts.b.nptxqspcavail == 0) + { + hcchar.b.chen = 0; + } + } + else + { + hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS); + if (hptxsts.b.ptxqspcavail == 0) + { + hcchar.b.chen = 0; + } + } + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); + return status; +} + +/** +* @brief Issue a ping token +* @param None +* @retval : None +*/ +USB_OTG_STS USB_OTG_HC_DoPing(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_HCCHAR_TypeDef hcchar; + USB_OTG_HCTSIZn_TypeDef hctsiz; + + hctsiz.d32 = 0; + hctsiz.b.dopng = 1; + hctsiz.b.pktcnt = 1; + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCTSIZ, hctsiz.d32); + + hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR); + hcchar.b.chen = 1; + hcchar.b.chdis = 0; + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); + return status; +} + +/** +* @brief Stop the device and clean up fifo's +* @param None +* @retval : None +*/ +void USB_OTG_StopHost(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_HCCHAR_TypeDef hcchar; + uint32_t i; + + USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HAINTMSK , 0); + USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HAINT, 0xFFFFFFFF); + /* Flush out any leftover queued requests. */ + + for (i = 0; i < pdev->cfg.host_channels; i++) + { + hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[i]->HCCHAR); + hcchar.b.chen = 0; + hcchar.b.chdis = 1; + hcchar.b.epdir = 0; + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[i]->HCCHAR, hcchar.d32); + } + + /* Flush the FIFO */ + USB_OTG_FlushRxFifo(pdev); + USB_OTG_FlushTxFifo(pdev , 0x10 ); +} +#endif +#ifdef USE_DEVICE_MODE +/* PCD Core Layer */ + +/** +* @brief USB_OTG_InitDevSpeed :Initializes the DevSpd field of DCFG register +* depending the PHY type and the enumeration speed of the device. +* @param pdev : Selected device +* @retval : None +*/ +void USB_OTG_InitDevSpeed(USB_OTG_CORE_HANDLE *pdev , uint8_t speed) +{ + USB_OTG_DCFG_TypeDef dcfg; + + dcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCFG); + dcfg.b.devspd = speed; + USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCFG, dcfg.d32); +} + + +/** +* @brief USB_OTG_CoreInitDev : Initializes the USB_OTG controller registers +* for device mode +* @param pdev : Selected device +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_CoreInitDev (USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_DEPCTL_TypeDef depctl; + uint32_t i; + USB_OTG_DCFG_TypeDef dcfg; + USB_OTG_FSIZ_TypeDef nptxfifosize; + USB_OTG_FSIZ_TypeDef txfifosize; + USB_OTG_DIEPMSK_TypeDef msk; + USB_OTG_DTHRCTL_TypeDef dthrctl; + + depctl.d32 = 0; + dcfg.d32 = 0; + nptxfifosize.d32 = 0; + txfifosize.d32 = 0; + msk.d32 = 0; + + /* Restart the Phy Clock */ + USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0); + /* Device configuration register */ + dcfg.d32 = USB_OTG_READ_REG32( &pdev->regs.DREGS->DCFG); + dcfg.b.perfrint = DCFG_FRAME_INTERVAL_80; + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DCFG, dcfg.d32 ); + +#ifdef USB_OTG_FS_CORE + if(pdev->cfg.coreID == USB_OTG_FS_CORE_ID ) + { + + /* Set Full speed phy */ + USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_FULL); + + /* set Rx FIFO size */ + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_FS_SIZE); + + /* EP0 TX*/ + nptxfifosize.b.depth = TX0_FIFO_FS_SIZE; + nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE; + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32 ); + + + /* EP1 TX*/ + txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth; + txfifosize.b.depth = TX1_FIFO_FS_SIZE; + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[0], txfifosize.d32 ); + + + /* EP2 TX*/ + txfifosize.b.startaddr += txfifosize.b.depth; + txfifosize.b.depth = TX2_FIFO_FS_SIZE; + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[1], txfifosize.d32 ); + + + /* EP3 TX*/ + txfifosize.b.startaddr += txfifosize.b.depth; + txfifosize.b.depth = TX3_FIFO_FS_SIZE; + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[2], txfifosize.d32 ); + } +#endif +#ifdef USB_OTG_HS_CORE + if(pdev->cfg.coreID == USB_OTG_HS_CORE_ID ) + { + + /* Set High speed phy */ + + if(pdev->cfg.phy_itface == USB_OTG_ULPI_PHY) + { + USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_HIGH); + } + else /* set High speed phy in Full speed mode */ + { + USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_HIGH_IN_FULL); + } + + /* set Rx FIFO size */ + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_HS_SIZE); + + /* EP0 TX*/ + nptxfifosize.b.depth = TX0_FIFO_HS_SIZE; + nptxfifosize.b.startaddr = RX_FIFO_HS_SIZE; + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32 ); + + + /* EP1 TX*/ + txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth; + txfifosize.b.depth = TX1_FIFO_HS_SIZE; + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[0], txfifosize.d32 ); + + + /* EP2 TX*/ + txfifosize.b.startaddr += txfifosize.b.depth; + txfifosize.b.depth = TX2_FIFO_HS_SIZE; + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[1], txfifosize.d32 ); + + + /* EP3 TX*/ + txfifosize.b.startaddr += txfifosize.b.depth; + txfifosize.b.depth = TX3_FIFO_HS_SIZE; + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[2], txfifosize.d32 ); + + /* EP4 TX*/ + txfifosize.b.startaddr += txfifosize.b.depth; + txfifosize.b.depth = TX4_FIFO_HS_SIZE; + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[3], txfifosize.d32 ); + + + /* EP5 TX*/ + txfifosize.b.startaddr += txfifosize.b.depth; + txfifosize.b.depth = TX5_FIFO_HS_SIZE; + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[4], txfifosize.d32 ); + } +#endif + /* Flush the FIFOs */ + USB_OTG_FlushTxFifo(pdev , 0x10); /* all Tx FIFOs */ + USB_OTG_FlushRxFifo(pdev); + /* Clear all pending Device Interrupts */ + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, 0 ); + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, 0 ); + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF ); + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, 0 ); + + for (i = 0; i < pdev->cfg.dev_endpoints; i++) + { + depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[i]->DIEPCTL); + if (depctl.b.epena) + { + depctl.d32 = 0; + depctl.b.epdis = 1; + depctl.b.snak = 1; + } + else + { + depctl.d32 = 0; + } + USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPCTL, depctl.d32); + USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPTSIZ, 0); + USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF); + } + for (i = 0; i < pdev->cfg.dev_endpoints; i++) + { + USB_OTG_DEPCTL_TypeDef depctl; + depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[i]->DOEPCTL); + if (depctl.b.epena) + { + depctl.d32 = 0; + depctl.b.epdis = 1; + depctl.b.snak = 1; + } + else + { + depctl.d32 = 0; + } + USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPCTL, depctl.d32); + USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPTSIZ, 0); + USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF); + } + msk.d32 = 0; + msk.b.txfifoundrn = 1; + USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPMSK, msk.d32, msk.d32); + + if (pdev->cfg.dma_enable == 1) + { + dthrctl.d32 = 0; + dthrctl.b.non_iso_thr_en = 1; + dthrctl.b.iso_thr_en = 1; + dthrctl.b.tx_thr_len = 64; + dthrctl.b.rx_thr_en = 1; + dthrctl.b.rx_thr_len = 64; + USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DTHRCTL, dthrctl.d32); + } + USB_OTG_EnableDevInt(pdev); + return status; +} + + +/** +* @brief USB_OTG_EnableDevInt : Enables the Device mode interrupts +* @param pdev : Selected device +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_EnableDevInt(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_GINTMSK_TypeDef intmsk; + + intmsk.d32 = 0; + + /* Disable all interrupts. */ + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTMSK, 0); + /* Clear any pending interrupts */ + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, 0xBFFFFFFF); + /* Enable the common interrupts */ + USB_OTG_EnableCommonInt(pdev); + + if (pdev->cfg.dma_enable == 0) + { + intmsk.b.rxstsqlvl = 1; + } + + /* Enable interrupts matching to the Device mode ONLY */ + intmsk.b.usbsuspend = 1; + intmsk.b.usbreset = 1; + intmsk.b.enumdone = 1; + intmsk.b.inepintr = 1; + intmsk.b.outepintr = 1; + intmsk.b.sofintr = 1; + + intmsk.b.incomplisoin = 1; + intmsk.b.incomplisoout = 1; +#ifdef VBUS_SENSING_ENABLED + intmsk.b.sessreqintr = 1; + intmsk.b.otgintr = 1; +#endif + USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, intmsk.d32); + return status; +} + + +/** +* @brief USB_OTG_GetDeviceSpeed +* Get the device speed from the device status register +* @param None +* @retval status +*/ +enum USB_OTG_SPEED USB_OTG_GetDeviceSpeed (USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_DSTS_TypeDef dsts; + enum USB_OTG_SPEED speed = USB_SPEED_UNKNOWN; + + + dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); + + switch (dsts.b.enumspd) + { + case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: + speed = USB_SPEED_HIGH; + break; + case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: + case DSTS_ENUMSPD_FS_PHY_48MHZ: + speed = USB_SPEED_FULL; + break; + + case DSTS_ENUMSPD_LS_PHY_6MHZ: + speed = USB_SPEED_LOW; + break; + } + + return speed; +} +/** +* @brief enables EP0 OUT to receive SETUP packets and configures EP0 +* for transmitting packets +* @param None +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_EP0Activate(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_DSTS_TypeDef dsts; + USB_OTG_DEPCTL_TypeDef diepctl; + USB_OTG_DCTL_TypeDef dctl; + + dctl.d32 = 0; + /* Read the Device Status and Endpoint 0 Control registers */ + dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); + diepctl.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[0]->DIEPCTL); + /* Set the MPS of the IN EP based on the enumeration speed */ + switch (dsts.b.enumspd) + { + case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: + case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: + case DSTS_ENUMSPD_FS_PHY_48MHZ: + diepctl.b.mps = DEP0CTL_MPS_64; + break; + case DSTS_ENUMSPD_LS_PHY_6MHZ: + diepctl.b.mps = DEP0CTL_MPS_8; + break; + } + USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[0]->DIEPCTL, diepctl.d32); + dctl.b.cgnpinnak = 1; + USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, dctl.d32); + return status; +} + + +/** +* @brief USB_OTG_EPActivate : Activates an EP +* @param pdev : Selected device +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_EPActivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_DEPCTL_TypeDef depctl; + USB_OTG_DAINT_TypeDef daintmsk; + __IO uint32_t *addr; + + + depctl.d32 = 0; + daintmsk.d32 = 0; + /* Read DEPCTLn register */ + if (ep->is_in == 1) + { + addr = &pdev->regs.INEP_REGS[ep->num]->DIEPCTL; + daintmsk.ep.in = 1 << ep->num; + } + else + { + addr = &pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL; + daintmsk.ep.out = 1 << ep->num; + } + /* If the EP is already active don't change the EP Control + * register. */ + depctl.d32 = USB_OTG_READ_REG32(addr); + if (!depctl.b.usbactep) + { + depctl.b.mps = ep->maxpacket; + depctl.b.eptype = ep->type; + depctl.b.txfnum = ep->tx_fifo_num; + depctl.b.setd0pid = 1; + depctl.b.usbactep = 1; + USB_OTG_WRITE_REG32(addr, depctl.d32); + } + /* Enable the Interrupt for this EP */ +#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED + if((ep->num == 1)&&(pdev->cfg.coreID == USB_OTG_HS_CORE_ID)) + { + USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DEACHMSK, 0, daintmsk.d32); + } + else +#endif + USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DAINTMSK, 0, daintmsk.d32); + return status; +} + + +/** +* @brief USB_OTG_EPDeactivate : Deactivates an EP +* @param pdev : Selected device +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_EPDeactivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_DEPCTL_TypeDef depctl; + USB_OTG_DAINT_TypeDef daintmsk; + __IO uint32_t *addr; + + depctl.d32 = 0; + daintmsk.d32 = 0; + /* Read DEPCTLn register */ + if (ep->is_in == 1) + { + addr = &pdev->regs.INEP_REGS[ep->num]->DIEPCTL; + daintmsk.ep.in = 1 << ep->num; + } + else + { + addr = &pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL; + daintmsk.ep.out = 1 << ep->num; + } + depctl.b.usbactep = 0; + USB_OTG_WRITE_REG32(addr, depctl.d32); + /* Disable the Interrupt for this EP */ + +#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED + if((ep->num == 1)&&(pdev->cfg.coreID == USB_OTG_HS_CORE_ID)) + { + USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DEACHMSK, daintmsk.d32, 0); + } + else +#endif + USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DAINTMSK, daintmsk.d32, 0); + return status; +} + + +/** +* @brief USB_OTG_EPStartXfer : Handle the setup for data xfer for an EP and +* starts the xfer +* @param pdev : Selected device +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_EPStartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_DEPCTL_TypeDef depctl; + USB_OTG_DEPXFRSIZ_TypeDef deptsiz; + USB_OTG_DSTS_TypeDef dsts; + uint32_t fifoemptymsk = 0; + + depctl.d32 = 0; + deptsiz.d32 = 0; + /* IN endpoint */ + if (ep->is_in == 1) + { + depctl.d32 = USB_OTG_READ_REG32(&(pdev->regs.INEP_REGS[ep->num]->DIEPCTL)); + deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.INEP_REGS[ep->num]->DIEPTSIZ)); + /* Zero Length Packet? */ + if (ep->xfer_len == 0) + { + deptsiz.b.xfersize = 0; + deptsiz.b.pktcnt = 1; + } + else + { + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet + * exist ? 1 : 0) + */ + deptsiz.b.xfersize = ep->xfer_len; + deptsiz.b.pktcnt = (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket; + + if (ep->type == EP_TYPE_ISOC) + { + deptsiz.b.mc = 1; + } + } + USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPTSIZ, deptsiz.d32); + + if (pdev->cfg.dma_enable == 1) + { + USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPDMA, ep->dma_addr); + } + else + { + if (ep->type != EP_TYPE_ISOC) + { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0) + { + fifoemptymsk = 1 << ep->num; + USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, 0, fifoemptymsk); + } + } + } + + + if (ep->type == EP_TYPE_ISOC) + { + dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); + + if (((dsts.b.soffn)&0x1) == 0) + { + depctl.b.setd1pid = 1; + } + else + { + depctl.b.setd0pid = 1; + } + } + + /* EP enable, IN data in FIFO */ + depctl.b.cnak = 1; + depctl.b.epena = 1; + USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPCTL, depctl.d32); + + if (ep->type == EP_TYPE_ISOC) + { + USB_OTG_WritePacket(pdev, ep->xfer_buff, ep->num, ep->xfer_len); + } + } + else + { + /* OUT endpoint */ + depctl.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL)); + deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ)); + /* Program the transfer size and packet count as follows: + * pktcnt = N + * xfersize = N * maxpacket + */ + if (ep->xfer_len == 0) + { + deptsiz.b.xfersize = ep->maxpacket; + deptsiz.b.pktcnt = 1; + } + else + { + deptsiz.b.pktcnt = (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket; + deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket; + } + USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ, deptsiz.d32); + + if (pdev->cfg.dma_enable == 1) + { + USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPDMA, ep->dma_addr); + } + + if (ep->type == EP_TYPE_ISOC) + { + if (ep->even_odd_frame) + { + depctl.b.setd1pid = 1; + } + else + { + depctl.b.setd0pid = 1; + } + } + /* EP enable */ + depctl.b.cnak = 1; + depctl.b.epena = 1; + USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL, depctl.d32); + } + return status; +} + + +/** +* @brief USB_OTG_EP0StartXfer : Handle the setup for a data xfer for EP0 and +* starts the xfer +* @param pdev : Selected device +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_EP0StartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_DEPCTL_TypeDef depctl; + USB_OTG_DEP0XFRSIZ_TypeDef deptsiz; + USB_OTG_INEPREGS *in_regs; + uint32_t fifoemptymsk = 0; + + depctl.d32 = 0; + deptsiz.d32 = 0; + /* IN endpoint */ + if (ep->is_in == 1) + { + in_regs = pdev->regs.INEP_REGS[0]; + depctl.d32 = USB_OTG_READ_REG32(&in_regs->DIEPCTL); + deptsiz.d32 = USB_OTG_READ_REG32(&in_regs->DIEPTSIZ); + /* Zero Length Packet? */ + if (ep->xfer_len == 0) + { + deptsiz.b.xfersize = 0; + deptsiz.b.pktcnt = 1; + + } + else + { + if (ep->xfer_len > ep->maxpacket) + { + ep->xfer_len = ep->maxpacket; + deptsiz.b.xfersize = ep->maxpacket; + } + else + { + deptsiz.b.xfersize = ep->xfer_len; + } + deptsiz.b.pktcnt = 1; + } + USB_OTG_WRITE_REG32(&in_regs->DIEPTSIZ, deptsiz.d32); + + if (pdev->cfg.dma_enable == 1) + { + USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPDMA, ep->dma_addr); + } + + /* EP enable, IN data in FIFO */ + depctl.b.cnak = 1; + depctl.b.epena = 1; + USB_OTG_WRITE_REG32(&in_regs->DIEPCTL, depctl.d32); + + + + if (pdev->cfg.dma_enable == 0) + { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0) + { + { + fifoemptymsk |= 1 << ep->num; + USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, 0, fifoemptymsk); + } + } + } + } + else + { + /* OUT endpoint */ + depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); + deptsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ); + /* Program the transfer size and packet count as follows: + * xfersize = N * (maxpacket + 4 - (maxpacket % 4)) + * pktcnt = N */ + if (ep->xfer_len == 0) + { + deptsiz.b.xfersize = ep->maxpacket; + deptsiz.b.pktcnt = 1; + } + else + { + ep->xfer_len = ep->maxpacket; + deptsiz.b.xfersize = ep->maxpacket; + deptsiz.b.pktcnt = 1; + } + USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ, deptsiz.d32); + if (pdev->cfg.dma_enable == 1) + { + USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPDMA, ep->dma_addr); + } + /* EP enable */ + depctl.b.cnak = 1; + depctl.b.epena = 1; + USB_OTG_WRITE_REG32 (&(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL), depctl.d32); + + } + return status; +} + + +/** +* @brief USB_OTG_EPSetStall : Set the EP STALL +* @param pdev : Selected device +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_EPSetStall(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_DEPCTL_TypeDef depctl; + __IO uint32_t *depctl_addr; + + depctl.d32 = 0; + if (ep->is_in == 1) + { + depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); + depctl.d32 = USB_OTG_READ_REG32(depctl_addr); + /* set the disable and stall bits */ + if (depctl.b.epena) + { + depctl.b.epdis = 1; + } + depctl.b.stall = 1; + USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); + } + else + { + depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); + depctl.d32 = USB_OTG_READ_REG32(depctl_addr); + /* set the stall bit */ + depctl.b.stall = 1; + USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); + } + return status; +} + + +/** +* @brief Clear the EP STALL +* @param pdev : Selected device +* @retval USB_OTG_STS : status +*/ +USB_OTG_STS USB_OTG_EPClearStall(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) +{ + USB_OTG_STS status = USB_OTG_OK; + USB_OTG_DEPCTL_TypeDef depctl; + __IO uint32_t *depctl_addr; + + depctl.d32 = 0; + + if (ep->is_in == 1) + { + depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); + } + else + { + depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); + } + depctl.d32 = USB_OTG_READ_REG32(depctl_addr); + /* clear the stall bits */ + depctl.b.stall = 0; + if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK) + { + depctl.b.setd0pid = 1; /* DATA0 */ + } + USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); + return status; +} + + +/** +* @brief USB_OTG_ReadDevAllOutEp_itr : returns OUT endpoint interrupt bits +* @param pdev : Selected device +* @retval OUT endpoint interrupt bits +*/ +uint32_t USB_OTG_ReadDevAllOutEp_itr(USB_OTG_CORE_HANDLE *pdev) +{ + uint32_t v; + v = USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINT); + v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINTMSK); + return ((v & 0xffff0000) >> 16); +} + + +/** +* @brief USB_OTG_ReadDevOutEP_itr : returns Device OUT EP Interrupt register +* @param pdev : Selected device +* @param ep : end point number +* @retval Device OUT EP Interrupt register +*/ +uint32_t USB_OTG_ReadDevOutEP_itr(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) +{ + uint32_t v; + v = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[epnum]->DOEPINT); + v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DOEPMSK); + return v; +} + + +/** +* @brief USB_OTG_ReadDevAllInEPItr : Get int status register +* @param pdev : Selected device +* @retval int status register +*/ +uint32_t USB_OTG_ReadDevAllInEPItr(USB_OTG_CORE_HANDLE *pdev) +{ + uint32_t v; + v = USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINT); + v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINTMSK); + return (v & 0xffff); +} + +/** +* @brief configures EPO to receive SETUP packets +* @param None +* @retval : None +*/ +void USB_OTG_EP0_OutStart(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_DEP0XFRSIZ_TypeDef doeptsize0; + doeptsize0.d32 = 0; + doeptsize0.b.supcnt = 3; + doeptsize0.b.pktcnt = 1; + doeptsize0.b.xfersize = 8 * 3; + USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPTSIZ, doeptsize0.d32 ); + + if (pdev->cfg.dma_enable == 1) + { + USB_OTG_DEPCTL_TypeDef doepctl; + doepctl.d32 = 0; + USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPDMA, + (uint32_t)&pdev->dev.setup_packet); + + /* EP enable */ + doepctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[0]->DOEPCTL); + doepctl.b.epena = 1; + doepctl.d32 = 0x80008000; + USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPCTL, doepctl.d32); + } +} + +/** +* @brief USB_OTG_RemoteWakeup : active remote wakeup signalling +* @param None +* @retval : None +*/ +void USB_OTG_ActiveRemoteWakeup(USB_OTG_CORE_HANDLE *pdev) +{ + + USB_OTG_DCTL_TypeDef dctl; + USB_OTG_DSTS_TypeDef dsts; + USB_OTG_PCGCCTL_TypeDef power; + + if (pdev->dev.DevRemoteWakeup) + { + dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); + if(dsts.b.suspsts == 1) + { + if(pdev->cfg.low_power) + { + /* un-gate USB Core clock */ + power.d32 = USB_OTG_READ_REG32(&pdev->regs.PCGCCTL); + power.b.gatehclk = 0; + power.b.stoppclk = 0; + USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32); + } + /* active Remote wakeup signaling */ + dctl.d32 = 0; + dctl.b.rmtwkupsig = 1; + USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, 0, dctl.d32); + USB_OTG_BSP_mDelay(5); + USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, 0 ); + } + } +} + + +/** +* @brief USB_OTG_UngateClock : active USB Core clock +* @param None +* @retval : None +*/ +void USB_OTG_UngateClock(USB_OTG_CORE_HANDLE *pdev) +{ + if(pdev->cfg.low_power) + { + + USB_OTG_DSTS_TypeDef dsts; + USB_OTG_PCGCCTL_TypeDef power; + + dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); + + if(dsts.b.suspsts == 1) + { + /* un-gate USB Core clock */ + power.d32 = USB_OTG_READ_REG32(&pdev->regs.PCGCCTL); + power.b.gatehclk = 0; + power.b.stoppclk = 0; + USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32); + + } + } +} + +/** +* @brief Stop the device and clean up fifo's +* @param None +* @retval : None +*/ +void USB_OTG_StopDevice(USB_OTG_CORE_HANDLE *pdev) +{ + uint32_t i; + + pdev->dev.device_status = 1; + + for (i = 0; i < pdev->cfg.dev_endpoints ; i++) + { + USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF); + USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF); + } + + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, 0 ); + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, 0 ); + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, 0 ); + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF ); + + /* Flush the FIFO */ + USB_OTG_FlushRxFifo(pdev); + USB_OTG_FlushTxFifo(pdev , 0x10 ); +} + +/** +* @brief returns the EP Status +* @param pdev : Selected device +* ep : endpoint structure +* @retval : EP status +*/ + +uint32_t USB_OTG_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,USB_OTG_EP *ep) +{ + USB_OTG_DEPCTL_TypeDef depctl; + __IO uint32_t *depctl_addr; + uint32_t Status = 0; + + depctl.d32 = 0; + if (ep->is_in == 1) + { + depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); + depctl.d32 = USB_OTG_READ_REG32(depctl_addr); + + if (depctl.b.stall == 1) + Status = USB_OTG_EP_TX_STALL; + else if (depctl.b.naksts == 1) + Status = USB_OTG_EP_TX_NAK; + else + Status = USB_OTG_EP_TX_VALID; + + } + else + { + depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); + depctl.d32 = USB_OTG_READ_REG32(depctl_addr); + if (depctl.b.stall == 1) + Status = USB_OTG_EP_RX_STALL; + else if (depctl.b.naksts == 1) + Status = USB_OTG_EP_RX_NAK; + else + Status = USB_OTG_EP_RX_VALID; + } + + /* Return the current status */ + return Status; +} + +/** +* @brief Set the EP Status +* @param pdev : Selected device +* Status : new Status +* ep : EP structure +* @retval : None +*/ +void USB_OTG_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep , uint32_t Status) +{ + USB_OTG_DEPCTL_TypeDef depctl; + __IO uint32_t *depctl_addr; + + depctl.d32 = 0; + + /* Process for IN endpoint */ + if (ep->is_in == 1) + { + depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); + depctl.d32 = USB_OTG_READ_REG32(depctl_addr); + + if (Status == USB_OTG_EP_TX_STALL) + { + USB_OTG_EPSetStall(pdev, ep); return; + } + else if (Status == USB_OTG_EP_TX_NAK) + depctl.b.snak = 1; + else if (Status == USB_OTG_EP_TX_VALID) + { + if (depctl.b.stall == 1) + { + ep->even_odd_frame = 0; + USB_OTG_EPClearStall(pdev, ep); + return; + } + depctl.b.cnak = 1; + depctl.b.usbactep = 1; + depctl.b.epena = 1; + } + else if (Status == USB_OTG_EP_TX_DIS) + depctl.b.usbactep = 0; + } + else /* Process for OUT endpoint */ + { + depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); + depctl.d32 = USB_OTG_READ_REG32(depctl_addr); + + if (Status == USB_OTG_EP_RX_STALL) { + depctl.b.stall = 1; + } + else if (Status == USB_OTG_EP_RX_NAK) + depctl.b.snak = 1; + else if (Status == USB_OTG_EP_RX_VALID) + { + if (depctl.b.stall == 1) + { + ep->even_odd_frame = 0; + USB_OTG_EPClearStall(pdev, ep); + return; + } + depctl.b.cnak = 1; + depctl.b.usbactep = 1; + depctl.b.epena = 1; + } + else if (Status == USB_OTG_EP_RX_DIS) + { + depctl.b.usbactep = 0; + } + } + + USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); +} + +#endif +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/usb/usb_dcd.c b/radio/bootloader/usb/usb_dcd.c new file mode 100644 index 000000000..36428e2a0 --- /dev/null +++ b/radio/bootloader/usb/usb_dcd.c @@ -0,0 +1,478 @@ +/** + ****************************************************************************** + * @file usb_dcd.c + * @author MCD Application Team + * @version V2.1.0 + * @date 19-March-2012 + * @brief Peripheral Device Interface Layer + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usb_dcd.h" +#include "usb_bsp.h" + + +/** @addtogroup USB_OTG_DRIVER +* @{ +*/ + +/** @defgroup USB_DCD +* @brief This file is the interface between EFSL ans Host mass-storage class +* @{ +*/ + + +/** @defgroup USB_DCD_Private_Defines +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USB_DCD_Private_TypesDefinitions +* @{ +*/ +/** +* @} +*/ + + + +/** @defgroup USB_DCD_Private_Macros +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USB_DCD_Private_Variables +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USB_DCD_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + + +/** @defgroup USB_DCD_Private_Functions +* @{ +*/ + + + +void DCD_Init(USB_OTG_CORE_HANDLE *pdev , + USB_OTG_CORE_ID_TypeDef coreID) +{ + uint32_t i; + USB_OTG_EP *ep; + + USB_OTG_SelectCore (pdev , coreID); + + pdev->dev.device_status = USB_OTG_DEFAULT; + pdev->dev.device_address = 0; + + /* Init ep structure */ + for (i = 0; i < pdev->cfg.dev_endpoints ; i++) + { + ep = &pdev->dev.in_ep[i]; + /* Init ep structure */ + ep->is_in = 1; + ep->num = i; + ep->tx_fifo_num = i; + /* Control until ep is actvated */ + ep->type = EP_TYPE_CTRL; + ep->maxpacket = USB_OTG_MAX_EP0_SIZE; + ep->xfer_buff = 0; + ep->xfer_len = 0; + } + + for (i = 0; i < pdev->cfg.dev_endpoints; i++) + { + ep = &pdev->dev.out_ep[i]; + /* Init ep structure */ + ep->is_in = 0; + ep->num = i; + ep->tx_fifo_num = i; + /* Control until ep is activated */ + ep->type = EP_TYPE_CTRL; + ep->maxpacket = USB_OTG_MAX_EP0_SIZE; + ep->xfer_buff = 0; + ep->xfer_len = 0; + } + + USB_OTG_DisableGlobalInt(pdev); + + /*Init the Core (common init.) */ + USB_OTG_CoreInit(pdev); + + + /* Force Device Mode*/ + USB_OTG_SetCurrentMode(pdev, DEVICE_MODE); + + /* Init Device */ + USB_OTG_CoreInitDev(pdev); + + + /* Enable USB Global interrupt */ + USB_OTG_EnableGlobalInt(pdev); +} + + +/** +* @brief Configure an EP +* @param pdev : Device instance +* @param epdesc : Endpoint Descriptor +* @retval : status +*/ +uint32_t DCD_EP_Open(USB_OTG_CORE_HANDLE *pdev , + uint8_t ep_addr, + uint16_t ep_mps, + uint8_t ep_type) +{ + USB_OTG_EP *ep; + + if ((ep_addr & 0x80) == 0x80) + { + ep = &pdev->dev.in_ep[ep_addr & 0x7F]; + } + else + { + ep = &pdev->dev.out_ep[ep_addr & 0x7F]; + } + ep->num = ep_addr & 0x7F; + + ep->is_in = (0x80 & ep_addr) != 0; + ep->maxpacket = ep_mps; + ep->type = ep_type; + if (ep->is_in) + { + /* Assign a Tx FIFO */ + ep->tx_fifo_num = ep->num; + } + /* Set initial data PID. */ + if (ep_type == USB_OTG_EP_BULK ) + { + ep->data_pid_start = 0; + } + USB_OTG_EPActivate(pdev , ep ); + return 0; +} +/** +* @brief called when an EP is disabled +* @param pdev: device instance +* @param ep_addr: endpoint address +* @retval : status +*/ +uint32_t DCD_EP_Close(USB_OTG_CORE_HANDLE *pdev , uint8_t ep_addr) +{ + USB_OTG_EP *ep; + + if ((ep_addr&0x80) == 0x80) + { + ep = &pdev->dev.in_ep[ep_addr & 0x7F]; + } + else + { + ep = &pdev->dev.out_ep[ep_addr & 0x7F]; + } + ep->num = ep_addr & 0x7F; + ep->is_in = (0x80 & ep_addr) != 0; + USB_OTG_EPDeactivate(pdev , ep ); + return 0; +} + + +/** +* @brief DCD_EP_PrepareRx +* @param pdev: device instance +* @param ep_addr: endpoint address +* @param pbuf: pointer to Rx buffer +* @param buf_len: data length +* @retval : status +*/ +uint32_t DCD_EP_PrepareRx( USB_OTG_CORE_HANDLE *pdev, + uint8_t ep_addr, + uint8_t *pbuf, + uint16_t buf_len) +{ + USB_OTG_EP *ep; + + ep = &pdev->dev.out_ep[ep_addr & 0x7F]; + + /*setup and start the Xfer */ + ep->xfer_buff = pbuf; + ep->xfer_len = buf_len; + ep->xfer_count = 0; + ep->is_in = 0; + ep->num = ep_addr & 0x7F; + + if (pdev->cfg.dma_enable == 1) + { + ep->dma_addr = (uint32_t)pbuf; + } + + if ( ep->num == 0 ) + { + USB_OTG_EP0StartXfer(pdev , ep); + } + else + { + USB_OTG_EPStartXfer(pdev, ep ); + } + return 0; +} + +/** +* @brief Transmit data over USB +* @param pdev: device instance +* @param ep_addr: endpoint address +* @param pbuf: pointer to Tx buffer +* @param buf_len: data length +* @retval : status +*/ +uint32_t DCD_EP_Tx ( USB_OTG_CORE_HANDLE *pdev, + uint8_t ep_addr, + uint8_t *pbuf, + uint32_t buf_len) +{ + USB_OTG_EP *ep; + + ep = &pdev->dev.in_ep[ep_addr & 0x7F]; + + /* Setup and start the Transfer */ + ep->is_in = 1; + ep->num = ep_addr & 0x7F; + ep->xfer_buff = pbuf; + ep->dma_addr = (uint32_t)pbuf; + ep->xfer_count = 0; + ep->xfer_len = buf_len; + + if ( ep->num == 0 ) + { + USB_OTG_EP0StartXfer(pdev , ep); + } + else + { + USB_OTG_EPStartXfer(pdev, ep ); + } + return 0; +} + + +/** +* @brief Stall an endpoint. +* @param pdev: device instance +* @param epnum: endpoint address +* @retval : status +*/ +uint32_t DCD_EP_Stall (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum) +{ + USB_OTG_EP *ep; + if ((0x80 & epnum) == 0x80) + { + ep = &pdev->dev.in_ep[epnum & 0x7F]; + } + else + { + ep = &pdev->dev.out_ep[epnum]; + } + + ep->is_stall = 1; + ep->num = epnum & 0x7F; + ep->is_in = ((epnum & 0x80) == 0x80); + + USB_OTG_EPSetStall(pdev , ep); + return (0); +} + + +/** +* @brief Clear stall condition on endpoints. +* @param pdev: device instance +* @param epnum: endpoint address +* @retval : status +*/ +uint32_t DCD_EP_ClrStall (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum) +{ + USB_OTG_EP *ep; + if ((0x80 & epnum) == 0x80) + { + ep = &pdev->dev.in_ep[epnum & 0x7F]; + } + else + { + ep = &pdev->dev.out_ep[epnum]; + } + + ep->is_stall = 0; + ep->num = epnum & 0x7F; + ep->is_in = ((epnum & 0x80) == 0x80); + + USB_OTG_EPClearStall(pdev , ep); + return (0); +} + + +/** +* @brief This Function flushes the FIFOs. +* @param pdev: device instance +* @param epnum: endpoint address +* @retval : status +*/ +uint32_t DCD_EP_Flush (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) +{ + + if ((epnum & 0x80) == 0x80) + { + USB_OTG_FlushTxFifo(pdev, epnum & 0x7F); + } + else + { + USB_OTG_FlushRxFifo(pdev); + } + + return (0); +} + + +/** +* @brief This Function set USB device address +* @param pdev: device instance +* @param address: new device address +* @retval : status +*/ +void DCD_EP_SetAddress (USB_OTG_CORE_HANDLE *pdev, uint8_t address) +{ + USB_OTG_DCFG_TypeDef dcfg; + dcfg.d32 = 0; + dcfg.b.devaddr = address; + USB_OTG_MODIFY_REG32( &pdev->regs.DREGS->DCFG, 0, dcfg.d32); +} + +/** +* @brief Connect device (enable internal pull-up) +* @param pdev: device instance +* @retval : None +*/ +void DCD_DevConnect (USB_OTG_CORE_HANDLE *pdev) +{ +#ifndef USE_OTG_MODE + USB_OTG_DCTL_TypeDef dctl; + dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL); + /* Connect device */ + dctl.b.sftdiscon = 0; + USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, dctl.d32); + USB_OTG_BSP_mDelay(3); +#endif +} + + +/** +* @brief Disconnect device (disable internal pull-up) +* @param pdev: device instance +* @retval : None +*/ +void DCD_DevDisconnect (USB_OTG_CORE_HANDLE *pdev) +{ +#ifndef USE_OTG_MODE + USB_OTG_DCTL_TypeDef dctl; + dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL); + /* Disconnect device for 3ms */ + dctl.b.sftdiscon = 1; + USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, dctl.d32); + USB_OTG_BSP_mDelay(3); +#endif +} + + +/** +* @brief returns the EP Status +* @param pdev : Selected device +* epnum : endpoint address +* @retval : EP status +*/ + +uint32_t DCD_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,uint8_t epnum) +{ + USB_OTG_EP *ep; + uint32_t Status = 0; + + if ((0x80 & epnum) == 0x80) + { + ep = &pdev->dev.in_ep[epnum & 0x7F]; + } + else + { + ep = &pdev->dev.out_ep[epnum]; + } + + Status = USB_OTG_GetEPStatus(pdev ,ep); + + /* Return the current status */ + return Status; +} + +/** +* @brief Set the EP Status +* @param pdev : Selected device +* Status : new Status +* epnum : EP address +* @retval : None +*/ +void DCD_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum , uint32_t Status) +{ + USB_OTG_EP *ep; + + if ((0x80 & epnum) == 0x80) + { + ep = &pdev->dev.in_ep[epnum & 0x7F]; + } + else + { + ep = &pdev->dev.out_ep[epnum]; + } + + USB_OTG_SetEPStatus(pdev ,ep , Status); +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/usb/usb_dcd_int.c b/radio/bootloader/usb/usb_dcd_int.c new file mode 100644 index 000000000..359d56997 --- /dev/null +++ b/radio/bootloader/usb/usb_dcd_int.c @@ -0,0 +1,869 @@ +/** + ****************************************************************************** + * @file usb_dcd_int.c + * @author MCD Application Team + * @version V2.1.0 + * @date 19-March-2012 + * @brief Peripheral Device interrupt subroutines + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usb_dcd_int.h" +/** @addtogroup USB_OTG_DRIVER +* @{ +*/ + +/** @defgroup USB_DCD_INT +* @brief This file contains the interrupt subroutines for the Device mode. +* @{ +*/ + + +/** @defgroup USB_DCD_INT_Private_Defines +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USB_DCD_INT_Private_TypesDefinitions +* @{ +*/ +/** +* @} +*/ + + + +/** @defgroup USB_DCD_INT_Private_Macros +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USB_DCD_INT_Private_Variables +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USB_DCD_INT_Private_FunctionPrototypes +* @{ +*/ +/* static functions */ +static uint32_t DCD_ReadDevInEP (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum); + +/* Interrupt Handlers */ +static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev); +static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev); +static uint32_t DCD_HandleSof_ISR(USB_OTG_CORE_HANDLE *pdev); + +static uint32_t DCD_HandleRxStatusQueueLevel_ISR(USB_OTG_CORE_HANDLE *pdev); +static uint32_t DCD_WriteEmptyTxFifo(USB_OTG_CORE_HANDLE *pdev , uint32_t epnum); + +static uint32_t DCD_HandleUsbReset_ISR(USB_OTG_CORE_HANDLE *pdev); +static uint32_t DCD_HandleEnumDone_ISR(USB_OTG_CORE_HANDLE *pdev); +static uint32_t DCD_HandleResume_ISR(USB_OTG_CORE_HANDLE *pdev); +static uint32_t DCD_HandleUSBSuspend_ISR(USB_OTG_CORE_HANDLE *pdev); + +static uint32_t DCD_IsoINIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev); +static uint32_t DCD_IsoOUTIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev); +#ifdef VBUS_SENSING_ENABLED +static uint32_t DCD_SessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev); +static uint32_t DCD_OTG_ISR(USB_OTG_CORE_HANDLE *pdev); +#endif + +/** +* @} +*/ + + +/** @defgroup USB_DCD_INT_Private_Functions +* @{ +*/ + + +#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED +/** +* @brief USBD_OTG_EP1OUT_ISR_Handler +* handles all USB Interrupts +* @param pdev: device instance +* @retval status +*/ +uint32_t USBD_OTG_EP1OUT_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) +{ + + USB_OTG_DOEPINTn_TypeDef doepint; + USB_OTG_DEPXFRSIZ_TypeDef deptsiz; + + doepint.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[1]->DOEPINT); + doepint.d32&= USB_OTG_READ_REG32(&pdev->regs.DREGS->DOUTEP1MSK); + + /* Transfer complete */ + if ( doepint.b.xfercompl ) + { + /* Clear the bit in DOEPINTn for this interrupt */ + CLEAR_OUT_EP_INTR(1, xfercompl); + if (pdev->cfg.dma_enable == 1) + { + deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[1]->DOEPTSIZ)); + /*ToDo : handle more than one single MPS size packet */ + pdev->dev.out_ep[1].xfer_count = pdev->dev.out_ep[1].maxpacket - \ + deptsiz.b.xfersize; + } + /* Inform upper layer: data ready */ + /* RX COMPLETE */ + USBD_DCD_INT_fops->DataOutStage(pdev , 1); + + } + + /* Endpoint disable */ + if ( doepint.b.epdisabled ) + { + /* Clear the bit in DOEPINTn for this interrupt */ + CLEAR_OUT_EP_INTR(1, epdisabled); + } + + return 1; +} + +/** +* @brief USBD_OTG_EP1IN_ISR_Handler +* handles all USB Interrupts +* @param pdev: device instance +* @retval status +*/ +uint32_t USBD_OTG_EP1IN_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) +{ + + USB_OTG_DIEPINTn_TypeDef diepint; + uint32_t fifoemptymsk, msk, emp; + + msk = USB_OTG_READ_REG32(&pdev->regs.DREGS->DINEP1MSK); + emp = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPEMPMSK); + msk |= ((emp >> 1 ) & 0x1) << 7; + diepint.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[1]->DIEPINT) & msk; + + if ( diepint.b.xfercompl ) + { + fifoemptymsk = 0x1 << 1; + USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, fifoemptymsk, 0); + CLEAR_IN_EP_INTR(1, xfercompl); + /* TX COMPLETE */ + USBD_DCD_INT_fops->DataInStage(pdev , 1); + } + if ( diepint.b.epdisabled ) + { + CLEAR_IN_EP_INTR(1, epdisabled); + } + if ( diepint.b.timeout ) + { + CLEAR_IN_EP_INTR(1, timeout); + } + if (diepint.b.intktxfemp) + { + CLEAR_IN_EP_INTR(1, intktxfemp); + } + if (diepint.b.inepnakeff) + { + CLEAR_IN_EP_INTR(1, inepnakeff); + } + if (diepint.b.emptyintr) + { + DCD_WriteEmptyTxFifo(pdev , 1); + CLEAR_IN_EP_INTR(1, emptyintr); + } + return 1; +} +#endif + +/** +* @brief STM32_USBF_OTG_ISR_Handler +* handles all USB Interrupts +* @param pdev: device instance +* @retval status +*/ +uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_GINTSTS_TypeDef gintr_status; + uint32_t retval = 0; + + if (USB_OTG_IsDeviceMode(pdev)) /* ensure that we are in device mode */ + { + gintr_status.d32 = USB_OTG_ReadCoreItr(pdev); + if (!gintr_status.d32) /* avoid spurious interrupt */ + { + return 0; + } + + if (gintr_status.b.outepintr) + { + retval |= DCD_HandleOutEP_ISR(pdev); + } + + if (gintr_status.b.inepint) + { + retval |= DCD_HandleInEP_ISR(pdev); + } + + if (gintr_status.b.modemismatch) + { + USB_OTG_GINTSTS_TypeDef gintsts; + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.modemismatch = 1; + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); + } + + if (gintr_status.b.wkupintr) + { + retval |= DCD_HandleResume_ISR(pdev); + } + + if (gintr_status.b.usbsuspend) + { + retval |= DCD_HandleUSBSuspend_ISR(pdev); + } + if (gintr_status.b.sofintr) + { + retval |= DCD_HandleSof_ISR(pdev); + + } + + if (gintr_status.b.rxstsqlvl) + { + retval |= DCD_HandleRxStatusQueueLevel_ISR(pdev); + + } + + if (gintr_status.b.usbreset) + { + retval |= DCD_HandleUsbReset_ISR(pdev); + + } + if (gintr_status.b.enumdone) + { + retval |= DCD_HandleEnumDone_ISR(pdev); + } + + if (gintr_status.b.incomplisoin) + { + retval |= DCD_IsoINIncomplete_ISR(pdev); + } + + if (gintr_status.b.incomplisoout) + { + retval |= DCD_IsoOUTIncomplete_ISR(pdev); + } +#ifdef VBUS_SENSING_ENABLED + if (gintr_status.b.sessreqintr) + { + retval |= DCD_SessionRequest_ISR(pdev); + } + + if (gintr_status.b.otgintr) + { + retval |= DCD_OTG_ISR(pdev); + } +#endif + } + return retval; +} + +#ifdef VBUS_SENSING_ENABLED +/** +* @brief DCD_SessionRequest_ISR +* Indicates that the USB_OTG controller has detected a connection +* @param pdev: device instance +* @retval status +*/ +static uint32_t DCD_SessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_GINTSTS_TypeDef gintsts; + USBD_DCD_INT_fops->DevConnected (pdev); + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.sessreqintr = 1; + USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32); + return 1; +} + +/** +* @brief DCD_OTG_ISR +* Indicates that the USB_OTG controller has detected an OTG event: +* used to detect the end of session i.e. disconnection +* @param pdev: device instance +* @retval status +*/ +static uint32_t DCD_OTG_ISR(USB_OTG_CORE_HANDLE *pdev) +{ + + USB_OTG_GOTGINT_TypeDef gotgint; + + gotgint.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGINT); + + if (gotgint.b.sesenddet) + { + USBD_DCD_INT_fops->DevDisconnected (pdev); + } + /* Clear OTG interrupt */ + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGINT, gotgint.d32); + return 1; +} +#endif +/** +* @brief DCD_HandleResume_ISR +* Indicates that the USB_OTG controller has detected a resume or +* remote Wake-up sequence +* @param pdev: device instance +* @retval status +*/ +static uint32_t DCD_HandleResume_ISR(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_GINTSTS_TypeDef gintsts; + USB_OTG_DCTL_TypeDef devctl; + USB_OTG_PCGCCTL_TypeDef power; + + if(pdev->cfg.low_power) + { + /* un-gate USB Core clock */ + power.d32 = USB_OTG_READ_REG32(&pdev->regs.PCGCCTL); + power.b.gatehclk = 0; + power.b.stoppclk = 0; + USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32); + } + + /* Clear the Remote Wake-up Signaling */ + devctl.d32 = 0; + devctl.b.rmtwkupsig = 1; + USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, devctl.d32, 0); + + /* Inform upper layer by the Resume Event */ + USBD_DCD_INT_fops->Resume (pdev); + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.wkupintr = 1; + USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32); + return 1; +} + +/** +* @brief USB_OTG_HandleUSBSuspend_ISR +* Indicates that SUSPEND state has been detected on the USB +* @param pdev: device instance +* @retval status +*/ +static uint32_t DCD_HandleUSBSuspend_ISR(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_GINTSTS_TypeDef gintsts; + USB_OTG_PCGCCTL_TypeDef power; + USB_OTG_DSTS_TypeDef dsts; + __IO uint8_t prev_status = 0; + + prev_status = pdev->dev.device_status; + USBD_DCD_INT_fops->Suspend (pdev); + + dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.usbsuspend = 1; + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); + + if((pdev->cfg.low_power) && (dsts.b.suspsts == 1) && + (pdev->dev.connection_status == 1) && + (prev_status == USB_OTG_CONFIGURED)) + { + /* switch-off the clocks */ + power.d32 = 0; + power.b.stoppclk = 1; + USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, power.d32); + + power.b.gatehclk = 1; + USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, power.d32); + + /* Request to enter Sleep mode after exit from current ISR */ + SCB->SCR |= (SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk); + } + return 1; +} + +/** +* @brief DCD_HandleInEP_ISR +* Indicates that an IN EP has a pending Interrupt +* @param pdev: device instance +* @retval status +*/ +static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_DIEPINTn_TypeDef diepint; + + uint32_t ep_intr; + uint32_t epnum = 0; + uint32_t fifoemptymsk; + diepint.d32 = 0; + ep_intr = USB_OTG_ReadDevAllInEPItr(pdev); + + while ( ep_intr ) + { + if (ep_intr&0x1) /* In ITR */ + { + diepint.d32 = DCD_ReadDevInEP(pdev , epnum); /* Get In ITR status */ + if ( diepint.b.xfercompl ) + { + fifoemptymsk = 0x1 << epnum; + USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, fifoemptymsk, 0); + CLEAR_IN_EP_INTR(epnum, xfercompl); + /* TX COMPLETE */ + USBD_DCD_INT_fops->DataInStage(pdev , epnum); + + if (pdev->cfg.dma_enable == 1) + { + if((epnum == 0) && (pdev->dev.device_state == USB_OTG_EP0_STATUS_IN)) + { + /* prepare to rx more setup packets */ + USB_OTG_EP0_OutStart(pdev); + } + } + } + if ( diepint.b.timeout ) + { + CLEAR_IN_EP_INTR(epnum, timeout); + } + if (diepint.b.intktxfemp) + { + CLEAR_IN_EP_INTR(epnum, intktxfemp); + } + if (diepint.b.inepnakeff) + { + CLEAR_IN_EP_INTR(epnum, inepnakeff); + } + if ( diepint.b.epdisabled ) + { + CLEAR_IN_EP_INTR(epnum, epdisabled); + } + if (diepint.b.emptyintr) + { + + DCD_WriteEmptyTxFifo(pdev , epnum); + + CLEAR_IN_EP_INTR(epnum, emptyintr); + } + } + epnum++; + ep_intr >>= 1; + } + + return 1; +} + +/** +* @brief DCD_HandleOutEP_ISR +* Indicates that an OUT EP has a pending Interrupt +* @param pdev: device instance +* @retval status +*/ +static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev) +{ + uint32_t ep_intr; + USB_OTG_DOEPINTn_TypeDef doepint; + USB_OTG_DEPXFRSIZ_TypeDef deptsiz; + uint32_t epnum = 0; + + doepint.d32 = 0; + + /* Read in the device interrupt bits */ + ep_intr = USB_OTG_ReadDevAllOutEp_itr(pdev); + + while ( ep_intr ) + { + if (ep_intr&0x1) + { + + doepint.d32 = USB_OTG_ReadDevOutEP_itr(pdev, epnum); + + /* Transfer complete */ + if ( doepint.b.xfercompl ) + { + /* Clear the bit in DOEPINTn for this interrupt */ + CLEAR_OUT_EP_INTR(epnum, xfercompl); + if (pdev->cfg.dma_enable == 1) + { + deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[epnum]->DOEPTSIZ)); + /*ToDo : handle more than one single MPS size packet */ + pdev->dev.out_ep[epnum].xfer_count = pdev->dev.out_ep[epnum].maxpacket - \ + deptsiz.b.xfersize; + } + /* Inform upper layer: data ready */ + /* RX COMPLETE */ + USBD_DCD_INT_fops->DataOutStage(pdev , epnum); + + if (pdev->cfg.dma_enable == 1) + { + if((epnum == 0) && (pdev->dev.device_state == USB_OTG_EP0_STATUS_OUT)) + { + /* prepare to rx more setup packets */ + USB_OTG_EP0_OutStart(pdev); + } + } + } + /* Endpoint disable */ + if ( doepint.b.epdisabled ) + { + /* Clear the bit in DOEPINTn for this interrupt */ + CLEAR_OUT_EP_INTR(epnum, epdisabled); + } + /* Setup Phase Done (control EPs) */ + if ( doepint.b.setup ) + { + + /* inform the upper layer that a setup packet is available */ + /* SETUP COMPLETE */ + USBD_DCD_INT_fops->SetupStage(pdev); + CLEAR_OUT_EP_INTR(epnum, setup); + } + } + epnum++; + ep_intr >>= 1; + } + return 1; +} + +/** +* @brief DCD_HandleSof_ISR +* Handles the SOF Interrupts +* @param pdev: device instance +* @retval status +*/ +static uint32_t DCD_HandleSof_ISR(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_GINTSTS_TypeDef GINTSTS; + + + USBD_DCD_INT_fops->SOF(pdev); + + /* Clear interrupt */ + GINTSTS.d32 = 0; + GINTSTS.b.sofintr = 1; + USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, GINTSTS.d32); + + return 1; +} + +/** +* @brief DCD_HandleRxStatusQueueLevel_ISR +* Handles the Rx Status Queue Level Interrupt +* @param pdev: device instance +* @retval status +*/ +static uint32_t DCD_HandleRxStatusQueueLevel_ISR(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_GINTMSK_TypeDef int_mask; + USB_OTG_DRXSTS_TypeDef status; + USB_OTG_EP *ep; + + /* Disable the Rx Status Queue Level interrupt */ + int_mask.d32 = 0; + int_mask.b.rxstsqlvl = 1; + USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, int_mask.d32, 0); + + /* Get the Status from the top of the FIFO */ + status.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRXSTSP ); + + ep = &pdev->dev.out_ep[status.b.epnum]; + + switch (status.b.pktsts) + { + case STS_GOUT_NAK: + break; + case STS_DATA_UPDT: + if (status.b.bcnt) + { + USB_OTG_ReadPacket(pdev,ep->xfer_buff, status.b.bcnt); + ep->xfer_buff += status.b.bcnt; + ep->xfer_count += status.b.bcnt; + } + break; + case STS_XFER_COMP: + break; + case STS_SETUP_COMP: + break; + case STS_SETUP_UPDT: + /* Copy the setup packet received in FIFO into the setup buffer in RAM */ + USB_OTG_ReadPacket(pdev , pdev->dev.setup_packet, 8); + ep->xfer_count += status.b.bcnt; + break; + default: + break; + } + + /* Enable the Rx Status Queue Level interrupt */ + USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, int_mask.d32); + + return 1; +} + +/** +* @brief DCD_WriteEmptyTxFifo +* check FIFO for the next packet to be loaded +* @param pdev: device instance +* @retval status +*/ +static uint32_t DCD_WriteEmptyTxFifo(USB_OTG_CORE_HANDLE *pdev, uint32_t epnum) +{ + USB_OTG_DTXFSTSn_TypeDef txstatus; + USB_OTG_EP *ep; + uint32_t len = 0; + uint32_t len32b; + txstatus.d32 = 0; + + ep = &pdev->dev.in_ep[epnum]; + + len = ep->xfer_len - ep->xfer_count; + + if (len > ep->maxpacket) + { + len = ep->maxpacket; + } + + len32b = (len + 3) / 4; + txstatus.d32 = USB_OTG_READ_REG32( &pdev->regs.INEP_REGS[epnum]->DTXFSTS); + + + + while (txstatus.b.txfspcavail > len32b && + ep->xfer_count < ep->xfer_len && + ep->xfer_len != 0) + { + /* Write the FIFO */ + len = ep->xfer_len - ep->xfer_count; + + if (len > ep->maxpacket) + { + len = ep->maxpacket; + } + len32b = (len + 3) / 4; + + USB_OTG_WritePacket (pdev , ep->xfer_buff, epnum, len); + + ep->xfer_buff += len; + ep->xfer_count += len; + + txstatus.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[epnum]->DTXFSTS); + } + + return 1; +} + +/** +* @brief DCD_HandleUsbReset_ISR +* This interrupt occurs when a USB Reset is detected +* @param pdev: device instance +* @retval status +*/ +static uint32_t DCD_HandleUsbReset_ISR(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_DAINT_TypeDef daintmsk; + USB_OTG_DOEPMSK_TypeDef doepmsk; + USB_OTG_DIEPMSK_TypeDef diepmsk; + USB_OTG_DCFG_TypeDef dcfg; + USB_OTG_DCTL_TypeDef dctl; + USB_OTG_GINTSTS_TypeDef gintsts; + uint32_t i; + + dctl.d32 = 0; + daintmsk.d32 = 0; + doepmsk.d32 = 0; + diepmsk.d32 = 0; + dcfg.d32 = 0; + gintsts.d32 = 0; + + /* Clear the Remote Wake-up Signaling */ + dctl.b.rmtwkupsig = 1; + USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, 0 ); + + /* Flush the Tx FIFO */ + USB_OTG_FlushTxFifo(pdev , 0 ); + + for (i = 0; i < pdev->cfg.dev_endpoints ; i++) + { + USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF); + USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF); + } + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF ); + + daintmsk.ep.in = 1; + daintmsk.ep.out = 1; + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, daintmsk.d32 ); + + doepmsk.b.setup = 1; + doepmsk.b.xfercompl = 1; + doepmsk.b.epdisabled = 1; + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, doepmsk.d32 ); +#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOUTEP1MSK, doepmsk.d32 ); +#endif + diepmsk.b.xfercompl = 1; + diepmsk.b.timeout = 1; + diepmsk.b.epdisabled = 1; + + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, diepmsk.d32 ); +#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DINEP1MSK, diepmsk.d32 ); +#endif + /* Reset Device Address */ + dcfg.d32 = USB_OTG_READ_REG32( &pdev->regs.DREGS->DCFG); + dcfg.b.devaddr = 0; + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DCFG, dcfg.d32); + + + /* setup EP0 to receive SETUP packets */ + USB_OTG_EP0_OutStart(pdev); + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.usbreset = 1; + USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32); + + /*Reset internal state machine */ + USBD_DCD_INT_fops->Reset(pdev); + return 1; +} + +/** +* @brief DCD_HandleEnumDone_ISR +* Read the device status register and set the device speed +* @param pdev: device instance +* @retval status +*/ +static uint32_t DCD_HandleEnumDone_ISR(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_GINTSTS_TypeDef gintsts; + USB_OTG_GUSBCFG_TypeDef gusbcfg; + + USB_OTG_EP0Activate(pdev); + + /* Set USB turn-around time based on device speed and PHY interface. */ + gusbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); + + /* Full or High speed */ + if ( USB_OTG_GetDeviceSpeed(pdev) == USB_SPEED_HIGH) + { + pdev->cfg.speed = USB_OTG_SPEED_HIGH; + pdev->cfg.mps = USB_OTG_HS_MAX_PACKET_SIZE ; + gusbcfg.b.usbtrdtim = 9; + } + else + { + pdev->cfg.speed = USB_OTG_SPEED_FULL; + pdev->cfg.mps = USB_OTG_FS_MAX_PACKET_SIZE ; + gusbcfg.b.usbtrdtim = 5; + } + + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, gusbcfg.d32); + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.enumdone = 1; + USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, gintsts.d32 ); + return 1; +} + + +/** +* @brief DCD_IsoINIncomplete_ISR +* handle the ISO IN incomplete interrupt +* @param pdev: device instance +* @retval status +*/ +static uint32_t DCD_IsoINIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_GINTSTS_TypeDef gintsts; + + gintsts.d32 = 0; + + USBD_DCD_INT_fops->IsoINIncomplete (pdev); + + /* Clear interrupt */ + gintsts.b.incomplisoin = 1; + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); + + return 1; +} + +/** +* @brief DCD_IsoOUTIncomplete_ISR +* handle the ISO OUT incomplete interrupt +* @param pdev: device instance +* @retval status +*/ +static uint32_t DCD_IsoOUTIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_GINTSTS_TypeDef gintsts; + + gintsts.d32 = 0; + + USBD_DCD_INT_fops->IsoOUTIncomplete (pdev); + + /* Clear interrupt */ + gintsts.b.incomplisoout = 1; + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); + return 1; +} +/** +* @brief DCD_ReadDevInEP +* Reads ep flags +* @param pdev: device instance +* @retval status +*/ +static uint32_t DCD_ReadDevInEP (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum) +{ + uint32_t v, msk, emp; + msk = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPMSK); + emp = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPEMPMSK); + msk |= ((emp >> epnum) & 0x1) << 7; + v = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[epnum]->DIEPINT) & msk; + return v; +} + + + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/usb/usbd_core.c b/radio/bootloader/usb/usbd_core.c new file mode 100644 index 000000000..c09028eef --- /dev/null +++ b/radio/bootloader/usb/usbd_core.c @@ -0,0 +1,506 @@ +/** + ****************************************************************************** + * @file usbd_core.c + * @author MCD Application Team + * @version V1.1.0 + * @date 19-March-2012 + * @brief This file provides all the USBD core functions. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_core.h" +#include "usbd_req.h" +#include "usbd_ioreq.h" +#include "usb_dcd_int.h" +#include "usb_bsp.h" + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY +* @{ +*/ + + +/** @defgroup USBD_CORE +* @brief usbd core module +* @{ +*/ + +/** @defgroup USBD_CORE_Private_TypesDefinitions +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USBD_CORE_Private_Defines +* @{ +*/ + +/** +* @} +*/ + + +/** @defgroup USBD_CORE_Private_Macros +* @{ +*/ +/** +* @} +*/ + + + + +/** @defgroup USBD_CORE_Private_FunctionPrototypes +* @{ +*/ +static uint8_t USBD_SetupStage(USB_OTG_CORE_HANDLE *pdev); +static uint8_t USBD_DataOutStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); +static uint8_t USBD_DataInStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); +static uint8_t USBD_SOF(USB_OTG_CORE_HANDLE *pdev); +static uint8_t USBD_Reset(USB_OTG_CORE_HANDLE *pdev); +static uint8_t USBD_Suspend(USB_OTG_CORE_HANDLE *pdev); +static uint8_t USBD_Resume(USB_OTG_CORE_HANDLE *pdev); +#ifdef VBUS_SENSING_ENABLED +static uint8_t USBD_DevConnected(USB_OTG_CORE_HANDLE *pdev); +static uint8_t USBD_DevDisconnected(USB_OTG_CORE_HANDLE *pdev); +#endif +static uint8_t USBD_IsoINIncomplete(USB_OTG_CORE_HANDLE *pdev); +static uint8_t USBD_IsoOUTIncomplete(USB_OTG_CORE_HANDLE *pdev); +static uint8_t USBD_RunTestMode (USB_OTG_CORE_HANDLE *pdev) ; +/** +* @} +*/ + +/** @defgroup USBD_CORE_Private_Variables +* @{ +*/ + +__IO USB_OTG_DCTL_TypeDef SET_TEST_MODE; + +USBD_DCD_INT_cb_TypeDef USBD_DCD_INT_cb = +{ + USBD_DataOutStage, + USBD_DataInStage, + USBD_SetupStage, + USBD_SOF, + USBD_Reset, + USBD_Suspend, + USBD_Resume, + USBD_IsoINIncomplete, + USBD_IsoOUTIncomplete, +#ifdef VBUS_SENSING_ENABLED +USBD_DevConnected, +USBD_DevDisconnected, +#endif +}; + +USBD_DCD_INT_cb_TypeDef *USBD_DCD_INT_fops = &USBD_DCD_INT_cb; +/** +* @} +*/ + +/** @defgroup USBD_CORE_Private_Functions +* @{ +*/ + +/** +* @brief USBD_Init +* Initailizes the device stack and load the class driver +* @param pdev: device instance +* @param core_address: USB OTG core ID +* @param class_cb: Class callback structure address +* @param usr_cb: User callback structure address +* @retval None +*/ +void USBD_Init(USB_OTG_CORE_HANDLE *pdev, + USB_OTG_CORE_ID_TypeDef coreID, + USBD_DEVICE *pDevice, + USBD_Class_cb_TypeDef *class_cb, + USBD_Usr_cb_TypeDef *usr_cb) +{ + /* Hardware Init */ + USB_OTG_BSP_Init(pdev); + + USBD_DeInit(pdev); + + /*Register class and user callbacks */ + pdev->dev.class_cb = class_cb; + pdev->dev.usr_cb = usr_cb; + pdev->dev.usr_device = pDevice; + + /* set USB OTG core params */ + DCD_Init(pdev , coreID); + + /* Upon Init call usr callback */ + pdev->dev.usr_cb->Init(); + + /* Enable Interrupts */ + USB_OTG_BSP_EnableInterrupt(pdev); +} + +/** +* @brief USBD_DeInit +* Re-Initialize th device library +* @param pdev: device instance +* @retval status: status +*/ +USBD_Status USBD_DeInit(USB_OTG_CORE_HANDLE *pdev) +{ + /* Software Init */ + + return USBD_OK; +} + +/** +* @brief USBD_SetupStage +* Handle the setup stage +* @param pdev: device instance +* @retval status +*/ +static uint8_t USBD_SetupStage(USB_OTG_CORE_HANDLE *pdev) +{ + USB_SETUP_REQ req; + + USBD_ParseSetupRequest(pdev , &req); + + switch (req.bmRequest & 0x1F) + { + case USB_REQ_RECIPIENT_DEVICE: + USBD_StdDevReq (pdev, &req); + break; + + case USB_REQ_RECIPIENT_INTERFACE: + USBD_StdItfReq(pdev, &req); + break; + + case USB_REQ_RECIPIENT_ENDPOINT: + USBD_StdEPReq(pdev, &req); + break; + + default: + DCD_EP_Stall(pdev , req.bmRequest & 0x80); + break; + } + return USBD_OK; +} + +/** +* @brief USBD_DataOutStage +* Handle data out stage +* @param pdev: device instance +* @param epnum: endpoint index +* @retval status +*/ +static uint8_t USBD_DataOutStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) +{ + USB_OTG_EP *ep; + + if(epnum == 0) + { + ep = &pdev->dev.out_ep[0]; + if ( pdev->dev.device_state == USB_OTG_EP0_DATA_OUT) + { + if(ep->rem_data_len > ep->maxpacket) + { + ep->rem_data_len -= ep->maxpacket; + + if(pdev->cfg.dma_enable == 1) + { + /* in slave mode this, is handled by the RxSTSQLvl ISR */ + ep->xfer_buff += ep->maxpacket; + } + USBD_CtlContinueRx (pdev, + ep->xfer_buff, + MIN(ep->rem_data_len ,ep->maxpacket)); + } + else + { + if((pdev->dev.class_cb->EP0_RxReady != NULL)&& + (pdev->dev.device_status == USB_OTG_CONFIGURED)) + { + pdev->dev.class_cb->EP0_RxReady(pdev); + } + USBD_CtlSendStatus(pdev); + } + } + } + else if((pdev->dev.class_cb->DataOut != NULL)&& + (pdev->dev.device_status == USB_OTG_CONFIGURED)) + { + pdev->dev.class_cb->DataOut(pdev, epnum); + } + return USBD_OK; +} + +/** +* @brief USBD_DataInStage +* Handle data in stage +* @param pdev: device instance +* @param epnum: endpoint index +* @retval status +*/ +static uint8_t USBD_DataInStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) +{ + USB_OTG_EP *ep; + + if(epnum == 0) + { + ep = &pdev->dev.in_ep[0]; + if ( pdev->dev.device_state == USB_OTG_EP0_DATA_IN) + { + if(ep->rem_data_len > ep->maxpacket) + { + ep->rem_data_len -= ep->maxpacket; + if(pdev->cfg.dma_enable == 1) + { + /* in slave mode this, is handled by the TxFifoEmpty ISR */ + ep->xfer_buff += ep->maxpacket; + } + USBD_CtlContinueSendData (pdev, + ep->xfer_buff, + ep->rem_data_len); + } + else + { /* last packet is MPS multiple, so send ZLP packet */ + if((ep->total_data_len % ep->maxpacket == 0) && + (ep->total_data_len >= ep->maxpacket) && + (ep->total_data_len < ep->ctl_data_len )) + { + + USBD_CtlContinueSendData(pdev , NULL, 0); + ep->ctl_data_len = 0; + } + else + { + if((pdev->dev.class_cb->EP0_TxSent != NULL)&& + (pdev->dev.device_status == USB_OTG_CONFIGURED)) + { + pdev->dev.class_cb->EP0_TxSent(pdev); + } + USBD_CtlReceiveStatus(pdev); + } + } + } + if (pdev->dev.test_mode == 1) + { + USBD_RunTestMode(pdev); + pdev->dev.test_mode = 0; + } + } + else if((pdev->dev.class_cb->DataIn != NULL)&& + (pdev->dev.device_status == USB_OTG_CONFIGURED)) + { + pdev->dev.class_cb->DataIn(pdev, epnum); + } + return USBD_OK; +} + + + + +/** +* @brief USBD_RunTestMode +* Launch test mode process +* @param pdev: device instance +* @retval status +*/ +static uint8_t USBD_RunTestMode (USB_OTG_CORE_HANDLE *pdev) +{ + USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, SET_TEST_MODE.d32); + return USBD_OK; +} + +/** +* @brief USBD_Reset +* Handle Reset event +* @param pdev: device instance +* @retval status +*/ + +static uint8_t USBD_Reset(USB_OTG_CORE_HANDLE *pdev) +{ + /* Open EP0 OUT */ + DCD_EP_Open(pdev, + 0x00, + USB_OTG_MAX_EP0_SIZE, + EP_TYPE_CTRL); + + /* Open EP0 IN */ + DCD_EP_Open(pdev, + 0x80, + USB_OTG_MAX_EP0_SIZE, + EP_TYPE_CTRL); + + /* Upon Reset call usr call back */ + pdev->dev.device_status = USB_OTG_DEFAULT; + pdev->dev.usr_cb->DeviceReset(pdev->cfg.speed); + + return USBD_OK; +} + +/** +* @brief USBD_Resume +* Handle Resume event +* @param pdev: device instance +* @retval status +*/ + +static uint8_t USBD_Resume(USB_OTG_CORE_HANDLE *pdev) +{ + /* Upon Resume call usr call back */ + pdev->dev.usr_cb->DeviceResumed(); + pdev->dev.device_status = pdev->dev.device_old_status; + pdev->dev.device_status = USB_OTG_CONFIGURED; + return USBD_OK; +} + + +/** +* @brief USBD_Suspend +* Handle Suspend event +* @param pdev: device instance +* @retval status +*/ + +static uint8_t USBD_Suspend(USB_OTG_CORE_HANDLE *pdev) +{ + pdev->dev.device_old_status = pdev->dev.device_status; + pdev->dev.device_status = USB_OTG_SUSPENDED; + /* Upon Resume call usr call back */ + pdev->dev.usr_cb->DeviceSuspended(); + return USBD_OK; +} + + +/** +* @brief USBD_SOF +* Handle SOF event +* @param pdev: device instance +* @retval status +*/ + +static uint8_t USBD_SOF(USB_OTG_CORE_HANDLE *pdev) +{ + if(pdev->dev.class_cb->SOF) + { + pdev->dev.class_cb->SOF(pdev); + } + return USBD_OK; +} +/** +* @brief USBD_SetCfg +* Configure device and start the interface +* @param pdev: device instance +* @param cfgidx: configuration index +* @retval status +*/ + +USBD_Status USBD_SetCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx) +{ + pdev->dev.class_cb->Init(pdev, cfgidx); + + /* Upon set config call usr call back */ + pdev->dev.usr_cb->DeviceConfigured(); + return USBD_OK; +} + +/** +* @brief USBD_ClrCfg +* Clear current configuration +* @param pdev: device instance +* @param cfgidx: configuration index +* @retval status: USBD_Status +*/ +USBD_Status USBD_ClrCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx) +{ + pdev->dev.class_cb->DeInit(pdev, cfgidx); + return USBD_OK; +} + +/** +* @brief USBD_IsoINIncomplete +* Handle iso in incomplete event +* @param pdev: device instance +* @retval status +*/ +static uint8_t USBD_IsoINIncomplete(USB_OTG_CORE_HANDLE *pdev) +{ + pdev->dev.class_cb->IsoINIncomplete(pdev); + return USBD_OK; +} + +/** +* @brief USBD_IsoOUTIncomplete +* Handle iso out incomplete event +* @param pdev: device instance +* @retval status +*/ +static uint8_t USBD_IsoOUTIncomplete(USB_OTG_CORE_HANDLE *pdev) +{ + pdev->dev.class_cb->IsoOUTIncomplete(pdev); + return USBD_OK; +} + +#ifdef VBUS_SENSING_ENABLED +/** +* @brief USBD_DevConnected +* Handle device connection event +* @param pdev: device instance +* @retval status +*/ +static uint8_t USBD_DevConnected(USB_OTG_CORE_HANDLE *pdev) +{ + pdev->dev.usr_cb->DeviceConnected(); + pdev->dev.connection_status = 1; + return USBD_OK; +} + +/** +* @brief USBD_DevDisconnected +* Handle device disconnection event +* @param pdev: device instance +* @retval status +*/ +static uint8_t USBD_DevDisconnected(USB_OTG_CORE_HANDLE *pdev) +{ + pdev->dev.usr_cb->DeviceDisconnected(); + pdev->dev.class_cb->DeInit(pdev, 0); + pdev->dev.connection_status = 0; + return USBD_OK; +} +#endif +/** +* @} +*/ + + +/** +* @} +*/ + + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/bootloader/usb/usbd_desc.c b/radio/bootloader/usb/usbd_desc.c new file mode 100644 index 000000000..373203498 --- /dev/null +++ b/radio/bootloader/usb/usbd_desc.c @@ -0,0 +1,223 @@ +/** + ****************************************************************************** + * @file usbd_desc.c + * @author MCD Application Team + * @version V1.1.0 + * @date 19-March-2012 + * @brief This file provides the USBD descriptors and string formating method. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_core.h" +#include "usbd_desc.h" +#include "usbd_req.h" +#include "usbd_conf.h" +#include "usb_regs.h" + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup USBD_DESC + * @brief USBD descriptors module + * @{ + */ + +/** @defgroup USBD_DESC_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_DESC_Private_Defines + * @{ + */ + +#define USBD_VID 0x0483 +#define USBD_PID 0x5720 + +#define USBD_LANGID_STRING 0x409 +#define USBD_MANUFACTURER_STRING "FrSky" + +#define USBD_PRODUCT_FS_STRING "FrSky Taranis Mass Storage" +#define USBD_SERIALNUMBER_FS_STRING "00000000001B" +#define USBD_CONFIGURATION_FS_STRING "MSC Config" +#define USBD_INTERFACE_FS_STRING "MSC Interface" + +USBD_DEVICE USR_desc = +{ + USBD_USR_DeviceDescriptor, + USBD_USR_LangIDStrDescriptor, + USBD_USR_ManufacturerStrDescriptor, + USBD_USR_ProductStrDescriptor, + USBD_USR_SerialStrDescriptor, + USBD_USR_ConfigStrDescriptor, + USBD_USR_InterfaceStrDescriptor, +}; + +/* USB Standard Device Descriptor */ +__ALIGN_BEGIN uint8_t USBD_DeviceDesc[USB_SIZ_DEVICE_DESC] __ALIGN_END = + { + 0x12, /*bLength */ + USB_DEVICE_DESCRIPTOR_TYPE, /*bDescriptorType*/ + 0x00, /*bcdUSB */ + 0x02, + 0x00, /*bDeviceClass*/ + 0x00, /*bDeviceSubClass*/ + 0x00, /*bDeviceProtocol*/ + USB_OTG_MAX_EP0_SIZE, /*bMaxPacketSize*/ + LOBYTE(USBD_VID), /*idVendor*/ + HIBYTE(USBD_VID), /*idVendor*/ + LOBYTE(USBD_PID), /*idVendor*/ + HIBYTE(USBD_PID), /*idVendor*/ + 0x00, /*bcdDevice rel. 2.00*/ + 0x02, + USBD_IDX_MFC_STR, /*Index of manufacturer string*/ + USBD_IDX_PRODUCT_STR, /*Index of product string*/ + USBD_IDX_SERIAL_STR, /*Index of serial number string*/ + USBD_CFG_MAX_NUM /*bNumConfigurations*/ + } ; /* USB_DeviceDescriptor */ + +/* USB Standard Device Descriptor */ +__ALIGN_BEGIN uint8_t USBD_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END = +{ + USB_LEN_DEV_QUALIFIER_DESC, + USB_DESC_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x01, + 0x00, +}; + +/* USB Standard Device Descriptor */ +__ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_SIZ_STRING_LANGID] __ALIGN_END = +{ + USB_SIZ_STRING_LANGID, + USB_DESC_TYPE_STRING, + LOBYTE(USBD_LANGID_STRING), + HIBYTE(USBD_LANGID_STRING), +}; + +/* +* @brief USBD_USR_DeviceDescriptor +* return the device descriptor +* @param speed : current device speed +* @param length : pointer to data length variable +* @retval pointer to descriptor buffer +*/ +uint8_t * USBD_USR_DeviceDescriptor( uint8_t speed , uint16_t *length) +{ + *length = sizeof(USBD_DeviceDesc); + return USBD_DeviceDesc; +} + +/** +* @brief USBD_USR_LangIDStrDescriptor +* return the LangID string descriptor +* @param speed : current device speed +* @param length : pointer to data length variable +* @retval pointer to descriptor buffer +*/ +uint8_t * USBD_USR_LangIDStrDescriptor( uint8_t speed , uint16_t *length) +{ + *length = sizeof(USBD_LangIDDesc); + return USBD_LangIDDesc; +} + + +/** +* @brief USBD_USR_ProductStrDescriptor +* return the product string descriptor +* @param speed : current device speed +* @param length : pointer to data length variable +* @retval pointer to descriptor buffer +*/ +uint8_t * USBD_USR_ProductStrDescriptor( uint8_t speed , uint16_t *length) +{ + + USBD_GetString ((uint8_t*)USBD_PRODUCT_FS_STRING, USBD_StrDesc, length); + + return USBD_StrDesc; +} + +/** +* @brief USBD_USR_ManufacturerStrDescriptor +* return the manufacturer string descriptor +* @param speed : current device speed +* @param length : pointer to data length variable +* @retval pointer to descriptor buffer +*/ +uint8_t * USBD_USR_ManufacturerStrDescriptor( uint8_t speed , uint16_t *length) +{ + USBD_GetString ((uint8_t*)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); + return USBD_StrDesc; +} + +/** +* @brief USBD_USR_SerialStrDescriptor +* return the serial number string descriptor +* @param speed : current device speed +* @param length : pointer to data length variable +* @retval pointer to descriptor buffer +*/ +uint8_t * USBD_USR_SerialStrDescriptor( uint8_t speed , uint16_t *length) +{ + USBD_GetString ((uint8_t*)USBD_SERIALNUMBER_FS_STRING, USBD_StrDesc, length); + + return USBD_StrDesc; +} + +/** +* @brief USBD_USR_ConfigStrDescriptor +* return the configuration string descriptor +* @param speed : current device speed +* @param length : pointer to data length variable +* @retval pointer to descriptor buffer +*/ +uint8_t * USBD_USR_ConfigStrDescriptor( uint8_t speed , uint16_t *length) +{ + USBD_GetString ((uint8_t *)USBD_CONFIGURATION_FS_STRING, USBD_StrDesc, length); + return USBD_StrDesc; +} + + +/** +* @brief USBD_USR_InterfaceStrDescriptor +* return the interface string descriptor +* @param speed : current device speed +* @param length : pointer to data length variable +* @retval pointer to descriptor buffer +*/ +uint8_t * USBD_USR_InterfaceStrDescriptor( uint8_t speed , uint16_t *length) +{ + USBD_GetString ((uint8_t*)USBD_INTERFACE_FS_STRING, USBD_StrDesc, length); + return USBD_StrDesc; +} + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/bootloader/usb/usbd_ioreq.c b/radio/bootloader/usb/usbd_ioreq.c new file mode 100644 index 000000000..139a86a9e --- /dev/null +++ b/radio/bootloader/usb/usbd_ioreq.c @@ -0,0 +1,244 @@ +/** + ****************************************************************************** + * @file usbd_ioreq.c + * @author MCD Application Team + * @version V1.1.0 + * @date 19-March-2012 + * @brief This file provides the IO requests APIs for control endpoints. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_ioreq.h" + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup USBD_IOREQ + * @brief control I/O requests module + * @{ + */ + +/** @defgroup USBD_IOREQ_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_Defines + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_Variables + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_FunctionPrototypes + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_Functions + * @{ + */ + +/** +* @brief USBD_CtlSendData +* send data on the ctl pipe +* @param pdev: device instance +* @param buff: pointer to data buffer +* @param len: length of data to be sent +* @retval status +*/ +USBD_Status USBD_CtlSendData (USB_OTG_CORE_HANDLE *pdev, + uint8_t *pbuf, + uint16_t len) +{ + USBD_Status ret = USBD_OK; + + pdev->dev.in_ep[0].total_data_len = len; + pdev->dev.in_ep[0].rem_data_len = len; + pdev->dev.device_state = USB_OTG_EP0_DATA_IN; + + DCD_EP_Tx (pdev, 0, pbuf, len); + + return ret; +} + +/** +* @brief USBD_CtlContinueSendData +* continue sending data on the ctl pipe +* @param pdev: device instance +* @param buff: pointer to data buffer +* @param len: length of data to be sent +* @retval status +*/ +USBD_Status USBD_CtlContinueSendData (USB_OTG_CORE_HANDLE *pdev, + uint8_t *pbuf, + uint16_t len) +{ + USBD_Status ret = USBD_OK; + + DCD_EP_Tx (pdev, 0, pbuf, len); + + + return ret; +} + +/** +* @brief USBD_CtlPrepareRx +* receive data on the ctl pipe +* @param pdev: USB OTG device instance +* @param buff: pointer to data buffer +* @param len: length of data to be received +* @retval status +*/ +USBD_Status USBD_CtlPrepareRx (USB_OTG_CORE_HANDLE *pdev, + uint8_t *pbuf, + uint16_t len) +{ + USBD_Status ret = USBD_OK; + + pdev->dev.out_ep[0].total_data_len = len; + pdev->dev.out_ep[0].rem_data_len = len; + pdev->dev.device_state = USB_OTG_EP0_DATA_OUT; + + DCD_EP_PrepareRx (pdev, + 0, + pbuf, + len); + + + return ret; +} + +/** +* @brief USBD_CtlContinueRx +* continue receive data on the ctl pipe +* @param pdev: USB OTG device instance +* @param buff: pointer to data buffer +* @param len: length of data to be received +* @retval status +*/ +USBD_Status USBD_CtlContinueRx (USB_OTG_CORE_HANDLE *pdev, + uint8_t *pbuf, + uint16_t len) +{ + USBD_Status ret = USBD_OK; + + DCD_EP_PrepareRx (pdev, + 0, + pbuf, + len); + return ret; +} +/** +* @brief USBD_CtlSendStatus +* send zero lzngth packet on the ctl pipe +* @param pdev: USB OTG device instance +* @retval status +*/ +USBD_Status USBD_CtlSendStatus (USB_OTG_CORE_HANDLE *pdev) +{ + USBD_Status ret = USBD_OK; + pdev->dev.device_state = USB_OTG_EP0_STATUS_IN; + DCD_EP_Tx (pdev, + 0, + NULL, + 0); + + USB_OTG_EP0_OutStart(pdev); + + return ret; +} + +/** +* @brief USBD_CtlReceiveStatus +* receive zero lzngth packet on the ctl pipe +* @param pdev: USB OTG device instance +* @retval status +*/ +USBD_Status USBD_CtlReceiveStatus (USB_OTG_CORE_HANDLE *pdev) +{ + USBD_Status ret = USBD_OK; + pdev->dev.device_state = USB_OTG_EP0_STATUS_OUT; + DCD_EP_PrepareRx ( pdev, + 0, + NULL, + 0); + + USB_OTG_EP0_OutStart(pdev); + + return ret; +} + + +/** +* @brief USBD_GetRxCount +* returns the received data length +* @param pdev: USB OTG device instance +* epnum: endpoint index +* @retval Rx Data blength +*/ +uint16_t USBD_GetRxCount (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) +{ + return pdev->dev.out_ep[epnum].xfer_count; +} + +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/usb/usbd_msc_bot.c b/radio/bootloader/usb/usbd_msc_bot.c new file mode 100644 index 000000000..227aa6e2d --- /dev/null +++ b/radio/bootloader/usb/usbd_msc_bot.c @@ -0,0 +1,400 @@ +/** + ****************************************************************************** + * @file usbd_msc_bot.c + * @author MCD Application Team + * @version V1.1.0 + * @date 19-March-2012 + * @brief This file provides all the BOT protocol core functions. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_msc_bot.h" +#include "usbd_msc_scsi.h" +#include "usbd_ioreq.h" +#include "usbd_msc_mem.h" + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup MSC_BOT + * @brief BOT protocol module + * @{ + */ + +/** @defgroup MSC_BOT_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup MSC_BOT_Private_Defines + * @{ + */ + +/** + * @} + */ + + +/** @defgroup MSC_BOT_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup MSC_BOT_Private_Variables + * @{ + */ +uint16_t MSC_BOT_DataLen; +uint8_t MSC_BOT_State; +uint8_t MSC_BOT_Status; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint8_t MSC_BOT_Data[MSC_MEDIA_PACKET] __ALIGN_END ; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN MSC_BOT_CBW_TypeDef MSC_BOT_cbw __ALIGN_END ; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN MSC_BOT_CSW_TypeDef MSC_BOT_csw __ALIGN_END ; +/** + * @} + */ + + +/** @defgroup MSC_BOT_Private_FunctionPrototypes + * @{ + */ +static void MSC_BOT_CBW_Decode (USB_OTG_CORE_HANDLE *pdev); + +static void MSC_BOT_SendData (USB_OTG_CORE_HANDLE *pdev, + uint8_t* pbuf, + uint16_t len); + +static void MSC_BOT_Abort(USB_OTG_CORE_HANDLE *pdev); +/** + * @} + */ + + +/** @defgroup MSC_BOT_Private_Functions + * @{ + */ + + + +/** +* @brief MSC_BOT_Init +* Initialize the BOT Process +* @param pdev: device instance +* @retval None +*/ +void MSC_BOT_Init (USB_OTG_CORE_HANDLE *pdev) +{ + MSC_BOT_State = BOT_IDLE; + MSC_BOT_Status = BOT_STATE_NORMAL; + USBD_STORAGE_fops->Init(0); + + DCD_EP_Flush(pdev, MSC_OUT_EP); + DCD_EP_Flush(pdev, MSC_IN_EP); + /* Prapare EP to Receive First BOT Cmd */ + DCD_EP_PrepareRx (pdev, + MSC_OUT_EP, + (uint8_t *)&MSC_BOT_cbw, + BOT_CBW_LENGTH); +} + +/** +* @brief MSC_BOT_Reset +* Reset the BOT Machine +* @param pdev: device instance +* @retval None +*/ +void MSC_BOT_Reset (USB_OTG_CORE_HANDLE *pdev) +{ + MSC_BOT_State = BOT_IDLE; + MSC_BOT_Status = BOT_STATE_RECOVERY; + /* Prapare EP to Receive First BOT Cmd */ + DCD_EP_PrepareRx (pdev, + MSC_OUT_EP, + (uint8_t *)&MSC_BOT_cbw, + BOT_CBW_LENGTH); +} + +/** +* @brief MSC_BOT_DeInit +* Uninitialize the BOT Machine +* @param pdev: device instance +* @retval None +*/ +void MSC_BOT_DeInit (USB_OTG_CORE_HANDLE *pdev) +{ + MSC_BOT_State = BOT_IDLE; +} + +/** +* @brief MSC_BOT_DataIn +* Handle BOT IN data stage +* @param pdev: device instance +* @param epnum: endpoint index +* @retval None +*/ +void MSC_BOT_DataIn (USB_OTG_CORE_HANDLE *pdev, + uint8_t epnum) +{ + + switch (MSC_BOT_State) + { + case BOT_DATA_IN: + if(SCSI_ProcessCmd(pdev, + MSC_BOT_cbw.bLUN, + &MSC_BOT_cbw.CB[0]) < 0) + { + MSC_BOT_SendCSW (pdev, CSW_CMD_FAILED); + } + break; + + case BOT_SEND_DATA: + case BOT_LAST_DATA_IN: + MSC_BOT_SendCSW (pdev, CSW_CMD_PASSED); + + break; + + default: + break; + } +} +/** +* @brief MSC_BOT_DataOut +* Proccess MSC OUT data +* @param pdev: device instance +* @param epnum: endpoint index +* @retval None +*/ +void MSC_BOT_DataOut (USB_OTG_CORE_HANDLE *pdev, + uint8_t epnum) +{ + switch (MSC_BOT_State) + { + case BOT_IDLE: + MSC_BOT_CBW_Decode(pdev); + break; + + case BOT_DATA_OUT: + + if(SCSI_ProcessCmd(pdev, + MSC_BOT_cbw.bLUN, + &MSC_BOT_cbw.CB[0]) < 0) + { + MSC_BOT_SendCSW (pdev, CSW_CMD_FAILED); + } + + break; + + default: + break; + } + +} + +/** +* @brief MSC_BOT_CBW_Decode +* Decode the CBW command and set the BOT state machine accordingtly +* @param pdev: device instance +* @retval None +*/ +static void MSC_BOT_CBW_Decode (USB_OTG_CORE_HANDLE *pdev) +{ + + MSC_BOT_csw.dTag = MSC_BOT_cbw.dTag; + MSC_BOT_csw.dDataResidue = MSC_BOT_cbw.dDataLength; + + if ((USBD_GetRxCount (pdev ,MSC_OUT_EP) != BOT_CBW_LENGTH) || + (MSC_BOT_cbw.dSignature != BOT_CBW_SIGNATURE)|| + (MSC_BOT_cbw.bLUN > 1) || + (MSC_BOT_cbw.bCBLength < 1) || + (MSC_BOT_cbw.bCBLength > 16)) + { + + SCSI_SenseCode(MSC_BOT_cbw.bLUN, + ILLEGAL_REQUEST, + INVALID_CDB); + MSC_BOT_Status = BOT_STATE_ERROR; + MSC_BOT_Abort(pdev); + + } + else + { + if(SCSI_ProcessCmd(pdev, + MSC_BOT_cbw.bLUN, + &MSC_BOT_cbw.CB[0]) < 0) + { + MSC_BOT_Abort(pdev); + } + /*Burst xfer handled internally*/ + else if ((MSC_BOT_State != BOT_DATA_IN) && + (MSC_BOT_State != BOT_DATA_OUT) && + (MSC_BOT_State != BOT_LAST_DATA_IN)) + { + if (MSC_BOT_DataLen > 0) + { + MSC_BOT_SendData(pdev, + MSC_BOT_Data, + MSC_BOT_DataLen); + } + else if (MSC_BOT_DataLen == 0) + { + MSC_BOT_SendCSW (pdev, + CSW_CMD_PASSED); + } + } + } +} + +/** +* @brief MSC_BOT_SendData +* Send the requested data +* @param pdev: device instance +* @param buf: pointer to data buffer +* @param len: Data Length +* @retval None +*/ +static void MSC_BOT_SendData(USB_OTG_CORE_HANDLE *pdev, + uint8_t* buf, + uint16_t len) +{ + + len = MIN (MSC_BOT_cbw.dDataLength, len); + MSC_BOT_csw.dDataResidue -= len; + MSC_BOT_csw.bStatus = CSW_CMD_PASSED; + MSC_BOT_State = BOT_SEND_DATA; + + DCD_EP_Tx (pdev, MSC_IN_EP, buf, len); +} + +/** +* @brief MSC_BOT_SendCSW +* Send the Command Status Wrapper +* @param pdev: device instance +* @param status : CSW status +* @retval None +*/ +void MSC_BOT_SendCSW (USB_OTG_CORE_HANDLE *pdev, + uint8_t CSW_Status) +{ + MSC_BOT_csw.dSignature = BOT_CSW_SIGNATURE; + MSC_BOT_csw.bStatus = CSW_Status; + MSC_BOT_State = BOT_IDLE; + + DCD_EP_Tx (pdev, + MSC_IN_EP, + (uint8_t *)&MSC_BOT_csw, + BOT_CSW_LENGTH); + + /* Prapare EP to Receive next Cmd */ + DCD_EP_PrepareRx (pdev, + MSC_OUT_EP, + (uint8_t *)&MSC_BOT_cbw, + BOT_CBW_LENGTH); + +} + +/** +* @brief MSC_BOT_Abort +* Abort the current transfer +* @param pdev: device instance +* @retval status +*/ + +static void MSC_BOT_Abort (USB_OTG_CORE_HANDLE *pdev) +{ + + if ((MSC_BOT_cbw.bmFlags == 0) && + (MSC_BOT_cbw.dDataLength != 0) && + (MSC_BOT_Status == BOT_STATE_NORMAL) ) + { + DCD_EP_Stall(pdev, MSC_OUT_EP ); + } + DCD_EP_Stall(pdev, MSC_IN_EP); + + if(MSC_BOT_Status == BOT_STATE_ERROR) + { + DCD_EP_PrepareRx (pdev, + MSC_OUT_EP, + (uint8_t *)&MSC_BOT_cbw, + BOT_CBW_LENGTH); + } +} + +/** +* @brief MSC_BOT_CplClrFeature +* Complete the clear feature request +* @param pdev: device instance +* @param epnum: endpoint index +* @retval None +*/ + +void MSC_BOT_CplClrFeature (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum) +{ + if(MSC_BOT_Status == BOT_STATE_ERROR )/* Bad CBW Signature */ + { + DCD_EP_Stall(pdev, MSC_IN_EP); + MSC_BOT_Status = BOT_STATE_NORMAL; + } + else if(((epnum & 0x80) == 0x80) && ( MSC_BOT_Status != BOT_STATE_RECOVERY)) + { + MSC_BOT_SendCSW (pdev, CSW_CMD_FAILED); + } + +} +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/usb/usbd_msc_core.c b/radio/bootloader/usb/usbd_msc_core.c new file mode 100644 index 000000000..5d8d4e815 --- /dev/null +++ b/radio/bootloader/usb/usbd_msc_core.c @@ -0,0 +1,496 @@ +/** + ****************************************************************************** + * @file usbd_msc_core.c + * @author MCD Application Team + * @version V1.1.0 + * @date 19-March-2012 + * @brief This file provides all the MSC core functions. + * + * @verbatim + * + * =================================================================== + * MSC Class Description + * =================================================================== + * This module manages the MSC class V1.0 following the "Universal + * Serial Bus Mass Storage Class (MSC) Bulk-Only Transport (BOT) Version 1.0 + * Sep. 31, 1999". + * This driver implements the following aspects of the specification: + * - Bulk-Only Transport protocol + * - Subclass : SCSI transparent command set (ref. SCSI Primary Commands - 3 (SPC-3)) + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_msc_mem.h" +#include "usbd_msc_core.h" +#include "usbd_msc_bot.h" +#include "usbd_req.h" + + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup MSC_CORE + * @brief Mass storage core module + * @{ + */ + +/** @defgroup MSC_CORE_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup MSC_CORE_Private_Defines + * @{ + */ + +/** + * @} + */ + + +/** @defgroup MSC_CORE_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup MSC_CORE_Private_FunctionPrototypes + * @{ + */ +uint8_t USBD_MSC_Init (void *pdev, + uint8_t cfgidx); + +uint8_t USBD_MSC_DeInit (void *pdev, + uint8_t cfgidx); + +uint8_t USBD_MSC_Setup (void *pdev, + USB_SETUP_REQ *req); + +uint8_t USBD_MSC_DataIn (void *pdev, + uint8_t epnum); + + +uint8_t USBD_MSC_DataOut (void *pdev, + uint8_t epnum); + +uint8_t *USBD_MSC_GetCfgDesc (uint8_t speed, + uint16_t *length); + +#ifdef USB_OTG_HS_CORE +uint8_t *USBD_MSC_GetOtherCfgDesc (uint8_t speed, + uint16_t *length); +#endif + + +uint8_t USBD_MSC_CfgDesc[USB_MSC_CONFIG_DESC_SIZ]; + + + + +/** + * @} + */ + + +/** @defgroup MSC_CORE_Private_Variables + * @{ + */ + + +USBD_Class_cb_TypeDef USBD_MSC_cb = +{ + USBD_MSC_Init, + USBD_MSC_DeInit, + USBD_MSC_Setup, + NULL, /*EP0_TxSent*/ + NULL, /*EP0_RxReady*/ + USBD_MSC_DataIn, + USBD_MSC_DataOut, + NULL, /*SOF */ + NULL, + NULL, + USBD_MSC_GetCfgDesc, +#ifdef USB_OTG_HS_CORE + USBD_MSC_GetOtherCfgDesc, +#endif +}; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +/* USB Mass storage device Configuration Descriptor */ +/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */ +__ALIGN_BEGIN uint8_t USBD_MSC_CfgDesc[USB_MSC_CONFIG_DESC_SIZ] __ALIGN_END = +{ + + 0x09, /* bLength: Configuation Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + USB_MSC_CONFIG_DESC_SIZ, + + 0x00, + 0x01, /* bNumInterfaces: 1 interface */ + 0x01, /* bConfigurationValue: */ + 0x04, /* iConfiguration: */ + 0xC0, /* bmAttributes: */ + 0x32, /* MaxPower 100 mA */ + + /******************** Mass Storage interface ********************/ + 0x09, /* bLength: Interface Descriptor size */ + 0x04, /* bDescriptorType: */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints*/ + 0x08, /* bInterfaceClass: MSC Class */ + 0x06, /* bInterfaceSubClass : SCSI transparent*/ + 0x50, /* nInterfaceProtocol */ + 0x05, /* iInterface: */ + /******************** Mass Storage Endpoints ********************/ + 0x07, /*Endpoint descriptor length = 7*/ + 0x05, /*Endpoint descriptor type */ + MSC_IN_EP, /*Endpoint address (IN, address 1) */ + 0x02, /*Bulk endpoint type */ + LOBYTE(MSC_MAX_PACKET), + HIBYTE(MSC_MAX_PACKET), + 0x00, /*Polling interval in milliseconds */ + + 0x07, /*Endpoint descriptor length = 7 */ + 0x05, /*Endpoint descriptor type */ + MSC_OUT_EP, /*Endpoint address (OUT, address 1) */ + 0x02, /*Bulk endpoint type */ + LOBYTE(MSC_MAX_PACKET), + HIBYTE(MSC_MAX_PACKET), + 0x00 /*Polling interval in milliseconds*/ +}; +#ifdef USB_OTG_HS_CORE + #ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif + #endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint8_t USBD_MSC_OtherCfgDesc[USB_MSC_CONFIG_DESC_SIZ] __ALIGN_END = +{ + + 0x09, /* bLength: Configuation Descriptor size */ + USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, + USB_MSC_CONFIG_DESC_SIZ, + + 0x00, + 0x01, /* bNumInterfaces: 1 interface */ + 0x01, /* bConfigurationValue: */ + 0x04, /* iConfiguration: */ + 0xC0, /* bmAttributes: */ + 0x32, /* MaxPower 100 mA */ + + /******************** Mass Storage interface ********************/ + 0x09, /* bLength: Interface Descriptor size */ + 0x04, /* bDescriptorType: */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints*/ + 0x08, /* bInterfaceClass: MSC Class */ + 0x06, /* bInterfaceSubClass : SCSI transparent command set*/ + 0x50, /* nInterfaceProtocol */ + 0x05, /* iInterface: */ + /******************** Mass Storage Endpoints ********************/ + 0x07, /*Endpoint descriptor length = 7*/ + 0x05, /*Endpoint descriptor type */ + MSC_IN_EP, /*Endpoint address (IN, address 1) */ + 0x02, /*Bulk endpoint type */ + 0x40, + 0x00, + 0x00, /*Polling interval in milliseconds */ + + 0x07, /*Endpoint descriptor length = 7 */ + 0x05, /*Endpoint descriptor type */ + MSC_OUT_EP, /*Endpoint address (OUT, address 1) */ + 0x02, /*Bulk endpoint type */ + 0x40, + 0x00, + 0x00 /*Polling interval in milliseconds*/ +}; +#endif + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN static uint8_t USBD_MSC_MaxLun __ALIGN_END = 0; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN static uint8_t USBD_MSC_AltSet __ALIGN_END = 0; + +/** + * @} + */ + + +/** @defgroup MSC_CORE_Private_Functions + * @{ + */ + +/** +* @brief USBD_MSC_Init +* Initialize the mass storage configuration +* @param pdev: device instance +* @param cfgidx: configuration index +* @retval status +*/ +uint8_t USBD_MSC_Init (void *pdev, + uint8_t cfgidx) +{ + USBD_MSC_DeInit(pdev , cfgidx ); + + /* Open EP IN */ + DCD_EP_Open(pdev, + MSC_IN_EP, + MSC_EPIN_SIZE, + USB_OTG_EP_BULK); + + /* Open EP OUT */ + DCD_EP_Open(pdev, + MSC_OUT_EP, + MSC_EPOUT_SIZE, + USB_OTG_EP_BULK); + + /* Init the BOT layer */ + MSC_BOT_Init(pdev); + + return USBD_OK; +} + +/** +* @brief USBD_MSC_DeInit +* DeInitilaize the mass storage configuration +* @param pdev: device instance +* @param cfgidx: configuration index +* @retval status +*/ +uint8_t USBD_MSC_DeInit (void *pdev, + uint8_t cfgidx) +{ + /* Close MSC EPs */ + DCD_EP_Close (pdev , MSC_IN_EP); + DCD_EP_Close (pdev , MSC_OUT_EP); + + /* Un Init the BOT layer */ + MSC_BOT_DeInit(pdev); + return USBD_OK; +} +/** +* @brief USBD_MSC_Setup +* Handle the MSC specific requests +* @param pdev: device instance +* @param req: USB request +* @retval status +*/ +uint8_t USBD_MSC_Setup (void *pdev, USB_SETUP_REQ *req) +{ + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + + /* Class request */ + case USB_REQ_TYPE_CLASS : + switch (req->bRequest) + { + case BOT_GET_MAX_LUN : + + if((req->wValue == 0) && + (req->wLength == 1) && + ((req->bmRequest & 0x80) == 0x80)) + { + USBD_MSC_MaxLun = USBD_STORAGE_fops->GetMaxLun(); + if(USBD_MSC_MaxLun > 0) + { + USBD_CtlSendData (pdev, + &USBD_MSC_MaxLun, + 1); + } + else + { + USBD_CtlError(pdev , req); + return USBD_FAIL; + + } + } + else + { + USBD_CtlError(pdev , req); + return USBD_FAIL; + } + break; + + case BOT_RESET : + if((req->wValue == 0) && + (req->wLength == 0) && + ((req->bmRequest & 0x80) != 0x80)) + { + MSC_BOT_Reset(pdev); + } + else + { + USBD_CtlError(pdev , req); + return USBD_FAIL; + } + break; + + default: + USBD_CtlError(pdev , req); + return USBD_FAIL; + } + break; + /* Interface & Endpoint request */ + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_INTERFACE : + USBD_CtlSendData (pdev, + &USBD_MSC_AltSet, + 1); + break; + + case USB_REQ_SET_INTERFACE : + USBD_MSC_AltSet = (uint8_t)(req->wValue); + break; + + case USB_REQ_CLEAR_FEATURE: + + /* Flush the FIFO and Clear the stall status */ + DCD_EP_Flush(pdev, (uint8_t)req->wIndex); + + /* Re-activate the EP */ + DCD_EP_Close (pdev , (uint8_t)req->wIndex); + if((((uint8_t)req->wIndex) & 0x80) == 0x80) + { + DCD_EP_Open(pdev, + ((uint8_t)req->wIndex), + MSC_EPIN_SIZE, + USB_OTG_EP_BULK); + } + else + { + DCD_EP_Open(pdev, + ((uint8_t)req->wIndex), + MSC_EPOUT_SIZE, + USB_OTG_EP_BULK); + } + + /* Handle BOT error */ + MSC_BOT_CplClrFeature(pdev, (uint8_t)req->wIndex); + break; + + } + break; + + default: + break; + } + return USBD_OK; +} + +/** +* @brief USBD_MSC_DataIn +* handle data IN Stage +* @param pdev: device instance +* @param epnum: endpoint index +* @retval status +*/ +uint8_t USBD_MSC_DataIn (void *pdev, + uint8_t epnum) +{ + MSC_BOT_DataIn(pdev , epnum); + return USBD_OK; +} + +/** +* @brief USBD_MSC_DataOut +* handle data OUT Stage +* @param pdev: device instance +* @param epnum: endpoint index +* @retval status +*/ +uint8_t USBD_MSC_DataOut (void *pdev, + uint8_t epnum) +{ + MSC_BOT_DataOut(pdev , epnum); + return USBD_OK; +} + +/** +* @brief USBD_MSC_GetCfgDesc +* return configuration descriptor +* @param speed : current device speed +* @param length : pointer data length +* @retval pointer to descriptor buffer +*/ +uint8_t *USBD_MSC_GetCfgDesc (uint8_t speed, uint16_t *length) +{ + *length = sizeof (USBD_MSC_CfgDesc); + return USBD_MSC_CfgDesc; +} + +/** +* @brief USBD_MSC_GetOtherCfgDesc +* return other speed configuration descriptor +* @param speed : current device speed +* @param length : pointer data length +* @retval pointer to descriptor buffer +*/ +#ifdef USB_OTG_HS_CORE +uint8_t *USBD_MSC_GetOtherCfgDesc (uint8_t speed, + uint16_t *length) +{ + *length = sizeof (USBD_MSC_OtherCfgDesc); + return USBD_MSC_OtherCfgDesc; +} +#endif +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/usb/usbd_msc_data.c b/radio/bootloader/usb/usbd_msc_data.c new file mode 100644 index 000000000..d65f05818 --- /dev/null +++ b/radio/bootloader/usb/usbd_msc_data.c @@ -0,0 +1,134 @@ +/** + ****************************************************************************** + * @file usbd_msc_data.c + * @author MCD Application Team + * @version V1.1.0 + * @date 19-March-2012 + * @brief This file provides all the vital inquiry pages and sense data. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_msc_data.h" + + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup MSC_DATA + * @brief Mass storage info/data module + * @{ + */ + +/** @defgroup MSC_DATA_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup MSC_DATA_Private_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup MSC_DATA_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup MSC_DATA_Private_Variables + * @{ + */ + + +/* USB Mass storage Page 0 Inquiry Data */ +const uint8_t MSC_Page00_Inquiry_Data[] = {//7 + 0x00, + 0x00, + 0x00, + (LENGTH_INQUIRY_PAGE00 - 4), + 0x00, + 0x80, + 0x83 +}; +/* USB Mass storage sense 6 Data */ +const uint8_t MSC_Mode_Sense6_data[] = { + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00 +}; +/* USB Mass storage sense 10 Data */ +const uint8_t MSC_Mode_Sense10_data[] = { + 0x00, + 0x06, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00 +}; +/** + * @} + */ + + +/** @defgroup MSC_DATA_Private_FunctionPrototypes + * @{ + */ +/** + * @} + */ + + +/** @defgroup MSC_DATA_Private_Functions + * @{ + */ + +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/usb/usbd_msc_scsi.c b/radio/bootloader/usb/usbd_msc_scsi.c new file mode 100644 index 000000000..11efc4414 --- /dev/null +++ b/radio/bootloader/usb/usbd_msc_scsi.c @@ -0,0 +1,734 @@ +/** + ****************************************************************************** + * @file usbd_msc_scsi.c + * @author MCD Application Team + * @version V1.1.0 + * @date 19-March-2012 + * @brief This file provides all the USBD SCSI layer functions. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_msc_bot.h" +#include "usbd_msc_scsi.h" +#include "usbd_msc_mem.h" +#include "usbd_msc_data.h" + + + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup MSC_SCSI + * @brief Mass storage SCSI layer module + * @{ + */ + +/** @defgroup MSC_SCSI_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup MSC_SCSI_Private_Defines + * @{ + */ + +/** + * @} + */ + + +/** @defgroup MSC_SCSI_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup MSC_SCSI_Private_Variables + * @{ + */ + +SCSI_Sense_TypeDef SCSI_Sense [SENSE_LIST_DEEPTH]; +uint8_t SCSI_Sense_Head; +uint8_t SCSI_Sense_Tail; + +uint32_t SCSI_blk_size; +uint32_t SCSI_blk_nbr; + +uint32_t SCSI_blk_addr; +uint32_t SCSI_blk_len; + +USB_OTG_CORE_HANDLE *cdev; +/** + * @} + */ + + +/** @defgroup MSC_SCSI_Private_FunctionPrototypes + * @{ + */ +static int8_t SCSI_TestUnitReady(uint8_t lun, uint8_t *params); +static int8_t SCSI_Inquiry(uint8_t lun, uint8_t *params); +static int8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t *params); +static int8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t *params); +static int8_t SCSI_RequestSense (uint8_t lun, uint8_t *params); +static int8_t SCSI_StartStopUnit(uint8_t lun, uint8_t *params); +static int8_t SCSI_ModeSense6 (uint8_t lun, uint8_t *params); +static int8_t SCSI_ModeSense10 (uint8_t lun, uint8_t *params); +static int8_t SCSI_Write10(uint8_t lun , uint8_t *params); +static int8_t SCSI_Read10(uint8_t lun , uint8_t *params); +static int8_t SCSI_Verify10(uint8_t lun, uint8_t *params); +static int8_t SCSI_CheckAddressRange (uint8_t lun , + uint32_t blk_offset , + uint16_t blk_nbr); +static int8_t SCSI_ProcessRead (uint8_t lun); + +static int8_t SCSI_ProcessWrite (uint8_t lun); +/** + * @} + */ + + +/** @defgroup MSC_SCSI_Private_Functions + * @{ + */ + + +/** +* @brief SCSI_ProcessCmd +* Process SCSI commands +* @param pdev: device instance +* @param lun: Logical unit number +* @param params: Command parameters +* @retval status +*/ +int8_t SCSI_ProcessCmd(USB_OTG_CORE_HANDLE *pdev, + uint8_t lun, + uint8_t *params) +{ + cdev = pdev; + + switch (params[0]) + { + case SCSI_TEST_UNIT_READY: + return SCSI_TestUnitReady(lun, params); + + case SCSI_REQUEST_SENSE: + return SCSI_RequestSense (lun, params); + case SCSI_INQUIRY: + return SCSI_Inquiry(lun, params); + + case SCSI_START_STOP_UNIT: + return SCSI_StartStopUnit(lun, params); + + case SCSI_ALLOW_MEDIUM_REMOVAL: + return SCSI_StartStopUnit(lun, params); + + case SCSI_MODE_SENSE6: + return SCSI_ModeSense6 (lun, params); + + case SCSI_MODE_SENSE10: + return SCSI_ModeSense10 (lun, params); + + case SCSI_READ_FORMAT_CAPACITIES: + return SCSI_ReadFormatCapacity(lun, params); + + case SCSI_READ_CAPACITY10: + return SCSI_ReadCapacity10(lun, params); + + case SCSI_READ10: + return SCSI_Read10(lun, params); + + case SCSI_WRITE10: + return SCSI_Write10(lun, params); + + case SCSI_VERIFY10: + return SCSI_Verify10(lun, params); + + default: + SCSI_SenseCode(lun, + ILLEGAL_REQUEST, + INVALID_CDB); + return -1; + } +} + + +/** +* @brief SCSI_TestUnitReady +* Process SCSI Test Unit Ready Command +* @param lun: Logical unit number +* @param params: Command parameters +* @retval status +*/ +static int8_t SCSI_TestUnitReady(uint8_t lun, uint8_t *params) +{ + + /* case 9 : Hi > D0 */ + if (MSC_BOT_cbw.dDataLength != 0) + { + SCSI_SenseCode(MSC_BOT_cbw.bLUN, + ILLEGAL_REQUEST, + INVALID_CDB); + return -1; + } + + if(USBD_STORAGE_fops->IsReady(lun) !=0 ) + { + SCSI_SenseCode(lun, + NOT_READY, + MEDIUM_NOT_PRESENT); + return -1; + } + MSC_BOT_DataLen = 0; + return 0; +} + +/** +* @brief SCSI_Inquiry +* Process Inquiry command +* @param lun: Logical unit number +* @param params: Command parameters +* @retval status +*/ +static int8_t SCSI_Inquiry(uint8_t lun, uint8_t *params) +{ + uint8_t* pPage; + uint16_t len; + + if (params[1] & 0x01)/*Evpd is set*/ + { + pPage = (uint8_t *)MSC_Page00_Inquiry_Data; + len = LENGTH_INQUIRY_PAGE00; + } + else + { + + pPage = (uint8_t *)&USBD_STORAGE_fops->pInquiry[lun * USBD_STD_INQUIRY_LENGTH]; + len = pPage[4] + 5; + + if (params[4] <= len) + { + len = params[4]; + } + } + MSC_BOT_DataLen = len; + + while (len) + { + len--; + MSC_BOT_Data[len] = pPage[len]; + } + return 0; +} + +/** +* @brief SCSI_ReadCapacity10 +* Process Read Capacity 10 command +* @param lun: Logical unit number +* @param params: Command parameters +* @retval status +*/ +static int8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t *params) +{ + + if(USBD_STORAGE_fops->GetCapacity(lun, &SCSI_blk_nbr, &SCSI_blk_size) != 0) + { + SCSI_SenseCode(lun, + NOT_READY, + MEDIUM_NOT_PRESENT); + return -1; + } + else + { + + MSC_BOT_Data[0] = (uint8_t)((SCSI_blk_nbr - 1) >> 24); + MSC_BOT_Data[1] = (uint8_t)((SCSI_blk_nbr - 1) >> 16); + MSC_BOT_Data[2] = (uint8_t)((SCSI_blk_nbr - 1) >> 8); + MSC_BOT_Data[3] = (uint8_t)(SCSI_blk_nbr - 1); + + MSC_BOT_Data[4] = (uint8_t)(SCSI_blk_size >> 24); + MSC_BOT_Data[5] = (uint8_t)(SCSI_blk_size >> 16); + MSC_BOT_Data[6] = (uint8_t)(SCSI_blk_size >> 8); + MSC_BOT_Data[7] = (uint8_t)(SCSI_blk_size); + + MSC_BOT_DataLen = 8; + return 0; + } +} +/** +* @brief SCSI_ReadFormatCapacity +* Process Read Format Capacity command +* @param lun: Logical unit number +* @param params: Command parameters +* @retval status +*/ +static int8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t *params) +{ + + uint32_t blk_size; + uint32_t blk_nbr; + uint16_t i; + + for(i=0 ; i < 12 ; i++) + { + MSC_BOT_Data[i] = 0; + } + + if(USBD_STORAGE_fops->GetCapacity(lun, &blk_nbr, &blk_size) != 0) + { + SCSI_SenseCode(lun, + NOT_READY, + MEDIUM_NOT_PRESENT); + return -1; + } + else + { + MSC_BOT_Data[3] = 0x08; + MSC_BOT_Data[4] = (uint8_t)((blk_nbr - 1) >> 24); + MSC_BOT_Data[5] = (uint8_t)((blk_nbr - 1) >> 16); + MSC_BOT_Data[6] = (uint8_t)((blk_nbr - 1) >> 8); + MSC_BOT_Data[7] = (uint8_t)(blk_nbr - 1); + + MSC_BOT_Data[8] = 0x02; + MSC_BOT_Data[9] = (uint8_t)(blk_size >> 16); + MSC_BOT_Data[10] = (uint8_t)(blk_size >> 8); + MSC_BOT_Data[11] = (uint8_t)(blk_size); + + MSC_BOT_DataLen = 12; + return 0; + } +} +/** +* @brief SCSI_ModeSense6 +* Process Mode Sense6 command +* @param lun: Logical unit number +* @param params: Command parameters +* @retval status +*/ +static int8_t SCSI_ModeSense6 (uint8_t lun, uint8_t *params) +{ + + uint16_t len = 8 ; + MSC_BOT_DataLen = len; + + while (len) + { + len--; + MSC_BOT_Data[len] = MSC_Mode_Sense6_data[len]; + } + return 0; +} + +/** +* @brief SCSI_ModeSense10 +* Process Mode Sense10 command +* @param lun: Logical unit number +* @param params: Command parameters +* @retval status +*/ +static int8_t SCSI_ModeSense10 (uint8_t lun, uint8_t *params) +{ + uint16_t len = 8; + + MSC_BOT_DataLen = len; + + while (len) + { + len--; + MSC_BOT_Data[len] = MSC_Mode_Sense10_data[len]; + } + return 0; +} + +/** +* @brief SCSI_RequestSense +* Process Request Sense command +* @param lun: Logical unit number +* @param params: Command parameters +* @retval status +*/ + +static int8_t SCSI_RequestSense (uint8_t lun, uint8_t *params) +{ + uint8_t i; + + for(i=0 ; i < REQUEST_SENSE_DATA_LEN ; i++) + { + MSC_BOT_Data[i] = 0; + } + + MSC_BOT_Data[0] = 0x70; + MSC_BOT_Data[7] = REQUEST_SENSE_DATA_LEN - 6; + + if((SCSI_Sense_Head != SCSI_Sense_Tail)) { + + MSC_BOT_Data[2] = SCSI_Sense[SCSI_Sense_Head].Skey; + MSC_BOT_Data[12] = SCSI_Sense[SCSI_Sense_Head].w.b.ASCQ; + MSC_BOT_Data[13] = SCSI_Sense[SCSI_Sense_Head].w.b.ASC; + SCSI_Sense_Head++; + + if (SCSI_Sense_Head == SENSE_LIST_DEEPTH) + { + SCSI_Sense_Head = 0; + } + } + MSC_BOT_DataLen = REQUEST_SENSE_DATA_LEN; + + if (params[4] <= REQUEST_SENSE_DATA_LEN) + { + MSC_BOT_DataLen = params[4]; + } + return 0; +} + +/** +* @brief SCSI_SenseCode +* Load the last error code in the error list +* @param lun: Logical unit number +* @param sKey: Sense Key +* @param ASC: Additional Sense Key +* @retval none + +*/ +void SCSI_SenseCode(uint8_t lun, uint8_t sKey, uint8_t ASC) +{ + SCSI_Sense[SCSI_Sense_Tail].Skey = sKey; + SCSI_Sense[SCSI_Sense_Tail].w.ASC = ASC << 8; + SCSI_Sense_Tail++; + if (SCSI_Sense_Tail == SENSE_LIST_DEEPTH) + { + SCSI_Sense_Tail = 0; + } +} +/** +* @brief SCSI_StartStopUnit +* Process Start Stop Unit command +* @param lun: Logical unit number +* @param params: Command parameters +* @retval status +*/ +static int8_t SCSI_StartStopUnit(uint8_t lun, uint8_t *params) +{ + MSC_BOT_DataLen = 0; + return 0; +} + +/** +* @brief SCSI_Read10 +* Process Read10 command +* @param lun: Logical unit number +* @param params: Command parameters +* @retval status +*/ +static int8_t SCSI_Read10(uint8_t lun , uint8_t *params) +{ + if(MSC_BOT_State == BOT_IDLE) /* Idle */ + { + + /* case 10 : Ho <> Di */ + + if ((MSC_BOT_cbw.bmFlags & 0x80) != 0x80) + { + SCSI_SenseCode(MSC_BOT_cbw.bLUN, + ILLEGAL_REQUEST, + INVALID_CDB); + return -1; + } + + if(USBD_STORAGE_fops->IsReady(lun) !=0 ) + { + SCSI_SenseCode(lun, + NOT_READY, + MEDIUM_NOT_PRESENT); + return -1; + } + + SCSI_blk_addr = (params[2] << 24) | \ + (params[3] << 16) | \ + (params[4] << 8) | \ + params[5]; + + SCSI_blk_len = (params[7] << 8) | \ + params[8]; + + + + if( SCSI_CheckAddressRange(lun, SCSI_blk_addr, SCSI_blk_len) < 0) + { + return -1; /* error */ + } + + MSC_BOT_State = BOT_DATA_IN; + SCSI_blk_addr *= SCSI_blk_size; + SCSI_blk_len *= SCSI_blk_size; + + /* cases 4,5 : Hi <> Dn */ + if (MSC_BOT_cbw.dDataLength != SCSI_blk_len) + { + SCSI_SenseCode(MSC_BOT_cbw.bLUN, + ILLEGAL_REQUEST, + INVALID_CDB); + return -1; + } + } + MSC_BOT_DataLen = MSC_MEDIA_PACKET; + + return SCSI_ProcessRead(lun); +} + +/** +* @brief SCSI_Write10 +* Process Write10 command +* @param lun: Logical unit number +* @param params: Command parameters +* @retval status +*/ + +static int8_t SCSI_Write10 (uint8_t lun , uint8_t *params) +{ + if (MSC_BOT_State == BOT_IDLE) /* Idle */ + { + + /* case 8 : Hi <> Do */ + + if ((MSC_BOT_cbw.bmFlags & 0x80) == 0x80) + { + SCSI_SenseCode(MSC_BOT_cbw.bLUN, + ILLEGAL_REQUEST, + INVALID_CDB); + return -1; + } + + /* Check whether Media is ready */ + if(USBD_STORAGE_fops->IsReady(lun) !=0 ) + { + SCSI_SenseCode(lun, + NOT_READY, + MEDIUM_NOT_PRESENT); + return -1; + } + + /* Check If media is write-protected */ + if(USBD_STORAGE_fops->IsWriteProtected(lun) !=0 ) + { + SCSI_SenseCode(lun, + NOT_READY, + WRITE_PROTECTED); + return -1; + } + + + SCSI_blk_addr = (params[2] << 24) | \ + (params[3] << 16) | \ + (params[4] << 8) | \ + params[5]; + SCSI_blk_len = (params[7] << 8) | \ + params[8]; + + /* check if LBA address is in the right range */ + if(SCSI_CheckAddressRange(lun, SCSI_blk_addr, SCSI_blk_len) < 0) + { + return -1; /* error */ + } + + SCSI_blk_addr *= SCSI_blk_size; + SCSI_blk_len *= SCSI_blk_size; + + /* cases 3,11,13 : Hn,Ho <> D0 */ + if (MSC_BOT_cbw.dDataLength != SCSI_blk_len) + { + SCSI_SenseCode(MSC_BOT_cbw.bLUN, + ILLEGAL_REQUEST, + INVALID_CDB); + return -1; + } + + /* Prepare EP to receive first data packet */ + MSC_BOT_State = BOT_DATA_OUT; + DCD_EP_PrepareRx (cdev, + MSC_OUT_EP, + MSC_BOT_Data, + MIN (SCSI_blk_len, MSC_MEDIA_PACKET)); + } + else /* Write Process ongoing */ + { + return SCSI_ProcessWrite(lun); + } + return 0; +} + + +/** +* @brief SCSI_Verify10 +* Process Verify10 command +* @param lun: Logical unit number +* @param params: Command parameters +* @retval status +*/ + +static int8_t SCSI_Verify10(uint8_t lun , uint8_t *params){ + if ((params[1]& 0x02) == 0x02) + { + SCSI_SenseCode (lun, ILLEGAL_REQUEST, INVALID_FIELED_IN_COMMAND); + return -1; /* Error, Verify Mode Not supported*/ + } + + if(SCSI_CheckAddressRange(lun, SCSI_blk_addr, SCSI_blk_len) < 0) + { + return -1; /* error */ + } + MSC_BOT_DataLen = 0; + return 0; +} + +/** +* @brief SCSI_CheckAddressRange +* Check address range +* @param lun: Logical unit number +* @param blk_offset: first block address +* @param blk_nbr: number of block to be processed +* @retval status +*/ +static int8_t SCSI_CheckAddressRange (uint8_t lun , uint32_t blk_offset , uint16_t blk_nbr) +{ + if (USBD_STORAGE_fops->GetCapacity(lun, &SCSI_blk_nbr, &SCSI_blk_size) != 0) + { + SCSI_SenseCode(lun, NOT_READY, MEDIUM_NOT_PRESENT); + return -1; + } + + if ((blk_offset + blk_nbr) > SCSI_blk_nbr ) + { + SCSI_SenseCode(lun, ILLEGAL_REQUEST, ADDRESS_OUT_OF_RANGE); + return -1; + } + + return 0; +} + +/** +* @brief SCSI_ProcessRead +* Handle Read Process +* @param lun: Logical unit number +* @retval status +*/ +static int8_t SCSI_ProcessRead (uint8_t lun) +{ + uint32_t len; + + len = MIN(SCSI_blk_len , MSC_MEDIA_PACKET); + + if( USBD_STORAGE_fops->Read(lun , + MSC_BOT_Data, + SCSI_blk_addr / SCSI_blk_size, + len / SCSI_blk_size) < 0) + { + + SCSI_SenseCode(lun, HARDWARE_ERROR, UNRECOVERED_READ_ERROR); + return -1; + } + + + DCD_EP_Tx (cdev, + MSC_IN_EP, + MSC_BOT_Data, + len); + + + SCSI_blk_addr += len; + SCSI_blk_len -= len; + + /* case 6 : Hi = Di */ + MSC_BOT_csw.dDataResidue -= len; + + if (SCSI_blk_len == 0) + { + MSC_BOT_State = BOT_LAST_DATA_IN; + } + return 0; +} + +/** +* @brief SCSI_ProcessWrite +* Handle Write Process +* @param lun: Logical unit number +* @retval status +*/ + +static int8_t SCSI_ProcessWrite (uint8_t lun) +{ + uint32_t len; + + len = MIN(SCSI_blk_len , MSC_MEDIA_PACKET); + + if(USBD_STORAGE_fops->Write(lun , + MSC_BOT_Data, + SCSI_blk_addr / SCSI_blk_size, + len / SCSI_blk_size) < 0) + { + SCSI_SenseCode(lun, HARDWARE_ERROR, WRITE_FAULT); + return -1; + } + + + SCSI_blk_addr += len; + SCSI_blk_len -= len; + + /* case 12 : Ho = Do */ + MSC_BOT_csw.dDataResidue -= len; + + if (SCSI_blk_len == 0) + { + MSC_BOT_SendCSW (cdev, CSW_CMD_PASSED); + } + else + { + /* Prapare EP to Receive next packet */ + DCD_EP_PrepareRx (cdev, + MSC_OUT_EP, + MSC_BOT_Data, + MIN (SCSI_blk_len, MSC_MEDIA_PACKET)); + } + + return 0; +} +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/usb/usbd_req.c b/radio/bootloader/usb/usbd_req.c new file mode 100644 index 000000000..63c1167d9 --- /dev/null +++ b/radio/bootloader/usb/usbd_req.c @@ -0,0 +1,868 @@ +/** + ****************************************************************************** + * @file usbd_req.c + * @author MCD Application Team + * @version V1.1.0 + * @date 19-March-2012 + * @brief This file provides the standard USB requests following chapter 9. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_req.h" +#include "usbd_ioreq.h" +#include "usbd_desc.h" + + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup USBD_REQ + * @brief USB standard requests module + * @{ + */ + +/** @defgroup USBD_REQ_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_REQ_Private_Defines + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_REQ_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_REQ_Private_Variables + * @{ + */ +extern __IO USB_OTG_DCTL_TypeDef SET_TEST_MODE; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint32_t USBD_ep_status __ALIGN_END = 0; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint32_t USBD_default_cfg __ALIGN_END = 0; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint32_t USBD_cfg_status __ALIGN_END = 0; + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint8_t USBD_StrDesc[USB_MAX_STR_DESC_SIZ] __ALIGN_END ; +/** + * @} + */ + + +/** @defgroup USBD_REQ_Private_FunctionPrototypes + * @{ + */ +static void USBD_GetDescriptor(USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req); + +static void USBD_SetAddress(USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req); + +static void USBD_SetConfig(USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req); + +static void USBD_GetConfig(USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req); + +static void USBD_GetStatus(USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req); + +static void USBD_SetFeature(USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req); + +static void USBD_ClrFeature(USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req); + +static uint8_t USBD_GetLen(uint8_t *buf); +/** + * @} + */ + + +/** @defgroup USBD_REQ_Private_Functions + * @{ + */ + + +/** +* @brief USBD_StdDevReq +* Handle standard usb device requests +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +USBD_Status USBD_StdDevReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req) +{ + USBD_Status ret = USBD_OK; + + switch (req->bRequest) + { + case USB_REQ_GET_DESCRIPTOR: + + USBD_GetDescriptor (pdev, req) ; + break; + + case USB_REQ_SET_ADDRESS: + USBD_SetAddress(pdev, req); + break; + + case USB_REQ_SET_CONFIGURATION: + USBD_SetConfig (pdev , req); + break; + + case USB_REQ_GET_CONFIGURATION: + USBD_GetConfig (pdev , req); + break; + + case USB_REQ_GET_STATUS: + USBD_GetStatus (pdev , req); + break; + + + case USB_REQ_SET_FEATURE: + USBD_SetFeature (pdev , req); + break; + + case USB_REQ_CLEAR_FEATURE: + USBD_ClrFeature (pdev , req); + break; + + default: + USBD_CtlError(pdev , req); + break; + } + + return ret; +} + +/** +* @brief USBD_StdItfReq +* Handle standard usb interface requests +* @param pdev: USB OTG device instance +* @param req: usb request +* @retval status +*/ +USBD_Status USBD_StdItfReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req) +{ + USBD_Status ret = USBD_OK; + + switch (pdev->dev.device_status) + { + case USB_OTG_CONFIGURED: + + if (LOBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) + { + pdev->dev.class_cb->Setup (pdev, req); + + if((req->wLength == 0)&& (ret == USBD_OK)) + { + USBD_CtlSendStatus(pdev); + } + } + else + { + USBD_CtlError(pdev , req); + } + break; + + default: + USBD_CtlError(pdev , req); + break; + } + return ret; +} + +/** +* @brief USBD_StdEPReq +* Handle standard usb endpoint requests +* @param pdev: USB OTG device instance +* @param req: usb request +* @retval status +*/ +USBD_Status USBD_StdEPReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req) +{ + + uint8_t ep_addr; + USBD_Status ret = USBD_OK; + + ep_addr = LOBYTE(req->wIndex); + + switch (req->bRequest) + { + + case USB_REQ_SET_FEATURE : + + switch (pdev->dev.device_status) + { + case USB_OTG_ADDRESSED: + if ((ep_addr != 0x00) && (ep_addr != 0x80)) + { + DCD_EP_Stall(pdev , ep_addr); + } + break; + + case USB_OTG_CONFIGURED: + if (req->wValue == USB_FEATURE_EP_HALT) + { + if ((ep_addr != 0x00) && (ep_addr != 0x80)) + { + DCD_EP_Stall(pdev , ep_addr); + + } + } + pdev->dev.class_cb->Setup (pdev, req); + USBD_CtlSendStatus(pdev); + + break; + + default: + USBD_CtlError(pdev , req); + break; + } + break; + + case USB_REQ_CLEAR_FEATURE : + + switch (pdev->dev.device_status) + { + case USB_OTG_ADDRESSED: + if ((ep_addr != 0x00) && (ep_addr != 0x80)) + { + DCD_EP_Stall(pdev , ep_addr); + } + break; + + case USB_OTG_CONFIGURED: + if (req->wValue == USB_FEATURE_EP_HALT) + { + if ((ep_addr != 0x00) && (ep_addr != 0x80)) + { + DCD_EP_ClrStall(pdev , ep_addr); + pdev->dev.class_cb->Setup (pdev, req); + } + USBD_CtlSendStatus(pdev); + } + break; + + default: + USBD_CtlError(pdev , req); + break; + } + break; + + case USB_REQ_GET_STATUS: + switch (pdev->dev.device_status) + { + case USB_OTG_ADDRESSED: + if ((ep_addr != 0x00) && (ep_addr != 0x80)) + { + DCD_EP_Stall(pdev , ep_addr); + } + break; + + case USB_OTG_CONFIGURED: + + + if ((ep_addr & 0x80)== 0x80) + { + if(pdev->dev.in_ep[ep_addr & 0x7F].is_stall) + { + USBD_ep_status = 0x0001; + } + else + { + USBD_ep_status = 0x0000; + } + } + else if ((ep_addr & 0x80)== 0x00) + { + if(pdev->dev.out_ep[ep_addr].is_stall) + { + USBD_ep_status = 0x0001; + } + + else + { + USBD_ep_status = 0x0000; + } + } + USBD_CtlSendData (pdev, + (uint8_t *)&USBD_ep_status, + 2); + break; + + default: + USBD_CtlError(pdev , req); + break; + } + break; + + default: + break; + } + return ret; +} +/** +* @brief USBD_GetDescriptor +* Handle Get Descriptor requests +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_GetDescriptor(USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req) +{ + uint16_t len; + uint8_t *pbuf; + + + switch (req->wValue >> 8) + { + case USB_DESC_TYPE_DEVICE: + pbuf = pdev->dev.usr_device->GetDeviceDescriptor(pdev->cfg.speed, &len); + if ((req->wLength == 64) ||( pdev->dev.device_status == USB_OTG_DEFAULT)) + { + len = 8; + } + break; + + case USB_DESC_TYPE_CONFIGURATION: + pbuf = (uint8_t *)pdev->dev.class_cb->GetConfigDescriptor(pdev->cfg.speed, &len); +#ifdef USB_OTG_HS_CORE + if((pdev->cfg.speed == USB_OTG_SPEED_FULL )&& + (pdev->cfg.phy_itface == USB_OTG_ULPI_PHY)) + { + pbuf = (uint8_t *)pdev->dev.class_cb->GetOtherConfigDescriptor(pdev->cfg.speed, &len); + } +#endif + pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + pdev->dev.pConfig_descriptor = pbuf; + break; + + case USB_DESC_TYPE_STRING: + switch ((uint8_t)(req->wValue)) + { + case USBD_IDX_LANGID_STR: + pbuf = pdev->dev.usr_device->GetLangIDStrDescriptor(pdev->cfg.speed, &len); + break; + + case USBD_IDX_MFC_STR: + pbuf = pdev->dev.usr_device->GetManufacturerStrDescriptor(pdev->cfg.speed, &len); + break; + + case USBD_IDX_PRODUCT_STR: + pbuf = pdev->dev.usr_device->GetProductStrDescriptor(pdev->cfg.speed, &len); + break; + + case USBD_IDX_SERIAL_STR: + pbuf = pdev->dev.usr_device->GetSerialStrDescriptor(pdev->cfg.speed, &len); + break; + + case USBD_IDX_CONFIG_STR: + pbuf = pdev->dev.usr_device->GetConfigurationStrDescriptor(pdev->cfg.speed, &len); + break; + + case USBD_IDX_INTERFACE_STR: + pbuf = pdev->dev.usr_device->GetInterfaceStrDescriptor(pdev->cfg.speed, &len); + break; + + default: +#ifdef USB_SUPPORT_USER_STRING_DESC + pbuf = pdev->dev.class_cb->GetUsrStrDescriptor(pdev->cfg.speed, (req->wValue) , &len); + break; +#else + USBD_CtlError(pdev , req); + return; +#endif /* USBD_CtlError(pdev , req); */ + } + break; + case USB_DESC_TYPE_DEVICE_QUALIFIER: +#ifdef USB_OTG_HS_CORE + if(pdev->cfg.speed == USB_OTG_SPEED_HIGH ) + { + + pbuf = (uint8_t *)pdev->dev.class_cb->GetConfigDescriptor(pdev->cfg.speed, &len); + + USBD_DeviceQualifierDesc[4]= pbuf[14]; + USBD_DeviceQualifierDesc[5]= pbuf[15]; + USBD_DeviceQualifierDesc[6]= pbuf[16]; + + pbuf = USBD_DeviceQualifierDesc; + len = USB_LEN_DEV_QUALIFIER_DESC; + break; + } + else + { + USBD_CtlError(pdev , req); + return; + } +#else + USBD_CtlError(pdev , req); + return; +#endif + + case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: +#ifdef USB_OTG_HS_CORE + + if(pdev->cfg.speed == USB_OTG_SPEED_HIGH ) + { + pbuf = (uint8_t *)pdev->dev.class_cb->GetOtherConfigDescriptor(pdev->cfg.speed, &len); + pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; + break; + } + else + { + USBD_CtlError(pdev , req); + return; + } +#else + USBD_CtlError(pdev , req); + return; +#endif + + + default: + USBD_CtlError(pdev , req); + return; + } + + if((len != 0)&& (req->wLength != 0)) + { + + len = MIN(len , req->wLength); + + USBD_CtlSendData (pdev, + pbuf, + len); + } + +} + +/** +* @brief USBD_SetAddress +* Set device address +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_SetAddress(USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req) +{ + uint8_t dev_addr; + + if ((req->wIndex == 0) && (req->wLength == 0)) + { + dev_addr = (uint8_t)(req->wValue) & 0x7F; + + if (pdev->dev.device_status == USB_OTG_CONFIGURED) + { + USBD_CtlError(pdev , req); + } + else + { + pdev->dev.device_address = dev_addr; + DCD_EP_SetAddress(pdev, dev_addr); + USBD_CtlSendStatus(pdev); + + if (dev_addr != 0) + { + pdev->dev.device_status = USB_OTG_ADDRESSED; + } + else + { + pdev->dev.device_status = USB_OTG_DEFAULT; + } + } + } + else + { + USBD_CtlError(pdev , req); + } +} + +/** +* @brief USBD_SetConfig +* Handle Set device configuration request +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_SetConfig(USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req) +{ + + static uint8_t cfgidx; + + cfgidx = (uint8_t)(req->wValue); + + if (cfgidx > USBD_CFG_MAX_NUM ) + { + USBD_CtlError(pdev , req); + } + else + { + switch (pdev->dev.device_status) + { + case USB_OTG_ADDRESSED: + if (cfgidx) + { + pdev->dev.device_config = cfgidx; + pdev->dev.device_status = USB_OTG_CONFIGURED; + USBD_SetCfg(pdev , cfgidx); + USBD_CtlSendStatus(pdev); + } + else + { + USBD_CtlSendStatus(pdev); + } + break; + + case USB_OTG_CONFIGURED: + if (cfgidx == 0) + { + pdev->dev.device_status = USB_OTG_ADDRESSED; + pdev->dev.device_config = cfgidx; + USBD_ClrCfg(pdev , cfgidx); + USBD_CtlSendStatus(pdev); + + } + else if (cfgidx != pdev->dev.device_config) + { + /* Clear old configuration */ + USBD_ClrCfg(pdev , pdev->dev.device_config); + + /* set new configuration */ + pdev->dev.device_config = cfgidx; + USBD_SetCfg(pdev , cfgidx); + USBD_CtlSendStatus(pdev); + } + else + { + USBD_CtlSendStatus(pdev); + } + break; + + default: + USBD_CtlError(pdev , req); + break; + } + } +} + +/** +* @brief USBD_GetConfig +* Handle Get device configuration request +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_GetConfig(USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req) +{ + + if (req->wLength != 1) + { + USBD_CtlError(pdev , req); + } + else + { + switch (pdev->dev.device_status ) + { + case USB_OTG_ADDRESSED: + + USBD_CtlSendData (pdev, + (uint8_t *)&USBD_default_cfg, + 1); + break; + + case USB_OTG_CONFIGURED: + + USBD_CtlSendData (pdev, + &pdev->dev.device_config, + 1); + break; + + default: + USBD_CtlError(pdev , req); + break; + } + } +} + +/** +* @brief USBD_GetStatus +* Handle Get Status request +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_GetStatus(USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req) +{ + + + switch (pdev->dev.device_status) + { + case USB_OTG_ADDRESSED: + case USB_OTG_CONFIGURED: + +#ifdef USBD_SELF_POWERED + USBD_cfg_status = USB_CONFIG_SELF_POWERED; +#else + USBD_cfg_status = 0x00; +#endif + + if (pdev->dev.DevRemoteWakeup) + { + USBD_cfg_status |= USB_CONFIG_REMOTE_WAKEUP; + } + + USBD_CtlSendData (pdev, + (uint8_t *)&USBD_cfg_status, + 2); + break; + + default : + USBD_CtlError(pdev , req); + break; + } +} + + +/** +* @brief USBD_SetFeature +* Handle Set device feature request +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_SetFeature(USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req) +{ + + USB_OTG_DCTL_TypeDef dctl; + uint8_t test_mode = 0; + + if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) + { + pdev->dev.DevRemoteWakeup = 1; + pdev->dev.class_cb->Setup (pdev, req); + USBD_CtlSendStatus(pdev); + } + + else if ((req->wValue == USB_FEATURE_TEST_MODE) && + ((req->wIndex & 0xFF) == 0)) + { + dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL); + + test_mode = req->wIndex >> 8; + switch (test_mode) + { + case 1: // TEST_J + dctl.b.tstctl = 1; + break; + + case 2: // TEST_K + dctl.b.tstctl = 2; + break; + + case 3: // TEST_SE0_NAK + dctl.b.tstctl = 3; + break; + + case 4: // TEST_PACKET + dctl.b.tstctl = 4; + break; + + case 5: // TEST_FORCE_ENABLE + dctl.b.tstctl = 5; + break; + } + SET_TEST_MODE = dctl; + pdev->dev.test_mode = 1; + USBD_CtlSendStatus(pdev); + } + +} + + +/** +* @brief USBD_ClrFeature +* Handle clear device feature request +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_ClrFeature(USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req) +{ + switch (pdev->dev.device_status) + { + case USB_OTG_ADDRESSED: + case USB_OTG_CONFIGURED: + if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) + { + pdev->dev.DevRemoteWakeup = 0; + pdev->dev.class_cb->Setup (pdev, req); + USBD_CtlSendStatus(pdev); + } + break; + + default : + USBD_CtlError(pdev , req); + break; + } +} + +/** +* @brief USBD_ParseSetupRequest +* Copy buffer into setup structure +* @param pdev: device instance +* @param req: usb request +* @retval None +*/ + +void USBD_ParseSetupRequest( USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req) +{ + req->bmRequest = *(uint8_t *) (pdev->dev.setup_packet); + req->bRequest = *(uint8_t *) (pdev->dev.setup_packet + 1); + req->wValue = SWAPBYTE (pdev->dev.setup_packet + 2); + req->wIndex = SWAPBYTE (pdev->dev.setup_packet + 4); + req->wLength = SWAPBYTE (pdev->dev.setup_packet + 6); + + pdev->dev.in_ep[0].ctl_data_len = req->wLength ; + pdev->dev.device_state = USB_OTG_EP0_SETUP; +} + +/** +* @brief USBD_CtlError +* Handle USB low level Error +* @param pdev: device instance +* @param req: usb request +* @retval None +*/ + +void USBD_CtlError( USB_OTG_CORE_HANDLE *pdev, + USB_SETUP_REQ *req) +{ + + DCD_EP_Stall(pdev , 0x80); + DCD_EP_Stall(pdev , 0); + USB_OTG_EP0_OutStart(pdev); +} + + +/** + * @brief USBD_GetString + * Convert Ascii string into unicode one + * @param desc : descriptor buffer + * @param unicode : Formatted string buffer (unicode) + * @param len : descriptor length + * @retval None + */ +void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) +{ + uint8_t idx = 0; + + if (desc != NULL) + { + *len = USBD_GetLen(desc) * 2 + 2; + unicode[idx++] = *len; + unicode[idx++] = USB_DESC_TYPE_STRING; + + while (*desc != NULL) + { + unicode[idx++] = *desc++; + unicode[idx++] = 0x00; + } + } +} + +/** + * @brief USBD_GetLen + * return the string length + * @param buf : pointer to the ascii string buffer + * @retval string length + */ +static uint8_t USBD_GetLen(uint8_t *buf) +{ + uint8_t len = 0; + + while (*buf != NULL) + { + len++; + buf++; + } + + return len; +} +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/usbd_storage_msd.cpp b/radio/bootloader/usbd_storage_msd.cpp new file mode 100644 index 000000000..b26490086 --- /dev/null +++ b/radio/bootloader/usbd_storage_msd.cpp @@ -0,0 +1,817 @@ +/** + ****************************************************************************** + * @file usbd_storage_msd.c + * @author MCD application Team + * @version V1.1.0 + * @date 19-March-2012 + * @brief This file provides the disk operations functions. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "radio.h" +#include "eeprom_rlc.h" +#include +#include +//#include +#include "drivers.h" +#include "i2c_ee.h" + +#include "diskio.h" +//#include "board_taranis.h" + +void I2C_EE_BufferWrite(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite) ; +void eeprom_read_block (void *pointer_ram, uint16_t pointer_eeprom, size_t size); + +extern "C" { +#include "misc.h" +#include "usbd_msc_mem.h" +#include "usb_conf.h" + +#define eeWriteBlockCmp I2C_EE_BufferWrite +#define eeprom_read_block I2C_EE_BufferRead + + +#define STORAGE_LUN_NBR 2 +#define BLOCKSIZE 512 + +/* USB Mass storage Standard Inquiry Data */ +const unsigned char STORAGE_Inquirydata[] = {//36 + + /* LUN 0 */ + 0x00, + 0x80, + 0x02, + 0x02, + (USBD_STD_INQUIRY_LENGTH - 5), + 0x00, + 0x00, + 0x00, + 'F', 'r', 'S', 'k', 'y', ' ', ' ', ' ', /* Manufacturer : 8 bytes */ + 'T', 'a', 'r', 'a', 'n', 'i', 's', ' ', /* Product : 16 Bytes */ + 'R', 'a', 'd', 'i', 'o', ' ', ' ', ' ', + '1', '.', '0', '0', /* Version : 4 Bytes */ + /* LUN 1 */ + 0x00, + 0x80, + 0x02, + 0x02, + (USBD_STD_INQUIRY_LENGTH - 5), + 0x00, + 0x00, + 0x00, + 'F', 'r', 'S', 'k', 'y', ' ', ' ', ' ', /* Manufacturer : 8 bytes */ + 'T', 'a', 'r', 'a', 'n', 'i', 's', ' ', /* Product : 16 Bytes */ + 'R', 'a', 'd', 'i', 'o', ' ', ' ', ' ', + '1', '.', '0' ,'0', /* Version : 4 Bytes */ +}; + +int32_t fat12Write( const uint8_t *buffer, uint16_t sector, uint32_t count ) ; +int32_t fat12Read( uint8_t *buffer, uint16_t sector, uint16_t count ) ; + +int8_t STORAGE_Init (uint8_t lun); + +int8_t STORAGE_GetCapacity (uint8_t lun, + uint32_t *block_num, + uint32_t *block_size); + +int8_t STORAGE_IsReady (uint8_t lun); + +int8_t STORAGE_IsWriteProtected (uint8_t lun); + +int8_t STORAGE_Read (uint8_t lun, + uint8_t *buf, + uint32_t blk_addr, + uint16_t blk_len); + +int8_t STORAGE_Write (uint8_t lun, + uint8_t *buf, + uint32_t blk_addr, + uint16_t blk_len); + +int8_t STORAGE_GetMaxLun (void); + +USBD_STORAGE_cb_TypeDef USBD_MICRO_SDIO_fops = +{ + STORAGE_Init, + STORAGE_GetCapacity, + STORAGE_IsReady, + STORAGE_IsWriteProtected, + STORAGE_Read, + STORAGE_Write, + STORAGE_GetMaxLun, + (int8_t *)STORAGE_Inquirydata, +}; + +USBD_STORAGE_cb_TypeDef *USBD_STORAGE_fops = &USBD_MICRO_SDIO_fops; + +__IO uint32_t count = 0; +} + +int8_t STORAGE_Init (uint8_t lun) +{ + NVIC_InitTypeDef NVIC_InitStructure; + NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority =0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + +/* TODO if no SD ... if( SD_Init() != 0) + { + return (-1); + } +*/ + return (0); +} + +/** + * @brief return medium capacity and block size + * @param lun : logical unit number + * @param block_num : number of physical block + * @param block_size : size of a physical block + * @retval Status + */ +int8_t STORAGE_GetCapacity (uint8_t lun, uint32_t *block_num, uint32_t *block_size) +{ + if (lun == 1) { + *block_size = BLOCKSIZE; + *block_num = EESIZE/BLOCKSIZE + 3 + 1024 ; + } + else { + if (socket_is_empty()) + return -1; + + *block_size = BLOCKSIZE; + + static DWORD sector_count = 0; + if (sector_count == 0) { + if (disk_ioctl(0, GET_SECTOR_COUNT, (BYTE*)§or_count) != RES_OK) { + sector_count = 0; + return -1; + } + } + + *block_num = sector_count; + } + + return 0; +} + +/** + * @brief check whether the medium is ready + * @param lun : logical unit number + * @retval Status + */ +int8_t STORAGE_IsReady (uint8_t lun) +{ + if (lun == 1) { + return 0; + } + else { + return !socket_is_empty() ? 0 : -1; + } +} + +/** + * @brief check whether the medium is write-protected + * @param lun : logical unit number + * @retval Status + */ +int8_t STORAGE_IsWriteProtected (uint8_t lun) +{ + return 0; +} + +/** + * @brief Read data from the medium + * @param lun : logical unit number + * @param buf : Pointer to the buffer to save data + * @param blk_addr : address of 1st block to be read + * @param blk_len : nmber of blocks to be read + * @retval Status + */ + +int8_t SD_ReadSectors(uint8_t *buff, uint32_t sector, uint32_t count); + +int8_t STORAGE_Read (uint8_t lun, + uint8_t *buf, + uint32_t blk_addr, + uint16_t blk_len) +{ + if (lun == 1) { + if (fat12Read(buf, blk_addr, blk_len) != 0) { + return -1; + } + } + else { + if (SD_ReadSectors(buf, + blk_addr, + blk_len) != 0) { + return -1; + } + } + + return 0; +} +/** + * @brief Write data to the medium + * @param lun : logical unit number + * @param buf : Pointer to the buffer to write from + * @param blk_addr : address of 1st block to be written + * @param blk_len : nmber of blocks to be read + * @retval Status + */ + +int8_t SD_WriteSectors(uint8_t *buf, uint32_t sector, uint32_t count); + +int8_t STORAGE_Write (uint8_t lun, + uint8_t *buf, + uint32_t blk_addr, + uint16_t blk_len) +{ + if (lun == 1) { + if (fat12Write(buf, blk_addr, blk_len) != 0) + return -1; + } + else { + if (SD_WriteSectors(buf, + blk_addr, + blk_len) != 0) + return -1; + } + + return (0); +} + +/** + * @brief Return number of supported logical unit + * @param None + * @retval number of logical unit + */ + +int8_t STORAGE_GetMaxLun (void) +{ + return (STORAGE_LUN_NBR - 1); +} + + +//------------------------------------------------------------------------------ +/** + * FAT12 boot sector partition. + */ +const char g_FATboot[BLOCKSIZE] = +{ + 0xeb, 0x3c, 0x90, // Jump instruction. + 0x39, 0x58, 0x20, 0x54, 0x45, 0x41, 0x4D, 0x00, // OEM Name + 0x00, 0x02, // Bytes per sector + 0x08, // Sectors per FS cluster. + 0x01, 0x00, // Reserved sector count + + 0x01, // Number of FATs + 0x10, 0x00, // Number of root directory entries + (EESIZE/BLOCKSIZE)+3, 0x04, // Total sectors = 1024+131=1155 + 0xf8, // Media descriptor + 0x01, 0x00, // Sectors per FAT table + 0x20, 0x00, // Sectors per track + 0x40, 0x00, // Number of heads + 0x00, 0x00, 0x00, 0x00, // Number of hidden sectors + + 0x00, 0x00, 0x00, 0x00, // Large number of sectors. + 0x00, // Physical drive number + 0x00, // Reserved + 0x29, // Extended boot signature + 0xCE, 0xFA, 0x5C, 0xD1, // Disk ID (serial number) + 0x56, 0x49, 0x52, 0x54, 0x46, 0x53, 0x20, 0x20, 0x20, 0x20, 0x20, // Volume label + 0x46, 0x41, 0x54, 0x31, 0x32, 0x20, 0x20, 0x20, // FAT file system type + 0x00, 0x00, // OS boot code + + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0xaa +}; + +#if defined(REV4a) +const char g_FAT[BLOCKSIZE] = +{ + 0xF8, 0xFF, 0xFF, 0x03, 0x40, 0x00, 0x05, 0x60, 0x00, 0x07, 0x80, 0x00, 0x09, 0xF0, 0xFF, 0x0B, + 0xC0, 0x00, 0x0D, 0xE0, 0x00, 0x0F, 0x00, 0x01, 0x11, 0x20, 0x01, 0x13, 0x40, 0x01, 0x15, 0x60, + 0x01, 0x17, 0x80, 0x01, 0x19, 0xA0, 0x01, 0x1B, 0xC0, 0x01, 0x1D, 0xE0, 0x01, 0x1F, 0x00, 0x02, + 0x21, 0x20, 0x02, 0x23, 0x40, 0x02, 0x25, 0x60, 0x02, 0x27, 0x80, 0x02, 0x29, 0xA0, 0x02, 0x2B, + 0xC0, 0x02, 0x2D, 0xE0, 0x02, 0x2F, 0x00, 0x03, 0x31, 0x20, 0x03, 0x33, 0x40, 0x03, 0x35, 0x60, + 0x03, 0x37, 0x80, 0x03, 0x39, 0xA0, 0x03, 0x3B, 0xC0, 0x03, 0x3D, 0xE0, 0x03, 0x3F, 0x00, 0x04, + 0x41, 0x20, 0x04, 0x43, 0x40, 0x04, 0x45, 0x60, 0x04, 0x47, 0x80, 0x04, 0x49, 0xA0, 0x04, 0x4B, + 0xC0, 0x04, 0x4D, 0xE0, 0x04, 0x4F, 0x00, 0x05, 0x51, 0x20, 0x05, 0x53, 0x40, 0x05, 0x55, 0x60, + 0x05, 0x57, 0x80, 0x05, 0x59, 0xA0, 0x05, 0x5B, 0xC0, 0x05, 0x5D, 0xE0, 0x05, 0x5F, 0x00, 0x06, + 0x61, 0x20, 0x06, 0x63, 0x40, 0x06, 0x65, 0x60, 0x06, 0x67, 0x80, 0x06, 0x69, 0xA0, 0x06, 0x6B, + 0xC0, 0x06, 0x6D, 0xE0, 0x06, 0x6F, 0x00, 0x07, 0x71, 0x20, 0x07, 0x73, 0x40, 0x07, 0x75, 0x60, + 0x07, 0x77, 0x80, 0x07, 0x79, 0xA0, 0x07, 0x7B, 0xC0, 0x07, 0x7D, 0xE0, 0x07, 0x7F, 0x00, 0x08, + 0x81, 0x20, 0x08, 0x83, 0x40, 0x08, 0x85, 0x60, 0x08, 0x87, 0x80, 0x08, 0x89, 0xF0, 0xFF, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; +#else +const char g_FAT[BLOCKSIZE] = +{ + 0xF8, 0xFF, 0xFF, 0x03, 0x40, 0x00, 0x05, 0x60, 0x00, 0x07, 0x80, 0x00, 0x09, 0xF0, 0xFF, 0x0B, + 0xC0, 0x00, 0x0D, 0xE0, 0x00, 0x0F, 0x00, 0x01, 0x11, 0x20, 0x01, 0x13, 0x40, 0x01, 0x15, 0x60, + 0x01, 0x17, 0x80, 0x01, 0x19, 0xA0, 0x01, 0x1B, 0xC0, 0x01, 0x1D, 0xE0, 0x01, 0x1F, 0x00, 0x02, + 0x21, 0x20, 0x02, 0x23, 0x40, 0x02, 0x25, 0x60, 0x02, 0x27, 0x80, 0x02, 0x29, 0xA0, 0x02, 0x2B, + 0xC0, 0x02, 0x2D, 0xE0, 0x02, 0x2F, 0x00, 0x03, 0x31, 0x20, 0x03, 0x33, 0x40, 0x03, 0x35, 0x60, + 0x03, 0x37, 0x80, 0x03, 0x39, 0xA0, 0x03, 0x3B, 0xC0, 0x03, 0x3D, 0xE0, 0x03, 0x3F, 0x00, 0x04, + 0x41, 0x20, 0x04, 0x43, 0x40, 0x04, 0x45, 0x60, 0x04, 0x47, 0x80, 0x04, 0x49, 0xA0, 0x04, 0x4B, + 0xC0, 0x04, 0x4D, 0xE0, 0x04, 0x4F, 0x00, 0x05, 0x51, 0x20, 0x05, 0x53, 0x40, 0x05, 0x55, 0x60, + 0x05, 0x57, 0x80, 0x05, 0x59, 0xA0, 0x05, 0x5B, 0xC0, 0x05, 0x5D, 0xE0, 0x05, 0x5F, 0x00, 0x06, + 0x61, 0x20, 0x06, 0x63, 0x40, 0x06, 0x65, 0x60, 0x06, 0x67, 0x80, 0x06, 0x69, 0xA0, 0x06, 0x6B, + 0xC0, 0x06, 0x6D, 0xE0, 0x06, 0x6F, 0x00, 0x07, 0x71, 0x20, 0x07, 0x73, 0x40, 0x07, 0x75, 0x60, + 0x07, 0x77, 0x80, 0x07, 0x79, 0xA0, 0x07, 0x7B, 0xC0, 0x07, 0x7D, 0xE0, 0x07, 0x7F, 0x00, 0x08, + 0x81, 0x20, 0x08, 0x83, 0x40, 0x08, 0x85, 0x60, 0x08, 0x87, 0x80, 0x08, 0x89, 0xF0, 0xFF, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; +#endif + +// File Attributes +// 0 0x01 Read Only. +// 1 0x02 Hidden. +// 2 0x04 System. +// 3 0x08 Volume Label. +// 4 0x10 Subdirectory. +// 5 0x20 Archive. +// 6 0x40 Device. +// 7 0x80 Reserved. + +typedef struct +{ + uint8_t name[8]; + uint8_t ext[3]; + uint8_t attribute; + uint8_t reserved; + uint8_t create_time_ms; + uint16_t create_time; + uint16_t create_date; + uint16_t access_date; + uint16_t ea_index; + uint16_t modify_time; + uint16_t modify_date; + uint16_t start_cluster; + uint32_t file_size; +} FATDirEntry_t; + +// First 16 FAT root directory entries (1 sector) +const FATDirEntry_t g_DIRroot[16] = +{ + { +#ifdef PCBTARANIS + { 'T', 'A', 'R', 'A', 'N', 'I', 'S', ' '}, + { ' ', ' ', ' '}, +#else + { 'E', 'R', 'S', 'K', 'Y', '_', '9', 'X'}, + { ' ', ' ', ' '}, +#endif + 0x08, // Volume + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + }, + { +#ifdef PCBTARANIS + { 'T', 'A', 'R', 'A', 'N', 'I', 'S', ' '}, + { 'B', 'I', 'N'}, +#else + { 'E', 'R', 'S', 'K', 'Y', '9', 'X', ' '}, + { 'B', 'I', 'N'}, +#endif + 0x24, // Archive, hidden, system + 0x00, + 0x3E, + 0xA301, + 0x3D55, + 0x3D55, + 0x0000, + 0xA302, + 0x3D55, + 0x0002, + EESIZE + }, + { + { 'F', 'I', 'R', 'M', 'W', 'A', 'R', 'E'}, + { 'B', 'I', 'N'}, + 0x24, // Archive, hidden, system + 0x00, + 0x3E, + 0xA301, + 0x3D55, + 0x3D55, + 0x0000, + 0xA302, + 0x3D55, + 0x000A, + 0x00080000 // 512K + }, + { + { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x00, + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + }, + { + { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x00, + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + }, + { + { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x00, + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + }, + { + { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x00, + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + }, + { + { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x00, + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + }, + { + { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x00, + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + }, + { + { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x00, + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + }, + { + { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x00, + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + }, + { + { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x00, + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + }, + { + { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x00, + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + }, + { + { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x00, + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + }, + { + { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x00, + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + }, + { + { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, + { ' ', ' ', ' '}, + 0x00, + 0x00, + 0x00, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x00000000 + }, +}; + +// count is number of 512 byte sectors +int32_t fat12Read( uint8_t *buffer, uint16_t sector, uint16_t count ) +{ + while ( count ) + { + if (sector == 0) { + memcpy( buffer, g_FATboot, BLOCKSIZE ) ; + } + else if (sector == 1/*Reserved sector count*/) { + // FAT table. + memcpy( buffer, g_FAT, BLOCKSIZE); + } + else if (sector == 2) { + memcpy( buffer, g_DIRroot, BLOCKSIZE ) ; + } + else if ( sector < 67 ) + { + eeprom_read_block (buffer, (sector-3)*BLOCKSIZE, BLOCKSIZE); + } + else if ( sector < 1155 ) + { + uint32_t address ; + address = sector - 67 ; + address *= 512 ; + address += 0x08000000 ; + memcpy( buffer, (uint8_t *)address, BLOCKSIZE ) ; + } + buffer += BLOCKSIZE ; + sector++ ; + count-- ; + } + return 0 ; +} +//------------------------------------------------------------------------------ + +extern uint32_t program( uint32_t *address, uint32_t *buffer ) ; // size is 256 bytes + +uint32_t isValidEepromStart( const uint8_t *buffer ) +{ + uint32_t size ; + uint32_t bs ; + // Check Taranis format + size = buffer[1] + ( buffer[2] << 8 ) ; + bs = buffer[5] ; + if ( ( size == 0x0100 ) && ( bs == 0x40 ) ) + { + return 1 ; + } + size = buffer[1] ; + bs = buffer[3] ; + if ( ( size == 0x0080 ) && ( bs == 0x80 ) ) + { + return 1 ; + } + return 0 ; +} + + +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +int32_t fat12Write(const uint8_t *buffer, uint16_t sector, uint32_t count ) +{ + static int offset = 0; + +// TRACE("FAT12 Write(sector=%d, count=%d)", sector, count); + + if ( sector >= 3 ) + { + if ( sector < 67 ) + { + while (count) + { + if (offset == 0 && sector == 3 &&/*test->version==EEFS_VERS && */ isValidEepromStart( buffer ) ) + { +// TRACE("EEPROM start found in sector %d", sector); + offset = sector; + } + if (offset && sector >= offset && (sector-offset) < EESIZE/BLOCKSIZE) + { + eeWriteBlockCmp((uint8_t *)buffer, (sector-offset)*BLOCKSIZE, BLOCKSIZE); + } + buffer += BLOCKSIZE; + sector++; + count--; + if (sector-offset >= EESIZE/BLOCKSIZE) + { +// TRACE("EEPROM end written at sector %d", sector-1); + offset = 0; + } + } + } + else if ( sector < 1155 ) + { + // firmware + uint32_t address ; + address = sector - 67 ; + address *= 512 ; + address += 0x08000000 ; + + uint32_t i ; + while ( count ) + { + for ( i = 0 ; i < 2 ; i += 1 ) + { + if ( address >= 0x08008000 ) // Protect bootloader + { + if ( address < (0x08000000 + (512*1024) - 256) ) // in range + { + program( (uint32_t *)address, (uint32_t *) buffer ) ; // size is 256 bytes + } + } + address += 256 ; + buffer += 256 ; + } + count -= 1 ; + } + } + } + return 0 ; +} + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/radio/bootloader/usbd_usr.cpp b/radio/bootloader/usbd_usr.cpp new file mode 100644 index 000000000..dd78aba75 --- /dev/null +++ b/radio/bootloader/usbd_usr.cpp @@ -0,0 +1,126 @@ +/** + ****************************************************************************** + * @file usbd_usr.c + * @author MCD Application Team + * @version V1.1.0 + * @date 19-March-2012 + * @brief This file includes the user application layer + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "radio.h" + +extern "C" { +#include "usbd_usr.h" + +/* Points to the DEVICE_PROP structure of current device */ +/* The purpose of this register is to speed up the execution */ + + +USBD_Usr_cb_TypeDef USR_cb = +{ + USBD_USR_Init, + USBD_USR_DeviceReset, + USBD_USR_DeviceConfigured, + USBD_USR_DeviceSuspended, + USBD_USR_DeviceResumed, + + USBD_USR_DeviceConnected, + USBD_USR_DeviceDisconnected, +}; +} + +/** +* @brief Whatever the user application needs to do when USB is initialised +* @param None +* @retval None +*/ +void USBD_USR_Init(void) +{ + +} + +/** +* @brief Displays the message on LCD on device reset event +* @param speed : device speed +* @retval None +*/ +void USBD_USR_DeviceReset (uint8_t speed) +{ + +} + + +/** +* @brief Displays the message on LCD on device config event +* @param None +* @retval Staus +*/ +void USBD_USR_DeviceConfigured (void) +{ + +} +/** +* @brief Displays the message on LCD on device suspend event +* @param None +* @retval None +*/ +void USBD_USR_DeviceSuspended(void) +{ + +} + + +/** +* @brief Displays the message on LCD on device resume event +* @param None +* @retval None +*/ +void USBD_USR_DeviceResumed(void) +{ + +} + +/** +* @brief USBD_USR_DeviceConnected +* Displays the message on LCD on device connection Event +* @param None +* @retval Staus +*/ +void USBD_USR_DeviceConnected (void) +{ + +} + + +/** +* @brief USBD_USR_DeviceDisonnected +* Displays the message on LCD on device disconnection Event +* @param None +* @retval Staus +*/ +void USBD_USR_DeviceDisconnected (void) +{ +// NVIC_SystemReset(); +} + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/vectors_sam3s.c b/radio/bootloader/vectors_sam3s.c new file mode 100644 index 000000000..11f014cea --- /dev/null +++ b/radio/bootloader/vectors_sam3s.c @@ -0,0 +1,198 @@ +/**************************************************************************** +* Copyright (c) 2011 by Michael Fischer. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. Neither the name of the author nor the names of its contributors may +* be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +* SUCH DAMAGE. +* +**************************************************************************** +* History: +* +* 22.05.2011 mifi First Version for the SAM3S4C +****************************************************************************/ +#define __VECTORS_SAM3S_C__ + +/*=========================================================================*/ +/* DEFINE: All extern Data */ +/*=========================================================================*/ +extern unsigned long _estack; + +/*=========================================================================*/ +/* DEFINE: Prototypes */ +/*=========================================================================*/ +void ResetHandler(void); + +void NMI_Handler (void) __attribute__((weak)); +void HardFault_Handler (void) __attribute__((weak)); +void MemManage_Handler (void) __attribute__((weak)); +void BusFault_Handler (void) __attribute__((weak)); +void UsageFault_Handler (void) __attribute__((weak)); +void SVC_Handler (void) __attribute__((weak)); +void DebugMon_Handler (void) __attribute__((weak)); +void PendSV_Handler (void) __attribute__((weak)); +void SysTick_Handler (void) __attribute__((weak)); + +void SUPC_IRQHandler (void) __attribute__((weak)); +void RSTC_IRQHandler (void) __attribute__((weak)); +void RTC_IRQHandler (void) __attribute__((weak)); +void RTT_IRQHandler (void) __attribute__((weak)); +void WDT_IRQHandler (void) __attribute__((weak)); +void PMC_IRQHandler (void) __attribute__((weak)); +void EEFC_IRQHandler (void) __attribute__((weak)); +void UART0_IRQHandler (void) __attribute__((weak)); +void UART1_IRQHandler (void) __attribute__((weak)); +void SMC_IRQHandler (void) __attribute__((weak)); +void PIOA_IRQHandler (void) __attribute__((weak)); +void PIOB_IRQHandler (void) __attribute__((weak)); +void PIOC_IRQHandler (void) __attribute__((weak)); +void USART0_IRQHandler (void) __attribute__((weak)); +void USART1_IRQHandler (void) __attribute__((weak)); +void MCI_IRQHandler (void) __attribute__((weak)); +void TWI0_IRQHandler (void) __attribute__((weak)); +void TWI1_IRQHandler (void) __attribute__((weak)); +void SPI_IRQHandler (void) __attribute__((weak)); +void SSC_IRQHandler (void) __attribute__((weak)); +void TC0_IRQHandler (void) __attribute__((weak)); +void TC1_IRQHandler (void) __attribute__((weak)); +void TC2_IRQHandler (void) __attribute__((weak)); +void TC3_IRQHandler (void) __attribute__((weak)); +void TC4_IRQHandler (void) __attribute__((weak)); +void TC5_IRQHandler (void) __attribute__((weak)); +void ADC_IRQHandler (void) __attribute__((weak)); +void DAC_IRQHandler (void) __attribute__((weak)); +void PWM_IRQHandler (void) __attribute__((weak)); +void CRCCU_IRQHandler (void) __attribute__((weak)); +void ACC_IRQHandler (void) __attribute__((weak)); +void USBD_IRQHandler (void) __attribute__((weak)); + +/*=========================================================================*/ +/* DEFINE: All code exported */ +/*=========================================================================*/ +/* + * This is our vector table. + */ +__attribute__ ((section(".vectors"), used)) +void (* const gVectors[])(void) = +{ + (void (*)(void))((unsigned long)&_estack), + ResetHandler, + NMI_Handler, + HardFault_Handler, + MemManage_Handler, + BusFault_Handler, + UsageFault_Handler, + 0, 0, 0, 0, + SVC_Handler, + DebugMon_Handler, + 0, + PendSV_Handler, + SysTick_Handler, + + SUPC_IRQHandler, /* 0 SUPPLY CONTROLLER */ + RSTC_IRQHandler, /* 1 RESET CONTROLLER */ + RTC_IRQHandler, /* 2 REAL TIME CLOCK */ + RTT_IRQHandler, /* 3 REAL TIME TIMER */ + WDT_IRQHandler, /* 4 WATCHDOG TIMER */ + PMC_IRQHandler, /* 5 PMC */ + EEFC_IRQHandler, /* 6 EEFC */ + 0, /* 7 Reserved */ + UART0_IRQHandler, /* 8 UART0 */ + UART1_IRQHandler, /* 9 UART1 */ + SMC_IRQHandler, /* 10 SMC */ + PIOA_IRQHandler, /* 11 Parallel IO Controller A */ + PIOB_IRQHandler, /* 12 Parallel IO Controller B */ + PIOC_IRQHandler, /* 13 Parallel IO Controller C */ + USART0_IRQHandler, /* 14 USART 0 */ + USART1_IRQHandler, /* 15 USART 1 */ + 0, /* 16 Reserved */ + 0, /* 17 Reserved */ + MCI_IRQHandler, /* 18 MCI */ + TWI0_IRQHandler, /* 19 TWI 0 */ + TWI1_IRQHandler, /* 20 TWI 1 */ + SPI_IRQHandler, /* 21 SPI */ + SSC_IRQHandler, /* 22 SSC */ + TC0_IRQHandler, /* 23 Timer Counter 0 */ + TC1_IRQHandler, /* 24 Timer Counter 1 */ + TC2_IRQHandler, /* 25 Timer Counter 2 */ + TC3_IRQHandler, /* 26 Timer Counter 3 */ + TC4_IRQHandler, /* 27 Timer Counter 4 */ + TC5_IRQHandler, /* 28 Timer Counter 5 */ + ADC_IRQHandler, /* 29 ADC controller */ + DAC_IRQHandler, /* 30 DAC controller */ + PWM_IRQHandler, /* 31 PWM */ + CRCCU_IRQHandler, /* 32 CRC Calculation Unit */ + ACC_IRQHandler, /* 33 Analog Comparator */ + USBD_IRQHandler, /* 34 USB Device Port */ + 0 /* 35 not used */ +}; /* gVectors */ + +/* + * And here are the weak interrupt handlers. + */ +void NMI_Handler (void) { while(1); } +void HardFault_Handler (void) { while(1); } +void MemManage_Handler (void) { while(1); } +void BusFault_Handler (void) { while(1); } +void UsageFault_Handler (void) { while(1); } +void SVC_Handler (void) { while(1); } +void DebugMon_Handler (void) { while(1); } +void PendSV_Handler (void) { while(1); } +void SysTick_Handler (void) { while(1); } + +void SUPC_IRQHandler (void) { while(1); } +void RSTC_IRQHandler (void) { while(1); } +void RTC_IRQHandler (void) { while(1); } +void RTT_IRQHandler (void) { while(1); } +void WDT_IRQHandler (void) { while(1); } +void PMC_IRQHandler (void) { while(1); } +void EEFC_IRQHandler (void) { while(1); } +void UART0_IRQHandler (void) { while(1); } +void UART1_IRQHandler (void) { while(1); } +void SMC_IRQHandler (void) { while(1); } +void PIOA_IRQHandler (void) { while(1); } +void PIOB_IRQHandler (void) { while(1); } +void PIOC_IRQHandler (void) { while(1); } +void USART0_IRQHandler (void) { while(1); } +void USART1_IRQHandler (void) { while(1); } +void MCI_IRQHandler (void) { while(1); } +void TWI0_IRQHandler (void) { while(1); } +void TWI1_IRQHandler (void) { while(1); } +void SPI_IRQHandler (void) { while(1); } +void SSC_IRQHandler (void) { while(1); } +void TC0_IRQHandler (void) { while(1); } +void TC1_IRQHandler (void) { while(1); } +void TC2_IRQHandler (void) { while(1); } +void TC3_IRQHandler (void) { while(1); } +void TC4_IRQHandler (void) { while(1); } +void TC5_IRQHandler (void) { while(1); } +void ADC_IRQHandler (void) { while(1); } +void DAC_IRQHandler (void) { while(1); } +void PWM_IRQHandler (void) { while(1); } +void CRCCU_IRQHandler (void) { while(1); } +void ACC_IRQHandler (void) { while(1); } +void USBD_IRQHandler (void) { while(1); } +// void USBD_IRQHandler (void) { while(1); } + +/*** EOF ***/ diff --git a/radio/bootloader/x9ddiskio.cpp b/radio/bootloader/x9ddiskio.cpp new file mode 100644 index 000000000..1fce8b45c --- /dev/null +++ b/radio/bootloader/x9ddiskio.cpp @@ -0,0 +1,1008 @@ +/* + * Authors (alphabetical order) + * - Andre Bernet + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * open9x is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include "radio.h" +#include "diskio.h" +#include "ff.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_rcc.h" +#include "logicio.h" +#include "hal.h" + +#define BOOL bool +#define FALSE false +#define TRUE true + +/* Definitions for MMC/SDC command */ +#define CMD0 (0x40+0) /* GO_IDLE_STATE */ +#define CMD1 (0x40+1) /* SEND_OP_COND (MMC) */ +#define ACMD41 (0xC0+41) /* SEND_OP_COND (SDC) */ +#define CMD8 (0x40+8) /* SEND_IF_COND */ +#define CMD9 (0x40+9) /* SEND_CSD */ +#define CMD10 (0x40+10) /* SEND_CID */ +#define CMD12 (0x40+12) /* STOP_TRANSMISSION */ +#define ACMD13 (0xC0+13) /* SD_STATUS (SDC) */ +#define CMD16 (0x40+16) /* SET_BLOCKLEN */ +#define CMD17 (0x40+17) /* READ_SINGLE_BLOCK */ +#define CMD18 (0x40+18) /* READ_MULTIPLE_BLOCK */ +#define CMD23 (0x40+23) /* SET_BLOCK_COUNT (MMC) */ +#define ACMD23 (0xC0+23) /* SET_WR_BLK_ERASE_COUNT (SDC) */ +#define CMD24 (0x40+24) /* WRITE_BLOCK */ +#define CMD25 (0x40+25) /* WRITE_MULTIPLE_BLOCK */ +#define CMD55 (0x40+55) /* APP_CMD */ +#define CMD58 (0x40+58) /* READ_OCR */ + +/* Card-Select Controls (Platform dependent) */ +#define SELECT() GPIO_ResetBits(GPIO_SPI_SD, GPIO_Pin_SPI_SD_CS) /* MMC CS = L */ +#define DESELECT() GPIO_SetBits(GPIO_SPI_SD, GPIO_Pin_SPI_SD_CS) /* MMC CS = H */ + +#if (_MAX_SS != 512) || (_FS_READONLY == 0) || (STM32_SD_DISK_IOCTRL_FORCE == 1) +#define STM32_SD_DISK_IOCTRL 1 +#else +#define STM32_SD_DISK_IOCTRL 0 +#endif + +#define BOOL bool +//#define FALSE false +//#define TRUE true + +/* Card type flags (CardType) */ +#define CT_MMC 0x01 +#define CT_SD1 0x02 +#define CT_SD2 0x04 +#define CT_SDC (CT_SD1|CT_SD2) +#define CT_BLOCK 0x08 + +int32_t Card_state; // = SD_ST_STARTUP ; +/*uint32_t Card_ID[4] ; +uint32_t Card_SCR[2] ; +uint32_t Card_CSD[4] ; +volatile uint32_t Card_initialized = 0; +uint32_t Sd_rca ; +uint32_t Cmd_A41_resp ; +uint8_t cardType; +uint32_t transSpeed; */ + +/*-----------------------------------------------------------------------*/ +/* Lock / unlock functions */ +/*-----------------------------------------------------------------------*/ +//int ff_cre_syncobj (BYTE vol, _SYNC_t *mutex) +//{ +// *mutex = CoCreateMutex(); +// return 1; +//} + +//int ff_req_grant (_SYNC_t mutex) +//{ +// CoEnterMutexSection(mutex); +// return 1; +//} + +//void ff_rel_grant (_SYNC_t mutex) +//{ +// CoLeaveMutexSection(mutex); +//} + +//int ff_del_syncobj (_SYNC_t mutex) +//{ +// return 1; +//} + +static const DWORD socket_state_mask_cp = (1 << 0); +static const DWORD socket_state_mask_wp = (1 << 1); + +static volatile +DSTATUS Stat = STA_NOINIT; /* Disk status */ + +static volatile +DWORD Timer1, Timer2; /* 100Hz decrement timers */ + +//static +BYTE CardType; /* Card type flags */ + +enum speed_setting { INTERFACE_SLOW, INTERFACE_FAST }; + +static void interface_speed( enum speed_setting speed ) +{ + DWORD tmp; + + tmp = SPI_SD->CR1; + if ( speed == INTERFACE_SLOW ) { + /* Set slow clock (100k-400k) */ + tmp = ( tmp | SPI_BaudRatePrescaler_128 ); + } else { + /* Set fast clock (depends on the CSD) */ + tmp = ( tmp & ~SPI_BaudRatePrescaler_128 ) | SPI_BaudRatePrescaler_SPI_SD; + } + SPI_SD->CR1 = tmp; +} + +static void socket_wp_init(void) +{ + return; +} + +static inline DWORD socket_is_write_protected(void) +{ + return 0; /* fake not protected */ +} + +static void socket_cp_init(void) +{ + return; +} + +DWORD socket_is_empty(void) +{ +// return 0; /* fake inserted */ + return GPIOD->IDR & GPIO_Pin_9 ; +} + +static void card_power(BYTE on) +{ + on=on; +} + +//#if (STM32_SD_DISK_IOCTRL == 1) +static int chk_power(void) +{ + return 1; /* fake powered */ +} +//#endif + +/*-----------------------------------------------------------------------*/ +/* Transmit/Receive a byte to MMC via SPI (Platform dependent) */ +/*-----------------------------------------------------------------------*/ +static BYTE stm32_spi_rw( BYTE out ) +{ + /* Loop while DR register in not empty */ + /// not needed: while (SPI_I2S_GetFlagStatus(SPI_SD, SPI_I2S_FLAG_TXE) == RESET) { ; } + + /* Send byte through the SPI peripheral */ + SPI_I2S_SendData(SPI_SD, out); + + /* Wait to receive a byte */ + while (SPI_I2S_GetFlagStatus(SPI_SD, SPI_I2S_FLAG_RXNE) == RESET) { ; } + + /* Return the byte read from the SPI bus */ + return SPI_I2S_ReceiveData(SPI_SD); +} + + + +/*-----------------------------------------------------------------------*/ +/* Transmit a byte to MMC via SPI (Platform dependent) */ +/*-----------------------------------------------------------------------*/ + +#define xmit_spi(dat) stm32_spi_rw(dat) + +/*-----------------------------------------------------------------------*/ +/* Receive a byte from MMC via SPI (Platform dependent) */ +/*-----------------------------------------------------------------------*/ + +static +BYTE rcvr_spi (void) +{ + return stm32_spi_rw(0xff); +} + +/* Alternative macro to receive data fast */ +#define rcvr_spi_m(dst) *(dst)=stm32_spi_rw(0xff) + + + +/*-----------------------------------------------------------------------*/ +/* Wait for card ready */ +/*-----------------------------------------------------------------------*/ + +static +BYTE wait_ready (void) +{ + BYTE res; + + + Timer2 = 50; /* Wait for ready in timeout of 500ms */ + rcvr_spi(); + do + res = rcvr_spi(); + while ((res != 0xFF) && Timer2); + + return res; +} + + + +/*-----------------------------------------------------------------------*/ +/* Deselect the card and release SPI bus */ +/*-----------------------------------------------------------------------*/ + +static +void release_spi (void) +{ + DESELECT(); + rcvr_spi(); +} + +#ifdef STM32_SD_USE_DMA +/*-----------------------------------------------------------------------*/ +/* Transmit/Receive Block using DMA (Platform dependent. STM32 here) */ +/*-----------------------------------------------------------------------*/ +static +void stm32_dma_transfer( + BOOL receive, /* FALSE for buff->SPI, TRUE for SPI->buff */ + const BYTE *buff, /* receive TRUE : 512 byte data block to be transmitted + receive FALSE : Data buffer to store received data */ + UINT btr /* receive TRUE : Byte count (must be multiple of 2) + receive FALSE : Byte count (must be 512) */ +) +{ + DMA_InitTypeDef DMA_InitStructure; + WORD rw_workbyte[] = { 0xffff }; + + /* shared DMA configuration values */ + DMA_InitStructure.DMA_PeripheralBaseAddr = (DWORD)(&(SPI_SD->DR)); + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_BufferSize = btr; + DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; + DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; + DMA_InitStructure.DMA_M2M = DMA_M2M_Disable; + + DMA_DeInit(DMA_Channel_SPI_SD_RX); + DMA_DeInit(DMA_Channel_SPI_SD_TX); + + if ( receive ) { + + /* DMA1 channel2 configuration SPI1 RX ---------------------------------------------*/ + /* DMA1 channel4 configuration SPI2 RX ---------------------------------------------*/ + DMA_InitStructure.DMA_MemoryBaseAddr = (DWORD)buff; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_Init(DMA_Channel_SPI_SD_RX, &DMA_InitStructure); + + /* DMA1 channel3 configuration SPI1 TX ---------------------------------------------*/ + /* DMA1 channel5 configuration SPI2 TX ---------------------------------------------*/ + DMA_InitStructure.DMA_MemoryBaseAddr = (DWORD)rw_workbyte; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable; + DMA_Init(DMA_Channel_SPI_SD_TX, &DMA_InitStructure); + + } else { + +//#if _FS_READONLY == 0 + /* DMA1 channel2 configuration SPI1 RX ---------------------------------------------*/ + /* DMA1 channel4 configuration SPI2 RX ---------------------------------------------*/ + DMA_InitStructure.DMA_MemoryBaseAddr = (DWORD)rw_workbyte; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable; + DMA_Init(DMA_Channel_SPI_SD_RX, &DMA_InitStructure); + + /* DMA1 channel3 configuration SPI1 TX ---------------------------------------------*/ + /* DMA1 channel5 configuration SPI2 TX ---------------------------------------------*/ + DMA_InitStructure.DMA_MemoryBaseAddr = (DWORD)buff; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_Init(DMA_Channel_SPI_SD_TX, &DMA_InitStructure); +//#endif + + } + + /* Enable DMA RX Channel */ + DMA_Cmd(DMA_Channel_SPI_SD_RX, ENABLE); + /* Enable DMA TX Channel */ + DMA_Cmd(DMA_Channel_SPI_SD_TX, ENABLE); + + /* Enable SPI TX/RX request */ + SPI_I2S_DMACmd(SPI_SD, SPI_I2S_DMAReq_Rx | SPI_I2S_DMAReq_Tx, ENABLE); + + /* Wait until DMA1_Channel 3 Transfer Complete */ + /// not needed: while (DMA_GetFlagStatus(DMA_FLAG_SPI_SD_TC_TX) == RESET) { ; } + /* Wait until DMA1_Channel 2 Receive Complete */ + while (DMA_GetFlagStatus(DMA_FLAG_SPI_SD_TC_RX) == RESET) { ; } + // same w/o function-call: + // while ( ( ( DMA1->ISR ) & DMA_FLAG_SPI_SD_TC_RX ) == RESET ) { ; } + + /* Disable DMA RX Channel */ + DMA_Cmd(DMA_Channel_SPI_SD_RX, DISABLE); + /* Disable DMA TX Channel */ + DMA_Cmd(DMA_Channel_SPI_SD_TX, DISABLE); + + /* Disable SPI RX/TX request */ + SPI_I2S_DMACmd(SPI_SD, SPI_I2S_DMAReq_Rx | SPI_I2S_DMAReq_Tx, DISABLE); +} +#endif /* STM32_SD_USE_DMA */ + + +/*-----------------------------------------------------------------------*/ +/* Power Control and interface-initialization (Platform dependent) */ +/*-----------------------------------------------------------------------*/ + +static void power_on (void) +{ + SPI_InitTypeDef SPI_InitStructure; + GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable GPIO clock for CS */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIO_CS, ENABLE); + /* Enable SPI clock, SPI1: APB2, SPI2: APB1 */ + RCC_APBPeriphClockCmd_SPI_SD(RCC_APBPeriph_SPI_SD, ENABLE); + + GPIO_PinAFConfig(GPIO_SPI_SD,GPIO_PinSource_SCK ,GPIO_AF_SD); + GPIO_PinAFConfig(GPIO_SPI_SD,GPIO_PinSource_MISO,GPIO_AF_SD); + GPIO_PinAFConfig(GPIO_SPI_SD,GPIO_PinSource_MOSI,GPIO_AF_SD); + + card_power(1); + + socket_cp_init();//Empty return + socket_wp_init();//Empty return. + +#ifdef BOOT +extern void hw_delay( uint16_t time ) ; + uint32_t count = 125 ; + do + { + hw_delay(20000) ; + wdt_reset() ; + } while ( --count ) ; +#else + CoTickDelay(125); +#endif + // for (Timer1 = 25; Timer1; ); /* Wait for 250ms */ + + /* SPI configuration */ + SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStructure.SPI_Mode = SPI_Mode_Master; + SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; + SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; + SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; + SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; + SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_SPI_SD; // + SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; + SPI_InitStructure.SPI_CRCPolynomial = 7; + + SPI_Init(SPI_SD, &SPI_InitStructure); + SPI_CalculateCRC(SPI_SD, DISABLE); + SPI_Cmd(SPI_SD, ENABLE); + + /* De-select the Card: Chip Select high */ + DESELECT(); + + /* Configure I/O for Flash Chip select */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_SPI_SD_CS; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIO_SPI_SD, &GPIO_InitStructure); + + /* Configure SPI pins: SCK MISO and MOSI with alternate function push-down */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_SPI_SD_SCK | GPIO_Pin_SPI_SD_MOSI ; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(GPIO_SPI_SD, &GPIO_InitStructure); + + /* Configure SPI pins: SCK MISO and MOSI with alternate function push-down */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_SPI_SD_MISO; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(GPIO_SPI_SD, &GPIO_InitStructure); + +#ifdef STM32_SD_USE_DMA + /* enable DMA clock */ + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE); +#endif +} + +static +void power_off (void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + if (!(Stat & STA_NOINIT)) { + SELECT(); + wait_ready(); + release_spi(); + } + + SPI_I2S_DeInit(SPI_SD); + SPI_Cmd(SPI_SD, DISABLE); + RCC_APBPeriphClockCmd_SPI_SD(RCC_APBPeriph_SPI_SD, DISABLE); + + //All SPI-Pins to input with weak internal pull-downs // + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_SPI_SD_SCK | GPIO_Pin_SPI_SD_MISO | GPIO_Pin_SPI_SD_MOSI; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; + GPIO_Init(GPIO_SPI_SD, &GPIO_InitStructure); + + card_power(0); + + Stat |= STA_NOINIT; /* Set STA_NOINIT */ +} + + +/*-----------------------------------------------------------------------*/ +/* Receive a data packet from MMC */ +/*-----------------------------------------------------------------------*/ + +static +BOOL rcvr_datablock ( + BYTE *buff, /* Data buffer to store received data */ + UINT btr /* Byte count (must be multiple of 4) */ +) +{ + BYTE token; + + + Timer1 = 10; + do { /* Wait for data packet in timeout of 100ms */ + token = rcvr_spi(); + } while ((token == 0xFF) && Timer1); + if(token != 0xFE) return FALSE; /* If not valid data token, return with error */ + +#ifdef STM32_SD_USE_DMA + stm32_dma_transfer( TRUE, buff, btr ); +#else + do { /* Receive the data block into buffer */ + rcvr_spi_m(buff++); + rcvr_spi_m(buff++); + rcvr_spi_m(buff++); + rcvr_spi_m(buff++); + } while (btr -= 4); +#endif /* STM32_SD_USE_DMA */ + + rcvr_spi(); /* Discard CRC */ + rcvr_spi(); + + return TRUE; /* Return with success */ +} + + + +/*-----------------------------------------------------------------------*/ +/* Send a data packet to MMC */ +/*-----------------------------------------------------------------------*/ + +//#if _FS_READONLY == 0 +static +BOOL xmit_datablock ( + const BYTE *buff, /* 512 byte data block to be transmitted */ + BYTE token /* Data/Stop token */ +) +{ + BYTE resp; +#ifndef STM32_SD_USE_DMA + BYTE wc; +#endif + + if (wait_ready() != 0xFF) return FALSE; + + xmit_spi(token); /* transmit data token */ + if (token != 0xFD) { /* Is data token */ + +#ifdef STM32_SD_USE_DMA + stm32_dma_transfer( FALSE, buff, 512 ); +#else + wc = 0; + do { /* transmit the 512 byte data block to MMC */ + xmit_spi(*buff++); + xmit_spi(*buff++); + } while (--wc); +#endif /* STM32_SD_USE_DMA */ + + xmit_spi(0xFF); /* CRC (Dummy) */ + xmit_spi(0xFF); + resp = rcvr_spi(); /* Receive data response */ + if ((resp & 0x1F) != 0x05) /* If not accepted, return with error */ + return FALSE; + } + + return TRUE; +} +//#endif /* _READONLY */ + + + +/*-----------------------------------------------------------------------*/ +/* Send a command packet to MMC */ +/*-----------------------------------------------------------------------*/ + +static +BYTE send_cmd ( + BYTE cmd, /* Command byte */ + DWORD arg /* Argument */ +) +{ + BYTE n, res; + + + if (cmd & 0x80) { /* ACMD is the command sequence of CMD55-CMD */ + cmd &= 0x7F; + res = send_cmd(CMD55, 0); + if (res > 1) return res; + } + + /* Select the card and wait for ready */ + SELECT(); + if (wait_ready() != 0xFF) { + return 0xFF; + } + + /* Send command packet */ + xmit_spi(cmd); /* Start + Command index */ + xmit_spi((BYTE)(arg >> 24)); /* Argument[31..24] */ + xmit_spi((BYTE)(arg >> 16)); /* Argument[23..16] */ + xmit_spi((BYTE)(arg >> 8)); /* Argument[15..8] */ + xmit_spi((BYTE)arg); /* Argument[7..0] */ + n = 0x01; /* Dummy CRC + Stop */ + if (cmd == CMD0) n = 0x95; /* Valid CRC for CMD0(0) */ + if (cmd == CMD8) n = 0x87; /* Valid CRC for CMD8(0x1AA) */ + xmit_spi(n); + + /* Receive command response */ + if (cmd == CMD12) rcvr_spi(); /* Skip a stuff byte when stop reading */ + + n = 10; /* Wait for a valid response in timeout of 10 attempts */ + do + res = rcvr_spi(); + while ((res & 0x80) && --n); + + return res; /* Return with the response value */ +} + + + +/*-------------------------------------------------------------------------- + + Public Functions + +---------------------------------------------------------------------------*/ + + +/*-----------------------------------------------------------------------*/ +/* Initialize Disk Drive */ +/*-----------------------------------------------------------------------*/ + +DSTATUS disk_initialize ( + BYTE drv /* Physical drive number (0) */ +) +{ + BYTE n, cmd, ty, ocr[4]; + + if (drv) return STA_NOINIT; /* Supports only single drive */ + if (Stat & STA_NODISK) return Stat; /* No card in the socket */ + + power_on(); /* Force socket power on and initialize interface */ + interface_speed(INTERFACE_SLOW); + for (n = 10; n; n--) rcvr_spi(); /* 80 dummy clocks */ + + ty = 0; + if (send_cmd(CMD0, 0) == 1) { /* Enter Idle state */ + Timer1 = 100; /* Initialization timeout of 1000 milliseconds */ + if (send_cmd(CMD8, 0x1AA) == 1) { /* SDHC */ + for (n = 0; n < 4; n++) ocr[n] = rcvr_spi(); /* Get trailing return value of R7 response */ + if (ocr[2] == 0x01 && ocr[3] == 0xAA) { /* The card can work at VDD range of 2.7-3.6V */ + while (Timer1 && send_cmd(ACMD41, 1UL << 30)); /* Wait for leaving idle state (ACMD41 with HCS bit) */ + if (Timer1 && send_cmd(CMD58, 0) == 0) { /* Check CCS bit in the OCR */ + for (n = 0; n < 4; n++) ocr[n] = rcvr_spi(); + ty = (ocr[0] & 0x40) ? CT_SD2 | CT_BLOCK : CT_SD2; + } + } + } else { /* SDSC or MMC */ + if (send_cmd(ACMD41, 0) <= 1) { + ty = CT_SD1; cmd = ACMD41; /* SDSC */ + } else { + ty = CT_MMC; cmd = CMD1; /* MMC */ + } + while (Timer1 && send_cmd(cmd, 0)); /* Wait for leaving idle state */ + if (!Timer1 || send_cmd(CMD16, 512) != 0) /* Set R/W block length to 512 */ + ty = 0; + } + } + CardType = ty; + release_spi(); + + if (ty) { /* Initialization succeeded */ + Stat &= ~STA_NOINIT; /* Clear STA_NOINIT */ + interface_speed(INTERFACE_FAST); + } else { /* Initialization failed */ +// power_off(); + } + + return Stat; +} + + + +/*-----------------------------------------------------------------------*/ +/* Get Disk Status */ +/*-----------------------------------------------------------------------*/ + +DSTATUS disk_status ( + BYTE drv /* Physical drive number (0) */ +) +{ + if (drv) return STA_NOINIT; /* Supports only single drive */ + return Stat; +} + + + +/*-----------------------------------------------------------------------*/ +/* Read Sector(s) */ +/*-----------------------------------------------------------------------*/ + +// TODO quick & dirty +int8_t SD_ReadSectors(uint8_t *buff, uint32_t sector, uint32_t count) +{ + if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert to byte address if needed */ + + if (send_cmd(CMD18, sector) == 0) { /* READ_MULTIPLE_BLOCK */ + do { + if (!rcvr_datablock(buff, 512)) { + break; + } + buff += 512; + } while (--count); + send_cmd(CMD12, 0); /* STOP_TRANSMISSION */ + } + + release_spi(); + + return 0; +} + +DRESULT disk_read ( + BYTE drv, /* Physical drive number (0) */ + BYTE *buff, /* Pointer to the data buffer to store read data */ + DWORD sector, /* Start sector number (LBA) */ + BYTE count /* Sector count (1..255) */ +) +{ + if (drv || !count) return RES_PARERR; + if (Stat & STA_NOINIT) return RES_NOTRDY; + + if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert to byte address if needed */ + + if (count == 1) { /* Single block read */ + if (send_cmd(CMD17, sector) == 0) { /* READ_SINGLE_BLOCK */ + if (rcvr_datablock(buff, 512)) { + count = 0; + } + } + } + else { /* Multiple block read */ + if (send_cmd(CMD18, sector) == 0) { /* READ_MULTIPLE_BLOCK */ + do { + if (!rcvr_datablock(buff, 512)) { + break; + } + buff += 512; + } while (--count); + send_cmd(CMD12, 0); /* STOP_TRANSMISSION */ + } + } + release_spi(); + + return count ? RES_ERROR : RES_OK; +} + + + +/*-----------------------------------------------------------------------*/ +/* Write Sector(s) */ +/*-----------------------------------------------------------------------*/ + +//#if _FS_READONLY == 0 + +// TODO quick & dirty +int8_t SD_WriteSectors(uint8_t *buff, uint32_t sector, uint32_t count) +{ + if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert to byte address if needed */ + if (CardType & CT_SDC) send_cmd(ACMD23, count); + if (send_cmd(CMD25, sector) == 0) { /* WRITE_MULTIPLE_BLOCK */ + do { + if (!xmit_datablock(buff, 0xFC)) break; + buff += 512; + } while (--count); + if (!xmit_datablock(0, 0xFD)) /* STOP_TRAN token */ + count = 1; + } + + release_spi(); + + return 0; +} + +DRESULT disk_write ( + BYTE drv, /* Physical drive number (0) */ + const BYTE *buff, /* Pointer to the data to be written */ + DWORD sector, /* Start sector number (LBA) */ + BYTE count /* Sector count (1..255) */ +) +{ + if (drv || !count) return RES_PARERR; + if (Stat & STA_NOINIT) return RES_NOTRDY; + if (Stat & STA_PROTECT) return RES_WRPRT; + + if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert to byte address if needed */ + + if (count == 1) { /* Single block write */ + if ((send_cmd(CMD24, sector) == 0) /* WRITE_BLOCK */ + && xmit_datablock(buff, 0xFE)) + count = 0; + } + else { /* Multiple block write */ + if (CardType & CT_SDC) send_cmd(ACMD23, count); + if (send_cmd(CMD25, sector) == 0) { /* WRITE_MULTIPLE_BLOCK */ + do { + if (!xmit_datablock(buff, 0xFC)) break; + buff += 512; + } while (--count); + if (!xmit_datablock(0, 0xFD)) /* STOP_TRAN token */ + count = 1; + } + } + release_spi(); + + return count ? RES_ERROR : RES_OK; +} +//#endif /* _READONLY == 0 */ + + + +/*-----------------------------------------------------------------------*/ +/* Miscellaneous Functions */ +/*-----------------------------------------------------------------------*/ + +//#if (STM32_SD_DISK_IOCTRL == 1) +DRESULT disk_ioctl ( + BYTE drv, /* Physical drive number (0) */ + BYTE ctrl, /* Control code */ + BYTE *buff /* Buffer to send/receive control data */ +) +{ + DRESULT res; + BYTE n, csd[16], *ptr = (BYTE *)buff; + WORD csize; + + if (drv) return RES_PARERR; + + res = RES_ERROR; + + if (ctrl == CTRL_POWER) { + switch (*ptr) { + case 0: /* Sub control code == 0 (POWER_OFF) */ + if (chk_power()) + power_off(); /* Power off */ + res = RES_OK; + break; + case 1: /* Sub control code == 1 (POWER_ON) */ + power_on(); /* Power on */ + res = RES_OK; + break; + case 2: /* Sub control code == 2 (POWER_GET) */ + *(ptr+1) = (BYTE)chk_power(); + res = RES_OK; + break; + default : + res = RES_PARERR; + } + } + else { + if (Stat & STA_NOINIT) return RES_NOTRDY; + + switch (ctrl) { + case CTRL_SYNC : /* Make sure that no pending write process */ + SELECT(); + if (wait_ready() == 0xFF) + res = RES_OK; + break; + + case GET_SECTOR_COUNT : /* Get number of sectors on the disk (DWORD) */ + if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { + if ((csd[0] >> 6) == 1) { /* SDC version 2.00 */ + csize = csd[9] + ((WORD)csd[8] << 8) + 1; + *(DWORD*)buff = (DWORD)csize << 10; + } else { /* SDC version 1.XX or MMC*/ + n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + ((csd[9] & 3) << 1) + 2; + csize = (csd[8] >> 6) + ((WORD)csd[7] << 2) + ((WORD)(csd[6] & 3) << 10) + 1; + *(DWORD*)buff = (DWORD)csize << (n - 9); + } + res = RES_OK; + } + break; + + case GET_SECTOR_SIZE : /* Get R/W sector size (WORD) */ + *(WORD*)buff = 512; + res = RES_OK; + break; + + case GET_BLOCK_SIZE : /* Get erase block size in unit of sector (DWORD) */ + if (CardType & CT_SD2) { /* SDC version 2.00 */ + if (send_cmd(ACMD13, 0) == 0) { /* Read SD status */ + rcvr_spi(); + if (rcvr_datablock(csd, 16)) { /* Read partial block */ + for (n = 64 - 16; n; n--) rcvr_spi(); /* Purge trailing data */ + *(DWORD*)buff = 16UL << (csd[10] >> 4); + res = RES_OK; + } + } + } else { /* SDC version 1.XX or MMC */ + if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { /* Read CSD */ + if (CardType & CT_SD1) { /* SDC version 1.XX */ + *(DWORD*)buff = (((csd[10] & 63) << 1) + ((WORD)(csd[11] & 128) >> 7) + 1) << ((csd[13] >> 6) - 1); + } else { /* MMC */ + *(DWORD*)buff = ((WORD)((csd[10] & 124) >> 2) + 1) * (((csd[11] & 3) << 3) + ((csd[11] & 224) >> 5) + 1); + } + res = RES_OK; + } + } + break; + + case MMC_GET_TYPE : /* Get card type flags (1 byte) */ + *ptr = CardType; + res = RES_OK; + break; + + case MMC_GET_CSD : /* Receive CSD as a data block (16 bytes) */ + if (send_cmd(CMD9, 0) == 0 /* READ_CSD */ + && rcvr_datablock(ptr, 16)) + res = RES_OK; + break; + + case MMC_GET_CID : /* Receive CID as a data block (16 bytes) */ + if (send_cmd(CMD10, 0) == 0 /* READ_CID */ + && rcvr_datablock(ptr, 16)) + res = RES_OK; + break; + + case MMC_GET_OCR : /* Receive OCR as an R3 resp (4 bytes) */ + if (send_cmd(CMD58, 0) == 0) { /* READ_OCR */ + for (n = 4; n; n--) *ptr++ = rcvr_spi(); + res = RES_OK; + } + break; + + case MMC_GET_SDSTAT : /* Receive SD status as a data block (64 bytes) */ + if (send_cmd(ACMD13, 0) == 0) { /* SD_STATUS */ + rcvr_spi(); + if (rcvr_datablock(ptr, 64)) + res = RES_OK; + } + break; + + default: + res = RES_PARERR; + } + + release_spi(); + } + + return res; +} +//#endif /* _USE_IOCTL != 0 */ + + +/*-----------------------------------------------------------------------*/ +/* Device Timer Interrupt Procedure (Platform dependent) */ +/*-----------------------------------------------------------------------*/ +/* This function must be called in period of 10ms */ + +void sdPoll10ms() +{ + static DWORD pv; + DWORD ns; + BYTE n, s; + + + n = Timer1; /* 100Hz decrement timers */ + if (n) Timer1 = --n; + n = Timer2; + if (n) Timer2 = --n; + + ns = pv; + pv = socket_is_empty() | socket_is_write_protected(); /* Sample socket switch */ + + if (ns == pv) { /* Have contacts stabled? */ + s = Stat; + + if (pv & socket_state_mask_wp) /* WP is H (write protected) */ + s |= STA_PROTECT; + else /* WP is L (write enabled) */ + s &= ~STA_PROTECT; + + if (pv & socket_state_mask_cp) /* INS = H (Socket empty) */ + s |= (STA_NODISK | STA_NOINIT); + else /* INS = L (Card inserted) */ + s &= ~STA_NODISK; + + Stat = s; + } +} + +FATFS g_FATFS_Obj; + +void sdInit() +{ + FRESULT fr ; + if (( fr = f_mount(0, &g_FATFS_Obj)) == FR_OK) + { + +// refreshSystemAudioFiles() ; + Card_state = 100 ; + } +} + +uint32_t sdMounted() +{ + // Should check for card present as well + return Card_state == 100 ; +} + +void sdMountPoll() +{ + /* TODO a define + static uint8_t mountTimer; + if (mountTimer-- == 0) { + mountTimer = 100; + if (!sdMounted()) { + sdInit(); + } + }*/ +} + + +// Checks for card ready for read/write +// returns 1 for YES, 0 for NO +uint32_t sd_card_ready( void ) +{ +// if ( CardIsConnected() ) +// { + if ( Card_state == 100 ) + { + return 1 ; + } +// } + return 0 ; +} + + diff --git a/radio/src/Makefile b/radio/src/Makefile index c5bf64f12..cdc10e396 100644 --- a/radio/src/Makefile +++ b/radio/src/Makefile @@ -250,6 +250,10 @@ GVARS = NO # Values = NO, READONLY, NOMENUS MENUS_LOCK == NO +# Include bootloader, for now only for Taranis +# Values = YES, NO +BOOTLOADER = YES + #------- END BUILD OPTIONS --------------------------- # Define programs and commands. @@ -257,6 +261,7 @@ SHELL = sh IMG2LBM = -python ../util/img2lbm.py TRANSLATE = -python ../util/translate.py SVNREV = $(shell sh -c "svnversion | egrep -o '[[:digit:]]+[[:alpha:]]*$$'") +BIN2LBM = -python ../util/bin2lbm.py SRC = CPPSRC = @@ -593,7 +598,11 @@ ifeq ($(PCB), TARANIS) else CPPDEFS = -DREV4 endif - LDSCRIPT = targets/taranis/stm32_flash.ld + ifeq ($(BOOTLOADER), YES) + LDSCRIPT = targets/taranis/stm32_flash_bl.ld + else + LDSCRIPT = targets/taranis/stm32_flash.ld + endif TRGT = arm-none-eabi- MCU = cortex-m3 OPT = 2 @@ -614,7 +623,6 @@ ifeq ($(PCB), TARANIS) CPPSRC += audio_arm.cpp CPPSRC += targets/taranis/pwr_driver.cpp targets/taranis/pulses_driver.cpp targets/taranis/keys_driver.cpp targets/taranis/adc_driver.cpp targets/taranis/trainer_driver.cpp targets/taranis/audio_driver.cpp targets/taranis/delays.cpp targets/taranis/uart_driver.cpp targets/taranis/sport_driver.cpp CPPSRC += bmp.cpp gui/view_channels.cpp gui/view_about.cpp gui/view_text.cpp - CPPSRC += loadboot.cpp SRC += targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c SRC += targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/misc.c SRC += targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_gpio.c @@ -664,6 +672,11 @@ ifeq ($(PCB), TARANIS) CPPSRC += protocols/hubsan.cpp CPPSRC += targets/taranis/a7105_driver.cpp endif + + ifeq ($(BOOTLOADER), YES) + CPPDEFS += -DBOOTLOADER + CPPSRC += loadboot.cpp + endif endif CC = $(TRGT)gcc @@ -1044,9 +1057,15 @@ all: begin gccversion sizebefore build sizeafter end ifeq ($(ARCH), AVR) build: stamp_header tra lbm allsrc.cpp elf remallsrc hex else - build: stamp_header tra lbm allsrc.cpp elf remallsrc bin + build: stamp_header tra lbm bootloader allsrc.cpp elf remallsrc bin endif +# build bootloader +.PHONY bootloader: + @echo "Building bootloader..." + $(MAKE) -C ../bootloader PCB=$(PCB) + $(BIN2LBM) bootloader.lbm ../bootloader/bootloader_ramBoot.bin + tra: translations/cz.h translations/de.h translations/es.h translations/fr.h translations/it.h translations/pl.h translations/pt.h translations/se.h lbm: fonts bitmaps/sticks.lbm @@ -1305,6 +1324,8 @@ clean_list : $(REMOVE) *.lst $(REMOVE) allsrc.cpp $(REMOVE) stamp-opentx.h + $(REMOVE) `find . -name "*.lbm"` + $(MAKE) -C ../bootloader clean #### Install diff --git a/radio/src/bootflashX.lbm b/radio/src/bootflashX.lbm deleted file mode 100644 index 88ef5f552..000000000 --- a/radio/src/bootflashX.lbm +++ /dev/null @@ -1,1939 +0,0 @@ -0x00,0x00,0x02,0x20,0xe5,0x63,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, -0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x29,0x64,0x00,0x20, -0x29,0x64,0x00,0x20,0x00,0x00,0x00,0x00,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, -0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, -0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, -0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, -0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, -0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, -0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, -0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, -0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, -0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, -0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, -0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, -0x29,0x64,0x00,0x20,0x0d,0x5e,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, -0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, -0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, -0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, -0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, -0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x59,0x5d,0x00,0x20, -0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, -0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, -0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20,0x29,0x64,0x00,0x20, -0x29,0x64,0x00,0x20,0x48,0x77,0x00,0x20,0x48,0x77,0x00,0x20,0x14,0x79,0x00,0x20, -0x14,0x79,0x00,0x20,0x38,0xb0,0x00,0x20,0x35,0x4b,0x82,0xb0,0x1a,0x68,0x42,0xf0, -0x01,0x02,0x1a,0x60,0x00,0x22,0x9a,0x60,0x19,0x68,0x21,0xf0,0x84,0x71,0x21,0xf4, -0x80,0x31,0x19,0x60,0x2f,0x49,0x59,0x60,0x19,0x68,0x21,0xf4,0x80,0x21,0x19,0x60, -0xda,0x60,0x00,0x92,0x01,0x92,0x1a,0x68,0x42,0xf4,0x80,0x32,0x1a,0x60,0x1a,0x68, -0x02,0xf4,0x00,0x32,0x01,0x92,0x00,0x9a,0x01,0x32,0x00,0x92,0x01,0x9a,0x1a,0xb9, -0x00,0x9a,0xb2,0xf5,0xa0,0x6f,0xf2,0xd1,0x21,0x4b,0x1b,0x68,0x13,0xf4,0x00,0x33, -0x18,0xbf,0x01,0x23,0x01,0x93,0x01,0x9b,0x01,0x2b,0x25,0xd1,0x1c,0x4b,0x9a,0x68, -0x9a,0x60,0x9a,0x68,0x42,0xf4,0x00,0x42,0x9a,0x60,0x9a,0x68,0x42,0xf4,0xa0,0x52, -0x9a,0x60,0x19,0x4a,0x5a,0x60,0x1a,0x68,0x42,0xf0,0x80,0x72,0x1a,0x60,0x19,0x68, -0x13,0x4a,0x89,0x01,0xfb,0xd5,0x15,0x4b,0x40,0xf2,0x03,0x71,0x19,0x60,0x93,0x68, -0x23,0xf0,0x03,0x03,0x93,0x60,0x93,0x68,0x43,0xf0,0x02,0x03,0x93,0x60,0x93,0x68, -0x03,0xf0,0x0c,0x03,0x08,0x2b,0xfa,0xd1,0x0d,0x4a,0x0e,0x4b,0x1a,0x60,0x0e,0x4a, -0x0e,0x4b,0x1a,0x60,0x0e,0x4a,0x0f,0x4b,0x1a,0x60,0x0f,0x4a,0x02,0x23,0x13,0x60, -0x0e,0x4a,0x13,0x60,0x0e,0x4b,0x0f,0x4a,0x9a,0x60,0x02,0xb0,0x70,0x47,0x00,0xbf, -0x00,0x38,0x02,0x40,0x10,0x30,0x00,0x24,0x0c,0x3c,0x41,0x05,0x00,0x3c,0x02,0x40, -0x00,0x87,0x93,0x03,0x6c,0x9f,0x00,0x20,0xc0,0xe1,0xe4,0x00,0x70,0x9f,0x00,0x20, -0x80,0xc3,0xc9,0x01,0x7c,0x9f,0x00,0x20,0x74,0x9f,0x00,0x20,0x78,0x9f,0x00,0x20, -0x00,0xed,0x00,0xe0,0x00,0x00,0x00,0x20,0x18,0x4b,0x19,0x4a,0x99,0x68,0x01,0xf0, -0x0c,0x01,0x04,0x29,0x08,0xbf,0x17,0x4b,0x1b,0xd0,0x08,0x29,0x18,0xbf,0x16,0x4b, -0x17,0xd1,0x59,0x68,0x5a,0x68,0x11,0xf4,0x80,0x0f,0x59,0x68,0x14,0xbf,0x11,0x4b, -0x11,0x4b,0x02,0xf0,0x3f,0x02,0xb3,0xfb,0xf2,0xf3,0x0c,0x4a,0xc1,0xf3,0x88,0x11, -0x52,0x68,0x4b,0x43,0xc2,0xf3,0x01,0x42,0x01,0x32,0x52,0x00,0xb3,0xfb,0xf2,0xf3, -0x07,0x4a,0x13,0x60,0x05,0x4b,0x9a,0x68,0x05,0x4b,0xc2,0xf3,0x03,0x12,0x9a,0x18, -0x12,0x79,0x19,0x68,0x31,0xfa,0x02,0xf2,0x1a,0x60,0x70,0x47,0x00,0x38,0x02,0x40, -0x48,0x77,0x00,0x20,0x00,0x1b,0xb7,0x00,0x00,0x24,0xf4,0x00,0x0a,0x4b,0x1a,0x68, -0x42,0xf0,0x01,0x02,0x1a,0x60,0x00,0x22,0x9a,0x60,0x19,0x68,0x21,0xf0,0x84,0x71, -0x21,0xf4,0x80,0x31,0x19,0x60,0x05,0x49,0x59,0x60,0x19,0x68,0x21,0xf4,0x80,0x21, -0x19,0x60,0xda,0x60,0x70,0x47,0x00,0xbf,0x00,0x38,0x02,0x40,0x10,0x30,0x00,0x24, -0x02,0x4b,0x00,0x22,0x1a,0x70,0x18,0x70,0x70,0x47,0x00,0xbf,0x02,0x38,0x02,0x40, -0x03,0x4b,0x1a,0x68,0x22,0xf0,0xf8,0x02,0x42,0xea,0xc0,0x00,0x18,0x60,0x70,0x47, -0x00,0x38,0x02,0x40,0x01,0x4b,0x18,0x60,0x70,0x47,0x00,0xbf,0x00,0x00,0x47,0x42, -0x06,0x4b,0x00,0x22,0x01,0x28,0x1a,0x70,0x1a,0x70,0x02,0xd0,0x04,0x28,0x04,0xd1, -0x01,0xe0,0x18,0x70,0x70,0x47,0x05,0x22,0x1a,0x70,0x70,0x47,0x70,0x38,0x02,0x40, -0x01,0x4b,0x18,0x60,0x70,0x47,0x00,0xbf,0x80,0x0e,0x47,0x42,0x01,0x43,0x41,0xea, -0x82,0x12,0x00,0x99,0x42,0xea,0x01,0x61,0x5a,0x08,0x01,0x3a,0x02,0x4b,0x41,0xea, -0x02,0x42,0x5a,0x60,0x70,0x47,0x00,0xbf,0x00,0x38,0x02,0x40,0x01,0x4b,0x18,0x60, -0x70,0x47,0x00,0xbf,0x60,0x00,0x47,0x42,0x80,0x01,0x03,0x4b,0x40,0xea,0x01,0x70, -0xc3,0xf8,0x84,0x00,0x70,0x47,0x00,0xbf,0x00,0x38,0x02,0x40,0x01,0x4b,0x18,0x60, -0x70,0x47,0x00,0xbf,0x68,0x00,0x47,0x42,0x01,0x4b,0x18,0x60,0x70,0x47,0x00,0xbf, -0x4c,0x00,0x47,0x42,0x03,0x4b,0x9a,0x68,0x22,0xf0,0xec,0x62,0x10,0x43,0x08,0x43, -0x98,0x60,0x70,0x47,0x00,0x38,0x02,0x40,0x03,0x4b,0x9a,0x68,0x22,0xf0,0x78,0x42, -0x10,0x43,0x08,0x43,0x98,0x60,0x70,0x47,0x00,0x38,0x02,0x40,0x03,0x4b,0x9a,0x68, -0x22,0xf0,0x03,0x02,0x10,0x43,0x98,0x60,0x70,0x47,0x00,0xbf,0x00,0x38,0x02,0x40, -0x02,0x4b,0x98,0x68,0x00,0xf0,0x0c,0x00,0x70,0x47,0x00,0xbf,0x00,0x38,0x02,0x40, -0x03,0x4b,0x9a,0x68,0x22,0xf0,0xf0,0x02,0x10,0x43,0x98,0x60,0x70,0x47,0x00,0xbf, -0x00,0x38,0x02,0x40,0x03,0x4b,0x9a,0x68,0x22,0xf4,0xe0,0x52,0x10,0x43,0x98,0x60, -0x70,0x47,0x00,0xbf,0x00,0x38,0x02,0x40,0x03,0x4b,0x9a,0x68,0x22,0xf4,0x60,0x42, -0x42,0xea,0xc0,0x00,0x98,0x60,0x70,0x47,0x00,0x38,0x02,0x40,0x10,0xb5,0x1e,0x4b, -0x9a,0x68,0x02,0xf0,0x0c,0x02,0x04,0x2a,0x08,0xbf,0x1c,0x4b,0x1a,0xd0,0x08,0x2a, -0x18,0xbf,0x1b,0x4b,0x16,0xd1,0x59,0x68,0x5a,0x68,0x11,0xf4,0x80,0x0f,0x59,0x68, -0x14,0xbf,0x16,0x4b,0x16,0x4b,0x02,0xf0,0x3f,0x02,0xb3,0xfb,0xf2,0xf3,0x12,0x4a, -0xc1,0xf3,0x88,0x11,0x52,0x68,0x4b,0x43,0xc2,0xf3,0x01,0x42,0x01,0x32,0x52,0x00, -0xb3,0xfb,0xf2,0xf3,0x0c,0x49,0x03,0x60,0x8b,0x68,0x0e,0x4a,0xc3,0xf3,0x03,0x13, -0xd3,0x5c,0x04,0x68,0x34,0xfa,0x03,0xf3,0x43,0x60,0x8c,0x68,0xc4,0xf3,0x82,0x24, -0x14,0x5d,0x33,0xfa,0x04,0xf4,0x84,0x60,0x89,0x68,0xc1,0xf3,0x42,0x31,0x52,0x5c, -0xd3,0x40,0xc3,0x60,0x10,0xbd,0x00,0xbf,0x00,0x38,0x02,0x40,0x00,0x1b,0xb7,0x00, -0x00,0x24,0xf4,0x00,0x5c,0x77,0x00,0x20,0x00,0xf4,0x40,0x73,0xb3,0xf5,0x40,0x7f, -0x08,0x4b,0x08,0xd1,0x99,0x68,0x20,0xf0,0x70,0x42,0x21,0xf4,0xf8,0x11,0x22,0xf4, -0x40,0x72,0x0a,0x43,0x9a,0x60,0x1a,0x6f,0x00,0x05,0x42,0xea,0x10,0x50,0x18,0x67, -0x70,0x47,0x00,0xbf,0x00,0x38,0x02,0x40,0x01,0x4b,0x18,0x60,0x70,0x47,0x00,0xbf, -0x3c,0x0e,0x47,0x42,0x01,0x4b,0x18,0x60,0x70,0x47,0x00,0xbf,0x40,0x0e,0x47,0x42, -0x01,0x4b,0x18,0x60,0x70,0x47,0x00,0xbf,0x5c,0x01,0x47,0x42,0x04,0x4b,0x1a,0x6b, -0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea,0x00,0x00,0x18,0x63,0x70,0x47,0x00,0xbf, -0x00,0x38,0x02,0x40,0x04,0x4b,0x5a,0x6b,0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea, -0x00,0x00,0x58,0x63,0x70,0x47,0x00,0xbf,0x00,0x38,0x02,0x40,0x04,0x4b,0x9a,0x6b, -0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea,0x00,0x00,0x98,0x63,0x70,0x47,0x00,0xbf, -0x00,0x38,0x02,0x40,0x04,0x4b,0x1a,0x6c,0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea, -0x00,0x00,0x18,0x64,0x70,0x47,0x00,0xbf,0x00,0x38,0x02,0x40,0x04,0x4b,0x5a,0x6c, -0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea,0x00,0x00,0x58,0x64,0x70,0x47,0x00,0xbf, -0x00,0x38,0x02,0x40,0x04,0x4b,0x1a,0x69,0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea, -0x00,0x00,0x18,0x61,0x70,0x47,0x00,0xbf,0x00,0x38,0x02,0x40,0x04,0x4b,0x5a,0x69, -0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea,0x00,0x00,0x58,0x61,0x70,0x47,0x00,0xbf, -0x00,0x38,0x02,0x40,0x04,0x4b,0x9a,0x69,0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea, -0x00,0x00,0x98,0x61,0x70,0x47,0x00,0xbf,0x00,0x38,0x02,0x40,0x04,0x4b,0x1a,0x6a, -0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea,0x00,0x00,0x18,0x62,0x70,0x47,0x00,0xbf, -0x00,0x38,0x02,0x40,0x04,0x4b,0x5a,0x6a,0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea, -0x00,0x00,0x58,0x62,0x70,0x47,0x00,0xbf,0x00,0x38,0x02,0x40,0x04,0x4b,0x1a,0x6d, -0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea,0x00,0x00,0x18,0x65,0x70,0x47,0x00,0xbf, -0x00,0x38,0x02,0x40,0x04,0x4b,0x5a,0x6d,0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea, -0x00,0x00,0x58,0x65,0x70,0x47,0x00,0xbf,0x00,0x38,0x02,0x40,0x04,0x4b,0x9a,0x6d, -0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea,0x00,0x00,0x98,0x65,0x70,0x47,0x00,0xbf, -0x00,0x38,0x02,0x40,0x04,0x4b,0x1a,0x6e,0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea, -0x00,0x00,0x18,0x66,0x70,0x47,0x00,0xbf,0x00,0x38,0x02,0x40,0x04,0x4b,0x5a,0x6e, -0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea,0x00,0x00,0x58,0x66,0x70,0x47,0x00,0xbf, -0x00,0x38,0x02,0x40,0x04,0x4b,0x1a,0x78,0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea, -0x00,0x00,0x18,0x70,0x70,0x47,0x00,0xbf,0x0d,0x38,0x02,0x40,0x43,0x09,0x08,0x4a, -0x01,0x2b,0x08,0xbf,0x13,0x68,0x03,0xd0,0x02,0x2b,0x0c,0xbf,0x13,0x6f,0x53,0x6f, -0x00,0xf0,0x1f,0x00,0x33,0xfa,0x00,0xf0,0x00,0xf0,0x01,0x00,0x70,0x47,0x00,0xbf, -0x00,0x38,0x02,0x40,0x07,0xb5,0x00,0x23,0x01,0x93,0x31,0x20,0xff,0xf7,0xe6,0xff, -0x01,0x9b,0x01,0x33,0x01,0x93,0x01,0x9b,0xb3,0xf5,0xa0,0x6f,0x01,0xd0,0x00,0x28, -0xf3,0xd0,0x31,0x20,0xff,0xf7,0xda,0xff,0x00,0x30,0x18,0xbf,0x01,0x20,0x0e,0xbd, -0x02,0x4b,0x5a,0x6f,0x42,0xf0,0x80,0x72,0x5a,0x67,0x70,0x47,0x00,0x38,0x02,0x40, -0x03,0x4b,0xdb,0x68,0x18,0x42,0x0c,0xbf,0x00,0x20,0x01,0x20,0x70,0x47,0x00,0xbf, -0x00,0x38,0x02,0x40,0x01,0x4b,0x18,0x70,0x70,0x47,0x00,0xbf,0x0e,0x38,0x02,0x40, -0x08,0xb5,0x2c,0x4b,0x98,0x42,0x05,0xd1,0x01,0x20,0x01,0x46,0xff,0xf7,0x32,0xff, -0x01,0x20,0x48,0xe0,0x28,0x4b,0x98,0x42,0x05,0xd1,0x02,0x20,0x01,0x21,0xff,0xf7, -0x29,0xff,0x02,0x20,0x3f,0xe0,0x25,0x4b,0x98,0x42,0x05,0xd1,0x04,0x20,0x01,0x21, -0xff,0xf7,0x20,0xff,0x04,0x20,0x36,0xe0,0x21,0x4b,0x98,0x42,0x05,0xd1,0x08,0x20, -0x01,0x21,0xff,0xf7,0x17,0xff,0x08,0x20,0x2d,0xe0,0x1e,0x4b,0x98,0x42,0x05,0xd1, -0x10,0x20,0x01,0x21,0xff,0xf7,0x0e,0xff,0x10,0x20,0x24,0xe0,0x1a,0x4b,0x98,0x42, -0x05,0xd1,0x20,0x20,0x01,0x21,0xff,0xf7,0x05,0xff,0x20,0x20,0x1b,0xe0,0x17,0x4b, -0x98,0x42,0x05,0xd1,0x40,0x20,0x01,0x21,0xff,0xf7,0xfc,0xfe,0x40,0x20,0x12,0xe0, -0x13,0x4b,0x98,0x42,0x05,0xd1,0x80,0x20,0x01,0x21,0xff,0xf7,0xf3,0xfe,0x80,0x20, -0x09,0xe0,0x10,0x4b,0x98,0x42,0x0b,0xd1,0x4f,0xf4,0x80,0x70,0x01,0x21,0xff,0xf7, -0xe9,0xfe,0x4f,0xf4,0x80,0x70,0x00,0x21,0xbd,0xe8,0x08,0x40,0xff,0xf7,0xe2,0xbe, -0x08,0xbd,0x00,0xbf,0x00,0x00,0x02,0x40,0x00,0x04,0x02,0x40,0x00,0x08,0x02,0x40, -0x00,0x0c,0x02,0x40,0x00,0x10,0x02,0x40,0x00,0x14,0x02,0x40,0x00,0x18,0x02,0x40, -0x00,0x1c,0x02,0x40,0x00,0x20,0x02,0x40,0x2d,0xe9,0xf0,0x47,0x00,0x23,0xd1,0xf8, -0x00,0x80,0x1a,0x46,0x4f,0xf0,0x01,0x0c,0x03,0x27,0x0c,0xfa,0x02,0xf4,0x04,0xea, -0x08,0x05,0xa5,0x42,0x2f,0xd1,0x17,0xfa,0x03,0xf4,0x06,0x68,0xe4,0x43,0x26,0x40, -0x06,0x60,0x0e,0x79,0xd0,0xf8,0x00,0x90,0x06,0xfa,0x03,0xfa,0x01,0x3e,0xf6,0xb2, -0x4a,0xea,0x09,0x09,0x01,0x2e,0xc0,0xf8,0x00,0x90,0x14,0xd8,0x91,0xf8,0x05,0x90, -0x86,0x68,0x09,0xfa,0x03,0xf9,0x26,0x40,0x86,0x60,0x86,0x68,0x49,0xea,0x06,0x06, -0x86,0x60,0x46,0x68,0x26,0xea,0x05,0x05,0x45,0x60,0x8d,0x79,0x46,0x68,0x95,0x40, -0xad,0xb2,0x35,0x43,0x45,0x60,0xc5,0x68,0x2c,0x40,0xc4,0x60,0xcc,0x79,0xc5,0x68, -0x9c,0x40,0x2c,0x43,0xc4,0x60,0x01,0x32,0x02,0x33,0x10,0x2a,0xc5,0xd1,0xbd,0xe8, -0xf0,0x87,0x4f,0xf6,0xff,0x73,0x03,0x60,0x00,0x23,0x03,0x71,0x43,0x71,0x83,0x71, -0xc3,0x71,0x70,0x47,0x82,0xb0,0x4f,0xf4,0x80,0x33,0x01,0x93,0x01,0x9b,0x0b,0x43, -0x01,0x93,0x01,0x9b,0xc3,0x61,0xc1,0x61,0x01,0x9b,0xc3,0x61,0xc3,0x69,0x01,0x93, -0xc3,0x69,0x01,0x93,0x02,0xb0,0x70,0x47,0x03,0x69,0x19,0x42,0x0c,0xbf,0x00,0x20, -0x01,0x20,0x70,0x47,0x00,0x69,0x80,0xb2,0x70,0x47,0x43,0x69,0x19,0x42,0x0c,0xbf, -0x00,0x20,0x01,0x20,0x70,0x47,0x40,0x69,0x80,0xb2,0x70,0x47,0x01,0x83,0x70,0x47, -0x41,0x83,0x70,0x47,0x0a,0xb1,0x01,0x83,0x70,0x47,0x41,0x83,0x70,0x47,0x41,0x61, -0x70,0x47,0x43,0x69,0x59,0x40,0x41,0x61,0x70,0x47,0x01,0xf0,0x07,0x03,0x30,0xb5, -0x9b,0x00,0x0f,0x24,0x9c,0x40,0x12,0xfa,0x03,0xf3,0xc9,0x08,0x08,0x31,0x50,0xf8, -0x21,0x50,0x25,0xea,0x04,0x04,0x40,0xf8,0x21,0x40,0x50,0xf8,0x21,0x40,0x23,0x43, -0x40,0xf8,0x21,0x30,0x30,0xbd,0x00,0xbf,0x08,0xb5,0x15,0x4b,0x98,0x42,0x0b,0xd1, -0x01,0x21,0x4f,0xf4,0x80,0x50,0xff,0xf7,0x5d,0xfe,0x4f,0xf4,0x80,0x50,0x00,0x21, -0xbd,0xe8,0x08,0x40,0xff,0xf7,0x56,0xbe,0x0e,0x4b,0x98,0x42,0x07,0xd1,0x4f,0xf4, -0x80,0x40,0x01,0x21,0xff,0xf7,0x42,0xfe,0x4f,0xf4,0x80,0x40,0x09,0xe0,0x0a,0x4b, -0x98,0x42,0x0b,0xd1,0x4f,0xf4,0x00,0x40,0x01,0x21,0xff,0xf7,0x37,0xfe,0x4f,0xf4, -0x00,0x40,0x00,0x21,0xbd,0xe8,0x08,0x40,0xff,0xf7,0x30,0xbe,0x08,0xbd,0x00,0xbf, -0x00,0x30,0x01,0x40,0x00,0x38,0x00,0x40,0x00,0x3c,0x00,0x40,0x0b,0x88,0x10,0xb5, -0x4c,0x88,0x02,0x88,0x23,0x43,0x8c,0x88,0x02,0xf4,0x41,0x52,0x23,0x43,0xcc,0x88, -0x23,0x43,0x0c,0x89,0x23,0x43,0x4c,0x89,0x23,0x43,0x8c,0x89,0x23,0x43,0xcc,0x89, -0x23,0x43,0x13,0x43,0x9b,0xb2,0x03,0x80,0x83,0x8b,0x23,0xf4,0x00,0x63,0x1b,0x04, -0x1b,0x0c,0x83,0x83,0x0b,0x8a,0x03,0x82,0x10,0xbd,0x83,0x8b,0xf0,0xb5,0x23,0xf4, -0x7a,0x63,0x23,0xf0,0x1f,0x03,0x1b,0x04,0x1b,0x0c,0x83,0x83,0x02,0x23,0x03,0x84, -0x8b,0x68,0x85,0x8b,0x00,0x22,0x02,0x2b,0xad,0xb2,0x38,0xd0,0x28,0x4a,0x8e,0x88, -0x94,0x68,0x00,0x2e,0x14,0xbf,0x02,0x26,0x01,0x26,0x24,0x02,0x48,0xbf,0x94,0x68, -0xdf,0xf8,0x90,0xc0,0x44,0xbf,0x24,0xf4,0x00,0x04,0x94,0x60,0xd2,0xf8,0x84,0x40, -0xd2,0xf8,0x84,0x70,0x52,0x68,0xc4,0xf3,0x88,0x14,0x02,0xf0,0x3f,0x02,0xbc,0xfb, -0xf2,0xf2,0x54,0x43,0xc7,0xf3,0x02,0x72,0xb4,0xfb,0xf2,0xf4,0xca,0x88,0xb2,0xf5, -0x00,0x7f,0x4f,0xf0,0x0a,0x02,0x01,0xd1,0x24,0x0a,0x02,0xe0,0x76,0x01,0xb4,0xfb, -0xf6,0xf4,0x62,0x43,0xb2,0xfb,0xf3,0xf3,0x05,0x33,0x0a,0x22,0x9b,0xb2,0xb3,0xfb, -0xf2,0xf3,0x03,0xf0,0x01,0x02,0x12,0x02,0xc3,0xf3,0x4f,0x03,0x92,0xb2,0x9c,0x1e, -0xa4,0xb2,0xfe,0x2c,0x28,0xbf,0x00,0x22,0xcc,0x88,0x28,0xbf,0x02,0x23,0x13,0x43, -0x23,0x43,0x9b,0xb2,0x03,0x84,0x0b,0x88,0x4a,0x88,0x2b,0x43,0x43,0xf4,0x00,0x63, -0x13,0x43,0x8a,0x88,0x13,0x43,0x8a,0x89,0x13,0x43,0x9b,0xb2,0x83,0x83,0xf0,0xbd, -0x00,0x38,0x02,0x40,0x00,0x1b,0xb7,0x00,0x00,0x23,0x03,0x80,0x43,0x80,0x83,0x80, -0xc3,0x80,0x03,0x81,0x43,0x81,0x83,0x81,0xc3,0x81,0x07,0x23,0x03,0x82,0x70,0x47, -0x00,0x23,0x02,0x22,0x03,0x80,0x43,0x80,0x83,0x80,0xc3,0x80,0x82,0x60,0x83,0x81, -0x70,0x47,0x03,0x88,0x19,0xb1,0x9b,0xb2,0x43,0xf0,0x40,0x03,0x03,0xe0,0x23,0xf0, -0x40,0x03,0x1b,0x04,0x1b,0x0c,0x03,0x80,0x70,0x47,0x83,0x8b,0x19,0xb1,0x9b,0xb2, -0x43,0xf4,0x80,0x63,0x03,0xe0,0x23,0xf4,0x80,0x63,0x1b,0x04,0x1b,0x0c,0x83,0x83, -0x70,0x47,0x03,0x88,0x23,0xf4,0x00,0x63,0x1b,0x04,0x1b,0x0c,0x03,0x80,0x03,0x88, -0x9b,0xb2,0x19,0x43,0x01,0x80,0x70,0x47,0x03,0x88,0xb1,0xf5,0x80,0x4f,0x04,0xbf, -0x9b,0xb2,0x43,0xf4,0x80,0x43,0x03,0xd0,0x23,0xf4,0x80,0x43,0x1b,0x04,0x1b,0x0c, -0x03,0x80,0x70,0x47,0x4f,0xf6,0xff,0x63,0x99,0x42,0x03,0x88,0x1c,0xbf,0x9b,0xb2, -0x43,0xf4,0x80,0x73,0x03,0xd1,0x23,0xf4,0x80,0x73,0x1b,0x04,0x1b,0x0c,0x03,0x80, -0x70,0x47,0x83,0x88,0x19,0xb1,0x9b,0xb2,0x43,0xf0,0x04,0x03,0x03,0xe0,0x23,0xf0, -0x04,0x03,0x1b,0x04,0x1b,0x0c,0x83,0x80,0x70,0x47,0x83,0x88,0x19,0xb1,0x9b,0xb2, -0x43,0xf0,0x10,0x03,0x03,0xe0,0x23,0xf0,0x10,0x03,0x1b,0x04,0x1b,0x0c,0x83,0x80, -0x70,0x47,0x80,0x89,0x80,0xb2,0x70,0x47,0x81,0x81,0x70,0x47,0x03,0x88,0x19,0xb1, -0x9b,0xb2,0x43,0xf4,0x00,0x53,0x03,0xe0,0x23,0xf4,0x00,0x53,0x1b,0x04,0x1b,0x0c, -0x03,0x80,0x70,0x47,0x03,0x88,0x9b,0xb2,0x43,0xf4,0x80,0x53,0x03,0x80,0x70,0x47, -0x01,0x29,0x15,0xbf,0x00,0x8b,0x80,0x8a,0x80,0xb2,0x80,0xb2,0x70,0x47,0x00,0x8a, -0x80,0xb2,0x70,0x47,0x83,0x88,0x9b,0xb2,0x0a,0xb1,0x19,0x43,0x01,0xe0,0x23,0xea, -0x01,0x01,0x81,0x80,0x70,0x47,0x01,0x23,0x09,0x09,0x13,0xfa,0x01,0xf1,0x83,0x88, -0x89,0xb2,0x9b,0xb2,0x0a,0xb1,0x19,0x43,0x01,0xe0,0x23,0xea,0x01,0x01,0x81,0x80, -0x70,0x47,0x03,0x89,0x19,0x42,0x0c,0xbf,0x00,0x20,0x01,0x20,0x70,0x47,0xc9,0x43, -0x89,0xb2,0x01,0x81,0x70,0x47,0x01,0x23,0x01,0xf0,0x0f,0x02,0x13,0xfa,0x02,0xf2, -0x10,0xb5,0x84,0x88,0x00,0x89,0xa4,0xb2,0x80,0xb2,0x10,0x40,0x05,0xd0,0x09,0x09, -0x8b,0x40,0x1c,0x42,0x0c,0xbf,0x00,0x20,0x01,0x20,0x10,0xbd,0x01,0xf0,0x0f,0x01, -0x01,0x23,0x8b,0x40,0xdb,0x43,0x9b,0xb2,0x03,0x81,0x70,0x47,0x40,0xf0,0xbe,0x60, -0x02,0x4b,0x40,0xf4,0x20,0x20,0xd8,0x60,0x70,0x47,0x00,0xbf,0x00,0xed,0x00,0xe0, -0xc3,0x78,0x10,0xb5,0xfb,0xb1,0x16,0x4b,0x42,0x78,0xdb,0x68,0x84,0x78,0xdb,0x43, -0xc3,0xf3,0x02,0x23,0xc3,0xf1,0x04,0x01,0xc9,0xb2,0x12,0xfa,0x01,0xf1,0x0f,0x22, -0x1a,0x41,0xc9,0xb2,0x22,0x40,0x0a,0x43,0x0e,0x4b,0x01,0x78,0x12,0x01,0xcb,0x18, -0xd2,0xb2,0x83,0xf8,0x00,0x23,0x03,0x78,0x01,0x22,0x59,0x09,0x03,0xf0,0x1f,0x03, -0x12,0xfa,0x03,0xf3,0x07,0xe0,0x03,0x78,0x01,0x22,0x59,0x09,0x03,0xf0,0x1f,0x03, -0x12,0xfa,0x03,0xf3,0x20,0x31,0x03,0x4a,0x42,0xf8,0x21,0x30,0x10,0xbd,0x00,0xbf, -0x00,0xed,0x00,0xe0,0x00,0xe1,0x00,0xe0,0x21,0xf0,0x60,0x41,0x21,0xf0,0x7f,0x01, -0x01,0x4b,0x08,0x43,0x98,0x60,0x70,0x47,0x00,0xed,0x00,0xe0,0x04,0x4b,0x1a,0x69, -0x09,0xb1,0x10,0x43,0x01,0xe0,0x22,0xea,0x00,0x00,0x18,0x61,0x70,0x47,0x00,0xbf, -0x00,0xed,0x00,0xe0,0x04,0x4b,0x04,0x28,0x1a,0x68,0x0c,0xbf,0x42,0xf0,0x04,0x02, -0x22,0xf0,0x04,0x02,0x1a,0x60,0x70,0x47,0x10,0xe0,0x00,0xe0,0x37,0xb5,0x00,0x23, -0x10,0x4c,0x05,0x46,0x01,0x93,0x03,0x20,0x02,0xf0,0xc2,0xf8,0x2b,0x68,0x01,0x3c, -0x1a,0x69,0x01,0x92,0x13,0xd0,0x01,0x9a,0x00,0x2a,0xf4,0xda,0x01,0x9a,0x42,0xf0, -0x01,0x02,0x01,0x92,0x01,0x9a,0x1a,0x61,0x06,0x4a,0x19,0x69,0x01,0x3a,0x01,0x91, -0x02,0xd0,0x01,0x99,0xc9,0x07,0xf8,0xd4,0x03,0x20,0x02,0xf0,0xa9,0xf8,0x00,0x20, -0x3e,0xbd,0x00,0xbf,0x41,0x0d,0x03,0x00,0x10,0xb5,0xc4,0x78,0x74,0xb9,0x00,0xeb, -0x82,0x00,0x03,0x33,0x9b,0x10,0xd0,0xf8,0xd0,0x00,0x22,0x46,0x03,0xe0,0x51,0xf8, -0x04,0x4c,0x01,0x32,0x04,0x60,0x04,0x31,0x9a,0x42,0xf8,0xd1,0x00,0x20,0x10,0xbd, -0x03,0x32,0x30,0xb5,0x92,0x10,0xd0,0xf8,0xd0,0x40,0x0b,0x46,0x00,0x20,0x03,0xe0, -0x25,0x68,0x01,0x30,0x43,0xf8,0x04,0x5c,0x04,0x33,0x90,0x42,0xf8,0xd1,0x01,0xeb, -0x80,0x00,0x30,0xbd,0x01,0x22,0xf0,0xb5,0x00,0x23,0x82,0x70,0x40,0x22,0x01,0x29, -0xc3,0x70,0x82,0x80,0x0c,0xd1,0x08,0x23,0x03,0x70,0x04,0x23,0x43,0x70,0x4f,0xf4, -0xa0,0x73,0xc3,0x80,0x02,0x23,0x03,0x72,0xc1,0x72,0x4f,0xf0,0xa0,0x43,0x09,0xe0, -0x41,0xb9,0x0c,0x23,0x03,0x70,0x06,0x23,0x43,0x70,0x4f,0xf4,0xa0,0x62,0x20,0x4b, -0xc1,0x72,0xc2,0x80,0x03,0xf5,0x00,0x62,0x02,0x61,0xc3,0x60,0x46,0x78,0x04,0x46, -0x01,0x46,0x1a,0x46,0x00,0x25,0x08,0xe0,0x02,0xf5,0x10,0x6c,0x02,0xf5,0x30,0x62, -0x0a,0x65,0xc1,0xf8,0x14,0xc0,0x01,0x35,0x3a,0x46,0x04,0x31,0xb5,0x42,0x02,0xf1, -0x20,0x07,0xf1,0xd3,0x03,0xf5,0x80,0x62,0x42,0x61,0x03,0xf5,0x88,0x62,0xc0,0xf8, -0xcc,0x20,0x06,0x78,0x03,0xf5,0xa0,0x65,0x01,0x46,0x00,0x22,0x03,0xe0,0xc1,0xf8, -0x8c,0x50,0x01,0x32,0x20,0x35,0x04,0x31,0xb2,0x42,0xf8,0xd3,0x19,0x46,0x00,0x22, -0x02,0xe0,0xc4,0xf8,0xcc,0x10,0x01,0x32,0x04,0x34,0xb2,0x42,0x01,0xf5,0x80,0x51, -0xf7,0xd3,0x03,0xf5,0x60,0x63,0xc0,0xf8,0x0c,0x31,0x00,0x20,0xf0,0xbd,0x00,0xbf, -0x00,0x00,0x04,0x40,0x38,0xb5,0x03,0x7a,0x00,0x25,0x01,0x2b,0x04,0x46,0xc2,0x68, -0x20,0xd1,0x93,0x6b,0x41,0x7a,0x65,0xf3,0x10,0x43,0x09,0xb1,0x43,0xf4,0x80,0x13, -0x93,0x63,0xd3,0x68,0x04,0xf1,0x0c,0x00,0x6f,0xf3,0x86,0x13,0x6f,0xf3,0x96,0x53, -0x6f,0xf3,0x51,0x43,0x6f,0xf3,0xd3,0x43,0xd3,0x60,0xff,0xf7,0x37,0xff,0xe3,0x78, -0x01,0x2b,0x1b,0xd1,0x05,0x23,0x63,0xf3,0x44,0x05,0xe3,0x68,0x45,0xf0,0x20,0x05, -0x9d,0x60,0x13,0xe0,0xd3,0x68,0x00,0xf1,0x0c,0x00,0x43,0xf0,0x40,0x03,0xd3,0x60, -0xff,0xf7,0x24,0xff,0x63,0x7a,0xe2,0x68,0x00,0x2b,0x0c,0xbf,0x4f,0xf4,0x50,0x23, -0x4f,0xf4,0xe8,0x13,0x93,0x63,0x14,0x20,0x01,0xf0,0xf2,0xff,0xe3,0x78,0x01,0x2b, -0x07,0xd1,0xe3,0x68,0x05,0x22,0x9d,0x68,0x62,0xf3,0x44,0x05,0x45,0xf0,0x20,0x05, -0x9d,0x60,0x00,0x20,0x38,0xbd,0xc3,0x68,0x00,0x20,0x9a,0x68,0x42,0xf0,0x01,0x02, -0x9a,0x60,0x70,0x47,0xc3,0x68,0x00,0x20,0x9a,0x68,0x22,0xf0,0x01,0x02,0x9a,0x60, -0x70,0x47,0x07,0xb5,0x00,0x23,0x01,0x93,0x01,0x9b,0x43,0xf0,0x20,0x03,0x01,0x93, -0x01,0x9b,0x61,0xf3,0x8a,0x13,0x01,0x93,0x01,0x9b,0xc2,0x68,0x13,0x61,0x06,0x4b, -0x11,0x69,0x01,0x3b,0x01,0x91,0x02,0xd0,0x01,0x99,0x88,0x06,0xf8,0xd4,0x03,0x20, -0x01,0xf0,0xae,0xff,0x00,0x20,0x0e,0xbd,0x41,0x0d,0x03,0x00,0x07,0xb5,0x00,0x23, -0x01,0x93,0x01,0x9b,0x43,0xf0,0x10,0x03,0x01,0x93,0x01,0x9b,0xc2,0x68,0x13,0x61, -0x06,0x4b,0x11,0x69,0x01,0x3b,0x01,0x91,0x02,0xd0,0x01,0x99,0xc9,0x06,0xf8,0xd4, -0x03,0x20,0x01,0xf0,0x95,0xff,0x00,0x20,0x0e,0xbd,0x00,0xbf,0x41,0x0d,0x03,0x00, -0x08,0xb5,0xc2,0x68,0x01,0x29,0xd3,0x68,0x6f,0xf3,0x5d,0x73,0x6f,0xf3,0x9e,0x73, -0x08,0xbf,0x43,0xf0,0x00,0x53,0x02,0xd0,0x09,0xb9,0x43,0xf0,0x80,0x43,0x32,0x20, -0xd3,0x60,0x01,0xf0,0x8d,0xff,0x00,0x20,0x08,0xbd,0xc3,0x68,0x58,0x69,0x00,0xf0, -0x01,0x00,0x70,0x47,0xc3,0x68,0x5b,0x69,0x13,0xf0,0x01,0x0f,0x14,0xbf,0x00,0x20, -0x01,0x20,0x70,0x47,0xc3,0x68,0x58,0x69,0x00,0xf0,0x01,0x00,0x70,0x47,0xc3,0x68, -0x5a,0x69,0x98,0x69,0x10,0x40,0x70,0x47,0xc3,0x68,0x58,0x68,0x70,0x47,0x03,0x69, -0x1a,0x68,0x61,0xf3,0x01,0x02,0x1a,0x60,0x70,0x47,0xc2,0x68,0x00,0x23,0x93,0x61, -0x4f,0xf0,0xff,0x31,0x6f,0xf0,0x80,0x43,0x53,0x61,0x51,0x60,0x53,0x61,0x0c,0x4b, -0x93,0x61,0xc3,0x78,0x91,0x69,0x00,0x2b,0x14,0xbf,0x4f,0xf4,0x00,0x63,0x4f,0xf4, -0x01,0x63,0x43,0xf0,0x80,0x43,0x43,0xf4,0x70,0x13,0x43,0xf4,0x40,0x53,0x43,0xf0, -0x0c,0x03,0x21,0xea,0x03,0x01,0x0b,0x43,0x93,0x61,0x00,0x20,0x70,0x47,0x00,0xbf, -0x00,0x08,0x00,0x80,0xf8,0xb5,0xd0,0xf8,0x0c,0x31,0x00,0x22,0x1a,0x60,0x03,0x69, -0x15,0x46,0x1a,0x68,0x04,0x46,0x65,0xf3,0xcc,0x22,0x1a,0x60,0xc3,0x7a,0x01,0x2b, -0x1b,0xd1,0x03,0x21,0xff,0xf7,0xc3,0xff,0xe3,0x68,0x80,0x21,0x4f,0xf4,0x80,0x02, -0x61,0xf3,0x0f,0x02,0x59,0x62,0x9a,0x62,0xc0,0x22,0x62,0xf3,0x0f,0x05,0x61,0xf3, -0x1f,0x45,0x4f,0xf4,0xa0,0x72,0xc3,0xf8,0x04,0x51,0x62,0xf3,0x0f,0x05,0x6f,0xf3, -0x1f,0x45,0xc3,0xf8,0x08,0x51,0xc3,0xf8,0x0c,0x51,0x10,0x21,0x20,0x46,0xff,0xf7, -0x40,0xff,0x20,0x46,0xff,0xf7,0x5a,0xff,0x22,0x69,0x00,0x23,0x4f,0xf0,0xff,0x31, -0x13,0x61,0x20,0x46,0x53,0x61,0x1e,0x46,0x91,0x61,0xff,0x25,0xd3,0x61,0x21,0x46, -0x10,0xe0,0x82,0x69,0x01,0x33,0x17,0x68,0x04,0x30,0xc7,0xf3,0x07,0x67,0x07,0xf0, -0x80,0x07,0xff,0xb2,0x00,0x2f,0x14,0xbf,0x4f,0xf0,0x90,0x47,0x00,0x27,0x17,0x60, -0x16,0x61,0x95,0x60,0x62,0x78,0x93,0x42,0xeb,0xd3,0x00,0x23,0x1d,0x46,0xff,0x20, -0x10,0xe0,0x4a,0x6d,0x01,0x33,0x16,0x68,0x04,0x31,0xc6,0xf3,0x07,0x66,0x06,0xf0, -0x80,0x06,0xf6,0xb2,0x00,0x2e,0x14,0xbf,0x4f,0xf0,0x90,0x46,0x00,0x26,0x16,0x60, -0x15,0x61,0x90,0x60,0x62,0x78,0x93,0x42,0xeb,0xd3,0x23,0x69,0x1a,0x69,0x42,0xf4, -0x80,0x72,0x1a,0x61,0xe2,0x78,0x01,0x2a,0x04,0xd1,0x05,0x4a,0x40,0x21,0x61,0xf3, -0x59,0x42,0x1a,0x63,0x20,0x46,0xff,0xf7,0x60,0xff,0x00,0x20,0xf8,0xbd,0x00,0xbf, -0x03,0x01,0x01,0x00,0x03,0x69,0x9b,0x68,0xc3,0xf3,0x41,0x03,0x5a,0x1e,0x02,0x2a, -0x9d,0xbf,0x03,0x4a,0xd3,0x18,0x13,0xf8,0x01,0x0c,0x03,0x20,0x70,0x47,0x00,0xbf, -0x6c,0x68,0x00,0x20,0x10,0xb5,0x03,0x69,0x81,0x69,0x9c,0x68,0x0a,0x68,0xc4,0xf3, -0x41,0x00,0x02,0x28,0x18,0xbf,0x6f,0xf3,0x0a,0x02,0x02,0xd1,0x03,0x20,0x60,0xf3, -0x0a,0x02,0x0a,0x60,0x5a,0x68,0x00,0x20,0x42,0xf4,0x80,0x72,0x5a,0x60,0x10,0xbd, -0x30,0xb5,0x4d,0x78,0x0b,0x78,0x00,0x22,0x01,0x2d,0x00,0xeb,0x83,0x04,0x05,0xd1, -0x15,0xfa,0x03,0xf3,0xa4,0x69,0x63,0xf3,0x0f,0x02,0x05,0xe0,0x01,0x25,0x15,0xfa, -0x03,0xf3,0x64,0x6d,0x63,0xf3,0x1f,0x42,0x23,0x68,0xc3,0xf3,0x07,0x25,0x05,0xf0, -0x80,0x05,0xed,0xb2,0x6d,0xb9,0x8d,0x68,0x65,0xf3,0x0a,0x03,0xcd,0x78,0xc9,0x88, -0x65,0xf3,0x93,0x43,0x61,0xf3,0x99,0x53,0x43,0xf0,0x80,0x53,0x43,0xf4,0x00,0x43, -0x23,0x60,0x03,0x69,0x00,0x20,0xd9,0x69,0x0a,0x43,0xda,0x61,0x30,0xbd,0x30,0xb5, -0x4d,0x78,0x0b,0x78,0x00,0x24,0x01,0x2d,0x22,0x46,0x00,0xeb,0x83,0x01,0x05,0xd1, -0x15,0xfa,0x03,0xf3,0x89,0x69,0x63,0xf3,0x0f,0x02,0x05,0xe0,0x01,0x25,0x15,0xfa, -0x03,0xf3,0x49,0x6d,0x63,0xf3,0x1f,0x42,0x03,0x69,0x6f,0xf3,0xcf,0x34,0x0c,0x60, -0xd9,0x69,0x00,0x20,0x21,0xea,0x02,0x02,0xda,0x61,0x30,0xbd,0xf8,0xb5,0x4f,0x78, -0x0b,0x78,0x01,0x2f,0x00,0xeb,0x83,0x03,0x49,0xd1,0x9e,0x69,0x4c,0x69,0x35,0x68, -0x33,0x69,0x2a,0x46,0x64,0xf3,0x12,0x03,0x14,0xb9,0x67,0xf3,0xdc,0x43,0x0b,0xe0, -0x8f,0x68,0xe4,0x19,0x01,0x3c,0xb4,0xfb,0xf7,0xf7,0xcc,0x78,0x67,0xf3,0xdc,0x43, -0x01,0x2c,0x08,0xbf,0x64,0xf3,0x5e,0x73,0x33,0x61,0xc3,0x78,0x01,0x2b,0x06,0xd1, -0x0b,0x78,0x0c,0x69,0x00,0xeb,0x83,0x03,0x9b,0x69,0x5c,0x61,0x0c,0xe0,0xcb,0x78, -0x01,0x2b,0x09,0xd0,0x4b,0x69,0x3b,0xb1,0x0c,0x78,0x01,0x27,0x17,0xfa,0x04,0xf4, -0x03,0x69,0x5e,0x6b,0x34,0x43,0x5c,0x63,0xcb,0x78,0x01,0x2b,0x07,0xd1,0x03,0x69, -0x9b,0x68,0xdb,0x05,0x54,0xbf,0x45,0xf0,0x00,0x52,0x45,0xf0,0x80,0x52,0x0b,0x78, -0x42,0xf0,0x04,0x42,0x00,0xeb,0x83,0x03,0x9b,0x69,0x1a,0x60,0xcb,0x78,0x01,0x2b, -0x38,0xd1,0x0a,0x78,0x8b,0x8a,0xc9,0x68,0xff,0xf7,0x4e,0xfd,0x32,0xe0,0x5e,0x6d, -0x4f,0x69,0x35,0x68,0x8c,0x68,0x2a,0x46,0x33,0x69,0x2f,0xb9,0x64,0xf3,0x12,0x03, -0x01,0x24,0x64,0xf3,0xdc,0x43,0x0a,0xe0,0x3f,0x19,0x01,0x3f,0xb7,0xfb,0xf4,0xf7, -0xbf,0x05,0xbf,0x0d,0x7c,0x43,0x67,0xf3,0xdc,0x43,0x64,0xf3,0x12,0x03,0x33,0x61, -0xc3,0x78,0x01,0x2b,0x01,0xbf,0x0b,0x78,0x0c,0x69,0x00,0xeb,0x83,0x03,0x5b,0x6d, -0x08,0xbf,0x5c,0x61,0xcb,0x78,0x01,0x2b,0x05,0xd1,0x4b,0x79,0x45,0xf0,0x00,0x52, -0x0b,0xb9,0x45,0xf0,0x80,0x52,0x0b,0x78,0x42,0xf0,0x04,0x42,0x00,0xeb,0x83,0x00, -0x43,0x6d,0x1a,0x60,0x00,0x20,0xf8,0xbd,0x73,0xb5,0x4d,0x78,0x01,0x2d,0x3e,0xd1, -0x83,0x69,0x4a,0x69,0x1e,0x68,0x1c,0x69,0x00,0x94,0xe4,0xb2,0x42,0xb9,0x62,0xf3, -0x06,0x04,0x8d,0xf8,0x00,0x40,0x9d,0xf8,0x02,0x40,0x65,0xf3,0xc4,0x04,0x0e,0xe0, -0x8d,0x68,0xaa,0x42,0x86,0xbf,0x4d,0x61,0x65,0xf3,0x06,0x04,0x62,0xf3,0x06,0x04, -0x8d,0xf8,0x00,0x40,0x9d,0xf8,0x02,0x40,0x01,0x22,0x62,0xf3,0xc4,0x04,0x8d,0xf8, -0x02,0x40,0x00,0x9a,0x1a,0x61,0xc2,0x78,0x01,0x2a,0x01,0xbf,0x0a,0x78,0x0c,0x69, -0x00,0xeb,0x82,0x02,0x92,0x69,0x08,0xbf,0x54,0x61,0x46,0xf0,0x04,0x42,0x1a,0x60, -0xc3,0x78,0x00,0x2b,0x35,0xd1,0x4b,0x69,0x00,0x2b,0x32,0xd0,0x0a,0x78,0x01,0x21, -0x11,0xfa,0x02,0xf2,0x03,0x69,0x58,0x6b,0x02,0x43,0x5a,0x63,0x29,0xe0,0x0b,0x78, -0x4e,0x69,0x00,0xeb,0x83,0x03,0x5b,0x6d,0x8c,0x68,0x1a,0x68,0x1d,0x69,0x00,0x95, -0xed,0xb2,0x06,0xb1,0x4c,0x61,0x64,0xf3,0x06,0x05,0x9d,0xf8,0x02,0x40,0x8d,0xf8, -0x00,0x50,0x01,0x25,0x65,0xf3,0xc4,0x04,0x8d,0xf8,0x02,0x40,0x00,0x9c,0x42,0xf0, -0x04,0x42,0x1c,0x61,0xc3,0x78,0x01,0x2b,0x01,0xbf,0x0b,0x78,0x0c,0x69,0x00,0xeb, -0x83,0x03,0x5b,0x6d,0x08,0xbf,0x5c,0x61,0x0b,0x78,0x00,0xeb,0x83,0x00,0x43,0x6d, -0x1a,0x60,0x00,0x20,0x7c,0xbd,0x4b,0x78,0x01,0x2b,0x0b,0x78,0x00,0xeb,0x83,0x00, -0x1c,0xbf,0x42,0x6d,0x13,0x68,0x09,0xd1,0x82,0x69,0x13,0x68,0xc3,0xf3,0x07,0x61, -0x01,0xf0,0x80,0x01,0xc9,0xb2,0x09,0xb1,0x43,0xf0,0x80,0x43,0x43,0xf4,0x00,0x13, -0x13,0x60,0x00,0x20,0x70,0x47,0x4b,0x78,0x01,0x2b,0x0b,0x78,0xc9,0x78,0x00,0xeb, -0x83,0x00,0x0c,0xbf,0x82,0x69,0x42,0x6d,0x02,0x39,0x13,0x68,0xc9,0xb2,0x6f,0xf3, -0x55,0x53,0x01,0x29,0x98,0xbf,0x43,0xf0,0x80,0x53,0x13,0x60,0x00,0x20,0x70,0x47, -0x03,0x69,0x9a,0x69,0xd8,0x69,0x10,0x40,0x00,0x0c,0x70,0x47,0x00,0xeb,0x81,0x01, -0x4b,0x6d,0x02,0x69,0x9b,0x68,0x50,0x69,0x18,0x40,0x70,0x47,0x03,0x69,0x98,0x69, -0xdb,0x69,0x18,0x40,0x80,0xb2,0x70,0x47,0x82,0xb0,0x00,0x23,0x00,0x93,0xc0,0x23, -0x8d,0xf8,0x03,0x30,0x01,0x22,0x00,0x23,0x62,0xf3,0xc4,0x03,0x8d,0xf8,0x02,0x30, -0x18,0x23,0x8d,0xf8,0x00,0x30,0x00,0x9a,0x43,0x6d,0x1a,0x61,0xc2,0x78,0x01,0x2a, -0x07,0xd1,0x00,0xf5,0xb8,0x60,0x0c,0x30,0x58,0x61,0x1a,0x68,0x4f,0xf0,0x80,0x22, -0x1a,0x60,0x02,0xb0,0x70,0x47,0xd0,0xf8,0x18,0x31,0x10,0xb5,0x04,0x46,0xd3,0xb1, -0x03,0x69,0x9a,0x68,0xd2,0x07,0x16,0xd5,0x82,0x7a,0x42,0xb1,0xd0,0xf8,0x0c,0x21, -0xd0,0xf8,0x0c,0x11,0x6f,0xf3,0x41,0x02,0x6f,0xf3,0x00,0x02,0x0a,0x60,0x5a,0x68, -0x05,0x20,0x42,0xf0,0x01,0x02,0x5a,0x60,0x01,0xf0,0xe2,0xfc,0x23,0x69,0x5a,0x68, -0x22,0xf0,0x01,0x02,0x5a,0x60,0x10,0xbd,0x83,0x7a,0x6b,0xb1,0x03,0x69,0x9b,0x68, -0xd9,0x07,0x41,0xbf,0xd0,0xf8,0x0c,0x31,0xd0,0xf8,0x0c,0x21,0x6f,0xf3,0x41,0x03, -0x6f,0xf3,0x00,0x03,0x48,0xbf,0x13,0x60,0x70,0x47,0x01,0x23,0x10,0xb5,0x00,0x22, -0x80,0xf8,0x12,0x31,0x04,0x46,0x03,0x46,0xff,0x21,0x04,0xe0,0x58,0x69,0x01,0x32, -0x81,0x60,0x18,0x6d,0x81,0x60,0x60,0x78,0x04,0x33,0x82,0x42,0xf6,0xd3,0x23,0x69, -0x00,0x22,0x1a,0x61,0x5a,0x61,0xda,0x61,0x4f,0xf0,0xff,0x32,0x9a,0x61,0x20,0x46, -0xff,0xf7,0xf4,0xfc,0x20,0x46,0x10,0x21,0xbd,0xe8,0x10,0x40,0xd1,0xe4,0x4b,0x78, -0x01,0x2b,0x0b,0x78,0x00,0xeb,0x83,0x00,0x0f,0xd1,0x83,0x69,0x18,0x68,0xc0,0xf3, -0x07,0x40,0x00,0xf0,0x20,0x03,0xdb,0xb2,0xcb,0xb9,0x00,0xf0,0x02,0x00,0xc0,0xb2, -0x00,0x28,0x0c,0xbf,0x30,0x20,0x20,0x20,0x70,0x47,0x43,0x6d,0x18,0x68,0xc0,0xf3, -0x07,0x40,0x00,0xf0,0x20,0x03,0xdb,0xb2,0x5b,0xb9,0x00,0xf0,0x02,0x00,0xc0,0xb2, -0x00,0x28,0x0c,0xbf,0x4f,0xf4,0x40,0x50,0x4f,0xf4,0x00,0x50,0x70,0x47,0x10,0x20, -0x70,0x47,0x4f,0xf4,0x80,0x50,0x70,0x47,0x4b,0x78,0x10,0xb5,0x01,0x2b,0x0b,0x78, -0x00,0xeb,0x83,0x03,0x0a,0xd1,0x9c,0x69,0x10,0x2a,0x23,0x68,0x02,0xd1,0xbd,0xe8, -0x10,0x40,0x10,0xe7,0x20,0x2a,0x0c,0xd0,0x30,0x2a,0x0f,0xe0,0x5c,0x6d,0xb2,0xf5, -0x80,0x5f,0x23,0x68,0x08,0xbf,0x43,0xf4,0x00,0x13,0x1a,0xd0,0xb2,0xf5,0x00,0x5f, -0x02,0xd1,0x43,0xf0,0x00,0x63,0x14,0xe0,0xb2,0xf5,0x40,0x5f,0x0e,0xd1,0xc3,0xf3, -0x07,0x42,0x02,0xf0,0x20,0x02,0x43,0xf0,0x80,0x63,0xd2,0xb2,0x43,0xf0,0x80,0x23, -0x3a,0xb1,0x00,0x23,0x4b,0x71,0xbd,0xe8,0x10,0x40,0x04,0xe7,0x0a,0xb9,0x62,0xf3, -0xcf,0x33,0x23,0x60,0x10,0xbd,0x00,0xbf,0xf8,0xb5,0x04,0x46,0xff,0xf7,0xb2,0xfb, -0x01,0x22,0x00,0x23,0x84,0xf8,0x12,0x21,0x84,0xf8,0x14,0x31,0x28,0x27,0x16,0x46, -0x19,0x46,0x40,0x25,0x10,0xe0,0x07,0xfb,0x03,0x40,0x80,0xf8,0x1c,0x31,0xa0,0xf8, -0x22,0x31,0x80,0xf8,0x1d,0x61,0x80,0xf8,0x1f,0x11,0xc0,0xf8,0x24,0x51,0xc0,0xf8, -0x28,0x11,0xc0,0xf8,0x30,0x11,0x01,0x33,0x62,0x78,0x93,0x42,0xeb,0xd3,0x00,0x23, -0x28,0x26,0x19,0x46,0x40,0x25,0x10,0xe0,0x06,0xfb,0x03,0x40,0x80,0xf8,0x74,0x33, -0xa0,0xf8,0x7a,0x33,0x80,0xf8,0x75,0x13,0x80,0xf8,0x77,0x13,0xc0,0xf8,0x7c,0x53, -0xc0,0xf8,0x80,0x13,0xc0,0xf8,0x88,0x13,0x01,0x33,0x62,0x78,0x93,0x42,0xeb,0xd3, -0x20,0x46,0xff,0xf7,0x27,0xfc,0x20,0x46,0xff,0xf7,0xd4,0xfb,0x00,0x21,0x20,0x46, -0xff,0xf7,0x5e,0xfc,0x20,0x46,0xff,0xf7,0xb5,0xfc,0x20,0x46,0xbd,0xe8,0xf8,0x40, -0xff,0xf7,0x11,0xbc,0x70,0xb5,0xcd,0xb2,0x0c,0x46,0x4f,0xf0,0x28,0x06,0x01,0xf0, -0x7f,0x01,0x06,0xfb,0x01,0x01,0x15,0xf0,0x80,0x0f,0x14,0xbf,0x01,0xf5,0x8e,0x71, -0x01,0xf5,0x5d,0x71,0x04,0xf0,0x7f,0x04,0xed,0x09,0x0c,0x70,0x4d,0x70,0x8a,0x60, -0xcb,0x70,0x05,0xb1,0xcc,0x80,0x02,0x2b,0x01,0xd1,0x00,0x23,0x0b,0x71,0xff,0xf7, -0x37,0xfd,0x00,0x20,0x70,0xbd,0x10,0xb5,0x01,0xf0,0x7f,0x03,0x4f,0xf0,0x28,0x04, -0x04,0xfb,0x03,0x03,0xca,0xb2,0x12,0xf0,0x80,0x0f,0x14,0xbf,0x03,0xf5,0x8e,0x73, -0x03,0xf5,0x5d,0x73,0x01,0xf0,0x7f,0x01,0xd2,0x09,0x19,0x70,0x5a,0x70,0x19,0x46, -0xff,0xf7,0x4d,0xfd,0x00,0x20,0x10,0xbd,0x38,0xb5,0x01,0xf0,0x7f,0x05,0x28,0x24, -0x04,0xfb,0x05,0x04,0x04,0xf5,0x5d,0x71,0x4b,0x61,0x00,0x23,0x8b,0x61,0x4b,0x70, -0xeb,0xb2,0xca,0x60,0x84,0xf8,0x74,0x33,0xc4,0x78,0x01,0x2c,0x08,0xbf,0x0a,0x61, -0x13,0xb9,0xff,0xf7,0xd9,0xfd,0x01,0xe0,0xff,0xf7,0x50,0xfd,0x00,0x20,0x38,0xbd, -0x70,0xb5,0x01,0xf0,0x7f,0x04,0x28,0x25,0x05,0xfb,0x04,0x05,0x05,0xf5,0x8e,0x71, -0x01,0x26,0xe4,0xb2,0xca,0x60,0x0a,0x61,0x00,0x22,0x85,0xf8,0x1c,0x41,0x4e,0x70, -0x05,0xf5,0x8c,0x75,0x8a,0x61,0x4b,0x61,0x14,0xb9,0xff,0xf7,0xbd,0xfd,0x01,0xe0, -0xff,0xf7,0x34,0xfd,0x00,0x20,0x70,0xbd,0xca,0xb2,0x12,0xf0,0x80,0x0f,0x4f,0xf0, -0x28,0x03,0x10,0xb5,0x15,0xbf,0x01,0xf0,0x7f,0x04,0x03,0xfb,0x01,0x03,0x03,0xfb, -0x04,0x03,0x03,0xf5,0x5d,0x73,0x18,0xbf,0x03,0xf5,0x8e,0x73,0x01,0xf0,0x7f,0x01, -0xd2,0x09,0x01,0x24,0x19,0x70,0x9c,0x70,0x5a,0x70,0x19,0x46,0xff,0xf7,0x0b,0xfe, -0x00,0x20,0x10,0xbd,0xca,0xb2,0x12,0xf0,0x80,0x0f,0x4f,0xf0,0x28,0x03,0x10,0xb5, -0x15,0xbf,0x01,0xf0,0x7f,0x04,0x03,0xfb,0x01,0x03,0x03,0xfb,0x04,0x03,0x03,0xf5, -0x5d,0x73,0x18,0xbf,0x03,0xf5,0x8e,0x73,0x01,0xf0,0x7f,0x01,0x00,0x24,0xd2,0x09, -0x19,0x70,0x9c,0x70,0x5a,0x70,0x19,0x46,0xff,0xf7,0x05,0xfe,0x20,0x46,0x10,0xbd, -0x08,0xb5,0x0b,0x06,0x04,0xd5,0x01,0xf0,0x7f,0x01,0xff,0xf7,0x6a,0xfb,0x01,0xe0, -0xff,0xf7,0x84,0xfb,0x00,0x20,0x08,0xbd,0x03,0x69,0x00,0x22,0x61,0xf3,0x0a,0x12, -0x19,0x68,0x0a,0x43,0x1a,0x60,0x70,0x47,0x03,0x69,0x03,0x20,0x5a,0x68,0x6f,0xf3, -0x41,0x02,0x5a,0x60,0x01,0xf0,0x2c,0xbb,0x03,0x69,0x03,0x20,0x5a,0x68,0x42,0xf0, -0x02,0x02,0x5a,0x60,0x01,0xf0,0x24,0xbb,0x11,0xf0,0x80,0x0f,0x4f,0xf0,0x28,0x03, -0x1b,0xbf,0x01,0xf0,0x7f,0x01,0x03,0xfb,0x01,0x01,0x03,0xfb,0x01,0x01,0x01,0xf5, -0x8e,0x71,0x08,0xbf,0x01,0xf5,0x5d,0x71,0xff,0xf7,0x69,0xbe,0x11,0xf0,0x80,0x0f, -0x4f,0xf0,0x28,0x03,0x1b,0xbf,0x01,0xf0,0x7f,0x01,0x03,0xfb,0x01,0x01,0x03,0xfb, -0x01,0x01,0x01,0xf5,0x8e,0x71,0x08,0xbf,0x01,0xf5,0x5d,0x71,0xff,0xf7,0x84,0xbe, -0x2d,0xe9,0xf0,0x4f,0x85,0xb0,0x04,0x46,0xff,0xf7,0x74,0xfb,0x00,0x28,0x00,0xf0, -0x5e,0x82,0x20,0x46,0xff,0xf7,0x7b,0xfb,0x05,0x46,0x00,0x2d,0x00,0xf0,0x57,0x82, -0xc5,0xf3,0x07,0x40,0x00,0xf0,0x08,0x00,0xc0,0xb2,0x00,0x28,0x5c,0xd0,0x20,0x46, -0xff,0xf7,0xb6,0xfd,0x27,0x46,0x82,0x46,0xa1,0x46,0x4f,0xf0,0x00,0x08,0xdf,0xf8, -0x6c,0xb3,0x2e,0x46,0x4b,0xe0,0x1a,0xf0,0x01,0x0f,0x41,0xd0,0x5f,0xfa,0x88,0xf2, -0x11,0x46,0x20,0x46,0x00,0x92,0xff,0xf7,0xa9,0xfd,0x10,0xf0,0x01,0x0f,0x05,0x46, -0x00,0x9a,0x22,0xd0,0x7b,0x6d,0x01,0x25,0x9d,0x60,0xe1,0x78,0x20,0x46,0xa9,0x42, -0x01,0xbf,0x1b,0x69,0xd9,0xf8,0x7c,0x13,0xc3,0xf3,0x12,0x03,0xc3,0xeb,0x01,0x03, -0x08,0xbf,0xc9,0xf8,0x8c,0x33,0xdb,0xf8,0x00,0x30,0x11,0x46,0x1b,0x68,0x98,0x47, -0xe3,0x78,0x01,0x2b,0x09,0xd1,0xb8,0xf1,0x00,0x0f,0x06,0xd1,0x94,0xf8,0x11,0x31, -0x05,0x2b,0x02,0xd1,0x20,0x46,0xff,0xf7,0x8f,0xfd,0x05,0xf0,0x02,0x03,0xdb,0xb2, -0x13,0xb1,0x7b,0x6d,0x02,0x25,0x9d,0x60,0x05,0xf0,0x08,0x05,0xed,0xb2,0x3d,0xb1, -0xdb,0xf8,0x00,0x30,0x20,0x46,0x9b,0x68,0x98,0x47,0x7b,0x6d,0x08,0x20,0x98,0x60, -0x08,0xf1,0x01,0x08,0x4f,0xea,0x5a,0x0a,0x04,0x37,0x09,0xf1,0x28,0x09,0xba,0xf1, -0x00,0x0f,0xb0,0xd1,0x35,0x46,0x01,0x20,0xc5,0xf3,0x07,0x43,0x03,0xf0,0x04,0x03, -0xdb,0xb2,0x00,0x2b,0x00,0xf0,0xa1,0x80,0x20,0x46,0xff,0xf7,0x5f,0xfd,0x27,0x46, -0x83,0x46,0x4f,0xf0,0x00,0x08,0x01,0x95,0x91,0xe0,0x1b,0xf0,0x01,0x0f,0x00,0xf0, -0x89,0x80,0x23,0x69,0x5f,0xfa,0x88,0xf9,0x19,0x69,0x5d,0x6b,0x04,0xeb,0x89,0x02, -0x25,0xfa,0x09,0xf5,0x92,0x69,0xed,0x01,0x92,0x68,0xed,0xb2,0x0d,0x43,0x15,0x40, -0xea,0x07,0x1c,0xd5,0x01,0x20,0x00,0xfa,0x08,0xf1,0x5a,0x6b,0x05,0x46,0x22,0xea, -0x01,0x02,0x5a,0x63,0xbb,0x69,0x99,0x4a,0x98,0x60,0x13,0x68,0x20,0x46,0x5b,0x68, -0x49,0x46,0x98,0x47,0xe3,0x78,0xab,0x42,0x09,0xd1,0xb8,0xf1,0x00,0x0f,0x06,0xd1, -0x94,0xf8,0x11,0x31,0x04,0x2b,0x02,0xd1,0x20,0x46,0xff,0xf7,0x2d,0xfd,0x05,0xf0, -0x08,0x03,0xdb,0xb2,0x13,0xb1,0xbb,0x69,0x08,0x25,0x9d,0x60,0x05,0xf0,0x10,0x03, -0xdb,0xb2,0x13,0xb1,0xbb,0x69,0x10,0x25,0x9d,0x60,0x05,0xf0,0x40,0x03,0xdb,0xb2, -0x13,0xb1,0xbb,0x69,0x40,0x25,0x9d,0x60,0x05,0xf0,0x02,0x03,0xdb,0xb2,0x13,0xb1, -0xbb,0x69,0x02,0x25,0x9d,0x60,0x25,0xf0,0x7f,0x05,0x15,0xf0,0xff,0x0f,0x39,0xd0, -0x28,0x25,0x05,0xfb,0x08,0x45,0x05,0xf5,0x8e,0x75,0xab,0x69,0x6a,0x69,0xc2,0x46, -0xc3,0xeb,0x02,0x0c,0xab,0x68,0xa0,0x46,0x9c,0x45,0x28,0xbf,0x9c,0x46,0x0c,0xf1, -0x03,0x0c,0xbb,0x69,0x4f,0xea,0x9c,0x0c,0x9b,0x69,0x66,0x46,0x14,0xe0,0xaa,0x68, -0x1c,0x1b,0x94,0x42,0x28,0xbf,0x14,0x46,0xa3,0xb2,0x40,0x46,0xe9,0x68,0x4a,0x46, -0xff,0xf7,0x52,0xf9,0xeb,0x68,0xe6,0x1c,0x1b,0x19,0xeb,0x60,0xab,0x69,0xb6,0x08, -0x1c,0x19,0xac,0x61,0xbb,0x69,0x9b,0x69,0x9b,0xb2,0xb3,0x42,0x05,0xd9,0xac,0x69, -0x6b,0x69,0x9c,0x42,0x01,0xd2,0x00,0x2b,0xe1,0xd1,0xbb,0x69,0x80,0x25,0x44,0x46, -0x9d,0x60,0xd0,0x46,0x08,0xf1,0x01,0x08,0x4f,0xea,0x5b,0x0b,0x04,0x37,0xbb,0xf1, -0x00,0x0f,0x7f,0xf4,0x6a,0xaf,0x01,0x9d,0x01,0x20,0x05,0xf0,0x02,0x03,0xdb,0xb2, -0x13,0xb1,0xe3,0x68,0x02,0x22,0x5a,0x61,0xc5,0xf3,0x07,0x63,0x03,0xf0,0x80,0x03, -0xdb,0xb2,0xcb,0xb1,0xa3,0x7a,0x43,0xb1,0xd4,0xf8,0x0c,0x31,0xd4,0xf8,0x0c,0x21, -0x6f,0xf3,0x41,0x03,0x6f,0xf3,0x00,0x03,0x13,0x60,0x23,0x69,0x20,0x46,0x5a,0x68, -0x22,0xf0,0x01,0x02,0x5a,0x60,0x4d,0x4b,0x1b,0x68,0x9b,0x69,0x98,0x47,0xe3,0x68, -0x4f,0xf0,0x00,0x42,0x5a,0x61,0x01,0x20,0xc5,0xf3,0x07,0x23,0x03,0xf0,0x08,0x03, -0xdb,0xb2,0x00,0x2b,0x2e,0xd0,0x00,0x23,0x8d,0xf8,0x0f,0x30,0x94,0xf8,0x12,0x31, -0x20,0x46,0x8d,0xf8,0x0f,0x30,0x41,0x4b,0x1b,0x68,0x5b,0x69,0x98,0x47,0x23,0x69, -0xe2,0x68,0x4f,0xf4,0x00,0x61,0x9b,0x68,0x51,0x61,0xa2,0x7a,0xca,0xb1,0xdb,0x07, -0x17,0xd5,0x94,0xf8,0x15,0x01,0x01,0x28,0x13,0xd1,0x9d,0xf8,0x0f,0x30,0x03,0x2b, -0x10,0xd1,0xd4,0xf8,0x0c,0x31,0x1a,0x68,0x42,0xf0,0x01,0x02,0x1a,0x60,0x1a,0x68, -0x42,0xf0,0x03,0x02,0x1a,0x60,0x32,0x4b,0x1a,0x69,0x42,0xf0,0x06,0x02,0x1a,0x61, -0x00,0xe0,0x01,0x20,0x05,0xf0,0x08,0x03,0xdb,0xb2,0x43,0xb1,0x2b,0x4b,0x20,0x46, -0x1b,0x68,0xdb,0x68,0x98,0x47,0xe3,0x68,0x08,0x22,0x5a,0x61,0x01,0x20,0x05,0xf0, -0x10,0x03,0xdb,0xb2,0x00,0x2b,0x34,0xd0,0xe3,0x68,0x28,0x26,0x9a,0x69,0x22,0xf0, -0x10,0x02,0x9a,0x61,0x1f,0x6a,0x07,0xf0,0x0f,0x03,0x06,0xfb,0x03,0x46,0xc7,0xf3, -0x43,0x43,0x02,0x2b,0x06,0xf5,0x5d,0x76,0x02,0xd0,0x06,0x2b,0x1b,0xd1,0x0e,0xe0, -0x47,0xf6,0xf0,0x73,0x3b,0x40,0xb3,0xb1,0xc7,0xf3,0x0a,0x17,0x20,0x46,0xf1,0x68, -0x3a,0x46,0xff,0xf7,0xb5,0xf8,0xf3,0x68,0xdb,0x19,0xf3,0x60,0x08,0xe0,0x04,0xf5, -0xb8,0x61,0x0c,0x31,0x20,0x46,0x08,0x22,0xff,0xf7,0xaa,0xf8,0xc7,0xf3,0x0a,0x17, -0xb3,0x69,0xdf,0x19,0xb7,0x61,0xe3,0x68,0x01,0x20,0x9a,0x69,0x42,0xf0,0x10,0x02, -0x9a,0x61,0xc5,0xf3,0x07,0x23,0x03,0xf0,0x10,0x03,0xdb,0xb2,0x00,0x2b,0x38,0xd0, -0x23,0x69,0x00,0x26,0x5a,0x68,0x31,0x46,0x22,0xf0,0x01,0x02,0x5a,0x60,0x20,0x46, -0xff,0xf7,0x57,0xf9,0x23,0x46,0x32,0x46,0xff,0x21,0x08,0xe0,0x6c,0x77,0x00,0x20, -0x00,0xed,0x00,0xe0,0x58,0x69,0x01,0x32,0x81,0x60,0x18,0x6d,0x81,0x60,0x60,0x78, -0x04,0x33,0x82,0x42,0xf6,0xd3,0x23,0x69,0x01,0x27,0x4f,0xf0,0xff,0x32,0x67,0xf3, -0x0f,0x06,0x9a,0x61,0x67,0xf3,0x1f,0x46,0x0b,0x22,0xde,0x61,0x5a,0x61,0x1a,0x61, -0x1a,0x68,0x20,0x46,0x6f,0xf3,0x0a,0x12,0x1a,0x60,0xff,0xf7,0xed,0xfb,0xe3,0x68, -0x4f,0xf4,0x80,0x52,0x5a,0x61,0x37,0x4b,0x20,0x46,0x1b,0x68,0x1b,0x69,0x98,0x47, -0x38,0x46,0xc5,0xf3,0x07,0x23,0x03,0xf0,0x20,0x03,0xdb,0xb2,0xeb,0xb1,0x20,0x46, -0xff,0xf7,0x40,0xfa,0xe3,0x68,0x20,0x46,0xde,0x68,0xff,0xf7,0x2b,0xfa,0x03,0x28, -0x06,0xd1,0x00,0x23,0xa3,0x70,0x4f,0xf4,0x00,0x73,0xa3,0x80,0x09,0x23,0x04,0xe0, -0x01,0x23,0x40,0x20,0xa3,0x70,0xa0,0x80,0x05,0x23,0x63,0xf3,0x8d,0x26,0xe3,0x68, -0x4f,0xf4,0x00,0x52,0xde,0x60,0x01,0x20,0x5a,0x61,0xc5,0xf3,0x07,0x43,0x03,0xf0, -0x10,0x03,0xdb,0xb2,0x4b,0xb1,0x1f,0x4b,0x20,0x46,0x1b,0x68,0xdb,0x69,0x98,0x47, -0xe3,0x68,0x4f,0xf4,0x80,0x12,0x5a,0x61,0x01,0x20,0xc5,0xf3,0x07,0x43,0x03,0xf0, -0x20,0x03,0xdb,0xb2,0x4b,0xb1,0x17,0x4b,0x20,0x46,0x1b,0x68,0x1b,0x6a,0x98,0x47, -0xe3,0x68,0x4f,0xf4,0x00,0x12,0x5a,0x61,0x01,0x20,0xc5,0xf3,0x07,0x63,0x03,0xf0, -0x40,0x03,0xdb,0xb2,0x4b,0xb1,0x0f,0x4b,0x20,0x46,0x1b,0x68,0x5b,0x6a,0x98,0x47, -0xe3,0x68,0x4f,0xf0,0x80,0x42,0x5a,0x61,0x01,0x20,0x05,0xf0,0x04,0x05,0xed,0xb2, -0x6d,0xb1,0xe3,0x68,0x5d,0x68,0x05,0xf0,0x04,0x03,0xdb,0xb2,0x23,0xb1,0x05,0x4b, -0x20,0x46,0x1b,0x68,0x9b,0x6a,0x98,0x47,0xe3,0x68,0x01,0x20,0x5d,0x60,0x05,0xb0, -0xbd,0xe8,0xf0,0x8f,0x6c,0x77,0x00,0x20,0xd0,0xf8,0xe8,0x35,0x10,0xb5,0x1b,0x69, -0x04,0x46,0x98,0x47,0x03,0x23,0x84,0xf8,0x12,0x31,0x00,0x20,0x10,0xbd,0x08,0xb5, -0x90,0xf8,0x12,0x31,0x80,0xf8,0x13,0x31,0x04,0x23,0x80,0xf8,0x12,0x31,0xd0,0xf8, -0xe8,0x35,0xdb,0x68,0x98,0x47,0x00,0x20,0x08,0xbd,0x08,0xb5,0xd0,0xf8,0xe4,0x35, -0xdb,0x69,0x03,0xb1,0x98,0x47,0x00,0x20,0x08,0xbd,0x08,0xb5,0xd0,0xf8,0xe4,0x35, -0x1b,0x6a,0x98,0x47,0x00,0x20,0x08,0xbd,0x08,0xb5,0xd0,0xf8,0xe4,0x35,0x5b,0x6a, -0x98,0x47,0x00,0x20,0x08,0xbd,0xd0,0xf8,0xe8,0x35,0x10,0xb5,0x5b,0x69,0x04,0x46, -0x98,0x47,0x01,0x23,0x84,0xf8,0x15,0x31,0x00,0x20,0x10,0xbd,0xd0,0xf8,0xe8,0x35, -0x10,0xb5,0x9b,0x69,0x04,0x46,0x98,0x47,0xd4,0xf8,0xe4,0x35,0x20,0x46,0x5b,0x68, -0x00,0x21,0x98,0x47,0x00,0x20,0x84,0xf8,0x15,0x01,0x10,0xbd,0x00,0x21,0x10,0xb5, -0x40,0x22,0x04,0x46,0x0b,0x46,0xff,0xf7,0x4d,0xfc,0x80,0x21,0x40,0x22,0x00,0x23, -0x20,0x46,0xff,0xf7,0x47,0xfc,0x01,0x23,0x84,0xf8,0x12,0x31,0xd4,0xf8,0xe8,0x35, -0xa0,0x78,0x5b,0x68,0x98,0x47,0x00,0x20,0x10,0xbd,0x13,0xb5,0x69,0x46,0x04,0x46, -0x00,0xf0,0x3c,0xf9,0x9d,0xf8,0x00,0x10,0x01,0xf0,0x1f,0x03,0x01,0x2b,0x07,0xd0, -0x02,0x2b,0x0a,0xd0,0x73,0xb9,0x20,0x46,0x69,0x46,0x00,0xf0,0xeb,0xf9,0x0f,0xe0, -0x20,0x46,0x69,0x46,0x00,0xf0,0xcc,0xf9,0x0a,0xe0,0x20,0x46,0x69,0x46,0x00,0xf0, -0x55,0xf9,0x05,0xe0,0x21,0xf0,0x7f,0x01,0xc9,0xb2,0x20,0x46,0xff,0xf7,0x8c,0xfc, -0x00,0x20,0x1c,0xbd,0x38,0xb5,0x04,0x46,0x00,0x29,0x48,0xd1,0x90,0xf8,0x11,0x31, -0x02,0x2b,0x38,0xd1,0xd0,0xf8,0x38,0x21,0xd0,0xf8,0x24,0x31,0x9a,0x42,0x11,0xd9, -0xc1,0x78,0xd2,0x1a,0x01,0x29,0x08,0xbf,0xd0,0xf8,0x28,0x11,0xc0,0xf8,0x38,0x21, -0x04,0xbf,0xcb,0x18,0xc0,0xf8,0x28,0x31,0x92,0xb2,0xd4,0xf8,0x28,0x11,0x00,0xf0, -0xb7,0xf8,0x20,0xe0,0xd0,0xf8,0x3c,0x21,0xb2,0xfb,0xf3,0xf5,0x03,0xfb,0x15,0x25, -0x65,0xb9,0x9a,0x42,0x0a,0xd3,0xd0,0xf8,0x40,0x31,0x9a,0x42,0x06,0xd2,0x29,0x46, -0x2a,0x46,0x00,0xf0,0xa5,0xf8,0xc4,0xf8,0x40,0x51,0x0c,0xe0,0xd4,0xf8,0xe4,0x35, -0xdb,0x68,0x2b,0xb1,0x94,0xf8,0x12,0x21,0x03,0x2a,0x01,0xd1,0x20,0x46,0x98,0x47, -0x20,0x46,0x00,0xf0,0xc6,0xf8,0x94,0xf8,0x16,0x31,0x01,0x2b,0x10,0xd1,0x09,0x4a, -0x23,0x69,0x12,0x68,0x5a,0x60,0x00,0x23,0x84,0xf8,0x16,0x31,0x08,0xe0,0xd0,0xf8, -0xe4,0x35,0x5b,0x69,0x23,0xb1,0x90,0xf8,0x12,0x21,0x03,0x2a,0x00,0xd1,0x98,0x47, -0x00,0x20,0x38,0xbd,0x80,0x9f,0x00,0x20,0x10,0xb5,0x04,0x46,0x59,0xbb,0x90,0xf8, -0x11,0x31,0x03,0x2b,0x30,0xd1,0xd0,0xf8,0x90,0x23,0xd0,0xf8,0x7c,0x33,0x9a,0x42, -0x14,0xd9,0xc1,0x78,0xd2,0x1a,0x01,0x29,0x08,0xbf,0xd0,0xf8,0x80,0x13,0xc0,0xf8, -0x90,0x23,0x04,0xbf,0xc9,0x18,0xc0,0xf8,0x80,0x13,0x9a,0x42,0x28,0xbf,0x1a,0x46, -0x92,0xb2,0xd0,0xf8,0x80,0x13,0x00,0xf0,0x74,0xf8,0x15,0xe0,0xd0,0xf8,0xe4,0x35, -0x1b,0x69,0x23,0xb1,0x90,0xf8,0x12,0x21,0x03,0x2a,0x00,0xd1,0x98,0x47,0x20,0x46, -0x00,0xf0,0x70,0xf8,0x08,0xe0,0xd0,0xf8,0xe4,0x35,0x9b,0x69,0x23,0xb1,0x90,0xf8, -0x12,0x21,0x03,0x2a,0x00,0xd1,0x98,0x47,0x00,0x20,0x10,0xbd,0x2d,0xe9,0xf0,0x41, -0x06,0x9f,0x04,0x46,0x16,0x46,0x98,0x46,0x0d,0x46,0x00,0xf0,0x0f,0xff,0x20,0x46, -0x29,0x46,0xc4,0xf8,0xe4,0x85,0xc4,0xf8,0xe8,0x75,0xc4,0xf8,0xec,0x65,0xff,0xf7, -0x23,0xfb,0xd4,0xf8,0xe8,0x35,0x1b,0x68,0x98,0x47,0x20,0x46,0xbd,0xe8,0xf0,0x41, -0x00,0xf0,0x3a,0xbf,0x00,0x20,0x70,0x47,0xd0,0xf8,0xe4,0x35,0x10,0xb5,0x1b,0x68, -0x04,0x46,0x98,0x47,0xd4,0xf8,0xe8,0x35,0x9b,0x68,0x98,0x47,0x00,0x20,0x10,0xbd, -0x08,0xb5,0xd0,0xf8,0xe4,0x35,0x5b,0x68,0x98,0x47,0x00,0x20,0x08,0xbd,0x00,0xbf, -0x10,0xb5,0x13,0x46,0x0c,0x46,0xc0,0xf8,0x3c,0x21,0xc0,0xf8,0x38,0x21,0x02,0x22, -0x80,0xf8,0x11,0x21,0x00,0x21,0x22,0x46,0xff,0xf7,0x9a,0xfb,0x00,0x20,0x10,0xbd, -0x10,0xb5,0x0c,0x46,0x13,0x46,0x00,0x21,0x22,0x46,0xff,0xf7,0x91,0xfb,0x00,0x20, -0x10,0xbd,0x10,0xb5,0x13,0x46,0x0c,0x46,0xc0,0xf8,0x94,0x23,0xc0,0xf8,0x90,0x23, -0x03,0x22,0x80,0xf8,0x11,0x21,0x00,0x21,0x22,0x46,0xff,0xf7,0x65,0xfb,0x00,0x20, -0x10,0xbd,0x10,0xb5,0x0c,0x46,0x13,0x46,0x00,0x21,0x22,0x46,0xff,0xf7,0x5c,0xfb, -0x00,0x20,0x10,0xbd,0x00,0x21,0x04,0x23,0x10,0xb5,0x0a,0x46,0x04,0x46,0x80,0xf8, -0x11,0x31,0x0b,0x46,0xff,0xf7,0x6c,0xfb,0x20,0x46,0xff,0xf7,0xed,0xf9,0x00,0x20, -0x10,0xbd,0x00,0x21,0x05,0x23,0x10,0xb5,0x0a,0x46,0x04,0x46,0x80,0xf8,0x11,0x31, -0x0b,0x46,0xff,0xf7,0x41,0xfb,0x20,0x46,0xff,0xf7,0xde,0xf9,0x00,0x20,0x10,0xbd, -0x28,0x23,0x03,0xfb,0x01,0x00,0xb0,0xf8,0x8c,0x03,0x70,0x47,0x90,0xf8,0xcc,0x35, -0x0b,0x70,0x90,0xf8,0xcd,0x35,0x4b,0x70,0x90,0xf8,0xcf,0x25,0x90,0xf8,0xce,0x35, -0x03,0xeb,0x02,0x23,0x4b,0x80,0x90,0xf8,0xd1,0x25,0x90,0xf8,0xd0,0x35,0x03,0xeb, -0x02,0x23,0x8b,0x80,0x90,0xf8,0xd3,0x25,0x90,0xf8,0xd2,0x35,0x03,0xeb,0x02,0x23, -0x9b,0xb2,0xcb,0x80,0xc0,0xf8,0x40,0x31,0x01,0x23,0x80,0xf8,0x11,0x31,0x70,0x47, -0x10,0xb5,0x80,0x21,0x04,0x46,0xff,0xf7,0x47,0xfb,0x20,0x46,0x00,0x21,0xff,0xf7, -0x43,0xfb,0x20,0x46,0xbd,0xe8,0x10,0x40,0xff,0xf7,0xa6,0xb9,0x38,0xb5,0x0d,0x46, -0x6b,0x78,0x04,0x46,0x01,0x2b,0x09,0x79,0x16,0xd0,0x33,0xd3,0x03,0x2b,0x63,0xd1, -0x90,0xf8,0x12,0x31,0x02,0x2b,0x34,0xd0,0x03,0x2b,0x59,0xd1,0x6b,0x88,0xfb,0xb9, -0x0b,0x1c,0x18,0xbf,0x01,0x23,0x80,0x29,0x0c,0xbf,0x00,0x23,0x03,0xf0,0x01,0x03, -0xb3,0xb1,0xff,0xf7,0x21,0xfb,0x13,0xe0,0x90,0xf8,0x12,0x31,0x02,0x2b,0x20,0xd0, -0x03,0x2b,0x45,0xd1,0x6b,0x88,0x00,0x2b,0x46,0xd1,0x0b,0x1c,0x18,0xbf,0x01,0x23, -0x80,0x29,0x0c,0xbf,0x00,0x23,0x03,0xf0,0x01,0x03,0x3b,0xb1,0xff,0xf7,0x2a,0xfb, -0xd4,0xf8,0xe4,0x35,0x20,0x46,0x9b,0x68,0x29,0x46,0x98,0x47,0x20,0x46,0xff,0xf7, -0x71,0xff,0x31,0xe0,0x90,0xf8,0x12,0x31,0x02,0x2b,0x02,0xd0,0x03,0x2b,0x27,0xd1, -0x0c,0xe0,0x0b,0x1c,0x18,0xbf,0x01,0x23,0x80,0x29,0x0c,0xbf,0x00,0x23,0x03,0xf0, -0x01,0x03,0x0b,0xb3,0x20,0x46,0xff,0xf7,0xef,0xfa,0x1d,0xe0,0x11,0xf0,0x80,0x0f, -0x4f,0xf0,0x28,0x03,0x1b,0xbf,0x01,0xf0,0x7f,0x01,0x03,0xfb,0x01,0x03,0x03,0xfb, -0x01,0x01,0x93,0xf8,0x1e,0x21,0x08,0xbf,0x91,0xf8,0x76,0x23,0x07,0x4b,0x02,0xb1, -0x01,0x22,0x1a,0x60,0x20,0x46,0x05,0x49,0x02,0x22,0xff,0xf7,0x11,0xff,0x03,0xe0, -0x20,0x46,0x29,0x46,0xff,0xf7,0x84,0xff,0x00,0x20,0x38,0xbd,0x14,0x79,0x00,0x20, -0x38,0xb5,0x90,0xf8,0x12,0x31,0x04,0x46,0x03,0x2b,0x0d,0x46,0x0c,0xd1,0x0b,0x79, -0x01,0x2b,0x09,0xd8,0xd0,0xf8,0xe4,0x35,0x9b,0x68,0x98,0x47,0xeb,0x88,0x3b,0xb9, -0x20,0x46,0xff,0xf7,0x27,0xff,0x03,0xe0,0x20,0x46,0x29,0x46,0xff,0xf7,0x68,0xff, -0x00,0x20,0x38,0xbd,0x73,0xb5,0x4b,0x78,0x04,0x46,0x0d,0x46,0x09,0x2b,0x00,0xf2, -0x1b,0x81,0xdf,0xe8,0x13,0xf0,0xcc,0x00,0x07,0x01,0x19,0x01,0xdf,0x00,0x19,0x01, -0x72,0x00,0x0a,0x00,0x19,0x01,0xbc,0x00,0x90,0x00,0x6b,0x88,0x1a,0x0a,0x01,0x3a, -0x06,0x2a,0x00,0xf2,0x09,0x81,0xdf,0xe8,0x12,0xf0,0x07,0x00,0x1a,0x00,0x27,0x00, -0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0xd0,0xf8,0xec,0x35,0x0d,0xf1,0x06,0x01, -0x1b,0x68,0x80,0x78,0x98,0x47,0xeb,0x88,0x01,0x46,0x40,0x2b,0x03,0xd0,0x94,0xf8, -0x12,0x31,0x01,0x2b,0x3a,0xd1,0x08,0x22,0xad,0xf8,0x06,0x20,0x36,0xe0,0xd0,0xf8, -0xe4,0x35,0x0d,0xf1,0x06,0x01,0x9b,0x6a,0x80,0x78,0x98,0x47,0x02,0x23,0x43,0x70, -0x01,0x46,0xc4,0xf8,0xf0,0x05,0x29,0xe0,0xdb,0xb2,0x05,0x2b,0x00,0xf2,0xdc,0x80, -0xdf,0xe8,0x03,0xf0,0x03,0x08,0x0d,0x12,0x17,0x1c,0xd0,0xf8,0xec,0x35,0x80,0x78, -0x5b,0x68,0x17,0xe0,0xd0,0xf8,0xec,0x35,0x80,0x78,0x9b,0x68,0x12,0xe0,0xd0,0xf8, -0xec,0x35,0x80,0x78,0xdb,0x68,0x0d,0xe0,0xd0,0xf8,0xec,0x35,0x80,0x78,0x1b,0x69, -0x08,0xe0,0xd0,0xf8,0xec,0x35,0x80,0x78,0x5b,0x69,0x03,0xe0,0xd0,0xf8,0xec,0x35, -0x80,0x78,0x9b,0x69,0x0d,0xf1,0x06,0x01,0x98,0x47,0x01,0x46,0xbd,0xf8,0x06,0x30, -0x00,0x2b,0x00,0xf0,0xb5,0x80,0xea,0x88,0x00,0x2a,0x00,0xf0,0xb1,0x80,0x9a,0x42, -0x28,0xbf,0x1a,0x46,0xad,0xf8,0x06,0x20,0x57,0xe0,0xab,0x88,0x00,0x2b,0x40,0xf0, -0xa3,0x80,0xeb,0x88,0x00,0x2b,0x40,0xf0,0x9f,0x80,0x90,0xf8,0x12,0x21,0x6b,0x88, -0x03,0x2a,0x00,0xf0,0x99,0x80,0x03,0xf0,0x7f,0x05,0x80,0xf8,0x14,0x51,0x29,0x46, -0xff,0xf7,0x6a,0xfa,0x20,0x46,0xff,0xf7,0x8d,0xfe,0x02,0x23,0x05,0xb9,0x01,0x23, -0x84,0xf8,0x12,0x31,0x8c,0xe0,0xa9,0x78,0x46,0x4e,0x01,0x29,0x31,0x71,0x00,0xf2, -0x83,0x80,0x90,0xf8,0x12,0x31,0x02,0x2b,0x02,0xd0,0x03,0x2b,0x7c,0xd1,0x08,0xe0, -0x00,0x29,0x63,0xd0,0x01,0x21,0x03,0x23,0x80,0xf8,0x10,0x11,0x80,0xf8,0x12,0x31, -0x11,0xe0,0x39,0xb9,0x02,0x23,0x80,0xf8,0x12,0x31,0x80,0xf8,0x10,0x11,0xff,0xf7, -0x2f,0xfe,0x53,0xe0,0x90,0xf8,0x10,0x11,0x01,0x29,0x50,0xd0,0xff,0xf7,0x28,0xfe, -0x31,0x79,0x84,0xf8,0x10,0x11,0x20,0x46,0xff,0xf7,0x16,0xfe,0x46,0xe0,0xea,0x88, -0x01,0x2a,0x59,0xd1,0x90,0xf8,0x12,0x31,0x02,0x2b,0x02,0xd0,0x03,0x2b,0x53,0xd1, -0x01,0xe0,0x2d,0x49,0x13,0xe0,0x00,0xf5,0x88,0x71,0x20,0x46,0x0f,0xe0,0x90,0xf8, -0x12,0x31,0x02,0x3b,0x01,0x2b,0x47,0xd8,0x26,0x4b,0x01,0x22,0xda,0x60,0xd0,0xf8, -0x18,0x21,0x0a,0xb1,0x03,0x22,0xda,0x60,0x24,0x49,0x20,0x46,0x02,0x22,0xff,0xf7, -0x07,0xfe,0x3d,0xe0,0x6b,0x88,0x01,0x2b,0x2d,0xd0,0x02,0x2b,0x38,0xd1,0xab,0x88, -0x13,0xf0,0xff,0x0f,0x34,0xd1,0x02,0x69,0x1b,0x0a,0x01,0x3b,0x52,0x68,0x04,0x2b, -0x0f,0xd8,0xdf,0xe8,0x03,0xf0,0x03,0x05,0x07,0x09,0x0b,0x00,0x01,0x23,0x06,0xe0, -0x02,0x23,0x04,0xe0,0x03,0x23,0x02,0xe0,0x04,0x23,0x00,0xe0,0x05,0x23,0x63,0xf3, -0x06,0x12,0x13,0x4b,0x1a,0x60,0x01,0x23,0x84,0xf8,0x16,0x31,0x20,0x46,0xff,0xf7, -0x11,0xfe,0x15,0xe0,0x90,0xf8,0x12,0x31,0x02,0x3b,0x01,0x2b,0x0c,0xd8,0x6b,0x88, -0x01,0x2b,0x0d,0xd1,0x00,0x23,0xc4,0xf8,0x18,0x31,0xd4,0xf8,0xe4,0x35,0x20,0x46, -0x9b,0x68,0x29,0x46,0x98,0x47,0xe9,0xe7,0x20,0x46,0x29,0x46,0xff,0xf7,0x40,0xfe, -0x00,0x20,0x7c,0xbd,0x14,0x79,0x00,0x20,0x1c,0x79,0x00,0x20,0x20,0x79,0x00,0x20, -0x80,0x9f,0x00,0x20,0x30,0xb5,0xc8,0xb1,0x00,0x23,0xdd,0xb2,0x01,0x33,0xc4,0x18, -0x14,0xf8,0x01,0x4c,0x00,0x2c,0xf8,0xd1,0x6b,0x1c,0x5b,0x00,0x13,0x80,0x0b,0x70, -0x03,0x23,0x4b,0x70,0x02,0x23,0x05,0xe0,0xca,0x54,0x5a,0x1c,0xd2,0xb2,0x02,0x33, -0x8c,0x54,0xdb,0xb2,0x10,0xf8,0x01,0x2b,0x00,0x2a,0xf5,0xd1,0x30,0xbd,0x00,0xbf, -0x10,0xb5,0x08,0x4b,0x08,0x4c,0x18,0x78,0x12,0x02,0x04,0xf8,0x30,0x10,0x04,0xeb, -0xc0,0x04,0x01,0x30,0xc0,0xb2,0x04,0x28,0x62,0x60,0x18,0x70,0x01,0xd1,0x00,0x22, -0x1a,0x70,0x10,0xbd,0xfc,0x9f,0x00,0x20,0xd4,0x9f,0x00,0x20,0xf8,0xb5,0x0d,0x4b, -0x0d,0x4d,0x1b,0x68,0x0e,0x46,0x17,0x46,0x5b,0x68,0x29,0x46,0x0b,0x4a,0x04,0x46, -0x98,0x47,0x18,0xb1,0x20,0x46,0x02,0x21,0x3a,0x22,0x06,0xe0,0x2b,0x68,0xbe,0x19, -0x9e,0x42,0x05,0xd9,0x20,0x46,0x05,0x21,0x21,0x22,0xff,0xf7,0xd1,0xff,0xff,0x20, -0x40,0xb2,0xf8,0xbd,0xec,0x78,0x00,0x20,0xc4,0x9f,0x00,0x20,0xc8,0x9f,0x00,0x20, -0x2d,0xe9,0xf7,0x43,0xdf,0xf8,0xc8,0x92,0x0c,0x46,0xc9,0xf8,0x00,0x00,0x13,0x78, -0x16,0x46,0x1e,0x2b,0x7a,0xd0,0x0d,0xd8,0x12,0x2b,0x5a,0xd0,0x04,0xd8,0xeb,0xb1, -0x03,0x2b,0x40,0xf0,0x1c,0x82,0x29,0xe0,0x1a,0x2b,0x73,0xd0,0x1b,0x2b,0x40,0xf0, -0x16,0x82,0x6b,0xe0,0x28,0x2b,0x00,0xf0,0xd2,0x80,0x06,0xd8,0x23,0x2b,0x00,0xf0, -0x83,0x80,0x25,0x2b,0x40,0xf0,0x0b,0x82,0xa7,0xe0,0x2f,0x2b,0x00,0xf0,0xf2,0x81, -0x5a,0x2b,0x6c,0xd0,0x2a,0x2b,0x40,0xf0,0x02,0x82,0x58,0xe1,0x8e,0x4b,0x9a,0x68, -0x00,0x2a,0x40,0xf0,0x5d,0x81,0x8d,0x4b,0x08,0x46,0x1b,0x68,0x9b,0x68,0x98,0x47, -0x00,0x28,0x40,0xf0,0x5d,0x81,0x8a,0x4b,0x18,0x80,0x8c,0xe0,0x00,0x22,0x89,0x48, -0x11,0x46,0x11,0x54,0x01,0x32,0x12,0x2a,0x86,0x4b,0xfa,0xd1,0x70,0x22,0x86,0x49, -0x86,0x48,0x1a,0x70,0x0c,0x22,0xda,0x71,0x00,0x78,0x0a,0x78,0x90,0x42,0x10,0xd0, -0x83,0x48,0x10,0xf8,0x32,0x40,0x00,0xeb,0xc2,0x00,0x9c,0x70,0x44,0x79,0x01,0x32, -0x1c,0x73,0xd2,0xb2,0x00,0x79,0x04,0x2a,0x58,0x73,0x0a,0x70,0x01,0xd1,0x00,0x23, -0x0b,0x70,0x77,0x4b,0x12,0x22,0x1a,0x80,0x32,0x79,0x12,0x2a,0x00,0xf2,0xcb,0x81, -0x1e,0xe0,0x53,0x78,0xdb,0x07,0x0c,0xd4,0x70,0x4b,0x24,0x22,0x1b,0x68,0xdb,0x69, -0x02,0xfb,0x01,0x34,0x25,0x79,0x33,0x79,0x05,0x35,0x9d,0x42,0x28,0xbf,0x1d,0x46, -0x01,0xe0,0x70,0x4c,0x07,0x25,0x6a,0x4b,0x1d,0x80,0x6a,0x4b,0x03,0xe0,0x01,0x3d, -0xad,0xb2,0x62,0x5d,0x5a,0x55,0x00,0x2d,0xf9,0xd1,0xaf,0xe1,0x64,0x4b,0x00,0x22, -0x1a,0x80,0xa8,0xe1,0x62,0x4b,0x08,0x22,0x1a,0x80,0x62,0x4a,0x66,0x4b,0x08,0x25, -0x01,0x3d,0xad,0xb2,0x59,0x5d,0x51,0x55,0x00,0x2d,0xf9,0xd1,0x9e,0xe1,0x5c,0x4b, -0x08,0x22,0x1a,0x80,0x5b,0x4a,0x61,0x4b,0x08,0x25,0x01,0x3d,0xad,0xb2,0x59,0x5d, -0x51,0x55,0x00,0x2d,0xf9,0xd1,0x91,0xe1,0x00,0x27,0x56,0x4a,0x3b,0x46,0xbb,0x54, -0x01,0x37,0x0c,0x2f,0x53,0x4e,0xfa,0xd1,0x50,0x4b,0x20,0x46,0x1b,0x68,0x01,0xa9, -0x5b,0x68,0x6a,0x46,0x98,0x47,0x00,0x28,0x40,0xf0,0xe2,0x80,0x08,0x23,0xf3,0x70, -0x01,0x9b,0x01,0x3b,0x1a,0x0e,0x32,0x71,0x1a,0x0c,0x72,0x71,0xf3,0x71,0x1a,0x0a, -0x02,0x23,0x33,0x72,0x00,0x9b,0xb2,0x71,0x1a,0x0c,0x72,0x72,0xf3,0x72,0x1a,0x0a, -0x43,0x4b,0xb2,0x72,0x1f,0x80,0x05,0x46,0x68,0xe1,0x40,0x4b,0x48,0x4f,0x1b,0x68, -0x48,0x4e,0x08,0x46,0x5b,0x68,0x39,0x46,0x32,0x46,0x98,0x47,0x00,0x28,0x40,0xf0, -0xbf,0x80,0x3a,0x68,0x3b,0x4b,0x01,0x3a,0x11,0x0e,0x19,0x70,0x11,0x0c,0x59,0x70, -0xda,0x70,0x11,0x0a,0x32,0x68,0x99,0x70,0x11,0x0e,0x19,0x71,0x11,0x0c,0x59,0x71, -0x11,0x0a,0xda,0x71,0x99,0x71,0x32,0x4b,0x08,0x22,0x1a,0x80,0xdb,0xe7,0xdf,0xf8, -0xf4,0x80,0x98,0xf8,0x00,0x30,0x00,0x2b,0x35,0xd1,0x2b,0x4d,0x95,0xf9,0x0c,0x30, -0x00,0x2b,0x2e,0xda,0x29,0x4b,0x08,0x46,0x1b,0x68,0x9b,0x68,0x98,0x47,0x00,0x28, -0x40,0xf0,0x96,0x80,0xf1,0x78,0xb3,0x78,0x09,0x04,0x41,0xea,0x03,0x61,0x73,0x79, -0xf2,0x79,0x19,0x43,0x33,0x79,0x2c,0x4f,0x41,0xea,0x03,0x21,0x33,0x7a,0x2b,0x4e, -0x43,0xea,0x02,0x22,0x32,0x60,0x39,0x60,0x92,0xb2,0x20,0x46,0xff,0xf7,0xc6,0xfe, -0x00,0x28,0xc0,0xf2,0x1a,0x81,0x02,0x23,0x88,0xf8,0x00,0x30,0x21,0x4b,0x3a,0x68, -0x1b,0x68,0x5a,0x43,0x3a,0x60,0x32,0x68,0x53,0x43,0xaa,0x68,0x33,0x60,0x9a,0x42, -0x01,0xd0,0x68,0x7b,0x04,0xe1,0x12,0x4b,0x1c,0x4d,0x4f,0xf4,0x80,0x52,0x1a,0x80, -0x2b,0x68,0x0e,0x4a,0xb3,0xf5,0x80,0x5f,0x34,0xbf,0x98,0x46,0x4f,0xf4,0x80,0x58, -0x15,0x4e,0x14,0x4b,0x11,0x68,0x1b,0x68,0x32,0x68,0x0f,0x69,0xb2,0xfb,0xf3,0xf2, -0xb8,0xfb,0xf3,0xf3,0x9b,0xb2,0x20,0x46,0x06,0x49,0xb8,0x47,0x00,0x28,0x23,0xda, -0x20,0x46,0x04,0x21,0x11,0x22,0xaa,0xe0,0x04,0xb0,0x00,0x20,0xec,0x78,0x00,0x20, -0x36,0xb0,0x00,0x20,0x00,0xa0,0x00,0x20,0xcc,0x9f,0x00,0x20,0xfc,0x9f,0x00,0x20, -0xd4,0x9f,0x00,0x20,0x7f,0x68,0x00,0x20,0x77,0x68,0x00,0x20,0x6f,0x68,0x00,0x20, -0xc4,0x9f,0x00,0x20,0xc8,0x9f,0x00,0x20,0xf4,0x9f,0x00,0x20,0xd0,0x9f,0x00,0x20, -0xf8,0x9f,0x00,0x20,0x34,0xb0,0x00,0x20,0x66,0x4b,0x81,0x21,0x18,0x68,0x66,0x4a, -0x43,0x46,0xfe,0xf7,0x9d,0xff,0x33,0x68,0x64,0x4a,0x43,0x44,0x91,0x68,0x33,0x60, -0x2b,0x68,0xc8,0xeb,0x01,0x01,0xc8,0xeb,0x03,0x03,0x2b,0x60,0x91,0x60,0x00,0x2b, -0x40,0xf0,0xb1,0x80,0x5e,0x4a,0x03,0x21,0x11,0x70,0x1d,0x46,0xae,0xe0,0x5c,0x4b, -0x1b,0x78,0x00,0x2b,0x4f,0xd1,0x5b,0x4b,0x93,0xf9,0x0c,0x20,0x00,0x2a,0x01,0xda, -0x58,0x7b,0x9d,0xe0,0x58,0x4d,0x08,0x46,0x2b,0x68,0x9b,0x68,0x98,0x47,0x18,0xb1, -0x20,0x46,0x02,0x21,0x3a,0x22,0x5a,0xe0,0x2b,0x68,0x20,0x46,0xdb,0x68,0x98,0x47, -0x05,0x46,0x02,0x21,0x20,0x46,0x27,0x22,0x00,0x2d,0x50,0xd1,0xf1,0x78,0xb3,0x78, -0x09,0x04,0x41,0xea,0x03,0x61,0x73,0x79,0xf2,0x79,0x19,0x43,0x33,0x79,0x4b,0x4f, -0x41,0xea,0x03,0x21,0x33,0x7a,0x4a,0x4e,0x43,0xea,0x02,0x22,0x32,0x60,0x39,0x60, -0x92,0xb2,0x20,0x46,0xff,0xf7,0x22,0xfe,0x00,0x28,0x76,0xdb,0x45,0x4b,0x3a,0x68, -0x1b,0x68,0x31,0x68,0x5a,0x43,0x59,0x43,0x3a,0x60,0x3e,0x4a,0x31,0x60,0x93,0x68, -0x8b,0x42,0x18,0xbf,0x50,0x7b,0x63,0xd1,0x39,0x4a,0x01,0x21,0x11,0x70,0x35,0x4a, -0xb3,0xf5,0x80,0x5f,0x28,0xbf,0x4f,0xf4,0x80,0x53,0x9b,0xb2,0x10,0x68,0x32,0x4a, -0xfe,0xf7,0x1a,0xff,0x5a,0xe0,0x36,0x4d,0x33,0x4a,0x2b,0x68,0x33,0x4e,0xb3,0xf5, -0x80,0x5f,0x34,0xbf,0x98,0x46,0x4f,0xf4,0x80,0x58,0x32,0x4b,0x11,0x68,0x1b,0x68, -0x32,0x68,0x4f,0x69,0xb2,0xfb,0xf3,0xf2,0xb8,0xfb,0xf3,0xf3,0x9b,0xb2,0x20,0x46, -0x25,0x49,0xb8,0x47,0x00,0x28,0x05,0xda,0x20,0x46,0x04,0x21,0x03,0x22,0xff,0xf7, -0xcf,0xfd,0x3a,0xe0,0x33,0x68,0x21,0x4a,0x43,0x44,0x91,0x68,0x33,0x60,0x2b,0x68, -0xc8,0xeb,0x01,0x01,0xc8,0xeb,0x03,0x03,0x2b,0x60,0x91,0x60,0x2b,0xb9,0xd9,0xf8, -0x00,0x00,0x00,0x21,0x00,0xf0,0x9e,0xf8,0x25,0xe0,0xb3,0xf5,0x80,0x5f,0x28,0xbf, -0x4f,0xf4,0x80,0x53,0x9b,0xb2,0xd9,0xf8,0x00,0x00,0x01,0x21,0x12,0x4a,0xfe,0xf7, -0xdb,0xfe,0x18,0xe0,0x55,0x78,0x15,0xf0,0x02,0x05,0x03,0xd0,0x08,0x46,0x24,0x22, -0x05,0x21,0xd4,0xe7,0x12,0x4b,0x08,0x46,0x1a,0x88,0x10,0x4b,0x19,0x68,0xff,0xf7, -0xb5,0xfd,0x00,0x28,0xa4,0xbf,0x10,0x4b,0x1d,0x80,0x07,0xda,0x05,0xe0,0x20,0x46, -0x05,0x21,0x20,0x22,0xc3,0xe7,0x00,0x25,0x00,0xe0,0xff,0x25,0x68,0xb2,0xbd,0xe8, -0xfe,0x83,0x00,0xbf,0xf8,0x9f,0x00,0x20,0x00,0xa0,0x00,0x20,0x24,0xb0,0x00,0x20, -0x34,0xb0,0x00,0x20,0x04,0xb0,0x00,0x20,0xec,0x78,0x00,0x20,0xf4,0x9f,0x00,0x20, -0xd0,0x9f,0x00,0x20,0xc8,0x9f,0x00,0x20,0x36,0xb0,0x00,0x20,0x70,0xb5,0x0e,0x4b, -0x04,0x46,0x1a,0x7b,0x0d,0x4d,0x32,0xb9,0x9b,0x68,0x23,0xb1,0x2b,0x78,0x13,0xb9, -0x01,0x21,0xfe,0xf7,0xd1,0xfe,0x81,0x21,0x20,0x46,0xfe,0xf7,0xcd,0xfe,0x2b,0x78, -0x02,0x2b,0x07,0xd1,0x04,0x4a,0x20,0x46,0x01,0x21,0x1f,0x23,0xbd,0xe8,0x70,0x40, -0xfe,0xf7,0x8a,0xbe,0x70,0xbd,0x00,0xbf,0x04,0xb0,0x00,0x20,0x00,0xb0,0x00,0x20, -0x0d,0x4b,0x10,0xb5,0x04,0x46,0x00,0x20,0x18,0x70,0x0c,0x4b,0x18,0x70,0x0c,0x4b, -0x1b,0x68,0x1b,0x68,0x98,0x47,0x01,0x21,0x20,0x46,0xfe,0xf7,0xe9,0xfe,0x81,0x21, -0x20,0x46,0xfe,0xf7,0xe5,0xfe,0x07,0x4a,0x20,0x46,0x01,0x21,0x1f,0x23,0xbd,0xe8, -0x10,0x40,0xfe,0xf7,0x69,0xbe,0x00,0xbf,0x34,0xb0,0x00,0x20,0x00,0xb0,0x00,0x20, -0xec,0x78,0x00,0x20,0x04,0xb0,0x00,0x20,0x04,0x4b,0x00,0x22,0x1a,0x70,0x04,0x4b, -0x01,0x21,0x04,0x4a,0x19,0x70,0x1f,0x23,0xfe,0xf7,0x56,0xbe,0x34,0xb0,0x00,0x20, -0x00,0xb0,0x00,0x20,0x04,0xb0,0x00,0x20,0x01,0x4b,0x00,0x22,0x1a,0x70,0x70,0x47, -0x34,0xb0,0x00,0x20,0x0a,0x4a,0x0b,0x4b,0x10,0xb5,0x13,0x60,0x0a,0x4b,0x11,0x73, -0x00,0x21,0x19,0x70,0x81,0x21,0x0d,0x23,0x04,0x46,0xfe,0xf7,0x59,0xfe,0x07,0x4a, -0x20,0x46,0x01,0x21,0x1f,0x23,0xbd,0xe8,0x10,0x40,0xfe,0xf7,0x35,0xbe,0x00,0xbf, -0x24,0xb0,0x00,0x20,0x55,0x53,0x42,0x53,0x34,0xb0,0x00,0x20,0x04,0xb0,0x00,0x20, -0x2d,0xe9,0xf0,0x41,0xdf,0xf8,0xd4,0x80,0x04,0x46,0x98,0xf8,0x00,0x70,0x17,0xb1, -0x01,0x2f,0x54,0xd1,0x47,0xe0,0x2b,0x4d,0x2b,0x4e,0x6b,0x68,0x01,0x21,0x73,0x60, -0xab,0x68,0xb3,0x60,0xff,0xf7,0xdc,0xfa,0x1f,0x28,0x2a,0x46,0x0a,0xd1,0x29,0x68, -0x26,0x4b,0x99,0x42,0x06,0xd1,0x69,0x7b,0x01,0x29,0x03,0xd8,0xab,0x7b,0x0b,0xb1, -0x10,0x2b,0x08,0xd9,0x50,0x7b,0x05,0x21,0x20,0x22,0xff,0xf7,0xd9,0xfc,0x20,0x4b, -0x02,0x22,0x1a,0x70,0x06,0xe0,0x20,0x46,0x05,0xf1,0x0f,0x02,0xff,0xf7,0x08,0xfd, -0x00,0x28,0x03,0xda,0x20,0x46,0xbd,0xe8,0xf0,0x41,0x4f,0xe7,0x98,0xf8,0x00,0x30, -0x01,0x3b,0xdb,0xb2,0x02,0x2b,0x22,0xd9,0x16,0x4b,0x20,0x46,0x19,0x88,0xd9,0xb1, -0xab,0x68,0xb2,0x68,0x99,0x42,0x38,0xbf,0x0b,0x46,0x9b,0xb2,0xd2,0x1a,0xb2,0x60, -0x04,0x22,0x88,0xf8,0x00,0x20,0x10,0x4a,0x20,0x46,0x81,0x21,0x37,0x73,0xbd,0xe8, -0xf0,0x41,0xfe,0xf7,0xf5,0xbd,0x07,0x4a,0x51,0x7b,0x0f,0x32,0xff,0xf7,0xe0,0xfc, -0x00,0x28,0x04,0xda,0x20,0x46,0x39,0x46,0xbd,0xe8,0xf0,0x41,0x82,0xe7,0xbd,0xe8, -0xf0,0x81,0x00,0xbf,0x04,0xb0,0x00,0x20,0x24,0xb0,0x00,0x20,0x55,0x53,0x42,0x43, -0x00,0xb0,0x00,0x20,0x36,0xb0,0x00,0x20,0x00,0xa0,0x00,0x20,0x34,0xb0,0x00,0x20, -0x10,0xb5,0x0c,0x4b,0x04,0x46,0x1b,0x78,0x02,0x2b,0x03,0xd0,0x10,0xd3,0x04,0x2b, -0x0e,0xd8,0x09,0xe0,0x08,0x4a,0x51,0x7b,0x0f,0x32,0xff,0xf7,0xb9,0xfc,0x00,0x28, -0x06,0xda,0x20,0x46,0x01,0x21,0x00,0xe0,0x00,0x21,0xbd,0xe8,0x10,0x40,0x59,0xe7, -0x10,0xbd,0x00,0xbf,0x34,0xb0,0x00,0x20,0x04,0xb0,0x00,0x20,0x10,0xb5,0x09,0x4c, -0x23,0x78,0x02,0x2b,0x05,0xd1,0x81,0x21,0xfe,0xf7,0xce,0xfd,0x00,0x23,0x23,0x70, -0x10,0xbd,0x0a,0x06,0x05,0xd5,0x01,0x2b,0x03,0xd0,0x01,0x21,0xbd,0xe8,0x10,0x40, -0x40,0xe7,0x10,0xbd,0x00,0xb0,0x00,0x20,0x20,0x23,0x0b,0x80,0x00,0x48,0x70,0x47, -0x9c,0x77,0x00,0x20,0x08,0xb5,0xff,0xf7,0x53,0xff,0x00,0x20,0x08,0xbd,0x08,0xb5, -0xff,0xf7,0xbe,0xff,0x00,0x20,0x08,0xbd,0xf8,0xb5,0x0b,0x78,0x05,0x46,0x13,0xf0, -0x60,0x06,0x0c,0x46,0x28,0xd0,0x20,0x2e,0x49,0xd1,0x4a,0x78,0xfe,0x2a,0x02,0xd0, -0xff,0x2a,0x1b,0xd1,0x11,0xe0,0x4e,0x88,0xc6,0xb9,0xcf,0x88,0x01,0x2f,0x15,0xd1, -0x1a,0x06,0x13,0xd5,0x1f,0x4b,0x1b,0x68,0x9b,0x69,0x98,0x47,0x1e,0x49,0xc0,0xb2, -0x08,0x70,0x58,0xb1,0x28,0x46,0x3a,0x46,0x18,0xe0,0x4a,0x88,0x32,0xb9,0xce,0x88, -0x26,0xb9,0x1b,0x06,0x02,0xd4,0xff,0xf7,0xef,0xfe,0x29,0xe0,0x28,0x46,0x21,0x46, -0xff,0xf7,0x36,0xfa,0x02,0x26,0x23,0xe0,0x4b,0x78,0x0a,0x2b,0x04,0xd0,0x0b,0x2b, -0x07,0xd0,0x01,0x2b,0x1c,0xd1,0x08,0xe0,0x10,0x49,0x01,0x22,0xff,0xf7,0xb0,0xf9, -0x16,0xe0,0x4a,0x88,0x0c,0x4b,0x5a,0x70,0x12,0xe0,0x09,0x79,0xfe,0xf7,0xa8,0xfd, -0x21,0x79,0x28,0x46,0xfe,0xf7,0x17,0xfd,0xa1,0x88,0x28,0x46,0xc9,0xb2,0x40,0x22, -0x02,0x23,0xfe,0xf7,0xef,0xfc,0x21,0x79,0x28,0x46,0xff,0xf7,0x87,0xff,0x00,0x26, -0x30,0x46,0xf8,0xbd,0xec,0x78,0x00,0x20,0x24,0x79,0x00,0x20,0x25,0x79,0x00,0x20, -0x10,0xb5,0x81,0x21,0x04,0x46,0xfe,0xf7,0xfe,0xfc,0x01,0x21,0x20,0x46,0xfe,0xf7, -0xfa,0xfc,0x20,0x46,0xff,0xf7,0xc0,0xfe,0x00,0x20,0x10,0xbd,0x10,0xb5,0x04,0x46, -0xff,0xf7,0xee,0xff,0x81,0x21,0x40,0x22,0x02,0x23,0x20,0x46,0xfe,0xf7,0xca,0xfc, -0x01,0x21,0x40,0x22,0x02,0x23,0x20,0x46,0xfe,0xf7,0xc4,0xfc,0x20,0x46,0xff,0xf7, -0x77,0xfe,0x00,0x20,0x10,0xbd,0x00,0xbf,0x12,0x23,0x0b,0x80,0x00,0x48,0x70,0x47, -0xe8,0x77,0x00,0x20,0x04,0x23,0x0b,0x80,0x00,0x48,0x70,0x47,0xfa,0x77,0x00,0x20, -0x10,0xb5,0x04,0x4c,0x0a,0x46,0x04,0x48,0x21,0x46,0xff,0xf7,0x9b,0xfb,0x20,0x46, -0x10,0xbd,0x00,0xbf,0x84,0x9f,0x00,0x20,0x58,0x76,0x00,0x20,0x10,0xb5,0x04,0x4c, -0x0a,0x46,0x04,0x48,0x21,0x46,0xff,0xf7,0x8d,0xfb,0x20,0x46,0x10,0xbd,0x00,0xbf, -0x84,0x9f,0x00,0x20,0x66,0x76,0x00,0x20,0x10,0xb5,0x04,0x4c,0x0a,0x46,0x04,0x48, -0x21,0x46,0xff,0xf7,0x7f,0xfb,0x20,0x46,0x10,0xbd,0x00,0xbf,0x84,0x9f,0x00,0x20, -0x71,0x76,0x00,0x20,0x10,0xb5,0x04,0x4c,0x0a,0x46,0x04,0x48,0x21,0x46,0xff,0xf7, -0x71,0xfb,0x20,0x46,0x10,0xbd,0x00,0xbf,0x84,0x9f,0x00,0x20,0x7e,0x76,0x00,0x20, -0x10,0xb5,0x04,0x4c,0x0a,0x46,0x04,0x48,0x21,0x46,0xff,0xf7,0x63,0xfb,0x20,0x46, -0x10,0xbd,0x00,0xbf,0x84,0x9f,0x00,0x20,0x84,0x76,0x00,0x20,0x73,0xb5,0x01,0x20, -0x1c,0x4c,0x01,0x46,0xfd,0xf7,0x9a,0xfb,0x4f,0xf4,0xc0,0x53,0x00,0x25,0x03,0x26, -0x00,0x93,0x20,0x46,0x02,0x23,0x69,0x46,0x8d,0xf8,0x04,0x30,0x8d,0xf8,0x05,0x60, -0x8d,0xf8,0x06,0x50,0x8d,0xf8,0x07,0x50,0xfd,0xf7,0xf6,0xfc,0x20,0x46,0x0b,0x21, -0x0a,0x22,0xfd,0xf7,0x72,0xfd,0x0a,0x22,0x20,0x46,0x0c,0x21,0xfd,0xf7,0x6d,0xfd, -0x4f,0xf4,0x00,0x73,0x8d,0xf8,0x05,0x60,0x20,0x46,0x01,0x26,0x69,0x46,0x00,0x93, -0x8d,0xf8,0x04,0x50,0x8d,0xf8,0x06,0x60,0x8d,0xf8,0x07,0x50,0xfd,0xf7,0xdc,0xfc, -0x31,0x46,0x4f,0xf4,0x80,0x40,0xfd,0xf7,0x99,0xfb,0x80,0x20,0x31,0x46,0xfd,0xf7, -0x71,0xfb,0x7c,0xbd,0x00,0x00,0x02,0x40,0x07,0xb5,0x4f,0xf4,0xc0,0x60,0xfd,0xf7, -0xe5,0xfe,0x43,0x23,0x8d,0xf8,0x04,0x30,0x03,0x22,0x01,0x23,0x01,0xa8,0x8d,0xf8, -0x05,0x30,0x8d,0xf8,0x06,0x20,0x8d,0xf8,0x07,0x30,0xfd,0xf7,0xe1,0xfe,0x0e,0xbd, -0x05,0x4b,0x1a,0x68,0x05,0x4b,0xb2,0xfb,0xf3,0xf3,0x58,0x43,0x00,0x23,0x01,0x33, -0x83,0x42,0xfc,0xd9,0x70,0x47,0x00,0xbf,0x48,0x77,0x00,0x20,0x40,0x42,0x0f,0x00, -0x4f,0xf4,0x7a,0x73,0x58,0x43,0xeb,0xe7,0xc9,0x08,0x2d,0xe9,0xf0,0x47,0x04,0x46, -0xd4,0x20,0x00,0xfb,0x01,0x41,0x55,0x48,0xa9,0x2c,0x01,0x44,0x88,0xbf,0xd4,0x39, -0x15,0x2a,0x09,0xd8,0x06,0x20,0x42,0x43,0x5b,0x07,0xd0,0xb2,0x40,0xf1,0x9b,0x80, -0x40,0x00,0xc0,0xb2,0xbd,0xe8,0xf0,0x87,0xa0,0x1d,0xbf,0x2a,0xc0,0xb2,0x4c,0x4d, -0x03,0xd8,0x05,0x26,0x06,0xfb,0x02,0x55,0xa0,0x3d,0xde,0x07,0x07,0xd4,0x13,0xf0, -0x02,0x06,0x05,0xd0,0x47,0x4e,0x36,0x78,0xc6,0xf3,0x80,0x16,0x00,0xe0,0x01,0x26, -0x5f,0x07,0x56,0xd5,0x2e,0x2a,0x44,0x4b,0x0e,0xd0,0x0c,0x34,0xbf,0x2a,0xe0,0xb2, -0x0e,0xd8,0x01,0x24,0x42,0x2a,0x08,0xd0,0x02,0x24,0x53,0x2a,0x05,0xd0,0x55,0x2a, -0x0c,0xbf,0x03,0x24,0x00,0x24,0x00,0xe0,0x00,0x24,0x14,0x25,0x05,0xfb,0x04,0x33, -0xdf,0xf8,0xe8,0x90,0x05,0x25,0xbf,0x2a,0x0e,0xd8,0x3d,0xb1,0x93,0xf8,0x00,0x80, -0x9f,0x7a,0x93,0xf8,0x01,0xc0,0xdc,0x7a,0x01,0x33,0x03,0xe0,0xac,0x46,0x2f,0x46, -0xa8,0x46,0x2c,0x46,0x01,0x33,0x0c,0xe0,0x3d,0xb1,0x93,0xf8,0x00,0x80,0x5f,0x78, -0x93,0xf8,0x02,0xc0,0xdc,0x78,0x04,0x33,0x03,0xe0,0x2c,0x46,0xac,0x46,0x2f,0x46, -0xa8,0x46,0x5e,0xb1,0x6f,0xea,0x08,0x08,0x6f,0xea,0x0c,0x0c,0xff,0x43,0xe4,0x43, -0x5f,0xfa,0x88,0xf8,0x5f,0xfa,0x8c,0xfc,0xff,0xb2,0xe4,0xb2,0x01,0xf1,0xd5,0x0a, -0xca,0x45,0x3f,0xbf,0x81,0xf8,0x00,0x80,0x81,0xf8,0x01,0xc0,0x81,0xf8,0xd4,0x70, -0x81,0xf8,0xd5,0x40,0x38,0xbf,0x02,0x31,0x15,0xf1,0xff,0x35,0xc3,0xd2,0xbd,0xe8, -0xf0,0x87,0x13,0xf0,0x08,0x03,0x08,0xd0,0x00,0x2e,0x14,0xbf,0xff,0x23,0x00,0x23, -0x05,0x34,0x01,0xf8,0x01,0x3b,0xe0,0xb2,0x01,0x23,0x14,0x4f,0x05,0x22,0x04,0x2a, -0x14,0xbf,0x4f,0xf0,0x00,0x0c,0x03,0xf0,0x01,0x0c,0x15,0xf8,0x01,0x4b,0xbc,0xf1, -0x00,0x0f,0x06,0xd1,0xb9,0x42,0x04,0xd2,0x0e,0xb1,0xe4,0x43,0xe4,0xb2,0x01,0xf8, -0x01,0x4b,0x01,0x3a,0xeb,0xd1,0x09,0x4b,0x99,0x42,0x04,0xd2,0x00,0x2e,0x14,0xbf, -0xff,0x26,0x00,0x26,0x0e,0x70,0xbd,0xe8,0xf0,0x87,0x00,0xbf,0x50,0x79,0x00,0x20, -0x86,0x68,0x00,0x20,0x46,0x82,0x00,0x20,0x70,0x6a,0x00,0x20,0xc6,0x7f,0x00,0x20, -0x00,0x23,0x41,0xe7,0xf8,0xb5,0x0f,0x46,0x1c,0x46,0x9d,0xf8,0x18,0x60,0x15,0x46, -0x08,0xe0,0x15,0xf8,0x01,0x2b,0x3a,0xb1,0x39,0x46,0x33,0x46,0xff,0xf7,0x34,0xff, -0x01,0x3c,0xe4,0xb2,0x00,0x2c,0xf4,0xd1,0xf8,0xbd,0x13,0xb5,0x00,0x24,0x00,0x94, -0xff,0xf7,0xe8,0xff,0x1c,0xbd,0x70,0xb5,0x0e,0x46,0x14,0x46,0x1d,0x46,0x14,0xf8, -0x01,0x2b,0x22,0xb1,0x31,0x46,0x2b,0x46,0xff,0xf7,0x1e,0xff,0xf7,0xe7,0x70,0xbd, -0x03,0x46,0x00,0x20,0x0a,0x46,0x19,0x46,0x03,0x46,0xec,0xe7,0x00,0x23,0xea,0xe7, -0xf8,0xb5,0x00,0xf1,0x14,0x04,0x06,0x46,0x0f,0x46,0x15,0x46,0xe4,0xb2,0x05,0xf0, -0x0f,0x02,0x05,0x3c,0x09,0x2a,0xe4,0xb2,0x02,0xd9,0x37,0x32,0x08,0x23,0x01,0xe0, -0x30,0x32,0x00,0x23,0x20,0x46,0x39,0x46,0xff,0xf7,0xfe,0xfe,0x2d,0x09,0xb4,0x42, -0xed,0xd1,0xf8,0xbd,0x07,0x4a,0x02,0xf5,0xd4,0x63,0x98,0x42,0x09,0xd2,0x92,0xf8, -0xa0,0x26,0x03,0x78,0x1a,0xb1,0x01,0x2a,0x43,0xea,0x01,0x03,0x00,0xd0,0x4b,0x40, -0x03,0x70,0x70,0x47,0x26,0x79,0x00,0x20,0xcb,0x08,0xd4,0x22,0x02,0xfb,0x03,0x00, -0x04,0x4b,0x01,0xf0,0x07,0x01,0xc0,0x18,0x01,0x23,0x13,0xfa,0x01,0xf1,0xc9,0xb2, -0xe0,0xe7,0x00,0xbf,0x50,0x79,0x00,0x20,0x00,0x2a,0x2d,0xe9,0xf0,0x41,0x14,0x46, -0x04,0xda,0xd4,0xb2,0x20,0x18,0x64,0x42,0xc0,0xb2,0x64,0xb2,0xca,0x08,0x4f,0xf0, -0x01,0x08,0x01,0xf0,0x07,0x01,0x08,0xfa,0x01,0xf8,0xd4,0x25,0x05,0xfb,0x02,0x05, -0x0e,0x4f,0x2a,0x35,0x7d,0x19,0x5f,0xfa,0x88,0xf8,0x07,0xf5,0xd4,0x67,0x11,0xe0, -0xbd,0x42,0x11,0xd2,0x13,0xf0,0x01,0x0f,0x4f,0xea,0x63,0x06,0x08,0xbf,0xf3,0xb2, -0x05,0xd0,0x28,0x46,0x41,0x46,0xff,0xf7,0xb5,0xff,0x46,0xf0,0x80,0x03,0x01,0x3c, -0x64,0xb2,0x01,0x35,0x00,0x2c,0xeb,0xd1,0xbd,0xe8,0xf0,0x81,0x26,0x79,0x00,0x20, -0x6b,0xb1,0x0c,0x4b,0x1b,0x78,0x5b,0x06,0x12,0xd4,0x08,0xe0,0x0b,0x78,0x01,0x30, -0xdb,0x43,0x01,0xf8,0x01,0x3b,0xc0,0xb2,0x90,0x42,0xf7,0xd3,0x70,0x47,0xd4,0x23, -0xc9,0x08,0x03,0xfb,0x01,0x01,0x04,0x4b,0x12,0x18,0xd2,0xb2,0xc9,0x18,0xf3,0xe7, -0x70,0x47,0x00,0xbf,0x46,0x82,0x00,0x20,0x50,0x79,0x00,0x20,0xff,0x23,0xab,0xe7, -0x00,0x2a,0x38,0xb5,0x14,0x46,0x04,0xda,0xd4,0xb2,0x61,0x18,0x64,0x42,0xc9,0xb2, -0x64,0xb2,0xcb,0x08,0xd4,0x25,0x05,0xfb,0x03,0x05,0x15,0x4b,0x11,0xf0,0x07,0x01, -0x1d,0x44,0x18,0xd0,0x01,0x22,0x12,0xfa,0x01,0xf3,0x0c,0x19,0x08,0x3c,0xdb,0xb2, -0x64,0xb2,0x59,0x42,0x00,0x2c,0x04,0xda,0x04,0xf1,0x08,0x01,0x12,0xfa,0x01,0xf1, -0xc9,0x1a,0xc9,0xb2,0x28,0x46,0x03,0xe0,0x08,0x3c,0x64,0xb2,0x28,0x46,0xff,0x21, -0xff,0xf7,0x60,0xff,0xd4,0x35,0x07,0x2c,0xf6,0xdc,0x00,0x2c,0x07,0xdd,0x01,0x21, -0xa1,0x40,0x01,0x39,0xc9,0xb2,0x28,0x46,0xbd,0xe8,0x38,0x40,0x52,0xe7,0x38,0xbd, -0x50,0x79,0x00,0x20,0x2d,0xe9,0xf0,0x4f,0x13,0xf0,0x20,0x07,0x85,0xb0,0x04,0x46, -0x8b,0x46,0x01,0x92,0x1e,0x46,0x9d,0xf9,0x38,0xa0,0x04,0xd0,0x13,0xf0,0x10,0x0f, -0x0c,0xbf,0x01,0x27,0x02,0x27,0x01,0x9d,0x00,0x23,0x00,0x2d,0xb8,0xbf,0x6d,0x42, -0xba,0xf1,0x00,0x0f,0xbe,0xbf,0xca,0xf1,0x00,0x0a,0x4f,0xfa,0x8a,0xfa,0x01,0x23, -0x71,0x06,0x02,0x93,0x25,0xd5,0x01,0x9b,0x00,0x2b,0x01,0xda,0x05,0x34,0xe4,0xb2, -0x42,0xf2,0x0f,0x73,0x9d,0x42,0x02,0xdd,0x05,0x34,0xe4,0xb2,0x02,0xe0,0xb5,0xf5, -0x7a,0x7f,0x02,0xdb,0x05,0x34,0xe4,0xb2,0x01,0xe0,0x63,0x2d,0x02,0xdd,0x05,0x34, -0xe4,0xb2,0x01,0xe0,0x09,0x2d,0x01,0xdd,0x05,0x34,0xe4,0xb2,0x5f,0xb1,0x02,0x2f, -0x03,0xd1,0x63,0x2d,0x07,0xdc,0x05,0x34,0xe4,0xb2,0x09,0x2d,0x03,0xdc,0x05,0x34, -0x00,0xe0,0x05,0x3c,0xe4,0xb2,0x31,0x4b,0xa2,0x1d,0x02,0x2f,0x83,0xf8,0xa1,0x26, -0x01,0xd1,0x10,0x3e,0xf6,0xb2,0x0b,0xf1,0x06,0x03,0xdb,0xb2,0x4f,0xf0,0x01,0x08, -0x03,0x93,0x3e,0xe0,0x0a,0x23,0x95,0xfb,0xf3,0xf2,0x03,0xfb,0x12,0x52,0x30,0x32, -0xd2,0xb2,0x20,0x46,0x59,0x46,0x33,0x46,0xff,0xf7,0xe6,0xfd,0x47,0x45,0x18,0xbf, -0xa1,0x46,0x14,0xd1,0xa4,0xf1,0x02,0x09,0x16,0xf0,0x01,0x0f,0x04,0xf1,0xff,0x34, -0x5f,0xfa,0x89,0xf9,0xe0,0xb2,0x04,0xd0,0x59,0x46,0x07,0x22,0xff,0xf7,0x50,0xff, -0x02,0xe0,0x03,0x99,0xff,0xf7,0xe8,0xfe,0x09,0x2d,0xc8,0xbf,0x00,0x27,0x0a,0x23, -0x95,0xfb,0xf3,0xf5,0x85,0xb9,0x4f,0xb1,0x02,0x2f,0x18,0xbf,0x2f,0x46,0x0b,0xd1, -0xb8,0xf1,0x01,0x0f,0x0c,0xbf,0x02,0x27,0x00,0x27,0x05,0xe0,0xf2,0x06,0x0b,0xd5, -0x02,0x9b,0x0b,0xb9,0x10,0x3e,0xf6,0xb2,0xa9,0xf1,0x05,0x04,0xe4,0xb2,0x08,0xf1, -0x01,0x08,0xd0,0x45,0xbe,0xdd,0xa1,0x46,0x01,0x9b,0x00,0x2b,0x0a,0xda,0xa9,0xf1, -0x05,0x09,0x5f,0xfa,0x89,0xf0,0x59,0x46,0x2d,0x22,0x33,0x46,0x05,0xb0,0xbd,0xe8, -0xf0,0x4f,0xa1,0xe5,0x05,0xb0,0xbd,0xe8,0xf0,0x8f,0x00,0xbf,0x26,0x79,0x00,0x20, -0x13,0xb5,0x05,0x24,0x00,0x94,0xff,0xf7,0x4d,0xff,0x1c,0xbd,0x00,0x23,0xf7,0xe7, -0x02,0x48,0x00,0x21,0x4f,0xf4,0xd4,0x62,0x02,0xf0,0x8a,0xbf,0x26,0x79,0x00,0x20, -0xf8,0xb5,0x03,0x69,0x0d,0x46,0x01,0xf1,0x09,0x01,0x00,0x2b,0x4f,0xd0,0x43,0x69, -0x0c,0x46,0x1f,0x7b,0x00,0x26,0x07,0xf0,0x08,0x0c,0x9a,0x5d,0x21,0x46,0x20,0x2a, -0x12,0xd0,0x05,0x2a,0x08,0xbf,0xe5,0x22,0xbc,0xf1,0x00,0x0f,0x06,0xd0,0xa2,0xf1, -0x41,0x01,0xc9,0xb2,0x19,0x29,0x01,0xd8,0x20,0x32,0xd2,0xb2,0x01,0x36,0x04,0xf8, -0x01,0x2b,0x08,0x2e,0x21,0x46,0xe8,0xd1,0x1a,0x7a,0x20,0x2a,0x18,0xd0,0x22,0x46, -0x2e,0x21,0x02,0xf8,0x01,0x1b,0x08,0x26,0x07,0xf0,0x10,0x07,0x9c,0x5d,0x11,0x46, -0x20,0x2c,0x0d,0xd0,0x37,0xb1,0xa4,0xf1,0x41,0x01,0xc9,0xb2,0x19,0x29,0x01,0xd8, -0x20,0x34,0xe4,0xb2,0x01,0x36,0x02,0xf8,0x01,0x4b,0x0b,0x2e,0x11,0x46,0xed,0xd1, -0xda,0x7a,0x2a,0x72,0x9a,0x7f,0xdc,0x7f,0x12,0x04,0x42,0xea,0x04,0x62,0x1c,0x7f, -0x22,0x43,0x5c,0x7f,0x42,0xea,0x04,0x22,0x2a,0x60,0x5c,0x7e,0x1a,0x7e,0x42,0xea, -0x04,0x22,0xaa,0x80,0xda,0x7d,0x9b,0x7d,0x43,0xea,0x02,0x23,0xeb,0x80,0x00,0x24, -0x0c,0x70,0xae,0x69,0x0e,0xb3,0xeb,0x69,0xfb,0xb1,0x03,0x69,0xb3,0xb1,0x02,0x8c, -0x4f,0xf6,0xff,0x73,0x9a,0x42,0x18,0xbf,0xc7,0x69,0x0a,0xd1,0x13,0xe0,0x00,0x21, -0x02,0xf0,0xfa,0xfa,0x60,0xb1,0xeb,0x69,0x01,0x3b,0x9c,0x42,0x0a,0xd2,0x30,0x55, -0x01,0x34,0x37,0xf8,0x02,0x0b,0x00,0x28,0xf1,0xd1,0x04,0xe0,0x1c,0x46,0x02,0xe0, -0x04,0x46,0x00,0xe0,0x00,0x24,0x00,0x23,0x33,0x55,0xf8,0xbd,0x08,0xb5,0x60,0xb1, -0x03,0x78,0x53,0xb1,0xc3,0x88,0x8b,0x42,0x09,0xd1,0x40,0x78,0x01,0xf0,0xfe,0xf9, -0x10,0xf0,0x01,0x00,0x18,0xbf,0x03,0x20,0x08,0xbd,0x09,0x20,0x08,0xbd,0x09,0x20, -0x08,0xbd,0x38,0xb5,0x43,0x6a,0x05,0x46,0x8b,0x42,0x0c,0x46,0x0c,0xd0,0x69,0xb1, -0x40,0x78,0x05,0xf1,0x28,0x01,0x22,0x46,0x01,0x23,0x01,0xf0,0x0f,0xfa,0x08,0xb9, -0x6c,0x62,0x38,0xbd,0x01,0x20,0x38,0xbd,0x00,0x20,0x38,0xbd,0x08,0x46,0x38,0xbd, -0x10,0xb5,0x04,0x46,0x0a,0x46,0x40,0x78,0x04,0xf1,0x28,0x01,0x01,0x23,0x01,0xf0, -0xfd,0xf9,0x80,0xbb,0x94,0xf8,0x26,0x32,0x94,0xf8,0x27,0x22,0x43,0xea,0x02,0x22, -0x17,0x4b,0x12,0xb2,0x9a,0x42,0x28,0xd1,0x94,0xf8,0x60,0x20,0x94,0xf8,0x61,0x30, -0x12,0x04,0x42,0xea,0x03,0x62,0x94,0xf8,0x5e,0x30,0x1a,0x43,0x94,0xf8,0x5f,0x30, -0x42,0xea,0x03,0x22,0x0f,0x4b,0x22,0xf0,0x7f,0x42,0x9a,0x42,0x16,0xd0,0x94,0xf8, -0x7c,0x00,0x94,0xf8,0x7d,0x20,0x00,0x04,0x40,0xea,0x02,0x60,0x94,0xf8,0x7a,0x20, -0x10,0x43,0x94,0xf8,0x7b,0x20,0x40,0xea,0x02,0x20,0x20,0xf0,0x7f,0x40,0xc0,0x1a, -0x18,0xbf,0x01,0x20,0x10,0xbd,0x03,0x20,0x10,0xbd,0x02,0x20,0x10,0xbd,0x00,0xbf, -0x55,0xaa,0xff,0xff,0x46,0x41,0x54,0x00,0x2d,0xe9,0xf0,0x41,0x03,0x68,0x1d,0x78, -0x30,0x3d,0x09,0x2d,0x05,0xd8,0x5a,0x78,0x3a,0x2a,0x02,0xd1,0x02,0x33,0x03,0x60, -0x01,0xe0,0x7f,0x4b,0x1d,0x78,0x00,0x2d,0x40,0xf0,0xe4,0x80,0x7c,0x4b,0x5c,0x68, -0x0c,0x60,0x00,0x2c,0x00,0xf0,0xe1,0x80,0x23,0x78,0x2b,0xb1,0x60,0x78,0x01,0xf0, -0x7d,0xf9,0xc2,0x07,0x40,0xf1,0xdc,0x80,0x00,0x20,0x20,0x70,0x60,0x70,0x01,0xf0, -0xdb,0xf8,0x10,0xf0,0x01,0x05,0x40,0xf0,0xd6,0x80,0x20,0x46,0x29,0x46,0xff,0xf7, -0x8f,0xff,0x01,0x28,0x16,0xd1,0x94,0xf8,0xea,0x31,0x00,0x2b,0x00,0xf0,0xd1,0x80, -0x94,0xf8,0xf0,0x51,0x94,0xf8,0xf1,0x31,0x2d,0x04,0x45,0xea,0x03,0x65,0x94,0xf8, -0xee,0x31,0x20,0x46,0x1d,0x43,0x94,0xf8,0xef,0x31,0x45,0xea,0x03,0x25,0x29,0x46, -0xff,0xf7,0x76,0xff,0x03,0x28,0x00,0xf0,0xb9,0x80,0x00,0x28,0x40,0xf0,0xb9,0x80, -0x94,0xf8,0x34,0x20,0x94,0xf8,0x33,0x30,0x43,0xea,0x02,0x23,0xb3,0xf5,0x00,0x7f, -0x40,0xf0,0xaf,0x80,0x94,0xf8,0x3f,0x60,0x94,0xf8,0x3e,0x30,0x53,0xea,0x06,0x26, -0x0d,0xd1,0x94,0xf8,0x4e,0x60,0x94,0xf8,0x4f,0x30,0x36,0x04,0x46,0xea,0x03,0x66, -0x94,0xf8,0x4c,0x30,0x1e,0x43,0x94,0xf8,0x4d,0x30,0x46,0xea,0x03,0x26,0x94,0xf8, -0x38,0x00,0x66,0x61,0x43,0x1e,0xdb,0xb2,0x01,0x2b,0xe0,0x70,0x00,0xf2,0x91,0x80, -0x94,0xf8,0x35,0x10,0xa1,0x70,0x00,0x29,0x00,0xf0,0x8b,0x80,0x4b,0x1e,0x0b,0x42, -0x40,0xf0,0x87,0x80,0x94,0xf8,0x39,0x30,0x94,0xf8,0x3a,0x20,0x43,0xea,0x02,0x22, -0x13,0x07,0x22,0x81,0x7d,0xd1,0x94,0xf8,0x3c,0x70,0x94,0xf8,0x3b,0x30,0x53,0xea, -0x07,0x23,0x0d,0xd1,0x94,0xf8,0x4a,0x30,0x94,0xf8,0x4b,0x70,0x1b,0x04,0x43,0xea, -0x07,0x63,0x94,0xf8,0x48,0x70,0x3b,0x43,0x94,0xf8,0x49,0x70,0x43,0xea,0x07,0x23, -0x94,0xf8,0x37,0xc0,0x94,0xf8,0x36,0x70,0x57,0xea,0x0c,0x2c,0x61,0xd0,0x00,0xfb, -0x06,0xf8,0x0c,0xeb,0x12,0x17,0x47,0x44,0xbb,0x42,0x5a,0xd3,0xdb,0x1b,0xb3,0xfb, -0xf1,0xf3,0x00,0x2b,0x55,0xd0,0x40,0xf6,0xf5,0x71,0x01,0x20,0x8b,0x42,0x05,0xd9, -0x4f,0xf6,0xf5,0x70,0x83,0x42,0x8c,0xbf,0x03,0x20,0x02,0x20,0x02,0x33,0x7f,0x19, -0x03,0x28,0x65,0x44,0x23,0x61,0x27,0x62,0xa5,0x61,0x12,0xd1,0x00,0x2a,0x40,0xd1, -0x94,0xf8,0x56,0x20,0x94,0xf8,0x57,0x10,0x12,0x04,0x42,0xea,0x01,0x62,0x94,0xf8, -0x54,0x10,0x9b,0x00,0x0a,0x43,0x94,0xf8,0x55,0x10,0x42,0xea,0x01,0x22,0xe2,0x61, -0x0d,0xe0,0x00,0x2a,0x2d,0xd0,0x45,0x44,0x02,0x28,0xe5,0x61,0x01,0xd1,0x5b,0x00, -0x05,0xe0,0x03,0x22,0x5a,0x43,0x03,0xf0,0x01,0x03,0x03,0xeb,0x52,0x03,0x03,0xf5, -0xfe,0x73,0x03,0x33,0xb6,0xeb,0x53,0x2f,0x1e,0xd3,0x11,0x4a,0x20,0x70,0x13,0x89, -0x00,0x20,0x01,0x33,0x9b,0xb2,0x13,0x81,0xe3,0x80,0x60,0x62,0x20,0x71,0xe0,0x60, -0xbd,0xe8,0xf0,0x81,0x0b,0x20,0xbd,0xe8,0xf0,0x81,0x0c,0x20,0xbd,0xe8,0xf0,0x81, -0x28,0x46,0xbd,0xe8,0xf0,0x81,0x03,0x20,0xbd,0xe8,0xf0,0x81,0x01,0x20,0xbd,0xe8, -0xf0,0x81,0x0d,0x20,0xbd,0xe8,0xf0,0x81,0x0d,0x20,0xbd,0xe8,0xf0,0x81,0x00,0xbf, -0xcc,0x7f,0x00,0x20,0x03,0x69,0x02,0x39,0x02,0x3b,0x99,0x42,0x3d,0xbf,0x82,0x78, -0x03,0x6a,0x02,0xfb,0x01,0x30,0x00,0x20,0x70,0x47,0x01,0x29,0xf8,0xb5,0x04,0x46, -0x0d,0x46,0x5b,0xd9,0x03,0x69,0x99,0x42,0x5a,0xd2,0x03,0x78,0x02,0x2b,0x28,0xd0, -0x03,0x2b,0x36,0xd0,0x01,0x2b,0x4e,0xd1,0x01,0xeb,0x51,0x06,0x81,0x69,0x01,0xeb, -0x56,0x21,0xff,0xf7,0x76,0xfe,0x00,0x28,0x45,0xd1,0xa1,0x69,0xf3,0x05,0x01,0x36, -0x04,0xeb,0xd3,0x53,0x01,0xeb,0x56,0x21,0x20,0x46,0x93,0xf8,0x28,0x70,0xff,0xf7, -0x68,0xfe,0x00,0x28,0x37,0xd1,0xf6,0x05,0x04,0xeb,0xd6,0x54,0x94,0xf8,0x28,0x00, -0xe9,0x07,0x47,0xea,0x00,0x20,0x01,0xd5,0x00,0x09,0xf8,0xbd,0x00,0x05,0x00,0x0d, -0xf8,0xbd,0x81,0x69,0x01,0xeb,0x15,0x21,0xff,0xf7,0x53,0xfe,0x18,0xbb,0x2d,0x06, -0x04,0xeb,0xd5,0x54,0x94,0xf8,0x29,0x00,0x94,0xf8,0x28,0x30,0x43,0xea,0x00,0x20, -0xf8,0xbd,0x81,0x69,0x01,0xeb,0xd5,0x11,0xff,0xf7,0x43,0xfe,0x98,0xb9,0x6d,0x06, -0x04,0xeb,0xd5,0x54,0x94,0xf8,0x2a,0x00,0x94,0xf8,0x2b,0x30,0x00,0x04,0x40,0xea, -0x03,0x60,0x94,0xf8,0x28,0x30,0x94,0xf8,0x29,0x70,0x18,0x43,0x40,0xea,0x07,0x20, -0x20,0xf0,0x70,0x40,0xf8,0xbd,0x4f,0xf0,0xff,0x30,0xf8,0xbd,0x01,0x20,0xf8,0xbd, -0x01,0x20,0xf8,0xbd,0x70,0xb5,0x04,0x46,0x0d,0x46,0xe1,0x80,0x81,0x68,0x01,0x29, -0x39,0xd0,0x03,0x68,0x1a,0x69,0x91,0x42,0x35,0xd2,0x79,0xb9,0x1a,0x78,0x03,0x2a, -0x01,0xd1,0xd9,0x69,0x51,0xb9,0x00,0x22,0xe2,0x60,0x1a,0x89,0xaa,0x42,0x82,0xbf, -0xdb,0x69,0x03,0xeb,0x15,0x13,0x23,0x61,0x25,0xd9,0x19,0xe0,0x9e,0x78,0x36,0x01, -0x0d,0xe0,0x20,0x68,0xff,0xf7,0x79,0xff,0x01,0x46,0x01,0x30,0x19,0xd0,0x01,0x29, -0x19,0xd9,0x23,0x68,0x1b,0x69,0x99,0x42,0x17,0xd2,0xad,0x1b,0xad,0xb2,0xb5,0x42, -0xef,0xd2,0xe1,0x60,0x20,0x68,0xff,0xf7,0x5d,0xff,0x00,0xeb,0x15,0x10,0x20,0x61, -0x23,0x68,0x05,0xf0,0x0f,0x05,0x28,0x33,0x03,0xeb,0x45,0x15,0x65,0x61,0x00,0x20, -0x70,0xbd,0x01,0x20,0x70,0xbd,0x02,0x20,0x70,0xbd,0x02,0x20,0x70,0xbd,0x70,0xb5, -0xc5,0x88,0x04,0x46,0x01,0x35,0xad,0xb2,0x00,0x2d,0x2a,0xd0,0x03,0x69,0x00,0x2b, -0x27,0xd0,0x15,0xf0,0x0f,0x06,0x1c,0xd1,0xc1,0x68,0x01,0x33,0x03,0x61,0x00,0x68, -0x19,0xb9,0x03,0x89,0xab,0x42,0x1c,0xd9,0x13,0xe0,0x83,0x78,0x01,0x3b,0x13,0xea, -0x15,0x13,0x0e,0xd1,0xff,0xf7,0x39,0xff,0x01,0x28,0x01,0x46,0x13,0xd9,0x43,0x1c, -0x13,0xd0,0x20,0x68,0x03,0x69,0x99,0x42,0x11,0xd2,0xe1,0x60,0xff,0xf7,0x22,0xff, -0x20,0x61,0x23,0x68,0xe5,0x80,0x28,0x33,0x03,0xeb,0x46,0x16,0x66,0x61,0x00,0x20, -0x70,0xbd,0x04,0x20,0x70,0xbd,0x02,0x20,0x70,0xbd,0x01,0x20,0x70,0xbd,0x04,0x20, -0x70,0xbd,0x2d,0xe9,0xf0,0x47,0xff,0x26,0x05,0x46,0x34,0x46,0x04,0x20,0xdf,0xf8, -0xf8,0x80,0x4f,0xf6,0xff,0x77,0x6a,0xe0,0x28,0x68,0xff,0xf7,0x9a,0xfd,0x00,0x28, -0x69,0xd1,0x6b,0x69,0x1a,0x78,0x00,0x2a,0x6c,0xd0,0xe5,0x2a,0xd9,0x7a,0x59,0xd0, -0x01,0xf0,0x3f,0x01,0xb1,0xf1,0x0f,0x0c,0x18,0xbf,0x4f,0xf0,0x01,0x0c,0x1c,0xea, -0xd1,0x0c,0x4f,0xd1,0x0f,0x29,0x39,0xd1,0x50,0x06,0x05,0xd5,0xe9,0x88,0x5e,0x7b, -0x02,0xf0,0xbf,0x04,0x29,0x84,0x01,0xe0,0xa2,0x42,0x43,0xd1,0x5a,0x7b,0xb2,0x42, -0x40,0xd1,0x1a,0x78,0x0d,0x21,0x02,0xf0,0x3f,0x02,0x01,0x3a,0xd5,0xf8,0x1c,0xe0, -0x4a,0x43,0x4f,0xf0,0x01,0x0c,0x00,0x21,0x11,0xf8,0x08,0x90,0x03,0xeb,0x09,0x00, -0x90,0xf8,0x01,0xa0,0x13,0xf8,0x09,0x00,0x40,0xea,0x0a,0x20,0xbc,0xf1,0x00,0x0f, -0x06,0xd0,0xfe,0x2a,0x26,0xd8,0x2e,0xf8,0x12,0x00,0x84,0x46,0x01,0x32,0x01,0xe0, -0xb8,0x42,0x1f,0xd1,0x01,0x31,0x0d,0x29,0xe6,0xd1,0x1b,0x78,0x59,0x06,0x26,0xd5, -0xfe,0x2a,0x17,0xd8,0x00,0x23,0x2e,0xf8,0x12,0x30,0x20,0xe0,0x6c,0xb9,0x01,0x46, -0x02,0x46,0x5c,0x5c,0x01,0x31,0x04,0xeb,0xc2,0x14,0x04,0xeb,0x52,0x02,0x0b,0x29, -0x02,0xf0,0xff,0x02,0xf5,0xd1,0x96,0x42,0x0f,0xd0,0x4f,0xf0,0xff,0x31,0x29,0x84, -0xbd,0xe8,0xf0,0x87,0xff,0x24,0x28,0x46,0xff,0xf7,0x51,0xff,0x18,0xb9,0x29,0x69, -0x00,0x29,0x91,0xd1,0x08,0xb1,0x00,0x23,0x2b,0x61,0xbd,0xe8,0xf0,0x87,0x01,0x3c, -0xe4,0xb2,0xf0,0xe7,0x04,0x20,0xf6,0xe7,0xc0,0x6a,0x00,0x20,0x2d,0xe9,0xf7,0x4f, -0x0b,0x78,0x04,0x46,0xa3,0xf1,0x2f,0x0c,0xdc,0xf1,0x00,0x02,0x42,0xeb,0x0c,0x02, -0x5c,0x2b,0x14,0xbf,0x13,0x46,0x42,0xf0,0x01,0x03,0x8a,0x46,0x1b,0xb1,0x01,0xf1, -0x01,0x0a,0x00,0x23,0x01,0xe0,0x03,0x68,0xdb,0x68,0xa3,0x60,0x9a,0xf8,0x00,0x30, -0x1f,0x2b,0x06,0xd8,0x20,0x46,0x00,0x21,0xff,0xf7,0xdc,0xfe,0x00,0x23,0x63,0x61, -0xd5,0xe1,0xd4,0xf8,0x1c,0x80,0x00,0x23,0x47,0x46,0x46,0x46,0x1a,0xf8,0x03,0x00, -0x03,0xf1,0x01,0x09,0x1f,0x28,0x8c,0xbf,0x00,0x22,0x01,0x22,0x2f,0x28,0x08,0xbf, -0x42,0xf0,0x01,0x02,0xba,0xb9,0x5c,0x28,0x15,0xd0,0xb9,0xf5,0x80,0x7f,0x00,0xf0, -0xbb,0x81,0x01,0x21,0x01,0xf0,0xb8,0xff,0x00,0x28,0x00,0xf0,0xb5,0x81,0x7f,0x28, -0x00,0xf2,0xb7,0x81,0xa5,0x4b,0x13,0xf8,0x01,0x2b,0x00,0x2a,0x00,0xf0,0xb1,0x81, -0x82,0x42,0xf8,0xd1,0xa8,0xe1,0x1f,0x28,0x94,0xbf,0x04,0x25,0x00,0x25,0x01,0x2b, -0x1e,0x46,0xca,0x44,0x0a,0xd0,0x02,0x2b,0x18,0xbf,0x1e,0x46,0x03,0xd1,0xb8,0xf8, -0x02,0x20,0x2e,0x2a,0x02,0xd0,0x08,0xeb,0x43,0x03,0x21,0xe0,0xb8,0xf8,0x00,0x20, -0x2e,0x2a,0xf8,0xd1,0x00,0x21,0x28,0xf8,0x13,0x10,0x00,0x22,0xa1,0x69,0x9a,0x42, -0x2c,0xbf,0x20,0x20,0x2e,0x20,0x88,0x54,0x01,0x32,0x0b,0x2a,0xf6,0xd1,0xa3,0x69, -0x45,0xf0,0x20,0x05,0xbf,0xe0,0x33,0xf8,0x02,0x2d,0xb2,0xf1,0x20,0x01,0x18,0xbf, -0x01,0x21,0x2e,0x2a,0x0c,0xbf,0x00,0x22,0x01,0xf0,0x01,0x02,0x1a,0xb9,0x01,0x3e, -0x00,0x2e,0xf0,0xd1,0x70,0xe1,0x00,0x22,0xa0,0x69,0x28,0xf8,0x16,0x20,0x08,0xeb, -0x46,0x01,0x00,0x23,0x20,0x22,0xc2,0x54,0x01,0x33,0x0b,0x2b,0xfb,0xd1,0x4f,0xf0, -0x00,0x09,0x01,0xe0,0x09,0xf1,0x01,0x09,0x37,0xf8,0x02,0x2b,0xa2,0xf1,0x20,0x0e, -0xde,0xf1,0x00,0x03,0x43,0xeb,0x0e,0x03,0x2e,0x2a,0x14,0xbf,0x1a,0x46,0x43,0xf0, -0x01,0x02,0x00,0x2a,0xee,0xd1,0xb9,0xf1,0x00,0x0f,0x01,0xd0,0x45,0xf0,0x03,0x05, -0x0b,0x46,0x33,0xf8,0x02,0x2d,0x2e,0x2a,0x00,0xf0,0x4f,0x81,0x01,0x3e,0x00,0xf0, -0x4c,0x81,0xf6,0xe7,0x38,0xf8,0x19,0x00,0x00,0x28,0x5b,0xd0,0x20,0x28,0x09,0xf1, -0x01,0x09,0x09,0xd0,0xb9,0xeb,0x06,0x02,0x18,0xbf,0x01,0x22,0x2e,0x28,0x14,0xbf, -0x00,0x21,0x02,0xf0,0x01,0x01,0x11,0xb1,0x45,0xf0,0x03,0x05,0xea,0xe7,0x9b,0x45, -0x34,0xbf,0x00,0x21,0x01,0x21,0xb1,0x45,0x08,0xbf,0x41,0xf0,0x01,0x01,0x81,0xb1, -0x0b,0x2b,0x02,0xd1,0x45,0xf0,0x03,0x05,0x3c,0xe0,0x1a,0xb1,0xb1,0x45,0x45,0xf0, -0x03,0x05,0x37,0xd8,0xbf,0x00,0xff,0xb2,0xb1,0x46,0x0b,0x23,0x4f,0xf0,0x08,0x0b, -0xd0,0xe7,0x7f,0x28,0x0b,0xd9,0x01,0x93,0x01,0xf0,0x0e,0xff,0x01,0x9b,0x18,0xb1, -0x53,0x49,0x08,0x18,0x10,0xf8,0x73,0x0c,0x45,0xf0,0x02,0x05,0x78,0xb1,0x51,0x4a, -0x12,0xf8,0x01,0x1b,0x11,0xb1,0x81,0x42,0xfa,0xd1,0x08,0xe0,0xa0,0xf1,0x41,0x02, -0x92,0xb2,0x19,0x2a,0x98,0xbf,0x47,0xf0,0x02,0x07,0x0d,0xd9,0x03,0xe0,0x45,0xf0, -0x03,0x05,0x5f,0x20,0x08,0xe0,0xa0,0xf1,0x61,0x02,0x92,0xb2,0x19,0x2a,0x03,0xd8, -0x20,0x38,0x47,0xf0,0x01,0x07,0x80,0xb2,0xa2,0x69,0x02,0xf8,0x0b,0x00,0x0b,0xf1, -0x01,0x0b,0x9f,0xe7,0xa2,0x69,0x11,0x78,0xe5,0x29,0x01,0xd1,0x05,0x21,0x11,0x70, -0x08,0x2b,0x01,0xd1,0xbf,0x00,0xff,0xb2,0x07,0xf0,0x0c,0x03,0x0c,0x2b,0x03,0xd0, -0x07,0xf0,0x03,0x02,0x03,0x2a,0x01,0xd1,0x45,0xf0,0x02,0x05,0xa8,0x07,0x09,0xd4, -0x07,0xf0,0x03,0x07,0x01,0x2f,0x08,0xbf,0x45,0xf0,0x10,0x05,0x04,0x2b,0x08,0xbf, -0x45,0xf0,0x08,0x05,0xa3,0x69,0xdd,0x72,0x20,0x46,0x00,0x21,0xff,0xf7,0xc2,0xfd, -0x00,0x28,0x00,0xf0,0xd4,0x80,0x8f,0xe0,0x20,0x68,0x21,0x69,0xff,0xf7,0xe1,0xfb, -0x00,0x28,0x40,0xf0,0x89,0x80,0x67,0x69,0x97,0xf8,0x00,0x80,0xb8,0xf1,0x00,0x0f, -0x00,0xf0,0x81,0x80,0xb8,0xf1,0xe5,0x0f,0xfb,0x7a,0x74,0xd0,0x03,0xf0,0x3f,0x03, -0xb3,0xf1,0x0f,0x02,0x18,0xbf,0x01,0x22,0x12,0xea,0xd3,0x02,0x6b,0xd1,0x0f,0x2b, -0x51,0xd1,0xd4,0xf8,0x1c,0xb0,0xbb,0xf1,0x00,0x0f,0x65,0xd0,0x18,0xf0,0x40,0x0f, -0x05,0xd0,0xe2,0x88,0x7e,0x7b,0x08,0xf0,0xbf,0x08,0x22,0x84,0x01,0xe0,0xa8,0x45, -0x59,0xd1,0x7b,0x7b,0xb3,0x42,0x56,0xd1,0x3d,0x78,0x0d,0x23,0x05,0xf0,0xbf,0x05, -0x01,0x3d,0x5d,0x43,0x4f,0xf0,0x01,0x09,0x00,0x23,0x0d,0x49,0x5a,0x5c,0xb9,0x18, -0x48,0x78,0xba,0x5c,0x42,0xea,0x00,0x20,0xb9,0xf1,0x00,0x0f,0x14,0xd0,0x01,0x93, -0x01,0xf0,0x90,0xfe,0xfe,0x2d,0x81,0x46,0x3d,0xd8,0x3b,0xf8,0x15,0x00,0x01,0xf0, -0x89,0xfe,0x81,0x45,0x01,0x9b,0x36,0xd1,0x01,0x35,0x09,0xe0,0x9f,0x76,0x00,0x20, -0xc0,0x6a,0x00,0x20,0xa8,0x76,0x00,0x20,0x4f,0xf6,0xff,0x72,0x90,0x42,0x2a,0xd1, -0x01,0x33,0x0d,0x2b,0xd9,0xd1,0x3b,0x78,0xc3,0xf3,0x80,0x13,0xb9,0xf1,0x00,0x0f, -0x0c,0xbf,0x00,0x23,0x03,0xf0,0x01,0x03,0x00,0x2b,0x5b,0xd0,0x3b,0xf8,0x15,0x30, -0x00,0x2b,0x57,0xd0,0x17,0xe0,0x00,0x2d,0x58,0xd1,0x02,0x46,0x03,0x46,0xb9,0x5c, -0x01,0x32,0x01,0xeb,0xc3,0x11,0x01,0xeb,0x53,0x03,0x0b,0x2a,0x03,0xf0,0xff,0x03, -0xf5,0xd1,0x9e,0x42,0x4a,0xd1,0x0f,0xe0,0x0b,0x2b,0x0d,0xd0,0xfd,0x5c,0xd1,0x5c, -0x01,0x33,0x8d,0x42,0xf8,0xd0,0xff,0x25,0x20,0x46,0xff,0xf7,0x78,0xfd,0x00,0x28, -0x3f,0xf4,0x72,0xaf,0x00,0xe0,0x04,0x20,0xa3,0x69,0xdb,0x7a,0x90,0xb1,0x04,0x28, -0x25,0xd1,0x13,0xf0,0x20,0x0f,0x03,0xf0,0x04,0x03,0x06,0xd0,0x00,0x20,0xa0,0x60, -0x60,0x61,0x00,0x2b,0x3f,0xf4,0x45,0xae,0x19,0xe0,0x00,0x2b,0x14,0xbf,0x04,0x20, -0x05,0x20,0x14,0xe0,0x59,0x07,0x12,0xd4,0x63,0x69,0xda,0x7a,0xd2,0x06,0x0d,0xd5, -0x59,0x7d,0x1a,0x7d,0x42,0xea,0x01,0x22,0xd9,0x7e,0x9b,0x7e,0x43,0xea,0x01,0x23, -0x43,0xea,0x02,0x43,0xa3,0x60,0x2c,0xe6,0x06,0x20,0x00,0xe0,0x05,0x20,0xbd,0xe8, -0xfe,0x8f,0x26,0xf8,0x02,0x0b,0x4b,0x46,0x28,0xe6,0x4f,0xf0,0x00,0x0b,0x08,0x23, -0x5f,0x46,0xaf,0xe6,0x08,0xf1,0xff,0x35,0xed,0xb2,0xbd,0xe7,0x4f,0xf0,0xff,0x33, -0xa2,0x69,0x23,0x84,0xd3,0x7a,0x13,0xf0,0x01,0x03,0xaf,0xd0,0xb3,0xe7,0xff,0x26, -0x35,0x46,0x29,0xe7,0x37,0xb5,0x00,0x24,0x0d,0x5d,0x05,0x55,0x01,0x34,0x0b,0x2c, -0xfa,0xd1,0x05,0x2b,0x0d,0xd9,0x00,0xe0,0x0a,0x46,0x11,0x46,0x31,0xf8,0x02,0x4b, -0x52,0x88,0x04,0xeb,0xc3,0x34,0xa4,0xb2,0x04,0xeb,0x53,0x03,0x9b,0xb2,0x00,0x2a, -0xf2,0xd1,0x07,0x22,0x03,0xf0,0x0f,0x04,0x04,0xf1,0x30,0x01,0x39,0x29,0x88,0xbf, -0x04,0xf1,0x37,0x01,0x0d,0xf8,0x02,0x10,0x01,0x3a,0x1b,0x09,0xf2,0xd1,0x02,0xac, -0xa1,0x18,0x7e,0x24,0x01,0xf8,0x08,0x4c,0x93,0x42,0x04,0xd0,0xc1,0x5c,0x20,0x29, -0x01,0xd0,0x01,0x33,0xf8,0xe7,0x20,0x21,0x07,0x2a,0x9f,0xbf,0x02,0xac,0xa1,0x18, -0x11,0xf8,0x08,0x1c,0x01,0x32,0xc1,0x54,0x01,0x33,0x07,0x2b,0xf3,0xd9,0x3e,0xbd, -0x48,0xb9,0x06,0x4a,0x53,0x68,0x03,0xb1,0x18,0x70,0x09,0xb1,0x00,0x23,0x0b,0x70, -0x51,0x60,0x00,0x20,0x70,0x47,0x0b,0x20,0x70,0x47,0x00,0xbf,0xcc,0x7f,0x00,0x20, -0x30,0xb5,0x00,0x23,0xad,0xf5,0x0f,0x7d,0x03,0x60,0x01,0x91,0x04,0x46,0x82,0xa9, -0x01,0xa8,0x15,0x46,0xff,0xf7,0x10,0xfb,0x8b,0xab,0x88,0x93,0x02,0xab,0x89,0x93, -0x18,0xb9,0x82,0xa8,0x01,0x99,0xff,0xf7,0x89,0xfd,0x87,0x9b,0x30,0xb9,0x23,0xb1, -0xda,0x7a,0xd2,0x06,0x05,0xd5,0x04,0x20,0x00,0xe0,0x06,0x20,0x0d,0xf5,0x0f,0x7d, -0x30,0xbd,0x05,0xf0,0x01,0x05,0xa5,0x71,0x1a,0x7d,0x59,0x7d,0xdd,0x7e,0x42,0xea, -0x01,0x21,0x9a,0x7e,0x42,0xea,0x05,0x22,0x42,0xea,0x01,0x42,0x22,0x61,0x9a,0x7f, -0xd9,0x7f,0x12,0x04,0x42,0xea,0x01,0x62,0x19,0x7f,0x5b,0x7f,0x0a,0x43,0x42,0xea, -0x03,0x23,0xe3,0x60,0x82,0x9b,0xa0,0x60,0x23,0x60,0xdb,0x88,0xa0,0x61,0xa3,0x80, -0xdc,0xe7,0x2d,0xe9,0xf8,0x4f,0x98,0x46,0x00,0x23,0x04,0x46,0x89,0x46,0xc8,0xf8, -0x00,0x30,0x81,0x88,0x00,0x68,0x17,0x46,0xff,0xf7,0x60,0xfa,0x05,0x46,0x00,0x28, -0x78,0xd1,0xa3,0x79,0x1a,0x06,0x72,0xd4,0xd8,0x07,0x72,0xd5,0xe6,0x68,0xa3,0x68, -0xf6,0x1a,0xb7,0x42,0x38,0xbf,0x3e,0x46,0x66,0xe0,0xa3,0x68,0xda,0x05,0x39,0xd1, -0x20,0x68,0x90,0xf8,0x02,0xa0,0x0a,0xf1,0xff,0x3a,0x0a,0xea,0x53,0x2a,0x5f,0xfa, -0x8a,0xfa,0xba,0xf1,0x00,0x0f,0x0a,0xd1,0x0b,0xb9,0x20,0x69,0x02,0xe0,0x61,0x69, -0xff,0xf7,0xc3,0xfb,0x01,0x28,0x09,0xd9,0x41,0x1c,0x29,0xd0,0x60,0x61,0xd4,0xf8, -0x00,0xb0,0x61,0x69,0x58,0x46,0xff,0xf7,0xad,0xfb,0x20,0xb9,0xa3,0x79,0x63,0xf0, -0x7f,0x03,0xa3,0x71,0x43,0xe0,0x00,0xeb,0x0a,0x02,0x77,0x0a,0x08,0xbf,0xa2,0x61, -0x10,0xd0,0x9b,0xf8,0x02,0x30,0x07,0xeb,0x0a,0x01,0x99,0x42,0x88,0xbf,0xca,0xeb, -0x03,0x07,0x9b,0xf8,0x01,0x00,0xfb,0xb2,0x49,0x46,0x00,0xf0,0x47,0xfc,0x38,0xb9, -0x7f,0x02,0x1f,0xe0,0x20,0x68,0xa1,0x69,0xa7,0x68,0xff,0xf7,0x22,0xfa,0x28,0xb1, -0xa3,0x79,0x01,0x25,0x63,0xf0,0x7f,0x03,0xa3,0x71,0x23,0xe0,0xa3,0x68,0xff,0x05, -0xdb,0x05,0xff,0x0d,0xdb,0x0d,0x22,0x68,0xc7,0xf5,0x00,0x77,0x28,0x33,0xbe,0x42, -0x38,0xbf,0x37,0x46,0xd3,0x18,0x03,0xe0,0x1a,0x5c,0x09,0xf8,0x00,0x20,0x01,0x30, -0xb8,0x42,0xf9,0xd1,0xa3,0x68,0xb9,0x44,0xdb,0x19,0xa3,0x60,0xd8,0xf8,0x00,0x30, -0xf6,0x1b,0xdb,0x19,0xc8,0xf8,0x00,0x30,0x00,0x2e,0x96,0xd1,0x02,0xe0,0x02,0x25, -0x00,0xe0,0x07,0x25,0x28,0x46,0xbd,0xe8,0xf8,0x8f,0x10,0xb5,0x81,0x88,0x04,0x46, -0x00,0x68,0xff,0xf7,0xdb,0xf9,0x00,0xb9,0x20,0x60,0x10,0xbd,0x10,0xb9,0x02,0x4b, -0x18,0x70,0x70,0x47,0x0b,0x20,0x70,0x47,0xcc,0x7f,0x00,0x20,0x00,0xb5,0xad,0xf5, -0x0f,0x7d,0x01,0x90,0x82,0xa9,0x01,0xa8,0xff,0xf7,0x36,0xfa,0xf0,0xb9,0x8b,0xab, -0x88,0x93,0x82,0xa8,0x02,0xab,0x01,0x99,0x89,0x93,0xff,0xf7,0xaf,0xfc,0x90,0xb9, -0x87,0x9b,0x84,0x9a,0x63,0xb1,0xda,0x7a,0xd1,0x06,0x12,0xd5,0x59,0x7d,0x1a,0x7d, -0x42,0xea,0x01,0x22,0xd9,0x7e,0x9b,0x7e,0x43,0xea,0x01,0x23,0x43,0xea,0x02,0x42, -0x82,0x9b,0xda,0x60,0x02,0xe0,0x04,0x28,0x08,0xbf,0x05,0x20,0x0d,0xf5,0x0f,0x7d, -0x00,0xbd,0x05,0x20,0xfa,0xe7,0x2d,0xe9,0xf0,0x43,0xad,0xf5,0x17,0x7d,0x01,0xaf, -0x00,0x23,0x82,0xae,0x38,0x60,0x88,0x46,0x03,0x70,0x31,0x46,0x38,0x46,0xff,0xf7, -0x03,0xfa,0x05,0x46,0x00,0x28,0x40,0xf0,0x8e,0x80,0x93,0xab,0x88,0x93,0x02,0xab, -0x89,0x93,0x82,0x9b,0x44,0x46,0xdb,0x68,0x84,0x93,0x5f,0xe0,0x30,0x46,0x01,0x21, -0xff,0xf7,0x70,0xfb,0x00,0x28,0x61,0xd1,0x30,0x46,0xff,0xf7,0xea,0xfb,0x01,0x46, -0x00,0x28,0x59,0xd1,0x87,0x9b,0x58,0x7d,0x1a,0x7d,0x42,0xea,0x00,0x22,0xd8,0x7e, -0x9b,0x7e,0x43,0xea,0x00,0x23,0x43,0xea,0x02,0x43,0x30,0x46,0x84,0x93,0xff,0xf7, -0x59,0xfb,0x00,0x28,0x4a,0xd1,0x30,0x46,0xff,0xf7,0xd3,0xfb,0x88,0xb9,0x87,0x9b, -0x59,0x7d,0x1a,0x7d,0x42,0xea,0x01,0x22,0xd9,0x7e,0x9b,0x7e,0x43,0xea,0x01,0x23, -0x43,0xea,0x02,0x43,0x99,0x45,0x09,0xd0,0x30,0x46,0xff,0xf7,0x88,0xfb,0x00,0x28, -0xe9,0xd0,0x04,0x28,0x14,0xbf,0x05,0x46,0x02,0x25,0x32,0xe0,0x3b,0x68,0x30,0x46, -0x8b,0xa9,0x91,0x93,0x92,0x94,0xff,0xf7,0xcb,0xf8,0x3a,0x68,0x13,0x78,0x13,0xb9, -0x8b,0xab,0x03,0xf1,0x09,0x02,0x00,0x23,0x00,0xe0,0x01,0x33,0xd1,0x5c,0x00,0x29, -0xfb,0xd1,0xd9,0x1c,0x8c,0x42,0x18,0x46,0x1a,0xd3,0x21,0x46,0x07,0xe0,0x01,0x3b, -0x12,0xf8,0x03,0x90,0xd7,0xf8,0x00,0xc0,0x01,0x39,0x0c,0xf8,0x01,0x90,0x00,0x2b, -0xf5,0xd1,0xc3,0x43,0xe4,0x18,0x3b,0x68,0x2f,0x22,0x1a,0x55,0xdd,0xf8,0x10,0x92, -0xb9,0xf1,0x00,0x0f,0x9a,0xd1,0x04,0xe0,0x05,0x46,0x02,0xe0,0x05,0x46,0x00,0xe0, -0x11,0x25,0x01,0xa9,0x0b,0x68,0xa5,0xb9,0x0d,0x4a,0x12,0x78,0x30,0x32,0x1a,0x70, -0x3a,0x22,0x5a,0x70,0x9a,0x1c,0x44,0x45,0x03,0xd1,0x2f,0x22,0x9a,0x70,0x03,0x33, -0x07,0xe0,0x0b,0x68,0x1b,0x5d,0x01,0x34,0x02,0xf8,0x01,0x3b,0x44,0x45,0x13,0x46, -0xf7,0xd3,0x00,0x22,0x1a,0x70,0x28,0x46,0x0d,0xf5,0x17,0x7d,0xbd,0xe8,0xf0,0x83, -0xcc,0x7f,0x00,0x20,0xf8,0xb5,0x04,0x46,0x0d,0x46,0x81,0x88,0x00,0x68,0xff,0xf7, -0xf5,0xf8,0x06,0x46,0x00,0x28,0x58,0xd1,0x94,0xf9,0x06,0x30,0x00,0x2b,0x53,0xdb, -0xe3,0x68,0x01,0x46,0x9d,0x42,0x28,0xbf,0x1d,0x46,0xa3,0x68,0xa0,0x60,0x00,0x2d, -0x42,0xd0,0x22,0x68,0x97,0x78,0x7f,0x02,0x6b,0xb1,0x01,0x3b,0x69,0x1e,0xb1,0xfb, -0xf7,0xf1,0xb3,0xfb,0xf7,0xf2,0x91,0x42,0x05,0xd3,0x7a,0x42,0x13,0x40,0xa3,0x60, -0xed,0x1a,0x61,0x69,0x01,0xe0,0x21,0x69,0x61,0x61,0x00,0x29,0x2c,0xd0,0x16,0xe0, -0x20,0x68,0xff,0xf7,0x52,0xfa,0x01,0x46,0x01,0x30,0x05,0xd1,0xa3,0x79,0x01,0x26, -0x63,0xf0,0x7f,0x03,0xa3,0x71,0x28,0xe0,0x01,0x29,0x14,0xd9,0x23,0x68,0x1b,0x69, -0x99,0x42,0x10,0xd2,0xa3,0x68,0x61,0x61,0xdb,0x19,0xa3,0x60,0xed,0x1b,0xbd,0x42, -0xe6,0xd8,0xa3,0x68,0x5b,0x19,0xa3,0x60,0xeb,0x05,0xda,0x0d,0x5b,0xb1,0x20,0x68, -0xff,0xf7,0x28,0xfa,0x20,0xb9,0xa3,0x79,0x63,0xf0,0x7f,0x03,0xa3,0x71,0x0b,0xe0, -0x00,0xeb,0x55,0x21,0x00,0xe0,0x11,0x46,0xa3,0x68,0xdb,0x05,0x05,0xd0,0xa3,0x69, -0x99,0x42,0x18,0xbf,0xa1,0x61,0x00,0xe0,0x02,0x26,0x30,0x46,0xf8,0xbd,0x10,0xb5, -0x04,0x46,0xad,0xf5,0x06,0x7d,0x01,0x91,0x01,0xa8,0x21,0x46,0xff,0xf7,0xfc,0xf8, -0x20,0xbb,0x83,0xab,0xa3,0x61,0x03,0xab,0xe3,0x61,0x20,0x46,0x01,0x99,0xff,0xf7, -0x75,0xfb,0xb0,0xb9,0x63,0x69,0x6b,0xb1,0xda,0x7a,0xd2,0x06,0x15,0xd5,0x59,0x7d, -0x1a,0x7d,0x42,0xea,0x01,0x22,0xd9,0x7e,0x9b,0x7e,0x43,0xea,0x01,0x23,0x43,0xea, -0x02,0x43,0xa3,0x60,0x23,0x68,0x20,0x46,0xdb,0x88,0x00,0x21,0xa3,0x80,0xff,0xf7, -0x59,0xfa,0x04,0x28,0x08,0xbf,0x05,0x20,0x00,0xe0,0x05,0x20,0x0d,0xf5,0x06,0x7d, -0x10,0xbd,0x70,0xb5,0x04,0x46,0xad,0xf5,0x04,0x7d,0x0e,0x46,0x81,0x88,0x00,0x68, -0xff,0xf7,0x5c,0xf8,0x05,0x46,0xf0,0xb9,0x26,0xb9,0x20,0x46,0x29,0x46,0xff,0xf7, -0x41,0xfa,0x17,0xe0,0x81,0xab,0xa3,0x61,0x01,0xab,0xe3,0x61,0x20,0x46,0xff,0xf7, -0xb8,0xfa,0x04,0x28,0x08,0xbf,0x25,0x61,0x00,0xd0,0x58,0xb9,0x20,0x46,0x31,0x46, -0xfe,0xf7,0xc6,0xff,0x20,0x46,0xff,0xf7,0x72,0xfa,0x04,0x28,0x02,0xd1,0x00,0x23, -0x23,0x61,0x00,0xe0,0x05,0x46,0x28,0x46,0x0d,0xf5,0x04,0x7d,0x70,0xbd,0x00,0xbf, -0x12,0x4b,0x4f,0xf4,0x00,0x51,0x59,0x83,0x4f,0xf4,0x00,0x62,0x4f,0xf4,0x80,0x41, -0x1a,0x83,0x59,0x83,0x09,0x22,0x0e,0xe0,0x4f,0xf4,0x00,0x61,0x59,0x83,0x10,0xf0, -0x80,0x0f,0x4f,0xf4,0x80,0x61,0x14,0xbf,0x19,0x83,0x59,0x83,0x40,0x00,0x4f,0xf4, -0x00,0x61,0xc0,0xb2,0x19,0x83,0x01,0x3a,0x04,0x49,0xed,0xd1,0x4f,0xf4,0x80,0x42, -0x4f,0xf4,0x00,0x53,0x0a,0x83,0x0b,0x83,0x70,0x47,0x00,0xbf,0x00,0x0c,0x02,0x40, -0x12,0x4b,0x4f,0xf4,0x00,0x61,0x19,0x83,0x4f,0xf4,0x00,0x52,0x4f,0xf4,0x80,0x41, -0x1a,0x83,0x59,0x83,0x09,0x22,0x0e,0xe0,0x10,0xf0,0x80,0x0f,0x4f,0xf4,0x80,0x61, -0x14,0xbf,0x19,0x83,0x59,0x83,0x40,0x00,0x4f,0xf4,0x00,0x61,0x59,0x83,0xc0,0xb2, -0x00,0xbf,0x19,0x83,0x00,0xbf,0x01,0x3a,0x04,0x49,0xed,0xd1,0x4f,0xf4,0x80,0x42, -0x4f,0xf4,0x00,0x53,0x0a,0x83,0x0b,0x83,0x70,0x47,0x00,0xbf,0x00,0x0c,0x02,0x40, -0xf0,0xb5,0x02,0x20,0x89,0xb0,0x01,0x21,0xfc,0xf7,0x28,0xf8,0x4f,0xf4,0x80,0x40, -0x01,0x21,0xfc,0xf7,0x47,0xf8,0x39,0x48,0x0d,0x21,0x05,0x22,0xfc,0xf7,0x0d,0xfa, -0x36,0x48,0x0e,0x21,0x05,0x22,0xfc,0xf7,0x08,0xfa,0x34,0x48,0x0f,0x21,0x05,0x22, -0xfc,0xf7,0x03,0xfa,0x32,0x4e,0x7d,0x24,0x4a,0xf6,0xaa,0x25,0x44,0xf6,0x20,0x60, -0x01,0xf0,0x8a,0xfc,0x01,0x3c,0x35,0x60,0xf8,0xd1,0x4f,0xf4,0x82,0x73,0xad,0xf8, -0x06,0x30,0x4f,0xf4,0x00,0x73,0xad,0xf8,0x0e,0x30,0x08,0x23,0xad,0xf8,0x10,0x30, -0x01,0xa9,0x07,0x23,0x27,0x48,0xad,0xf8,0x14,0x30,0xad,0xf8,0x04,0x40,0xad,0xf8, -0x08,0x40,0xad,0xf8,0x0a,0x40,0xad,0xf8,0x0c,0x40,0xad,0xf8,0x12,0x40,0xfc,0xf7, -0x25,0xfa,0x21,0x46,0x1f,0x48,0xfc,0xf7,0x19,0xfb,0x1c,0x4d,0x01,0x21,0x1d,0x48, -0xfc,0xf7,0xb7,0xfa,0x4f,0xf4,0x80,0x53,0x2b,0x83,0x26,0x46,0x01,0x27,0x8d,0xf8, -0x1e,0x40,0x8d,0xf8,0x1f,0x40,0x28,0x46,0x02,0x24,0x06,0xa9,0x06,0x93,0x8d,0xf8, -0x1c,0x70,0x8d,0xf8,0x1d,0x40,0xfc,0xf7,0x3f,0xf9,0x4f,0xf4,0x20,0x43,0x28,0x46, -0x06,0xa9,0x06,0x93,0x8d,0xf8,0x1d,0x40,0x8d,0xf8,0x1c,0x40,0x8d,0xf8,0x1e,0x60, -0x8d,0xf8,0x1f,0x70,0xfc,0xf7,0x30,0xf9,0x4f,0xf4,0x80,0x43,0x28,0x46,0x06,0xa9, -0x06,0x93,0x8d,0xf8,0x1d,0x40,0x8d,0xf8,0x1c,0x40,0x8d,0xf8,0x1e,0x60,0x8d,0xf8, -0x1f,0x70,0xfc,0xf7,0x21,0xf9,0x09,0xb0,0xf0,0xbd,0x00,0xbf,0x00,0x04,0x02,0x40, -0x00,0x30,0x00,0x40,0x00,0x38,0x00,0x40,0x01,0x46,0x08,0xb5,0x06,0x48,0xfc,0xf7, -0xd3,0xfa,0x05,0x48,0x01,0x21,0xfc,0xf7,0x04,0xfb,0x00,0x28,0xf9,0xd0,0x02,0x48, -0xfc,0xf7,0xc7,0xfa,0xc0,0xb2,0x08,0xbd,0x00,0x38,0x00,0x40,0xff,0x20,0xeb,0xe7, -0x10,0xb5,0x06,0x4c,0x32,0x23,0x23,0x60,0xff,0xf7,0xf8,0xff,0xff,0xf7,0xf6,0xff, -0xff,0x28,0x02,0xd0,0x23,0x68,0x00,0x2b,0xf8,0xd1,0x10,0xbd,0xd8,0x7f,0x00,0x20, -0x02,0x4b,0x4f,0xf4,0x80,0x52,0x1a,0x83,0xe8,0xe7,0x00,0xbf,0x00,0x04,0x02,0x40, -0x02,0x06,0x38,0xb5,0x04,0x46,0x0d,0x46,0x07,0xd5,0x77,0x20,0x00,0x21,0xff,0xf7, -0xf7,0xff,0x01,0x28,0x32,0xd8,0x04,0xf0,0x7f,0x04,0x19,0x4b,0x4f,0xf4,0x80,0x52, -0x5a,0x83,0xff,0xf7,0xd5,0xff,0xff,0x28,0x27,0xd1,0x20,0x46,0xff,0xf7,0xbc,0xff, -0x28,0x0e,0xff,0xf7,0xb9,0xff,0xc5,0xf3,0x07,0x40,0xff,0xf7,0xb5,0xff,0xc5,0xf3, -0x07,0x20,0xff,0xf7,0xb1,0xff,0xe8,0xb2,0xff,0xf7,0xae,0xff,0x95,0x20,0x40,0x2c, -0x03,0xd0,0x48,0x2c,0x0c,0xbf,0x87,0x20,0x01,0x20,0xff,0xf7,0xa5,0xff,0x4c,0x2c, -0x01,0xd1,0xff,0xf7,0xb3,0xff,0x0a,0x24,0xff,0xf7,0xb0,0xff,0x03,0x06,0x05,0xd5, -0x01,0x3c,0xe4,0xb2,0x00,0x2c,0xf7,0xd1,0x38,0xbd,0xff,0x20,0x38,0xbd,0x00,0xbf, -0x00,0x04,0x02,0x40,0x70,0xb5,0x15,0x4e,0x0a,0x23,0x04,0x46,0x0d,0x46,0x73,0x60, -0xff,0xf7,0x9c,0xff,0xff,0x28,0x03,0xd1,0x70,0x68,0x00,0x28,0xf8,0xd1,0x70,0xbd, -0xfe,0x28,0x18,0xd1,0xff,0x20,0xff,0xf7,0x7f,0xff,0x20,0x70,0xff,0x20,0xff,0xf7, -0x7b,0xff,0x60,0x70,0xff,0x20,0xff,0xf7,0x77,0xff,0xa0,0x70,0xff,0x20,0xff,0xf7, -0x73,0xff,0xe0,0x70,0x04,0x34,0x04,0x3d,0xec,0xd1,0xff,0xf7,0x7f,0xff,0xff,0xf7, -0x7d,0xff,0x01,0x20,0x70,0xbd,0x00,0x20,0x70,0xbd,0x00,0xbf,0xd8,0x7f,0x00,0x20, -0x38,0xb5,0x04,0x46,0x0d,0x46,0xff,0xf7,0x73,0xff,0xff,0x28,0x22,0xd1,0x28,0x46, -0xff,0xf7,0x5a,0xff,0xfd,0x2d,0x1b,0xd0,0x00,0x25,0x60,0x5d,0xff,0xf7,0x54,0xff, -0x63,0x19,0x58,0x78,0x02,0x35,0xff,0xf7,0x4f,0xff,0xb5,0xf5,0x00,0x7f,0xf4,0xd1, -0xff,0x20,0xff,0xf7,0x49,0xff,0xff,0x20,0xff,0xf7,0x46,0xff,0xff,0xf7,0x56,0xff, -0x00,0xf0,0x1f,0x00,0xa0,0xf1,0x05,0x01,0x48,0x42,0x40,0xeb,0x01,0x00,0x38,0xbd, -0x01,0x20,0x38,0xbd,0x00,0x20,0x38,0xbd,0x02,0x4b,0x18,0x69,0x00,0xf4,0x00,0x70, -0x70,0x47,0x00,0xbf,0x00,0x0c,0x02,0x40,0x73,0xb5,0x00,0x28,0x40,0xf0,0x84,0x80, -0x47,0x4b,0x1a,0x78,0x90,0x07,0x7d,0xd4,0xff,0xf7,0xa2,0xfe,0x45,0x4b,0x0a,0x24, -0x1a,0x88,0x92,0xb2,0x42,0xf0,0x30,0x02,0x1a,0x80,0x01,0x3c,0xe4,0xb2,0xff,0xf7, -0x2d,0xff,0x00,0x2c,0xf9,0xd1,0x40,0x20,0x21,0x46,0xff,0xf7,0x41,0xff,0x01,0x28, -0x55,0xd1,0x3d,0x4d,0x64,0x23,0x48,0x20,0x4f,0xf4,0xd5,0x71,0x6b,0x60,0xff,0xf7, -0x37,0xff,0x01,0x28,0x2f,0xd1,0xff,0xf7,0x19,0xff,0x01,0xab,0xe0,0x54,0x01,0x34, -0x04,0x2c,0xf8,0xd1,0x9d,0xf8,0x06,0x30,0x01,0x2b,0x3f,0xd1,0x9d,0xf8,0x07,0x30, -0xaa,0x2b,0x3b,0xd1,0x30,0x4c,0x63,0x68,0x00,0x2b,0x4f,0xd0,0xe9,0x20,0x4f,0xf0, -0x80,0x41,0xff,0xf7,0x1d,0xff,0x00,0x28,0xf5,0xd1,0x47,0xe0,0x7a,0x20,0x00,0x21, -0xff,0xf7,0x16,0xff,0x50,0xbb,0x04,0x46,0xff,0xf7,0xf8,0xfe,0x01,0xab,0xe0,0x54, -0x01,0x34,0x04,0x2c,0xf8,0xd1,0x9d,0xf8,0x04,0x30,0x13,0xf0,0x40,0x0f,0x0c,0xbf, -0x04,0x24,0x0c,0x24,0x1b,0xe0,0xe9,0x20,0x21,0x46,0xff,0xf7,0x01,0xff,0x01,0x28, -0x8c,0xbf,0x01,0x24,0x02,0x24,0x8c,0xbf,0x41,0x26,0xe9,0x26,0x6b,0x68,0x00,0x2b, -0x29,0xd0,0x30,0x46,0x00,0x21,0xff,0xf7,0xf3,0xfe,0x00,0x28,0xf6,0xd1,0x22,0xe0, -0x50,0x20,0x4f,0xf4,0x00,0x71,0xff,0xf7,0xeb,0xfe,0x00,0xb1,0x00,0x24,0x12,0x4b, -0x1c,0x72,0xff,0xf7,0xdd,0xfe,0x64,0xb1,0x0d,0x4b,0x1a,0x78,0x02,0xf0,0xfe,0x02, -0x1a,0x70,0x0c,0x4b,0x1a,0x88,0x92,0xb2,0x22,0xf0,0x38,0x02,0x42,0xf0,0x08,0x02, -0x1a,0x80,0x07,0x4b,0x18,0x78,0x00,0xe0,0x01,0x20,0x7c,0xbd,0x06,0x4b,0x5b,0x68, -0x00,0x2b,0xe3,0xd0,0xb2,0xe7,0x04,0x4b,0x5b,0x68,0x00,0x2b,0xde,0xd0,0xd7,0xe7, -0xce,0x78,0x00,0x20,0x00,0x38,0x00,0x40,0xd8,0x7f,0x00,0x20,0x10,0xb9,0x02,0x4b, -0x18,0x78,0x70,0x47,0x01,0x20,0x70,0x47,0xce,0x78,0x00,0x20,0x38,0xb5,0x0e,0x4b, -0x04,0x46,0x1b,0x7a,0x15,0x46,0x1b,0x07,0x58,0xbf,0x49,0x02,0x52,0x20,0xff,0xf7, -0xaf,0xfe,0x68,0xb9,0x20,0x46,0x4f,0xf4,0x00,0x71,0xff,0xf7,0xeb,0xfe,0x18,0xb1, -0x01,0x3d,0x04,0xf5,0x00,0x74,0xf5,0xd1,0x4c,0x20,0x00,0x21,0xff,0xf7,0xa0,0xfe, -0xff,0xf7,0x96,0xfe,0x00,0x20,0x38,0xbd,0xd8,0x7f,0x00,0x20,0x00,0x30,0x18,0xbf, -0x01,0x20,0x00,0x2b,0x08,0xbf,0x40,0xf0,0x01,0x00,0x38,0xb5,0x0c,0x46,0x1d,0x46, -0x11,0x46,0x00,0x28,0x32,0xd1,0x1b,0x4b,0x1b,0x78,0xd8,0x07,0x30,0xd4,0x1a,0x4b, -0x1b,0x7a,0x1a,0x07,0x58,0xbf,0x49,0x02,0x01,0x2d,0x0d,0xd1,0x51,0x20,0xff,0xf7, -0x7f,0xfe,0xe8,0xb9,0x20,0x46,0x4f,0xf4,0x00,0x71,0xff,0xf7,0xbb,0xfe,0xd0,0xf1, -0x01,0x05,0x38,0xbf,0x00,0x25,0x13,0xe0,0x52,0x20,0xff,0xf7,0x71,0xfe,0x78,0xb9, -0x20,0x46,0x4f,0xf4,0x00,0x71,0xff,0xf7,0xad,0xfe,0x28,0xb1,0x01,0x3d,0xed,0xb2, -0x04,0xf5,0x00,0x74,0x00,0x2d,0xf3,0xd1,0x4c,0x20,0x00,0x21,0xff,0xf7,0x60,0xfe, -0xff,0xf7,0x56,0xfe,0x28,0x1c,0x18,0xbf,0x01,0x20,0x38,0xbd,0x04,0x20,0x38,0xbd, -0x03,0x20,0x38,0xbd,0xce,0x78,0x00,0x20,0xd8,0x7f,0x00,0x20,0x70,0xb5,0x12,0x4b, -0x16,0x46,0x1b,0x7a,0x0c,0x46,0x1a,0x07,0x58,0xbf,0x4c,0x02,0x13,0xf0,0x06,0x0f, -0x05,0x46,0x03,0xd0,0xd7,0x20,0x31,0x46,0xff,0xf7,0x42,0xfe,0x59,0x20,0x21,0x46, -0xff,0xf7,0x3e,0xfe,0x60,0xb9,0x28,0x46,0xfc,0x21,0xff,0xf7,0xa9,0xfe,0x18,0xb1, -0x01,0x3e,0x05,0xf5,0x00,0x75,0xf6,0xd1,0x00,0x20,0xfd,0x21,0xff,0xf7,0xa0,0xfe, -0xff,0xf7,0x26,0xfe,0x00,0x20,0x70,0xbd,0xd8,0x7f,0x00,0x20,0x00,0x30,0x18,0xbf, -0x01,0x20,0x00,0x2b,0x08,0xbf,0x40,0xf0,0x01,0x00,0x70,0xb5,0x0c,0x46,0x15,0x46, -0x1e,0x46,0x00,0x28,0x3f,0xd1,0x23,0x4b,0x1a,0x78,0xd2,0x07,0x3d,0xd4,0x1b,0x78, -0x58,0x07,0x3c,0xd4,0x20,0x4b,0x1b,0x7a,0x19,0x07,0x58,0xbf,0x6d,0x02,0x01,0x2e, -0x0d,0xd1,0x58,0x20,0x29,0x46,0xff,0xf7,0x0b,0xfe,0x30,0xbb,0xfe,0x21,0x20,0x46, -0xff,0xf7,0x76,0xfe,0xd0,0xf1,0x01,0x06,0x38,0xbf,0x00,0x26,0x1d,0xe0,0x13,0xf0, -0x06,0x0f,0x03,0xd0,0xd7,0x20,0x31,0x46,0xff,0xf7,0xfa,0xfd,0x59,0x20,0x29,0x46, -0xff,0xf7,0xf6,0xfd,0x88,0xb9,0x20,0x46,0xfc,0x21,0xff,0xf7,0x61,0xfe,0x28,0xb1, -0x01,0x3e,0xf6,0xb2,0x04,0xf5,0x00,0x74,0x00,0x2e,0xf4,0xd1,0x00,0x20,0xfd,0x21, -0xff,0xf7,0x56,0xfe,0x00,0x28,0x08,0xbf,0x01,0x26,0xff,0xf7,0xd9,0xfd,0x30,0x1c, -0x18,0xbf,0x01,0x20,0x70,0xbd,0x04,0x20,0x70,0xbd,0x03,0x20,0x70,0xbd,0x02,0x20, -0x70,0xbd,0x00,0xbf,0xce,0x78,0x00,0x20,0xd8,0x7f,0x00,0x20,0x70,0xb5,0x05,0x46, -0x86,0xb0,0x14,0x46,0x00,0x28,0x40,0xf0,0x27,0x81,0x05,0x29,0x3a,0xd1,0x13,0x78, -0x01,0x2b,0x31,0xd0,0x03,0xd3,0x02,0x2b,0x40,0xf0,0x1e,0x81,0x2f,0xe0,0x90,0x4b, -0x1b,0x78,0xdd,0x07,0x07,0xd4,0x8f,0x4b,0x4f,0xf4,0x80,0x52,0x5a,0x83,0xff,0xf7, -0x9f,0xfd,0xff,0xf7,0xad,0xfd,0x8c,0x48,0xfb,0xf7,0x36,0xff,0x8a,0x48,0x00,0x21, -0xfb,0xf7,0xff,0xff,0x4f,0xf4,0x80,0x40,0x00,0x21,0xfb,0xf7,0x4b,0xfd,0x4f,0xf4, -0x60,0x43,0x04,0x93,0x00,0x25,0x02,0x23,0x82,0x48,0x04,0xa9,0x8d,0xf8,0x17,0x30, -0x8d,0xf8,0x14,0x50,0x8d,0xf8,0x16,0x50,0xfb,0xf7,0x86,0xfe,0x7c,0x4b,0x1a,0x78, -0x42,0xf0,0x01,0x02,0x1a,0x70,0xf0,0xe0,0xff,0xf7,0xe2,0xfc,0xed,0xe0,0x01,0x23, -0x53,0x70,0xea,0xe0,0x76,0x4b,0x03,0x25,0x1b,0x78,0xd8,0x07,0x00,0xf1,0xe5,0x80, -0x0e,0x29,0x00,0xf2,0xdb,0x80,0xdf,0xe8,0x11,0xf0,0x0f,0x00,0x1a,0x00,0x56,0x00, -0x5a,0x00,0xd9,0x00,0xd9,0x00,0xd9,0x00,0xd9,0x00,0xd9,0x00,0xd9,0x00,0xa9,0x00, -0xad,0x00,0xaf,0x00,0xbb,0x00,0xc9,0x00,0x6a,0x4b,0x4f,0xf4,0x80,0x52,0x5a,0x83, -0xff,0xf7,0x56,0xfd,0xb0,0xf1,0xff,0x05,0x18,0xbf,0x01,0x25,0xc1,0xe0,0x49,0x20, -0x00,0x21,0xff,0xf7,0x65,0xfd,0x05,0x46,0x00,0x28,0x40,0xf0,0xb9,0x80,0x68,0x46, -0x10,0x21,0xff,0xf7,0x9f,0xfd,0x00,0x28,0x00,0xf0,0xb2,0x80,0x9d,0xf8,0x00,0x30, -0x9b,0x11,0x01,0x2b,0x9d,0xf8,0x08,0x30,0x07,0xd1,0x9d,0xf8,0x09,0x20,0x01,0x32, -0x02,0xeb,0x03,0x23,0x9b,0xb2,0x9b,0x02,0x1b,0xe0,0x9d,0xf8,0x07,0x20,0x9d,0xf8, -0x05,0x10,0x92,0x00,0x01,0x32,0x02,0xeb,0x93,0x13,0x9d,0xf8,0x06,0x20,0x01,0xf0, -0x0f,0x01,0x02,0xf0,0x03,0x02,0x03,0xeb,0x82,0x23,0x9d,0xf8,0x0a,0x20,0x01,0xeb, -0xd2,0x11,0x9d,0xf8,0x09,0x20,0x02,0xf0,0x03,0x02,0x01,0xeb,0x42,0x02,0x07,0x3a, -0x93,0x40,0x23,0x60,0x85,0xe0,0x4f,0xf4,0x00,0x73,0x13,0x80,0x6c,0xe0,0x47,0x4d, -0x29,0x7a,0x11,0xf0,0x04,0x01,0x1b,0xd0,0xcd,0x20,0x00,0x21,0xff,0xf7,0x20,0xfd, -0x00,0x28,0x75,0xd1,0xff,0xf7,0x02,0xfd,0x68,0x46,0x10,0x21,0xff,0xf7,0x5a,0xfd, -0x00,0x28,0x6d,0xd0,0x30,0x25,0x01,0x3d,0xed,0xb2,0xff,0xf7,0xf7,0xfc,0x00,0x2d, -0xf9,0xd1,0x9d,0xf8,0x0a,0x30,0x10,0x22,0x1b,0x11,0x12,0xfa,0x03,0xf3,0xd8,0xe7, -0x49,0x20,0xff,0xf7,0x05,0xfd,0x06,0x46,0x00,0x28,0x59,0xd1,0x68,0x46,0x10,0x21, -0xff,0xf7,0x40,0xfd,0x00,0x28,0x53,0xd0,0x2d,0x7a,0x9d,0xf8,0x0a,0x20,0x15,0xf0, -0x02,0x05,0x9d,0xf8,0x0b,0x30,0x0d,0xd0,0x9d,0xf8,0x0d,0x10,0x02,0xf0,0x3f,0x02, -0xdb,0x09,0x03,0xeb,0x42,0x03,0x89,0x11,0x01,0x33,0x01,0x39,0x8b,0x40,0x35,0x46, -0x23,0x60,0x3e,0xe0,0xc2,0xf3,0x84,0x02,0x51,0x1c,0x03,0xf0,0x03,0x02,0x5b,0x09, -0x03,0xeb,0xc2,0x02,0x01,0x32,0x4a,0x43,0x22,0x60,0x32,0xe0,0x1f,0x4b,0x1b,0x7a, -0x13,0x70,0x19,0xe0,0x49,0x20,0x00,0xe0,0x4a,0x20,0x00,0x21,0xff,0xf7,0xd0,0xfc, -0x05,0x46,0x28,0xbb,0x20,0x46,0x10,0x21,0xff,0xf7,0x0c,0xfd,0x08,0xbb,0x1f,0xe0, -0x7a,0x20,0x00,0x21,0xff,0xf7,0xc4,0xfc,0xd0,0xb9,0x05,0x46,0xff,0xf7,0xa6,0xfc, -0x60,0x55,0x01,0x35,0x04,0x2d,0xf9,0xd1,0x00,0x25,0x12,0xe0,0xcd,0x20,0x00,0x21, -0xff,0xf7,0xb6,0xfc,0x60,0xb9,0xff,0xf7,0x99,0xfc,0x40,0x21,0x20,0x46,0xff,0xf7, -0xf1,0xfc,0xd0,0xf1,0x01,0x05,0x38,0xbf,0x00,0x25,0x02,0xe0,0x04,0x25,0x00,0xe0, -0x01,0x25,0xff,0xf7,0x9d,0xfc,0x00,0xe0,0x04,0x25,0x28,0x46,0x06,0xb0,0x70,0xbd, -0xce,0x78,0x00,0x20,0x00,0x04,0x02,0x40,0x00,0x38,0x00,0x40,0xd8,0x7f,0x00,0x20, -0x0e,0x4b,0x5a,0x68,0xd2,0xb2,0x12,0xb1,0x01,0x3a,0xd2,0xb2,0x5a,0x60,0x1b,0x68, -0xdb,0xb2,0x1b,0xb1,0x01,0x3b,0x09,0x4a,0xdb,0xb2,0x13,0x60,0x08,0x4b,0x07,0x4a, -0x1b,0x69,0xd1,0x68,0x03,0xf4,0x00,0x73,0x99,0x42,0xd3,0x60,0x01,0xbf,0x05,0x4b, -0x1a,0x78,0x02,0xf0,0xf9,0x02,0x1a,0x70,0x70,0x47,0x00,0xbf,0xd8,0x7f,0x00,0x20, -0x00,0x0c,0x02,0x40,0xce,0x78,0x00,0x20,0x10,0xb5,0x05,0x4c,0x00,0x20,0x04,0xf1, -0x10,0x01,0xff,0xf7,0xe5,0xf8,0x10,0xb9,0x64,0x23,0xc4,0xf8,0x38,0x32,0x10,0xbd, -0xd8,0x7f,0x00,0x20,0x04,0x4b,0xd3,0xf8,0x38,0x02,0xa0,0xf1,0x64,0x0c,0xdc,0xf1, -0x00,0x00,0x40,0xeb,0x0c,0x00,0x70,0x47,0xd8,0x7f,0x00,0x20,0x70,0x47,0x04,0x4b, -0xd3,0xf8,0x38,0x02,0xa0,0xf1,0x64,0x03,0x58,0x42,0x40,0xeb,0x03,0x00,0x70,0x47, -0xd8,0x7f,0x00,0x20,0x84,0xb0,0x01,0x90,0x00,0x23,0x1c,0xe0,0x8d,0xf8,0x0f,0x30, -0x05,0xe0,0x9d,0xf8,0x0f,0x20,0x01,0x32,0xd2,0xb2,0x8d,0xf8,0x0f,0x20,0x9d,0xf8, -0x0f,0x20,0xf9,0x2a,0xf5,0xd9,0x8d,0xf8,0x0f,0x30,0x05,0xe0,0x9d,0xf8,0x0f,0x20, -0x01,0x32,0xd2,0xb2,0x8d,0xf8,0x0f,0x20,0x9d,0xf8,0x0f,0x20,0x4a,0x2a,0xf5,0xd9, -0x01,0x9a,0x01,0x3a,0x01,0x92,0x01,0x9a,0x00,0x2a,0xdf,0xd1,0x04,0xb0,0x70,0x47, -0x37,0xb5,0x02,0x20,0x01,0x21,0x1c,0x4d,0xfb,0xf7,0xa0,0xfb,0x4f,0xf4,0x80,0x73, -0x00,0x24,0x00,0x93,0x28,0x46,0x02,0x23,0x69,0x46,0x8d,0xf8,0x04,0x30,0x8d,0xf8, -0x05,0x30,0x8d,0xf8,0x06,0x40,0x8d,0xf8,0x07,0x40,0xfb,0xf7,0xfd,0xfc,0x28,0x46, -0x08,0x21,0x03,0x22,0xfb,0xf7,0x79,0xfd,0x10,0x4b,0x11,0x49,0x5a,0x6c,0x11,0x48, -0x42,0xf4,0x00,0x32,0x5a,0x64,0xa3,0xf5,0x74,0x43,0x64,0x22,0xda,0x62,0x0e,0x4a, -0x09,0x68,0x12,0x68,0x4a,0x43,0x42,0xf2,0x10,0x71,0xb2,0xfb,0xf1,0xf2,0x01,0x3a, -0x92,0xb2,0x1a,0x85,0x60,0x22,0x1a,0x83,0x50,0x21,0x01,0x22,0x1a,0x84,0x01,0x80, -0x59,0x63,0x9c,0x82,0x1a,0x80,0x3e,0xbd,0x00,0x04,0x02,0x40,0x00,0x38,0x02,0x40, -0x7c,0x9f,0x00,0x20,0x14,0x82,0x00,0x20,0x78,0x9f,0x00,0x20,0x38,0xb5,0x04,0x46, -0x24,0x11,0x00,0xf0,0x0f,0x00,0x0d,0x46,0xff,0xf7,0xda,0xfa,0x44,0xf0,0x10,0x00, -0xff,0xf7,0xd6,0xfa,0x05,0xf0,0x0f,0x00,0x40,0xf0,0x60,0x00,0xff,0xf7,0xd0,0xfa, -0x2d,0x09,0x45,0xf0,0x70,0x00,0xbd,0xe8,0x38,0x40,0xff,0xf7,0xc9,0xba,0x2d,0xe9, -0xf0,0x41,0x48,0x4c,0x00,0x25,0x26,0x46,0x47,0x4b,0xea,0x08,0x4f,0xf0,0xd4,0x08, -0x08,0xfb,0x02,0x38,0x01,0x27,0x05,0xf0,0x07,0x03,0x9f,0x40,0xe9,0xb2,0x00,0x20, -0xff,0xf7,0xd4,0xff,0xaf,0x20,0xff,0xf7,0xb3,0xfa,0x4f,0xf4,0x00,0x60,0x20,0x83, -0x4f,0xf4,0x00,0x53,0x4f,0xf4,0x80,0x40,0x3c,0x4a,0x23,0x83,0xff,0xb2,0x60,0x83, -0x00,0x21,0x18,0xf8,0x01,0x30,0x08,0xeb,0x01,0x00,0x40,0x78,0x3b,0x40,0x18,0xbf, -0xf0,0x23,0x07,0x42,0x18,0xbf,0x0f,0x33,0x13,0xf0,0x80,0x0f,0x4f,0xf4,0x80,0x60, -0x14,0xbf,0x20,0x83,0x60,0x83,0x4f,0xf4,0x00,0x60,0x60,0x83,0x58,0x06,0x46,0xbf, -0x4f,0xf4,0x40,0x60,0x20,0x83,0xa2,0x61,0x00,0xbf,0x4f,0xf4,0x00,0x60,0x60,0x83, -0x98,0x06,0x46,0xbf,0x4f,0xf4,0x40,0x60,0x20,0x83,0xa2,0x61,0x00,0xbf,0x4f,0xf4, -0x00,0x60,0x70,0x83,0xd8,0x06,0x46,0xbf,0x4f,0xf4,0x40,0x60,0x20,0x83,0xa2,0x61, -0x00,0xbf,0x4f,0xf4,0x00,0x60,0x60,0x83,0x18,0x07,0x46,0xbf,0x4f,0xf4,0x40,0x60, -0x20,0x83,0xa2,0x61,0x00,0xbf,0x4f,0xf4,0x00,0x60,0x70,0x83,0x58,0x07,0x46,0xbf, -0x4f,0xf4,0x40,0x60,0x20,0x83,0xa2,0x61,0x00,0xbf,0x4f,0xf4,0x00,0x60,0x60,0x83, -0x98,0x07,0x46,0xbf,0x4f,0xf4,0x40,0x60,0x20,0x83,0xa2,0x61,0x00,0xbf,0xdb,0x07, -0x4f,0xf4,0x00,0x60,0x48,0xbf,0x4f,0xf4,0x40,0x63,0x70,0x83,0x4c,0xbf,0x23,0x83, -0xa2,0x61,0x00,0xbf,0x4f,0xf4,0x00,0x60,0x60,0x83,0x00,0xbf,0x02,0x31,0xd4,0x29, -0x20,0x83,0x9e,0xd1,0x4f,0xf4,0x80,0x40,0x4f,0xf4,0x00,0x53,0x30,0x83,0x01,0x35, -0x00,0x20,0x33,0x83,0xff,0xf7,0x64,0xfa,0x40,0x2d,0x7f,0xf4,0x75,0xaf,0xbd,0xe8, -0xf0,0x81,0x00,0xbf,0x00,0x0c,0x02,0x40,0x26,0x79,0x00,0x20,0x00,0x08,0x00,0x04, -0x03,0x4b,0x1a,0x88,0x03,0x4b,0xc2,0xf1,0x64,0x02,0x5a,0x63,0x70,0x47,0x00,0xbf, -0x14,0x82,0x00,0x20,0x00,0x44,0x01,0x40,0x01,0x4b,0x00,0x22,0x5a,0x63,0x70,0x47, -0x00,0x44,0x01,0x40,0x03,0x4b,0x18,0x80,0x03,0x4b,0xc0,0xf1,0x64,0x00,0x58,0x63, -0x70,0x47,0x00,0xbf,0x14,0x82,0x00,0x20,0x00,0x44,0x01,0x40,0x73,0xb5,0xff,0xf7, -0xe7,0xfe,0x49,0x4d,0x08,0x20,0x01,0x21,0xfb,0xf7,0x88,0xfa,0x4f,0xf4,0x30,0x53, -0x00,0x24,0x01,0x26,0x00,0x93,0x28,0x46,0x02,0x23,0x69,0x46,0x8d,0xf8,0x04,0x60, -0x8d,0xf8,0x05,0x30,0x8d,0xf8,0x06,0x40,0x8d,0xf8,0x07,0x40,0xfb,0xf7,0xe4,0xfb, -0x4f,0xf4,0xa0,0x43,0x69,0x46,0x8d,0xf8,0x04,0x60,0x8d,0xf8,0x07,0x60,0x28,0x46, -0x4f,0xf4,0x80,0x56,0x00,0x93,0x8d,0xf8,0x06,0x40,0x8d,0xf8,0x05,0x40,0xfb,0xf7, -0xd3,0xfb,0x2e,0x83,0x05,0x20,0xff,0xf7,0x95,0xfe,0x6e,0x83,0x78,0x20,0xff,0xf7, -0x91,0xfe,0x2e,0x83,0x40,0xf6,0xc4,0x15,0x28,0x46,0xff,0xf7,0x8b,0xfe,0xe2,0x20, -0xff,0xf7,0xd6,0xf9,0x28,0x46,0xff,0xf7,0x85,0xfe,0xff,0xf7,0xa9,0xfe,0x25,0x20, -0xff,0xf7,0xce,0xf9,0x2b,0x20,0xff,0xf7,0xcb,0xf9,0xea,0x20,0xff,0xf7,0xc8,0xf9, -0x81,0x20,0xff,0xf7,0xc5,0xf9,0x1e,0x20,0xff,0xf7,0xc2,0xf9,0xa6,0x20,0xff,0xf7, -0xbf,0xf9,0xd1,0x20,0xff,0xf7,0xbc,0xf9,0xd5,0x20,0xff,0xf7,0xb9,0xf9,0xa0,0x20, -0xff,0xf7,0xb6,0xf9,0xc8,0x20,0xff,0xf7,0xb3,0xf9,0x1d,0x20,0xff,0xf7,0xb0,0xf9, -0xf1,0x20,0xff,0xf7,0xad,0xf9,0x3f,0x20,0xff,0xf7,0xaa,0xf9,0x84,0x20,0xff,0xf7, -0xa7,0xf9,0xc4,0x20,0xff,0xf7,0xa4,0xf9,0x89,0x20,0xff,0xf7,0xa1,0xf9,0xf8,0x20, -0xff,0xf7,0x9e,0xf9,0xf4,0x20,0xff,0xf7,0x9b,0xf9,0x20,0x46,0xff,0xf7,0x98,0xf9, -0xf5,0x20,0xff,0xf7,0x95,0xf9,0x60,0x20,0xff,0xf7,0x92,0xf9,0xf6,0x20,0xff,0xf7, -0x8f,0xf9,0x47,0x20,0xff,0xf7,0x8c,0xf9,0xf7,0x20,0xff,0xf7,0x89,0xf9,0x9f,0x20, -0xff,0xf7,0x86,0xf9,0xaf,0x20,0xff,0xf7,0x83,0xf9,0x78,0x20,0xff,0xf7,0x32,0xfe, -0xaf,0x20,0xff,0xf7,0x7d,0xf9,0x7c,0xbd,0x00,0x0c,0x02,0x40,0x10,0xb5,0x04,0x46, -0x81,0x20,0xff,0xf7,0x75,0xf9,0x05,0x34,0xe0,0xb2,0xbd,0xe8,0x10,0x40,0xff,0xf7, -0x6f,0xb9,0x00,0xbf,0x70,0xb5,0x0a,0x4c,0x80,0x26,0x32,0x20,0x40,0x25,0x26,0x83, -0x00,0xf0,0x62,0xfe,0x32,0x20,0x25,0x83,0x00,0xf0,0x5e,0xfe,0x32,0x20,0x66,0x83, -0x00,0xf0,0x5a,0xfe,0x32,0x20,0x65,0x83,0x00,0xf0,0x56,0xfe,0x01,0x20,0x70,0xbd, -0x00,0x04,0x02,0x40,0x70,0xb5,0x0a,0x4c,0x40,0x26,0x32,0x20,0x80,0x25,0x66,0x83, -0x00,0xf0,0x4a,0xfe,0x32,0x20,0x65,0x83,0x00,0xf0,0x46,0xfe,0x32,0x20,0x26,0x83, -0x00,0xf0,0x42,0xfe,0x32,0x20,0x25,0x83,0xbd,0xe8,0x70,0x40,0x00,0xf0,0x3c,0xbe, -0x00,0x04,0x02,0x40,0x38,0xb5,0x0a,0x4c,0x40,0x25,0x32,0x20,0x65,0x83,0x00,0xf0, -0x33,0xfe,0x80,0x23,0x63,0x83,0x32,0x20,0x00,0xf0,0x2e,0xfe,0x32,0x20,0x25,0x83, -0x00,0xf0,0x2a,0xfe,0x32,0x20,0x65,0x83,0xbd,0xe8,0x38,0x40,0x00,0xf0,0x24,0xbe, -0x00,0x04,0x02,0x40,0x38,0xb5,0x0a,0x4c,0x40,0x25,0x32,0x20,0x65,0x83,0x00,0xf0, -0x1b,0xfe,0x80,0x23,0x23,0x83,0x32,0x20,0x00,0xf0,0x16,0xfe,0x32,0x20,0x25,0x83, -0x00,0xf0,0x12,0xfe,0x32,0x20,0x65,0x83,0xbd,0xe8,0x38,0x40,0x00,0xf0,0x0c,0xbe, -0x00,0x04,0x02,0x40,0x38,0xb5,0x12,0x4d,0x40,0x22,0x6a,0x83,0x32,0x20,0x00,0xf0, -0x03,0xfe,0x80,0x23,0x2b,0x83,0x32,0x20,0x00,0xf0,0xfe,0xfd,0x40,0x22,0x2a,0x83, -0x32,0x20,0x00,0xf0,0xf9,0xfd,0x32,0x24,0x2b,0x69,0x1b,0x06,0x07,0xd5,0x01,0x3c, -0x32,0x20,0xa4,0xb2,0x00,0xf0,0xf0,0xfd,0x00,0x2c,0xf5,0xd1,0x00,0xe0,0x02,0x24, -0x03,0x4b,0x40,0x22,0x32,0x20,0x5a,0x83,0x00,0xf0,0xe6,0xfd,0x20,0xb2,0x38,0xbd, -0x00,0x04,0x02,0x40,0x70,0xb5,0x06,0x46,0x09,0x25,0x10,0x4c,0x12,0xe0,0x40,0x22, -0x62,0x83,0x32,0x06,0x02,0xd5,0x80,0x23,0x23,0x83,0x01,0xe0,0x80,0x22,0x62,0x83, -0x32,0x20,0x00,0xf0,0xd1,0xfd,0x40,0x23,0x76,0x00,0x23,0x83,0x32,0x20,0xf6,0xb2, -0x00,0xf0,0xca,0xfd,0x01,0x3d,0xad,0xb2,0x00,0x2d,0xe8,0xd1,0x03,0x4b,0x40,0x22, -0x32,0x20,0x5a,0x83,0xbd,0xe8,0x70,0x40,0x00,0xf0,0xbe,0xbd,0x00,0x04,0x02,0x40, -0x70,0xb5,0x10,0x4d,0x80,0x22,0x2a,0x83,0x09,0x26,0x00,0x24,0x10,0xe0,0x40,0x23, -0x6b,0x83,0x32,0x20,0x00,0xf0,0xb0,0xfd,0x40,0x22,0x32,0x20,0x2a,0x83,0x00,0xf0, -0xab,0xfd,0x2b,0x69,0x64,0x00,0xe4,0xb2,0x19,0x06,0x48,0xbf,0x44,0xf0,0x01,0x04, -0x01,0x3e,0xb6,0xb2,0x00,0x2e,0xea,0xd1,0x02,0x4b,0x40,0x22,0x5a,0x83,0x20,0x46, -0x70,0xbd,0x00,0xbf,0x00,0x04,0x02,0x40,0x38,0xb5,0x02,0x20,0x01,0x21,0xfb,0xf7, -0x15,0xf9,0x0e,0x4b,0x0e,0x4c,0x1a,0x6b,0x4f,0xf4,0x00,0x75,0x42,0xf0,0x02,0x02, -0x1a,0x63,0x1a,0x6b,0x28,0x46,0x42,0xf0,0x10,0x02,0x1a,0x63,0x44,0xf2,0x01,0x11, -0x65,0x83,0x00,0xf0,0x01,0xfa,0xc0,0x20,0x4c,0xf2,0x05,0x11,0x00,0xf0,0xfc,0xf9, -0x80,0x23,0x23,0x83,0x40,0x23,0x23,0x83,0x65,0x83,0x38,0xbd,0x00,0x38,0x02,0x40, -0x00,0x04,0x02,0x40,0x10,0xb5,0x04,0x46,0xff,0xf7,0x04,0xff,0x5c,0x20,0xff,0xf7, -0x89,0xff,0xff,0xf7,0x5f,0xff,0x00,0x20,0xff,0xf7,0x84,0xff,0xff,0xf7,0x5a,0xff, -0x20,0x46,0xff,0xf7,0x7f,0xff,0xff,0xf7,0x55,0xff,0xbd,0xe8,0x10,0x40,0x09,0xe7, -0x10,0xb5,0xff,0xf7,0xef,0xfe,0x5c,0x20,0xff,0xf7,0x74,0xff,0xff,0xf7,0x4a,0xff, -0x00,0x20,0xff,0xf7,0x6f,0xff,0xff,0xf7,0x45,0xff,0xff,0xf7,0xe3,0xfe,0x5d,0x20, -0xff,0xf7,0x68,0xff,0xff,0xf7,0x3e,0xff,0xff,0xf7,0x8a,0xff,0x04,0x46,0xff,0xf7, -0x21,0xff,0xff,0xf7,0xef,0xfe,0x20,0x46,0x10,0xbd,0x38,0xb5,0x0d,0x46,0x04,0x46, -0xff,0xf7,0xd0,0xfe,0xa2,0x20,0xff,0xf7,0x55,0xff,0xff,0xf7,0x2b,0xff,0x28,0x0a, -0xff,0xf7,0x50,0xff,0xff,0xf7,0x26,0xff,0xe8,0xb2,0xff,0xf7,0x4b,0xff,0xff,0xf7, -0x21,0xff,0x20,0x78,0xff,0xf7,0x46,0xff,0xff,0xf7,0x1c,0xff,0xbd,0xe8,0x38,0x40, -0xd0,0xe6,0x70,0xb5,0x0d,0x46,0x16,0x46,0x04,0x46,0xff,0xf7,0xb3,0xfe,0xa2,0x20, -0xff,0xf7,0x38,0xff,0xff,0xf7,0x0e,0xff,0x28,0x0a,0xff,0xf7,0x33,0xff,0xff,0xf7, -0x09,0xff,0xe8,0xb2,0xff,0xf7,0x2e,0xff,0xff,0xf7,0x04,0xff,0xff,0xf7,0xa2,0xfe, -0xa3,0x20,0xff,0xf7,0x27,0xff,0xff,0xf7,0xfd,0xfe,0x11,0xe0,0x01,0x2e,0x07,0xd1, -0xff,0xf7,0x46,0xff,0x20,0x70,0xff,0xf7,0xdd,0xfe,0xff,0xf7,0xab,0xfe,0x05,0xe0, -0xff,0xf7,0x3e,0xff,0x04,0xf8,0x01,0x0b,0xff,0xf7,0xbc,0xfe,0x01,0x3e,0xb6,0xb2, -0x00,0x2e,0xeb,0xd1,0x70,0xbd,0x70,0xb5,0x0d,0x46,0x16,0x46,0x04,0x46,0xff,0xf7, -0x81,0xfe,0xa2,0x20,0xff,0xf7,0x06,0xff,0xff,0xf7,0xdc,0xfe,0x28,0x0a,0xff,0xf7, -0x01,0xff,0xff,0xf7,0xd7,0xfe,0xe8,0xb2,0xff,0xf7,0xfc,0xfe,0xff,0xf7,0xd2,0xfe, -0x07,0xe0,0x14,0xf8,0x01,0x0b,0xff,0xf7,0xf5,0xfe,0xff,0xf7,0xcb,0xfe,0x01,0x3e, -0xf6,0xb2,0x00,0x2e,0xf5,0xd1,0xbd,0xe8,0x70,0x40,0x7b,0xe6,0x08,0xb5,0xff,0xf7, -0x61,0xfe,0xa2,0x20,0xff,0xf7,0xe6,0xfe,0xff,0xf7,0xbc,0xfe,0x00,0x28,0xf6,0xd0, -0xbd,0xe8,0x08,0x40,0x6e,0xe6,0x2d,0xe9,0xf8,0x43,0x5f,0xfa,0x82,0xf9,0x11,0xf0, -0x3f,0x05,0x06,0x46,0x0c,0x46,0xc2,0xf3,0x87,0x18,0x09,0xf0,0x3f,0x07,0x17,0xd1, -0xb8,0xf1,0x00,0x0f,0x4b,0xd0,0x01,0xeb,0x88,0x19,0x1f,0xfa,0x89,0xf9,0x05,0x46, -0x09,0xe0,0x28,0x46,0x21,0x46,0x40,0x22,0xff,0xf7,0xb5,0xff,0xff,0xf7,0xd6,0xff, -0x40,0x34,0xa4,0xb2,0x40,0x35,0x4c,0x45,0xf3,0xd1,0x06,0xeb,0x88,0x10,0x35,0xe0, -0xc5,0xf1,0x40,0x05,0xed,0xb2,0xb8,0xf1,0x00,0x0f,0x0d,0xd1,0xaa,0x42,0x2f,0xd9, -0x2a,0x46,0xff,0xf7,0xa0,0xff,0x2c,0x19,0xff,0xf7,0xc0,0xff,0x70,0x19,0xc5,0xeb, -0x09,0x05,0xa1,0xb2,0xea,0xb2,0x24,0xe0,0x57,0x1b,0xbf,0xb2,0x2c,0x19,0xc7,0xf3, -0x87,0x18,0xa4,0xb2,0x2a,0x46,0x75,0x19,0x04,0xeb,0x88,0x16,0xff,0xf7,0x8b,0xff, -0x07,0xf0,0x3f,0x07,0xff,0xf7,0xaa,0xff,0xb6,0xb2,0xa9,0x46,0x0a,0xe0,0x48,0x46, -0x21,0x46,0x40,0x22,0xff,0xf7,0x7f,0xff,0xff,0xf7,0xa0,0xff,0x40,0x34,0xa4,0xb2, -0x09,0xf1,0x40,0x09,0xb4,0x42,0xf2,0xd1,0x05,0xeb,0x88,0x10,0x37,0xb1,0x21,0x46, -0x3a,0x46,0xff,0xf7,0x70,0xff,0xbd,0xe8,0xf8,0x43,0x8f,0xe7,0xbd,0xe8,0xf8,0x83, -0x01,0x4b,0x18,0x70,0x70,0x47,0x00,0xbf,0x18,0x82,0x00,0x20,0x02,0x4b,0x00,0x22, -0x18,0x78,0x1a,0x70,0x70,0x47,0x00,0xbf,0x18,0x82,0x00,0x20,0x30,0xb5,0x04,0x78, -0x63,0x00,0x03,0xf0,0x0e,0x03,0x63,0xf3,0x03,0x04,0x04,0x70,0x29,0xb1,0x43,0xf0, -0x01,0x01,0xe3,0xb2,0x61,0xf3,0x03,0x03,0x03,0x70,0x41,0x78,0x83,0x78,0x01,0x31, -0xc9,0xb2,0x41,0x70,0xa3,0xb1,0x04,0x78,0x14,0xf0,0x0f,0x0f,0x10,0xd1,0x63,0x2b, -0x0b,0xd0,0x33,0x4c,0x42,0xf0,0x20,0x05,0x10,0x2b,0x25,0x70,0x01,0xd1,0x0f,0x29, -0x03,0xd9,0x03,0x78,0x6f,0xf3,0x05,0x13,0x03,0x70,0x00,0x23,0x43,0x70,0x83,0x70, -0x83,0x78,0x08,0x2b,0x3a,0xd0,0x06,0xd8,0x01,0x2b,0x3e,0xd0,0x0e,0xd3,0x02,0x2b, -0x34,0xd0,0x04,0x2b,0x03,0xe0,0x5f,0x2b,0x23,0xd0,0x02,0xd8,0x10,0x2b,0x45,0xd1, -0x2c,0xe0,0x61,0x2b,0x10,0xd0,0x62,0x2b,0x40,0xd1,0x38,0xe0,0x03,0x78,0x03,0xf0, -0x0f,0x02,0x0f,0x2a,0x3a,0xd1,0x61,0x22,0x82,0x70,0x42,0x78,0x10,0x2a,0x84,0xbf, -0x6f,0xf3,0x05,0x13,0x03,0x70,0x16,0xe0,0x19,0x4b,0x42,0xf0,0x60,0x02,0x1a,0x70, -0x03,0x78,0xc3,0xf3,0x01,0x12,0x01,0x32,0x62,0xf3,0x05,0x13,0x03,0x70,0x5f,0x23, -0x08,0xe0,0x43,0x78,0x20,0x2b,0x08,0xbf,0x62,0xf0,0x7f,0x02,0x14,0xd0,0x28,0x2b, -0x1c,0xd1,0x10,0x23,0x83,0x70,0x00,0x23,0x43,0x70,0x30,0xbd,0x41,0x78,0x2f,0x29, -0x03,0xd9,0x5b,0x10,0x83,0x70,0x00,0x23,0x43,0x70,0x81,0x78,0x43,0x78,0x01,0x39, -0x19,0x42,0x0b,0xd1,0x42,0xf0,0x40,0x02,0x05,0x4b,0x1a,0x70,0x30,0xbd,0x43,0x78, -0x3f,0x2b,0x03,0xd9,0x08,0x23,0x83,0x70,0x00,0x23,0x43,0x70,0x30,0xbd,0x00,0xbf, -0x18,0x82,0x00,0x20,0x00,0xf0,0x0f,0x03,0x0f,0x2b,0x07,0xd0,0x04,0x4a,0x03,0x20, -0x00,0xfb,0x03,0x20,0x62,0x23,0x83,0x70,0x00,0x23,0x43,0x70,0x70,0x47,0x00,0xbf, -0x19,0x82,0x00,0x20,0x00,0xf0,0x0f,0x00,0x0f,0x28,0x09,0xd0,0x03,0x22,0x50,0x43, -0x04,0x4b,0x63,0x21,0x1a,0x18,0x91,0x70,0x1a,0x5c,0x6f,0xf3,0x05,0x12,0x1a,0x54, -0x70,0x47,0x00,0xbf,0x19,0x82,0x00,0x20,0x2d,0xe9,0xf0,0x41,0x11,0x4f,0x03,0x26, -0x97,0xf8,0x2e,0x30,0x01,0x25,0x01,0x33,0xdb,0xb2,0x87,0xf8,0x2e,0x30,0x00,0xf0, -0xc3,0xf8,0x6f,0xea,0x00,0x08,0x5f,0xfa,0x88,0xf8,0x00,0x22,0x01,0x37,0x00,0xe0, -0x22,0x46,0x54,0x1c,0x15,0xfa,0x04,0xf3,0x13,0xea,0x08,0x0f,0x06,0xfb,0x02,0x70, -0x0c,0xbf,0x00,0x21,0x01,0x21,0xd2,0xb2,0xff,0xf7,0x38,0xff,0x06,0x2c,0xef,0xd1, -0xbd,0xe8,0xf0,0x81,0x18,0x82,0x00,0x20,0x2d,0xe9,0xf0,0x4f,0xc1,0xf3,0x02,0x23, -0x03,0x27,0x01,0xea,0x07,0x06,0x9b,0x02,0x85,0xb0,0xc1,0xf3,0x03,0x12,0x75,0x1e, -0x03,0xf1,0x80,0x43,0xc1,0xf3,0x41,0x38,0xc1,0xf3,0x81,0x0b,0x01,0x24,0x09,0xb2, -0x01,0x92,0x02,0x95,0x03,0xf5,0x00,0x33,0x00,0x22,0x25,0x46,0x03,0x91,0x00,0x90, -0xdd,0xf8,0x00,0xa0,0x14,0xea,0x0a,0x0f,0x6b,0xd0,0x51,0x00,0x07,0xfa,0x01,0xf9, -0xd3,0xf8,0x00,0xc0,0x2c,0xea,0x09,0x0c,0x06,0xfa,0x01,0xf9,0xc3,0xf8,0x00,0xc0, -0xd3,0xf8,0x00,0xc0,0x49,0xea,0x0c,0x0c,0xc3,0xf8,0x00,0xc0,0xdd,0xf8,0x08,0xc0, -0xbc,0xf1,0x01,0x0f,0x29,0xd8,0x6f,0xf0,0x03,0x00,0x00,0xfa,0x01,0xf9,0xd3,0xf8, -0x08,0xc0,0xdd,0xf8,0x0c,0xa0,0x09,0xea,0x0c,0x0c,0x08,0xfa,0x01,0xf9,0xc3,0xf8, -0x08,0xc0,0xd3,0xf8,0x08,0xc0,0xba,0xf1,0x00,0x0f,0x49,0xea,0x0c,0x0c,0x1f,0xfa, -0x82,0xf9,0x05,0xfa,0x09,0xf9,0xc3,0xf8,0x08,0xc0,0xd3,0xf8,0x04,0xc0,0x2c,0xea, -0x09,0x0c,0xb8,0xbf,0x05,0xfa,0x02,0xf9,0xc3,0xf8,0x04,0xc0,0xbe,0xbf,0xd3,0xf8, -0x04,0xc0,0x49,0xea,0x0c,0x0c,0xc3,0xf8,0x04,0xc0,0x1f,0xfa,0x82,0xf9,0x4f,0xea, -0x49,0x09,0x07,0xfa,0x09,0xf9,0x0b,0xfa,0x01,0xf1,0xd3,0xf8,0x0c,0xc0,0x0f,0x20, -0x2c,0xea,0x09,0x0c,0xc3,0xf8,0x0c,0xc0,0xd3,0xf8,0x0c,0xc0,0x41,0xea,0x0c,0x01, -0x02,0xf0,0x07,0x0c,0x4f,0xea,0x8c,0x0c,0x00,0xfa,0x0c,0xf9,0xd9,0x60,0xd1,0x08, -0x08,0x31,0x53,0xf8,0x21,0xa0,0x2a,0xea,0x09,0x09,0xdd,0xf8,0x04,0xa0,0x43,0xf8, -0x21,0x90,0x0a,0xfa,0x0c,0xfc,0x53,0xf8,0x21,0x90,0x4c,0xea,0x09,0x0c,0x43,0xf8, -0x21,0xc0,0x01,0x32,0x64,0x00,0x10,0x2a,0x8a,0xd1,0x05,0xb0,0xbd,0xe8,0xf0,0x8f, -0x08,0xb5,0x08,0x4b,0x4f,0xf4,0xe0,0x50,0x1a,0x6b,0x40,0xf2,0x04,0x41,0x42,0xf0, -0x10,0x02,0x1a,0x63,0xff,0xf7,0x60,0xff,0x8c,0x20,0x4f,0xf4,0x41,0x71,0xbd,0xe8, -0x08,0x40,0x59,0xe7,0x00,0x38,0x02,0x40,0x0e,0x4b,0x1b,0x69,0x13,0xf0,0x80,0x00, -0x18,0xbf,0x10,0x20,0x1a,0x07,0x48,0xbf,0x40,0xf0,0x40,0x00,0x5b,0x07,0x0a,0x4b, -0x48,0xbf,0x40,0xf0,0x08,0x00,0x1b,0x69,0x59,0x05,0x48,0xbf,0x40,0xf0,0x02,0x00, -0x1a,0x05,0x48,0xbf,0x40,0xf0,0x20,0x00,0xdb,0x04,0x48,0xbf,0x40,0xf0,0x04,0x00, -0x70,0x47,0x00,0xbf,0x00,0x0c,0x02,0x40,0x00,0x10,0x02,0x40,0x08,0xb5,0x0e,0x4b, -0x20,0x20,0x1a,0x6b,0x04,0x21,0x42,0xf0,0x01,0x02,0x1a,0x63,0x1a,0x6b,0x42,0xf0, -0x02,0x02,0x1a,0x63,0x1a,0x6b,0x42,0xf0,0x10,0x02,0x1a,0x63,0xff,0xf7,0x24,0xff, -0x3a,0x20,0x4f,0xf4,0x82,0x71,0xff,0xf7,0x1f,0xff,0x4e,0xf2,0x07,0x30,0x40,0xf2, -0x04,0x41,0xbd,0xe8,0x08,0x40,0x17,0xe7,0x00,0x38,0x02,0x40,0x10,0xb5,0x46,0x4b, -0x0e,0x28,0x19,0x69,0xd3,0xf8,0x10,0x24,0x03,0xf5,0x80,0x53,0x1b,0x69,0x0b,0xd8, -0x03,0x23,0x58,0x43,0x41,0x4b,0xc0,0x5c,0x00,0xf0,0x0f,0x00,0xa0,0xf1,0x0f,0x01, -0x48,0x42,0x40,0xeb,0x01,0x00,0x10,0xbd,0x0f,0x38,0x15,0x28,0x71,0xd8,0xdf,0xe8, -0x00,0xf0,0x0b,0x10,0x17,0x19,0x1d,0x24,0x26,0x2a,0x33,0x37,0x3b,0x42,0x46,0x4a, -0x4e,0x52,0x55,0x59,0x5d,0x62,0x66,0x69,0x03,0xf0,0x01,0x00,0x80,0xf0,0x01,0x00, -0x5b,0xe0,0x02,0xf0,0x20,0x00,0x03,0xf0,0x01,0x03,0x18,0x43,0x21,0x28,0x08,0xe0, -0xd0,0x43,0x0d,0xe0,0xd8,0x43,0x00,0xf0,0x04,0x00,0x4e,0xe0,0x03,0xf0,0x06,0x00, -0x06,0x28,0x14,0xbf,0x00,0x20,0x01,0x20,0x47,0xe0,0xd8,0x43,0x11,0xe0,0xc8,0x43, -0x00,0xf0,0x20,0x00,0x41,0xe0,0x03,0xf4,0x00,0x40,0x01,0xf0,0x20,0x01,0x08,0x43, -0x48,0xf2,0x20,0x02,0x90,0x42,0xec,0xe7,0xd8,0x43,0x00,0xf4,0x00,0x40,0x34,0xe0, -0xd0,0x43,0x00,0xf0,0x02,0x00,0x30,0xe0,0x03,0xf0,0x80,0x00,0x02,0xf0,0x02,0x02, -0x10,0x43,0x82,0x28,0xdd,0xe7,0xd8,0x43,0x00,0xf0,0x80,0x00,0x25,0xe0,0xd0,0x43, -0x00,0xf0,0x10,0x00,0x21,0xe0,0x02,0xf0,0x18,0x00,0x18,0x28,0xd1,0xe7,0xd0,0x43, -0x00,0xf0,0x08,0x00,0x19,0xe0,0x03,0xf4,0x80,0x40,0x16,0xe0,0xd8,0x43,0x00,0xf4, -0x80,0x40,0x12,0xe0,0xd8,0x43,0x00,0xf4,0x00,0x70,0x0e,0xe0,0x03,0xf4,0x40,0x70, -0xb0,0xf5,0x40,0x7f,0xbd,0xe7,0xd8,0x43,0x00,0xf4,0x80,0x70,0x05,0xe0,0x03,0xf4, -0x00,0x50,0x02,0xe0,0xd8,0x43,0x00,0xf4,0x00,0x50,0x00,0x30,0x18,0xbf,0x01,0x20, -0x10,0xbd,0x00,0x20,0x10,0xbd,0x00,0xbf,0x00,0x00,0x02,0x40,0x19,0x82,0x00,0x20, -0x03,0x23,0x58,0x43,0x10,0xb5,0x00,0xf1,0x0f,0x04,0x1e,0x2c,0x88,0xbf,0x00,0xf1, -0x0e,0x04,0xe0,0xb2,0xff,0xf7,0x62,0xff,0x90,0xb9,0x01,0x34,0xe0,0xb2,0xff,0xf7, -0x5d,0xff,0x78,0xb1,0xb4,0xf1,0x1f,0x00,0x18,0xbf,0x01,0x20,0x24,0x2c,0x0c,0xbf, -0x00,0x24,0x00,0xf0,0x01,0x04,0x00,0x2c,0x14,0xbf,0x01,0x20,0x02,0x20,0x10,0xbd, -0x00,0x20,0x10,0xbd,0x02,0x20,0x10,0xbd,0x7f,0x28,0x15,0xd9,0x0b,0x4b,0x31,0xb1, -0xff,0x28,0x10,0xd8,0x0a,0x4b,0x80,0x38,0x33,0xf8,0x10,0x00,0x70,0x47,0x33,0xf8, -0x02,0x2f,0x82,0x42,0x03,0xd0,0x01,0x31,0x89,0xb2,0x80,0x29,0xf7,0xd1,0x01,0xf1, -0x80,0x00,0xc0,0xb2,0x70,0x47,0x00,0x20,0x70,0x47,0x00,0xbf,0x4c,0x6b,0x00,0x20, -0x4e,0x6b,0x00,0x20,0x07,0x4a,0x00,0x23,0x32,0xf8,0x02,0x1f,0x49,0xb1,0x88,0x42, -0x05,0xd1,0x05,0x4a,0x02,0xeb,0x43,0x03,0xb3,0xf8,0xe0,0x02,0x70,0x47,0x01,0x33, -0xf2,0xe7,0x70,0x47,0x4c,0x6c,0x00,0x20,0x4e,0x6b,0x00,0x20,0x70,0x47,0x70,0x47, -0x70,0x47,0x70,0x47,0x70,0x47,0x70,0x47,0x70,0x47,0x00,0x00,0x00,0x20,0x70,0x47, -0x01,0x20,0x70,0x47,0x13,0xb5,0x31,0x23,0x00,0x24,0x8d,0xf8,0x04,0x30,0x01,0xa8, -0x01,0x23,0x8d,0xf8,0x05,0x40,0x8d,0xf8,0x06,0x40,0x8d,0xf8,0x07,0x30,0xfb,0xf7, -0xa7,0xf8,0x20,0x46,0x1c,0xbd,0x01,0x28,0x08,0xb5,0x06,0xd0,0xfe,0xf7,0x2c,0xfe, -0x00,0x28,0x14,0xbf,0xff,0x20,0x00,0x20,0x00,0xe0,0x00,0x20,0x40,0xb2,0x08,0xbd, -0x01,0x28,0xf8,0xb5,0x0e,0x46,0x14,0x46,0x05,0xd1,0x4f,0xf4,0x00,0x73,0x13,0x60, -0x40,0xf2,0x43,0x43,0x12,0xe0,0xfe,0xf7,0x17,0xfe,0x90,0xb9,0x4f,0xf4,0x00,0x73, -0x23,0x60,0x09,0x4c,0x25,0x68,0x27,0x46,0x3d,0xb9,0x28,0x46,0x01,0x21,0x22,0x46, -0xfe,0xf7,0x9c,0xff,0x08,0xb1,0x25,0x60,0x03,0xe0,0x3b,0x68,0x33,0x60,0x00,0x20, -0x00,0xe0,0xff,0x20,0x40,0xb2,0xf8,0xbd,0x4c,0x82,0x00,0x20,0xf8,0xb5,0x05,0x46, -0x0c,0x46,0x16,0x46,0x40,0xf2,0x82,0x47,0x27,0xe0,0x28,0x46,0x15,0x49,0xd4,0xb1, -0x01,0x2c,0x04,0xbf,0x28,0x46,0x14,0x49,0x15,0xd0,0x02,0x2c,0x04,0xbf,0x28,0x46, -0x12,0x49,0x10,0xd0,0x42,0x2c,0x08,0xd8,0xe1,0x1e,0x49,0x02,0x89,0xb2,0x28,0x46, -0x4f,0xf4,0x00,0x72,0xff,0xf7,0x1d,0xfc,0x09,0xe0,0xbc,0x42,0x07,0xd8,0x0c,0x49, -0x63,0x02,0x59,0x18,0x28,0x46,0x4f,0xf4,0x00,0x72,0x00,0xf0,0x37,0xfb,0x01,0x34, -0x01,0x3e,0x05,0xf5,0x00,0x75,0xa4,0xb2,0xb6,0xb2,0x00,0x2e,0xd5,0xd1,0x30,0x46, -0xf8,0xbd,0x00,0xbf,0x10,0x70,0x00,0x20,0x10,0x72,0x00,0x20,0x10,0x74,0x00,0x20, -0x00,0x7a,0xff,0x07,0x10,0xb5,0x04,0x46,0x01,0x2c,0x08,0x46,0x04,0xd1,0x91,0xb2, -0x1a,0x46,0xff,0xf7,0xbb,0xff,0x03,0xe0,0x11,0x46,0x1a,0x46,0xfe,0xf7,0x5e,0xfe, -0x00,0x28,0x14,0xbf,0xff,0x20,0x00,0x20,0x40,0xb2,0x10,0xbd,0x02,0x29,0x2d,0xe9, -0xf0,0x47,0x05,0x46,0x0c,0x46,0x16,0x46,0x5f,0xd9,0x42,0x29,0x35,0xd8,0x2d,0xe0, -0x7b,0x68,0xd3,0xf1,0x01,0x03,0x38,0xbf,0x00,0x23,0x03,0x2c,0x14,0xbf,0x00,0x23, -0x03,0xf0,0x01,0x03,0x3b,0xb1,0x6b,0x78,0x80,0x2b,0x04,0xd1,0xeb,0x78,0x80,0x2b, -0x08,0xbf,0xc7,0xf8,0x04,0x80,0xd9,0xf8,0x04,0x10,0x59,0xb1,0x8c,0x42,0x09,0xdb, -0x61,0x1a,0x3f,0x29,0x06,0xdc,0x49,0x02,0x89,0xb2,0x28,0x46,0x4f,0xf4,0x00,0x72, -0xff,0xf7,0x21,0xfc,0x01,0x34,0x7b,0x68,0xa4,0xb2,0xe3,0x1a,0x01,0x3e,0x3f,0x2b, -0x05,0xf5,0x00,0x75,0x06,0xdd,0x00,0x23,0x7b,0x60,0x03,0xe0,0x18,0x4f,0x4f,0xf0, -0x03,0x08,0xb9,0x46,0x00,0x2e,0xcb,0xd1,0x27,0xe0,0x40,0xf2,0x82,0x43,0x99,0x42, -0x23,0xd8,0x14,0x4f,0x4c,0x02,0xdf,0xf8,0x50,0x90,0xe7,0x19,0xdf,0xf8,0x4c,0x80, -0x07,0xf5,0x80,0x74,0xca,0x46,0xc6,0xb1,0x4f,0x45,0x05,0xd9,0x47,0x45,0x03,0xd8, -0x38,0x46,0x29,0x46,0x00,0xf0,0x06,0xf9,0x54,0x45,0x06,0xd9,0x44,0x45,0x04,0xd8, -0x05,0xf5,0x80,0x71,0x20,0x46,0x00,0xf0,0xfd,0xf8,0x07,0xf5,0x00,0x77,0x05,0xf5, -0x00,0x75,0x01,0x3e,0x04,0xf5,0x00,0x74,0xe5,0xe7,0x00,0x20,0xbd,0xe8,0xf0,0x87, -0x4c,0x82,0x00,0x20,0x00,0x7a,0xff,0x07,0xff,0x7f,0x00,0x08,0xff,0xfe,0x07,0x08, -0x10,0xb5,0x04,0x46,0x01,0x2c,0x08,0x46,0x04,0xd1,0x91,0xb2,0x1a,0x46,0xff,0xf7, -0x85,0xff,0x03,0xe0,0x11,0x46,0x1a,0x46,0xfe,0xf7,0x40,0xfe,0x00,0x28,0x14,0xbf, -0xff,0x20,0x00,0x20,0x40,0xb2,0x10,0xbd,0x01,0x48,0xfb,0xf7,0xc9,0xbd,0x00,0xbf, -0x58,0x82,0x00,0x20,0x03,0x68,0x9b,0x0c,0x9b,0x04,0xb3,0xf1,0x00,0x5f,0x0e,0xd1, -0x43,0x68,0x1b,0x0d,0x1b,0x05,0xb3,0xf1,0x00,0x6f,0x0a,0xd1,0x80,0x68,0x00,0x0d, -0x00,0x05,0xa0,0xf1,0x00,0x63,0x58,0x42,0x40,0xeb,0x03,0x00,0x70,0x47,0x00,0x20, -0x70,0x47,0x00,0x20,0x70,0x47,0x04,0x4b,0x93,0xf8,0xf4,0x25,0x42,0xf0,0x01,0x02, -0x83,0xf8,0xf4,0x25,0xff,0xf7,0xb8,0xbc,0x58,0x82,0x00,0x20,0x12,0x4b,0x13,0x49, -0x1a,0x6c,0x42,0xf4,0x80,0x72,0x1a,0x64,0xa3,0xf5,0x06,0x33,0x42,0xf2,0x0f,0x72, -0xda,0x62,0x0f,0x4a,0x09,0x68,0x12,0x68,0x4a,0x43,0x0e,0x49,0xb2,0xfb,0xf1,0xf2, -0x01,0x3a,0x92,0xb2,0x1a,0x85,0x00,0x22,0x1a,0x84,0x1a,0x83,0x9a,0x82,0x05,0x22, -0x1a,0x80,0x9a,0x89,0x92,0xb2,0x42,0xf0,0x01,0x02,0x9a,0x81,0x06,0x4b,0x4f,0xf4, -0x00,0x52,0x5a,0x60,0x70,0x47,0x00,0xbf,0x00,0x38,0x02,0x40,0x70,0x9f,0x00,0x20, -0x74,0x9f,0x00,0x20,0x40,0x42,0x0f,0x00,0x00,0xe1,0x00,0xe0,0x03,0x4a,0x13,0x8a, -0x23,0xf0,0x01,0x03,0x1b,0x04,0x1b,0x0c,0x13,0x82,0xbc,0xe7,0x00,0x20,0x00,0x40, -0x0d,0x4b,0x0e,0x49,0x1a,0x6c,0x42,0xf0,0x80,0x02,0x1a,0x64,0xa3,0xf5,0x07,0x33, -0x4f,0xf6,0xff,0x72,0xda,0x62,0x0a,0x4a,0x09,0x68,0x12,0x68,0x4a,0x43,0x09,0x49, -0xb2,0xfb,0xf1,0xf2,0x01,0x3a,0x92,0xb2,0x1a,0x85,0x00,0x22,0x1a,0x84,0x1a,0x83, -0x9a,0x82,0x01,0x22,0x1a,0x80,0x70,0x47,0x00,0x38,0x02,0x40,0x70,0x9f,0x00,0x20, -0x74,0x9f,0x00,0x20,0x80,0x96,0x98,0x00,0x04,0x4b,0x00,0x22,0x5a,0x62,0x01,0x22, -0x9a,0x82,0x5a,0x6a,0x82,0x42,0xfc,0xd3,0x70,0x47,0x00,0xbf,0x00,0x1c,0x00,0x40, -0x03,0x4b,0x04,0x4a,0x5a,0x60,0x02,0xf1,0x88,0x32,0x5a,0x60,0x70,0x47,0x00,0xbf, -0x00,0x3c,0x02,0x40,0x23,0x01,0x67,0x45,0x04,0x49,0x05,0x4a,0x4a,0xf6,0xaa,0x23, -0x00,0xe0,0x13,0x60,0xc8,0x68,0xc0,0x03,0xfb,0xd4,0x70,0x47,0x00,0x3c,0x02,0x40, -0x00,0x30,0x00,0x40,0x38,0xb5,0x12,0x4c,0x05,0x46,0xff,0xf7,0xed,0xff,0x23,0x69, -0x23,0xf4,0x40,0x73,0x23,0x61,0x23,0x69,0x43,0xf4,0x00,0x73,0x23,0x61,0x23,0x69, -0x23,0xf0,0xf8,0x03,0x23,0x61,0x23,0x69,0x43,0xf0,0x02,0x03,0x43,0xea,0xc5,0x05, -0x25,0x61,0x23,0x69,0x43,0xf4,0x80,0x33,0x23,0x61,0xff,0xf7,0xd5,0xff,0x23,0x69, -0x23,0xf0,0x02,0x03,0x23,0x61,0x23,0x69,0x23,0xf0,0xf8,0x03,0x23,0x61,0x38,0xbd, -0x00,0x3c,0x02,0x40,0xf8,0xb5,0x2d,0x4b,0x04,0x46,0x98,0x42,0x0d,0x46,0x07,0xd1, -0x08,0x46,0xff,0xf7,0x27,0xff,0x2a,0x4b,0x00,0x22,0x00,0xb9,0x01,0x22,0x1a,0x60, -0x27,0x4b,0x1b,0x68,0x00,0x2b,0x44,0xd1,0x24,0x4b,0x9c,0x42,0x03,0xd1,0x02,0x20, -0xff,0xf7,0xc0,0xff,0x0d,0xe0,0x23,0x4b,0x9c,0x42,0x03,0xd1,0x03,0x20,0xff,0xf7, -0xb9,0xff,0x0a,0xe0,0x20,0x4b,0x9c,0x42,0x03,0xd1,0x04,0x20,0xff,0xf7,0xb2,0xff, -0x07,0xe0,0x1e,0x4b,0x05,0x20,0x9c,0x42,0x07,0xd0,0x1d,0x4b,0x06,0x20,0x9c,0x42, -0x03,0xd0,0x1c,0x4b,0x9c,0x42,0x02,0xd1,0x07,0x20,0xff,0xf7,0xa3,0xff,0x1a,0x4e, -0x00,0x27,0xff,0xf7,0x91,0xff,0x33,0x69,0x23,0xf4,0x40,0x73,0x33,0x61,0x33,0x69, -0x43,0xf4,0x00,0x73,0x33,0x61,0x33,0x69,0x43,0xf0,0x01,0x03,0x33,0x61,0xeb,0x59, -0xe3,0x51,0xff,0xf7,0x81,0xff,0x33,0x69,0x23,0xf0,0x01,0x03,0x33,0x61,0xe2,0x59, -0xeb,0x59,0x9a,0x42,0x07,0xd1,0x04,0x37,0xb7,0xf5,0x80,0x7f,0xe1,0xd1,0x00,0x20, -0xf8,0xbd,0x01,0x20,0xf8,0xbd,0x02,0x20,0xf8,0xbd,0x00,0xbf,0x00,0x80,0x00,0x08, -0x10,0x79,0x00,0x20,0x00,0xc0,0x00,0x08,0x00,0x00,0x01,0x08,0x00,0x00,0x02,0x08, -0x00,0x00,0x04,0x08,0x00,0x00,0x06,0x08,0x00,0x3c,0x02,0x40,0x00,0xe0,0x18,0x46, -0x11,0xf8,0x01,0x2b,0x03,0x46,0x03,0xf8,0x01,0x2b,0x00,0x2a,0xf7,0xd1,0x70,0x47, -0x2d,0xe9,0xf0,0x41,0x07,0x46,0x0c,0x46,0x01,0xf1,0x09,0x06,0x38,0x46,0x21,0x46, -0xfe,0xf7,0x07,0xfa,0x05,0x46,0x00,0x28,0x40,0xd1,0x63,0x7a,0x00,0x2b,0x3d,0xd0, -0xa0,0x69,0x03,0x78,0x13,0xb9,0x31,0x46,0xff,0xf7,0xe0,0xff,0xd4,0xf8,0x18,0x80, -0x40,0x46,0x00,0xf0,0xaf,0xf9,0x03,0x1f,0x18,0xf8,0x03,0x20,0x80,0x44,0xdb,0x0f, -0x2e,0x2a,0x18,0xf8,0x03,0x2c,0x18,0xbf,0x01,0x23,0xb2,0xf1,0x62,0x01,0x18,0xbf, -0x01,0x21,0x42,0x2a,0x0c,0xbf,0x00,0x22,0x01,0xf0,0x01,0x02,0x00,0x2a,0x18,0xbf, -0x01,0x23,0x18,0xf8,0x02,0x2c,0xb2,0xf1,0x69,0x01,0x18,0xbf,0x01,0x21,0x49,0x2a, -0x0c,0xbf,0x00,0x22,0x01,0xf0,0x01,0x02,0x00,0x2a,0x18,0xbf,0x01,0x23,0x18,0xf8, -0x01,0x2c,0xb2,0xf1,0x6e,0x01,0x18,0xbf,0x01,0x21,0x4e,0x2a,0x0c,0xbf,0x00,0x22, -0x01,0xf0,0x01,0x02,0x00,0x2a,0xb9,0xd1,0x00,0x2b,0xb7,0xd1,0x28,0x46,0xbd,0xe8, -0xf0,0x81,0x2d,0xe9,0xf0,0x41,0x24,0x4c,0x00,0x21,0x04,0xf5,0xc3,0x63,0xc4,0xf8, -0x10,0x36,0x30,0x23,0xc4,0xf8,0x14,0x36,0x06,0x46,0x04,0xf5,0x20,0x60,0xfe,0xf7, -0xb0,0xf9,0x04,0xf5,0xbf,0x61,0x04,0xf5,0x20,0x60,0xfe,0xf7,0xaa,0xf9,0x04,0xf5, -0x20,0x60,0x04,0xf5,0xbf,0x61,0xfe,0xf7,0xa4,0xf9,0x00,0x25,0x17,0x48,0xa0,0xf5, -0x81,0x61,0xff,0xf7,0x8d,0xff,0xd4,0xf8,0xf8,0x35,0x04,0x28,0xc4,0xf8,0x24,0x3a, -0x1d,0xd0,0x01,0x35,0xb5,0x42,0xf1,0xd9,0x0f,0x4d,0x11,0x4e,0x01,0x24,0x05,0xf5, -0xc3,0x68,0x32,0x27,0x07,0xfb,0x04,0x83,0x0c,0x48,0xc5,0xf8,0x10,0x36,0xa0,0xf5, -0x81,0x61,0xff,0xf7,0x75,0xff,0xd5,0xf8,0xf8,0x35,0x46,0xf8,0x04,0x3f,0x38,0xb9, -0x95,0xf8,0x01,0x36,0x23,0xb1,0x01,0x34,0x07,0x2c,0xeb,0xd1,0x00,0xe0,0x00,0x24, -0x20,0x46,0xbd,0xe8,0xf0,0x81,0x00,0xbf,0x58,0x82,0x00,0x20,0x58,0x8c,0x00,0x20, -0x7c,0x8c,0x00,0x20,0x70,0xb5,0x12,0x4d,0x12,0x4c,0x06,0x46,0x12,0x49,0x28,0x46, -0xff,0xf7,0x4c,0xff,0x04,0xf5,0xc3,0x63,0x32,0x21,0x01,0xfb,0x06,0x31,0x04,0xf5, -0x2b,0x64,0xff,0xf7,0x43,0xff,0x01,0x22,0x29,0x46,0x20,0x46,0xfd,0xf7,0x10,0xff, -0x20,0x46,0x4f,0xf4,0x00,0x41,0xfe,0xf7,0xbd,0xf8,0x08,0x4b,0x20,0x46,0x04,0xf1, -0x1c,0x01,0x4f,0xf4,0x80,0x52,0xbd,0xe8,0x70,0x40,0xfd,0xf7,0x42,0xbf,0x00,0xbf, -0xcc,0x8c,0x00,0x20,0x58,0x82,0x00,0x20,0xaf,0x76,0x00,0x20,0x24,0x9d,0x00,0x20, -0x70,0xb5,0x2d,0x4d,0x04,0x46,0xfd,0xf7,0x1b,0xf9,0x00,0x20,0x2b,0x49,0xfc,0xf7, -0x8f,0xff,0xd5,0xf8,0xd8,0x39,0x7b,0xb9,0x20,0x46,0xff,0xf7,0xc3,0xff,0x28,0x48, -0xfd,0xf7,0xb3,0xff,0x01,0x23,0x27,0x48,0xc5,0xf8,0xd8,0x39,0xff,0xf7,0xd2,0xfd, -0x10,0xb9,0x02,0x23,0xc5,0xf8,0xd8,0x39,0x1f,0x4d,0xd5,0xf8,0xd8,0x39,0x02,0x2b, -0x0e,0xd1,0x18,0x20,0x20,0x49,0xfc,0xf7,0x73,0xff,0x30,0x20,0x1f,0x49,0xfc,0xf7, -0x6f,0xff,0xff,0xf7,0xeb,0xf9,0x82,0x28,0x14,0xbf,0x04,0x20,0x03,0x20,0x70,0xbd, -0x1b,0x4e,0x32,0x22,0x06,0xf5,0xc3,0x63,0x02,0xfb,0x04,0x32,0x00,0x20,0x15,0x23, -0x10,0x21,0xfc,0xf7,0x4a,0xff,0x28,0x20,0x16,0x49,0xfc,0xf7,0x59,0xff,0x30,0x20, -0x15,0x49,0xfc,0xf7,0x55,0xff,0xff,0xf7,0xd1,0xf9,0x83,0x28,0x0d,0xd1,0x20,0x46, -0xff,0xf7,0x88,0xff,0x06,0xeb,0x84,0x04,0xd4,0xf8,0x24,0x3a,0x00,0x28,0x0c,0xbf, -0x02,0x20,0x04,0x20,0xc5,0xf8,0xdc,0x39,0x70,0xbd,0xa0,0xf1,0x82,0x0c,0xdc,0xf1, -0x00,0x00,0x40,0xeb,0x0c,0x00,0x70,0xbd,0x50,0x93,0x00,0x20,0xba,0x76,0x00,0x20, -0x08,0x8d,0x00,0x20,0x24,0x8d,0x00,0x20,0xc6,0x76,0x00,0x20,0xdb,0x76,0x00,0x20, -0x58,0x82,0x00,0x20,0xe3,0x76,0x00,0x20,0xeb,0x76,0x00,0x20,0x0f,0x2a,0xf0,0xb4, -0x98,0xbf,0x03,0x46,0x31,0xd9,0x41,0xea,0x00,0x03,0x9b,0x07,0x36,0xd1,0x0c,0x46, -0x03,0x46,0x15,0x46,0x26,0x68,0x10,0x3d,0x1e,0x60,0x66,0x68,0x5e,0x60,0xa6,0x68, -0x9e,0x60,0xe6,0x68,0x10,0x34,0xde,0x60,0x10,0x33,0x0f,0x2d,0xf2,0xd8,0xa2,0xf1, -0x10,0x04,0x02,0xf0,0x0f,0x02,0x24,0xf0,0x0f,0x04,0x10,0x34,0x03,0x2a,0x00,0xeb, -0x04,0x03,0x21,0x44,0x11,0xd9,0x0e,0x46,0x1d,0x46,0x14,0x46,0x56,0xf8,0x04,0x7b, -0x04,0x3c,0x03,0x2c,0x45,0xf8,0x04,0x7b,0xf8,0xd8,0x14,0x1f,0x02,0xf0,0x03,0x02, -0x24,0xf0,0x03,0x04,0x04,0x34,0x09,0x19,0x1b,0x19,0x2a,0xb1,0x11,0xf8,0x01,0x4b, -0x01,0x3a,0x03,0xf8,0x01,0x4b,0xf9,0xd1,0xf0,0xbc,0x70,0x47,0x03,0x46,0xf5,0xe7, -0x10,0xf0,0x03,0x0f,0x03,0x46,0x70,0xb4,0x41,0xd0,0x00,0x2a,0x3d,0xd0,0xce,0xb2, -0x01,0xe0,0x00,0x2a,0x39,0xd0,0x03,0xf8,0x01,0x6b,0x54,0x1e,0x13,0xf0,0x03,0x0f, -0x22,0x46,0x1d,0x46,0xf5,0xd1,0x03,0x2c,0x29,0xd9,0xca,0xb2,0x0f,0x2c,0x84,0xbf, -0x2b,0x46,0x26,0x46,0x42,0xea,0x02,0x22,0x42,0xea,0x02,0x42,0x11,0xd9,0x10,0x3e, -0x1a,0x60,0x5a,0x60,0x9a,0x60,0xda,0x60,0x10,0x33,0x0f,0x2e,0xf7,0xd8,0xa4,0xf1, -0x10,0x03,0x04,0xf0,0x0f,0x04,0x23,0xf0,0x0f,0x03,0x10,0x33,0x03,0x2c,0x1d,0x44, -0x0d,0xd9,0x2e,0x46,0x23,0x46,0x04,0x3b,0x46,0xf8,0x04,0x2b,0x03,0x2b,0xfa,0xd8, -0x23,0x1f,0x04,0xf0,0x03,0x04,0x23,0xf0,0x03,0x03,0x04,0x33,0xed,0x18,0xc9,0xb2, -0x1c,0xb1,0x01,0x3c,0x05,0xf8,0x01,0x1b,0xfb,0xd1,0x70,0xbc,0x70,0x47,0x05,0x46, -0x14,0x46,0xc8,0xe7,0x20,0xf0,0x03,0x01,0x10,0xf0,0x03,0x00,0xc0,0xf1,0x00,0x00, -0x51,0xf8,0x04,0x3b,0x00,0xf1,0x04,0x0c,0x4f,0xea,0xcc,0x0c,0x6f,0xf0,0x00,0x02, -0x1c,0xbf,0x22,0xfa,0x0c,0xf2,0x13,0x43,0x4f,0xf0,0x01,0x0c,0x4c,0xea,0x0c,0x2c, -0x4c,0xea,0x0c,0x4c,0xa3,0xeb,0x0c,0x02,0x22,0xea,0x03,0x02,0x12,0xea,0xcc,0x12, -0x04,0xbf,0x51,0xf8,0x04,0x3b,0x04,0x30,0xf4,0xd0,0x13,0xf0,0xff,0x0f,0x1f,0xbf, -0x01,0x30,0x13,0xf4,0x7f,0x4f,0x01,0x30,0x13,0xf4,0x7f,0x0f,0x18,0xbf,0x01,0x30, -0x70,0x47,0x00,0xbf,0x00,0x21,0x03,0xe0,0x0a,0x4b,0x5b,0x58,0x43,0x50,0x04,0x31, -0x09,0x48,0x0a,0x4b,0x42,0x18,0x9a,0x42,0xf6,0xd3,0x09,0x4a,0x02,0xe0,0x00,0x23, -0x42,0xf8,0x04,0x3b,0x07,0x4b,0x9a,0x42,0xf9,0xd3,0xf9,0xf7,0xc5,0xfe,0x00,0xf0, -0x0d,0xf8,0x70,0x47,0x48,0x77,0x00,0x20,0x48,0x77,0x00,0x20,0x14,0x79,0x00,0x20, -0x14,0x79,0x00,0x20,0x38,0xb0,0x00,0x20,0xfe,0xe7,0x00,0x00,0x2d,0xe9,0xf0,0x4f, -0xb2,0x4c,0x89,0xb0,0x4a,0xf6,0xaa,0x25,0xfe,0xf7,0x08,0xfe,0x25,0x60,0xfc,0xf7, -0xc7,0xff,0x00,0x20,0xae,0x49,0xfc,0xf7,0x3b,0xfe,0xfe,0xf7,0x48,0xfd,0xad,0x4b, -0x25,0x60,0x1a,0x6b,0x42,0xf0,0x01,0x02,0x1a,0x63,0xff,0xf7,0x19,0xfa,0xfe,0xf7, -0x6b,0xff,0xff,0xf7,0xdd,0xfc,0x62,0xb6,0xff,0xf7,0xa0,0xfc,0xa6,0x4b,0x4f,0xf4, -0x00,0x70,0xc3,0xf8,0xe0,0x09,0x4f,0xf4,0x41,0x71,0xff,0xf7,0x75,0xf9,0x00,0x20, -0xfe,0xf7,0x9a,0xf9,0xfe,0xf7,0x80,0xfc,0xff,0xf7,0xfa,0xfc,0x9f,0x48,0xfc,0xf7, -0xcd,0xfc,0x9f,0x4b,0x9f,0x4a,0x00,0x93,0x9c,0x48,0x9f,0x4b,0x01,0x21,0x00,0x26, -0xfb,0xf7,0xac,0xfd,0x4f,0xf4,0x80,0x02,0x02,0x23,0x05,0x92,0x35,0x46,0x37,0x46, -0xb2,0x46,0x34,0x46,0x06,0x93,0xb0,0x46,0x90,0x4a,0x4a,0xf6,0xaa,0x21,0x93,0x4b, -0x11,0x60,0x93,0xf8,0xf4,0x05,0x00,0x28,0xf6,0xd0,0x11,0x60,0x8e,0x4a,0x92,0xf8, -0xe4,0x19,0x11,0xb1,0x01,0x39,0x82,0xf8,0xe4,0x19,0x4f,0xf0,0x00,0x09,0x83,0xf8, -0xf4,0x95,0xfc,0xf7,0x75,0xff,0x48,0x46,0x85,0x49,0xfc,0xf7,0xe9,0xfd,0xfe,0xf7, -0x66,0xfc,0x00,0x28,0x00,0xf0,0x8d,0x81,0x48,0x46,0xdf,0xf8,0x48,0x92,0x87,0x49, -0xfc,0xf7,0xde,0xfd,0xd9,0xf8,0x10,0x30,0x9b,0x05,0x01,0xd4,0x0a,0x2c,0x09,0xd1, -0x18,0x20,0x83,0x49,0xfc,0xf7,0xd4,0xfd,0xd9,0xf8,0x10,0x30,0x9c,0x05,0x04,0xd5, -0x0a,0x24,0x76,0xe1,0x00,0x2c,0x40,0xf0,0x8a,0x81,0x00,0x20,0x7d,0x49,0xfd,0xf7, -0x17,0xfd,0x00,0x24,0x00,0x28,0x40,0xf0,0x6c,0x81,0x7b,0x48,0xfd,0xf7,0xfe,0xfd, -0x18,0xb1,0x80,0xe1,0x02,0x2c,0x10,0xd1,0x00,0xe0,0x80,0x46,0x77,0x48,0x78,0x49, -0xfd,0xf7,0x2d,0xff,0x04,0x46,0x00,0x28,0x40,0xf0,0x7b,0x81,0xff,0xf7,0x99,0xfd, -0x25,0x46,0x82,0x46,0x27,0x46,0xa0,0x46,0x02,0xe0,0x03,0x2c,0x40,0xf0,0x98,0x80, -0xba,0xf1,0x06,0x0f,0x34,0xbf,0x52,0x46,0x06,0x22,0x4f,0xf0,0x00,0x09,0x07,0x92, -0x4f,0xf0,0x10,0x0b,0x4c,0x46,0x23,0xe0,0x6a,0x4a,0x32,0x23,0x03,0xfb,0x04,0x20, -0xff,0xf7,0xf8,0xfe,0x48,0x45,0x88,0xbf,0x5f,0xfa,0x80,0xf9,0x15,0x28,0x07,0xd9, -0x05,0xf1,0x15,0x03,0x83,0x42,0x98,0xbf,0x28,0x46,0x02,0xd9,0x15,0x38,0x00,0xe0, -0x00,0x20,0x32,0x23,0x03,0xfb,0x04,0x00,0x5e,0x4b,0x59,0x46,0x1a,0x18,0x00,0x20, -0x15,0x23,0xfc,0xf7,0x6a,0xfd,0x0b,0xf1,0x08,0x0b,0x01,0x34,0x5f,0xfa,0x8b,0xfb, -0x07,0x9a,0x94,0x42,0xd8,0xd1,0xfe,0xf7,0xf1,0xff,0x83,0x46,0xa0,0xf1,0x44,0x00, -0x43,0x42,0x43,0xeb,0x00,0x03,0xbb,0xf1,0x64,0x0f,0x08,0xbf,0x43,0xf0,0x01,0x03, -0x73,0xb1,0x63,0x1e,0x9f,0x42,0x01,0xd2,0x01,0x37,0x09,0xe0,0xa2,0x45,0x07,0xd9, -0x08,0xf1,0x01,0x08,0x5f,0xfa,0x88,0xf8,0x40,0x46,0xff,0xf7,0x42,0xfd,0x82,0x46, -0xab,0xf1,0x40,0x01,0x4b,0x42,0x43,0xeb,0x01,0x03,0xbb,0xf1,0x60,0x0f,0x08,0xbf, -0x43,0xf0,0x01,0x03,0x6b,0xb1,0x0f,0xb1,0x01,0x3f,0x0a,0xe0,0xb8,0xf1,0x00,0x0f, -0x07,0xd0,0x08,0xf1,0xff,0x38,0x5f,0xfa,0x88,0xf8,0x40,0x46,0xff,0xf7,0x29,0xfd, -0x82,0x46,0xab,0xf1,0x41,0x02,0x53,0x42,0x43,0xeb,0x02,0x03,0xbb,0xf1,0x61,0x0f, -0x08,0xbf,0x43,0xf0,0x01,0x03,0x23,0xb1,0x05,0xf1,0x15,0x03,0x4b,0x45,0x38,0xbf, -0x01,0x35,0xab,0xf1,0x45,0x09,0xd9,0xf1,0x00,0x03,0x43,0xeb,0x09,0x03,0xbb,0xf1, -0x65,0x0f,0x08,0xbf,0x43,0xf0,0x01,0x03,0x0b,0xb1,0x05,0xb1,0x01,0x3d,0x03,0x24, -0xbb,0xf1,0x83,0x0f,0x04,0xd1,0x20,0x4b,0x00,0x22,0xc3,0xf8,0xd8,0x29,0x04,0x24, -0xb9,0x1c,0xc9,0x00,0x00,0x20,0xc9,0xb2,0x7e,0x22,0x03,0x46,0xfc,0xf7,0x88,0xfd, -0x04,0x2c,0x17,0xd1,0x38,0x46,0xff,0xf7,0x73,0xfd,0x18,0x4b,0x03,0x24,0x03,0xeb, -0x87,0x03,0xd3,0xf8,0x24,0x2a,0x14,0x4b,0xa2,0xf5,0x00,0x42,0x01,0x28,0xc3,0xf8, -0xdc,0x29,0x00,0xf0,0xa6,0x80,0x02,0x28,0x08,0xd0,0x03,0x28,0x14,0xbf,0x04,0x24, -0x03,0x24,0x9e,0xe0,0x05,0x2c,0x40,0xf0,0x8f,0x80,0x02,0xe0,0x16,0x4b,0x00,0x26, -0x05,0x93,0x18,0x20,0x15,0x49,0x00,0x24,0xfc,0xf7,0xea,0xfc,0xdf,0xf8,0x18,0xb0, -0x13,0x4b,0x22,0x46,0xdd,0xf8,0x14,0x90,0x3e,0xe0,0x00,0xbf,0x00,0x30,0x00,0x40, -0xfa,0x76,0x00,0x20,0x00,0x38,0x02,0x40,0x50,0x93,0x00,0x20,0x58,0x82,0x00,0x20, -0xd0,0x78,0x00,0x20,0x08,0x78,0x00,0x20,0xbc,0x77,0x00,0x20,0x06,0x77,0x00,0x20, -0x0d,0x77,0x00,0x20,0x38,0x9d,0x00,0x20,0x13,0x77,0x00,0x20,0x58,0x8c,0x00,0x20, -0x1d,0x77,0x00,0x20,0x70,0x88,0x00,0x20,0x00,0x80,0x00,0x08,0x1f,0x77,0x00,0x20, -0x24,0x8d,0x00,0x20,0x00,0x00,0x02,0x40,0x03,0xeb,0x84,0x01,0x48,0x46,0x03,0x92, -0x04,0x93,0xff,0xf7,0xd7,0xfb,0xdb,0xf8,0xd4,0x19,0x03,0x9a,0x40,0x34,0xb1,0xf5, -0x80,0x7f,0x88,0xbf,0xa1,0xf5,0x80,0x71,0x04,0x9b,0x09,0xf5,0x80,0x79,0x8c,0xbf, -0xcb,0xf8,0xd4,0x19,0xcb,0xf8,0xd4,0x29,0xdb,0xf8,0xd4,0x19,0x00,0x29,0xe3,0xd1, -0x35,0x4b,0xcd,0xf8,0x14,0x90,0xd3,0xf8,0xdc,0x39,0x89,0x46,0xc3,0xf3,0x07,0x3b, -0x0b,0xf1,0x01,0x04,0x64,0xb2,0x08,0x46,0x22,0x46,0x27,0x21,0xfc,0xf7,0x26,0xfd, -0x48,0x46,0x30,0x21,0x22,0x46,0xfc,0xf7,0x21,0xfd,0x58,0x46,0x28,0x21,0x08,0x22, -0x01,0x36,0xfc,0xf7,0x1d,0xfd,0x07,0xe0,0x5f,0xfa,0x89,0xf0,0x28,0x21,0x08,0x22, -0xfc,0xf7,0x16,0xfd,0x09,0xf1,0x01,0x09,0xb1,0x45,0xf5,0xd3,0x23,0x48,0xdf,0xf8, -0x88,0x90,0x23,0x4b,0x00,0xf1,0x1c,0x01,0x4f,0xf4,0x80,0x52,0xfd,0xf7,0x11,0xfc, -0xd9,0xf8,0xe0,0x39,0xd9,0xf8,0xd4,0x49,0x9b,0x08,0x09,0x3b,0x00,0x2c,0x0c,0xbf, -0x06,0x24,0x05,0x24,0x9e,0x42,0x01,0xd8,0x06,0x2c,0x0a,0xd1,0xfe,0xf7,0xde,0xfe, -0x18,0x49,0x04,0x46,0x18,0x20,0xfc,0xf7,0x5b,0xfc,0x82,0x2c,0x0c,0xbf,0x03,0x24, -0x06,0x24,0x06,0x9a,0x01,0x2a,0x04,0xd1,0xfe,0xf7,0x61,0xfb,0x02,0x23,0x06,0x93, -0x01,0xe0,0x01,0x22,0x06,0x92,0x0c,0x4b,0xd3,0xf8,0x10,0x2c,0x13,0x2a,0x03,0xd8, -0x01,0x32,0xc3,0xf8,0x10,0x2c,0x3f,0xe6,0xfe,0xf7,0x82,0xfa,0x3c,0xe6,0x01,0x2c, -0x7f,0xf4,0x80,0xae,0x79,0xe6,0x10,0x20,0x07,0x49,0xfc,0xf7,0x39,0xfc,0x01,0x24, -0xdf,0xe7,0x02,0x24,0xdd,0xe7,0x00,0xbf,0x50,0x93,0x00,0x20,0x08,0x8d,0x00,0x20, -0x24,0x9d,0x00,0x20,0x28,0x77,0x00,0x20,0x3a,0x77,0x00,0x20,0x02,0x01,0x02,0x00, -0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x03,0x00,0x80,0x83,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x6f,0x00, -0x00,0x07,0x00,0x07,0x00,0x14,0x7f,0x14,0x7f,0x14,0x24,0x2a,0x7f,0x2a,0x12,0x23, -0x13,0x08,0x64,0x62,0x36,0x49,0x55,0x22,0x50,0x00,0x05,0x03,0x00,0x00,0x00,0x1c, -0x22,0x41,0x00,0x00,0x41,0x22,0x1c,0x00,0x14,0x08,0x3e,0x08,0x14,0x08,0x08,0x3e, -0x08,0x08,0x00,0x50,0x30,0x00,0x00,0x08,0x08,0x08,0x08,0x08,0x00,0x60,0x60,0x00, -0x00,0x20,0x10,0x08,0x04,0x02,0x00,0x3e,0x49,0x45,0x3e,0x00,0x00,0x42,0x7f,0x40, -0x00,0x62,0x51,0x49,0x46,0x00,0x41,0x49,0x49,0x36,0x00,0x18,0x14,0x12,0x7f,0x00, -0x27,0x45,0x45,0x39,0x00,0x3e,0x49,0x49,0x32,0x00,0x01,0x79,0x05,0x03,0x00,0x36, -0x49,0x49,0x36,0x00,0x06,0x49,0x29,0x1e,0x00,0x00,0x36,0x36,0x00,0x00,0x00,0x56, -0x36,0x00,0x00,0x08,0x14,0x22,0x41,0x14,0x14,0x14,0x14,0x14,0x41,0x22,0x14,0x08, -0x00,0x02,0x01,0x51,0x09,0x06,0x00,0x06,0x09,0x09,0x06,0x7e,0x09,0x09,0x09,0x7e, -0x7f,0x49,0x49,0x49,0x36,0x3e,0x41,0x41,0x41,0x22,0x7f,0x41,0x41,0x22,0x1c,0x7f, -0x49,0x49,0x49,0x41,0x7f,0x09,0x09,0x09,0x01,0x3e,0x41,0x49,0x49,0x7a,0x7f,0x08, -0x08,0x08,0x7f,0x00,0x41,0x7f,0x41,0x00,0x20,0x40,0x41,0x3f,0x01,0x7f,0x08,0x14, -0x22,0x41,0x7f,0x40,0x40,0x40,0x40,0x7f,0x02,0x0c,0x02,0x7f,0x7f,0x04,0x08,0x10, -0x7f,0x3e,0x41,0x41,0x41,0x3e,0x7f,0x09,0x09,0x09,0x06,0x3e,0x41,0x51,0x21,0x5e, -0x7f,0x09,0x19,0x29,0x46,0x26,0x49,0x49,0x49,0x32,0x01,0x01,0x7f,0x01,0x01,0x3f, -0x40,0x40,0x40,0x3f,0x1f,0x20,0x40,0x20,0x1f,0x3f,0x40,0x30,0x40,0x3f,0x63,0x14, -0x08,0x14,0x63,0x07,0x08,0x70,0x08,0x07,0x61,0x51,0x49,0x45,0x43,0x00,0x7f,0x41, -0x41,0x00,0x02,0x04,0x08,0x10,0x20,0x00,0x41,0x41,0x7f,0x00,0x04,0x02,0x01,0x02, -0x04,0x40,0x40,0x40,0x40,0x40,0x00,0x01,0x02,0x04,0x00,0x20,0x54,0x54,0x54,0x78, -0x7f,0x48,0x44,0x44,0x38,0x38,0x44,0x44,0x44,0x20,0x38,0x44,0x44,0x48,0x7f,0x38, -0x54,0x54,0x54,0x18,0x08,0x7e,0x09,0x01,0x02,0x0c,0x52,0x52,0x52,0x3e,0x7f,0x08, -0x04,0x04,0x78,0x00,0x44,0x7d,0x40,0x00,0x20,0x40,0x44,0x3d,0x00,0x7f,0x10,0x28, -0x44,0x00,0x00,0x41,0x7f,0x40,0x00,0x7c,0x04,0x18,0x04,0x78,0x7c,0x08,0x04,0x04, -0x78,0x38,0x44,0x44,0x44,0x38,0x7c,0x14,0x14,0x14,0x08,0x08,0x14,0x14,0x18,0x7c, -0x7c,0x08,0x04,0x04,0x08,0x48,0x54,0x54,0x54,0x20,0x04,0x3f,0x44,0x40,0x20,0x3c, -0x40,0x40,0x20,0x7c,0x1c,0x20,0x40,0x20,0x1c,0x3c,0x40,0x20,0x40,0x3c,0x44,0x28, -0x10,0x28,0x44,0x0c,0x50,0x50,0x50,0x3c,0x44,0x64,0x54,0x4c,0x44,0x00,0x08,0x36, -0x41,0x00,0x00,0x00,0x7f,0x00,0x00,0x00,0x41,0x36,0x08,0x00,0x08,0x08,0x22,0x1c, -0x08,0x08,0x1c,0x22,0x08,0x08,0x04,0x02,0x7f,0x02,0x04,0x10,0x20,0x7f,0x20,0x10, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xff,0xff,0xc3,0xc3,0xc3,0xc3,0xc3,0xe7,0xfe,0x3c,0x3f,0x3f, -0x30,0x30,0x30,0x30,0x30,0x39,0x1f,0x0f,0x3c,0x7e,0xe7,0xc3,0xc3,0xc3,0xc3,0xc7, -0x8e,0x0c,0x0c,0x1c,0x38,0x30,0x30,0x30,0x30,0x39,0x1f,0x0f,0xff,0xff,0x00,0x00, -0x00,0x00,0x00,0x00,0xff,0xff,0x0f,0x1f,0x38,0x30,0x30,0x30,0x30,0x38,0x1f,0x0f, -0x01,0x03,0x05,0x07,0x09,0x0e,0x10,0x12,0x14,0x16,0x18,0x1c,0x1e,0x80,0x9a,0x90, -0x41,0x8e,0x41,0x8f,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8e,0x8f,0x90,0x92,0x92, -0x4f,0x99,0x4f,0x55,0x55,0x59,0x99,0x9a,0x9b,0x9c,0x9d,0x9e,0x9f,0x41,0x49,0x4f, -0x55,0xa5,0xa5,0xa6,0xa7,0xa8,0xa9,0xaa,0xab,0xac,0x21,0xae,0xaf,0xb0,0xb1,0xb2, -0xb3,0xb4,0xb5,0xb6,0xb7,0xb8,0xb9,0xba,0xbb,0xbc,0xbd,0xbe,0xbf,0xc0,0xc1,0xc2, -0xc3,0xc4,0xc5,0xc6,0xc7,0xc8,0xc9,0xca,0xcb,0xcc,0xcd,0xce,0xcf,0xd0,0xd1,0xd2, -0xd3,0xd4,0xd5,0xd6,0xd7,0xd8,0xd9,0xda,0xdb,0xdc,0xdd,0xde,0xdf,0xe0,0xe1,0xe2, -0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,0xea,0xeb,0xec,0xed,0xee,0xef,0xf0,0xf1,0xf2, -0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,0xfe,0xff,0x00,0xc7,0x00, -0xfc,0x00,0xe9,0x00,0xe2,0x00,0xe4,0x00,0xe0,0x00,0xe5,0x00,0xe7,0x00,0xea,0x00, -0xeb,0x00,0xe8,0x00,0xef,0x00,0xee,0x00,0xec,0x00,0xc4,0x00,0xc5,0x00,0xc9,0x00, -0xe6,0x00,0xc6,0x00,0xf4,0x00,0xf6,0x00,0xf2,0x00,0xfb,0x00,0xf9,0x00,0xff,0x00, -0xd6,0x00,0xdc,0x00,0xa2,0x00,0xa3,0x00,0xa5,0x00,0xa7,0x20,0x92,0x01,0xe1,0x00, -0xed,0x00,0xf3,0x00,0xfa,0x00,0xf1,0x00,0xd1,0x00,0xaa,0x00,0xba,0x00,0xbf,0x00, -0x10,0x23,0xac,0x00,0xbd,0x00,0xbc,0x00,0xa1,0x00,0xab,0x00,0xbb,0x00,0x91,0x25, -0x92,0x25,0x93,0x25,0x02,0x25,0x24,0x25,0x61,0x25,0x62,0x25,0x56,0x25,0x55,0x25, -0x63,0x25,0x51,0x25,0x57,0x25,0x5d,0x25,0x5c,0x25,0x5b,0x25,0x10,0x25,0x14,0x25, -0x34,0x25,0x2c,0x25,0x1c,0x25,0x00,0x25,0x3c,0x25,0x5e,0x25,0x5f,0x25,0x5a,0x25, -0x54,0x25,0x69,0x25,0x66,0x25,0x60,0x25,0x50,0x25,0x6c,0x25,0x67,0x25,0x68,0x25, -0x64,0x25,0x65,0x25,0x59,0x25,0x58,0x25,0x52,0x25,0x53,0x25,0x6b,0x25,0x6a,0x25, -0x18,0x25,0x0c,0x25,0x88,0x25,0x84,0x25,0x8c,0x25,0x90,0x25,0x80,0x25,0xb1,0x03, -0xdf,0x00,0x93,0x03,0xc0,0x03,0xa3,0x03,0xc3,0x03,0xb5,0x00,0xc4,0x03,0xa6,0x03, -0x98,0x03,0xa9,0x03,0xb4,0x03,0x1e,0x22,0xc6,0x03,0xb5,0x03,0x29,0x22,0x61,0x22, -0xb1,0x00,0x65,0x22,0x64,0x22,0x20,0x23,0x21,0x23,0xf7,0x00,0x48,0x22,0xb0,0x00, -0x19,0x22,0xb7,0x00,0x1a,0x22,0x7f,0x20,0xb2,0x00,0xa0,0x25,0xa0,0x00,0x61,0x00, -0x62,0x00,0x63,0x00,0x64,0x00,0x65,0x00,0x66,0x00,0x67,0x00,0x68,0x00,0x69,0x00, -0x6a,0x00,0x6b,0x00,0x6c,0x00,0x6d,0x00,0x6e,0x00,0x6f,0x00,0x70,0x00,0x71,0x00, -0x72,0x00,0x73,0x00,0x74,0x00,0x75,0x00,0x76,0x00,0x77,0x00,0x78,0x00,0x79,0x00, -0x7a,0x00,0xa1,0x00,0xa2,0x00,0xa3,0x00,0xa5,0x00,0xac,0x00,0xaf,0x00,0xe0,0x00, -0xe1,0x00,0xe2,0x00,0xe3,0x00,0xe4,0x00,0xe5,0x00,0xe6,0x00,0xe7,0x00,0xe8,0x00, -0xe9,0x00,0xea,0x00,0xeb,0x00,0xec,0x00,0xed,0x00,0xee,0x00,0xef,0x00,0xf0,0x00, -0xf1,0x00,0xf2,0x00,0xf3,0x00,0xf4,0x00,0xf5,0x00,0xf6,0x00,0xf8,0x00,0xf9,0x00, -0xfa,0x00,0xfb,0x00,0xfc,0x00,0xfd,0x00,0xfe,0x00,0xff,0x00,0x01,0x01,0x03,0x01, -0x05,0x01,0x07,0x01,0x09,0x01,0x0b,0x01,0x0d,0x01,0x0f,0x01,0x11,0x01,0x13,0x01, -0x15,0x01,0x17,0x01,0x19,0x01,0x1b,0x01,0x1d,0x01,0x1f,0x01,0x21,0x01,0x23,0x01, -0x25,0x01,0x27,0x01,0x29,0x01,0x2b,0x01,0x2d,0x01,0x2f,0x01,0x31,0x01,0x33,0x01, -0x35,0x01,0x37,0x01,0x3a,0x01,0x3c,0x01,0x3e,0x01,0x40,0x01,0x42,0x01,0x44,0x01, -0x46,0x01,0x48,0x01,0x4b,0x01,0x4d,0x01,0x4f,0x01,0x51,0x01,0x53,0x01,0x55,0x01, -0x57,0x01,0x59,0x01,0x5b,0x01,0x5d,0x01,0x5f,0x01,0x61,0x01,0x63,0x01,0x65,0x01, -0x67,0x01,0x69,0x01,0x6b,0x01,0x6d,0x01,0x6f,0x01,0x71,0x01,0x73,0x01,0x75,0x01, -0x77,0x01,0x7a,0x01,0x7c,0x01,0x7e,0x01,0x92,0x01,0xb1,0x03,0xb2,0x03,0xb3,0x03, -0xb4,0x03,0xb5,0x03,0xb6,0x03,0xb7,0x03,0xb8,0x03,0xb9,0x03,0xba,0x03,0xbb,0x03, -0xbc,0x03,0xbd,0x03,0xbe,0x03,0xbf,0x03,0xc0,0x03,0xc1,0x03,0xc3,0x03,0xc4,0x03, -0xc5,0x03,0xc6,0x03,0xc7,0x03,0xc8,0x03,0xc9,0x03,0xca,0x03,0x30,0x04,0x31,0x04, -0x32,0x04,0x33,0x04,0x34,0x04,0x35,0x04,0x36,0x04,0x37,0x04,0x38,0x04,0x39,0x04, -0x3a,0x04,0x3b,0x04,0x3c,0x04,0x3d,0x04,0x3e,0x04,0x3f,0x04,0x40,0x04,0x41,0x04, -0x42,0x04,0x43,0x04,0x44,0x04,0x45,0x04,0x46,0x04,0x47,0x04,0x48,0x04,0x49,0x04, -0x4a,0x04,0x4b,0x04,0x4c,0x04,0x4d,0x04,0x4e,0x04,0x4f,0x04,0x51,0x04,0x52,0x04, -0x53,0x04,0x54,0x04,0x55,0x04,0x56,0x04,0x57,0x04,0x58,0x04,0x59,0x04,0x5a,0x04, -0x5b,0x04,0x5c,0x04,0x5e,0x04,0x5f,0x04,0x70,0x21,0x71,0x21,0x72,0x21,0x73,0x21, -0x74,0x21,0x75,0x21,0x76,0x21,0x77,0x21,0x78,0x21,0x79,0x21,0x7a,0x21,0x7b,0x21, -0x7c,0x21,0x7d,0x21,0x7e,0x21,0x7f,0x21,0x41,0xff,0x42,0xff,0x43,0xff,0x44,0xff, -0x45,0xff,0x46,0xff,0x47,0xff,0x48,0xff,0x49,0xff,0x4a,0xff,0x4b,0xff,0x4c,0xff, -0x4d,0xff,0x4e,0xff,0x4f,0xff,0x50,0xff,0x51,0xff,0x52,0xff,0x53,0xff,0x54,0xff, -0x55,0xff,0x56,0xff,0x57,0xff,0x58,0xff,0x59,0xff,0x5a,0xff,0x00,0x00,0x41,0x00, -0x42,0x00,0x43,0x00,0x44,0x00,0x45,0x00,0x46,0x00,0x47,0x00,0x48,0x00,0x49,0x00, -0x4a,0x00,0x4b,0x00,0x4c,0x00,0x4d,0x00,0x4e,0x00,0x4f,0x00,0x50,0x00,0x51,0x00, -0x52,0x00,0x53,0x00,0x54,0x00,0x55,0x00,0x56,0x00,0x57,0x00,0x58,0x00,0x59,0x00, -0x5a,0x00,0x21,0x00,0xe0,0xff,0xe1,0xff,0xe5,0xff,0xe2,0xff,0xe3,0xff,0xc0,0x00, -0xc1,0x00,0xc2,0x00,0xc3,0x00,0xc4,0x00,0xc5,0x00,0xc6,0x00,0xc7,0x00,0xc8,0x00, -0xc9,0x00,0xca,0x00,0xcb,0x00,0xcc,0x00,0xcd,0x00,0xce,0x00,0xcf,0x00,0xd0,0x00, -0xd1,0x00,0xd2,0x00,0xd3,0x00,0xd4,0x00,0xd5,0x00,0xd6,0x00,0xd8,0x00,0xd9,0x00, -0xda,0x00,0xdb,0x00,0xdc,0x00,0xdd,0x00,0xde,0x00,0x78,0x01,0x00,0x01,0x02,0x01, -0x04,0x01,0x06,0x01,0x08,0x01,0x0a,0x01,0x0c,0x01,0x0e,0x01,0x10,0x01,0x12,0x01, -0x14,0x01,0x16,0x01,0x18,0x01,0x1a,0x01,0x1c,0x01,0x1e,0x01,0x20,0x01,0x22,0x01, -0x24,0x01,0x26,0x01,0x28,0x01,0x2a,0x01,0x2c,0x01,0x2e,0x01,0x30,0x01,0x32,0x01, -0x34,0x01,0x36,0x01,0x39,0x01,0x3b,0x01,0x3d,0x01,0x3f,0x01,0x41,0x01,0x43,0x01, -0x45,0x01,0x47,0x01,0x4a,0x01,0x4c,0x01,0x4e,0x01,0x50,0x01,0x52,0x01,0x54,0x01, -0x56,0x01,0x58,0x01,0x5a,0x01,0x5c,0x01,0x5e,0x01,0x60,0x01,0x62,0x01,0x64,0x01, -0x66,0x01,0x68,0x01,0x6a,0x01,0x6c,0x01,0x6e,0x01,0x70,0x01,0x72,0x01,0x74,0x01, -0x76,0x01,0x79,0x01,0x7b,0x01,0x7d,0x01,0x91,0x01,0x91,0x03,0x92,0x03,0x93,0x03, -0x94,0x03,0x95,0x03,0x96,0x03,0x97,0x03,0x98,0x03,0x99,0x03,0x9a,0x03,0x9b,0x03, -0x9c,0x03,0x9d,0x03,0x9e,0x03,0x9f,0x03,0xa0,0x03,0xa1,0x03,0xa3,0x03,0xa4,0x03, -0xa5,0x03,0xa6,0x03,0xa7,0x03,0xa8,0x03,0xa9,0x03,0xaa,0x03,0x10,0x04,0x11,0x04, -0x12,0x04,0x13,0x04,0x14,0x04,0x15,0x04,0x16,0x04,0x17,0x04,0x18,0x04,0x19,0x04, -0x1a,0x04,0x1b,0x04,0x1c,0x04,0x1d,0x04,0x1e,0x04,0x1f,0x04,0x20,0x04,0x21,0x04, -0x22,0x04,0x23,0x04,0x24,0x04,0x25,0x04,0x26,0x04,0x27,0x04,0x28,0x04,0x29,0x04, -0x2a,0x04,0x2b,0x04,0x2c,0x04,0x2d,0x04,0x2e,0x04,0x2f,0x04,0x01,0x04,0x02,0x04, -0x03,0x04,0x04,0x04,0x05,0x04,0x06,0x04,0x07,0x04,0x08,0x04,0x09,0x04,0x0a,0x04, -0x0b,0x04,0x0c,0x04,0x0e,0x04,0x0f,0x04,0x60,0x21,0x61,0x21,0x62,0x21,0x63,0x21, -0x64,0x21,0x65,0x21,0x66,0x21,0x67,0x21,0x68,0x21,0x69,0x21,0x6a,0x21,0x6b,0x21, -0x6c,0x21,0x6d,0x21,0x6e,0x21,0x6f,0x21,0x21,0xff,0x22,0xff,0x23,0xff,0x24,0xff, -0x25,0xff,0x26,0xff,0x27,0xff,0x28,0xff,0x29,0xff,0x2a,0xff,0x2b,0xff,0x2c,0xff, -0x2d,0xff,0x2e,0xff,0x2f,0xff,0x30,0xff,0x31,0xff,0x32,0xff,0x33,0xff,0x34,0xff, -0x35,0xff,0x36,0xff,0x37,0xff,0x38,0xff,0x39,0xff,0x3a,0xff,0x00,0x00,0x00,0x00, -0xeb,0x3c,0x90,0x39,0x58,0x20,0x54,0x45,0x41,0x4d,0x00,0x00,0x02,0x08,0x01,0x00, -0x01,0x10,0x00,0x43,0x04,0xf8,0x01,0x00,0x20,0x00,0x40,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x29,0xce,0xfa,0x5c,0xd1,0x56,0x49,0x52,0x54,0x46, -0x53,0x20,0x20,0x20,0x20,0x20,0x46,0x41,0x54,0x31,0x32,0x20,0x20,0x20,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x55,0xaa, -0xf8,0xff,0xff,0x03,0x40,0x00,0x05,0x60,0x00,0x07,0x80,0x00,0x09,0xf0,0xff,0x0b, -0xc0,0x00,0x0d,0xe0,0x00,0x0f,0x00,0x01,0x11,0x20,0x01,0x13,0x40,0x01,0x15,0x60, -0x01,0x17,0x80,0x01,0x19,0xa0,0x01,0x1b,0xc0,0x01,0x1d,0xe0,0x01,0x1f,0x00,0x02, -0x21,0x20,0x02,0x23,0x40,0x02,0x25,0x60,0x02,0x27,0x80,0x02,0x29,0xa0,0x02,0x2b, -0xc0,0x02,0x2d,0xe0,0x02,0x2f,0x00,0x03,0x31,0x20,0x03,0x33,0x40,0x03,0x35,0x60, -0x03,0x37,0x80,0x03,0x39,0xa0,0x03,0x3b,0xc0,0x03,0x3d,0xe0,0x03,0x3f,0x00,0x04, -0x41,0x20,0x04,0x43,0x40,0x04,0x45,0x60,0x04,0x47,0x80,0x04,0x49,0xa0,0x04,0x4b, -0xc0,0x04,0x4d,0xe0,0x04,0x4f,0x00,0x05,0x51,0x20,0x05,0x53,0x40,0x05,0x55,0x60, -0x05,0x57,0x80,0x05,0x59,0xa0,0x05,0x5b,0xc0,0x05,0x5d,0xe0,0x05,0x5f,0x00,0x06, -0x61,0x20,0x06,0x63,0x40,0x06,0x65,0x60,0x06,0x67,0x80,0x06,0x69,0xa0,0x06,0x6b, -0xc0,0x06,0x6d,0xe0,0x06,0x6f,0x00,0x07,0x71,0x20,0x07,0x73,0x40,0x07,0x75,0x60, -0x07,0x77,0x80,0x07,0x79,0xa0,0x07,0x7b,0xc0,0x07,0x7d,0xe0,0x07,0x7f,0x00,0x08, -0x81,0x20,0x08,0x83,0x40,0x08,0x85,0x60,0x08,0x87,0x80,0x08,0x89,0xf0,0xff,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x45,0x52,0x53,0x4b,0x59,0x5f,0x39,0x58,0x20,0x20,0x20,0x08,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x54,0x41,0x52,0x41,0x4e,0x49,0x53,0x20,0x42,0x49,0x4e,0x24,0x00,0x3e,0x01,0xa3, -0x55,0x3d,0x55,0x3d,0x00,0x00,0x02,0xa3,0x55,0x3d,0x02,0x00,0x00,0x80,0x00,0x00, -0x46,0x49,0x52,0x4d,0x57,0x41,0x52,0x45,0x42,0x49,0x4e,0x24,0x00,0x3e,0x01,0xa3, -0x55,0x3d,0x55,0x3d,0x00,0x00,0x02,0xa3,0x55,0x3d,0x0a,0x00,0x00,0x00,0x08,0x00, -0x00,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x80,0x02,0x02,0x1f,0x00,0x00,0x00,0x46,0x72,0x53,0x6b,0x79,0x20,0x20,0x20, -0x54,0x61,0x72,0x61,0x6e,0x69,0x73,0x20,0x52,0x61,0x64,0x69,0x6f,0x20,0x20,0x20, -0x31,0x2e,0x30,0x30,0x00,0x80,0x02,0x02,0x1f,0x00,0x00,0x00,0x46,0x72,0x53,0x6b, -0x79,0x20,0x20,0x20,0x54,0x61,0x72,0x61,0x6e,0x69,0x73,0x20,0x52,0x61,0x64,0x69, -0x6f,0x20,0x20,0x20,0x31,0x2e,0x30,0x30,0x4d,0x53,0x43,0x20,0x49,0x6e,0x74,0x65, -0x72,0x66,0x61,0x63,0x65,0x00,0x4d,0x53,0x43,0x20,0x43,0x6f,0x6e,0x66,0x69,0x67, -0x00,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x31,0x42,0x00,0x46,0x72, -0x53,0x6b,0x79,0x00,0x46,0x72,0x53,0x6b,0x79,0x20,0x54,0x61,0x72,0x61,0x6e,0x69, -0x73,0x20,0x4d,0x61,0x73,0x73,0x20,0x53,0x74,0x6f,0x72,0x61,0x67,0x65,0x00,0x22, -0x2a,0x3a,0x3c,0x3e,0x3f,0x7c,0x7f,0x00,0x2b,0x2c,0x3b,0x3d,0x5b,0x5d,0x00,0x5c, -0x66,0x69,0x72,0x6d,0x77,0x61,0x72,0x65,0x5c,0x00,0x05,0x46,0x6c,0x61,0x73,0x68, -0x20,0x46,0x69,0x6c,0x65,0x00,0x4e,0x4f,0x54,0x20,0x41,0x20,0x56,0x41,0x4c,0x49, -0x44,0x20,0x46,0x49,0x52,0x4d,0x57,0x41,0x52,0x45,0x00,0x07,0x5b,0x45,0x58,0x49, -0x54,0x5d,0x00,0x03,0x59,0x45,0x53,0x0b,0x4e,0x4f,0x00,0x03,0x5b,0x4d,0x45,0x4e, -0x55,0x5d,0x0b,0x5b,0x45,0x58,0x49,0x54,0x5d,0x00,0x42,0x6f,0x6f,0x74,0x20,0x4c, -0x6f,0x61,0x64,0x65,0x72,0x00,0x0c,0x52,0x65,0x61,0x64,0x79,0x00,0x08,0x42,0x55, -0x53,0x59,0x00,0x5c,0x66,0x69,0x72,0x6d,0x77,0x61,0x72,0x65,0x00,0x2e,0x00,0x46, -0x6c,0x61,0x73,0x68,0x69,0x6e,0x67,0x00,0x46,0x6c,0x61,0x73,0x68,0x69,0x6e,0x67, -0x20,0x43,0x6f,0x6d,0x70,0x6c,0x65,0x74,0x65,0x00,0x05,0x4e,0x6f,0x20,0x46,0x69, -0x72,0x6d,0x77,0x61,0x72,0x65,0x00,0x00,0x00,0x87,0x93,0x03,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04,0x06,0x07,0x08,0x09,0x00,0x00,0x00,0x00, -0x01,0x02,0x03,0x04,0x01,0x02,0x03,0x04,0x06,0x07,0x08,0x09,0x70,0x77,0x00,0x20, -0x89,0x1f,0x00,0x20,0xd5,0x1e,0x00,0x20,0x8b,0x1e,0x00,0x20,0xfb,0x1d,0x00,0x20, -0x5d,0x1e,0x00,0x20,0xdf,0x1d,0x00,0x20,0xc9,0x1d,0x00,0x20,0x0b,0x1e,0x00,0x20, -0x19,0x1e,0x00,0x20,0x27,0x1e,0x00,0x20,0x3d,0x1e,0x00,0x20,0x09,0x02,0x20,0x00, -0x01,0x01,0x04,0xc0,0x32,0x09,0x04,0x00,0x00,0x02,0x08,0x06,0x50,0x05,0x07,0x05, -0x81,0x02,0x40,0x00,0x00,0x07,0x05,0x01,0x02,0x40,0x00,0x00,0x5d,0x2d,0x00,0x20, -0x41,0x2d,0x00,0x20,0x89,0x2c,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x7f,0x2c,0x00,0x20,0x75,0x2c,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x69,0x2c,0x00,0x20,0x12,0x01,0x00,0x02,0x00,0x00,0x00,0x40, -0x83,0x04,0x20,0x57,0x00,0x02,0x01,0x02,0x03,0x01,0x04,0x03,0x09,0x04,0x0a,0x06, -0x00,0x02,0x00,0x00,0x00,0x40,0x01,0x00,0x89,0x2d,0x00,0x20,0x95,0x2d,0x00,0x20, -0xf5,0x2d,0x00,0x20,0x11,0x2e,0x00,0x20,0xd9,0x2d,0x00,0x20,0xbd,0x2d,0x00,0x20, -0xa1,0x2d,0x00,0x20,0x04,0x08,0x00,0x38,0x38,0x7c,0xfe,0x0a,0x40,0x50,0xff,0xf7, -0xf3,0xf9,0x00,0x00,0xf9,0xf3,0xf7,0xff,0xff,0xff,0xff,0xff,0xfc,0xfc,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xcf,0x87,0x03, -0x49,0xcf,0xcf,0xcf,0xcf,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0x3f,0x3f,0xff,0xff,0xff,0xff,0xff,0xef,0xcf,0x9f,0x00,0x00, -0x9f,0xcf,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0x3f,0x7f,0xff,0x3f,0x8f,0xe3,0xf8,0xff,0xff,0xff,0xff,0xfe,0xfc,0xfe,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xcf,0xcf,0xcf, -0xcf,0x49,0x03,0x87,0xcf,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff, -0xff,0x7f,0x7f,0xff,0xff,0xff,0xff,0x7f,0x7f,0xff,0xff,0x9e,0x8c,0xc0,0xe1,0xe1, -0xc0,0x8c,0x9e,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x01,0x00, -0x0d,0x5b,0x00,0x20,0x0f,0x5b,0x00,0x20,0x11,0x5b,0x00,0x20,0x13,0x5b,0x00,0x20, -0x15,0x5b,0x00,0x20,0x17,0x5b,0x00,0x20,0x19,0x5b,0x00,0x20,0xf0,0x78,0x00,0x20, -0x25,0x5b,0x00,0x20,0x61,0x5b,0x00,0x20,0x47,0x5b,0x00,0x20,0x1d,0x5b,0x00,0x20, -0x25,0x5c,0x00,0x20,0x31,0x5d,0x00,0x20,0x21,0x5b,0x00,0x20,0x10,0x76,0x00,0x20, -0x01,0x00,0x00,0x00, - diff --git a/radio/src/loadboot.cpp b/radio/src/loadboot.cpp index f69ab8d19..9093076e8 100644 --- a/radio/src/loadboot.cpp +++ b/radio/src/loadboot.cpp @@ -47,28 +47,32 @@ #include -//#include "lcd.h" #ifdef PCBSKY #include "AT91SAM3S4.h" #endif #ifdef PCBTARANIS -#include "stm32f2xx.h" -#include "stm32f2xx_gpio.h" + #include "stm32f2xx.h" + #include "stm32f2xx_gpio.h" +#else + #ifdef PCBX9D + #include "x9d\stm32f2xx.h" + #include "x9d\stm32f2xx_gpio.h" + #endif +#endif +#if defined(PCBX9D) || defined(PCBTARANIS) void bwdt_reset() { IWDG->KR = 0xAAAA ; // reload } #endif -#ifdef PCBTARANIS -//#include "lcd.h" +#if defined(PCBX9D) || defined(PCBTARANIS) __attribute__ ((section(".bootrodata"), used)) void _bootStart( void ) ; - __attribute__ ((section(".isr_boot_vector"), used)) const uint32_t BootVectors[] = { (uint32_t)&_estack, @@ -76,7 +80,7 @@ const uint32_t BootVectors[] = { } ; #endif -#ifdef PCBTARANIS +#if defined(PCBX9D) || defined(PCBTARANIS) __attribute__ ((section(".bootrodata.*"), used)) #endif @@ -85,39 +89,13 @@ __attribute__ ((section(".bootrodata"), used)) #endif const uint8_t BootCode[] = { -#ifdef PCBTARANIS -#include "bootflashX.lbm" -#else - #ifdef REVX - #include "bootflash8.lbm" - #else - #include "bootflash4.lbm" - #endif -#endif +#include "bootloader.lbm" } ; -#ifdef PCBTARANIS +#if defined(PCBX9D) || defined(PCBTARANIS) __attribute__ ((section(".bootrodata"), used)) -static void run_application( void ) ; - -static void run_application() -{ - asm(" mov.w r1, #134217728"); // 0x8000000 - asm(" add.w r1, #32768"); // 0x8000 - - asm(" movw r0, #60680"); // 0xED08 - asm(" movt r0, #57344"); // 0xE000 - asm(" str r1, [r0, #0]"); // Set the VTOR - - asm("ldr r0, [r1, #0]"); // Stack pointer value - asm("msr msp, r0"); // Set it - asm("ldr r0, [r1, #4]"); // Reset address - asm("mov.w r1, #1"); - asm("orr r0, r1"); // Set lsbit - asm("bx r0"); // Execute application -} void _bootStart() { @@ -161,7 +139,20 @@ void _bootStart() } } - run_application() ; +// run_application() ; + asm(" mov.w r1, #134217728"); // 0x8000000 + asm(" add.w r1, #32768"); // 0x8000 + + asm(" movw r0, #60680"); // 0xED08 + asm(" movt r0, #57344"); // 0xE000 + asm(" str r1, [r0, #0]"); // Set the VTOR + + asm("ldr r0, [r1, #0]"); // Stack pointer value + asm("msr msp, r0"); // Set it + asm("ldr r0, [r1, #4]"); // Reset address + asm("mov.w r1, #1"); + asm("orr r0, r1"); // Set lsbit + asm("bx r0"); // Execute application } #endif diff --git a/radio/src/targets/sky9x/sam3s4c_flash.ld b/radio/src/targets/sky9x/sam3s4c_flash.ld index fd8241a61..247bf4b1b 100644 --- a/radio/src/targets/sky9x/sam3s4c_flash.ld +++ b/radio/src/targets/sky9x/sam3s4c_flash.ld @@ -71,9 +71,15 @@ SECTIONS */ .text : { - _stext = .; /* Provide the name for the start of this section */ + FILL(0xFFFF) - CREATE_OBJECT_SYMBOLS + CREATE_OBJECT_SYMBOLS + + *(.bootrodata) + *(.bootrodata.*) + + . = ALIGN(32768); /* Align the start of the exidx part */ + _stext = .; /* Provide the name for the start of this section */ KEEP(*(.vectors)) *(.text) @@ -129,11 +135,8 @@ SECTIONS . = ALIGN(4); /* Align the end of the section */ } > RAM - _ebss = .; /* Provide the name for the end of this section */ + _ebss = .; /* Provide the name for the end of this section */ - . = ALIGN(4); /* Align the end of the section */ - __end = .; - _end = .; /* * The ".stack" section is our stack. diff --git a/radio/src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c b/radio/src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c index 95a58c955..162a1bb77 100644 --- a/radio/src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c +++ b/radio/src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c @@ -232,9 +232,12 @@ void SystemInit(void) #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else -// SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -extern uint32_t g_pfnVectors ; - SCB->VTOR = (uint32_t) &g_pfnVectors ; /* Vector Table Relocation in Internal FLASH */ + #if defined(BOOTLOADER) + extern uint32_t g_pfnVectors ; + SCB->VTOR = (uint32_t) &g_pfnVectors ; /* Vector Table Relocation in Internal FLASH */ + #else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + #endif #endif } diff --git a/radio/src/targets/taranis/stm32_flash.ld b/radio/src/targets/taranis/stm32_flash.ld index b478c181b..a3279e20a 100644 --- a/radio/src/targets/taranis/stm32_flash.ld +++ b/radio/src/targets/taranis/stm32_flash.ld @@ -32,9 +32,6 @@ /* Entry Point */ ENTRY(Reset_Handler) -/* Highest address of the user mode stack */ -_estack = 0x20020000; /* end of 128K SRAM */ - /* Generate a link error if heap and stack don't fit into RAM */ _Min_Heap_Size = 0; /* required amount of heap */ _Min_Stack_Size = 0x200; /* required amount of stack */ @@ -55,16 +52,6 @@ SECTIONS /* The program code and other data goes into FLASH */ .text : { - FILL(0xFFFF) - - CREATE_OBJECT_SYMBOLS - - KEEP(*(.isr_boot_vector)) /* Startup code */ - *(.bootrodata) - *(.bootrodata.*) - - . = ALIGN(32768); /* Align the start of the main program */ - _stext = .; /* Provide the name for the start of this section */ . = ALIGN(4); KEEP(*(.isr_vector)) /* Startup code */ *(.text) /* .text sections (code) */ @@ -154,6 +141,8 @@ SECTIONS . = ALIGN(4); } >RAM + PROVIDE ( _estack = ORIGIN(RAM) + LENGTH(RAM) ); + /* MEMORY_bank1 section, code must be located here explicitly */ /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */ .memory_b1_text : diff --git a/radio/src/targets/taranis/stm32_flash_bl.ld b/radio/src/targets/taranis/stm32_flash_bl.ld new file mode 100644 index 000000000..da01f5785 --- /dev/null +++ b/radio/src/targets/taranis/stm32_flash_bl.ld @@ -0,0 +1,176 @@ +/* +***************************************************************************** +** +** File : stm32_flash.ld +** +** Abstract : Linker script for STM32F205 Device with +** 0.5MByte FLASH, 128KByte SRAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Environment : Atollic TrueSTUDIO(R) +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +** (c)Copyright Atollic AB. +** You may use this file as-is or modify it according to the needs of your +** project. Distribution of this file (unmodified or modified) is not +** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the +** rights to distribute the assembled, compiled & linked contents of this +** file as part of an application binary file, provided that it is built +** using the Atollic TrueSTUDIO(R) toolchain. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20020000; /* end of 128K SRAM */ + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0; /* required amount of heap */ +_Min_Stack_Size = 0x200; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K + MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + + /* The program code and other data goes into FLASH */ + .text : + { + FILL(0xFFFF) + + CREATE_OBJECT_SYMBOLS + + KEEP(*(.isr_boot_vector)) /* Startup code */ + *(.bootrodata) + *(.bootrodata.*) + + . = ALIGN(32768); /* Align the start of the main program */ + _stext = .; /* Provide the name for the start of this section */ + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(.fini_array*)) + KEEP (*(SORT(.fini_array.*))) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = .; + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : AT ( _sidata ) + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + PROVIDE ( end = _ebss ); + PROVIDE ( _end = _ebss ); + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(4); + } >RAM + + /* MEMORY_bank1 section, code must be located here explicitly */ + /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */ + .memory_b1_text : + { + *(.mb1text) /* .mb1text sections (code) */ + *(.mb1text*) /* .mb1text* sections (code) */ + *(.mb1rodata) /* read-only data (constants) */ + *(.mb1rodata*) + } >MEMORY_B1 + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/radio/util/bin2lbm.py b/radio/util/bin2lbm.py new file mode 100644 index 000000000..3a41b90dd --- /dev/null +++ b/radio/util/bin2lbm.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python + +import sys + +fileout = sys.argv[1] +print fileout +filename = sys.argv[2] +print filename + +fr = open(filename, "rb") +fw = open(fileout, "w") + +st = fr.read(16) + +while st: + for b in st: + fw.write("0x%02x," % ord(b)) + fw.write("\n") + st = fr.read(16) + +fw.write("\n") + +fw.close() From eb3cc1447b18ba9100945398aa204d63f23b8935 Mon Sep 17 00:00:00 2001 From: Andre Bernet Date: Sat, 18 Jan 2014 20:43:41 +0100 Subject: [PATCH 003/285] obj dir not required anymore for bootloader --- radio/bootloader/makefile | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/radio/bootloader/makefile b/radio/bootloader/makefile index bfcfe11aa..c046f1c2e 100644 --- a/radio/bootloader/makefile +++ b/radio/bootloader/makefile @@ -25,7 +25,7 @@ AS = $(TRGT)as BIN = $(CP) -O ihex BINX = $(CP) -O binary -OBJDIR = obj +OBJDIR = . MCU = cortex-m3 @@ -358,10 +358,7 @@ $(AOBJS) : $(OBJDIR)/%.o : %.s # $(PROJECT)_ramBootT clean: - -rm -f obj/*.o - -rm -f xobj/*.o - -rm -f robj/*.o - -rm -f tobj/*.o + -rm -f *.o -rm -f *.elf -rm -f *.map -rm -f *.hex From 4506328144886a3d568ab9584cc9908c981563d5 Mon Sep 17 00:00:00 2001 From: mhotar Date: Sat, 1 Mar 2014 00:25:18 +0100 Subject: [PATCH 004/285] Preflight check label and items --- radio/src/gui/menu_model.cpp | 23 ++++++++++++++--------- radio/src/translations.cpp | 1 + radio/src/translations/en.h.txt | 9 +++++---- 3 files changed, 20 insertions(+), 13 deletions(-) diff --git a/radio/src/gui/menu_model.cpp b/radio/src/gui/menu_model.cpp index bea52b0ce..ae6e3036f 100644 --- a/radio/src/gui/menu_model.cpp +++ b/radio/src/gui/menu_model.cpp @@ -873,10 +873,11 @@ enum menuModelSetupItems { ITEM_MODEL_THROTTLE_REVERSED, ITEM_MODEL_THROTTLE_TRACE, ITEM_MODEL_THROTTLE_TRIM, - ITEM_MODEL_THROTTLE_WARNING, + CASE_PCBTARANIS(ITEM_MODEL_PREFLIGHT_LABEL) #if defined(PCBTARANIS) ITEM_MODEL_CHECKLIST_DISPLAY, #endif + ITEM_MODEL_THROTTLE_WARNING, ITEM_MODEL_SWITCHES_WARNING, CASE_PCBTARANIS(ITEM_MODEL_POT_WARNING) ITEM_MODEL_BEEP_CENTER, @@ -964,7 +965,7 @@ void menuModelSetup(uint8_t event) #define POT_WARN_ITEMS() ((g_model.nPotsToWarn >> 6) ? (uint8_t)NUM_POTS : (uint8_t)0) bool CURSOR_ON_CELL = (m_posHorz >= 0); - MENU_TAB({ 0, 0, CASE_PCBTARANIS(0) 2, IF_PERSISTENT_TIMERS(0) 0, 0, 2, IF_PERSISTENT_TIMERS(0) 0, 0, 0, 1, 0, 0, 0, 0, 0, CASE_PCBTARANIS(0) 7, POT_WARN_ITEMS(), NAVIGATION_LINE_BY_LINE|(NUM_STICKS+NUM_POTS+NUM_ROTARY_ENCODERS-1), LABEL(InternalModule), 0, IF_PORT1_ON(1), IF_PORT1_ON(IS_D8_RX(0) ? (uint8_t)1 : (uint8_t)2), IF_PORT1_ON(FAILSAFE_ROWS(0)), LABEL(ExternalModule), (g_model.externalModule==MODULE_TYPE_XJT || IS_MODULE_DSM2(EXTERNAL_MODULE)) ? (uint8_t)1 : (uint8_t)0, PORT2_CHANNELS_ROWS(), (IS_MODULE_XJT(1) && IS_D8_RX(1)) ? (uint8_t)1 : (IS_MODULE_PPM(1) || IS_MODULE_XJT(1) || IS_MODULE_DSM2(1)) ? (uint8_t)2 : HIDDEN_ROW, IF_PORT2_XJT(FAILSAFE_ROWS(1)), LABEL(Trainer), 0, TRAINER_CHANNELS_ROWS(), IF_TRAINER_ON(2)}); + MENU_TAB({ 0, 0, CASE_PCBTARANIS(0) 2, IF_PERSISTENT_TIMERS(0) 0, 0, 2, IF_PERSISTENT_TIMERS(0) 0, 0, 0, 1, 0, 0, 0, 0,LABEL(PreflightCheck), CASE_PCBTARANIS(0) 0, 7, POT_WARN_ITEMS(), NAVIGATION_LINE_BY_LINE|(NUM_STICKS+NUM_POTS+NUM_ROTARY_ENCODERS-1), LABEL(InternalModule), 0, IF_PORT1_ON(1), IF_PORT1_ON(IS_D8_RX(0) ? (uint8_t)1 : (uint8_t)2), IF_PORT1_ON(FAILSAFE_ROWS(0)), LABEL(ExternalModule), (g_model.externalModule==MODULE_TYPE_XJT || IS_MODULE_DSM2(EXTERNAL_MODULE)) ? (uint8_t)1 : (uint8_t)0, PORT2_CHANNELS_ROWS(), (IS_MODULE_XJT(1) && IS_D8_RX(1)) ? (uint8_t)1 : (IS_MODULE_PPM(1) || IS_MODULE_XJT(1) || IS_MODULE_DSM2(1)) ? (uint8_t)2 : HIDDEN_ROW, IF_PORT2_XJT(FAILSAFE_ROWS(1)), LABEL(Trainer), 0, TRAINER_CHANNELS_ROWS(), IF_TRAINER_ON(2)}); #elif defined(CPUM64) #define CURSOR_ON_CELL (true) #define MODEL_SETUP_MAX_LINES ((IS_PPM_PROTOCOL(protocol)||IS_DSM2_PROTOCOL(protocol)||IS_PXX_PROTOCOL(protocol)) ? 1+ITEM_MODEL_SETUP_MAX : ITEM_MODEL_SETUP_MAX) @@ -1142,16 +1143,20 @@ void menuModelSetup(uint8_t event) g_model.thrTrim = onoffMenuItem(g_model.thrTrim, MODEL_SETUP_2ND_COLUMN, y, STR_TTRIM, attr, event); break; - case ITEM_MODEL_THROTTLE_WARNING: - g_model.disableThrottleWarning = !onoffMenuItem(!g_model.disableThrottleWarning, MODEL_SETUP_2ND_COLUMN, y, STR_THROTTLEWARNING, attr, event); - break; - #if defined(PCBTARANIS) + case ITEM_MODEL_PREFLIGHT_LABEL: + lcd_putsLeft(y, TR_PREFLIGHT); + break; + case ITEM_MODEL_CHECKLIST_DISPLAY: g_model.displayText = onoffMenuItem(g_model.displayText, MODEL_SETUP_2ND_COLUMN, y, STR_CHECKLIST, attr, event); break; #endif + case ITEM_MODEL_THROTTLE_WARNING: + g_model.disableThrottleWarning = !onoffMenuItem(!g_model.disableThrottleWarning, MODEL_SETUP_2ND_COLUMN, y, STR_THROTTLEWARNING, attr, event); + break; + case ITEM_MODEL_SWITCHES_WARNING: { lcd_putsLeft(y, STR_SWITCHWARNING); @@ -1201,9 +1206,9 @@ void menuModelSetup(uint8_t event) uint8_t swactive = !(g_model.nSwToWarn & 1 << i); #if defined(PCBTARANIS) c = "\300-\301"[states & 0x03]; - lcd_putcAtt(MODEL_SETUP_2ND_COLUMN+i*(2*FW), y, 'A'+i, line && (m_posHorz == i) ? INVERS : 0); - if (swactive) lcd_putc(MODEL_SETUP_2ND_COLUMN+i*(2*FW)+FWNUM, y, c); - lcd_putsAtt(MODEL_SETUP_2ND_COLUMN+((NUM_SWITCHES-1)*2*FW+2), y, PSTR("<]"), (m_posHorz == NUM_SWITCHES-1 && !s_noHi) ? line : 0); + lcd_putcAtt(MODEL_SETUP_2ND_COLUMN+i*(2*FW+1), y, 'A'+i, line && (m_posHorz == i) ? INVERS : 0); + if (swactive) lcd_putc(MODEL_SETUP_2ND_COLUMN+i*(2*FW+1)+FWNUM+1, y, c); + lcd_putsAtt(MODEL_SETUP_2ND_COLUMN+((NUM_SWITCHES-1)*2*FW+8), y, PSTR("<]"), (m_posHorz == NUM_SWITCHES-1 && !s_noHi) ? line : 0); states >>= 2; #else attr = 0; diff --git a/radio/src/translations.cpp b/radio/src/translations.cpp index f85c49c49..3042345f7 100644 --- a/radio/src/translations.cpp +++ b/radio/src/translations.cpp @@ -496,6 +496,7 @@ const pm_char STR_VIEW_TEXT[] PROGMEM = "View text"; const pm_char STR_VIEW_CHANNELS[] PROGMEM = "View Channels"; const pm_char STR_VIEW_NOTES[] PROGMEM = "View Notes"; const pm_char STR_POTWARNING[] PROGMEM = TR_POTWARNING; + const pm_char STR_PREFLIGHT[] PROGMEM = TR_PREFLIGHT; const pm_char STR_CHECKLIST[] PROGMEM = TR_CHECKLIST; const pm_char STR_UART3MODE[] PROGMEM = TR_UART3MODE; const pm_char STR_POT1TYPE[] PROGMEM = TR_POT1TYPE; diff --git a/radio/src/translations/en.h.txt b/radio/src/translations/en.h.txt index 32940a94e..c22ecb8ed 100644 --- a/radio/src/translations/en.h.txt +++ b/radio/src/translations/en.h.txt @@ -523,9 +523,9 @@ #define TR_BLONBRIGHTNESS INDENT"ON Brightness" #define TR_BLOFFBRIGHTNESS INDENT"OFF Brightness" #define TR_SPLASHSCREEN "Splash screen" -#define TR_THROTTLEWARNING TR("T-Warning","Throttle Warning") -#define TR_SWITCHWARNING TR("S-Warning","Switch Warning") -#define TR_POTWARNING TR("Pot Warn.","Pot Warning") +#define TR_THROTTLEWARNING TR("T-Warning", INDENT "Throttle State") +#define TR_SWITCHWARNING TR("S-Warning", INDENT "Switch Positions") +#define TR_POTWARNING TR("Pot Warn.", INDENT "Pot Setup") #define TR_TIMEZONE TR("Time Zone","GPS Time zone") #define TR_RXCHANNELORD TR("Rx Channel Ord","Default channel order") #define TR_SLAVE "Slave" @@ -720,7 +720,8 @@ #define TR_LOWALARM INDENT "Low Alarm" #define TR_CRITICALALARM INDENT "Critical Alarm" #define TR_PERSISTENT_MAH INDENT "Store mAh" -#define TR_CHECKLIST "Display Checklist" +#define TR_PREFLIGHT "Preflight Checks" +#define TR_CHECKLIST INDENT "Display Checklist" #define TR_FAS_OFFSET TR(INDENT "FAS Ofs", INDENT "FAS Offset") #define TR_UART3MODE "Serial port" #define TR_POT1TYPE "S1 Type" From 55ff2e6b5ea2401c17cb713e9e42f0e54f2ec5da Mon Sep 17 00:00:00 2001 From: mhotar Date: Sat, 1 Mar 2014 01:20:47 +0100 Subject: [PATCH 005/285] Throttle label and missing string defs --- radio/src/gui/menu_model.cpp | 13 +++++++++---- radio/src/translations.cpp | 1 + radio/src/translations.h | 4 +++- radio/src/translations/en.h.txt | 7 ++++--- 4 files changed, 17 insertions(+), 8 deletions(-) diff --git a/radio/src/gui/menu_model.cpp b/radio/src/gui/menu_model.cpp index ae6e3036f..da8b1ae88 100644 --- a/radio/src/gui/menu_model.cpp +++ b/radio/src/gui/menu_model.cpp @@ -870,6 +870,7 @@ enum menuModelSetupItems { ITEM_MODEL_EXTENDED_LIMITS, ITEM_MODEL_EXTENDED_TRIMS, ITEM_MODEL_TRIM_INC, + ITEM_MODEL_THROTTLE_LABEL, ITEM_MODEL_THROTTLE_REVERSED, ITEM_MODEL_THROTTLE_TRACE, ITEM_MODEL_THROTTLE_TRIM, @@ -965,19 +966,19 @@ void menuModelSetup(uint8_t event) #define POT_WARN_ITEMS() ((g_model.nPotsToWarn >> 6) ? (uint8_t)NUM_POTS : (uint8_t)0) bool CURSOR_ON_CELL = (m_posHorz >= 0); - MENU_TAB({ 0, 0, CASE_PCBTARANIS(0) 2, IF_PERSISTENT_TIMERS(0) 0, 0, 2, IF_PERSISTENT_TIMERS(0) 0, 0, 0, 1, 0, 0, 0, 0,LABEL(PreflightCheck), CASE_PCBTARANIS(0) 0, 7, POT_WARN_ITEMS(), NAVIGATION_LINE_BY_LINE|(NUM_STICKS+NUM_POTS+NUM_ROTARY_ENCODERS-1), LABEL(InternalModule), 0, IF_PORT1_ON(1), IF_PORT1_ON(IS_D8_RX(0) ? (uint8_t)1 : (uint8_t)2), IF_PORT1_ON(FAILSAFE_ROWS(0)), LABEL(ExternalModule), (g_model.externalModule==MODULE_TYPE_XJT || IS_MODULE_DSM2(EXTERNAL_MODULE)) ? (uint8_t)1 : (uint8_t)0, PORT2_CHANNELS_ROWS(), (IS_MODULE_XJT(1) && IS_D8_RX(1)) ? (uint8_t)1 : (IS_MODULE_PPM(1) || IS_MODULE_XJT(1) || IS_MODULE_DSM2(1)) ? (uint8_t)2 : HIDDEN_ROW, IF_PORT2_XJT(FAILSAFE_ROWS(1)), LABEL(Trainer), 0, TRAINER_CHANNELS_ROWS(), IF_TRAINER_ON(2)}); + MENU_TAB({ 0, 0, CASE_PCBTARANIS(0) 2, IF_PERSISTENT_TIMERS(0) 0, 0, 2, IF_PERSISTENT_TIMERS(0) 0, 0, 0, 1, 0,LABEL(Throttle), 0, 0, 0,LABEL(PreflightCheck), CASE_PCBTARANIS(0) 0, 7, POT_WARN_ITEMS(), NAVIGATION_LINE_BY_LINE|(NUM_STICKS+NUM_POTS+NUM_ROTARY_ENCODERS-1), LABEL(InternalModule), 0, IF_PORT1_ON(1), IF_PORT1_ON(IS_D8_RX(0) ? (uint8_t)1 : (uint8_t)2), IF_PORT1_ON(FAILSAFE_ROWS(0)), LABEL(ExternalModule), (g_model.externalModule==MODULE_TYPE_XJT || IS_MODULE_DSM2(EXTERNAL_MODULE)) ? (uint8_t)1 : (uint8_t)0, PORT2_CHANNELS_ROWS(), (IS_MODULE_XJT(1) && IS_D8_RX(1)) ? (uint8_t)1 : (IS_MODULE_PPM(1) || IS_MODULE_XJT(1) || IS_MODULE_DSM2(1)) ? (uint8_t)2 : HIDDEN_ROW, IF_PORT2_XJT(FAILSAFE_ROWS(1)), LABEL(Trainer), 0, TRAINER_CHANNELS_ROWS(), IF_TRAINER_ON(2)}); #elif defined(CPUM64) #define CURSOR_ON_CELL (true) #define MODEL_SETUP_MAX_LINES ((IS_PPM_PROTOCOL(protocol)||IS_DSM2_PROTOCOL(protocol)||IS_PXX_PROTOCOL(protocol)) ? 1+ITEM_MODEL_SETUP_MAX : ITEM_MODEL_SETUP_MAX) uint8_t protocol = g_model.protocol; - MENU_TAB({ 0, 0, CASE_PCBTARANIS(0) 2, IF_PERSISTENT_TIMERS(0) 0, 0, 2, IF_PERSISTENT_TIMERS(0) 0, 0, 0, 0, 0, 0, 0, 0, 0, 5, NUM_STICKS+NUM_POTS+NUM_ROTARY_ENCODERS-1, FIELD_PROTOCOL_MAX, 2 }); + MENU_TAB({ 0, 0, CASE_PCBTARANIS(0) 2, IF_PERSISTENT_TIMERS(0) 0, 0, 2, IF_PERSISTENT_TIMERS(0) 0, 0, 0, 0, 0,LABEL(Throttle), 0, 0, 0, 0, 5, NUM_STICKS+NUM_POTS+NUM_ROTARY_ENCODERS-1, FIELD_PROTOCOL_MAX, 2 }); #else #define CURSOR_ON_CELL (true) #define MODEL_SETUP_MAX_LINES ((IS_PPM_PROTOCOL(protocol)||IS_DSM2_PROTOCOL(protocol)||IS_PXX_PROTOCOL(protocol)) ? 1+ITEM_MODEL_SETUP_MAX : ITEM_MODEL_SETUP_MAX) uint8_t protocol = g_model.protocol; - MENU_TAB({ 0, 0, CASE_PCBTARANIS(0) 2, IF_PERSISTENT_TIMERS(0) 0, 0, 2, IF_PERSISTENT_TIMERS(0) 0, 0, 0, 1, 0, 0, 0, 0, 0, 6, NUM_STICKS+NUM_POTS+NUM_ROTARY_ENCODERS-1, FIELD_PROTOCOL_MAX, 2, CASE_PCBSKY9X(1) CASE_PCBSKY9X(2) }); + MENU_TAB({ 0, 0, CASE_PCBTARANIS(0) 2, IF_PERSISTENT_TIMERS(0) 0, 0, 2, IF_PERSISTENT_TIMERS(0) 0, 0, 0, 1, 0,LABEL(Throttle), 0, 0, 0, 0, 6, NUM_STICKS+NUM_POTS+NUM_ROTARY_ENCODERS-1, FIELD_PROTOCOL_MAX, 2, CASE_PCBSKY9X(1) CASE_PCBSKY9X(2) }); #endif if (!MENU_CHECK(menuTabModel, e_ModelSetup, MODEL_SETUP_MAX_LINES)) { @@ -1122,6 +1123,10 @@ void menuModelSetup(uint8_t event) g_model.trimInc = selectMenuItem(MODEL_SETUP_2ND_COLUMN, y, STR_TRIMINC, STR_VTRIMINC, g_model.trimInc, -2, 2, attr, event); break; + case ITEM_MODEL_THROTTLE_LABEL: + lcd_putsLeft(y, STR_THROTTLE_LABEL); + break; + case ITEM_MODEL_THROTTLE_REVERSED: g_model.throttleReversed = onoffMenuItem(g_model.throttleReversed, MODEL_SETUP_2ND_COLUMN, y, STR_THROTTLEREVERSE, attr, event ) ; break; @@ -1145,7 +1150,7 @@ void menuModelSetup(uint8_t event) #if defined(PCBTARANIS) case ITEM_MODEL_PREFLIGHT_LABEL: - lcd_putsLeft(y, TR_PREFLIGHT); + lcd_putsLeft(y, STR_PREFLIGHT); break; case ITEM_MODEL_CHECKLIST_DISPLAY: diff --git a/radio/src/translations.cpp b/radio/src/translations.cpp index 3042345f7..b30c2f26e 100644 --- a/radio/src/translations.cpp +++ b/radio/src/translations.cpp @@ -211,6 +211,7 @@ const pm_char STR_ALARMWARNING[] PROGMEM = TR_ALARMWARNING; #if defined(ROTARY_ENCODERS) const pm_char STR_RENAVIG[] PROGMEM = TR_RENAVIG; #endif +const pm_char STR_THROTTLE_LABEL[] PROGMEM = TR_THROTTLE_LABEL; const pm_char STR_THROTTLEREVERSE[] PROGMEM = TR_THROTTLEREVERSE; const pm_char STR_MINUTEBEEP[] PROGMEM = TR_MINUTEBEEP; const pm_char STR_BEEPCOUNTDOWN[] PROGMEM = TR_BEEPCOUNTDOWN; diff --git a/radio/src/translations.h b/radio/src/translations.h index 18c39df1a..ec882c0a2 100644 --- a/radio/src/translations.h +++ b/radio/src/translations.h @@ -370,6 +370,7 @@ extern const pm_char STR_INACTIVITYALARM[]; extern const pm_char STR_MEMORYWARNING[]; extern const pm_char STR_ALARMWARNING[]; extern const pm_char STR_RENAVIG[]; +extern const pm_char STR_THROTTLE_LABEL[]; extern const pm_char STR_THROTTLEREVERSE[]; extern const pm_char STR_MINUTEBEEP[]; extern const pm_char STR_BEEPCOUNTDOWN[]; @@ -611,7 +612,7 @@ extern const pm_char STR_SD_SECTORS[]; extern const pm_char STR_SD_SIZE[]; extern const pm_char STR_TYPE[]; extern const pm_char STR_GLOBAL_VARS[]; -extern const pm_char STR_GLOBAL_V[]; +extern const pm_char STR_GLOBAL_V[]; extern const pm_char STR_GLOBAL_VAR[]; extern const pm_char STR_OWN[]; extern const pm_char STR_ROTARY_ENCODER[]; @@ -687,6 +688,7 @@ extern const pm_char STR_VIEW_TEXT[]; extern const pm_char STR_VIEW_CHANNELS[]; extern const pm_char STR_VIEW_NOTES[]; extern const pm_char STR_POTWARNING[]; + extern const pm_char STR_PREFLIGHT[]; extern const pm_char STR_CHECKLIST[]; extern const pm_char STR_UART3MODE[]; extern const pm_char STR_POT1TYPE[]; diff --git a/radio/src/translations/en.h.txt b/radio/src/translations/en.h.txt index c22ecb8ed..b34cd334b 100644 --- a/radio/src/translations/en.h.txt +++ b/radio/src/translations/en.h.txt @@ -450,8 +450,8 @@ #define TR_ELIMITS TR("E.Limits", "Extended Limits") #define TR_ETRIMS TR("E.Trims", "Extended Trims") #define TR_TRIMINC "Trim Step" -#define TR_TTRACE TR("T-Source", "Throttle Source") -#define TR_TTRIM TR("T-Trim", "Throttle Trim") +#define TR_TTRACE INDENT "Source" +#define TR_TTRIM INDENT "Idle Trim" #define TR_BEEPCTR TR("Ctr Beep", "Center Beep") #define TR_PROTO TR(INDENT "Proto", INDENT "Protocol") #define TR_PPMFRAME TR("PPM frame", INDENT "PPM frame") @@ -514,7 +514,8 @@ #define TR_MEMORYWARNING INDENT"Memory Low" #define TR_ALARMWARNING INDENT"Sound Off" #define TR_RENAVIG "RotEnc Navig" -#define TR_THROTTLEREVERSE TR("T-Reverse", "Throttle reverse") +#define TR_THROTTLE_LABEL "Throttle" +#define TR_THROTTLEREVERSE INDENT "Reverse" #define TR_MINUTEBEEP TR(INDENT"Minute",INDENT"Minute call") #define TR_BEEPCOUNTDOWN INDENT"Countdown" #define TR_PERSISTENT TR(INDENT"Persist.",INDENT"Persistent") From 83651486f43b8b04d83b20fa640d944516852975 Mon Sep 17 00:00:00 2001 From: mhotar Date: Sat, 1 Mar 2014 02:08:45 +0100 Subject: [PATCH 006/285] Translations updated --- radio/src/translations/cz.h.txt | 16 +++++++++------- radio/src/translations/de.h.txt | 16 +++++++++------- radio/src/translations/es.h.txt | 16 +++++++++------- radio/src/translations/fi.h.txt | 16 +++++++++------- radio/src/translations/fr.h.txt | 16 +++++++++------- radio/src/translations/it.h.txt | 16 +++++++++------- radio/src/translations/pl.h.txt | 16 +++++++++------- radio/src/translations/pt.h.txt | 16 +++++++++------- radio/src/translations/se.h.txt | 16 +++++++++------- 9 files changed, 81 insertions(+), 63 deletions(-) diff --git a/radio/src/translations/cz.h.txt b/radio/src/translations/cz.h.txt index 4a6fba404..09d101a40 100644 --- a/radio/src/translations/cz.h.txt +++ b/radio/src/translations/cz.h.txt @@ -440,8 +440,8 @@ #define TR_ELIMITS TR("Limit+25%", "Kanál +/- 125%") #define TR_ETRIMS TR("širšíTrim", "Široký trim") #define TR_TRIMINC TR("KrokTrimu", "Krok trimu") -#define TR_TTRACE TR("StopaPlyn", "Stopař plynu") -#define TR_TTRIM TR("TrimPlynu", "TrimPlyn-volnoběh") +#define TR_TTRACE TR(INDENT "StopaPlyn", INDENT "Stopař plynu") +#define TR_TTRIM TR(INDENT "TrimPlynu", INDENT "Trim-volnoběh") #define TR_BEEPCTR "(\043)Středy" #define TR_PROTO INDENT"Protokol" #define TR_PPMFRAME "PPM frame" @@ -504,7 +504,8 @@ #define TR_MEMORYWARNING INDENT"Plná pamět'" #define TR_ALARMWARNING INDENT"Vypnutý zvuk" #define TR_RENAVIG "Navig. RotEnc" -#define TR_THROTTLEREVERSE TR("ReversPlyn", "Revers plynu") +#define TR_THROTTLE_LABEL "Plyn" +#define TR_THROTTLEREVERSE INDENT "Revers" #define TR_MINUTEBEEP TR(INDENT"Minuta", INDENT"Oznamovat minuty") #define TR_BEEPCOUNTDOWN INDENT"Odpočet" #define TR_PERSISTENT INDENT"Trvalé" @@ -513,9 +514,9 @@ #define TR_BLONBRIGHTNESS INDENT"Jas Zap." #define TR_BLOFFBRIGHTNESS INDENT"Jas Vyp." #define TR_SPLASHSCREEN "úvodníLogo" -#define TR_THROTTLEWARNING "(\043)Plyn" -#define TR_SWITCHWARNING "(\043)Spínače" -#define TR_POTWARNING TR("Pot Warn.","Pot Warning") +#define TR_THROTTLEWARNING TR("(\043)Plyn", INDENT "(\043)Plyn") +#define TR_SWITCHWARNING TR("(\043)Spínače", INDENT "(\043)Spínače") +#define TR_POTWARNING TR("Pot Warn.", INDENT "Pot Warning") #define TR_TIMEZONE "časové pásmo" #define TR_RXCHANNELORD TR("Pořadí kanálů", "Výchozí pořadí kanálů") #define TR_SLAVE "Podřízený" @@ -710,7 +711,8 @@ #define TR_LOWALARM INDENT "Nízký Alarm" #define TR_CRITICALALARM INDENT "Kritický Alarm" #define TR_PERSISTENT_MAH INDENT "Store mAh" -#define TR_CHECKLIST "Display Checklist" +#define TR_PREFLIGHT "Preflight Checks" +#define TR_CHECKLIST INDENT "Display Checklist" #define TR_FAS_OFFSET TR(INDENT "FAS Ofs", INDENT "FAS Offset") #define TR_UART3MODE "Serial port" #define TR_POT1TYPE "S1 Type" diff --git a/radio/src/translations/de.h.txt b/radio/src/translations/de.h.txt index 5d99446cd..eae9626d5 100644 --- a/radio/src/translations/de.h.txt +++ b/radio/src/translations/de.h.txt @@ -440,8 +440,8 @@ #define TR_ELIMITS TR("Erw.Limit","Erweit. Limits") #define TR_ETRIMS TR("Erw.Trims","Erweit. Trimmung") #define TR_TRIMINC TR("Trim Schr.","Trimm Schritte") -#define TR_TTRACE TR("Gasquelle","Gas Quelle") -#define TR_TTRIM TR("Gastrim","Gas Trimmung") +#define TR_TTRACE TR(INDENT "Gasquelle", INDENT "Gas Quelle") +#define TR_TTRIM TR(INDENT "Gastrim",INDENT "Gas Trimmung") #define TR_BEEPCTR TR("Mitt.Piep","Mittelst. Pieps") #define TR_PROTO TR(INDENT"Proto.",INDENT"Protokoll") #define TR_PPMFRAME "PPM Einst." @@ -504,7 +504,8 @@ #define TR_MEMORYWARNING INDENT"Speicher voll" #define TR_ALARMWARNING INDENT"Ton aus" #define TR_RENAVIG "Drehgeb. Navig." -#define TR_THROTTLEREVERSE TR("Gas invers", "Vollgas hinten?") //Änderung wg TH9x, Taranis +#define TR_THROTTLE_LABEL "Gas" +#define TR_THROTTLEREVERSE TR(INDENT "Gas invers", INDENT "Vollgas hinten?") //Änderung wg TH9x, Taranis #define TR_MINUTEBEEP TR(INDENT"Minute",INDENT"Jede Minute") #define TR_BEEPCOUNTDOWN INDENT"Countdown" #define TR_PERSISTENT TR(INDENT"M-Zeit",INDENT"Modell Zeit") @@ -513,9 +514,9 @@ #define TR_BLONBRIGHTNESS INDENT"An Helligkeit" #define TR_BLOFFBRIGHTNESS INDENT"Aus Helligkeit" #define TR_SPLASHSCREEN "Startbild" -#define TR_THROTTLEWARNING "Gas Alarm" -#define TR_SWITCHWARNING TR("Sch. Alarm","Schalter Alarm") -#define TR_POTWARNING TR("Pot Warn.","Pot Warning") +#define TR_THROTTLEWARNING TR("Gas Alarm", INDENT "Gas Alarm") +#define TR_SWITCHWARNING TR("Sch. Alarm",INDENT "Schalter Alarm") +#define TR_POTWARNING TR("Pot Warn.", INDENT "Pot Warning") #define TR_TIMEZONE TR("Zeitzone","GPS Zeit Zone") #define TR_RXCHANNELORD TR("Kanalanordnung","Kanalvoreinstellung") #define TR_SLAVE "Sch\205ler PPM1-8 als Ausgang" @@ -710,7 +711,8 @@ #define TR_LOWALARM INDENT "Low Alarm" #define TR_CRITICALALARM INDENT "Kritisch Alarm" #define TR_PERSISTENT_MAH INDENT "Store mAh" -#define TR_CHECKLIST "Display Checklist" +#define TR_PREFLIGHT "Preflight Checks" +#define TR_CHECKLIST INDENT "Display Checklist" #define TR_FAS_OFFSET TR(INDENT "FAS Ofs", INDENT "FAS Offset") #define TR_UART3MODE "Serial port" #define TR_POT1TYPE "S1 Type" diff --git a/radio/src/translations/es.h.txt b/radio/src/translations/es.h.txt index 44d96759a..c01910b4e 100644 --- a/radio/src/translations/es.h.txt +++ b/radio/src/translations/es.h.txt @@ -440,8 +440,8 @@ #define TR_ELIMITS TR("E.Limite","Ampliar Limites") #define TR_ETRIMS TR("E.Trims","Ampliar Trims") #define TR_TRIMINC "Paso Trim" -#define TR_TTRACE TR("Fuente-A","Fuente Acelerad") -#define TR_TTRIM TR("Trim-A","Trim Acelerad") +#define TR_TTRACE TR( INDENT "Fuente-A", INDENT "Fuente Acelerad") +#define TR_TTRIM TR(INDENT "Trim-A", INDENT "Trim Acelerad") #define TR_BEEPCTR TR("Ctr Beep","Center Beep") #define TR_PROTO TR(INDENT"Proto",INDENT"Protocol") #define TR_PPMFRAME "Trama PPM" @@ -504,7 +504,8 @@ #define TR_MEMORYWARNING INDENT"Memoria Baja" #define TR_ALARMWARNING INDENT"Sin Sonido" #define TR_RENAVIG "RotEnc Navig" -#define TR_THROTTLEREVERSE TR("Invert_Acel", "Invertir Acel.") +#define TR_THROTTLE_LABEL "Throttle" +#define TR_THROTTLEREVERSE TR(INDENT "Invert_Acel", INDENT "Invertir Acel.") #define TR_MINUTEBEEP TR(INDENT"Minuto",INDENT"Cada Minuto") #define TR_BEEPCOUNTDOWN INDENT"Cuentaatras" #define TR_PERSISTENT TR(INDENT"Persist.",INDENT"Persistente") @@ -513,9 +514,9 @@ #define TR_BLONBRIGHTNESS INDENT"MAS Brillo" #define TR_BLOFFBRIGHTNESS INDENT"MENOS Brillo" #define TR_SPLASHSCREEN "Ptalla.inicio" -#define TR_THROTTLEWARNING TR("Aviso-A", "Aviso Acelerador") -#define TR_SWITCHWARNING TR("Aviso-I", "Aviso Intrptor") -#define TR_POTWARNING TR("Pot Warn.","Pot Warning") +#define TR_THROTTLEWARNING TR("Aviso-A", INDENT "Aviso Acelerador") +#define TR_SWITCHWARNING TR("Aviso-I", INDENT "Aviso Intrptor") +#define TR_POTWARNING TR("Pot Warn.", INDENT "Pot Warning") #define TR_TIMEZONE TR("Zona Hora", "GPS Zona Hora") #define TR_RXCHANNELORD TR("Rx Orden canal", "Orden habitual canales") #define TR_SLAVE "Esclavo" @@ -710,7 +711,8 @@ #define TR_LOWALARM INDENT "Alarma baja" #define TR_CRITICALALARM INDENT "Alarma Critica" #define TR_PERSISTENT_MAH INDENT "Valor mAh" -#define TR_CHECKLIST "Display Checklist" +#define TR_PREFLIGHT "Preflight Checks" +#define TR_CHECKLIST INDENT "Display Checklist" #define TR_FAS_OFFSET TR(INDENT "FAS Ofs", INDENT "FAS Offset") #define TR_UART3MODE "Serial port" #define TR_POT1TYPE "S1 Type" diff --git a/radio/src/translations/fi.h.txt b/radio/src/translations/fi.h.txt index 6b1dea41a..41509b804 100644 --- a/radio/src/translations/fi.h.txt +++ b/radio/src/translations/fi.h.txt @@ -440,8 +440,8 @@ #define TR_ELIMITS TR("E.Limits", "Extended Limits") #define TR_ETRIMS TR("E.Trims", "Extended Trims") #define TR_TRIMINC "Trim Step" -#define TR_TTRACE TR("T-Source", "Throttle Source") -#define TR_TTRIM TR("T-Trim", "Throttle Trim") +#define TR_TTRACE TR(INDENT "T-Source", INDENT "Throttle Source") +#define TR_TTRIM TR(INDENT "T-Trim", INDENT "Throttle Trim") #define TR_BEEPCTR TR("Ctr Beep", "Center Beep") #define TR_PROTO TR(INDENT "Proto", INDENT "Protocol") #define TR_PPMFRAME TR("PPM frame", INDENT "PPM frame") @@ -504,7 +504,8 @@ #define TR_MEMORYWARNING INDENT"Memory Low" #define TR_ALARMWARNING INDENT"Sound Off" #define TR_RENAVIG "RotEnc Navig" -#define TR_THROTTLEREVERSE TR("T-Reverse", "Throttle reverse") +#define TR_THROTTLE_LABEL "Throttle" +#define TR_THROTTLEREVERSE TR(INDENT "T-Reverse", INDENT "Throttle reverse") #define TR_MINUTEBEEP TR(INDENT"Minute",INDENT"Minute call") #define TR_BEEPCOUNTDOWN INDENT"Countdown" #define TR_PERSISTENT TR(INDENT"Persist.",INDENT"Persistent") @@ -513,9 +514,9 @@ #define TR_BLONBRIGHTNESS INDENT"ON Brightness" #define TR_BLOFFBRIGHTNESS INDENT"OFF Brightness" #define TR_SPLASHSCREEN "Splash screen" -#define TR_THROTTLEWARNING TR("T-Warning","Throttle Warning") -#define TR_SWITCHWARNING TR("S-Warning","Switch Warning") -#define TR_POTWARNING TR("Pot Warn.","Pot Warning") +#define TR_THROTTLEWARNING TR("T-Warning", INDENT "Throttle Warning") +#define TR_SWITCHWARNING TR("S-Warning",INDENT "Switch Warning") +#define TR_POTWARNING TR("Pot Warn.",INDENT "Pot Warning") #define TR_TIMEZONE TR("Time Zone","GPS Time zone") #define TR_RXCHANNELORD TR("Rx Channel Ord","Default channel order") #define TR_SLAVE "Slave" @@ -710,7 +711,8 @@ #define TR_LOWALARM INDENT "Low Alarm" #define TR_CRITICALALARM INDENT "Critical Alarm" #define TR_PERSISTENT_MAH INDENT "Store mAh" -#define TR_CHECKLIST "Display Checklist" +#define TR_PREFLIGHT "Preflight Checks" +#define TR_CHECKLIST INDENT "Display Checklist" #define TR_FAS_OFFSET TR(INDENT "FAS Ofs", INDENT "FAS Offset") #define TR_UART3MODE "Serial port" #define TR_POT1TYPE "S1 Type" diff --git a/radio/src/translations/fr.h.txt b/radio/src/translations/fr.h.txt index a3b12102e..88135ba8b 100644 --- a/radio/src/translations/fr.h.txt +++ b/radio/src/translations/fr.h.txt @@ -440,8 +440,8 @@ #define TR_ELIMITS TR("Limites ét","Limites étendues") #define TR_ETRIMS TR("Trims ét.","Trims étendus") #define TR_TRIMINC TR("Pas Trim","Pas des trims") -#define TR_TTRACE "Source gaz" -#define TR_TTRIM "Trim gaz" +#define TR_TTRACE INDENT"Source gaz" +#define TR_TTRIM INDENT"Trim gaz" #define TR_BEEPCTR TR("Bips centr","Bips centrage") #define TR_PROTO TR(INDENT"Proto.",INDENT"Protocole") #define TR_PPMFRAME INDENT"Trame PPM" @@ -504,7 +504,8 @@ #define TR_MEMORYWARNING INDENT"Mémoire pleine" #define TR_ALARMWARNING TR(INDENT"Silence",INDENT"Sons désactivés") #define TR_RENAVIG "Navig EncRot" -#define TR_THROTTLEREVERSE TR("Inv. gaz","Inversion gaz") +#define TR_THROTTLE_LABEL "Gaz" +#define TR_THROTTLEREVERSE TR(INDENT"Inv. gaz",INDENT"Inversion gaz") #define TR_MINUTEBEEP TR(INDENT"Bip min.",INDENT"Annonces minutes") #define TR_BEEPCOUNTDOWN TR(INDENT"Bip fin",INDENT"Compte à rebours") #define TR_PERSISTENT TR(INDENT"Persist.",INDENT"Persistant") @@ -513,9 +514,9 @@ #define TR_BLONBRIGHTNESS INDENT"Luminosité ON" #define TR_BLOFFBRIGHTNESS INDENT"Luminosité OFF" #define TR_SPLASHSCREEN "Logo d'accueil" -#define TR_THROTTLEWARNING "Alerte gaz" -#define TR_SWITCHWARNING TR("Alerte int","Alerte interrupt.") -#define TR_POTWARNING TR("Alerte pot","Alerte potentiom.") +#define TR_THROTTLEWARNING TR("Alerte gaz",INDENT"Alerte gaz") +#define TR_SWITCHWARNING TR("Alerte int",INDENT"Alerte interrupt.") +#define TR_POTWARNING TR("Alerte pot",INDENT"Alerte potentiom.") #define TR_TIMEZONE "Fuseau horaire" #define TR_RXCHANNELORD TR("Ordre voies RX","Ordre des voies préféré") #define TR_SLAVE "Elève" @@ -710,7 +711,8 @@ #define TR_LOWALARM INDENT "Alarme basse" #define TR_CRITICALALARM INDENT "Alarme critique" #define TR_PERSISTENT_MAH TR(INDENT "Enr. mAh",INDENT "Enregistrer mAh") -#define TR_CHECKLIST "Afficher notes" +#define TR_PREFLIGHT "Preflight Checks" +#define TR_CHECKLIST INDENT"Afficher notes" #define TR_FAS_OFFSET TR(INDENT "Corr FAS", INDENT "Correction FAS") #define TR_UART3MODE "Port série" #define TR_POT1TYPE "Type S1" diff --git a/radio/src/translations/it.h.txt b/radio/src/translations/it.h.txt index 5b6857738..cba63389d 100644 --- a/radio/src/translations/it.h.txt +++ b/radio/src/translations/it.h.txt @@ -440,8 +440,8 @@ #define TR_ELIMITS TR("Limiti.E","Limiti Estesi") #define TR_ETRIMS TR("Trim Ext","Trim Estesi") #define TR_TRIMINC "Trim Step" -#define TR_TTRACE TR("T-Source","Throttle Source") -#define TR_TTRIM TR("T-Trim","Throttle Trim") +#define TR_TTRACE TR(INDENT "T-Source",INDENT "Throttle Source") +#define TR_TTRIM TR(INDENT "T-Trim",INDENT "Throttle Trim") #define TR_BEEPCTR TR("Ctr Beep","Center Beep") #define TR_PROTO TR(INDENT "Proto", INDENT "Protocollo") #define TR_PPMFRAME TR("PPM frame", INDENT "PPM frame") @@ -504,7 +504,8 @@ #define TR_MEMORYWARNING INDENT"Avviso memoria" #define TR_ALARMWARNING INDENT"Spento" #define TR_RENAVIG "Navig RotEnc " -#define TR_THROTTLEREVERSE TR("Thr inv.", "Throttle Inverso") +#define TR_THROTTLE_LABEL "Throttle" +#define TR_THROTTLEREVERSE TR(INDENT "Thr inv.", INDENT "Throttle Inverso") #define TR_MINUTEBEEP INDENT"Minuto" #define TR_BEEPCOUNTDOWN TR(INDENT"Conto rov",INDENT"Conto rovescia") #define TR_PERSISTENT TR(INDENT"Persist.",INDENT"Persistente") @@ -513,9 +514,9 @@ #define TR_BLONBRIGHTNESS TR(INDENT"Lumin. ON",INDENT"Luminosità ON") #define TR_BLOFFBRIGHTNESS TR(INDENT"Lumin. OFF",INDENT"Luminosità OFF") #define TR_SPLASHSCREEN TR("Schermo avvio", "Schermata di avvio") -#define TR_THROTTLEWARNING TR("All. Thr", "Allarme Throttle") -#define TR_SWITCHWARNING TR("Avv. Int.", "Avviso Interr.") -#define TR_POTWARNING TR("Pot Warn.","Pot Warning") +#define TR_THROTTLEWARNING TR("All. Thr", INDENT"Allarme Throttle") +#define TR_SWITCHWARNING TR("Avv. Int.", INDENT"Avviso Interr.") +#define TR_POTWARNING TR("Pot Warn.", INDENT"Pot Warning") #define TR_TIMEZONE "Ora locale" #define TR_RXCHANNELORD "Ordine ch RX" #define TR_SLAVE "Allievo" @@ -710,7 +711,8 @@ #define TR_LOWALARM INDENT "Allarme Basso" #define TR_CRITICALALARM INDENT "Allarme Critico" #define TR_PERSISTENT_MAH INDENT "Store mAh" -#define TR_CHECKLIST "Display Checklist" +#define TR_PREFLIGHT "Preflight Checks" +#define TR_CHECKLIST INDENT "Display Checklist" #define TR_FAS_OFFSET TR(INDENT "FAS Ofs", INDENT "FAS Offset") #define TR_UART3MODE "Serial port" #define TR_POT1TYPE "S1 Type" diff --git a/radio/src/translations/pl.h.txt b/radio/src/translations/pl.h.txt index 0a3bde330..f2434da46 100644 --- a/radio/src/translations/pl.h.txt +++ b/radio/src/translations/pl.h.txt @@ -440,8 +440,8 @@ #define TR_ELIMITS TR("Limit+25%", "Kanał +/- 125%") #define TR_ETRIMS TR("Trymery 100%", "Poszerzone Trymery") #define TR_TRIMINC TR("Krok Trymera", "Krok trymera") -#define TR_TTRACE TR("Źródło gazu", "Źródło gazu") -#define TR_TTRIM TR("Trymer gazu", "Trymer gazu") +#define TR_TTRACE TR(INDENT"Źródło gazu", INDENT"Źródło gazu") +#define TR_TTRIM TR(INDENT"Trymer gazu", INDENT"Trymer gazu") #define TR_BEEPCTR "(\043)Pikanie środka" #define TR_PROTO INDENT"Protokól" #define TR_PPMFRAME "Ramka PPM" @@ -504,7 +504,8 @@ #define TR_MEMORYWARNING INDENT"Pełna pamięć'" #define TR_ALARMWARNING INDENT"Wyłącz dźwięk" #define TR_RENAVIG "Nawigacja potencjometrem" -#define TR_THROTTLEREVERSE TR("Odwróć gaz", "Odwróć gaz") +#define TR_THROTTLE_LABEL "Throttle" +#define TR_THROTTLEREVERSE TR(INDENT"Odwróć gaz", INDENT"Odwróć gaz") #define TR_MINUTEBEEP TR(INDENT"Minuta", INDENT"Pik co minutę") #define TR_BEEPCOUNTDOWN TR(INDENT"Odliczanie", INDENT"Odliczanie") #define TR_PERSISTENT INDENT"Dokładny" @@ -513,9 +514,9 @@ #define TR_BLONBRIGHTNESS INDENT"Jasnośc wł." #define TR_BLOFFBRIGHTNESS INDENT"Jasność wył." #define TR_SPLASHSCREEN "Logo ekranu" -#define TR_THROTTLEWARNING "(\043)Gaz" -#define TR_SWITCHWARNING "(\043)Przełącznik" -#define TR_POTWARNING TR("Pot Warn.","Pot Warning") +#define TR_THROTTLEWARNING TR("(\043)Gaz",INDENT"(\043)Gaz") +#define TR_SWITCHWARNING TR("(\043)Przełącznik",INDENT"(\043)Przełącznik") +#define TR_POTWARNING TR("Pot Warn.",INDENT"Pot Warning") #define TR_TIMEZONE "Strefa czasowa" #define TR_RXCHANNELORD TR("Kolejność kanałów", "Bazowa kolejność kanałów") #define TR_SLAVE "Uczeń" @@ -710,7 +711,8 @@ #define TR_LOWALARM INDENT "Alarm niski" #define TR_CRITICALALARM INDENT "Alarm krytyczny" #define TR_PERSISTENT_MAH INDENT "Zapisz mAh" -#define TR_CHECKLIST "Display Checklist" +#define TR_PREFLIGHT "Preflight Checks" +#define TR_CHECKLIST INDENT"Display Checklist" #define TR_FAS_OFFSET TR(INDENT "FAS Ofs", INDENT "FAS Offset") #define TR_UART3MODE "Port szreg." #define TR_POT1TYPE "Typ S1" diff --git a/radio/src/translations/pt.h.txt b/radio/src/translations/pt.h.txt index f831cf0a1..8e8c17b2c 100644 --- a/radio/src/translations/pt.h.txt +++ b/radio/src/translations/pt.h.txt @@ -440,8 +440,8 @@ #define TR_ELIMITS "E.Limits" #define TR_ETRIMS "E.Trims" #define TR_TRIMINC "Trim Step" -#define TR_TTRACE "T-Trace" -#define TR_TTRIM "T-Trim" +#define TR_TTRACE INDENT"T-Trace" +#define TR_TTRIM INDENT"T-Trim" #define TR_BEEPCTR "Ctr Beep" #define TR_PROTO INDENT"Proto" #define TR_PPMFRAME "PPM frame" @@ -504,7 +504,8 @@ #define TR_MEMORYWARNING INDENT"Memoria Baixa" #define TR_ALARMWARNING INDENT"Som Off" #define TR_RENAVIG "RotEnc Navig" -#define TR_THROTTLEREVERSE "Inverte Acel." +#define TR_THROTTLE_LABEL "Throttle" +#define TR_THROTTLEREVERSE INDENT"Inverte Acel." #define TR_MINUTEBEEP INDENT"Beep Minuto" #define TR_BEEPCOUNTDOWN INDENT"Beep Regressivo" #define TR_PERSISTENT INDENT"Persist." @@ -513,9 +514,9 @@ #define TR_BLONBRIGHTNESS INDENT"ON Brightness" #define TR_BLOFFBRIGHTNESS INDENT"OFF Brightness" #define TR_SPLASHSCREEN "Splash screen" -#define TR_THROTTLEWARNING "Avisa Acel" -#define TR_SWITCHWARNING "Avisa Chav" -#define TR_POTWARNING TR("Pot Warn.","Pot Warning") +#define TR_THROTTLEWARNING TR("Avisa Acel",INDENT"Avisa Acel") +#define TR_SWITCHWARNING TR("Avisa Chav",INDENT"Avisa Chav") +#define TR_POTWARNING TR("Pot Warn.",INDENT"Pot Warning") #define TR_TIMEZONE "Time Zone" #define TR_RXCHANNELORD "Ordem Canal RX" #define TR_SLAVE "Escravo" @@ -710,7 +711,8 @@ #define TR_LOWALARM INDENT "Low Alarm" #define TR_CRITICALALARM INDENT "Critical Alarm" #define TR_PERSISTENT_MAH INDENT "Store mAh" -#define TR_CHECKLIST "Display Checklist" +#define TR_PREFLIGHT "Preflight Checks" +#define TR_CHECKLIST INDENT "Display Checklist" #define TR_FAS_OFFSET TR(INDENT "FAS Ofs", INDENT "FAS Offset") #define TR_UART3MODE "Serial port" #define TR_POT1TYPE "S1 Type" diff --git a/radio/src/translations/se.h.txt b/radio/src/translations/se.h.txt index 3e899b755..0fac67a01 100644 --- a/radio/src/translations/se.h.txt +++ b/radio/src/translations/se.h.txt @@ -440,8 +440,8 @@ #define TR_ELIMITS TR("Gränser++","Utökade Gränser") #define TR_ETRIMS TR("Trimmar++","Utökade Trimmar") #define TR_TRIMINC TR("Trimning","Trimökning") -#define TR_TTRACE "Följ Gas" -#define TR_TTRIM "Gastrim" +#define TR_TTRACE INDENT"Följ Gas" +#define TR_TTRIM INDENT"Gastrim" #define TR_BEEPCTR TR("Cent.pip", "Centerpip") #define TR_PROTO TR(INDENT"Proto",INDENT"Protokoll") #define TR_PPMFRAME "PPM-paket" @@ -504,7 +504,8 @@ #define TR_MEMORYWARNING INDENT"Lite Minne" #define TR_ALARMWARNING INDENT"Ljud Av" #define TR_RENAVIG "RotEnc Navig" -#define TR_THROTTLEREVERSE "Revers.Gas" +#define TR_THROTTLE_LABEL "Throttle" +#define TR_THROTTLEREVERSE INDENT"Revers.Gas" #define TR_MINUTEBEEP INDENT"Minutpip" #define TR_BEEPCOUNTDOWN INDENT"Räkna Ned" #define TR_PERSISTENT TR("Jämt på ",INDENT"Alltid På") @@ -513,9 +514,9 @@ #define TR_BLONBRIGHTNESS INDENT"På Ljusstyrka" #define TR_BLOFFBRIGHTNESS INDENT"Av Ljusstyrka" #define TR_SPLASHSCREEN "Startbild" -#define TR_THROTTLEWARNING "Gasvarning" -#define TR_SWITCHWARNING TR("Bryt.varn.","Brytarvarning") -#define TR_POTWARNING TR("Pot Warn.","Pot Warning") +#define TR_THROTTLEWARNING TR("Gasvarning",INDENT"Gasvarning") +#define TR_SWITCHWARNING TR("Bryt.varn.",INDENT"Brytarvarning") +#define TR_POTWARNING TR("Pot Warn.",INDENT"Pot Warning") #define TR_TIMEZONE TR("Tidszon","GPS Tidszon") #define TR_RXCHANNELORD "Kanaler i RX" #define TR_SLAVE "Elev" @@ -710,7 +711,8 @@ #define TR_LOWALARM INDENT "Låg-alarm" #define TR_CRITICALALARM INDENT "Kritiskt alarm" #define TR_PERSISTENT_MAH INDENT "Store mAh" -#define TR_CHECKLIST "Display Checklist" +#define TR_PREFLIGHT "Preflight Checks" +#define TR_CHECKLIST INDENT "Display Checklist" #define TR_FAS_OFFSET TR(INDENT "FAS Ofs", INDENT "FAS Offset") #define TR_UART3MODE "Serieporten" #define TR_POT1TYPE "S1-ratten" From 61bb02ceea619ba4e07a1e5e4745174d80751394 Mon Sep 17 00:00:00 2001 From: mhotar Date: Sat, 1 Mar 2014 23:32:05 +0100 Subject: [PATCH 007/285] Thr grouping for Taranis only --- radio/src/gui/menu_model.cpp | 8 +++++--- radio/src/translations.cpp | 2 +- radio/src/translations.h | 2 +- radio/src/translations/cz.h.txt | 6 +++--- radio/src/translations/de.h.txt | 6 +++--- radio/src/translations/en.h.txt | 6 +++--- radio/src/translations/es.h.txt | 6 +++--- radio/src/translations/fi.h.txt | 6 +++--- radio/src/translations/fr.h.txt | 6 +++--- radio/src/translations/it.h.txt | 6 +++--- radio/src/translations/pl.h.txt | 6 +++--- radio/src/translations/pt.h.txt | 6 +++--- radio/src/translations/se.h.txt | 6 +++--- 13 files changed, 37 insertions(+), 35 deletions(-) diff --git a/radio/src/gui/menu_model.cpp b/radio/src/gui/menu_model.cpp index da8b1ae88..5e42edc11 100644 --- a/radio/src/gui/menu_model.cpp +++ b/radio/src/gui/menu_model.cpp @@ -870,7 +870,7 @@ enum menuModelSetupItems { ITEM_MODEL_EXTENDED_LIMITS, ITEM_MODEL_EXTENDED_TRIMS, ITEM_MODEL_TRIM_INC, - ITEM_MODEL_THROTTLE_LABEL, + CASE_PCBTARANIS(ITEM_MODEL_THROTTLE_LABEL) ITEM_MODEL_THROTTLE_REVERSED, ITEM_MODEL_THROTTLE_TRACE, ITEM_MODEL_THROTTLE_TRIM, @@ -972,13 +972,13 @@ void menuModelSetup(uint8_t event) #define MODEL_SETUP_MAX_LINES ((IS_PPM_PROTOCOL(protocol)||IS_DSM2_PROTOCOL(protocol)||IS_PXX_PROTOCOL(protocol)) ? 1+ITEM_MODEL_SETUP_MAX : ITEM_MODEL_SETUP_MAX) uint8_t protocol = g_model.protocol; - MENU_TAB({ 0, 0, CASE_PCBTARANIS(0) 2, IF_PERSISTENT_TIMERS(0) 0, 0, 2, IF_PERSISTENT_TIMERS(0) 0, 0, 0, 0, 0,LABEL(Throttle), 0, 0, 0, 0, 5, NUM_STICKS+NUM_POTS+NUM_ROTARY_ENCODERS-1, FIELD_PROTOCOL_MAX, 2 }); + MENU_TAB({ 0, 0, CASE_PCBTARANIS(0) 2, IF_PERSISTENT_TIMERS(0) 0, 0, 2, IF_PERSISTENT_TIMERS(0) 0, 0, 0, 0, 0, 0, 0, 0, 0, 5, NUM_STICKS+NUM_POTS+NUM_ROTARY_ENCODERS-1, FIELD_PROTOCOL_MAX, 2 }); #else #define CURSOR_ON_CELL (true) #define MODEL_SETUP_MAX_LINES ((IS_PPM_PROTOCOL(protocol)||IS_DSM2_PROTOCOL(protocol)||IS_PXX_PROTOCOL(protocol)) ? 1+ITEM_MODEL_SETUP_MAX : ITEM_MODEL_SETUP_MAX) uint8_t protocol = g_model.protocol; - MENU_TAB({ 0, 0, CASE_PCBTARANIS(0) 2, IF_PERSISTENT_TIMERS(0) 0, 0, 2, IF_PERSISTENT_TIMERS(0) 0, 0, 0, 1, 0,LABEL(Throttle), 0, 0, 0, 0, 6, NUM_STICKS+NUM_POTS+NUM_ROTARY_ENCODERS-1, FIELD_PROTOCOL_MAX, 2, CASE_PCBSKY9X(1) CASE_PCBSKY9X(2) }); + MENU_TAB({ 0, 0, CASE_PCBTARANIS(0) 2, IF_PERSISTENT_TIMERS(0) 0, 0, 2, IF_PERSISTENT_TIMERS(0) 0, 0, 0, 1, 0, 0, 0, 0, 0, 6, NUM_STICKS+NUM_POTS+NUM_ROTARY_ENCODERS-1, FIELD_PROTOCOL_MAX, 2, CASE_PCBSKY9X(1) CASE_PCBSKY9X(2) }); #endif if (!MENU_CHECK(menuTabModel, e_ModelSetup, MODEL_SETUP_MAX_LINES)) { @@ -1123,9 +1123,11 @@ void menuModelSetup(uint8_t event) g_model.trimInc = selectMenuItem(MODEL_SETUP_2ND_COLUMN, y, STR_TRIMINC, STR_VTRIMINC, g_model.trimInc, -2, 2, attr, event); break; +#if defined(PCBTARANIS) case ITEM_MODEL_THROTTLE_LABEL: lcd_putsLeft(y, STR_THROTTLE_LABEL); break; +#endif case ITEM_MODEL_THROTTLE_REVERSED: g_model.throttleReversed = onoffMenuItem(g_model.throttleReversed, MODEL_SETUP_2ND_COLUMN, y, STR_THROTTLEREVERSE, attr, event ) ; diff --git a/radio/src/translations.cpp b/radio/src/translations.cpp index b30c2f26e..12dff79c1 100644 --- a/radio/src/translations.cpp +++ b/radio/src/translations.cpp @@ -211,7 +211,6 @@ const pm_char STR_ALARMWARNING[] PROGMEM = TR_ALARMWARNING; #if defined(ROTARY_ENCODERS) const pm_char STR_RENAVIG[] PROGMEM = TR_RENAVIG; #endif -const pm_char STR_THROTTLE_LABEL[] PROGMEM = TR_THROTTLE_LABEL; const pm_char STR_THROTTLEREVERSE[] PROGMEM = TR_THROTTLEREVERSE; const pm_char STR_MINUTEBEEP[] PROGMEM = TR_MINUTEBEEP; const pm_char STR_BEEPCOUNTDOWN[] PROGMEM = TR_BEEPCOUNTDOWN; @@ -502,6 +501,7 @@ const pm_char STR_VIEW_TEXT[] PROGMEM = "View text"; const pm_char STR_UART3MODE[] PROGMEM = TR_UART3MODE; const pm_char STR_POT1TYPE[] PROGMEM = TR_POT1TYPE; const pm_char STR_POT2TYPE[] PROGMEM = TR_POT2TYPE; + const pm_char STR_THROTTLE_LABEL[] PROGMEM = TR_THROTTLE_LABEL; #endif #if MENUS_LOCK == 1 diff --git a/radio/src/translations.h b/radio/src/translations.h index ec882c0a2..5154676b8 100644 --- a/radio/src/translations.h +++ b/radio/src/translations.h @@ -370,7 +370,6 @@ extern const pm_char STR_INACTIVITYALARM[]; extern const pm_char STR_MEMORYWARNING[]; extern const pm_char STR_ALARMWARNING[]; extern const pm_char STR_RENAVIG[]; -extern const pm_char STR_THROTTLE_LABEL[]; extern const pm_char STR_THROTTLEREVERSE[]; extern const pm_char STR_MINUTEBEEP[]; extern const pm_char STR_BEEPCOUNTDOWN[]; @@ -693,6 +692,7 @@ extern const pm_char STR_VIEW_TEXT[]; extern const pm_char STR_UART3MODE[]; extern const pm_char STR_POT1TYPE[]; extern const pm_char STR_POT2TYPE[]; + extern const pm_char STR_THROTTLE_LABEL[]; #endif #if MENUS_LOCK == 1 diff --git a/radio/src/translations/cz.h.txt b/radio/src/translations/cz.h.txt index 09d101a40..91b85620d 100644 --- a/radio/src/translations/cz.h.txt +++ b/radio/src/translations/cz.h.txt @@ -440,8 +440,8 @@ #define TR_ELIMITS TR("Limit+25%", "Kanál +/- 125%") #define TR_ETRIMS TR("širšíTrim", "Široký trim") #define TR_TRIMINC TR("KrokTrimu", "Krok trimu") -#define TR_TTRACE TR(INDENT "StopaPlyn", INDENT "Stopař plynu") -#define TR_TTRIM TR(INDENT "TrimPlynu", INDENT "Trim-volnoběh") +#define TR_TTRACE TR("StopaPlyn", INDENT "Stopař plynu") +#define TR_TTRIM TR("TrimPlynu", INDENT "Trim-volnoběh") #define TR_BEEPCTR "(\043)Středy" #define TR_PROTO INDENT"Protokol" #define TR_PPMFRAME "PPM frame" @@ -505,7 +505,7 @@ #define TR_ALARMWARNING INDENT"Vypnutý zvuk" #define TR_RENAVIG "Navig. RotEnc" #define TR_THROTTLE_LABEL "Plyn" -#define TR_THROTTLEREVERSE INDENT "Revers" +#define TR_THROTTLEREVERSE TR("ReversPlyn", INDENT"Revers plynu") #define TR_MINUTEBEEP TR(INDENT"Minuta", INDENT"Oznamovat minuty") #define TR_BEEPCOUNTDOWN INDENT"Odpočet" #define TR_PERSISTENT INDENT"Trvalé" diff --git a/radio/src/translations/de.h.txt b/radio/src/translations/de.h.txt index eae9626d5..e93fcd68f 100644 --- a/radio/src/translations/de.h.txt +++ b/radio/src/translations/de.h.txt @@ -440,8 +440,8 @@ #define TR_ELIMITS TR("Erw.Limit","Erweit. Limits") #define TR_ETRIMS TR("Erw.Trims","Erweit. Trimmung") #define TR_TRIMINC TR("Trim Schr.","Trimm Schritte") -#define TR_TTRACE TR(INDENT "Gasquelle", INDENT "Gas Quelle") -#define TR_TTRIM TR(INDENT "Gastrim",INDENT "Gas Trimmung") +#define TR_TTRACE TR("Gasquelle", INDENT "Gas Quelle") +#define TR_TTRIM TR("Gastrim",INDENT "Gas Trimmung") #define TR_BEEPCTR TR("Mitt.Piep","Mittelst. Pieps") #define TR_PROTO TR(INDENT"Proto.",INDENT"Protokoll") #define TR_PPMFRAME "PPM Einst." @@ -505,7 +505,7 @@ #define TR_ALARMWARNING INDENT"Ton aus" #define TR_RENAVIG "Drehgeb. Navig." #define TR_THROTTLE_LABEL "Gas" -#define TR_THROTTLEREVERSE TR(INDENT "Gas invers", INDENT "Vollgas hinten?") //Änderung wg TH9x, Taranis +#define TR_THROTTLEREVERSE TR("Gas invers", INDENT "Vollgas hinten?") //Änderung wg TH9x, Taranis #define TR_MINUTEBEEP TR(INDENT"Minute",INDENT"Jede Minute") #define TR_BEEPCOUNTDOWN INDENT"Countdown" #define TR_PERSISTENT TR(INDENT"M-Zeit",INDENT"Modell Zeit") diff --git a/radio/src/translations/en.h.txt b/radio/src/translations/en.h.txt index b34cd334b..a7c5f9938 100644 --- a/radio/src/translations/en.h.txt +++ b/radio/src/translations/en.h.txt @@ -450,8 +450,8 @@ #define TR_ELIMITS TR("E.Limits", "Extended Limits") #define TR_ETRIMS TR("E.Trims", "Extended Trims") #define TR_TRIMINC "Trim Step" -#define TR_TTRACE INDENT "Source" -#define TR_TTRIM INDENT "Idle Trim" +#define TR_TTRACE TR("T-Source", INDENT "Source") +#define TR_TTRIM TR("T-IdleTrim", INDENT "Idle Trim") #define TR_BEEPCTR TR("Ctr Beep", "Center Beep") #define TR_PROTO TR(INDENT "Proto", INDENT "Protocol") #define TR_PPMFRAME TR("PPM frame", INDENT "PPM frame") @@ -515,7 +515,7 @@ #define TR_ALARMWARNING INDENT"Sound Off" #define TR_RENAVIG "RotEnc Navig" #define TR_THROTTLE_LABEL "Throttle" -#define TR_THROTTLEREVERSE INDENT "Reverse" +#define TR_THROTTLEREVERSE TR("T-Reverse", INDENT "Reverse") #define TR_MINUTEBEEP TR(INDENT"Minute",INDENT"Minute call") #define TR_BEEPCOUNTDOWN INDENT"Countdown" #define TR_PERSISTENT TR(INDENT"Persist.",INDENT"Persistent") diff --git a/radio/src/translations/es.h.txt b/radio/src/translations/es.h.txt index c01910b4e..d361be05b 100644 --- a/radio/src/translations/es.h.txt +++ b/radio/src/translations/es.h.txt @@ -440,8 +440,8 @@ #define TR_ELIMITS TR("E.Limite","Ampliar Limites") #define TR_ETRIMS TR("E.Trims","Ampliar Trims") #define TR_TRIMINC "Paso Trim" -#define TR_TTRACE TR( INDENT "Fuente-A", INDENT "Fuente Acelerad") -#define TR_TTRIM TR(INDENT "Trim-A", INDENT "Trim Acelerad") +#define TR_TTRACE TR("Fuente-A", INDENT "Fuente Acelerad") +#define TR_TTRIM TR("Trim-A", INDENT "Trim Acelerad") #define TR_BEEPCTR TR("Ctr Beep","Center Beep") #define TR_PROTO TR(INDENT"Proto",INDENT"Protocol") #define TR_PPMFRAME "Trama PPM" @@ -505,7 +505,7 @@ #define TR_ALARMWARNING INDENT"Sin Sonido" #define TR_RENAVIG "RotEnc Navig" #define TR_THROTTLE_LABEL "Throttle" -#define TR_THROTTLEREVERSE TR(INDENT "Invert_Acel", INDENT "Invertir Acel.") +#define TR_THROTTLEREVERSE TR("Invert_Acel", INDENT "Invertir Acel.") #define TR_MINUTEBEEP TR(INDENT"Minuto",INDENT"Cada Minuto") #define TR_BEEPCOUNTDOWN INDENT"Cuentaatras" #define TR_PERSISTENT TR(INDENT"Persist.",INDENT"Persistente") diff --git a/radio/src/translations/fi.h.txt b/radio/src/translations/fi.h.txt index 41509b804..d0541e7f2 100644 --- a/radio/src/translations/fi.h.txt +++ b/radio/src/translations/fi.h.txt @@ -440,8 +440,8 @@ #define TR_ELIMITS TR("E.Limits", "Extended Limits") #define TR_ETRIMS TR("E.Trims", "Extended Trims") #define TR_TRIMINC "Trim Step" -#define TR_TTRACE TR(INDENT "T-Source", INDENT "Throttle Source") -#define TR_TTRIM TR(INDENT "T-Trim", INDENT "Throttle Trim") +#define TR_TTRACE TR("T-Source", INDENT "Throttle Source") +#define TR_TTRIM TR("T-Trim", INDENT "Throttle Trim") #define TR_BEEPCTR TR("Ctr Beep", "Center Beep") #define TR_PROTO TR(INDENT "Proto", INDENT "Protocol") #define TR_PPMFRAME TR("PPM frame", INDENT "PPM frame") @@ -505,7 +505,7 @@ #define TR_ALARMWARNING INDENT"Sound Off" #define TR_RENAVIG "RotEnc Navig" #define TR_THROTTLE_LABEL "Throttle" -#define TR_THROTTLEREVERSE TR(INDENT "T-Reverse", INDENT "Throttle reverse") +#define TR_THROTTLEREVERSE TR("T-Reverse", INDENT "Throttle reverse") #define TR_MINUTEBEEP TR(INDENT"Minute",INDENT"Minute call") #define TR_BEEPCOUNTDOWN INDENT"Countdown" #define TR_PERSISTENT TR(INDENT"Persist.",INDENT"Persistent") diff --git a/radio/src/translations/fr.h.txt b/radio/src/translations/fr.h.txt index 88135ba8b..6fec8a7d7 100644 --- a/radio/src/translations/fr.h.txt +++ b/radio/src/translations/fr.h.txt @@ -440,8 +440,8 @@ #define TR_ELIMITS TR("Limites ét","Limites étendues") #define TR_ETRIMS TR("Trims ét.","Trims étendus") #define TR_TRIMINC TR("Pas Trim","Pas des trims") -#define TR_TTRACE INDENT"Source gaz" -#define TR_TTRIM INDENT"Trim gaz" +#define TR_TTRACE TR("Source gaz",INDENT"Source gaz") +#define TR_TTRIM TR("Trim gaz",INDENT"Trim gaz") #define TR_BEEPCTR TR("Bips centr","Bips centrage") #define TR_PROTO TR(INDENT"Proto.",INDENT"Protocole") #define TR_PPMFRAME INDENT"Trame PPM" @@ -505,7 +505,7 @@ #define TR_ALARMWARNING TR(INDENT"Silence",INDENT"Sons désactivés") #define TR_RENAVIG "Navig EncRot" #define TR_THROTTLE_LABEL "Gaz" -#define TR_THROTTLEREVERSE TR(INDENT"Inv. gaz",INDENT"Inversion gaz") +#define TR_THROTTLEREVERSE TR("Inv. gaz",INDENT"Inversion gaz") #define TR_MINUTEBEEP TR(INDENT"Bip min.",INDENT"Annonces minutes") #define TR_BEEPCOUNTDOWN TR(INDENT"Bip fin",INDENT"Compte à rebours") #define TR_PERSISTENT TR(INDENT"Persist.",INDENT"Persistant") diff --git a/radio/src/translations/it.h.txt b/radio/src/translations/it.h.txt index cba63389d..7e3283647 100644 --- a/radio/src/translations/it.h.txt +++ b/radio/src/translations/it.h.txt @@ -440,8 +440,8 @@ #define TR_ELIMITS TR("Limiti.E","Limiti Estesi") #define TR_ETRIMS TR("Trim Ext","Trim Estesi") #define TR_TRIMINC "Trim Step" -#define TR_TTRACE TR(INDENT "T-Source",INDENT "Throttle Source") -#define TR_TTRIM TR(INDENT "T-Trim",INDENT "Throttle Trim") +#define TR_TTRACE TR("T-Source",INDENT "Throttle Source") +#define TR_TTRIM TR("T-Trim",INDENT "Throttle Trim") #define TR_BEEPCTR TR("Ctr Beep","Center Beep") #define TR_PROTO TR(INDENT "Proto", INDENT "Protocollo") #define TR_PPMFRAME TR("PPM frame", INDENT "PPM frame") @@ -505,7 +505,7 @@ #define TR_ALARMWARNING INDENT"Spento" #define TR_RENAVIG "Navig RotEnc " #define TR_THROTTLE_LABEL "Throttle" -#define TR_THROTTLEREVERSE TR(INDENT "Thr inv.", INDENT "Throttle Inverso") +#define TR_THROTTLEREVERSE TR("Thr inv.", INDENT "Throttle Inverso") #define TR_MINUTEBEEP INDENT"Minuto" #define TR_BEEPCOUNTDOWN TR(INDENT"Conto rov",INDENT"Conto rovescia") #define TR_PERSISTENT TR(INDENT"Persist.",INDENT"Persistente") diff --git a/radio/src/translations/pl.h.txt b/radio/src/translations/pl.h.txt index f2434da46..065201e6d 100644 --- a/radio/src/translations/pl.h.txt +++ b/radio/src/translations/pl.h.txt @@ -440,8 +440,8 @@ #define TR_ELIMITS TR("Limit+25%", "Kanał +/- 125%") #define TR_ETRIMS TR("Trymery 100%", "Poszerzone Trymery") #define TR_TRIMINC TR("Krok Trymera", "Krok trymera") -#define TR_TTRACE TR(INDENT"Źródło gazu", INDENT"Źródło gazu") -#define TR_TTRIM TR(INDENT"Trymer gazu", INDENT"Trymer gazu") +#define TR_TTRACE TR("Źródło gazu", INDENT"Źródło gazu") +#define TR_TTRIM TR("Trymer gazu", INDENT"Trymer gazu") #define TR_BEEPCTR "(\043)Pikanie środka" #define TR_PROTO INDENT"Protokól" #define TR_PPMFRAME "Ramka PPM" @@ -505,7 +505,7 @@ #define TR_ALARMWARNING INDENT"Wyłącz dźwięk" #define TR_RENAVIG "Nawigacja potencjometrem" #define TR_THROTTLE_LABEL "Throttle" -#define TR_THROTTLEREVERSE TR(INDENT"Odwróć gaz", INDENT"Odwróć gaz") +#define TR_THROTTLEREVERSE TR("Odwróć gaz", INDENT"Odwróć gaz") #define TR_MINUTEBEEP TR(INDENT"Minuta", INDENT"Pik co minutę") #define TR_BEEPCOUNTDOWN TR(INDENT"Odliczanie", INDENT"Odliczanie") #define TR_PERSISTENT INDENT"Dokładny" diff --git a/radio/src/translations/pt.h.txt b/radio/src/translations/pt.h.txt index 8e8c17b2c..aa6662795 100644 --- a/radio/src/translations/pt.h.txt +++ b/radio/src/translations/pt.h.txt @@ -440,8 +440,8 @@ #define TR_ELIMITS "E.Limits" #define TR_ETRIMS "E.Trims" #define TR_TRIMINC "Trim Step" -#define TR_TTRACE INDENT"T-Trace" -#define TR_TTRIM INDENT"T-Trim" +#define TR_TTRACE TR("T-Trace",INDENT"T-Trace") +#define TR_TTRIM TR("T-Trim",INDENT"T-Trim") #define TR_BEEPCTR "Ctr Beep" #define TR_PROTO INDENT"Proto" #define TR_PPMFRAME "PPM frame" @@ -505,7 +505,7 @@ #define TR_ALARMWARNING INDENT"Som Off" #define TR_RENAVIG "RotEnc Navig" #define TR_THROTTLE_LABEL "Throttle" -#define TR_THROTTLEREVERSE INDENT"Inverte Acel." +#define TR_THROTTLEREVERSE TR("Inverte Acel.",INDENT"Inverte Acel.") #define TR_MINUTEBEEP INDENT"Beep Minuto" #define TR_BEEPCOUNTDOWN INDENT"Beep Regressivo" #define TR_PERSISTENT INDENT"Persist." diff --git a/radio/src/translations/se.h.txt b/radio/src/translations/se.h.txt index 0fac67a01..024726df1 100644 --- a/radio/src/translations/se.h.txt +++ b/radio/src/translations/se.h.txt @@ -440,8 +440,8 @@ #define TR_ELIMITS TR("Gränser++","Utökade Gränser") #define TR_ETRIMS TR("Trimmar++","Utökade Trimmar") #define TR_TRIMINC TR("Trimning","Trimökning") -#define TR_TTRACE INDENT"Följ Gas" -#define TR_TTRIM INDENT"Gastrim" +#define TR_TTRACE TR("Följ Gas",INDENT"Följ Gas") +#define TR_TTRIM TR("Gastrim",INDENT"Gastrim") #define TR_BEEPCTR TR("Cent.pip", "Centerpip") #define TR_PROTO TR(INDENT"Proto",INDENT"Protokoll") #define TR_PPMFRAME "PPM-paket" @@ -505,7 +505,7 @@ #define TR_ALARMWARNING INDENT"Ljud Av" #define TR_RENAVIG "RotEnc Navig" #define TR_THROTTLE_LABEL "Throttle" -#define TR_THROTTLEREVERSE INDENT"Revers.Gas" +#define TR_THROTTLEREVERSE TR("Revers.Gas",INDENT"Revers.Gas") #define TR_MINUTEBEEP INDENT"Minutpip" #define TR_BEEPCOUNTDOWN INDENT"Räkna Ned" #define TR_PERSISTENT TR("Jämt på ",INDENT"Alltid På") From b90cff13b4e59590963c26d26afe342c704a8e0a Mon Sep 17 00:00:00 2001 From: bsongis Date: Mon, 3 Mar 2014 17:57:36 +0100 Subject: [PATCH 008/285] Some duplicated files removed --- radio/bootloader/{makefile => Makefile} | 36 +- radio/bootloader/boot.cpp | 2 +- radio/bootloader/include/usbd_desc.h | 120 -- radio/bootloader/usb/usb_bsp.c | 135 -- radio/bootloader/usb/usb_core.c | 2162 ----------------------- radio/bootloader/usb/usb_dcd.c | 478 ----- radio/bootloader/usb/usb_dcd_int.c | 869 --------- radio/bootloader/usb/usbd_core.c | 506 ------ radio/bootloader/usb/usbd_desc.c | 223 --- radio/bootloader/usb/usbd_ioreq.c | 244 --- radio/bootloader/usb/usbd_msc_bot.c | 400 ----- radio/bootloader/usb/usbd_msc_core.c | 496 ------ radio/bootloader/usb/usbd_msc_data.c | 134 -- radio/bootloader/usb/usbd_msc_scsi.c | 734 -------- radio/bootloader/usb/usbd_req.c | 868 --------- 15 files changed, 19 insertions(+), 7388 deletions(-) rename radio/bootloader/{makefile => Makefile} (85%) delete mode 100644 radio/bootloader/include/usbd_desc.h delete mode 100644 radio/bootloader/usb/usb_bsp.c delete mode 100644 radio/bootloader/usb/usb_core.c delete mode 100644 radio/bootloader/usb/usb_dcd.c delete mode 100644 radio/bootloader/usb/usb_dcd_int.c delete mode 100644 radio/bootloader/usb/usbd_core.c delete mode 100644 radio/bootloader/usb/usbd_desc.c delete mode 100644 radio/bootloader/usb/usbd_ioreq.c delete mode 100644 radio/bootloader/usb/usbd_msc_bot.c delete mode 100644 radio/bootloader/usb/usbd_msc_core.c delete mode 100644 radio/bootloader/usb/usbd_msc_data.c delete mode 100644 radio/bootloader/usb/usbd_msc_scsi.c delete mode 100644 radio/bootloader/usb/usbd_req.c diff --git a/radio/bootloader/makefile b/radio/bootloader/Makefile similarity index 85% rename from radio/bootloader/makefile rename to radio/bootloader/Makefile index c046f1c2e..9e61997ab 100644 --- a/radio/bootloader/makefile +++ b/radio/bootloader/Makefile @@ -123,24 +123,24 @@ endif UADEFS = ifeq ($(PCB), TARANIS) -SRC = system_stm32f2xx.c \ - stm32f2xx_rcc.c \ - stm32f2xx_gpio.c \ - stm32f2xx_spi.c \ - misc.c \ - ccsbcs.c \ - usb/usb_core.c \ - usb/usb_dcd.c \ - usb/usb_dcd_int.c \ - usb/usbd_core.c \ - usb/usbd_ioreq.c \ - usb/usbd_req.c \ - usb/usbd_msc_data.c \ - usb/usbd_msc_scsi.c \ - usb/usbd_msc_bot.c \ - usb/usbd_msc_core.c \ - usb/usbd_desc.c \ - usb/usb_bsp.c +SRC = system_stm32f2xx.c \ + stm32f2xx_rcc.c \ + stm32f2xx_gpio.c \ + stm32f2xx_spi.c \ + misc.c \ + ccsbcs.c \ + ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/src/usb_core.c \ + ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/src/usb_dcd.c \ + ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/src/usb_dcd_int.c \ + ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_core.c \ + ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_ioreq.c \ + ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_req.c \ + ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_data.c \ + ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_scsi.c \ + ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_bot.c \ + ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_core.c \ + ../src/targets/taranis/usbd_desc.c \ + ../src/targets/taranis/usb_bsp.c CPPSRC = aspi.cpp \ lcd_driver.cpp \ diff --git a/radio/bootloader/boot.cpp b/radio/bootloader/boot.cpp index 01a1dbdca..ae8627f11 100644 --- a/radio/bootloader/boot.cpp +++ b/radio/bootloader/boot.cpp @@ -68,7 +68,7 @@ extern "C" { #include "usb_dcd_int.h" #include "usb_bsp.h" -#include "usbd_desc.h" +#include "../src/targets/taranis/usbd_desc.h" #include "usbd_msc_core.h" #include "usbd_usr.h" } diff --git a/radio/bootloader/include/usbd_desc.h b/radio/bootloader/include/usbd_desc.h deleted file mode 100644 index 75b694e76..000000000 --- a/radio/bootloader/include/usbd_desc.h +++ /dev/null @@ -1,120 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_desc.h - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief header file for the usbd_desc.c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#ifndef __USB_DESC_H -#define __USB_DESC_H - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_def.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USB_DESC - * @brief general defines for the usb device library file - * @{ - */ - -/** @defgroup USB_DESC_Exported_Defines - * @{ - */ -#define USB_DEVICE_DESCRIPTOR_TYPE 0x01 -#define USB_CONFIGURATION_DESCRIPTOR_TYPE 0x02 -#define USB_STRING_DESCRIPTOR_TYPE 0x03 -#define USB_INTERFACE_DESCRIPTOR_TYPE 0x04 -#define USB_ENDPOINT_DESCRIPTOR_TYPE 0x05 -#define USB_SIZ_DEVICE_DESC 18 -#define USB_SIZ_STRING_LANGID 4 - -/** - * @} - */ - - -/** @defgroup USBD_DESC_Exported_TypesDefinitions - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USBD_DESC_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBD_DESC_Exported_Variables - * @{ - */ -extern uint8_t USBD_DeviceDesc [USB_SIZ_DEVICE_DESC]; -extern uint8_t USBD_StrDesc[USB_MAX_STR_DESC_SIZ]; -extern uint8_t USBD_OtherSpeedCfgDesc[USB_LEN_CFG_DESC]; -extern uint8_t USBD_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC]; -extern uint8_t USBD_LangIDDesc[USB_SIZ_STRING_LANGID]; -extern USBD_DEVICE USR_desc; -/** - * @} - */ - -/** @defgroup USBD_DESC_Exported_FunctionsPrototype - * @{ - */ - - -uint8_t * USBD_USR_DeviceDescriptor( uint8_t speed , uint16_t *length); -uint8_t * USBD_USR_LangIDStrDescriptor( uint8_t speed , uint16_t *length); -uint8_t * USBD_USR_ManufacturerStrDescriptor ( uint8_t speed , uint16_t *length); -uint8_t * USBD_USR_ProductStrDescriptor ( uint8_t speed , uint16_t *length); -uint8_t * USBD_USR_SerialStrDescriptor( uint8_t speed , uint16_t *length); -uint8_t * USBD_USR_ConfigStrDescriptor( uint8_t speed , uint16_t *length); -uint8_t * USBD_USR_InterfaceStrDescriptor( uint8_t speed , uint16_t *length); - -#ifdef USB_SUPPORT_USER_STRING_DESC -uint8_t * USBD_USR_USRStringDesc (uint8_t speed, uint8_t idx , uint16_t *length); -#endif /* USB_SUPPORT_USER_STRING_DESC */ - -/** - * @} - */ - -#endif /* __USBD_DESC_H */ - -/** - * @} - */ - -/** -* @} -*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/usb/usb_bsp.c b/radio/bootloader/usb/usb_bsp.c deleted file mode 100644 index bd43c8a0f..000000000 --- a/radio/bootloader/usb/usb_bsp.c +++ /dev/null @@ -1,135 +0,0 @@ -/** - ****************************************************************************** - * @file usb_bsp.c - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief This file is responsible to offer board support package and is - * configurable by user. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_rcc.h" -#include "stm32f2xx_gpio.h" -#include "misc.h" -#include "usb_bsp.h" -#include "usbd_conf.h" - -extern uint32_t SystemCoreClock; - -/** -* @brief USB_OTG_BSP_Init -* Initilizes BSP configurations -* @param None -* @retval None -*/ - -void USB_OTG_BSP_Init(USB_OTG_CORE_HANDLE *pdev) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - RCC_AHB1PeriphClockCmd( RCC_AHB1Periph_GPIOA , ENABLE); - - /* Configure SOF ID DM DP Pins */ - GPIO_InitStructure.GPIO_Pin = // GPIO_Pin_8 | - GPIO_Pin_11 | - GPIO_Pin_12; - - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ; - GPIO_Init(GPIOA, &GPIO_InitStructure); - - //GPIO_PinAFConfig(GPIOA,GPIO_PinSource8,GPIO_AF_OTG1_FS) ; - GPIO_PinAFConfig(GPIOA,GPIO_PinSource11,GPIO_AF_OTG1_FS) ; - GPIO_PinAFConfig(GPIOA,GPIO_PinSource12,GPIO_AF_OTG1_FS) ; - - /* Configure VBUS Pin */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ; - GPIO_Init(GPIOA, &GPIO_InitStructure); - -/* // Configure ID pin - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; - GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_PinAFConfig(GPIOA,GPIO_PinSource10,GPIO_AF_OTG1_FS) ; -*/ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_OTG_FS, ENABLE) ; -} -/** -* @brief USB_OTG_BSP_EnableInterrupt -* Enabele USB Global interrupt -* @param None -* @retval None -*/ -void USB_OTG_BSP_EnableInterrupt(USB_OTG_CORE_HANDLE *pdev) -{ - NVIC_InitTypeDef NVIC_InitStructure; - - NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1); - NVIC_InitStructure.NVIC_IRQChannel = OTG_FS_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); -} -/** -* @brief USB_OTG_BSP_uDelay -* This function provides delay time in micro sec -* @param usec : Value of delay required in micro sec -* @retval None -*/ -void USB_OTG_BSP_uDelay (const uint32_t usec) -{ - uint32_t count = 0; - const uint32_t utime = ((SystemCoreClock/1000000) * usec); - do - { - if ( ++count > utime ) - { - return ; - } - } - while (1); -} - - -/** -* @brief USB_OTG_BSP_mDelay -* This function provides delay time in milli sec -* @param msec : Value of delay required in milli sec -* @retval None -*/ -void USB_OTG_BSP_mDelay (const uint32_t msec) -{ - USB_OTG_BSP_uDelay(msec * 1000); -} - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/usb/usb_core.c b/radio/bootloader/usb/usb_core.c deleted file mode 100644 index 12a207d81..000000000 --- a/radio/bootloader/usb/usb_core.c +++ /dev/null @@ -1,2162 +0,0 @@ -/** - ****************************************************************************** - * @file usb_core.c - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief USB-OTG Core Layer - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_core.h" -#include "usb_bsp.h" - - -/** @addtogroup USB_OTG_DRIVER -* @{ -*/ - -/** @defgroup USB_CORE -* @brief This file includes the USB-OTG Core Layer -* @{ -*/ - - -/** @defgroup USB_CORE_Private_Defines -* @{ -*/ - -/** -* @} -*/ - - -/** @defgroup USB_CORE_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - - -/** @defgroup USB_CORE_Private_Macros -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_CORE_Private_Variables -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_CORE_Private_FunctionPrototypes -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_CORE_Private_Functions -* @{ -*/ - -/** -* @brief USB_OTG_EnableCommonInt -* Initializes the commmon interrupts, used in both device and modes -* @param pdev : Selected device -* @retval None -*/ -static void USB_OTG_EnableCommonInt(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTMSK_TypeDef int_mask; - - int_mask.d32 = 0; - /* Clear any pending USB_OTG Interrupts */ -#ifndef USE_OTG_MODE - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GOTGINT, 0xFFFFFFFF); -#endif - /* Clear any pending interrupts */ - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, 0xBFFFFFFF); - /* Enable the interrupts in the INTMSK */ - int_mask.b.wkupintr = 1; - int_mask.b.usbsuspend = 1; - -#ifdef USE_OTG_MODE - int_mask.b.otgintr = 1; - int_mask.b.sessreqintr = 1; - int_mask.b.conidstschng = 1; -#endif - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTMSK, int_mask.d32); -} - -/** -* @brief USB_OTG_CoreReset : Soft reset of the core -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -static USB_OTG_STS USB_OTG_CoreReset(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - __IO USB_OTG_GRSTCTL_TypeDef greset; - uint32_t count = 0; - - greset.d32 = 0; - /* Wait for AHB master IDLE state. */ - do - { - USB_OTG_BSP_uDelay(3); - greset.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRSTCTL); - if (++count > 200000) - { - return USB_OTG_OK; - } - } - while (greset.b.ahbidle == 0); - /* Core Soft Reset */ - count = 0; - greset.b.csftrst = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRSTCTL, greset.d32 ); - do - { - greset.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRSTCTL); - if (++count > 200000) - { - break; - } - } - while (greset.b.csftrst == 1); - /* Wait for 3 PHY Clocks*/ - USB_OTG_BSP_uDelay(3); - return status; -} - -/** -* @brief USB_OTG_WritePacket : Writes a packet into the Tx FIFO associated -* with the EP -* @param pdev : Selected device -* @param src : source pointer -* @param ch_ep_num : end point number -* @param bytes : No. of bytes -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_WritePacket(USB_OTG_CORE_HANDLE *pdev, - uint8_t *src, - uint8_t ch_ep_num, - uint16_t len) -{ - USB_OTG_STS status = USB_OTG_OK; - if (pdev->cfg.dma_enable == 0) - { - uint32_t count32b= 0 , i= 0; - __IO uint32_t *fifo; - - count32b = (len + 3) / 4; - fifo = pdev->regs.DFIFO[ch_ep_num]; - for (i = 0; i < count32b; i++, src+=4) - { - USB_OTG_WRITE_REG32( fifo, *((__packed uint32_t *)src) ); - } - } - return status; -} - - -/** -* @brief USB_OTG_ReadPacket : Reads a packet from the Rx FIFO -* @param pdev : Selected device -* @param dest : Destination Pointer -* @param bytes : No. of bytes -* @retval None -*/ -void *USB_OTG_ReadPacket(USB_OTG_CORE_HANDLE *pdev, - uint8_t *dest, - uint16_t len) -{ - uint32_t i=0; - uint32_t count32b = (len + 3) / 4; - - __IO uint32_t *fifo = pdev->regs.DFIFO[0]; - - for ( i = 0; i < count32b; i++, dest += 4 ) - { - *(__packed uint32_t *)dest = USB_OTG_READ_REG32(fifo); - - } - return ((void *)dest); -} - -/** -* @brief USB_OTG_SelectCore -* Initialize core registers address. -* @param pdev : Selected device -* @param coreID : USB OTG Core ID -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_SelectCore(USB_OTG_CORE_HANDLE *pdev, - USB_OTG_CORE_ID_TypeDef coreID) -{ - uint32_t i , baseAddress = 0; - USB_OTG_STS status = USB_OTG_OK; - - pdev->cfg.dma_enable = 0; - - /* at startup the core is in FS mode */ - pdev->cfg.speed = USB_OTG_SPEED_FULL; - pdev->cfg.mps = USB_OTG_FS_MAX_PACKET_SIZE ; - - /* initialize device cfg following its address */ - if (coreID == USB_OTG_FS_CORE_ID) - { - baseAddress = USB_OTG_FS_BASE_ADDR; - pdev->cfg.coreID = USB_OTG_FS_CORE_ID; - pdev->cfg.host_channels = 8 ; - pdev->cfg.dev_endpoints = 4 ; - pdev->cfg.TotalFifoSize = 320; /* in 32-bits */ - pdev->cfg.phy_itface = USB_OTG_EMBEDDED_PHY; - -#ifdef USB_OTG_FS_SOF_OUTPUT_ENABLED - pdev->cfg.Sof_output = 1; -#endif - -#ifdef USB_OTG_FS_LOW_PWR_MGMT_SUPPORT - pdev->cfg.low_power = 1; -#endif - } - else if (coreID == USB_OTG_HS_CORE_ID) - { - baseAddress = USB_OTG_HS_BASE_ADDR; - pdev->cfg.coreID = USB_OTG_HS_CORE_ID; - pdev->cfg.host_channels = 12 ; - pdev->cfg.dev_endpoints = 6 ; - pdev->cfg.TotalFifoSize = 1280;/* in 32-bits */ - -#ifdef USB_OTG_ULPI_PHY_ENABLED - pdev->cfg.phy_itface = USB_OTG_ULPI_PHY; -#else -#ifdef USB_OTG_EMBEDDED_PHY_ENABLED - pdev->cfg.phy_itface = USB_OTG_EMBEDDED_PHY; -#endif -#endif - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - pdev->cfg.dma_enable = 1; -#endif - -#ifdef USB_OTG_HS_SOF_OUTPUT_ENABLED - pdev->cfg.Sof_output = 1; -#endif - -#ifdef USB_OTG_HS_LOW_PWR_MGMT_SUPPORT - pdev->cfg.low_power = 1; -#endif - - } - - pdev->regs.GREGS = (USB_OTG_GREGS *)(baseAddress + \ - USB_OTG_CORE_GLOBAL_REGS_OFFSET); - pdev->regs.DREGS = (USB_OTG_DREGS *) (baseAddress + \ - USB_OTG_DEV_GLOBAL_REG_OFFSET); - - for (i = 0; i < pdev->cfg.dev_endpoints; i++) - { - pdev->regs.INEP_REGS[i] = (USB_OTG_INEPREGS *) \ - (baseAddress + USB_OTG_DEV_IN_EP_REG_OFFSET + \ - (i * USB_OTG_EP_REG_OFFSET)); - pdev->regs.OUTEP_REGS[i] = (USB_OTG_OUTEPREGS *) \ - (baseAddress + USB_OTG_DEV_OUT_EP_REG_OFFSET + \ - (i * USB_OTG_EP_REG_OFFSET)); - } - pdev->regs.HREGS = (USB_OTG_HREGS *)(baseAddress + \ - USB_OTG_HOST_GLOBAL_REG_OFFSET); - pdev->regs.HPRT0 = (uint32_t *)(baseAddress + USB_OTG_HOST_PORT_REGS_OFFSET); - - for (i = 0; i < pdev->cfg.host_channels; i++) - { - pdev->regs.HC_REGS[i] = (USB_OTG_HC_REGS *)(baseAddress + \ - USB_OTG_HOST_CHAN_REGS_OFFSET + \ - (i * USB_OTG_CHAN_REGS_OFFSET)); - } - for (i = 0; i < pdev->cfg.host_channels; i++) - { - pdev->regs.DFIFO[i] = (uint32_t *)(baseAddress + USB_OTG_DATA_FIFO_OFFSET +\ - (i * USB_OTG_DATA_FIFO_SIZE)); - } - pdev->regs.PCGCCTL = (uint32_t *)(baseAddress + USB_OTG_PCGCCTL_OFFSET); - - return status; -} - - -/** -* @brief USB_OTG_CoreInit -* Initializes the USB_OTG controller registers and prepares the core -* device mode or host mode operation. -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_CoreInit(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_GUSBCFG_TypeDef usbcfg; - USB_OTG_GCCFG_TypeDef gccfg; - USB_OTG_GAHBCFG_TypeDef ahbcfg; - - usbcfg.d32 = 0; - gccfg.d32 = 0; - ahbcfg.d32 = 0; - - - - if (pdev->cfg.phy_itface == USB_OTG_ULPI_PHY) - { - gccfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GCCFG); - gccfg.b.pwdn = 0; - - if (pdev->cfg.Sof_output) - { - gccfg.b.sofouten = 1; - } - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GCCFG, gccfg.d32); - - /* Init The ULPI Interface */ - usbcfg.d32 = 0; - usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); - - usbcfg.b.physel = 0; /* HS Interface */ -#ifdef USB_OTG_INTERNAL_VBUS_ENABLED - usbcfg.b.ulpi_ext_vbus_drv = 0; /* Use internal VBUS */ -#else -#ifdef USB_OTG_EXTERNAL_VBUS_ENABLED - usbcfg.b.ulpi_ext_vbus_drv = 1; /* Use external VBUS */ -#endif -#endif - usbcfg.b.term_sel_dl_pulse = 0; /* Data line pulsing using utmi_txvalid */ - - usbcfg.b.ulpi_fsls = 0; - usbcfg.b.ulpi_clk_sus_m = 0; - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); - - /* Reset after a PHY select */ - USB_OTG_CoreReset(pdev); - - if(pdev->cfg.dma_enable == 1) - { - - ahbcfg.b.hburstlen = 5; /* 64 x 32-bits*/ - ahbcfg.b.dmaenable = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32); - - } - } - else /* FS interface (embedded Phy) */ - { - - usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);; - usbcfg.b.physel = 1; /* FS Interface */ - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); - /* Reset after a PHY select and set Host mode */ - USB_OTG_CoreReset(pdev); - /* Deactivate the power down*/ - gccfg.d32 = 0; - gccfg.b.pwdn = 1; - - gccfg.b.vbussensingA = 1 ; - gccfg.b.vbussensingB = 1 ; -#ifndef VBUS_SENSING_ENABLED - gccfg.b.disablevbussensing = 1; -#endif - - if(pdev->cfg.Sof_output) - { - gccfg.b.sofouten = 1; - } - - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GCCFG, gccfg.d32); - USB_OTG_BSP_mDelay(20); - } - /* case the HS core is working in FS mode */ - if(pdev->cfg.dma_enable == 1) - { - - ahbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GAHBCFG); - ahbcfg.b.hburstlen = 5; /* 64 x 32-bits*/ - ahbcfg.b.dmaenable = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32); - - } - /* initialize OTG features */ -#ifdef USE_OTG_MODE - usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); - usbcfg.b.hnpcap = 1; - usbcfg.b.srpcap = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); - USB_OTG_EnableCommonInt(pdev); -#endif - return status; -} -/** -* @brief USB_OTG_EnableGlobalInt -* Enables the controller's Global Int in the AHB Config reg -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EnableGlobalInt(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_GAHBCFG_TypeDef ahbcfg; - - ahbcfg.d32 = 0; - ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ - USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GAHBCFG, 0, ahbcfg.d32); - return status; -} - - -/** -* @brief USB_OTG_DisableGlobalInt -* Enables the controller's Global Int in the AHB Config reg -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_DisableGlobalInt(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_GAHBCFG_TypeDef ahbcfg; - ahbcfg.d32 = 0; - ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ - USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32, 0); - return status; -} - - -/** -* @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO -* @param pdev : Selected device -* @param num : FO num -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_FlushTxFifo (USB_OTG_CORE_HANDLE *pdev , uint32_t num ) -{ - USB_OTG_STS status = USB_OTG_OK; - __IO USB_OTG_GRSTCTL_TypeDef greset; - - uint32_t count = 0; - greset.d32 = 0; - greset.b.txfflsh = 1; - greset.b.txfnum = num; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GRSTCTL, greset.d32 ); - do - { - greset.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRSTCTL); - if (++count > 200000) - { - break; - } - } - while (greset.b.txfflsh == 1); - /* Wait for 3 PHY Clocks*/ - USB_OTG_BSP_uDelay(3); - return status; -} - - -/** -* @brief USB_OTG_FlushRxFifo : Flush a Rx FIFO -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_FlushRxFifo( USB_OTG_CORE_HANDLE *pdev ) -{ - USB_OTG_STS status = USB_OTG_OK; - __IO USB_OTG_GRSTCTL_TypeDef greset; - uint32_t count = 0; - - greset.d32 = 0; - greset.b.rxfflsh = 1; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GRSTCTL, greset.d32 ); - do - { - greset.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRSTCTL); - if (++count > 200000) - { - break; - } - } - while (greset.b.rxfflsh == 1); - /* Wait for 3 PHY Clocks*/ - USB_OTG_BSP_uDelay(3); - return status; -} - - -/** -* @brief USB_OTG_SetCurrentMode : Set ID line -* @param pdev : Selected device -* @param mode : (Host/device) -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_SetCurrentMode(USB_OTG_CORE_HANDLE *pdev , uint8_t mode) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_GUSBCFG_TypeDef usbcfg; - - usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); - - usbcfg.b.force_host = 0; - usbcfg.b.force_dev = 0; - - if ( mode == HOST_MODE) - { - usbcfg.b.force_host = 1; - } - else if ( mode == DEVICE_MODE) - { - usbcfg.b.force_dev = 1; - } - - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); - USB_OTG_BSP_mDelay(50); - return status; -} - - -/** -* @brief USB_OTG_GetMode : Get current mode -* @param pdev : Selected device -* @retval current mode -*/ -uint32_t USB_OTG_GetMode(USB_OTG_CORE_HANDLE *pdev) -{ - return (USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS ) & 0x1); -} - - -/** -* @brief USB_OTG_IsDeviceMode : Check if it is device mode -* @param pdev : Selected device -* @retval num_in_ep -*/ -uint8_t USB_OTG_IsDeviceMode(USB_OTG_CORE_HANDLE *pdev) -{ - return (USB_OTG_GetMode(pdev) != HOST_MODE); -} - - -/** -* @brief USB_OTG_IsHostMode : Check if it is host mode -* @param pdev : Selected device -* @retval num_in_ep -*/ -uint8_t USB_OTG_IsHostMode(USB_OTG_CORE_HANDLE *pdev) -{ - return (USB_OTG_GetMode(pdev) == HOST_MODE); -} - - -/** -* @brief USB_OTG_ReadCoreItr : returns the Core Interrupt register -* @param pdev : Selected device -* @retval Status -*/ -uint32_t USB_OTG_ReadCoreItr(USB_OTG_CORE_HANDLE *pdev) -{ - uint32_t v = 0; - v = USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS); - v &= USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTMSK); - return v; -} - - -/** -* @brief USB_OTG_ReadOtgItr : returns the USB_OTG Interrupt register -* @param pdev : Selected device -* @retval Status -*/ -uint32_t USB_OTG_ReadOtgItr (USB_OTG_CORE_HANDLE *pdev) -{ - return (USB_OTG_READ_REG32 (&pdev->regs.GREGS->GOTGINT)); -} - -#ifdef USE_HOST_MODE -/** -* @brief USB_OTG_CoreInitHost : Initializes USB_OTG controller for host mode -* @param pdev : Selected device -* @retval status -*/ -USB_OTG_STS USB_OTG_CoreInitHost(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_FSIZ_TypeDef nptxfifosize; - USB_OTG_FSIZ_TypeDef ptxfifosize; - USB_OTG_HCFG_TypeDef hcfg; - -#ifdef USE_OTG_MODE - USB_OTG_OTGCTL_TypeDef gotgctl; -#endif - - uint32_t i = 0; - - nptxfifosize.d32 = 0; - ptxfifosize.d32 = 0; -#ifdef USE_OTG_MODE - gotgctl.d32 = 0; -#endif - hcfg.d32 = 0; - - - /* configure charge pump IO */ - USB_OTG_BSP_ConfigVBUS(pdev); - - /* Restart the Phy Clock */ - USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0); - - /* Initialize Host Configuration Register */ - if (pdev->cfg.phy_itface == USB_OTG_ULPI_PHY) - { - USB_OTG_InitFSLSPClkSel(pdev , HCFG_30_60_MHZ); - } - else - { - USB_OTG_InitFSLSPClkSel(pdev , HCFG_48_MHZ); - } - USB_OTG_ResetPort(pdev); - - hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG); - hcfg.b.fslssupp = 0; - USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HCFG, hcfg.d32); - - /* Configure data FIFO sizes */ - /* Rx FIFO */ -#ifdef USB_OTG_FS_CORE - if(pdev->cfg.coreID == USB_OTG_FS_CORE_ID) - { - /* set Rx FIFO size */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_FS_SIZE); - nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE; - nptxfifosize.b.depth = TXH_NP_FS_FIFOSIZ; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32); - - ptxfifosize.b.startaddr = RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ; - ptxfifosize.b.depth = TXH_P_FS_FIFOSIZ; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32); - } -#endif -#ifdef USB_OTG_HS_CORE - if (pdev->cfg.coreID == USB_OTG_HS_CORE_ID) - { - /* set Rx FIFO size */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_HS_SIZE); - nptxfifosize.b.startaddr = RX_FIFO_HS_SIZE; - nptxfifosize.b.depth = TXH_NP_HS_FIFOSIZ; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32); - - ptxfifosize.b.startaddr = RX_FIFO_HS_SIZE + TXH_NP_HS_FIFOSIZ; - ptxfifosize.b.depth = TXH_P_HS_FIFOSIZ; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32); - } -#endif - -#ifdef USE_OTG_MODE - /* Clear Host Set HNP Enable in the USB_OTG Control Register */ - gotgctl.b.hstsethnpen = 1; - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GOTGCTL, gotgctl.d32, 0); -#endif - - /* Make sure the FIFOs are flushed. */ - USB_OTG_FlushTxFifo(pdev, 0x10 ); /* all Tx FIFOs */ - USB_OTG_FlushRxFifo(pdev); - - - /* Clear all pending HC Interrupts */ - for (i = 0; i < pdev->cfg.host_channels; i++) - { - USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCINT, 0xFFFFFFFF ); - USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCINTMSK, 0 ); - } -#ifndef USE_OTG_MODE - USB_OTG_DriveVbus(pdev, 1); -#endif - - USB_OTG_EnableHostInt(pdev); - return status; -} - -/** -* @brief USB_OTG_IsEvenFrame -* This function returns the frame number for sof packet -* @param pdev : Selected device -* @retval Frame number -*/ -uint8_t USB_OTG_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev) -{ - return !(USB_OTG_READ_REG32(&pdev->regs.HREGS->HFNUM) & 0x1); -} - -/** -* @brief USB_OTG_DriveVbus : set/reset vbus -* @param pdev : Selected device -* @param state : VBUS state -* @retval None -*/ -void USB_OTG_DriveVbus (USB_OTG_CORE_HANDLE *pdev, uint8_t state) -{ - USB_OTG_HPRT0_TypeDef hprt0; - - hprt0.d32 = 0; - - /* enable disable the external charge pump */ - USB_OTG_BSP_DriveVBUS(pdev, state); - - /* Turn on the Host port power. */ - hprt0.d32 = USB_OTG_ReadHPRT0(pdev); - if ((hprt0.b.prtpwr == 0 ) && (state == 1 )) - { - hprt0.b.prtpwr = 1; - USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); - } - if ((hprt0.b.prtpwr == 1 ) && (state == 0 )) - { - hprt0.b.prtpwr = 0; - USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); - } - - USB_OTG_BSP_mDelay(200); -} -/** -* @brief USB_OTG_EnableHostInt: Enables the Host mode interrupts -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EnableHostInt(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_GINTMSK_TypeDef intmsk; - intmsk.d32 = 0; - /* Disable all interrupts. */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTMSK, 0); - - /* Clear any pending interrupts. */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, 0xFFFFFFFF); - - /* Enable the common interrupts */ - USB_OTG_EnableCommonInt(pdev); - - if (pdev->cfg.dma_enable == 0) - { - intmsk.b.rxstsqlvl = 1; - } - intmsk.b.portintr = 1; - intmsk.b.hcintr = 1; - intmsk.b.disconnect = 1; - intmsk.b.sofintr = 1; - intmsk.b.incomplisoout = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, intmsk.d32, intmsk.d32); - return status; -} - -/** -* @brief USB_OTG_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the -* HCFG register on the PHY type -* @param pdev : Selected device -* @param freq : clock frequency -* @retval None -*/ -void USB_OTG_InitFSLSPClkSel(USB_OTG_CORE_HANDLE *pdev , uint8_t freq) -{ - USB_OTG_HCFG_TypeDef hcfg; - - hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG); - hcfg.b.fslspclksel = freq; - USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HCFG, hcfg.d32); -} - - -/** -* @brief USB_OTG_ReadHPRT0 : Reads HPRT0 to modify later -* @param pdev : Selected device -* @retval HPRT0 value -*/ -uint32_t USB_OTG_ReadHPRT0(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_HPRT0_TypeDef hprt0; - - hprt0.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0); - hprt0.b.prtena = 0; - hprt0.b.prtconndet = 0; - hprt0.b.prtenchng = 0; - hprt0.b.prtovrcurrchng = 0; - return hprt0.d32; -} - - -/** -* @brief USB_OTG_ReadHostAllChannels_intr : Register PCD Callbacks -* @param pdev : Selected device -* @retval Status -*/ -uint32_t USB_OTG_ReadHostAllChannels_intr (USB_OTG_CORE_HANDLE *pdev) -{ - return (USB_OTG_READ_REG32 (&pdev->regs.HREGS->HAINT)); -} - - -/** -* @brief USB_OTG_ResetPort : Reset Host Port -* @param pdev : Selected device -* @retval status -* @note : (1)The application must wait at least 10 ms (+ 10 ms security) -* before clearing the reset bit. -*/ -uint32_t USB_OTG_ResetPort(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_HPRT0_TypeDef hprt0; - - hprt0.d32 = USB_OTG_ReadHPRT0(pdev); - hprt0.b.prtrst = 1; - USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); - USB_OTG_BSP_mDelay (10); /* See Note #1 */ - hprt0.b.prtrst = 0; - USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); - USB_OTG_BSP_mDelay (20); - return 1; -} - - -/** -* @brief USB_OTG_HC_Init : Prepares a host channel for transferring packets -* @param pdev : Selected device -* @param hc_num : channel number -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_HC_Init(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) -{ - USB_OTG_STS status = USB_OTG_OK; - uint32_t intr_enable = 0; - USB_OTG_HCINTMSK_TypeDef hcintmsk; - USB_OTG_GINTMSK_TypeDef gintmsk; - USB_OTG_HCCHAR_TypeDef hcchar; - USB_OTG_HCINTn_TypeDef hcint; - - - gintmsk.d32 = 0; - hcintmsk.d32 = 0; - hcchar.d32 = 0; - - /* Clear old interrupt conditions for this host channel. */ - hcint.d32 = 0xFFFFFFFF; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINT, hcint.d32); - - /* Enable channel interrupts required for this transfer. */ - hcintmsk.d32 = 0; - - if (pdev->cfg.dma_enable == 1) - { - hcintmsk.b.ahberr = 1; - } - - switch (pdev->host.hc[hc_num].ep_type) - { - case EP_TYPE_CTRL: - case EP_TYPE_BULK: - hcintmsk.b.xfercompl = 1; - hcintmsk.b.stall = 1; - hcintmsk.b.xacterr = 1; - hcintmsk.b.datatglerr = 1; - hcintmsk.b.nak = 1; - if (pdev->host.hc[hc_num].ep_is_in) - { - hcintmsk.b.bblerr = 1; - } - else - { - hcintmsk.b.nyet = 1; - if (pdev->host.hc[hc_num].do_ping) - { - hcintmsk.b.ack = 1; - } - } - break; - case EP_TYPE_INTR: - hcintmsk.b.xfercompl = 1; - hcintmsk.b.nak = 1; - hcintmsk.b.stall = 1; - hcintmsk.b.xacterr = 1; - hcintmsk.b.datatglerr = 1; - hcintmsk.b.frmovrun = 1; - - if (pdev->host.hc[hc_num].ep_is_in) - { - hcintmsk.b.bblerr = 1; - } - - break; - case EP_TYPE_ISOC: - hcintmsk.b.xfercompl = 1; - hcintmsk.b.frmovrun = 1; - hcintmsk.b.ack = 1; - - if (pdev->host.hc[hc_num].ep_is_in) - { - hcintmsk.b.xacterr = 1; - hcintmsk.b.bblerr = 1; - } - break; - } - - - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, hcintmsk.d32); - - - /* Enable the top level host channel interrupt. */ - intr_enable = (1 << hc_num); - USB_OTG_MODIFY_REG32(&pdev->regs.HREGS->HAINTMSK, 0, intr_enable); - - /* Make sure host channel interrupts are enabled. */ - gintmsk.b.hcintr = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, 0, gintmsk.d32); - - /* Program the HCCHAR register */ - hcchar.d32 = 0; - hcchar.b.devaddr = pdev->host.hc[hc_num].dev_addr; - hcchar.b.epnum = pdev->host.hc[hc_num].ep_num; - hcchar.b.epdir = pdev->host.hc[hc_num].ep_is_in; - hcchar.b.lspddev = (pdev->host.hc[hc_num].speed == HPRT0_PRTSPD_LOW_SPEED); - hcchar.b.eptype = pdev->host.hc[hc_num].ep_type; - hcchar.b.mps = pdev->host.hc[hc_num].max_packet; - if (pdev->host.hc[hc_num].ep_type == HCCHAR_INTR) - { - hcchar.b.oddfrm = 1; - } - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); - return status; -} - - -/** -* @brief USB_OTG_HC_StartXfer : Start transfer -* @param pdev : Selected device -* @param hc_num : channel number -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_HC_StartXfer(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_HCCHAR_TypeDef hcchar; - USB_OTG_HCTSIZn_TypeDef hctsiz; - USB_OTG_HNPTXSTS_TypeDef hnptxsts; - USB_OTG_HPTXSTS_TypeDef hptxsts; - USB_OTG_GINTMSK_TypeDef intmsk; - uint16_t len_words = 0; - - uint16_t num_packets; - uint16_t max_hc_pkt_count; - - max_hc_pkt_count = 256; - hctsiz.d32 = 0; - hcchar.d32 = 0; - intmsk.d32 = 0; - - /* Compute the expected number of packets associated to the transfer */ - if (pdev->host.hc[hc_num].xfer_len > 0) - { - num_packets = (pdev->host.hc[hc_num].xfer_len + \ - pdev->host.hc[hc_num].max_packet - 1) / pdev->host.hc[hc_num].max_packet; - - if (num_packets > max_hc_pkt_count) - { - num_packets = max_hc_pkt_count; - pdev->host.hc[hc_num].xfer_len = num_packets * \ - pdev->host.hc[hc_num].max_packet; - } - } - else - { - num_packets = 1; - } - if (pdev->host.hc[hc_num].ep_is_in) - { - pdev->host.hc[hc_num].xfer_len = num_packets * \ - pdev->host.hc[hc_num].max_packet; - } - /* Initialize the HCTSIZn register */ - hctsiz.b.xfersize = pdev->host.hc[hc_num].xfer_len; - hctsiz.b.pktcnt = num_packets; - hctsiz.b.pid = pdev->host.hc[hc_num].data_pid; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCTSIZ, hctsiz.d32); - - if (pdev->cfg.dma_enable == 1) - { - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCDMA, (unsigned int)pdev->host.hc[hc_num].xfer_buff); - } - - - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR); - hcchar.b.oddfrm = USB_OTG_IsEvenFrame(pdev); - - /* Set host channel enable */ - hcchar.b.chen = 1; - hcchar.b.chdis = 0; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); - - if (pdev->cfg.dma_enable == 0) /* Slave mode */ - { - if((pdev->host.hc[hc_num].ep_is_in == 0) && - (pdev->host.hc[hc_num].xfer_len > 0)) - { - switch(pdev->host.hc[hc_num].ep_type) - { - /* Non periodic transfer */ - case EP_TYPE_CTRL: - case EP_TYPE_BULK: - - hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS); - len_words = (pdev->host.hc[hc_num].xfer_len + 3) / 4; - - /* check if there is enough space in FIFO space */ - if(len_words > hnptxsts.b.nptxfspcavail) - { - /* need to process data in nptxfempty interrupt */ - intmsk.b.nptxfempty = 1; - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, intmsk.d32); - } - - break; - /* Periodic transfer */ - case EP_TYPE_INTR: - case EP_TYPE_ISOC: - hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS); - len_words = (pdev->host.hc[hc_num].xfer_len + 3) / 4; - /* check if there is enough space in FIFO space */ - if(len_words > hptxsts.b.ptxfspcavail) /* split the transfer */ - { - /* need to process data in ptxfempty interrupt */ - intmsk.b.ptxfempty = 1; - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, intmsk.d32); - } - break; - - default: - break; - } - - /* Write packet into the Tx FIFO. */ - USB_OTG_WritePacket(pdev, - pdev->host.hc[hc_num].xfer_buff , - hc_num, pdev->host.hc[hc_num].xfer_len); - } - } - return status; -} - - -/** -* @brief USB_OTG_HC_Halt : Halt channel -* @param pdev : Selected device -* @param hc_num : channel number -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_HC_Halt(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_HNPTXSTS_TypeDef nptxsts; - USB_OTG_HPTXSTS_TypeDef hptxsts; - USB_OTG_HCCHAR_TypeDef hcchar; - - nptxsts.d32 = 0; - hptxsts.d32 = 0; - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR); - hcchar.b.chen = 1; - hcchar.b.chdis = 1; - - /* Check for space in the request queue to issue the halt. */ - if (hcchar.b.eptype == HCCHAR_CTRL || hcchar.b.eptype == HCCHAR_BULK) - { - nptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS); - if (nptxsts.b.nptxqspcavail == 0) - { - hcchar.b.chen = 0; - } - } - else - { - hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS); - if (hptxsts.b.ptxqspcavail == 0) - { - hcchar.b.chen = 0; - } - } - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); - return status; -} - -/** -* @brief Issue a ping token -* @param None -* @retval : None -*/ -USB_OTG_STS USB_OTG_HC_DoPing(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_HCCHAR_TypeDef hcchar; - USB_OTG_HCTSIZn_TypeDef hctsiz; - - hctsiz.d32 = 0; - hctsiz.b.dopng = 1; - hctsiz.b.pktcnt = 1; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCTSIZ, hctsiz.d32); - - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR); - hcchar.b.chen = 1; - hcchar.b.chdis = 0; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); - return status; -} - -/** -* @brief Stop the device and clean up fifo's -* @param None -* @retval : None -*/ -void USB_OTG_StopHost(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_HCCHAR_TypeDef hcchar; - uint32_t i; - - USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HAINTMSK , 0); - USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HAINT, 0xFFFFFFFF); - /* Flush out any leftover queued requests. */ - - for (i = 0; i < pdev->cfg.host_channels; i++) - { - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[i]->HCCHAR); - hcchar.b.chen = 0; - hcchar.b.chdis = 1; - hcchar.b.epdir = 0; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[i]->HCCHAR, hcchar.d32); - } - - /* Flush the FIFO */ - USB_OTG_FlushRxFifo(pdev); - USB_OTG_FlushTxFifo(pdev , 0x10 ); -} -#endif -#ifdef USE_DEVICE_MODE -/* PCD Core Layer */ - -/** -* @brief USB_OTG_InitDevSpeed :Initializes the DevSpd field of DCFG register -* depending the PHY type and the enumeration speed of the device. -* @param pdev : Selected device -* @retval : None -*/ -void USB_OTG_InitDevSpeed(USB_OTG_CORE_HANDLE *pdev , uint8_t speed) -{ - USB_OTG_DCFG_TypeDef dcfg; - - dcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCFG); - dcfg.b.devspd = speed; - USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCFG, dcfg.d32); -} - - -/** -* @brief USB_OTG_CoreInitDev : Initializes the USB_OTG controller registers -* for device mode -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_CoreInitDev (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - uint32_t i; - USB_OTG_DCFG_TypeDef dcfg; - USB_OTG_FSIZ_TypeDef nptxfifosize; - USB_OTG_FSIZ_TypeDef txfifosize; - USB_OTG_DIEPMSK_TypeDef msk; - USB_OTG_DTHRCTL_TypeDef dthrctl; - - depctl.d32 = 0; - dcfg.d32 = 0; - nptxfifosize.d32 = 0; - txfifosize.d32 = 0; - msk.d32 = 0; - - /* Restart the Phy Clock */ - USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0); - /* Device configuration register */ - dcfg.d32 = USB_OTG_READ_REG32( &pdev->regs.DREGS->DCFG); - dcfg.b.perfrint = DCFG_FRAME_INTERVAL_80; - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DCFG, dcfg.d32 ); - -#ifdef USB_OTG_FS_CORE - if(pdev->cfg.coreID == USB_OTG_FS_CORE_ID ) - { - - /* Set Full speed phy */ - USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_FULL); - - /* set Rx FIFO size */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_FS_SIZE); - - /* EP0 TX*/ - nptxfifosize.b.depth = TX0_FIFO_FS_SIZE; - nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32 ); - - - /* EP1 TX*/ - txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth; - txfifosize.b.depth = TX1_FIFO_FS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[0], txfifosize.d32 ); - - - /* EP2 TX*/ - txfifosize.b.startaddr += txfifosize.b.depth; - txfifosize.b.depth = TX2_FIFO_FS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[1], txfifosize.d32 ); - - - /* EP3 TX*/ - txfifosize.b.startaddr += txfifosize.b.depth; - txfifosize.b.depth = TX3_FIFO_FS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[2], txfifosize.d32 ); - } -#endif -#ifdef USB_OTG_HS_CORE - if(pdev->cfg.coreID == USB_OTG_HS_CORE_ID ) - { - - /* Set High speed phy */ - - if(pdev->cfg.phy_itface == USB_OTG_ULPI_PHY) - { - USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_HIGH); - } - else /* set High speed phy in Full speed mode */ - { - USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_HIGH_IN_FULL); - } - - /* set Rx FIFO size */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_HS_SIZE); - - /* EP0 TX*/ - nptxfifosize.b.depth = TX0_FIFO_HS_SIZE; - nptxfifosize.b.startaddr = RX_FIFO_HS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32 ); - - - /* EP1 TX*/ - txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth; - txfifosize.b.depth = TX1_FIFO_HS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[0], txfifosize.d32 ); - - - /* EP2 TX*/ - txfifosize.b.startaddr += txfifosize.b.depth; - txfifosize.b.depth = TX2_FIFO_HS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[1], txfifosize.d32 ); - - - /* EP3 TX*/ - txfifosize.b.startaddr += txfifosize.b.depth; - txfifosize.b.depth = TX3_FIFO_HS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[2], txfifosize.d32 ); - - /* EP4 TX*/ - txfifosize.b.startaddr += txfifosize.b.depth; - txfifosize.b.depth = TX4_FIFO_HS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[3], txfifosize.d32 ); - - - /* EP5 TX*/ - txfifosize.b.startaddr += txfifosize.b.depth; - txfifosize.b.depth = TX5_FIFO_HS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[4], txfifosize.d32 ); - } -#endif - /* Flush the FIFOs */ - USB_OTG_FlushTxFifo(pdev , 0x10); /* all Tx FIFOs */ - USB_OTG_FlushRxFifo(pdev); - /* Clear all pending Device Interrupts */ - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, 0 ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, 0 ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, 0 ); - - for (i = 0; i < pdev->cfg.dev_endpoints; i++) - { - depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[i]->DIEPCTL); - if (depctl.b.epena) - { - depctl.d32 = 0; - depctl.b.epdis = 1; - depctl.b.snak = 1; - } - else - { - depctl.d32 = 0; - } - USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPCTL, depctl.d32); - USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPTSIZ, 0); - USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF); - } - for (i = 0; i < pdev->cfg.dev_endpoints; i++) - { - USB_OTG_DEPCTL_TypeDef depctl; - depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[i]->DOEPCTL); - if (depctl.b.epena) - { - depctl.d32 = 0; - depctl.b.epdis = 1; - depctl.b.snak = 1; - } - else - { - depctl.d32 = 0; - } - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPCTL, depctl.d32); - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPTSIZ, 0); - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF); - } - msk.d32 = 0; - msk.b.txfifoundrn = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPMSK, msk.d32, msk.d32); - - if (pdev->cfg.dma_enable == 1) - { - dthrctl.d32 = 0; - dthrctl.b.non_iso_thr_en = 1; - dthrctl.b.iso_thr_en = 1; - dthrctl.b.tx_thr_len = 64; - dthrctl.b.rx_thr_en = 1; - dthrctl.b.rx_thr_len = 64; - USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DTHRCTL, dthrctl.d32); - } - USB_OTG_EnableDevInt(pdev); - return status; -} - - -/** -* @brief USB_OTG_EnableDevInt : Enables the Device mode interrupts -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EnableDevInt(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_GINTMSK_TypeDef intmsk; - - intmsk.d32 = 0; - - /* Disable all interrupts. */ - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTMSK, 0); - /* Clear any pending interrupts */ - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, 0xBFFFFFFF); - /* Enable the common interrupts */ - USB_OTG_EnableCommonInt(pdev); - - if (pdev->cfg.dma_enable == 0) - { - intmsk.b.rxstsqlvl = 1; - } - - /* Enable interrupts matching to the Device mode ONLY */ - intmsk.b.usbsuspend = 1; - intmsk.b.usbreset = 1; - intmsk.b.enumdone = 1; - intmsk.b.inepintr = 1; - intmsk.b.outepintr = 1; - intmsk.b.sofintr = 1; - - intmsk.b.incomplisoin = 1; - intmsk.b.incomplisoout = 1; -#ifdef VBUS_SENSING_ENABLED - intmsk.b.sessreqintr = 1; - intmsk.b.otgintr = 1; -#endif - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, intmsk.d32); - return status; -} - - -/** -* @brief USB_OTG_GetDeviceSpeed -* Get the device speed from the device status register -* @param None -* @retval status -*/ -enum USB_OTG_SPEED USB_OTG_GetDeviceSpeed (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_DSTS_TypeDef dsts; - enum USB_OTG_SPEED speed = USB_SPEED_UNKNOWN; - - - dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - - switch (dsts.b.enumspd) - { - case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: - speed = USB_SPEED_HIGH; - break; - case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: - case DSTS_ENUMSPD_FS_PHY_48MHZ: - speed = USB_SPEED_FULL; - break; - - case DSTS_ENUMSPD_LS_PHY_6MHZ: - speed = USB_SPEED_LOW; - break; - } - - return speed; -} -/** -* @brief enables EP0 OUT to receive SETUP packets and configures EP0 -* for transmitting packets -* @param None -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EP0Activate(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DSTS_TypeDef dsts; - USB_OTG_DEPCTL_TypeDef diepctl; - USB_OTG_DCTL_TypeDef dctl; - - dctl.d32 = 0; - /* Read the Device Status and Endpoint 0 Control registers */ - dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - diepctl.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[0]->DIEPCTL); - /* Set the MPS of the IN EP based on the enumeration speed */ - switch (dsts.b.enumspd) - { - case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: - case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: - case DSTS_ENUMSPD_FS_PHY_48MHZ: - diepctl.b.mps = DEP0CTL_MPS_64; - break; - case DSTS_ENUMSPD_LS_PHY_6MHZ: - diepctl.b.mps = DEP0CTL_MPS_8; - break; - } - USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[0]->DIEPCTL, diepctl.d32); - dctl.b.cgnpinnak = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, dctl.d32); - return status; -} - - -/** -* @brief USB_OTG_EPActivate : Activates an EP -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EPActivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - USB_OTG_DAINT_TypeDef daintmsk; - __IO uint32_t *addr; - - - depctl.d32 = 0; - daintmsk.d32 = 0; - /* Read DEPCTLn register */ - if (ep->is_in == 1) - { - addr = &pdev->regs.INEP_REGS[ep->num]->DIEPCTL; - daintmsk.ep.in = 1 << ep->num; - } - else - { - addr = &pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL; - daintmsk.ep.out = 1 << ep->num; - } - /* If the EP is already active don't change the EP Control - * register. */ - depctl.d32 = USB_OTG_READ_REG32(addr); - if (!depctl.b.usbactep) - { - depctl.b.mps = ep->maxpacket; - depctl.b.eptype = ep->type; - depctl.b.txfnum = ep->tx_fifo_num; - depctl.b.setd0pid = 1; - depctl.b.usbactep = 1; - USB_OTG_WRITE_REG32(addr, depctl.d32); - } - /* Enable the Interrupt for this EP */ -#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED - if((ep->num == 1)&&(pdev->cfg.coreID == USB_OTG_HS_CORE_ID)) - { - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DEACHMSK, 0, daintmsk.d32); - } - else -#endif - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DAINTMSK, 0, daintmsk.d32); - return status; -} - - -/** -* @brief USB_OTG_EPDeactivate : Deactivates an EP -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EPDeactivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - USB_OTG_DAINT_TypeDef daintmsk; - __IO uint32_t *addr; - - depctl.d32 = 0; - daintmsk.d32 = 0; - /* Read DEPCTLn register */ - if (ep->is_in == 1) - { - addr = &pdev->regs.INEP_REGS[ep->num]->DIEPCTL; - daintmsk.ep.in = 1 << ep->num; - } - else - { - addr = &pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL; - daintmsk.ep.out = 1 << ep->num; - } - depctl.b.usbactep = 0; - USB_OTG_WRITE_REG32(addr, depctl.d32); - /* Disable the Interrupt for this EP */ - -#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED - if((ep->num == 1)&&(pdev->cfg.coreID == USB_OTG_HS_CORE_ID)) - { - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DEACHMSK, daintmsk.d32, 0); - } - else -#endif - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DAINTMSK, daintmsk.d32, 0); - return status; -} - - -/** -* @brief USB_OTG_EPStartXfer : Handle the setup for data xfer for an EP and -* starts the xfer -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EPStartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - USB_OTG_DEPXFRSIZ_TypeDef deptsiz; - USB_OTG_DSTS_TypeDef dsts; - uint32_t fifoemptymsk = 0; - - depctl.d32 = 0; - deptsiz.d32 = 0; - /* IN endpoint */ - if (ep->is_in == 1) - { - depctl.d32 = USB_OTG_READ_REG32(&(pdev->regs.INEP_REGS[ep->num]->DIEPCTL)); - deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.INEP_REGS[ep->num]->DIEPTSIZ)); - /* Zero Length Packet? */ - if (ep->xfer_len == 0) - { - deptsiz.b.xfersize = 0; - deptsiz.b.pktcnt = 1; - } - else - { - /* Program the transfer size and packet count - * as follows: xfersize = N * maxpacket + - * short_packet pktcnt = N + (short_packet - * exist ? 1 : 0) - */ - deptsiz.b.xfersize = ep->xfer_len; - deptsiz.b.pktcnt = (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket; - - if (ep->type == EP_TYPE_ISOC) - { - deptsiz.b.mc = 1; - } - } - USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPTSIZ, deptsiz.d32); - - if (pdev->cfg.dma_enable == 1) - { - USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPDMA, ep->dma_addr); - } - else - { - if (ep->type != EP_TYPE_ISOC) - { - /* Enable the Tx FIFO Empty Interrupt for this EP */ - if (ep->xfer_len > 0) - { - fifoemptymsk = 1 << ep->num; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, 0, fifoemptymsk); - } - } - } - - - if (ep->type == EP_TYPE_ISOC) - { - dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - - if (((dsts.b.soffn)&0x1) == 0) - { - depctl.b.setd1pid = 1; - } - else - { - depctl.b.setd0pid = 1; - } - } - - /* EP enable, IN data in FIFO */ - depctl.b.cnak = 1; - depctl.b.epena = 1; - USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPCTL, depctl.d32); - - if (ep->type == EP_TYPE_ISOC) - { - USB_OTG_WritePacket(pdev, ep->xfer_buff, ep->num, ep->xfer_len); - } - } - else - { - /* OUT endpoint */ - depctl.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL)); - deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ)); - /* Program the transfer size and packet count as follows: - * pktcnt = N - * xfersize = N * maxpacket - */ - if (ep->xfer_len == 0) - { - deptsiz.b.xfersize = ep->maxpacket; - deptsiz.b.pktcnt = 1; - } - else - { - deptsiz.b.pktcnt = (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket; - deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket; - } - USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ, deptsiz.d32); - - if (pdev->cfg.dma_enable == 1) - { - USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPDMA, ep->dma_addr); - } - - if (ep->type == EP_TYPE_ISOC) - { - if (ep->even_odd_frame) - { - depctl.b.setd1pid = 1; - } - else - { - depctl.b.setd0pid = 1; - } - } - /* EP enable */ - depctl.b.cnak = 1; - depctl.b.epena = 1; - USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL, depctl.d32); - } - return status; -} - - -/** -* @brief USB_OTG_EP0StartXfer : Handle the setup for a data xfer for EP0 and -* starts the xfer -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EP0StartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - USB_OTG_DEP0XFRSIZ_TypeDef deptsiz; - USB_OTG_INEPREGS *in_regs; - uint32_t fifoemptymsk = 0; - - depctl.d32 = 0; - deptsiz.d32 = 0; - /* IN endpoint */ - if (ep->is_in == 1) - { - in_regs = pdev->regs.INEP_REGS[0]; - depctl.d32 = USB_OTG_READ_REG32(&in_regs->DIEPCTL); - deptsiz.d32 = USB_OTG_READ_REG32(&in_regs->DIEPTSIZ); - /* Zero Length Packet? */ - if (ep->xfer_len == 0) - { - deptsiz.b.xfersize = 0; - deptsiz.b.pktcnt = 1; - - } - else - { - if (ep->xfer_len > ep->maxpacket) - { - ep->xfer_len = ep->maxpacket; - deptsiz.b.xfersize = ep->maxpacket; - } - else - { - deptsiz.b.xfersize = ep->xfer_len; - } - deptsiz.b.pktcnt = 1; - } - USB_OTG_WRITE_REG32(&in_regs->DIEPTSIZ, deptsiz.d32); - - if (pdev->cfg.dma_enable == 1) - { - USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPDMA, ep->dma_addr); - } - - /* EP enable, IN data in FIFO */ - depctl.b.cnak = 1; - depctl.b.epena = 1; - USB_OTG_WRITE_REG32(&in_regs->DIEPCTL, depctl.d32); - - - - if (pdev->cfg.dma_enable == 0) - { - /* Enable the Tx FIFO Empty Interrupt for this EP */ - if (ep->xfer_len > 0) - { - { - fifoemptymsk |= 1 << ep->num; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, 0, fifoemptymsk); - } - } - } - } - else - { - /* OUT endpoint */ - depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); - deptsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ); - /* Program the transfer size and packet count as follows: - * xfersize = N * (maxpacket + 4 - (maxpacket % 4)) - * pktcnt = N */ - if (ep->xfer_len == 0) - { - deptsiz.b.xfersize = ep->maxpacket; - deptsiz.b.pktcnt = 1; - } - else - { - ep->xfer_len = ep->maxpacket; - deptsiz.b.xfersize = ep->maxpacket; - deptsiz.b.pktcnt = 1; - } - USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ, deptsiz.d32); - if (pdev->cfg.dma_enable == 1) - { - USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPDMA, ep->dma_addr); - } - /* EP enable */ - depctl.b.cnak = 1; - depctl.b.epena = 1; - USB_OTG_WRITE_REG32 (&(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL), depctl.d32); - - } - return status; -} - - -/** -* @brief USB_OTG_EPSetStall : Set the EP STALL -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EPSetStall(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - __IO uint32_t *depctl_addr; - - depctl.d32 = 0; - if (ep->is_in == 1) - { - depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - /* set the disable and stall bits */ - if (depctl.b.epena) - { - depctl.b.epdis = 1; - } - depctl.b.stall = 1; - USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); - } - else - { - depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - /* set the stall bit */ - depctl.b.stall = 1; - USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); - } - return status; -} - - -/** -* @brief Clear the EP STALL -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EPClearStall(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - __IO uint32_t *depctl_addr; - - depctl.d32 = 0; - - if (ep->is_in == 1) - { - depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); - } - else - { - depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); - } - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - /* clear the stall bits */ - depctl.b.stall = 0; - if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK) - { - depctl.b.setd0pid = 1; /* DATA0 */ - } - USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); - return status; -} - - -/** -* @brief USB_OTG_ReadDevAllOutEp_itr : returns OUT endpoint interrupt bits -* @param pdev : Selected device -* @retval OUT endpoint interrupt bits -*/ -uint32_t USB_OTG_ReadDevAllOutEp_itr(USB_OTG_CORE_HANDLE *pdev) -{ - uint32_t v; - v = USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINT); - v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINTMSK); - return ((v & 0xffff0000) >> 16); -} - - -/** -* @brief USB_OTG_ReadDevOutEP_itr : returns Device OUT EP Interrupt register -* @param pdev : Selected device -* @param ep : end point number -* @retval Device OUT EP Interrupt register -*/ -uint32_t USB_OTG_ReadDevOutEP_itr(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) -{ - uint32_t v; - v = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[epnum]->DOEPINT); - v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DOEPMSK); - return v; -} - - -/** -* @brief USB_OTG_ReadDevAllInEPItr : Get int status register -* @param pdev : Selected device -* @retval int status register -*/ -uint32_t USB_OTG_ReadDevAllInEPItr(USB_OTG_CORE_HANDLE *pdev) -{ - uint32_t v; - v = USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINT); - v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINTMSK); - return (v & 0xffff); -} - -/** -* @brief configures EPO to receive SETUP packets -* @param None -* @retval : None -*/ -void USB_OTG_EP0_OutStart(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_DEP0XFRSIZ_TypeDef doeptsize0; - doeptsize0.d32 = 0; - doeptsize0.b.supcnt = 3; - doeptsize0.b.pktcnt = 1; - doeptsize0.b.xfersize = 8 * 3; - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPTSIZ, doeptsize0.d32 ); - - if (pdev->cfg.dma_enable == 1) - { - USB_OTG_DEPCTL_TypeDef doepctl; - doepctl.d32 = 0; - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPDMA, - (uint32_t)&pdev->dev.setup_packet); - - /* EP enable */ - doepctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[0]->DOEPCTL); - doepctl.b.epena = 1; - doepctl.d32 = 0x80008000; - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPCTL, doepctl.d32); - } -} - -/** -* @brief USB_OTG_RemoteWakeup : active remote wakeup signalling -* @param None -* @retval : None -*/ -void USB_OTG_ActiveRemoteWakeup(USB_OTG_CORE_HANDLE *pdev) -{ - - USB_OTG_DCTL_TypeDef dctl; - USB_OTG_DSTS_TypeDef dsts; - USB_OTG_PCGCCTL_TypeDef power; - - if (pdev->dev.DevRemoteWakeup) - { - dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - if(dsts.b.suspsts == 1) - { - if(pdev->cfg.low_power) - { - /* un-gate USB Core clock */ - power.d32 = USB_OTG_READ_REG32(&pdev->regs.PCGCCTL); - power.b.gatehclk = 0; - power.b.stoppclk = 0; - USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32); - } - /* active Remote wakeup signaling */ - dctl.d32 = 0; - dctl.b.rmtwkupsig = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, 0, dctl.d32); - USB_OTG_BSP_mDelay(5); - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, 0 ); - } - } -} - - -/** -* @brief USB_OTG_UngateClock : active USB Core clock -* @param None -* @retval : None -*/ -void USB_OTG_UngateClock(USB_OTG_CORE_HANDLE *pdev) -{ - if(pdev->cfg.low_power) - { - - USB_OTG_DSTS_TypeDef dsts; - USB_OTG_PCGCCTL_TypeDef power; - - dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - - if(dsts.b.suspsts == 1) - { - /* un-gate USB Core clock */ - power.d32 = USB_OTG_READ_REG32(&pdev->regs.PCGCCTL); - power.b.gatehclk = 0; - power.b.stoppclk = 0; - USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32); - - } - } -} - -/** -* @brief Stop the device and clean up fifo's -* @param None -* @retval : None -*/ -void USB_OTG_StopDevice(USB_OTG_CORE_HANDLE *pdev) -{ - uint32_t i; - - pdev->dev.device_status = 1; - - for (i = 0; i < pdev->cfg.dev_endpoints ; i++) - { - USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF); - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF); - } - - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, 0 ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, 0 ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, 0 ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF ); - - /* Flush the FIFO */ - USB_OTG_FlushRxFifo(pdev); - USB_OTG_FlushTxFifo(pdev , 0x10 ); -} - -/** -* @brief returns the EP Status -* @param pdev : Selected device -* ep : endpoint structure -* @retval : EP status -*/ - -uint32_t USB_OTG_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,USB_OTG_EP *ep) -{ - USB_OTG_DEPCTL_TypeDef depctl; - __IO uint32_t *depctl_addr; - uint32_t Status = 0; - - depctl.d32 = 0; - if (ep->is_in == 1) - { - depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - - if (depctl.b.stall == 1) - Status = USB_OTG_EP_TX_STALL; - else if (depctl.b.naksts == 1) - Status = USB_OTG_EP_TX_NAK; - else - Status = USB_OTG_EP_TX_VALID; - - } - else - { - depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - if (depctl.b.stall == 1) - Status = USB_OTG_EP_RX_STALL; - else if (depctl.b.naksts == 1) - Status = USB_OTG_EP_RX_NAK; - else - Status = USB_OTG_EP_RX_VALID; - } - - /* Return the current status */ - return Status; -} - -/** -* @brief Set the EP Status -* @param pdev : Selected device -* Status : new Status -* ep : EP structure -* @retval : None -*/ -void USB_OTG_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep , uint32_t Status) -{ - USB_OTG_DEPCTL_TypeDef depctl; - __IO uint32_t *depctl_addr; - - depctl.d32 = 0; - - /* Process for IN endpoint */ - if (ep->is_in == 1) - { - depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - - if (Status == USB_OTG_EP_TX_STALL) - { - USB_OTG_EPSetStall(pdev, ep); return; - } - else if (Status == USB_OTG_EP_TX_NAK) - depctl.b.snak = 1; - else if (Status == USB_OTG_EP_TX_VALID) - { - if (depctl.b.stall == 1) - { - ep->even_odd_frame = 0; - USB_OTG_EPClearStall(pdev, ep); - return; - } - depctl.b.cnak = 1; - depctl.b.usbactep = 1; - depctl.b.epena = 1; - } - else if (Status == USB_OTG_EP_TX_DIS) - depctl.b.usbactep = 0; - } - else /* Process for OUT endpoint */ - { - depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - - if (Status == USB_OTG_EP_RX_STALL) { - depctl.b.stall = 1; - } - else if (Status == USB_OTG_EP_RX_NAK) - depctl.b.snak = 1; - else if (Status == USB_OTG_EP_RX_VALID) - { - if (depctl.b.stall == 1) - { - ep->even_odd_frame = 0; - USB_OTG_EPClearStall(pdev, ep); - return; - } - depctl.b.cnak = 1; - depctl.b.usbactep = 1; - depctl.b.epena = 1; - } - else if (Status == USB_OTG_EP_RX_DIS) - { - depctl.b.usbactep = 0; - } - } - - USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); -} - -#endif -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/usb/usb_dcd.c b/radio/bootloader/usb/usb_dcd.c deleted file mode 100644 index 36428e2a0..000000000 --- a/radio/bootloader/usb/usb_dcd.c +++ /dev/null @@ -1,478 +0,0 @@ -/** - ****************************************************************************** - * @file usb_dcd.c - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief Peripheral Device Interface Layer - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_dcd.h" -#include "usb_bsp.h" - - -/** @addtogroup USB_OTG_DRIVER -* @{ -*/ - -/** @defgroup USB_DCD -* @brief This file is the interface between EFSL ans Host mass-storage class -* @{ -*/ - - -/** @defgroup USB_DCD_Private_Defines -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_DCD_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - - -/** @defgroup USB_DCD_Private_Macros -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_DCD_Private_Variables -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_DCD_Private_FunctionPrototypes -* @{ -*/ - -/** -* @} -*/ - - -/** @defgroup USB_DCD_Private_Functions -* @{ -*/ - - - -void DCD_Init(USB_OTG_CORE_HANDLE *pdev , - USB_OTG_CORE_ID_TypeDef coreID) -{ - uint32_t i; - USB_OTG_EP *ep; - - USB_OTG_SelectCore (pdev , coreID); - - pdev->dev.device_status = USB_OTG_DEFAULT; - pdev->dev.device_address = 0; - - /* Init ep structure */ - for (i = 0; i < pdev->cfg.dev_endpoints ; i++) - { - ep = &pdev->dev.in_ep[i]; - /* Init ep structure */ - ep->is_in = 1; - ep->num = i; - ep->tx_fifo_num = i; - /* Control until ep is actvated */ - ep->type = EP_TYPE_CTRL; - ep->maxpacket = USB_OTG_MAX_EP0_SIZE; - ep->xfer_buff = 0; - ep->xfer_len = 0; - } - - for (i = 0; i < pdev->cfg.dev_endpoints; i++) - { - ep = &pdev->dev.out_ep[i]; - /* Init ep structure */ - ep->is_in = 0; - ep->num = i; - ep->tx_fifo_num = i; - /* Control until ep is activated */ - ep->type = EP_TYPE_CTRL; - ep->maxpacket = USB_OTG_MAX_EP0_SIZE; - ep->xfer_buff = 0; - ep->xfer_len = 0; - } - - USB_OTG_DisableGlobalInt(pdev); - - /*Init the Core (common init.) */ - USB_OTG_CoreInit(pdev); - - - /* Force Device Mode*/ - USB_OTG_SetCurrentMode(pdev, DEVICE_MODE); - - /* Init Device */ - USB_OTG_CoreInitDev(pdev); - - - /* Enable USB Global interrupt */ - USB_OTG_EnableGlobalInt(pdev); -} - - -/** -* @brief Configure an EP -* @param pdev : Device instance -* @param epdesc : Endpoint Descriptor -* @retval : status -*/ -uint32_t DCD_EP_Open(USB_OTG_CORE_HANDLE *pdev , - uint8_t ep_addr, - uint16_t ep_mps, - uint8_t ep_type) -{ - USB_OTG_EP *ep; - - if ((ep_addr & 0x80) == 0x80) - { - ep = &pdev->dev.in_ep[ep_addr & 0x7F]; - } - else - { - ep = &pdev->dev.out_ep[ep_addr & 0x7F]; - } - ep->num = ep_addr & 0x7F; - - ep->is_in = (0x80 & ep_addr) != 0; - ep->maxpacket = ep_mps; - ep->type = ep_type; - if (ep->is_in) - { - /* Assign a Tx FIFO */ - ep->tx_fifo_num = ep->num; - } - /* Set initial data PID. */ - if (ep_type == USB_OTG_EP_BULK ) - { - ep->data_pid_start = 0; - } - USB_OTG_EPActivate(pdev , ep ); - return 0; -} -/** -* @brief called when an EP is disabled -* @param pdev: device instance -* @param ep_addr: endpoint address -* @retval : status -*/ -uint32_t DCD_EP_Close(USB_OTG_CORE_HANDLE *pdev , uint8_t ep_addr) -{ - USB_OTG_EP *ep; - - if ((ep_addr&0x80) == 0x80) - { - ep = &pdev->dev.in_ep[ep_addr & 0x7F]; - } - else - { - ep = &pdev->dev.out_ep[ep_addr & 0x7F]; - } - ep->num = ep_addr & 0x7F; - ep->is_in = (0x80 & ep_addr) != 0; - USB_OTG_EPDeactivate(pdev , ep ); - return 0; -} - - -/** -* @brief DCD_EP_PrepareRx -* @param pdev: device instance -* @param ep_addr: endpoint address -* @param pbuf: pointer to Rx buffer -* @param buf_len: data length -* @retval : status -*/ -uint32_t DCD_EP_PrepareRx( USB_OTG_CORE_HANDLE *pdev, - uint8_t ep_addr, - uint8_t *pbuf, - uint16_t buf_len) -{ - USB_OTG_EP *ep; - - ep = &pdev->dev.out_ep[ep_addr & 0x7F]; - - /*setup and start the Xfer */ - ep->xfer_buff = pbuf; - ep->xfer_len = buf_len; - ep->xfer_count = 0; - ep->is_in = 0; - ep->num = ep_addr & 0x7F; - - if (pdev->cfg.dma_enable == 1) - { - ep->dma_addr = (uint32_t)pbuf; - } - - if ( ep->num == 0 ) - { - USB_OTG_EP0StartXfer(pdev , ep); - } - else - { - USB_OTG_EPStartXfer(pdev, ep ); - } - return 0; -} - -/** -* @brief Transmit data over USB -* @param pdev: device instance -* @param ep_addr: endpoint address -* @param pbuf: pointer to Tx buffer -* @param buf_len: data length -* @retval : status -*/ -uint32_t DCD_EP_Tx ( USB_OTG_CORE_HANDLE *pdev, - uint8_t ep_addr, - uint8_t *pbuf, - uint32_t buf_len) -{ - USB_OTG_EP *ep; - - ep = &pdev->dev.in_ep[ep_addr & 0x7F]; - - /* Setup and start the Transfer */ - ep->is_in = 1; - ep->num = ep_addr & 0x7F; - ep->xfer_buff = pbuf; - ep->dma_addr = (uint32_t)pbuf; - ep->xfer_count = 0; - ep->xfer_len = buf_len; - - if ( ep->num == 0 ) - { - USB_OTG_EP0StartXfer(pdev , ep); - } - else - { - USB_OTG_EPStartXfer(pdev, ep ); - } - return 0; -} - - -/** -* @brief Stall an endpoint. -* @param pdev: device instance -* @param epnum: endpoint address -* @retval : status -*/ -uint32_t DCD_EP_Stall (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum) -{ - USB_OTG_EP *ep; - if ((0x80 & epnum) == 0x80) - { - ep = &pdev->dev.in_ep[epnum & 0x7F]; - } - else - { - ep = &pdev->dev.out_ep[epnum]; - } - - ep->is_stall = 1; - ep->num = epnum & 0x7F; - ep->is_in = ((epnum & 0x80) == 0x80); - - USB_OTG_EPSetStall(pdev , ep); - return (0); -} - - -/** -* @brief Clear stall condition on endpoints. -* @param pdev: device instance -* @param epnum: endpoint address -* @retval : status -*/ -uint32_t DCD_EP_ClrStall (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum) -{ - USB_OTG_EP *ep; - if ((0x80 & epnum) == 0x80) - { - ep = &pdev->dev.in_ep[epnum & 0x7F]; - } - else - { - ep = &pdev->dev.out_ep[epnum]; - } - - ep->is_stall = 0; - ep->num = epnum & 0x7F; - ep->is_in = ((epnum & 0x80) == 0x80); - - USB_OTG_EPClearStall(pdev , ep); - return (0); -} - - -/** -* @brief This Function flushes the FIFOs. -* @param pdev: device instance -* @param epnum: endpoint address -* @retval : status -*/ -uint32_t DCD_EP_Flush (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) -{ - - if ((epnum & 0x80) == 0x80) - { - USB_OTG_FlushTxFifo(pdev, epnum & 0x7F); - } - else - { - USB_OTG_FlushRxFifo(pdev); - } - - return (0); -} - - -/** -* @brief This Function set USB device address -* @param pdev: device instance -* @param address: new device address -* @retval : status -*/ -void DCD_EP_SetAddress (USB_OTG_CORE_HANDLE *pdev, uint8_t address) -{ - USB_OTG_DCFG_TypeDef dcfg; - dcfg.d32 = 0; - dcfg.b.devaddr = address; - USB_OTG_MODIFY_REG32( &pdev->regs.DREGS->DCFG, 0, dcfg.d32); -} - -/** -* @brief Connect device (enable internal pull-up) -* @param pdev: device instance -* @retval : None -*/ -void DCD_DevConnect (USB_OTG_CORE_HANDLE *pdev) -{ -#ifndef USE_OTG_MODE - USB_OTG_DCTL_TypeDef dctl; - dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL); - /* Connect device */ - dctl.b.sftdiscon = 0; - USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, dctl.d32); - USB_OTG_BSP_mDelay(3); -#endif -} - - -/** -* @brief Disconnect device (disable internal pull-up) -* @param pdev: device instance -* @retval : None -*/ -void DCD_DevDisconnect (USB_OTG_CORE_HANDLE *pdev) -{ -#ifndef USE_OTG_MODE - USB_OTG_DCTL_TypeDef dctl; - dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL); - /* Disconnect device for 3ms */ - dctl.b.sftdiscon = 1; - USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, dctl.d32); - USB_OTG_BSP_mDelay(3); -#endif -} - - -/** -* @brief returns the EP Status -* @param pdev : Selected device -* epnum : endpoint address -* @retval : EP status -*/ - -uint32_t DCD_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,uint8_t epnum) -{ - USB_OTG_EP *ep; - uint32_t Status = 0; - - if ((0x80 & epnum) == 0x80) - { - ep = &pdev->dev.in_ep[epnum & 0x7F]; - } - else - { - ep = &pdev->dev.out_ep[epnum]; - } - - Status = USB_OTG_GetEPStatus(pdev ,ep); - - /* Return the current status */ - return Status; -} - -/** -* @brief Set the EP Status -* @param pdev : Selected device -* Status : new Status -* epnum : EP address -* @retval : None -*/ -void DCD_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum , uint32_t Status) -{ - USB_OTG_EP *ep; - - if ((0x80 & epnum) == 0x80) - { - ep = &pdev->dev.in_ep[epnum & 0x7F]; - } - else - { - ep = &pdev->dev.out_ep[epnum]; - } - - USB_OTG_SetEPStatus(pdev ,ep , Status); -} - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/usb/usb_dcd_int.c b/radio/bootloader/usb/usb_dcd_int.c deleted file mode 100644 index 359d56997..000000000 --- a/radio/bootloader/usb/usb_dcd_int.c +++ /dev/null @@ -1,869 +0,0 @@ -/** - ****************************************************************************** - * @file usb_dcd_int.c - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief Peripheral Device interrupt subroutines - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_dcd_int.h" -/** @addtogroup USB_OTG_DRIVER -* @{ -*/ - -/** @defgroup USB_DCD_INT -* @brief This file contains the interrupt subroutines for the Device mode. -* @{ -*/ - - -/** @defgroup USB_DCD_INT_Private_Defines -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_DCD_INT_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - - -/** @defgroup USB_DCD_INT_Private_Macros -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_DCD_INT_Private_Variables -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_DCD_INT_Private_FunctionPrototypes -* @{ -*/ -/* static functions */ -static uint32_t DCD_ReadDevInEP (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum); - -/* Interrupt Handlers */ -static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_HandleSof_ISR(USB_OTG_CORE_HANDLE *pdev); - -static uint32_t DCD_HandleRxStatusQueueLevel_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_WriteEmptyTxFifo(USB_OTG_CORE_HANDLE *pdev , uint32_t epnum); - -static uint32_t DCD_HandleUsbReset_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_HandleEnumDone_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_HandleResume_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_HandleUSBSuspend_ISR(USB_OTG_CORE_HANDLE *pdev); - -static uint32_t DCD_IsoINIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_IsoOUTIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev); -#ifdef VBUS_SENSING_ENABLED -static uint32_t DCD_SessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_OTG_ISR(USB_OTG_CORE_HANDLE *pdev); -#endif - -/** -* @} -*/ - - -/** @defgroup USB_DCD_INT_Private_Functions -* @{ -*/ - - -#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED -/** -* @brief USBD_OTG_EP1OUT_ISR_Handler -* handles all USB Interrupts -* @param pdev: device instance -* @retval status -*/ -uint32_t USBD_OTG_EP1OUT_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) -{ - - USB_OTG_DOEPINTn_TypeDef doepint; - USB_OTG_DEPXFRSIZ_TypeDef deptsiz; - - doepint.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[1]->DOEPINT); - doepint.d32&= USB_OTG_READ_REG32(&pdev->regs.DREGS->DOUTEP1MSK); - - /* Transfer complete */ - if ( doepint.b.xfercompl ) - { - /* Clear the bit in DOEPINTn for this interrupt */ - CLEAR_OUT_EP_INTR(1, xfercompl); - if (pdev->cfg.dma_enable == 1) - { - deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[1]->DOEPTSIZ)); - /*ToDo : handle more than one single MPS size packet */ - pdev->dev.out_ep[1].xfer_count = pdev->dev.out_ep[1].maxpacket - \ - deptsiz.b.xfersize; - } - /* Inform upper layer: data ready */ - /* RX COMPLETE */ - USBD_DCD_INT_fops->DataOutStage(pdev , 1); - - } - - /* Endpoint disable */ - if ( doepint.b.epdisabled ) - { - /* Clear the bit in DOEPINTn for this interrupt */ - CLEAR_OUT_EP_INTR(1, epdisabled); - } - - return 1; -} - -/** -* @brief USBD_OTG_EP1IN_ISR_Handler -* handles all USB Interrupts -* @param pdev: device instance -* @retval status -*/ -uint32_t USBD_OTG_EP1IN_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) -{ - - USB_OTG_DIEPINTn_TypeDef diepint; - uint32_t fifoemptymsk, msk, emp; - - msk = USB_OTG_READ_REG32(&pdev->regs.DREGS->DINEP1MSK); - emp = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPEMPMSK); - msk |= ((emp >> 1 ) & 0x1) << 7; - diepint.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[1]->DIEPINT) & msk; - - if ( diepint.b.xfercompl ) - { - fifoemptymsk = 0x1 << 1; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, fifoemptymsk, 0); - CLEAR_IN_EP_INTR(1, xfercompl); - /* TX COMPLETE */ - USBD_DCD_INT_fops->DataInStage(pdev , 1); - } - if ( diepint.b.epdisabled ) - { - CLEAR_IN_EP_INTR(1, epdisabled); - } - if ( diepint.b.timeout ) - { - CLEAR_IN_EP_INTR(1, timeout); - } - if (diepint.b.intktxfemp) - { - CLEAR_IN_EP_INTR(1, intktxfemp); - } - if (diepint.b.inepnakeff) - { - CLEAR_IN_EP_INTR(1, inepnakeff); - } - if (diepint.b.emptyintr) - { - DCD_WriteEmptyTxFifo(pdev , 1); - CLEAR_IN_EP_INTR(1, emptyintr); - } - return 1; -} -#endif - -/** -* @brief STM32_USBF_OTG_ISR_Handler -* handles all USB Interrupts -* @param pdev: device instance -* @retval status -*/ -uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintr_status; - uint32_t retval = 0; - - if (USB_OTG_IsDeviceMode(pdev)) /* ensure that we are in device mode */ - { - gintr_status.d32 = USB_OTG_ReadCoreItr(pdev); - if (!gintr_status.d32) /* avoid spurious interrupt */ - { - return 0; - } - - if (gintr_status.b.outepintr) - { - retval |= DCD_HandleOutEP_ISR(pdev); - } - - if (gintr_status.b.inepint) - { - retval |= DCD_HandleInEP_ISR(pdev); - } - - if (gintr_status.b.modemismatch) - { - USB_OTG_GINTSTS_TypeDef gintsts; - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.modemismatch = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); - } - - if (gintr_status.b.wkupintr) - { - retval |= DCD_HandleResume_ISR(pdev); - } - - if (gintr_status.b.usbsuspend) - { - retval |= DCD_HandleUSBSuspend_ISR(pdev); - } - if (gintr_status.b.sofintr) - { - retval |= DCD_HandleSof_ISR(pdev); - - } - - if (gintr_status.b.rxstsqlvl) - { - retval |= DCD_HandleRxStatusQueueLevel_ISR(pdev); - - } - - if (gintr_status.b.usbreset) - { - retval |= DCD_HandleUsbReset_ISR(pdev); - - } - if (gintr_status.b.enumdone) - { - retval |= DCD_HandleEnumDone_ISR(pdev); - } - - if (gintr_status.b.incomplisoin) - { - retval |= DCD_IsoINIncomplete_ISR(pdev); - } - - if (gintr_status.b.incomplisoout) - { - retval |= DCD_IsoOUTIncomplete_ISR(pdev); - } -#ifdef VBUS_SENSING_ENABLED - if (gintr_status.b.sessreqintr) - { - retval |= DCD_SessionRequest_ISR(pdev); - } - - if (gintr_status.b.otgintr) - { - retval |= DCD_OTG_ISR(pdev); - } -#endif - } - return retval; -} - -#ifdef VBUS_SENSING_ENABLED -/** -* @brief DCD_SessionRequest_ISR -* Indicates that the USB_OTG controller has detected a connection -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_SessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - USBD_DCD_INT_fops->DevConnected (pdev); - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.sessreqintr = 1; - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32); - return 1; -} - -/** -* @brief DCD_OTG_ISR -* Indicates that the USB_OTG controller has detected an OTG event: -* used to detect the end of session i.e. disconnection -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_OTG_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - - USB_OTG_GOTGINT_TypeDef gotgint; - - gotgint.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGINT); - - if (gotgint.b.sesenddet) - { - USBD_DCD_INT_fops->DevDisconnected (pdev); - } - /* Clear OTG interrupt */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGINT, gotgint.d32); - return 1; -} -#endif -/** -* @brief DCD_HandleResume_ISR -* Indicates that the USB_OTG controller has detected a resume or -* remote Wake-up sequence -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleResume_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - USB_OTG_DCTL_TypeDef devctl; - USB_OTG_PCGCCTL_TypeDef power; - - if(pdev->cfg.low_power) - { - /* un-gate USB Core clock */ - power.d32 = USB_OTG_READ_REG32(&pdev->regs.PCGCCTL); - power.b.gatehclk = 0; - power.b.stoppclk = 0; - USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32); - } - - /* Clear the Remote Wake-up Signaling */ - devctl.d32 = 0; - devctl.b.rmtwkupsig = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, devctl.d32, 0); - - /* Inform upper layer by the Resume Event */ - USBD_DCD_INT_fops->Resume (pdev); - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.wkupintr = 1; - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32); - return 1; -} - -/** -* @brief USB_OTG_HandleUSBSuspend_ISR -* Indicates that SUSPEND state has been detected on the USB -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleUSBSuspend_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - USB_OTG_PCGCCTL_TypeDef power; - USB_OTG_DSTS_TypeDef dsts; - __IO uint8_t prev_status = 0; - - prev_status = pdev->dev.device_status; - USBD_DCD_INT_fops->Suspend (pdev); - - dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.usbsuspend = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); - - if((pdev->cfg.low_power) && (dsts.b.suspsts == 1) && - (pdev->dev.connection_status == 1) && - (prev_status == USB_OTG_CONFIGURED)) - { - /* switch-off the clocks */ - power.d32 = 0; - power.b.stoppclk = 1; - USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, power.d32); - - power.b.gatehclk = 1; - USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, power.d32); - - /* Request to enter Sleep mode after exit from current ISR */ - SCB->SCR |= (SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk); - } - return 1; -} - -/** -* @brief DCD_HandleInEP_ISR -* Indicates that an IN EP has a pending Interrupt -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_DIEPINTn_TypeDef diepint; - - uint32_t ep_intr; - uint32_t epnum = 0; - uint32_t fifoemptymsk; - diepint.d32 = 0; - ep_intr = USB_OTG_ReadDevAllInEPItr(pdev); - - while ( ep_intr ) - { - if (ep_intr&0x1) /* In ITR */ - { - diepint.d32 = DCD_ReadDevInEP(pdev , epnum); /* Get In ITR status */ - if ( diepint.b.xfercompl ) - { - fifoemptymsk = 0x1 << epnum; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, fifoemptymsk, 0); - CLEAR_IN_EP_INTR(epnum, xfercompl); - /* TX COMPLETE */ - USBD_DCD_INT_fops->DataInStage(pdev , epnum); - - if (pdev->cfg.dma_enable == 1) - { - if((epnum == 0) && (pdev->dev.device_state == USB_OTG_EP0_STATUS_IN)) - { - /* prepare to rx more setup packets */ - USB_OTG_EP0_OutStart(pdev); - } - } - } - if ( diepint.b.timeout ) - { - CLEAR_IN_EP_INTR(epnum, timeout); - } - if (diepint.b.intktxfemp) - { - CLEAR_IN_EP_INTR(epnum, intktxfemp); - } - if (diepint.b.inepnakeff) - { - CLEAR_IN_EP_INTR(epnum, inepnakeff); - } - if ( diepint.b.epdisabled ) - { - CLEAR_IN_EP_INTR(epnum, epdisabled); - } - if (diepint.b.emptyintr) - { - - DCD_WriteEmptyTxFifo(pdev , epnum); - - CLEAR_IN_EP_INTR(epnum, emptyintr); - } - } - epnum++; - ep_intr >>= 1; - } - - return 1; -} - -/** -* @brief DCD_HandleOutEP_ISR -* Indicates that an OUT EP has a pending Interrupt -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - uint32_t ep_intr; - USB_OTG_DOEPINTn_TypeDef doepint; - USB_OTG_DEPXFRSIZ_TypeDef deptsiz; - uint32_t epnum = 0; - - doepint.d32 = 0; - - /* Read in the device interrupt bits */ - ep_intr = USB_OTG_ReadDevAllOutEp_itr(pdev); - - while ( ep_intr ) - { - if (ep_intr&0x1) - { - - doepint.d32 = USB_OTG_ReadDevOutEP_itr(pdev, epnum); - - /* Transfer complete */ - if ( doepint.b.xfercompl ) - { - /* Clear the bit in DOEPINTn for this interrupt */ - CLEAR_OUT_EP_INTR(epnum, xfercompl); - if (pdev->cfg.dma_enable == 1) - { - deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[epnum]->DOEPTSIZ)); - /*ToDo : handle more than one single MPS size packet */ - pdev->dev.out_ep[epnum].xfer_count = pdev->dev.out_ep[epnum].maxpacket - \ - deptsiz.b.xfersize; - } - /* Inform upper layer: data ready */ - /* RX COMPLETE */ - USBD_DCD_INT_fops->DataOutStage(pdev , epnum); - - if (pdev->cfg.dma_enable == 1) - { - if((epnum == 0) && (pdev->dev.device_state == USB_OTG_EP0_STATUS_OUT)) - { - /* prepare to rx more setup packets */ - USB_OTG_EP0_OutStart(pdev); - } - } - } - /* Endpoint disable */ - if ( doepint.b.epdisabled ) - { - /* Clear the bit in DOEPINTn for this interrupt */ - CLEAR_OUT_EP_INTR(epnum, epdisabled); - } - /* Setup Phase Done (control EPs) */ - if ( doepint.b.setup ) - { - - /* inform the upper layer that a setup packet is available */ - /* SETUP COMPLETE */ - USBD_DCD_INT_fops->SetupStage(pdev); - CLEAR_OUT_EP_INTR(epnum, setup); - } - } - epnum++; - ep_intr >>= 1; - } - return 1; -} - -/** -* @brief DCD_HandleSof_ISR -* Handles the SOF Interrupts -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleSof_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef GINTSTS; - - - USBD_DCD_INT_fops->SOF(pdev); - - /* Clear interrupt */ - GINTSTS.d32 = 0; - GINTSTS.b.sofintr = 1; - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, GINTSTS.d32); - - return 1; -} - -/** -* @brief DCD_HandleRxStatusQueueLevel_ISR -* Handles the Rx Status Queue Level Interrupt -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleRxStatusQueueLevel_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTMSK_TypeDef int_mask; - USB_OTG_DRXSTS_TypeDef status; - USB_OTG_EP *ep; - - /* Disable the Rx Status Queue Level interrupt */ - int_mask.d32 = 0; - int_mask.b.rxstsqlvl = 1; - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, int_mask.d32, 0); - - /* Get the Status from the top of the FIFO */ - status.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRXSTSP ); - - ep = &pdev->dev.out_ep[status.b.epnum]; - - switch (status.b.pktsts) - { - case STS_GOUT_NAK: - break; - case STS_DATA_UPDT: - if (status.b.bcnt) - { - USB_OTG_ReadPacket(pdev,ep->xfer_buff, status.b.bcnt); - ep->xfer_buff += status.b.bcnt; - ep->xfer_count += status.b.bcnt; - } - break; - case STS_XFER_COMP: - break; - case STS_SETUP_COMP: - break; - case STS_SETUP_UPDT: - /* Copy the setup packet received in FIFO into the setup buffer in RAM */ - USB_OTG_ReadPacket(pdev , pdev->dev.setup_packet, 8); - ep->xfer_count += status.b.bcnt; - break; - default: - break; - } - - /* Enable the Rx Status Queue Level interrupt */ - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, int_mask.d32); - - return 1; -} - -/** -* @brief DCD_WriteEmptyTxFifo -* check FIFO for the next packet to be loaded -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_WriteEmptyTxFifo(USB_OTG_CORE_HANDLE *pdev, uint32_t epnum) -{ - USB_OTG_DTXFSTSn_TypeDef txstatus; - USB_OTG_EP *ep; - uint32_t len = 0; - uint32_t len32b; - txstatus.d32 = 0; - - ep = &pdev->dev.in_ep[epnum]; - - len = ep->xfer_len - ep->xfer_count; - - if (len > ep->maxpacket) - { - len = ep->maxpacket; - } - - len32b = (len + 3) / 4; - txstatus.d32 = USB_OTG_READ_REG32( &pdev->regs.INEP_REGS[epnum]->DTXFSTS); - - - - while (txstatus.b.txfspcavail > len32b && - ep->xfer_count < ep->xfer_len && - ep->xfer_len != 0) - { - /* Write the FIFO */ - len = ep->xfer_len - ep->xfer_count; - - if (len > ep->maxpacket) - { - len = ep->maxpacket; - } - len32b = (len + 3) / 4; - - USB_OTG_WritePacket (pdev , ep->xfer_buff, epnum, len); - - ep->xfer_buff += len; - ep->xfer_count += len; - - txstatus.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[epnum]->DTXFSTS); - } - - return 1; -} - -/** -* @brief DCD_HandleUsbReset_ISR -* This interrupt occurs when a USB Reset is detected -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleUsbReset_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_DAINT_TypeDef daintmsk; - USB_OTG_DOEPMSK_TypeDef doepmsk; - USB_OTG_DIEPMSK_TypeDef diepmsk; - USB_OTG_DCFG_TypeDef dcfg; - USB_OTG_DCTL_TypeDef dctl; - USB_OTG_GINTSTS_TypeDef gintsts; - uint32_t i; - - dctl.d32 = 0; - daintmsk.d32 = 0; - doepmsk.d32 = 0; - diepmsk.d32 = 0; - dcfg.d32 = 0; - gintsts.d32 = 0; - - /* Clear the Remote Wake-up Signaling */ - dctl.b.rmtwkupsig = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, 0 ); - - /* Flush the Tx FIFO */ - USB_OTG_FlushTxFifo(pdev , 0 ); - - for (i = 0; i < pdev->cfg.dev_endpoints ; i++) - { - USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF); - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF); - } - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF ); - - daintmsk.ep.in = 1; - daintmsk.ep.out = 1; - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, daintmsk.d32 ); - - doepmsk.b.setup = 1; - doepmsk.b.xfercompl = 1; - doepmsk.b.epdisabled = 1; - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, doepmsk.d32 ); -#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOUTEP1MSK, doepmsk.d32 ); -#endif - diepmsk.b.xfercompl = 1; - diepmsk.b.timeout = 1; - diepmsk.b.epdisabled = 1; - - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, diepmsk.d32 ); -#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DINEP1MSK, diepmsk.d32 ); -#endif - /* Reset Device Address */ - dcfg.d32 = USB_OTG_READ_REG32( &pdev->regs.DREGS->DCFG); - dcfg.b.devaddr = 0; - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DCFG, dcfg.d32); - - - /* setup EP0 to receive SETUP packets */ - USB_OTG_EP0_OutStart(pdev); - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.usbreset = 1; - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32); - - /*Reset internal state machine */ - USBD_DCD_INT_fops->Reset(pdev); - return 1; -} - -/** -* @brief DCD_HandleEnumDone_ISR -* Read the device status register and set the device speed -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleEnumDone_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - USB_OTG_GUSBCFG_TypeDef gusbcfg; - - USB_OTG_EP0Activate(pdev); - - /* Set USB turn-around time based on device speed and PHY interface. */ - gusbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); - - /* Full or High speed */ - if ( USB_OTG_GetDeviceSpeed(pdev) == USB_SPEED_HIGH) - { - pdev->cfg.speed = USB_OTG_SPEED_HIGH; - pdev->cfg.mps = USB_OTG_HS_MAX_PACKET_SIZE ; - gusbcfg.b.usbtrdtim = 9; - } - else - { - pdev->cfg.speed = USB_OTG_SPEED_FULL; - pdev->cfg.mps = USB_OTG_FS_MAX_PACKET_SIZE ; - gusbcfg.b.usbtrdtim = 5; - } - - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, gusbcfg.d32); - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.enumdone = 1; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, gintsts.d32 ); - return 1; -} - - -/** -* @brief DCD_IsoINIncomplete_ISR -* handle the ISO IN incomplete interrupt -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_IsoINIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - - gintsts.d32 = 0; - - USBD_DCD_INT_fops->IsoINIncomplete (pdev); - - /* Clear interrupt */ - gintsts.b.incomplisoin = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); - - return 1; -} - -/** -* @brief DCD_IsoOUTIncomplete_ISR -* handle the ISO OUT incomplete interrupt -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_IsoOUTIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - - gintsts.d32 = 0; - - USBD_DCD_INT_fops->IsoOUTIncomplete (pdev); - - /* Clear interrupt */ - gintsts.b.incomplisoout = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); - return 1; -} -/** -* @brief DCD_ReadDevInEP -* Reads ep flags -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_ReadDevInEP (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum) -{ - uint32_t v, msk, emp; - msk = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPMSK); - emp = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPEMPMSK); - msk |= ((emp >> epnum) & 0x1) << 7; - v = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[epnum]->DIEPINT) & msk; - return v; -} - - - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/usb/usbd_core.c b/radio/bootloader/usb/usbd_core.c deleted file mode 100644 index c09028eef..000000000 --- a/radio/bootloader/usb/usbd_core.c +++ /dev/null @@ -1,506 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_core.c - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief This file provides all the USBD core functions. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_core.h" -#include "usbd_req.h" -#include "usbd_ioreq.h" -#include "usb_dcd_int.h" -#include "usb_bsp.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY -* @{ -*/ - - -/** @defgroup USBD_CORE -* @brief usbd core module -* @{ -*/ - -/** @defgroup USBD_CORE_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USBD_CORE_Private_Defines -* @{ -*/ - -/** -* @} -*/ - - -/** @defgroup USBD_CORE_Private_Macros -* @{ -*/ -/** -* @} -*/ - - - - -/** @defgroup USBD_CORE_Private_FunctionPrototypes -* @{ -*/ -static uint8_t USBD_SetupStage(USB_OTG_CORE_HANDLE *pdev); -static uint8_t USBD_DataOutStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); -static uint8_t USBD_DataInStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); -static uint8_t USBD_SOF(USB_OTG_CORE_HANDLE *pdev); -static uint8_t USBD_Reset(USB_OTG_CORE_HANDLE *pdev); -static uint8_t USBD_Suspend(USB_OTG_CORE_HANDLE *pdev); -static uint8_t USBD_Resume(USB_OTG_CORE_HANDLE *pdev); -#ifdef VBUS_SENSING_ENABLED -static uint8_t USBD_DevConnected(USB_OTG_CORE_HANDLE *pdev); -static uint8_t USBD_DevDisconnected(USB_OTG_CORE_HANDLE *pdev); -#endif -static uint8_t USBD_IsoINIncomplete(USB_OTG_CORE_HANDLE *pdev); -static uint8_t USBD_IsoOUTIncomplete(USB_OTG_CORE_HANDLE *pdev); -static uint8_t USBD_RunTestMode (USB_OTG_CORE_HANDLE *pdev) ; -/** -* @} -*/ - -/** @defgroup USBD_CORE_Private_Variables -* @{ -*/ - -__IO USB_OTG_DCTL_TypeDef SET_TEST_MODE; - -USBD_DCD_INT_cb_TypeDef USBD_DCD_INT_cb = -{ - USBD_DataOutStage, - USBD_DataInStage, - USBD_SetupStage, - USBD_SOF, - USBD_Reset, - USBD_Suspend, - USBD_Resume, - USBD_IsoINIncomplete, - USBD_IsoOUTIncomplete, -#ifdef VBUS_SENSING_ENABLED -USBD_DevConnected, -USBD_DevDisconnected, -#endif -}; - -USBD_DCD_INT_cb_TypeDef *USBD_DCD_INT_fops = &USBD_DCD_INT_cb; -/** -* @} -*/ - -/** @defgroup USBD_CORE_Private_Functions -* @{ -*/ - -/** -* @brief USBD_Init -* Initailizes the device stack and load the class driver -* @param pdev: device instance -* @param core_address: USB OTG core ID -* @param class_cb: Class callback structure address -* @param usr_cb: User callback structure address -* @retval None -*/ -void USBD_Init(USB_OTG_CORE_HANDLE *pdev, - USB_OTG_CORE_ID_TypeDef coreID, - USBD_DEVICE *pDevice, - USBD_Class_cb_TypeDef *class_cb, - USBD_Usr_cb_TypeDef *usr_cb) -{ - /* Hardware Init */ - USB_OTG_BSP_Init(pdev); - - USBD_DeInit(pdev); - - /*Register class and user callbacks */ - pdev->dev.class_cb = class_cb; - pdev->dev.usr_cb = usr_cb; - pdev->dev.usr_device = pDevice; - - /* set USB OTG core params */ - DCD_Init(pdev , coreID); - - /* Upon Init call usr callback */ - pdev->dev.usr_cb->Init(); - - /* Enable Interrupts */ - USB_OTG_BSP_EnableInterrupt(pdev); -} - -/** -* @brief USBD_DeInit -* Re-Initialize th device library -* @param pdev: device instance -* @retval status: status -*/ -USBD_Status USBD_DeInit(USB_OTG_CORE_HANDLE *pdev) -{ - /* Software Init */ - - return USBD_OK; -} - -/** -* @brief USBD_SetupStage -* Handle the setup stage -* @param pdev: device instance -* @retval status -*/ -static uint8_t USBD_SetupStage(USB_OTG_CORE_HANDLE *pdev) -{ - USB_SETUP_REQ req; - - USBD_ParseSetupRequest(pdev , &req); - - switch (req.bmRequest & 0x1F) - { - case USB_REQ_RECIPIENT_DEVICE: - USBD_StdDevReq (pdev, &req); - break; - - case USB_REQ_RECIPIENT_INTERFACE: - USBD_StdItfReq(pdev, &req); - break; - - case USB_REQ_RECIPIENT_ENDPOINT: - USBD_StdEPReq(pdev, &req); - break; - - default: - DCD_EP_Stall(pdev , req.bmRequest & 0x80); - break; - } - return USBD_OK; -} - -/** -* @brief USBD_DataOutStage -* Handle data out stage -* @param pdev: device instance -* @param epnum: endpoint index -* @retval status -*/ -static uint8_t USBD_DataOutStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) -{ - USB_OTG_EP *ep; - - if(epnum == 0) - { - ep = &pdev->dev.out_ep[0]; - if ( pdev->dev.device_state == USB_OTG_EP0_DATA_OUT) - { - if(ep->rem_data_len > ep->maxpacket) - { - ep->rem_data_len -= ep->maxpacket; - - if(pdev->cfg.dma_enable == 1) - { - /* in slave mode this, is handled by the RxSTSQLvl ISR */ - ep->xfer_buff += ep->maxpacket; - } - USBD_CtlContinueRx (pdev, - ep->xfer_buff, - MIN(ep->rem_data_len ,ep->maxpacket)); - } - else - { - if((pdev->dev.class_cb->EP0_RxReady != NULL)&& - (pdev->dev.device_status == USB_OTG_CONFIGURED)) - { - pdev->dev.class_cb->EP0_RxReady(pdev); - } - USBD_CtlSendStatus(pdev); - } - } - } - else if((pdev->dev.class_cb->DataOut != NULL)&& - (pdev->dev.device_status == USB_OTG_CONFIGURED)) - { - pdev->dev.class_cb->DataOut(pdev, epnum); - } - return USBD_OK; -} - -/** -* @brief USBD_DataInStage -* Handle data in stage -* @param pdev: device instance -* @param epnum: endpoint index -* @retval status -*/ -static uint8_t USBD_DataInStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) -{ - USB_OTG_EP *ep; - - if(epnum == 0) - { - ep = &pdev->dev.in_ep[0]; - if ( pdev->dev.device_state == USB_OTG_EP0_DATA_IN) - { - if(ep->rem_data_len > ep->maxpacket) - { - ep->rem_data_len -= ep->maxpacket; - if(pdev->cfg.dma_enable == 1) - { - /* in slave mode this, is handled by the TxFifoEmpty ISR */ - ep->xfer_buff += ep->maxpacket; - } - USBD_CtlContinueSendData (pdev, - ep->xfer_buff, - ep->rem_data_len); - } - else - { /* last packet is MPS multiple, so send ZLP packet */ - if((ep->total_data_len % ep->maxpacket == 0) && - (ep->total_data_len >= ep->maxpacket) && - (ep->total_data_len < ep->ctl_data_len )) - { - - USBD_CtlContinueSendData(pdev , NULL, 0); - ep->ctl_data_len = 0; - } - else - { - if((pdev->dev.class_cb->EP0_TxSent != NULL)&& - (pdev->dev.device_status == USB_OTG_CONFIGURED)) - { - pdev->dev.class_cb->EP0_TxSent(pdev); - } - USBD_CtlReceiveStatus(pdev); - } - } - } - if (pdev->dev.test_mode == 1) - { - USBD_RunTestMode(pdev); - pdev->dev.test_mode = 0; - } - } - else if((pdev->dev.class_cb->DataIn != NULL)&& - (pdev->dev.device_status == USB_OTG_CONFIGURED)) - { - pdev->dev.class_cb->DataIn(pdev, epnum); - } - return USBD_OK; -} - - - - -/** -* @brief USBD_RunTestMode -* Launch test mode process -* @param pdev: device instance -* @retval status -*/ -static uint8_t USBD_RunTestMode (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, SET_TEST_MODE.d32); - return USBD_OK; -} - -/** -* @brief USBD_Reset -* Handle Reset event -* @param pdev: device instance -* @retval status -*/ - -static uint8_t USBD_Reset(USB_OTG_CORE_HANDLE *pdev) -{ - /* Open EP0 OUT */ - DCD_EP_Open(pdev, - 0x00, - USB_OTG_MAX_EP0_SIZE, - EP_TYPE_CTRL); - - /* Open EP0 IN */ - DCD_EP_Open(pdev, - 0x80, - USB_OTG_MAX_EP0_SIZE, - EP_TYPE_CTRL); - - /* Upon Reset call usr call back */ - pdev->dev.device_status = USB_OTG_DEFAULT; - pdev->dev.usr_cb->DeviceReset(pdev->cfg.speed); - - return USBD_OK; -} - -/** -* @brief USBD_Resume -* Handle Resume event -* @param pdev: device instance -* @retval status -*/ - -static uint8_t USBD_Resume(USB_OTG_CORE_HANDLE *pdev) -{ - /* Upon Resume call usr call back */ - pdev->dev.usr_cb->DeviceResumed(); - pdev->dev.device_status = pdev->dev.device_old_status; - pdev->dev.device_status = USB_OTG_CONFIGURED; - return USBD_OK; -} - - -/** -* @brief USBD_Suspend -* Handle Suspend event -* @param pdev: device instance -* @retval status -*/ - -static uint8_t USBD_Suspend(USB_OTG_CORE_HANDLE *pdev) -{ - pdev->dev.device_old_status = pdev->dev.device_status; - pdev->dev.device_status = USB_OTG_SUSPENDED; - /* Upon Resume call usr call back */ - pdev->dev.usr_cb->DeviceSuspended(); - return USBD_OK; -} - - -/** -* @brief USBD_SOF -* Handle SOF event -* @param pdev: device instance -* @retval status -*/ - -static uint8_t USBD_SOF(USB_OTG_CORE_HANDLE *pdev) -{ - if(pdev->dev.class_cb->SOF) - { - pdev->dev.class_cb->SOF(pdev); - } - return USBD_OK; -} -/** -* @brief USBD_SetCfg -* Configure device and start the interface -* @param pdev: device instance -* @param cfgidx: configuration index -* @retval status -*/ - -USBD_Status USBD_SetCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx) -{ - pdev->dev.class_cb->Init(pdev, cfgidx); - - /* Upon set config call usr call back */ - pdev->dev.usr_cb->DeviceConfigured(); - return USBD_OK; -} - -/** -* @brief USBD_ClrCfg -* Clear current configuration -* @param pdev: device instance -* @param cfgidx: configuration index -* @retval status: USBD_Status -*/ -USBD_Status USBD_ClrCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx) -{ - pdev->dev.class_cb->DeInit(pdev, cfgidx); - return USBD_OK; -} - -/** -* @brief USBD_IsoINIncomplete -* Handle iso in incomplete event -* @param pdev: device instance -* @retval status -*/ -static uint8_t USBD_IsoINIncomplete(USB_OTG_CORE_HANDLE *pdev) -{ - pdev->dev.class_cb->IsoINIncomplete(pdev); - return USBD_OK; -} - -/** -* @brief USBD_IsoOUTIncomplete -* Handle iso out incomplete event -* @param pdev: device instance -* @retval status -*/ -static uint8_t USBD_IsoOUTIncomplete(USB_OTG_CORE_HANDLE *pdev) -{ - pdev->dev.class_cb->IsoOUTIncomplete(pdev); - return USBD_OK; -} - -#ifdef VBUS_SENSING_ENABLED -/** -* @brief USBD_DevConnected -* Handle device connection event -* @param pdev: device instance -* @retval status -*/ -static uint8_t USBD_DevConnected(USB_OTG_CORE_HANDLE *pdev) -{ - pdev->dev.usr_cb->DeviceConnected(); - pdev->dev.connection_status = 1; - return USBD_OK; -} - -/** -* @brief USBD_DevDisconnected -* Handle device disconnection event -* @param pdev: device instance -* @retval status -*/ -static uint8_t USBD_DevDisconnected(USB_OTG_CORE_HANDLE *pdev) -{ - pdev->dev.usr_cb->DeviceDisconnected(); - pdev->dev.class_cb->DeInit(pdev, 0); - pdev->dev.connection_status = 0; - return USBD_OK; -} -#endif -/** -* @} -*/ - - -/** -* @} -*/ - - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/radio/bootloader/usb/usbd_desc.c b/radio/bootloader/usb/usbd_desc.c deleted file mode 100644 index 373203498..000000000 --- a/radio/bootloader/usb/usbd_desc.c +++ /dev/null @@ -1,223 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_desc.c - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief This file provides the USBD descriptors and string formating method. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_core.h" -#include "usbd_desc.h" -#include "usbd_req.h" -#include "usbd_conf.h" -#include "usb_regs.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup USBD_DESC - * @brief USBD descriptors module - * @{ - */ - -/** @defgroup USBD_DESC_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_DESC_Private_Defines - * @{ - */ - -#define USBD_VID 0x0483 -#define USBD_PID 0x5720 - -#define USBD_LANGID_STRING 0x409 -#define USBD_MANUFACTURER_STRING "FrSky" - -#define USBD_PRODUCT_FS_STRING "FrSky Taranis Mass Storage" -#define USBD_SERIALNUMBER_FS_STRING "00000000001B" -#define USBD_CONFIGURATION_FS_STRING "MSC Config" -#define USBD_INTERFACE_FS_STRING "MSC Interface" - -USBD_DEVICE USR_desc = -{ - USBD_USR_DeviceDescriptor, - USBD_USR_LangIDStrDescriptor, - USBD_USR_ManufacturerStrDescriptor, - USBD_USR_ProductStrDescriptor, - USBD_USR_SerialStrDescriptor, - USBD_USR_ConfigStrDescriptor, - USBD_USR_InterfaceStrDescriptor, -}; - -/* USB Standard Device Descriptor */ -__ALIGN_BEGIN uint8_t USBD_DeviceDesc[USB_SIZ_DEVICE_DESC] __ALIGN_END = - { - 0x12, /*bLength */ - USB_DEVICE_DESCRIPTOR_TYPE, /*bDescriptorType*/ - 0x00, /*bcdUSB */ - 0x02, - 0x00, /*bDeviceClass*/ - 0x00, /*bDeviceSubClass*/ - 0x00, /*bDeviceProtocol*/ - USB_OTG_MAX_EP0_SIZE, /*bMaxPacketSize*/ - LOBYTE(USBD_VID), /*idVendor*/ - HIBYTE(USBD_VID), /*idVendor*/ - LOBYTE(USBD_PID), /*idVendor*/ - HIBYTE(USBD_PID), /*idVendor*/ - 0x00, /*bcdDevice rel. 2.00*/ - 0x02, - USBD_IDX_MFC_STR, /*Index of manufacturer string*/ - USBD_IDX_PRODUCT_STR, /*Index of product string*/ - USBD_IDX_SERIAL_STR, /*Index of serial number string*/ - USBD_CFG_MAX_NUM /*bNumConfigurations*/ - } ; /* USB_DeviceDescriptor */ - -/* USB Standard Device Descriptor */ -__ALIGN_BEGIN uint8_t USBD_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END = -{ - USB_LEN_DEV_QUALIFIER_DESC, - USB_DESC_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x01, - 0x00, -}; - -/* USB Standard Device Descriptor */ -__ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_SIZ_STRING_LANGID] __ALIGN_END = -{ - USB_SIZ_STRING_LANGID, - USB_DESC_TYPE_STRING, - LOBYTE(USBD_LANGID_STRING), - HIBYTE(USBD_LANGID_STRING), -}; - -/* -* @brief USBD_USR_DeviceDescriptor -* return the device descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_USR_DeviceDescriptor( uint8_t speed , uint16_t *length) -{ - *length = sizeof(USBD_DeviceDesc); - return USBD_DeviceDesc; -} - -/** -* @brief USBD_USR_LangIDStrDescriptor -* return the LangID string descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_USR_LangIDStrDescriptor( uint8_t speed , uint16_t *length) -{ - *length = sizeof(USBD_LangIDDesc); - return USBD_LangIDDesc; -} - - -/** -* @brief USBD_USR_ProductStrDescriptor -* return the product string descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_USR_ProductStrDescriptor( uint8_t speed , uint16_t *length) -{ - - USBD_GetString ((uint8_t*)USBD_PRODUCT_FS_STRING, USBD_StrDesc, length); - - return USBD_StrDesc; -} - -/** -* @brief USBD_USR_ManufacturerStrDescriptor -* return the manufacturer string descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_USR_ManufacturerStrDescriptor( uint8_t speed , uint16_t *length) -{ - USBD_GetString ((uint8_t*)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); - return USBD_StrDesc; -} - -/** -* @brief USBD_USR_SerialStrDescriptor -* return the serial number string descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_USR_SerialStrDescriptor( uint8_t speed , uint16_t *length) -{ - USBD_GetString ((uint8_t*)USBD_SERIALNUMBER_FS_STRING, USBD_StrDesc, length); - - return USBD_StrDesc; -} - -/** -* @brief USBD_USR_ConfigStrDescriptor -* return the configuration string descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_USR_ConfigStrDescriptor( uint8_t speed , uint16_t *length) -{ - USBD_GetString ((uint8_t *)USBD_CONFIGURATION_FS_STRING, USBD_StrDesc, length); - return USBD_StrDesc; -} - - -/** -* @brief USBD_USR_InterfaceStrDescriptor -* return the interface string descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_USR_InterfaceStrDescriptor( uint8_t speed , uint16_t *length) -{ - USBD_GetString ((uint8_t*)USBD_INTERFACE_FS_STRING, USBD_StrDesc, length); - return USBD_StrDesc; -} - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/radio/bootloader/usb/usbd_ioreq.c b/radio/bootloader/usb/usbd_ioreq.c deleted file mode 100644 index 139a86a9e..000000000 --- a/radio/bootloader/usb/usbd_ioreq.c +++ /dev/null @@ -1,244 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_ioreq.c - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief This file provides the IO requests APIs for control endpoints. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_ioreq.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup USBD_IOREQ - * @brief control I/O requests module - * @{ - */ - -/** @defgroup USBD_IOREQ_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_Variables - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_FunctionPrototypes - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_Functions - * @{ - */ - -/** -* @brief USBD_CtlSendData -* send data on the ctl pipe -* @param pdev: device instance -* @param buff: pointer to data buffer -* @param len: length of data to be sent -* @retval status -*/ -USBD_Status USBD_CtlSendData (USB_OTG_CORE_HANDLE *pdev, - uint8_t *pbuf, - uint16_t len) -{ - USBD_Status ret = USBD_OK; - - pdev->dev.in_ep[0].total_data_len = len; - pdev->dev.in_ep[0].rem_data_len = len; - pdev->dev.device_state = USB_OTG_EP0_DATA_IN; - - DCD_EP_Tx (pdev, 0, pbuf, len); - - return ret; -} - -/** -* @brief USBD_CtlContinueSendData -* continue sending data on the ctl pipe -* @param pdev: device instance -* @param buff: pointer to data buffer -* @param len: length of data to be sent -* @retval status -*/ -USBD_Status USBD_CtlContinueSendData (USB_OTG_CORE_HANDLE *pdev, - uint8_t *pbuf, - uint16_t len) -{ - USBD_Status ret = USBD_OK; - - DCD_EP_Tx (pdev, 0, pbuf, len); - - - return ret; -} - -/** -* @brief USBD_CtlPrepareRx -* receive data on the ctl pipe -* @param pdev: USB OTG device instance -* @param buff: pointer to data buffer -* @param len: length of data to be received -* @retval status -*/ -USBD_Status USBD_CtlPrepareRx (USB_OTG_CORE_HANDLE *pdev, - uint8_t *pbuf, - uint16_t len) -{ - USBD_Status ret = USBD_OK; - - pdev->dev.out_ep[0].total_data_len = len; - pdev->dev.out_ep[0].rem_data_len = len; - pdev->dev.device_state = USB_OTG_EP0_DATA_OUT; - - DCD_EP_PrepareRx (pdev, - 0, - pbuf, - len); - - - return ret; -} - -/** -* @brief USBD_CtlContinueRx -* continue receive data on the ctl pipe -* @param pdev: USB OTG device instance -* @param buff: pointer to data buffer -* @param len: length of data to be received -* @retval status -*/ -USBD_Status USBD_CtlContinueRx (USB_OTG_CORE_HANDLE *pdev, - uint8_t *pbuf, - uint16_t len) -{ - USBD_Status ret = USBD_OK; - - DCD_EP_PrepareRx (pdev, - 0, - pbuf, - len); - return ret; -} -/** -* @brief USBD_CtlSendStatus -* send zero lzngth packet on the ctl pipe -* @param pdev: USB OTG device instance -* @retval status -*/ -USBD_Status USBD_CtlSendStatus (USB_OTG_CORE_HANDLE *pdev) -{ - USBD_Status ret = USBD_OK; - pdev->dev.device_state = USB_OTG_EP0_STATUS_IN; - DCD_EP_Tx (pdev, - 0, - NULL, - 0); - - USB_OTG_EP0_OutStart(pdev); - - return ret; -} - -/** -* @brief USBD_CtlReceiveStatus -* receive zero lzngth packet on the ctl pipe -* @param pdev: USB OTG device instance -* @retval status -*/ -USBD_Status USBD_CtlReceiveStatus (USB_OTG_CORE_HANDLE *pdev) -{ - USBD_Status ret = USBD_OK; - pdev->dev.device_state = USB_OTG_EP0_STATUS_OUT; - DCD_EP_PrepareRx ( pdev, - 0, - NULL, - 0); - - USB_OTG_EP0_OutStart(pdev); - - return ret; -} - - -/** -* @brief USBD_GetRxCount -* returns the received data length -* @param pdev: USB OTG device instance -* epnum: endpoint index -* @retval Rx Data blength -*/ -uint16_t USBD_GetRxCount (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) -{ - return pdev->dev.out_ep[epnum].xfer_count; -} - -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/usb/usbd_msc_bot.c b/radio/bootloader/usb/usbd_msc_bot.c deleted file mode 100644 index 227aa6e2d..000000000 --- a/radio/bootloader/usb/usbd_msc_bot.c +++ /dev/null @@ -1,400 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_msc_bot.c - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief This file provides all the BOT protocol core functions. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_msc_bot.h" -#include "usbd_msc_scsi.h" -#include "usbd_ioreq.h" -#include "usbd_msc_mem.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup MSC_BOT - * @brief BOT protocol module - * @{ - */ - -/** @defgroup MSC_BOT_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_BOT_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup MSC_BOT_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_BOT_Private_Variables - * @{ - */ -uint16_t MSC_BOT_DataLen; -uint8_t MSC_BOT_State; -uint8_t MSC_BOT_Status; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint8_t MSC_BOT_Data[MSC_MEDIA_PACKET] __ALIGN_END ; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN MSC_BOT_CBW_TypeDef MSC_BOT_cbw __ALIGN_END ; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN MSC_BOT_CSW_TypeDef MSC_BOT_csw __ALIGN_END ; -/** - * @} - */ - - -/** @defgroup MSC_BOT_Private_FunctionPrototypes - * @{ - */ -static void MSC_BOT_CBW_Decode (USB_OTG_CORE_HANDLE *pdev); - -static void MSC_BOT_SendData (USB_OTG_CORE_HANDLE *pdev, - uint8_t* pbuf, - uint16_t len); - -static void MSC_BOT_Abort(USB_OTG_CORE_HANDLE *pdev); -/** - * @} - */ - - -/** @defgroup MSC_BOT_Private_Functions - * @{ - */ - - - -/** -* @brief MSC_BOT_Init -* Initialize the BOT Process -* @param pdev: device instance -* @retval None -*/ -void MSC_BOT_Init (USB_OTG_CORE_HANDLE *pdev) -{ - MSC_BOT_State = BOT_IDLE; - MSC_BOT_Status = BOT_STATE_NORMAL; - USBD_STORAGE_fops->Init(0); - - DCD_EP_Flush(pdev, MSC_OUT_EP); - DCD_EP_Flush(pdev, MSC_IN_EP); - /* Prapare EP to Receive First BOT Cmd */ - DCD_EP_PrepareRx (pdev, - MSC_OUT_EP, - (uint8_t *)&MSC_BOT_cbw, - BOT_CBW_LENGTH); -} - -/** -* @brief MSC_BOT_Reset -* Reset the BOT Machine -* @param pdev: device instance -* @retval None -*/ -void MSC_BOT_Reset (USB_OTG_CORE_HANDLE *pdev) -{ - MSC_BOT_State = BOT_IDLE; - MSC_BOT_Status = BOT_STATE_RECOVERY; - /* Prapare EP to Receive First BOT Cmd */ - DCD_EP_PrepareRx (pdev, - MSC_OUT_EP, - (uint8_t *)&MSC_BOT_cbw, - BOT_CBW_LENGTH); -} - -/** -* @brief MSC_BOT_DeInit -* Uninitialize the BOT Machine -* @param pdev: device instance -* @retval None -*/ -void MSC_BOT_DeInit (USB_OTG_CORE_HANDLE *pdev) -{ - MSC_BOT_State = BOT_IDLE; -} - -/** -* @brief MSC_BOT_DataIn -* Handle BOT IN data stage -* @param pdev: device instance -* @param epnum: endpoint index -* @retval None -*/ -void MSC_BOT_DataIn (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum) -{ - - switch (MSC_BOT_State) - { - case BOT_DATA_IN: - if(SCSI_ProcessCmd(pdev, - MSC_BOT_cbw.bLUN, - &MSC_BOT_cbw.CB[0]) < 0) - { - MSC_BOT_SendCSW (pdev, CSW_CMD_FAILED); - } - break; - - case BOT_SEND_DATA: - case BOT_LAST_DATA_IN: - MSC_BOT_SendCSW (pdev, CSW_CMD_PASSED); - - break; - - default: - break; - } -} -/** -* @brief MSC_BOT_DataOut -* Proccess MSC OUT data -* @param pdev: device instance -* @param epnum: endpoint index -* @retval None -*/ -void MSC_BOT_DataOut (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum) -{ - switch (MSC_BOT_State) - { - case BOT_IDLE: - MSC_BOT_CBW_Decode(pdev); - break; - - case BOT_DATA_OUT: - - if(SCSI_ProcessCmd(pdev, - MSC_BOT_cbw.bLUN, - &MSC_BOT_cbw.CB[0]) < 0) - { - MSC_BOT_SendCSW (pdev, CSW_CMD_FAILED); - } - - break; - - default: - break; - } - -} - -/** -* @brief MSC_BOT_CBW_Decode -* Decode the CBW command and set the BOT state machine accordingtly -* @param pdev: device instance -* @retval None -*/ -static void MSC_BOT_CBW_Decode (USB_OTG_CORE_HANDLE *pdev) -{ - - MSC_BOT_csw.dTag = MSC_BOT_cbw.dTag; - MSC_BOT_csw.dDataResidue = MSC_BOT_cbw.dDataLength; - - if ((USBD_GetRxCount (pdev ,MSC_OUT_EP) != BOT_CBW_LENGTH) || - (MSC_BOT_cbw.dSignature != BOT_CBW_SIGNATURE)|| - (MSC_BOT_cbw.bLUN > 1) || - (MSC_BOT_cbw.bCBLength < 1) || - (MSC_BOT_cbw.bCBLength > 16)) - { - - SCSI_SenseCode(MSC_BOT_cbw.bLUN, - ILLEGAL_REQUEST, - INVALID_CDB); - MSC_BOT_Status = BOT_STATE_ERROR; - MSC_BOT_Abort(pdev); - - } - else - { - if(SCSI_ProcessCmd(pdev, - MSC_BOT_cbw.bLUN, - &MSC_BOT_cbw.CB[0]) < 0) - { - MSC_BOT_Abort(pdev); - } - /*Burst xfer handled internally*/ - else if ((MSC_BOT_State != BOT_DATA_IN) && - (MSC_BOT_State != BOT_DATA_OUT) && - (MSC_BOT_State != BOT_LAST_DATA_IN)) - { - if (MSC_BOT_DataLen > 0) - { - MSC_BOT_SendData(pdev, - MSC_BOT_Data, - MSC_BOT_DataLen); - } - else if (MSC_BOT_DataLen == 0) - { - MSC_BOT_SendCSW (pdev, - CSW_CMD_PASSED); - } - } - } -} - -/** -* @brief MSC_BOT_SendData -* Send the requested data -* @param pdev: device instance -* @param buf: pointer to data buffer -* @param len: Data Length -* @retval None -*/ -static void MSC_BOT_SendData(USB_OTG_CORE_HANDLE *pdev, - uint8_t* buf, - uint16_t len) -{ - - len = MIN (MSC_BOT_cbw.dDataLength, len); - MSC_BOT_csw.dDataResidue -= len; - MSC_BOT_csw.bStatus = CSW_CMD_PASSED; - MSC_BOT_State = BOT_SEND_DATA; - - DCD_EP_Tx (pdev, MSC_IN_EP, buf, len); -} - -/** -* @brief MSC_BOT_SendCSW -* Send the Command Status Wrapper -* @param pdev: device instance -* @param status : CSW status -* @retval None -*/ -void MSC_BOT_SendCSW (USB_OTG_CORE_HANDLE *pdev, - uint8_t CSW_Status) -{ - MSC_BOT_csw.dSignature = BOT_CSW_SIGNATURE; - MSC_BOT_csw.bStatus = CSW_Status; - MSC_BOT_State = BOT_IDLE; - - DCD_EP_Tx (pdev, - MSC_IN_EP, - (uint8_t *)&MSC_BOT_csw, - BOT_CSW_LENGTH); - - /* Prapare EP to Receive next Cmd */ - DCD_EP_PrepareRx (pdev, - MSC_OUT_EP, - (uint8_t *)&MSC_BOT_cbw, - BOT_CBW_LENGTH); - -} - -/** -* @brief MSC_BOT_Abort -* Abort the current transfer -* @param pdev: device instance -* @retval status -*/ - -static void MSC_BOT_Abort (USB_OTG_CORE_HANDLE *pdev) -{ - - if ((MSC_BOT_cbw.bmFlags == 0) && - (MSC_BOT_cbw.dDataLength != 0) && - (MSC_BOT_Status == BOT_STATE_NORMAL) ) - { - DCD_EP_Stall(pdev, MSC_OUT_EP ); - } - DCD_EP_Stall(pdev, MSC_IN_EP); - - if(MSC_BOT_Status == BOT_STATE_ERROR) - { - DCD_EP_PrepareRx (pdev, - MSC_OUT_EP, - (uint8_t *)&MSC_BOT_cbw, - BOT_CBW_LENGTH); - } -} - -/** -* @brief MSC_BOT_CplClrFeature -* Complete the clear feature request -* @param pdev: device instance -* @param epnum: endpoint index -* @retval None -*/ - -void MSC_BOT_CplClrFeature (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum) -{ - if(MSC_BOT_Status == BOT_STATE_ERROR )/* Bad CBW Signature */ - { - DCD_EP_Stall(pdev, MSC_IN_EP); - MSC_BOT_Status = BOT_STATE_NORMAL; - } - else if(((epnum & 0x80) == 0x80) && ( MSC_BOT_Status != BOT_STATE_RECOVERY)) - { - MSC_BOT_SendCSW (pdev, CSW_CMD_FAILED); - } - -} -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/usb/usbd_msc_core.c b/radio/bootloader/usb/usbd_msc_core.c deleted file mode 100644 index 5d8d4e815..000000000 --- a/radio/bootloader/usb/usbd_msc_core.c +++ /dev/null @@ -1,496 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_msc_core.c - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief This file provides all the MSC core functions. - * - * @verbatim - * - * =================================================================== - * MSC Class Description - * =================================================================== - * This module manages the MSC class V1.0 following the "Universal - * Serial Bus Mass Storage Class (MSC) Bulk-Only Transport (BOT) Version 1.0 - * Sep. 31, 1999". - * This driver implements the following aspects of the specification: - * - Bulk-Only Transport protocol - * - Subclass : SCSI transparent command set (ref. SCSI Primary Commands - 3 (SPC-3)) - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_msc_mem.h" -#include "usbd_msc_core.h" -#include "usbd_msc_bot.h" -#include "usbd_req.h" - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup MSC_CORE - * @brief Mass storage core module - * @{ - */ - -/** @defgroup MSC_CORE_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_CORE_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup MSC_CORE_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_CORE_Private_FunctionPrototypes - * @{ - */ -uint8_t USBD_MSC_Init (void *pdev, - uint8_t cfgidx); - -uint8_t USBD_MSC_DeInit (void *pdev, - uint8_t cfgidx); - -uint8_t USBD_MSC_Setup (void *pdev, - USB_SETUP_REQ *req); - -uint8_t USBD_MSC_DataIn (void *pdev, - uint8_t epnum); - - -uint8_t USBD_MSC_DataOut (void *pdev, - uint8_t epnum); - -uint8_t *USBD_MSC_GetCfgDesc (uint8_t speed, - uint16_t *length); - -#ifdef USB_OTG_HS_CORE -uint8_t *USBD_MSC_GetOtherCfgDesc (uint8_t speed, - uint16_t *length); -#endif - - -uint8_t USBD_MSC_CfgDesc[USB_MSC_CONFIG_DESC_SIZ]; - - - - -/** - * @} - */ - - -/** @defgroup MSC_CORE_Private_Variables - * @{ - */ - - -USBD_Class_cb_TypeDef USBD_MSC_cb = -{ - USBD_MSC_Init, - USBD_MSC_DeInit, - USBD_MSC_Setup, - NULL, /*EP0_TxSent*/ - NULL, /*EP0_RxReady*/ - USBD_MSC_DataIn, - USBD_MSC_DataOut, - NULL, /*SOF */ - NULL, - NULL, - USBD_MSC_GetCfgDesc, -#ifdef USB_OTG_HS_CORE - USBD_MSC_GetOtherCfgDesc, -#endif -}; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -/* USB Mass storage device Configuration Descriptor */ -/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */ -__ALIGN_BEGIN uint8_t USBD_MSC_CfgDesc[USB_MSC_CONFIG_DESC_SIZ] __ALIGN_END = -{ - - 0x09, /* bLength: Configuation Descriptor size */ - USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ - USB_MSC_CONFIG_DESC_SIZ, - - 0x00, - 0x01, /* bNumInterfaces: 1 interface */ - 0x01, /* bConfigurationValue: */ - 0x04, /* iConfiguration: */ - 0xC0, /* bmAttributes: */ - 0x32, /* MaxPower 100 mA */ - - /******************** Mass Storage interface ********************/ - 0x09, /* bLength: Interface Descriptor size */ - 0x04, /* bDescriptorType: */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints*/ - 0x08, /* bInterfaceClass: MSC Class */ - 0x06, /* bInterfaceSubClass : SCSI transparent*/ - 0x50, /* nInterfaceProtocol */ - 0x05, /* iInterface: */ - /******************** Mass Storage Endpoints ********************/ - 0x07, /*Endpoint descriptor length = 7*/ - 0x05, /*Endpoint descriptor type */ - MSC_IN_EP, /*Endpoint address (IN, address 1) */ - 0x02, /*Bulk endpoint type */ - LOBYTE(MSC_MAX_PACKET), - HIBYTE(MSC_MAX_PACKET), - 0x00, /*Polling interval in milliseconds */ - - 0x07, /*Endpoint descriptor length = 7 */ - 0x05, /*Endpoint descriptor type */ - MSC_OUT_EP, /*Endpoint address (OUT, address 1) */ - 0x02, /*Bulk endpoint type */ - LOBYTE(MSC_MAX_PACKET), - HIBYTE(MSC_MAX_PACKET), - 0x00 /*Polling interval in milliseconds*/ -}; -#ifdef USB_OTG_HS_CORE - #ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif - #endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint8_t USBD_MSC_OtherCfgDesc[USB_MSC_CONFIG_DESC_SIZ] __ALIGN_END = -{ - - 0x09, /* bLength: Configuation Descriptor size */ - USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, - USB_MSC_CONFIG_DESC_SIZ, - - 0x00, - 0x01, /* bNumInterfaces: 1 interface */ - 0x01, /* bConfigurationValue: */ - 0x04, /* iConfiguration: */ - 0xC0, /* bmAttributes: */ - 0x32, /* MaxPower 100 mA */ - - /******************** Mass Storage interface ********************/ - 0x09, /* bLength: Interface Descriptor size */ - 0x04, /* bDescriptorType: */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints*/ - 0x08, /* bInterfaceClass: MSC Class */ - 0x06, /* bInterfaceSubClass : SCSI transparent command set*/ - 0x50, /* nInterfaceProtocol */ - 0x05, /* iInterface: */ - /******************** Mass Storage Endpoints ********************/ - 0x07, /*Endpoint descriptor length = 7*/ - 0x05, /*Endpoint descriptor type */ - MSC_IN_EP, /*Endpoint address (IN, address 1) */ - 0x02, /*Bulk endpoint type */ - 0x40, - 0x00, - 0x00, /*Polling interval in milliseconds */ - - 0x07, /*Endpoint descriptor length = 7 */ - 0x05, /*Endpoint descriptor type */ - MSC_OUT_EP, /*Endpoint address (OUT, address 1) */ - 0x02, /*Bulk endpoint type */ - 0x40, - 0x00, - 0x00 /*Polling interval in milliseconds*/ -}; -#endif - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN static uint8_t USBD_MSC_MaxLun __ALIGN_END = 0; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN static uint8_t USBD_MSC_AltSet __ALIGN_END = 0; - -/** - * @} - */ - - -/** @defgroup MSC_CORE_Private_Functions - * @{ - */ - -/** -* @brief USBD_MSC_Init -* Initialize the mass storage configuration -* @param pdev: device instance -* @param cfgidx: configuration index -* @retval status -*/ -uint8_t USBD_MSC_Init (void *pdev, - uint8_t cfgidx) -{ - USBD_MSC_DeInit(pdev , cfgidx ); - - /* Open EP IN */ - DCD_EP_Open(pdev, - MSC_IN_EP, - MSC_EPIN_SIZE, - USB_OTG_EP_BULK); - - /* Open EP OUT */ - DCD_EP_Open(pdev, - MSC_OUT_EP, - MSC_EPOUT_SIZE, - USB_OTG_EP_BULK); - - /* Init the BOT layer */ - MSC_BOT_Init(pdev); - - return USBD_OK; -} - -/** -* @brief USBD_MSC_DeInit -* DeInitilaize the mass storage configuration -* @param pdev: device instance -* @param cfgidx: configuration index -* @retval status -*/ -uint8_t USBD_MSC_DeInit (void *pdev, - uint8_t cfgidx) -{ - /* Close MSC EPs */ - DCD_EP_Close (pdev , MSC_IN_EP); - DCD_EP_Close (pdev , MSC_OUT_EP); - - /* Un Init the BOT layer */ - MSC_BOT_DeInit(pdev); - return USBD_OK; -} -/** -* @brief USBD_MSC_Setup -* Handle the MSC specific requests -* @param pdev: device instance -* @param req: USB request -* @retval status -*/ -uint8_t USBD_MSC_Setup (void *pdev, USB_SETUP_REQ *req) -{ - - switch (req->bmRequest & USB_REQ_TYPE_MASK) - { - - /* Class request */ - case USB_REQ_TYPE_CLASS : - switch (req->bRequest) - { - case BOT_GET_MAX_LUN : - - if((req->wValue == 0) && - (req->wLength == 1) && - ((req->bmRequest & 0x80) == 0x80)) - { - USBD_MSC_MaxLun = USBD_STORAGE_fops->GetMaxLun(); - if(USBD_MSC_MaxLun > 0) - { - USBD_CtlSendData (pdev, - &USBD_MSC_MaxLun, - 1); - } - else - { - USBD_CtlError(pdev , req); - return USBD_FAIL; - - } - } - else - { - USBD_CtlError(pdev , req); - return USBD_FAIL; - } - break; - - case BOT_RESET : - if((req->wValue == 0) && - (req->wLength == 0) && - ((req->bmRequest & 0x80) != 0x80)) - { - MSC_BOT_Reset(pdev); - } - else - { - USBD_CtlError(pdev , req); - return USBD_FAIL; - } - break; - - default: - USBD_CtlError(pdev , req); - return USBD_FAIL; - } - break; - /* Interface & Endpoint request */ - case USB_REQ_TYPE_STANDARD: - switch (req->bRequest) - { - case USB_REQ_GET_INTERFACE : - USBD_CtlSendData (pdev, - &USBD_MSC_AltSet, - 1); - break; - - case USB_REQ_SET_INTERFACE : - USBD_MSC_AltSet = (uint8_t)(req->wValue); - break; - - case USB_REQ_CLEAR_FEATURE: - - /* Flush the FIFO and Clear the stall status */ - DCD_EP_Flush(pdev, (uint8_t)req->wIndex); - - /* Re-activate the EP */ - DCD_EP_Close (pdev , (uint8_t)req->wIndex); - if((((uint8_t)req->wIndex) & 0x80) == 0x80) - { - DCD_EP_Open(pdev, - ((uint8_t)req->wIndex), - MSC_EPIN_SIZE, - USB_OTG_EP_BULK); - } - else - { - DCD_EP_Open(pdev, - ((uint8_t)req->wIndex), - MSC_EPOUT_SIZE, - USB_OTG_EP_BULK); - } - - /* Handle BOT error */ - MSC_BOT_CplClrFeature(pdev, (uint8_t)req->wIndex); - break; - - } - break; - - default: - break; - } - return USBD_OK; -} - -/** -* @brief USBD_MSC_DataIn -* handle data IN Stage -* @param pdev: device instance -* @param epnum: endpoint index -* @retval status -*/ -uint8_t USBD_MSC_DataIn (void *pdev, - uint8_t epnum) -{ - MSC_BOT_DataIn(pdev , epnum); - return USBD_OK; -} - -/** -* @brief USBD_MSC_DataOut -* handle data OUT Stage -* @param pdev: device instance -* @param epnum: endpoint index -* @retval status -*/ -uint8_t USBD_MSC_DataOut (void *pdev, - uint8_t epnum) -{ - MSC_BOT_DataOut(pdev , epnum); - return USBD_OK; -} - -/** -* @brief USBD_MSC_GetCfgDesc -* return configuration descriptor -* @param speed : current device speed -* @param length : pointer data length -* @retval pointer to descriptor buffer -*/ -uint8_t *USBD_MSC_GetCfgDesc (uint8_t speed, uint16_t *length) -{ - *length = sizeof (USBD_MSC_CfgDesc); - return USBD_MSC_CfgDesc; -} - -/** -* @brief USBD_MSC_GetOtherCfgDesc -* return other speed configuration descriptor -* @param speed : current device speed -* @param length : pointer data length -* @retval pointer to descriptor buffer -*/ -#ifdef USB_OTG_HS_CORE -uint8_t *USBD_MSC_GetOtherCfgDesc (uint8_t speed, - uint16_t *length) -{ - *length = sizeof (USBD_MSC_OtherCfgDesc); - return USBD_MSC_OtherCfgDesc; -} -#endif -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/usb/usbd_msc_data.c b/radio/bootloader/usb/usbd_msc_data.c deleted file mode 100644 index d65f05818..000000000 --- a/radio/bootloader/usb/usbd_msc_data.c +++ /dev/null @@ -1,134 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_msc_data.c - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief This file provides all the vital inquiry pages and sense data. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_msc_data.h" - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup MSC_DATA - * @brief Mass storage info/data module - * @{ - */ - -/** @defgroup MSC_DATA_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_DATA_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_DATA_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_DATA_Private_Variables - * @{ - */ - - -/* USB Mass storage Page 0 Inquiry Data */ -const uint8_t MSC_Page00_Inquiry_Data[] = {//7 - 0x00, - 0x00, - 0x00, - (LENGTH_INQUIRY_PAGE00 - 4), - 0x00, - 0x80, - 0x83 -}; -/* USB Mass storage sense 6 Data */ -const uint8_t MSC_Mode_Sense6_data[] = { - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00 -}; -/* USB Mass storage sense 10 Data */ -const uint8_t MSC_Mode_Sense10_data[] = { - 0x00, - 0x06, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00 -}; -/** - * @} - */ - - -/** @defgroup MSC_DATA_Private_FunctionPrototypes - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_DATA_Private_Functions - * @{ - */ - -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/usb/usbd_msc_scsi.c b/radio/bootloader/usb/usbd_msc_scsi.c deleted file mode 100644 index 11efc4414..000000000 --- a/radio/bootloader/usb/usbd_msc_scsi.c +++ /dev/null @@ -1,734 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_msc_scsi.c - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief This file provides all the USBD SCSI layer functions. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_msc_bot.h" -#include "usbd_msc_scsi.h" -#include "usbd_msc_mem.h" -#include "usbd_msc_data.h" - - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup MSC_SCSI - * @brief Mass storage SCSI layer module - * @{ - */ - -/** @defgroup MSC_SCSI_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_SCSI_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup MSC_SCSI_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_SCSI_Private_Variables - * @{ - */ - -SCSI_Sense_TypeDef SCSI_Sense [SENSE_LIST_DEEPTH]; -uint8_t SCSI_Sense_Head; -uint8_t SCSI_Sense_Tail; - -uint32_t SCSI_blk_size; -uint32_t SCSI_blk_nbr; - -uint32_t SCSI_blk_addr; -uint32_t SCSI_blk_len; - -USB_OTG_CORE_HANDLE *cdev; -/** - * @} - */ - - -/** @defgroup MSC_SCSI_Private_FunctionPrototypes - * @{ - */ -static int8_t SCSI_TestUnitReady(uint8_t lun, uint8_t *params); -static int8_t SCSI_Inquiry(uint8_t lun, uint8_t *params); -static int8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t *params); -static int8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t *params); -static int8_t SCSI_RequestSense (uint8_t lun, uint8_t *params); -static int8_t SCSI_StartStopUnit(uint8_t lun, uint8_t *params); -static int8_t SCSI_ModeSense6 (uint8_t lun, uint8_t *params); -static int8_t SCSI_ModeSense10 (uint8_t lun, uint8_t *params); -static int8_t SCSI_Write10(uint8_t lun , uint8_t *params); -static int8_t SCSI_Read10(uint8_t lun , uint8_t *params); -static int8_t SCSI_Verify10(uint8_t lun, uint8_t *params); -static int8_t SCSI_CheckAddressRange (uint8_t lun , - uint32_t blk_offset , - uint16_t blk_nbr); -static int8_t SCSI_ProcessRead (uint8_t lun); - -static int8_t SCSI_ProcessWrite (uint8_t lun); -/** - * @} - */ - - -/** @defgroup MSC_SCSI_Private_Functions - * @{ - */ - - -/** -* @brief SCSI_ProcessCmd -* Process SCSI commands -* @param pdev: device instance -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -int8_t SCSI_ProcessCmd(USB_OTG_CORE_HANDLE *pdev, - uint8_t lun, - uint8_t *params) -{ - cdev = pdev; - - switch (params[0]) - { - case SCSI_TEST_UNIT_READY: - return SCSI_TestUnitReady(lun, params); - - case SCSI_REQUEST_SENSE: - return SCSI_RequestSense (lun, params); - case SCSI_INQUIRY: - return SCSI_Inquiry(lun, params); - - case SCSI_START_STOP_UNIT: - return SCSI_StartStopUnit(lun, params); - - case SCSI_ALLOW_MEDIUM_REMOVAL: - return SCSI_StartStopUnit(lun, params); - - case SCSI_MODE_SENSE6: - return SCSI_ModeSense6 (lun, params); - - case SCSI_MODE_SENSE10: - return SCSI_ModeSense10 (lun, params); - - case SCSI_READ_FORMAT_CAPACITIES: - return SCSI_ReadFormatCapacity(lun, params); - - case SCSI_READ_CAPACITY10: - return SCSI_ReadCapacity10(lun, params); - - case SCSI_READ10: - return SCSI_Read10(lun, params); - - case SCSI_WRITE10: - return SCSI_Write10(lun, params); - - case SCSI_VERIFY10: - return SCSI_Verify10(lun, params); - - default: - SCSI_SenseCode(lun, - ILLEGAL_REQUEST, - INVALID_CDB); - return -1; - } -} - - -/** -* @brief SCSI_TestUnitReady -* Process SCSI Test Unit Ready Command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_TestUnitReady(uint8_t lun, uint8_t *params) -{ - - /* case 9 : Hi > D0 */ - if (MSC_BOT_cbw.dDataLength != 0) - { - SCSI_SenseCode(MSC_BOT_cbw.bLUN, - ILLEGAL_REQUEST, - INVALID_CDB); - return -1; - } - - if(USBD_STORAGE_fops->IsReady(lun) !=0 ) - { - SCSI_SenseCode(lun, - NOT_READY, - MEDIUM_NOT_PRESENT); - return -1; - } - MSC_BOT_DataLen = 0; - return 0; -} - -/** -* @brief SCSI_Inquiry -* Process Inquiry command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_Inquiry(uint8_t lun, uint8_t *params) -{ - uint8_t* pPage; - uint16_t len; - - if (params[1] & 0x01)/*Evpd is set*/ - { - pPage = (uint8_t *)MSC_Page00_Inquiry_Data; - len = LENGTH_INQUIRY_PAGE00; - } - else - { - - pPage = (uint8_t *)&USBD_STORAGE_fops->pInquiry[lun * USBD_STD_INQUIRY_LENGTH]; - len = pPage[4] + 5; - - if (params[4] <= len) - { - len = params[4]; - } - } - MSC_BOT_DataLen = len; - - while (len) - { - len--; - MSC_BOT_Data[len] = pPage[len]; - } - return 0; -} - -/** -* @brief SCSI_ReadCapacity10 -* Process Read Capacity 10 command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t *params) -{ - - if(USBD_STORAGE_fops->GetCapacity(lun, &SCSI_blk_nbr, &SCSI_blk_size) != 0) - { - SCSI_SenseCode(lun, - NOT_READY, - MEDIUM_NOT_PRESENT); - return -1; - } - else - { - - MSC_BOT_Data[0] = (uint8_t)((SCSI_blk_nbr - 1) >> 24); - MSC_BOT_Data[1] = (uint8_t)((SCSI_blk_nbr - 1) >> 16); - MSC_BOT_Data[2] = (uint8_t)((SCSI_blk_nbr - 1) >> 8); - MSC_BOT_Data[3] = (uint8_t)(SCSI_blk_nbr - 1); - - MSC_BOT_Data[4] = (uint8_t)(SCSI_blk_size >> 24); - MSC_BOT_Data[5] = (uint8_t)(SCSI_blk_size >> 16); - MSC_BOT_Data[6] = (uint8_t)(SCSI_blk_size >> 8); - MSC_BOT_Data[7] = (uint8_t)(SCSI_blk_size); - - MSC_BOT_DataLen = 8; - return 0; - } -} -/** -* @brief SCSI_ReadFormatCapacity -* Process Read Format Capacity command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t *params) -{ - - uint32_t blk_size; - uint32_t blk_nbr; - uint16_t i; - - for(i=0 ; i < 12 ; i++) - { - MSC_BOT_Data[i] = 0; - } - - if(USBD_STORAGE_fops->GetCapacity(lun, &blk_nbr, &blk_size) != 0) - { - SCSI_SenseCode(lun, - NOT_READY, - MEDIUM_NOT_PRESENT); - return -1; - } - else - { - MSC_BOT_Data[3] = 0x08; - MSC_BOT_Data[4] = (uint8_t)((blk_nbr - 1) >> 24); - MSC_BOT_Data[5] = (uint8_t)((blk_nbr - 1) >> 16); - MSC_BOT_Data[6] = (uint8_t)((blk_nbr - 1) >> 8); - MSC_BOT_Data[7] = (uint8_t)(blk_nbr - 1); - - MSC_BOT_Data[8] = 0x02; - MSC_BOT_Data[9] = (uint8_t)(blk_size >> 16); - MSC_BOT_Data[10] = (uint8_t)(blk_size >> 8); - MSC_BOT_Data[11] = (uint8_t)(blk_size); - - MSC_BOT_DataLen = 12; - return 0; - } -} -/** -* @brief SCSI_ModeSense6 -* Process Mode Sense6 command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_ModeSense6 (uint8_t lun, uint8_t *params) -{ - - uint16_t len = 8 ; - MSC_BOT_DataLen = len; - - while (len) - { - len--; - MSC_BOT_Data[len] = MSC_Mode_Sense6_data[len]; - } - return 0; -} - -/** -* @brief SCSI_ModeSense10 -* Process Mode Sense10 command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_ModeSense10 (uint8_t lun, uint8_t *params) -{ - uint16_t len = 8; - - MSC_BOT_DataLen = len; - - while (len) - { - len--; - MSC_BOT_Data[len] = MSC_Mode_Sense10_data[len]; - } - return 0; -} - -/** -* @brief SCSI_RequestSense -* Process Request Sense command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ - -static int8_t SCSI_RequestSense (uint8_t lun, uint8_t *params) -{ - uint8_t i; - - for(i=0 ; i < REQUEST_SENSE_DATA_LEN ; i++) - { - MSC_BOT_Data[i] = 0; - } - - MSC_BOT_Data[0] = 0x70; - MSC_BOT_Data[7] = REQUEST_SENSE_DATA_LEN - 6; - - if((SCSI_Sense_Head != SCSI_Sense_Tail)) { - - MSC_BOT_Data[2] = SCSI_Sense[SCSI_Sense_Head].Skey; - MSC_BOT_Data[12] = SCSI_Sense[SCSI_Sense_Head].w.b.ASCQ; - MSC_BOT_Data[13] = SCSI_Sense[SCSI_Sense_Head].w.b.ASC; - SCSI_Sense_Head++; - - if (SCSI_Sense_Head == SENSE_LIST_DEEPTH) - { - SCSI_Sense_Head = 0; - } - } - MSC_BOT_DataLen = REQUEST_SENSE_DATA_LEN; - - if (params[4] <= REQUEST_SENSE_DATA_LEN) - { - MSC_BOT_DataLen = params[4]; - } - return 0; -} - -/** -* @brief SCSI_SenseCode -* Load the last error code in the error list -* @param lun: Logical unit number -* @param sKey: Sense Key -* @param ASC: Additional Sense Key -* @retval none - -*/ -void SCSI_SenseCode(uint8_t lun, uint8_t sKey, uint8_t ASC) -{ - SCSI_Sense[SCSI_Sense_Tail].Skey = sKey; - SCSI_Sense[SCSI_Sense_Tail].w.ASC = ASC << 8; - SCSI_Sense_Tail++; - if (SCSI_Sense_Tail == SENSE_LIST_DEEPTH) - { - SCSI_Sense_Tail = 0; - } -} -/** -* @brief SCSI_StartStopUnit -* Process Start Stop Unit command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_StartStopUnit(uint8_t lun, uint8_t *params) -{ - MSC_BOT_DataLen = 0; - return 0; -} - -/** -* @brief SCSI_Read10 -* Process Read10 command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_Read10(uint8_t lun , uint8_t *params) -{ - if(MSC_BOT_State == BOT_IDLE) /* Idle */ - { - - /* case 10 : Ho <> Di */ - - if ((MSC_BOT_cbw.bmFlags & 0x80) != 0x80) - { - SCSI_SenseCode(MSC_BOT_cbw.bLUN, - ILLEGAL_REQUEST, - INVALID_CDB); - return -1; - } - - if(USBD_STORAGE_fops->IsReady(lun) !=0 ) - { - SCSI_SenseCode(lun, - NOT_READY, - MEDIUM_NOT_PRESENT); - return -1; - } - - SCSI_blk_addr = (params[2] << 24) | \ - (params[3] << 16) | \ - (params[4] << 8) | \ - params[5]; - - SCSI_blk_len = (params[7] << 8) | \ - params[8]; - - - - if( SCSI_CheckAddressRange(lun, SCSI_blk_addr, SCSI_blk_len) < 0) - { - return -1; /* error */ - } - - MSC_BOT_State = BOT_DATA_IN; - SCSI_blk_addr *= SCSI_blk_size; - SCSI_blk_len *= SCSI_blk_size; - - /* cases 4,5 : Hi <> Dn */ - if (MSC_BOT_cbw.dDataLength != SCSI_blk_len) - { - SCSI_SenseCode(MSC_BOT_cbw.bLUN, - ILLEGAL_REQUEST, - INVALID_CDB); - return -1; - } - } - MSC_BOT_DataLen = MSC_MEDIA_PACKET; - - return SCSI_ProcessRead(lun); -} - -/** -* @brief SCSI_Write10 -* Process Write10 command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ - -static int8_t SCSI_Write10 (uint8_t lun , uint8_t *params) -{ - if (MSC_BOT_State == BOT_IDLE) /* Idle */ - { - - /* case 8 : Hi <> Do */ - - if ((MSC_BOT_cbw.bmFlags & 0x80) == 0x80) - { - SCSI_SenseCode(MSC_BOT_cbw.bLUN, - ILLEGAL_REQUEST, - INVALID_CDB); - return -1; - } - - /* Check whether Media is ready */ - if(USBD_STORAGE_fops->IsReady(lun) !=0 ) - { - SCSI_SenseCode(lun, - NOT_READY, - MEDIUM_NOT_PRESENT); - return -1; - } - - /* Check If media is write-protected */ - if(USBD_STORAGE_fops->IsWriteProtected(lun) !=0 ) - { - SCSI_SenseCode(lun, - NOT_READY, - WRITE_PROTECTED); - return -1; - } - - - SCSI_blk_addr = (params[2] << 24) | \ - (params[3] << 16) | \ - (params[4] << 8) | \ - params[5]; - SCSI_blk_len = (params[7] << 8) | \ - params[8]; - - /* check if LBA address is in the right range */ - if(SCSI_CheckAddressRange(lun, SCSI_blk_addr, SCSI_blk_len) < 0) - { - return -1; /* error */ - } - - SCSI_blk_addr *= SCSI_blk_size; - SCSI_blk_len *= SCSI_blk_size; - - /* cases 3,11,13 : Hn,Ho <> D0 */ - if (MSC_BOT_cbw.dDataLength != SCSI_blk_len) - { - SCSI_SenseCode(MSC_BOT_cbw.bLUN, - ILLEGAL_REQUEST, - INVALID_CDB); - return -1; - } - - /* Prepare EP to receive first data packet */ - MSC_BOT_State = BOT_DATA_OUT; - DCD_EP_PrepareRx (cdev, - MSC_OUT_EP, - MSC_BOT_Data, - MIN (SCSI_blk_len, MSC_MEDIA_PACKET)); - } - else /* Write Process ongoing */ - { - return SCSI_ProcessWrite(lun); - } - return 0; -} - - -/** -* @brief SCSI_Verify10 -* Process Verify10 command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ - -static int8_t SCSI_Verify10(uint8_t lun , uint8_t *params){ - if ((params[1]& 0x02) == 0x02) - { - SCSI_SenseCode (lun, ILLEGAL_REQUEST, INVALID_FIELED_IN_COMMAND); - return -1; /* Error, Verify Mode Not supported*/ - } - - if(SCSI_CheckAddressRange(lun, SCSI_blk_addr, SCSI_blk_len) < 0) - { - return -1; /* error */ - } - MSC_BOT_DataLen = 0; - return 0; -} - -/** -* @brief SCSI_CheckAddressRange -* Check address range -* @param lun: Logical unit number -* @param blk_offset: first block address -* @param blk_nbr: number of block to be processed -* @retval status -*/ -static int8_t SCSI_CheckAddressRange (uint8_t lun , uint32_t blk_offset , uint16_t blk_nbr) -{ - if (USBD_STORAGE_fops->GetCapacity(lun, &SCSI_blk_nbr, &SCSI_blk_size) != 0) - { - SCSI_SenseCode(lun, NOT_READY, MEDIUM_NOT_PRESENT); - return -1; - } - - if ((blk_offset + blk_nbr) > SCSI_blk_nbr ) - { - SCSI_SenseCode(lun, ILLEGAL_REQUEST, ADDRESS_OUT_OF_RANGE); - return -1; - } - - return 0; -} - -/** -* @brief SCSI_ProcessRead -* Handle Read Process -* @param lun: Logical unit number -* @retval status -*/ -static int8_t SCSI_ProcessRead (uint8_t lun) -{ - uint32_t len; - - len = MIN(SCSI_blk_len , MSC_MEDIA_PACKET); - - if( USBD_STORAGE_fops->Read(lun , - MSC_BOT_Data, - SCSI_blk_addr / SCSI_blk_size, - len / SCSI_blk_size) < 0) - { - - SCSI_SenseCode(lun, HARDWARE_ERROR, UNRECOVERED_READ_ERROR); - return -1; - } - - - DCD_EP_Tx (cdev, - MSC_IN_EP, - MSC_BOT_Data, - len); - - - SCSI_blk_addr += len; - SCSI_blk_len -= len; - - /* case 6 : Hi = Di */ - MSC_BOT_csw.dDataResidue -= len; - - if (SCSI_blk_len == 0) - { - MSC_BOT_State = BOT_LAST_DATA_IN; - } - return 0; -} - -/** -* @brief SCSI_ProcessWrite -* Handle Write Process -* @param lun: Logical unit number -* @retval status -*/ - -static int8_t SCSI_ProcessWrite (uint8_t lun) -{ - uint32_t len; - - len = MIN(SCSI_blk_len , MSC_MEDIA_PACKET); - - if(USBD_STORAGE_fops->Write(lun , - MSC_BOT_Data, - SCSI_blk_addr / SCSI_blk_size, - len / SCSI_blk_size) < 0) - { - SCSI_SenseCode(lun, HARDWARE_ERROR, WRITE_FAULT); - return -1; - } - - - SCSI_blk_addr += len; - SCSI_blk_len -= len; - - /* case 12 : Ho = Do */ - MSC_BOT_csw.dDataResidue -= len; - - if (SCSI_blk_len == 0) - { - MSC_BOT_SendCSW (cdev, CSW_CMD_PASSED); - } - else - { - /* Prapare EP to Receive next packet */ - DCD_EP_PrepareRx (cdev, - MSC_OUT_EP, - MSC_BOT_Data, - MIN (SCSI_blk_len, MSC_MEDIA_PACKET)); - } - - return 0; -} -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/usb/usbd_req.c b/radio/bootloader/usb/usbd_req.c deleted file mode 100644 index 63c1167d9..000000000 --- a/radio/bootloader/usb/usbd_req.c +++ /dev/null @@ -1,868 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_req.c - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief This file provides the standard USB requests following chapter 9. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_req.h" -#include "usbd_ioreq.h" -#include "usbd_desc.h" - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup USBD_REQ - * @brief USB standard requests module - * @{ - */ - -/** @defgroup USBD_REQ_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_REQ_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_REQ_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_REQ_Private_Variables - * @{ - */ -extern __IO USB_OTG_DCTL_TypeDef SET_TEST_MODE; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint32_t USBD_ep_status __ALIGN_END = 0; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint32_t USBD_default_cfg __ALIGN_END = 0; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint32_t USBD_cfg_status __ALIGN_END = 0; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint8_t USBD_StrDesc[USB_MAX_STR_DESC_SIZ] __ALIGN_END ; -/** - * @} - */ - - -/** @defgroup USBD_REQ_Private_FunctionPrototypes - * @{ - */ -static void USBD_GetDescriptor(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -static void USBD_SetAddress(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -static void USBD_SetConfig(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -static void USBD_GetConfig(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -static void USBD_GetStatus(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -static void USBD_SetFeature(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -static void USBD_ClrFeature(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -static uint8_t USBD_GetLen(uint8_t *buf); -/** - * @} - */ - - -/** @defgroup USBD_REQ_Private_Functions - * @{ - */ - - -/** -* @brief USBD_StdDevReq -* Handle standard usb device requests -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -USBD_Status USBD_StdDevReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req) -{ - USBD_Status ret = USBD_OK; - - switch (req->bRequest) - { - case USB_REQ_GET_DESCRIPTOR: - - USBD_GetDescriptor (pdev, req) ; - break; - - case USB_REQ_SET_ADDRESS: - USBD_SetAddress(pdev, req); - break; - - case USB_REQ_SET_CONFIGURATION: - USBD_SetConfig (pdev , req); - break; - - case USB_REQ_GET_CONFIGURATION: - USBD_GetConfig (pdev , req); - break; - - case USB_REQ_GET_STATUS: - USBD_GetStatus (pdev , req); - break; - - - case USB_REQ_SET_FEATURE: - USBD_SetFeature (pdev , req); - break; - - case USB_REQ_CLEAR_FEATURE: - USBD_ClrFeature (pdev , req); - break; - - default: - USBD_CtlError(pdev , req); - break; - } - - return ret; -} - -/** -* @brief USBD_StdItfReq -* Handle standard usb interface requests -* @param pdev: USB OTG device instance -* @param req: usb request -* @retval status -*/ -USBD_Status USBD_StdItfReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req) -{ - USBD_Status ret = USBD_OK; - - switch (pdev->dev.device_status) - { - case USB_OTG_CONFIGURED: - - if (LOBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) - { - pdev->dev.class_cb->Setup (pdev, req); - - if((req->wLength == 0)&& (ret == USBD_OK)) - { - USBD_CtlSendStatus(pdev); - } - } - else - { - USBD_CtlError(pdev , req); - } - break; - - default: - USBD_CtlError(pdev , req); - break; - } - return ret; -} - -/** -* @brief USBD_StdEPReq -* Handle standard usb endpoint requests -* @param pdev: USB OTG device instance -* @param req: usb request -* @retval status -*/ -USBD_Status USBD_StdEPReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req) -{ - - uint8_t ep_addr; - USBD_Status ret = USBD_OK; - - ep_addr = LOBYTE(req->wIndex); - - switch (req->bRequest) - { - - case USB_REQ_SET_FEATURE : - - switch (pdev->dev.device_status) - { - case USB_OTG_ADDRESSED: - if ((ep_addr != 0x00) && (ep_addr != 0x80)) - { - DCD_EP_Stall(pdev , ep_addr); - } - break; - - case USB_OTG_CONFIGURED: - if (req->wValue == USB_FEATURE_EP_HALT) - { - if ((ep_addr != 0x00) && (ep_addr != 0x80)) - { - DCD_EP_Stall(pdev , ep_addr); - - } - } - pdev->dev.class_cb->Setup (pdev, req); - USBD_CtlSendStatus(pdev); - - break; - - default: - USBD_CtlError(pdev , req); - break; - } - break; - - case USB_REQ_CLEAR_FEATURE : - - switch (pdev->dev.device_status) - { - case USB_OTG_ADDRESSED: - if ((ep_addr != 0x00) && (ep_addr != 0x80)) - { - DCD_EP_Stall(pdev , ep_addr); - } - break; - - case USB_OTG_CONFIGURED: - if (req->wValue == USB_FEATURE_EP_HALT) - { - if ((ep_addr != 0x00) && (ep_addr != 0x80)) - { - DCD_EP_ClrStall(pdev , ep_addr); - pdev->dev.class_cb->Setup (pdev, req); - } - USBD_CtlSendStatus(pdev); - } - break; - - default: - USBD_CtlError(pdev , req); - break; - } - break; - - case USB_REQ_GET_STATUS: - switch (pdev->dev.device_status) - { - case USB_OTG_ADDRESSED: - if ((ep_addr != 0x00) && (ep_addr != 0x80)) - { - DCD_EP_Stall(pdev , ep_addr); - } - break; - - case USB_OTG_CONFIGURED: - - - if ((ep_addr & 0x80)== 0x80) - { - if(pdev->dev.in_ep[ep_addr & 0x7F].is_stall) - { - USBD_ep_status = 0x0001; - } - else - { - USBD_ep_status = 0x0000; - } - } - else if ((ep_addr & 0x80)== 0x00) - { - if(pdev->dev.out_ep[ep_addr].is_stall) - { - USBD_ep_status = 0x0001; - } - - else - { - USBD_ep_status = 0x0000; - } - } - USBD_CtlSendData (pdev, - (uint8_t *)&USBD_ep_status, - 2); - break; - - default: - USBD_CtlError(pdev , req); - break; - } - break; - - default: - break; - } - return ret; -} -/** -* @brief USBD_GetDescriptor -* Handle Get Descriptor requests -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_GetDescriptor(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - uint16_t len; - uint8_t *pbuf; - - - switch (req->wValue >> 8) - { - case USB_DESC_TYPE_DEVICE: - pbuf = pdev->dev.usr_device->GetDeviceDescriptor(pdev->cfg.speed, &len); - if ((req->wLength == 64) ||( pdev->dev.device_status == USB_OTG_DEFAULT)) - { - len = 8; - } - break; - - case USB_DESC_TYPE_CONFIGURATION: - pbuf = (uint8_t *)pdev->dev.class_cb->GetConfigDescriptor(pdev->cfg.speed, &len); -#ifdef USB_OTG_HS_CORE - if((pdev->cfg.speed == USB_OTG_SPEED_FULL )&& - (pdev->cfg.phy_itface == USB_OTG_ULPI_PHY)) - { - pbuf = (uint8_t *)pdev->dev.class_cb->GetOtherConfigDescriptor(pdev->cfg.speed, &len); - } -#endif - pbuf[1] = USB_DESC_TYPE_CONFIGURATION; - pdev->dev.pConfig_descriptor = pbuf; - break; - - case USB_DESC_TYPE_STRING: - switch ((uint8_t)(req->wValue)) - { - case USBD_IDX_LANGID_STR: - pbuf = pdev->dev.usr_device->GetLangIDStrDescriptor(pdev->cfg.speed, &len); - break; - - case USBD_IDX_MFC_STR: - pbuf = pdev->dev.usr_device->GetManufacturerStrDescriptor(pdev->cfg.speed, &len); - break; - - case USBD_IDX_PRODUCT_STR: - pbuf = pdev->dev.usr_device->GetProductStrDescriptor(pdev->cfg.speed, &len); - break; - - case USBD_IDX_SERIAL_STR: - pbuf = pdev->dev.usr_device->GetSerialStrDescriptor(pdev->cfg.speed, &len); - break; - - case USBD_IDX_CONFIG_STR: - pbuf = pdev->dev.usr_device->GetConfigurationStrDescriptor(pdev->cfg.speed, &len); - break; - - case USBD_IDX_INTERFACE_STR: - pbuf = pdev->dev.usr_device->GetInterfaceStrDescriptor(pdev->cfg.speed, &len); - break; - - default: -#ifdef USB_SUPPORT_USER_STRING_DESC - pbuf = pdev->dev.class_cb->GetUsrStrDescriptor(pdev->cfg.speed, (req->wValue) , &len); - break; -#else - USBD_CtlError(pdev , req); - return; -#endif /* USBD_CtlError(pdev , req); */ - } - break; - case USB_DESC_TYPE_DEVICE_QUALIFIER: -#ifdef USB_OTG_HS_CORE - if(pdev->cfg.speed == USB_OTG_SPEED_HIGH ) - { - - pbuf = (uint8_t *)pdev->dev.class_cb->GetConfigDescriptor(pdev->cfg.speed, &len); - - USBD_DeviceQualifierDesc[4]= pbuf[14]; - USBD_DeviceQualifierDesc[5]= pbuf[15]; - USBD_DeviceQualifierDesc[6]= pbuf[16]; - - pbuf = USBD_DeviceQualifierDesc; - len = USB_LEN_DEV_QUALIFIER_DESC; - break; - } - else - { - USBD_CtlError(pdev , req); - return; - } -#else - USBD_CtlError(pdev , req); - return; -#endif - - case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: -#ifdef USB_OTG_HS_CORE - - if(pdev->cfg.speed == USB_OTG_SPEED_HIGH ) - { - pbuf = (uint8_t *)pdev->dev.class_cb->GetOtherConfigDescriptor(pdev->cfg.speed, &len); - pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; - break; - } - else - { - USBD_CtlError(pdev , req); - return; - } -#else - USBD_CtlError(pdev , req); - return; -#endif - - - default: - USBD_CtlError(pdev , req); - return; - } - - if((len != 0)&& (req->wLength != 0)) - { - - len = MIN(len , req->wLength); - - USBD_CtlSendData (pdev, - pbuf, - len); - } - -} - -/** -* @brief USBD_SetAddress -* Set device address -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_SetAddress(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - uint8_t dev_addr; - - if ((req->wIndex == 0) && (req->wLength == 0)) - { - dev_addr = (uint8_t)(req->wValue) & 0x7F; - - if (pdev->dev.device_status == USB_OTG_CONFIGURED) - { - USBD_CtlError(pdev , req); - } - else - { - pdev->dev.device_address = dev_addr; - DCD_EP_SetAddress(pdev, dev_addr); - USBD_CtlSendStatus(pdev); - - if (dev_addr != 0) - { - pdev->dev.device_status = USB_OTG_ADDRESSED; - } - else - { - pdev->dev.device_status = USB_OTG_DEFAULT; - } - } - } - else - { - USBD_CtlError(pdev , req); - } -} - -/** -* @brief USBD_SetConfig -* Handle Set device configuration request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_SetConfig(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - - static uint8_t cfgidx; - - cfgidx = (uint8_t)(req->wValue); - - if (cfgidx > USBD_CFG_MAX_NUM ) - { - USBD_CtlError(pdev , req); - } - else - { - switch (pdev->dev.device_status) - { - case USB_OTG_ADDRESSED: - if (cfgidx) - { - pdev->dev.device_config = cfgidx; - pdev->dev.device_status = USB_OTG_CONFIGURED; - USBD_SetCfg(pdev , cfgidx); - USBD_CtlSendStatus(pdev); - } - else - { - USBD_CtlSendStatus(pdev); - } - break; - - case USB_OTG_CONFIGURED: - if (cfgidx == 0) - { - pdev->dev.device_status = USB_OTG_ADDRESSED; - pdev->dev.device_config = cfgidx; - USBD_ClrCfg(pdev , cfgidx); - USBD_CtlSendStatus(pdev); - - } - else if (cfgidx != pdev->dev.device_config) - { - /* Clear old configuration */ - USBD_ClrCfg(pdev , pdev->dev.device_config); - - /* set new configuration */ - pdev->dev.device_config = cfgidx; - USBD_SetCfg(pdev , cfgidx); - USBD_CtlSendStatus(pdev); - } - else - { - USBD_CtlSendStatus(pdev); - } - break; - - default: - USBD_CtlError(pdev , req); - break; - } - } -} - -/** -* @brief USBD_GetConfig -* Handle Get device configuration request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_GetConfig(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - - if (req->wLength != 1) - { - USBD_CtlError(pdev , req); - } - else - { - switch (pdev->dev.device_status ) - { - case USB_OTG_ADDRESSED: - - USBD_CtlSendData (pdev, - (uint8_t *)&USBD_default_cfg, - 1); - break; - - case USB_OTG_CONFIGURED: - - USBD_CtlSendData (pdev, - &pdev->dev.device_config, - 1); - break; - - default: - USBD_CtlError(pdev , req); - break; - } - } -} - -/** -* @brief USBD_GetStatus -* Handle Get Status request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_GetStatus(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - - - switch (pdev->dev.device_status) - { - case USB_OTG_ADDRESSED: - case USB_OTG_CONFIGURED: - -#ifdef USBD_SELF_POWERED - USBD_cfg_status = USB_CONFIG_SELF_POWERED; -#else - USBD_cfg_status = 0x00; -#endif - - if (pdev->dev.DevRemoteWakeup) - { - USBD_cfg_status |= USB_CONFIG_REMOTE_WAKEUP; - } - - USBD_CtlSendData (pdev, - (uint8_t *)&USBD_cfg_status, - 2); - break; - - default : - USBD_CtlError(pdev , req); - break; - } -} - - -/** -* @brief USBD_SetFeature -* Handle Set device feature request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_SetFeature(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - - USB_OTG_DCTL_TypeDef dctl; - uint8_t test_mode = 0; - - if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) - { - pdev->dev.DevRemoteWakeup = 1; - pdev->dev.class_cb->Setup (pdev, req); - USBD_CtlSendStatus(pdev); - } - - else if ((req->wValue == USB_FEATURE_TEST_MODE) && - ((req->wIndex & 0xFF) == 0)) - { - dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL); - - test_mode = req->wIndex >> 8; - switch (test_mode) - { - case 1: // TEST_J - dctl.b.tstctl = 1; - break; - - case 2: // TEST_K - dctl.b.tstctl = 2; - break; - - case 3: // TEST_SE0_NAK - dctl.b.tstctl = 3; - break; - - case 4: // TEST_PACKET - dctl.b.tstctl = 4; - break; - - case 5: // TEST_FORCE_ENABLE - dctl.b.tstctl = 5; - break; - } - SET_TEST_MODE = dctl; - pdev->dev.test_mode = 1; - USBD_CtlSendStatus(pdev); - } - -} - - -/** -* @brief USBD_ClrFeature -* Handle clear device feature request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_ClrFeature(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - switch (pdev->dev.device_status) - { - case USB_OTG_ADDRESSED: - case USB_OTG_CONFIGURED: - if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) - { - pdev->dev.DevRemoteWakeup = 0; - pdev->dev.class_cb->Setup (pdev, req); - USBD_CtlSendStatus(pdev); - } - break; - - default : - USBD_CtlError(pdev , req); - break; - } -} - -/** -* @brief USBD_ParseSetupRequest -* Copy buffer into setup structure -* @param pdev: device instance -* @param req: usb request -* @retval None -*/ - -void USBD_ParseSetupRequest( USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - req->bmRequest = *(uint8_t *) (pdev->dev.setup_packet); - req->bRequest = *(uint8_t *) (pdev->dev.setup_packet + 1); - req->wValue = SWAPBYTE (pdev->dev.setup_packet + 2); - req->wIndex = SWAPBYTE (pdev->dev.setup_packet + 4); - req->wLength = SWAPBYTE (pdev->dev.setup_packet + 6); - - pdev->dev.in_ep[0].ctl_data_len = req->wLength ; - pdev->dev.device_state = USB_OTG_EP0_SETUP; -} - -/** -* @brief USBD_CtlError -* Handle USB low level Error -* @param pdev: device instance -* @param req: usb request -* @retval None -*/ - -void USBD_CtlError( USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - - DCD_EP_Stall(pdev , 0x80); - DCD_EP_Stall(pdev , 0); - USB_OTG_EP0_OutStart(pdev); -} - - -/** - * @brief USBD_GetString - * Convert Ascii string into unicode one - * @param desc : descriptor buffer - * @param unicode : Formatted string buffer (unicode) - * @param len : descriptor length - * @retval None - */ -void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) -{ - uint8_t idx = 0; - - if (desc != NULL) - { - *len = USBD_GetLen(desc) * 2 + 2; - unicode[idx++] = *len; - unicode[idx++] = USB_DESC_TYPE_STRING; - - while (*desc != NULL) - { - unicode[idx++] = *desc++; - unicode[idx++] = 0x00; - } - } -} - -/** - * @brief USBD_GetLen - * return the string length - * @param buf : pointer to the ascii string buffer - * @retval string length - */ -static uint8_t USBD_GetLen(uint8_t *buf) -{ - uint8_t len = 0; - - while (*buf != NULL) - { - len++; - buf++; - } - - return len; -} -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ From 74354164227d5cd57b078e8a84d47e6c5d35ca54 Mon Sep 17 00:00:00 2001 From: bsongis Date: Mon, 3 Mar 2014 19:15:00 +0100 Subject: [PATCH 009/285] More cleaning in bootloader --- radio/bootloader/Makefile | 4 +- radio/bootloader/aspi.cpp | 136 ------------------------- radio/bootloader/usbd_usr.cpp | 126 ----------------------- radio/src/Makefile | 2 +- radio/src/opentx.h | 4 +- radio/src/targets/taranis/aspi.cpp | 2 +- radio/src/targets/taranis/usbd_usr.cpp | 4 +- 7 files changed, 10 insertions(+), 268 deletions(-) delete mode 100644 radio/bootloader/aspi.cpp delete mode 100644 radio/bootloader/usbd_usr.cpp diff --git a/radio/bootloader/Makefile b/radio/bootloader/Makefile index 9e61997ab..3b87b4ff5 100644 --- a/radio/bootloader/Makefile +++ b/radio/bootloader/Makefile @@ -142,13 +142,13 @@ SRC = system_stm32f2xx.c \ ../src/targets/taranis/usbd_desc.c \ ../src/targets/taranis/usb_bsp.c -CPPSRC = aspi.cpp \ +CPPSRC = ../src/targets/taranis/aspi.cpp \ lcd_driver.cpp \ driversboot.cpp \ logicioboot.cpp \ ff.cpp \ x9ddiskio.cpp \ - usbd_usr.cpp \ + ../src/targets/taranis/usbd_usr.cpp \ usbd_storage_msd.cpp \ i2c_ee.cpp \ lcdboot.cpp \ diff --git a/radio/bootloader/aspi.cpp b/radio/bootloader/aspi.cpp deleted file mode 100644 index 8de383af0..000000000 --- a/radio/bootloader/aspi.cpp +++ /dev/null @@ -1,136 +0,0 @@ -/** - ****************************************************************************** - * @file Project/spi/spi.c - * @author X9D Application Team - * @Hardware version V0.2 - * @date 11-July-2012 - * @brief This file provides spi Init(Analog spi),read and write. - driver for LCD. - * * - ****************************************************************************** -*/ - -#include "radio.h" -#include "stm32f2xx.h" -#include "stm32f2xx_gpio.h" -#include "stm32f2xx_rcc.h" -#include "hal.h" -#include "aspi.h" - -#define __no_operation __NOP - -/** -**********send command to lcd************** -*/ -//hardware spi -/*u16 spiCmd(u8 addr) -{ - u8 readValue; - - SPI_RS_LOW(); - SPI_NCS_LOW(); - - SPI_WRITE_BYTE(addr); - SPI_WAIT_DONE(); - - readValue=SPI_READ_BYTE(); - SPI_NCS_HIGH(); - return readValue; -}*/ - -//Anolog spi -void AspiCmd(uint8_t Command_Byte) -{ - int i=8; - LCD_A0_LOW(); - - LCD_CLK_HIGH(); - LCD_NCS_LOW(); - - while (i--) - { - LCD_CLK_LOW(); - if(Command_Byte&0x80) - { - LCD_MOSI_HIGH(); - } - else LCD_MOSI_LOW(); - - Command_Byte=Command_Byte<<1; - LCD_CLK_HIGH(); - } - LCD_NCS_HIGH(); - LCD_A0_HIGH(); -} - -/** - -********send data to lcd************** - -*/ - -//hardware spi -/* -u16 spiData(u8 addr) -{ - u16 readValue; - OLED_RS_HIGH(); - SPI_NCS_LOW(); - - SPI_WRITE_BYTE(addr); - SPI_WAIT_DONE(); - - readValue=SPI_READ_BYTE(); - SPI_NCS_HIGH(); - return readValue; -} -*/ - -//Anolog spi -void AspiData(uint8_t Para_data) -{ - int i=8; - LCD_CLK_HIGH(); - LCD_A0_HIGH(); - LCD_NCS_LOW(); - while (i--) - { - if(Para_data&0x80) - { - LCD_MOSI_HIGH(); - }else LCD_MOSI_LOW(); - Para_data<<=1; - LCD_CLK_LOW(); - __no_operation(); - LCD_CLK_HIGH(); - __no_operation(); - } - LCD_NCS_HIGH(); - LCD_A0_HIGH(); -} - -/*** -**********read one byte in a register******* -*/ - -/* -u16 spiRegAccess(u8 addrByte, u8 writeValue) -{ - u8 readValue; - - SPI_NCS_LOW(); - - SPI_WRITE_BYTE(addrByte); - SPI_WAIT_DONE(); - - SPI_WRITE_BYTE(writeValue); - SPI_WAIT_DONE(); - - readValue=SPI_READ_BYTE(); - SPI_NCS_HIGH(); - return readValue; -} - -*/ - - diff --git a/radio/bootloader/usbd_usr.cpp b/radio/bootloader/usbd_usr.cpp deleted file mode 100644 index dd78aba75..000000000 --- a/radio/bootloader/usbd_usr.cpp +++ /dev/null @@ -1,126 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_usr.c - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief This file includes the user application layer - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "radio.h" - -extern "C" { -#include "usbd_usr.h" - -/* Points to the DEVICE_PROP structure of current device */ -/* The purpose of this register is to speed up the execution */ - - -USBD_Usr_cb_TypeDef USR_cb = -{ - USBD_USR_Init, - USBD_USR_DeviceReset, - USBD_USR_DeviceConfigured, - USBD_USR_DeviceSuspended, - USBD_USR_DeviceResumed, - - USBD_USR_DeviceConnected, - USBD_USR_DeviceDisconnected, -}; -} - -/** -* @brief Whatever the user application needs to do when USB is initialised -* @param None -* @retval None -*/ -void USBD_USR_Init(void) -{ - -} - -/** -* @brief Displays the message on LCD on device reset event -* @param speed : device speed -* @retval None -*/ -void USBD_USR_DeviceReset (uint8_t speed) -{ - -} - - -/** -* @brief Displays the message on LCD on device config event -* @param None -* @retval Staus -*/ -void USBD_USR_DeviceConfigured (void) -{ - -} -/** -* @brief Displays the message on LCD on device suspend event -* @param None -* @retval None -*/ -void USBD_USR_DeviceSuspended(void) -{ - -} - - -/** -* @brief Displays the message on LCD on device resume event -* @param None -* @retval None -*/ -void USBD_USR_DeviceResumed(void) -{ - -} - -/** -* @brief USBD_USR_DeviceConnected -* Displays the message on LCD on device connection Event -* @param None -* @retval Staus -*/ -void USBD_USR_DeviceConnected (void) -{ - -} - - -/** -* @brief USBD_USR_DeviceDisonnected -* Displays the message on LCD on device disconnection Event -* @param None -* @retval Staus -*/ -void USBD_USR_DeviceDisconnected (void) -{ -// NVIC_SystemReset(); -} - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/Makefile b/radio/src/Makefile index 41c800531..eb132116e 100644 --- a/radio/src/Makefile +++ b/radio/src/Makefile @@ -708,8 +708,8 @@ ifeq ($(PCB), TARANIS) endif ifeq ($(BOOTLOADER), YES) - CPPDEFS += -DBOOTLOADER CPPSRC += loadboot.cpp + CPPDEFS += -DBOOTLOADER endif endif diff --git a/radio/src/opentx.h b/radio/src/opentx.h index 5c86d0dd3..9534ae9e1 100644 --- a/radio/src/opentx.h +++ b/radio/src/opentx.h @@ -1111,7 +1111,7 @@ template void swap(t & a, t & b) { t tmp = b; b = a; a = tmp; } uint16_t isqrt32(uint32_t n); #endif -#if defined(CPUARM) +#if defined(CPUARM) && !defined(BOOT) #if !defined(SIMU) extern "C" { #include @@ -1513,7 +1513,9 @@ enum AUDIO_SOUNDS { #include "targets/gruvin9x/somo14d.h" #endif +#if !defined(BOOT) #include "translations.h" +#endif #if defined(HAPTIC) #include "haptic.h" diff --git a/radio/src/targets/taranis/aspi.cpp b/radio/src/targets/taranis/aspi.cpp index b03d54a6d..5aa1487a6 100644 --- a/radio/src/targets/taranis/aspi.cpp +++ b/radio/src/targets/taranis/aspi.cpp @@ -10,7 +10,7 @@ ****************************************************************************** */ -#include "../opentx.h" +#include "../../opentx.h" #include "./STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_gpio.h" /** diff --git a/radio/src/targets/taranis/usbd_usr.cpp b/radio/src/targets/taranis/usbd_usr.cpp index 32fedc43c..26187ef41 100644 --- a/radio/src/targets/taranis/usbd_usr.cpp +++ b/radio/src/targets/taranis/usbd_usr.cpp @@ -26,7 +26,7 @@ */ /* Includes ------------------------------------------------------------------*/ -#include "../opentx.h" +#include "../../opentx.h" extern "C" { #include "usbd_usr.h" @@ -119,7 +119,9 @@ void USBD_USR_DeviceConnected (void) */ void USBD_USR_DeviceDisconnected (void) { +#if !defined(BOOT) NVIC_SystemReset(); +#endif } From 9bb64c07ae17e6c74d5a056b6a86aee54ba0ebe4 Mon Sep 17 00:00:00 2001 From: bsongis Date: Mon, 3 Mar 2014 22:57:46 +0100 Subject: [PATCH 010/285] Align french translations --- radio/src/translations/en.h.txt | 64 ++--- radio/src/translations/fr.h.txt | 432 ++++++++++++++++---------------- 2 files changed, 251 insertions(+), 245 deletions(-) diff --git a/radio/src/translations/en.h.txt b/radio/src/translations/en.h.txt index e99c62650..7f26756f8 100644 --- a/radio/src/translations/en.h.txt +++ b/radio/src/translations/en.h.txt @@ -168,7 +168,7 @@ #endif #if defined(CPUARM) - #define TR_CSWEQUAL "a=x\0 " + #define TR_CSWEQUAL "a=x\0 " #else #define TR_CSWEQUAL #endif @@ -333,7 +333,7 @@ #define TR_VSCREEN "Nums""Bars" #define LEN_GPSFORMAT "\004" -#define TR_GPSFORMAT "HMS NMEA" +#define TR_GPSFORMAT "HMS ""NMEA" #define LEN2_VTEMPLATES 13 #define LEN_VTEMPLATES "\015" @@ -474,17 +474,17 @@ #define TR_ELEDIRECTION TR("ELE Direction","Long. cyc. direction") #define TR_AILDIRECTION TR("AIL Direction","Lateral cyc. direction") #define TR_COLDIRECTION TR("PIT Direction","Coll. pitch direction") -#define TR_MODE INDENT"Mode" +#define TR_MODE INDENT "Mode" #define TR_NOFREEEXPO "No free expo!" #define TR_NOFREEMIXER "No free mixer!" #define TR_INSERTMIX "INSERT MIX " #define TR_EDITMIX "EDIT MIX " -#define TR_SOURCE INDENT"Source" +#define TR_SOURCE INDENT "Source" #define TR_WEIGHT "Weight" #define TR_EXPO TR("Expo","Exponential") #define TR_SIDE "Side" #define TR_DIFFERENTIAL "Differ" -#define TR_OFFSET INDENT"Offset" +#define TR_OFFSET INDENT "Offset" #define TR_TRIM "Trim" #define TR_DREX "DRex" #define TR_CURVE "Curve" @@ -500,33 +500,33 @@ #define TR_CV "CV" #define TR_GV "GV" #define TR_ACHANNEL "A\004channel" -#define TR_RANGE INDENT"Range" +#define TR_RANGE INDENT "Range" #define TR_BAR "Bar" -#define TR_ALARM INDENT"Alarm" +#define TR_ALARM INDENT "Alarm" #define TR_USRDATA "UsrData" -#define TR_BLADES INDENT"Blades" +#define TR_BLADES INDENT "Blades" #define TR_SCREEN "Screen " #define TR_SOUND_LABEL "Sound" -#define TR_LENGTH INDENT"Length" -#define TR_SPKRPITCH INDENT"Pitch" +#define TR_LENGTH INDENT "Length" +#define TR_SPKRPITCH INDENT "Pitch" #define TR_HAPTIC_LABEL "Haptic" -#define TR_HAPTICSTRENGTH INDENT"Strength" +#define TR_HAPTICSTRENGTH INDENT "Strength" #define TR_CONTRAST "Contrast" #define TR_ALARMS_LABEL "Alarms" #define TR_BATTERY_RANGE TR("Battery range","Battery meter range") -#define TR_BATTERYWARNING INDENT"Battery Low" -#define TR_INACTIVITYALARM INDENT"Inactivity" -#define TR_MEMORYWARNING INDENT"Memory Low" -#define TR_ALARMWARNING INDENT"Sound Off" +#define TR_BATTERYWARNING INDENT "Battery Low" +#define TR_INACTIVITYALARM INDENT "Inactivity" +#define TR_MEMORYWARNING INDENT "Memory Low" +#define TR_ALARMWARNING INDENT "Sound Off" #define TR_RENAVIG "RotEnc Navig" #define TR_THROTTLEREVERSE TR("T-Reverse", "Throttle reverse") -#define TR_MINUTEBEEP TR(INDENT"Minute",INDENT"Minute call") -#define TR_BEEPCOUNTDOWN INDENT"Countdown" -#define TR_PERSISTENT TR(INDENT"Persist.",INDENT"Persistent") +#define TR_MINUTEBEEP TR(INDENT "Minute",INDENT "Minute call") +#define TR_BEEPCOUNTDOWN INDENT "Countdown" +#define TR_PERSISTENT TR(INDENT "Persist.",INDENT "Persistent") #define TR_BACKLIGHT_LABEL "Backlight" -#define TR_BLDELAY INDENT"Duration" -#define TR_BLONBRIGHTNESS INDENT"ON Brightness" -#define TR_BLOFFBRIGHTNESS INDENT"OFF Brightness" +#define TR_BLDELAY INDENT "Duration" +#define TR_BLONBRIGHTNESS INDENT "ON Brightness" +#define TR_BLOFFBRIGHTNESS INDENT "OFF Brightness" #define TR_SPLASHSCREEN "Splash screen" #define TR_THROTTLEWARNING TR("T-Warning","Throttle Warning") #define TR_SWITCHWARNING TR("S-Warning","Switch Warning") @@ -610,9 +610,9 @@ #define TR_MENUTEMPLATES "TEMPLATES" #define TR_MENUSTAT "STATS" #define TR_MENUDEBUG "DEBUG" -#define TR_RXNUM TR("RxNum", INDENT"Receiver No.") +#define TR_RXNUM TR("RxNum", INDENT "Receiver No.") #define TR_SYNCMENU "[Sync]" -#define TR_LIMIT INDENT"Limit" +#define TR_LIMIT INDENT "Limit" #define TR_MINRSSI "Min Rssi" #define TR_LATITUDE "Latitude" #define TR_LONGITUDE "Longitude" @@ -621,8 +621,8 @@ #define TR_SHUTDOWN "SHUTTING DOWN" #define TR_BATT_CALIB "Battery Calib" #define TR_CURRENT_CALIB "Current Calib" -#define TR_VOLTAGE INDENT"Voltage" -#define TR_CURRENT INDENT"Current" +#define TR_VOLTAGE INDENT "Voltage" +#define TR_CURRENT INDENT "Current" #define TR_SELECT_MODEL "Select Model" #define TR_CREATE_MODEL "Create Model" #define TR_COPY_MODEL "Copy Model" @@ -710,8 +710,8 @@ #define TR_ABOUT_US "About" #define TR_AND_SWITCH "AND Switch" #define TR_CF "CF" -#define TR_SPEAKER INDENT"Speaker" -#define TR_BUZZER INDENT"Buzzer" +#define TR_SPEAKER INDENT "Speaker" +#define TR_BUZZER INDENT "Buzzer" #define TR_BYTES "bytes" #define TR_MODULE_BIND "[Bind]" #define TR_MODULE_RANGE "[Range]" @@ -807,11 +807,11 @@ #define TR_ABOUT_PARENTS_3 "ER9X (Erez Raviv)" #define TR_ABOUT_PARENTS_4 "TH9X (Thomas Husterer)" -#define TR_CHR_SHORT 's' -#define TR_CHR_LONG 'l' -#define TR_CHR_TOGGLE 't' -#define TR_CHR_HOUR 'h' -#define TR_CHR_INPUT 'I' // Values between A-I will work +#define TR_CHR_SHORT 's' +#define TR_CHR_LONG 'l' +#define TR_CHR_TOGGLE 't' +#define TR_CHR_HOUR 'h' +#define TR_CHR_INPUT 'I' // Values between A-I will work #define TR_BEEP_VOLUME "Beep Volume" #define TR_WAV_VOLUME "Wav Volume" diff --git a/radio/src/translations/fr.h.txt b/radio/src/translations/fr.h.txt index d1762df32..69880ef7c 100644 --- a/radio/src/translations/fr.h.txt +++ b/radio/src/translations/fr.h.txt @@ -1,10 +1,7 @@ /* * Authors (alphabetical order) + * - Andre Bernet * - Bertrand Songis - * - Bernet Andre - * - Kjell Kernen - * - Martin Hotar - * - Romolo Manfredini * * opentx is based on code named * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, @@ -39,90 +36,90 @@ * \001 to \035 -extended spacing (value * FW/2) * \0 -ends actual string */ - + // NON ZERO TERMINATED STRINGS -#define LEN_OFFON "\003" -#define TR_OFFON "OFF""ON\0" +#define LEN_OFFON "\003" +#define TR_OFFON "OFF""ON\0" -#define LEN_MMMINV "\003" -#define TR_MMMINV "---""INV" +#define LEN_MMMINV "\003" +#define TR_MMMINV "---""INV" -#define LEN_NCHANNELS "\004" -#define TR_NCHANNELS "\0014CH\0016CH\0018CH10CH12CH14CH16CH" +#define LEN_NCHANNELS "\004" +#define TR_NCHANNELS "\0014CH\0016CH\0018CH10CH12CH14CH16CH" -#define LEN_VBEEPMODE "\005" -#define TR_VBEEPMODE "Aucun""Alarm""NoKey""Tout\0" +#define LEN_VBEEPMODE "\005" +#define TR_VBEEPMODE "Aucun""Alarm""NoKey""Tout\0" -#define LEN_VBEEPLEN "\005" -#define TR_VBEEPLEN "0====""=0===""==0==""===0=""====0" +#define LEN_VBEEPLEN "\005" +#define TR_VBEEPLEN "0====""=0===""==0==""===0=""====0" -#define LEN_VRENAVIG "\003" -#define TR_VRENAVIG "NonREaREb" +#define LEN_VRENAVIG "\003" +#define TR_VRENAVIG "NonREaREb" -#define LEN_VBLMODE TR("\004","\011") -#define TR_VBLMODE TR("OFF\0""Btns""Ctrl""Tous""ON\0","OFF\0 ""Touches\0 ""Controles""Tous\0 ""ON\0 ") +#define LEN_VBLMODE TR("\004","\011") +#define TR_VBLMODE TR("OFF\0""Btns""Ctrl""Tous""ON\0","OFF\0 ""Touches\0 ""Controles""Tous\0 ""ON\0 ") -#define LEN_TRNMODE "\003" -#define TR_TRNMODE "OFF"" +="" :=" +#define LEN_TRNMODE "\003" +#define TR_TRNMODE "OFF"" +="" :=" -#define LEN_TRNCHN "\003" -#define TR_TRNCHN "CH1CH2CH3CH4" +#define LEN_TRNCHN "\003" +#define TR_TRNCHN "CH1CH2CH3CH4" -#define LEN_UART3MODES "\017" -#define TR_UART3MODES "OFF\0 ""Recopie S-Port\0""Debug\0 " +#define LEN_UART3MODES "\017" +#define TR_UART3MODES "OFF\0 ""Recopie S-Port\0""Debug\0 " -#define LEN_POTTYPES "\017" -#define TR_POTTYPES "Potentiomètre\0 ""Inter multi-pos" +#define LEN_POTTYPES "\017" +#define TR_POTTYPES "Rien\0 ""Potentiomètre\0 ""Inter multi-pos" -#define LEN_DATETIME "\005" -#define TR_DATETIME "DATE:""HEURE" +#define LEN_DATETIME "\005" +#define TR_DATETIME "DATE:""HEURE" -#define LEN_VLCD "\006" -#define TR_VLCD "NormalOptrex" +#define LEN_VLCD "\006" +#define TR_VLCD "NormalOptrex" -#define LEN_COUNTRYCODES TR("\002", "\006") -#define TR_COUNTRYCODES TR("US""JP""EU", "USA\0 ""Japon\0""Europe") +#define LEN_COUNTRYCODES TR("\002", "\006") +#define TR_COUNTRYCODES TR("US""JP""EU", "USA\0 ""Japon\0""Europe") -#define LEN_VTRIMINC TR("\006","\013") -#define TR_VTRIMINC TR("Expo\0 ""ExFin\0""Fin\0 ""Moyen\0""Gros\0 ","Exponentiel""Extra Fin\0 ""Fin\0 ""Moyen\0 ""Grossier\0 ") +#define LEN_VTRIMINC TR("\006","\013") +#define TR_VTRIMINC TR("Expo\0 ""ExFin\0""Fin\0 ""Moyen\0""Gros\0 ","Exponentiel""Extra Fin\0 ""Fin\0 ""Moyen\0 ""Grossier\0 ") #define LEN_VBEEPCOUNTDOWN "\006" #define TR_VBEEPCOUNTDOWN "SilentBeeps\0Voice\0" -#define LEN_RETA123 "\001" +#define LEN_RETA123 "\001" #if defined(PCBGRUVIN9X) #if ROTARY_ENCODERS > 2 - #define TR_RETA123 "DPGA123abcd" + #define TR_RETA123 "DPGA123abcd" #else - #define TR_RETA123 "DPGA123ab" + #define TR_RETA123 "DPGA123ab" #endif #elif defined(PCBTARANIS) - #define TR_RETA123 "DPGA12LR" -#else - #define TR_RETA123 "DPGA123" + #define TR_RETA123 "DPGA12LR" +#else + #define TR_RETA123 "DPGA123" #endif -#define LEN_VPROTOS "\006" +#define LEN_VPROTOS "\006" #if defined(PXX) - #define TR_PXX "PXX\0 " + #define TR_PXX "PXX\0 " #elif defined(DSM2) || defined(IRPROTOS) - #define TR_PXX "[PXX]\0" + #define TR_PXX "[PXX]\0" #else #define TR_PXX #endif #if defined(DSM2) - #define TR_DSM2 "LP45\0 ""DSM2\0 ""DSMX\0 " + #define TR_DSM2 "LP45\0 ""DSM2\0 ""DSMX\0 " #elif defined(IRPROTOS) - #define TR_DSM2 "[LP45]""[DSM2]""[DSMX]" + #define TR_DSM2 "[LP45]""[DSM2]""[DSMX]" #else #define TR_DSM2 #endif #if defined(IRPROTOS) - #define TR_IRPROTOS "SILV TRAC09PICZ SWIFT\0" + #define TR_IRPROTOS "SILV TRAC09PICZ SWIFT\0" #else #define TR_IRPROTOS #endif @@ -130,25 +127,25 @@ #if defined(CPUARM) #define TR_XPPM #else - #define TR_XPPM "PPM16\0""PPMsim" + #define TR_XPPM "PPM16\0""PPMsim" #endif -#define TR_VPROTOS "PPM\0 " TR_XPPM TR_PXX TR_DSM2 TR_IRPROTOS +#define TR_VPROTOS "PPM\0 " TR_XPPM TR_PXX TR_DSM2 TR_IRPROTOS -#define LEN_POSNEG "\003" -#define TR_POSNEG "POS""NEG" +#define LEN_POSNEG "\003" +#define TR_POSNEG "POS""NEG" -#define LEN_VCURVEFUNC "\003" -#define TR_VCURVEFUNC "---""x>0""x<0""|x|""f>0""f<0""|f|" +#define LEN_VCURVEFUNC "\003" +#define TR_VCURVEFUNC "---""x>0""x<0""|x|""f>0""f<0""|f|" -#define LEN_VMLTPX TR("\010","\013") -#define TR_VMLTPX TR("Ajoute\0 ""Multipl.""Remplace","Additionner""Multiplier\0""Remplacer\0 ") +#define LEN_VMLTPX TR("\010", "\013") +#define TR_VMLTPX TR("Ajoute\0 ""Multipl.""Remplace","Additionner""Multiplier\0""Remplacer\0 ") -#define LEN_VMLTPX2 "\002" -#define TR_VMLTPX2 "+=""*="":=" +#define LEN_VMLTPX2 "\002" +#define TR_VMLTPX2 "+=""*="":=" -#define LEN_VMIXTRIMS "\003" -#define TR_VMIXTRIMS "OFF""ON\0""Dir""Prf""Gaz""Ail" +#define LEN_VMIXTRIMS "\003" +#define TR_VMIXTRIMS "OFF""ON\0""Dir""Prf""Gaz""Ail" #if defined(PCBTARANIS) #define TR_CSWTIMER "Tempo" @@ -168,86 +165,87 @@ #endif #if defined(CPUARM) - #define TR_CSWEQUAL "a=x\0 " + #define TR_CSWEQUAL "a=x\0 " #else #define TR_CSWEQUAL #endif -#define LEN_VCSWFUNC "\005" +#define LEN_VCSWFUNC "\005" #if defined(CPUARM) -#define TR_VCSWFUNC "---\0 " TR_CSWEQUAL "a{x\0 ""a>x\0 ""ax""|a|b\0 ""ax\0 ""ax""|a|b\0 ""ax\0 ""ax""|a|b\0 ""ax\0 ""ax""|a|b\0 ""a" +#define LEN_VALARMFN "\001" +#define TR_VALARMFN "<>" -#define LEN_VTELPROTO "\007" -#define TR_VTELPROTO "Aucun ""Hub\0 ""WSHHigh""Halcyon" +#define LEN_VTELPROTO "\007" +#define TR_VTELPROTO "Aucun ""Hub\0 ""WSHHigh""Halcyon" -#define LEN_VOLTSRC "\003" -#define TR_VOLTSRC "---""A1\0""A2\0""FAS""Cel" +#define LEN_VOLTSRC "\003" +#define TR_VOLTSRC "---""A1\0""A2\0""FAS""Cel" -#define LEN_VARIOSRC "\005" +#define LEN_VARIOSRC "\005" #if defined(FRSKY_SPORT) - #define TR_VARIOSRC "Vario""A1\0 ""A2\0" + #define TR_VARIOSRC "Vario""A1\0 ""A2\0""dTE\0" #else #define TR_VARIOSRC "Alti\0""Alti+""Vario""A1\0 ""A2\0" #endif -#define LEN_VSCREEN TR("\004","\007") -#define TR_VSCREEN TR("Val.""Bars","Valeurs""Barres\0") +#define LEN_VSCREEN TR("\004", "\007") +#define TR_VSCREEN TR("Val.""Bars", "Valeurs""Barres\0") -#define LEN_GPSFORMAT "\004" -#define TR_GPSFORMAT "DMS\0NMEA" +#define LEN_GPSFORMAT "\004" +#define TR_GPSFORMAT "DMS\0""NMEA" -#define LEN2_VTEMPLATES 15 -#define LEN_VTEMPLATES "\017" -#define TR_VTEMPLATES "Suppr Mixages\0 ""4 Voies simple\0""Coupure Gaz\0 ""Empennage V\0 ""Elevon\\Delta\0 ""eCCPM\0 ""Conf. Hélico\0 ""Test Servo\0 " +#define LEN2_VTEMPLATES 15 +#define LEN_VTEMPLATES "\017" +#define TR_VTEMPLATES "Suppr Mixages\0 ""4 Voies simple\0""Coupure Gaz\0 ""Empennage V\0 ""Elevon\\Delta\0 ""eCCPM\0 ""Conf. Hélico\0 ""Test Servo\0 " -#define LEN_VSWASHTYPE "\004" -#define TR_VSWASHTYPE "--- ""120 ""120X""140 ""90\0" +#define LEN_VSWASHTYPE "\004" +#define TR_VSWASHTYPE "--- ""120 ""120X""140 ""90\0" -#define LEN_VKEYS "\005" -#define TR_VKEYS TR("Menu\0""Exit\0""Bas\0 ""Haut\0""Droit""Gauch", "Menu\0""Exit\0""Enter""Page\0""Plus\0""Minus") +#define LEN_VKEYS "\005" +#define TR_VKEYS TR("Menu\0""Exit\0""Bas\0 ""Haut\0""Droit""Gauch", "Menu\0""Exit\0""Enter""Page\0""Plus\0""Minus") -#define LEN_VRENCODERS "\003" -#define TR_VRENCODERS "REa""REb" +#define LEN_VRENCODERS "\003" +#define TR_VRENCODERS "REa""REb" -#define LEN_VSWITCHES "\003" -#define LEN_VSRCRAW "\004" +#define LEN_VSWITCHES "\003" +#define LEN_VSRCRAW "\004" #if defined(PCBTARANIS) #define TR_POTS_VSRCRAW "S1\0 ""S2\0 ""S3\0 ""LS\0 ""RS\0 " @@ -355,11 +361,11 @@ #endif #if defined(CPUARM) - #define TR_LOGICALSW "IL1""IL2""IL3""IL4""IL5""IL6""IL7""IL8""IL9""ILA""ILB""ILC""ILD""ILE""ILF""ILG""ILH""ILI""ILJ""ILK""ILL""ILM""ILN""ILO""ILP""ILQ""ILR""ILS""ILT""ILU""ILV""ILW" + #define TR_LOGICALSW "IL1""IL2""IL3""IL4""IL5""IL6""IL7""IL8""IL9""ILA""ILB""ILC""ILD""ILE""ILF""ILG""ILH""ILI""ILJ""ILK""ILL""ILM""ILN""ILO""ILP""ILQ""ILR""ILS""ILT""ILU""ILV""ILW" #elif defined(PCBGRUVIN9X) || defined(CPUM2561) || defined(CPUM128) - #define TR_LOGICALSW "IL1""IL2""IL3""IL4""IL5""IL6""IL7""IL8""IL9""ILA""ILB""ILC""ILD""ILE""ILF" + #define TR_LOGICALSW "IL1""IL2""IL3""IL4""IL5""IL6""IL7""IL8""IL9""ILA""ILB""ILC""ILD""ILE""ILF" #else - #define TR_LOGICALSW "IL1""IL2""IL3""IL4""IL5""IL6""IL7""IL8""IL9""ILA""ILB""ILC" + #define TR_LOGICALSW "IL1""IL2""IL3""IL4""IL5""IL6""IL7""IL8""IL9""ILA""ILB""ILC" #endif #define TR_TRIMS_SWITCHES "tDg""tDd""tPb""tPh""tGb""tGh""tAg""tAd" @@ -385,21 +391,21 @@ #endif #if defined(HELI) -#define TR_CYC_VSRCRAW "CYC1""CYC2""CYC3" + #define TR_CYC_VSRCRAW "CYC1""CYC2""CYC3" #else -#define TR_CYC_VSRCRAW "[C1]""[C2]""[C3]" + #define TR_CYC_VSRCRAW "[C1]""[C2]""[C3]" #endif -#define TR_VSRCRAW "---\0""Dir\0""Prf\0""Gaz\0""Ail\0" TR_POTS_VSRCRAW TR_ROTARY_ENCODERS "MAX\0" TR_CYC_VSRCRAW "TrmD" "TrmP" "TrmG" "TrmA" TR_SW_VSRCRAW +#define TR_VSRCRAW "---\0""Dir\0""Prf\0""Gaz\0""Ail\0" TR_POTS_VSRCRAW TR_ROTARY_ENCODERS "MAX\0" TR_CYC_VSRCRAW "TrmD" "TrmP" "TrmG" "TrmA" TR_SW_VSRCRAW -#define LEN_VTMRMODES "\003" -#define TR_VTMRMODES "OFF""ABS""GZs""GZ%""GZt" +#define LEN_VTMRMODES "\003" +#define TR_VTMRMODES "OFF""ABS""GZs""GZ%""GZt" #define LEN_VTRAINERMODES "\006" #define TR_VTRAINERMODES "Maître""Elève\0" -#define LEN_VFAILSAFE "\011" -#define TR_VFAILSAFE "Maintien\0""Prédéfini""Pas d'imp" +#define LEN_VFAILSAFE "\011" +#define TR_VFAILSAFE "Maintien\0""Prédéfini""Pas d'imp" #if defined(MAVLINK) #define LEN_MAVLINK_BAUDS "\006" @@ -442,43 +448,43 @@ #endif #define TR_BITMAP "Image du modèle" #define TR_TIMER "Chrono " -#define TR_ELIMITS TR("Limites ét","Limites étendues") -#define TR_ETRIMS TR("Trims ét.","Trims étendus") -#define TR_TRIMINC TR("Pas Trim","Pas des trims") +#define TR_ELIMITS TR("Limites ét", "Limites étendues") +#define TR_ETRIMS TR("Trims ét.", "Trims étendus") +#define TR_TRIMINC TR("Pas Trim", "Pas des trims") #define TR_TTRACE "Source gaz" #define TR_TTRIM "Trim gaz" -#define TR_BEEPCTR TR("Bips centr","Bips centrage") -#define TR_PROTO TR(INDENT"Proto.",INDENT"Protocole") -#define TR_PPMFRAME INDENT"Trame PPM" +#define TR_BEEPCTR TR("Bips centr", "Bips centrage") +#define TR_PROTO TR(INDENT "Proto.", INDENT "Protocole") +#define TR_PPMFRAME INDENT "Trame PPM" #define TR_MS "ms" -#define TR_SWITCH TR("Inter","Interrupteur") +#define TR_SWITCH TR("Inter", "Interrupteur") #define TR_TRIMS "Trims" #define TR_FADEIN "Fondu ON" #define TR_FADEOUT "Fondu OFF" #define TR_DEFAULT "(défaut)" #define TR_CHECKTRIMS "\006Vérif\012Trims" #define OFS_CHECKTRIMS (9*FW) -#define TR_SWASHTYPE TR("Type de Plat.","Type de plateau") -#define TR_COLLECTIVE TR("Collectif","Voie du pas collectif") -#define TR_SWASHRING TR("Limite Cycl.","Limite du cyclique") -#define TR_ELEDIRECTION TR("Inv. longitud.","Inversion longitudinal") -#define TR_AILDIRECTION TR("Inv. latéral","Inversion latéral") -#define TR_COLDIRECTION TR("Inv. collectif","Inversion collectif") -#define TR_MODE INDENT"Mode" +#define TR_SWASHTYPE TR("Type de Plat.", "Type de plateau") +#define TR_COLLECTIVE TR("Collectif", "Voie du pas collectif") +#define TR_SWASHRING TR("Limite Cycl.", "Limite du cyclique") +#define TR_ELEDIRECTION TR("Inv. longitud.", "Inversion longitudinal") +#define TR_AILDIRECTION TR("Inv. latéral", "Inversion latéral") +#define TR_COLDIRECTION TR("Inv. collectif", "Inversion collectif") +#define TR_MODE INDENT "Mode" #define TR_NOFREEEXPO "Max expos atteint!" #define TR_NOFREEMIXER "Max mixages atteint!" #define TR_INSERTMIX "INSERER MIXAGE" #define TR_EDITMIX "EDITER MIXAGE" -#define TR_SOURCE INDENT"Source" +#define TR_SOURCE INDENT "Source" #define TR_WEIGHT "Ratio" -#define TR_EXPO TR("Expo","Exponentiel") +#define TR_EXPO TR("Expo", "Exponentiel") #define TR_SIDE "Coté" #define TR_DIFFERENTIAL "Différentiel" -#define TR_OFFSET INDENT"Décalage" +#define TR_OFFSET INDENT "Décalage" #define TR_TRIM "Trim" #define TR_DREX "DRex" #define TR_CURVE "Courbe" -#define TR_FLMODE TR("Phase","Phases") +#define TR_FLMODE TR("Phase", "Phases") #define TR_MIXWARNING "Alerte" #define TR_OFF "OFF" #define TR_MULTPX "Opération" @@ -490,33 +496,33 @@ #define TR_CV "CB" #define TR_GV "VG" #define TR_ACHANNEL "A" -#define TR_RANGE INDENT"Plage" +#define TR_RANGE INDENT "Plage" #define TR_BAR "Barre" -#define TR_ALARM INDENT"Alarme" +#define TR_ALARM INDENT "Alarme" #define TR_USRDATA "Données" -#define TR_BLADES INDENT"Pales" +#define TR_BLADES INDENT "Pales" #define TR_SCREEN "Ecran " #define TR_SOUND_LABEL "Son" -#define TR_LENGTH INDENT"Durée" -#define TR_SPKRPITCH INDENT"Tonalité" +#define TR_LENGTH INDENT "Durée" +#define TR_SPKRPITCH INDENT "Tonalité" #define TR_HAPTIC_LABEL "Vibreur" -#define TR_HAPTICSTRENGTH INDENT"Force" +#define TR_HAPTICSTRENGTH INDENT "Force" #define TR_CONTRAST "Contraste" #define TR_ALARMS_LABEL "Alarmes" #define TR_BATTERY_RANGE "Plage batterie" -#define TR_BATTERYWARNING TR(INDENT"Batterie",INDENT"Batterie faible") -#define TR_INACTIVITYALARM INDENT"Inactivité" -#define TR_MEMORYWARNING INDENT"Mémoire pleine" -#define TR_ALARMWARNING TR(INDENT"Silence",INDENT"Sons désactivés") +#define TR_BATTERYWARNING TR(INDENT "Batterie",INDENT "Batterie faible") +#define TR_INACTIVITYALARM INDENT "Inactivité" +#define TR_MEMORYWARNING INDENT "Mémoire pleine" +#define TR_ALARMWARNING TR(INDENT "Silence",INDENT "Sons désactivés") #define TR_RENAVIG "Navig EncRot" #define TR_THROTTLEREVERSE TR("Inv. gaz","Inversion gaz") -#define TR_MINUTEBEEP TR(INDENT"Bip min.",INDENT"Annonces minutes") -#define TR_BEEPCOUNTDOWN TR(INDENT"Bip fin",INDENT"Compte à rebours") -#define TR_PERSISTENT TR(INDENT"Persist.",INDENT"Persistant") +#define TR_MINUTEBEEP TR(INDENT "Bip min.",INDENT "Annonces minutes") +#define TR_BEEPCOUNTDOWN TR(INDENT "Bip fin",INDENT "Compte à rebours") +#define TR_PERSISTENT TR(INDENT "Persist.",INDENT "Persistant") #define TR_BACKLIGHT_LABEL "Rétroéclairage" -#define TR_BLDELAY INDENT"Durée" -#define TR_BLONBRIGHTNESS INDENT"Luminosité ON" -#define TR_BLOFFBRIGHTNESS INDENT"Luminosité OFF" +#define TR_BLDELAY INDENT "Durée" +#define TR_BLONBRIGHTNESS INDENT "Luminosité ON" +#define TR_BLOFFBRIGHTNESS INDENT "Luminosité OFF" #define TR_SPLASHSCREEN "Logo d'accueil" #define TR_THROTTLEWARNING "Alerte gaz" #define TR_SWITCHWARNING TR("Alerte int","Alerte interrupt.") @@ -581,28 +587,28 @@ #define TR_MENUHELISETUP TR("CONF.HELI","CONFIGURATION HELICO") #if defined(PCBTARANIS) - #define TR_MENUINPUTS "ENTREES" - #define TR_MENULIMITS "SORTIES" + #define TR_MENUINPUTS "ENTREES" + #define TR_MENULIMITS "SORTIES" #elif defined(PPM_CENTER_ADJUSTABLE) || defined(PPM_LIMITS_SYMETRICAL) // The right menu titles for the gurus ... - #define TR_MENUINPUTS "MANCHES" - #define TR_MENULIMITS "SORTIES" + #define TR_MENUINPUTS "MANCHES" + #define TR_MENULIMITS "SORTIES" #else - #define TR_MENUINPUTS "DR/EXPO" - #define TR_MENULIMITS "LIMITES" + #define TR_MENUINPUTS "DR/EXPO" + #define TR_MENULIMITS "LIMITES" #endif #define TR_MENUCURVES "COURBES" #define TR_MENUCURVE "COURBE" -#define TR_MENULOGICALSWITCH "INTER LOG." -#define TR_MENULOGICALSWITCHES TR("INTERS LOG.","INTERS LOGIQUES") +#define TR_MENULOGICALSWITCH "INTER LOG." +#define TR_MENULOGICALSWITCHES TR("INTERS LOG.","INTERS LOGIQUES") #define TR_MENUCUSTOMFUNC TR("FONCTIONS SPEC.","FONCTIONS SPECIALES") #define TR_MENUTELEMETRY "TELEMESURE" #define TR_MENUTEMPLATES "GABARITS" #define TR_MENUSTAT TR("STATS","STATISTIQUES") #define TR_MENUDEBUG "DEBUG" -#define TR_RXNUM TR(INDENT"NumRx",INDENT"No. récepteur") +#define TR_RXNUM TR(INDENT "NumRx",INDENT "No. récepteur") #define TR_SYNCMENU "Sync [MENU]" -#define TR_LIMIT INDENT"Limite" +#define TR_LIMIT INDENT "Limite" #define TR_MINRSSI "RSSI Min." #define TR_LATITUDE "Latitude" #define TR_LONGITUDE "Longitude" @@ -611,8 +617,8 @@ #define TR_SHUTDOWN "ARRET EN COURS" #define TR_BATT_CALIB "Calib. Batterie" #define TR_CURRENT_CALIB "Calib. Courant" -#define TR_VOLTAGE INDENT"Tension" -#define TR_CURRENT INDENT"Courant" +#define TR_VOLTAGE INDENT "Tension" +#define TR_CURRENT INDENT "Courant" #define TR_SELECT_MODEL "Sélect. Modèle" #define TR_CREATE_MODEL "Créer Modèle" #define TR_COPY_MODEL "Copier Modèle" @@ -679,10 +685,10 @@ #define TR_CHANNELS_MONITOR "MONITEUR CANAUX" #define TR_INTERNALRF "HF interne" #define TR_EXTERNALRF "HF externe" -#define TR_FAILSAFE INDENT"Type failsafe" +#define TR_FAILSAFE INDENT "Type failsafe" #define TR_FAILSAFESET "REGLAGES FAILSAFE" #define TR_COUNTRYCODE "Zone géo." -#define TR_VOICELANG TR("Langue voix","Langue annonces vocales") +#define TR_VOICELANG TR("Langue voix", "Langue annonces vocales") #define TR_UNITSSYSTEM "Unités" #define TR_EDIT "Editer" #define TR_INSERT_BEFORE "Insérer avant" @@ -692,16 +698,16 @@ #define TR_PASTE "Coller" #define TR_DELETE "Effacer" #define TR_INSERT "Insérer" -#define TR_RESET_FLIGHT TR("Réinit. vol","Réinitialiser vol") -#define TR_RESET_TIMER1 TR("Réinit. Timer1","Réinitialiser Timer1") -#define TR_RESET_TIMER2 TR("Réinit. Timer2","Réinitialiser Timer2") -#define TR_RESET_TELEMETRY TR("Réinit. Télém.","Réinit. Télémesure") +#define TR_RESET_FLIGHT TR("Réinit. vol", "Réinitialiser vol") +#define TR_RESET_TIMER1 TR("Réinit. Timer1", "Réinitialiser Timer1") +#define TR_RESET_TIMER2 TR("Réinit. Timer2", "Réinitialiser Timer2") +#define TR_RESET_TELEMETRY TR("Réinit. Télém.", "Réinit. Télémesure") #define TR_STATISTICS "Statistiques" #define TR_ABOUT_US "A propos" #define TR_AND_SWITCH "ET suppl." #define TR_CF "FS" -#define TR_SPEAKER INDENT"Haut-p." -#define TR_BUZZER INDENT"Bipeur" +#define TR_SPEAKER INDENT "Haut-p." +#define TR_BUZZER INDENT "Bipeur" #define TR_BYTES "bytes" #define TR_MODULE_BIND "[Bind]" #define TR_MODULE_RANGE "[Port.]" @@ -709,12 +715,12 @@ #define TR_SET "[Déf.]" #define TR_TRAINER "Ecolage" #define TR_ANTENNAPROBLEM CENTER "Antenne radio défectueuse!" -#define TR_MODELIDUSED TR("ID déjà affecté","No de modèle déjà utilisé") +#define TR_MODELIDUSED TR("ID déjà affecté", "No de modèle déjà utilisé") #define TR_MODULE INDENT "Type de module" #define TR_CHANNELRANGE INDENT "Plage de canaux" #define TR_LOWALARM INDENT "Alarme basse" #define TR_CRITICALALARM INDENT "Alarme critique" -#define TR_PERSISTENT_MAH TR(INDENT "Enr. mAh",INDENT "Enregistrer mAh") +#define TR_PERSISTENT_MAH TR(INDENT "Enr. mAh", INDENT "Enregistrer mAh") #define TR_CHECKLIST "Afficher notes" #define TR_FAS_OFFSET TR(INDENT "Corr FAS", INDENT "Correction FAS") #define TR_UART3MODE "Port série" @@ -751,17 +757,17 @@ #define TR_CSW_HEADERS { " Fonction ", " V1 ", " V2 ", " V2 ", " ET suppl. ", " Durée ", " Délai " } //Taranis About screen -#define TR_ABOUTUS TR(" A PROPOS ","A PROPOS") +#define TR_ABOUTUS TR(" A PROPOS ", "A PROPOS") -#define TR_ABOUT_OPENTX_1 TR("OpenTX\001est\001libre,\001non-","OpenTX est libre, non-") -#define TR_ABOUT_OPENTX_2 TR("commercial,\001et\001offert\001sans","commercial et n'offre aucune") -#define TR_ABOUT_OPENTX_3 TR("garantie.\001Il\001est\001développé","garantie. Il a été développé") -#define TR_ABOUT_OPENTX_4 TR("gratuitement.\001Donations","gratuitement. Vos donations") -#define TR_ABOUT_OPENTX_5 TR("bienvenues!","sont bienvenues!") +#define TR_ABOUT_OPENTX_1 TR("OpenTX\001est\001libre,\001non-", "OpenTX est libre, non-") +#define TR_ABOUT_OPENTX_2 TR("commercial,\001et\001offert\001sans", "commercial et n'offre aucune") +#define TR_ABOUT_OPENTX_3 TR("garantie.\001Il\001est\001développé", "garantie. Il a été développé") +#define TR_ABOUT_OPENTX_4 TR("gratuitement.\001Donations", "gratuitement. Vos donations") +#define TR_ABOUT_OPENTX_5 TR("bienvenues!", "sont bienvenues!") #define TR_ABOUT_BERTRAND_1 "Bertrand Songis" -#define TR_ABOUT_BERTRAND_2 TR("Auteur\001principal\001d'OpenTX","Auteur principal d'OpenTX") -#define TR_ABOUT_BERTRAND_3 TR("Codéveloppeur\001de\001C9X","Codéveloppeur de Companion9x") +#define TR_ABOUT_BERTRAND_2 TR("Auteur\001principal\001d'OpenTX", "Auteur principal d'OpenTX") +#define TR_ABOUT_BERTRAND_3 TR("Codéveloppeur\001de\001C9X", "Codéveloppeur de Companion9x") #define TR_ABOUT_MIKE_1 "Mike Blandford" #define TR_ABOUT_MIKE_2 "Maître du code et des" @@ -783,13 +789,13 @@ #define TR_ABOUT_MARTIN_2 "Design graphique" #if defined(PCBTARANIS) - #define TR_ABOUT_HARDWARE_1 "FrSky" - #define TR_ABOUT_HARDWARE_2 "Développeur/fabricant" - #define TR_ABOUT_HARDWARE_3 "du matériel" + #define TR_ABOUT_HARDWARE_1 "FrSky" + #define TR_ABOUT_HARDWARE_2 "Développeur/fabricant" + #define TR_ABOUT_HARDWARE_3 "du matériel" #else - #define TR_ABOUT_HARDWARE_1 "Brent Nelson" - #define TR_ABOUT_HARDWARE_2 "Développeur/fabricant" - #define TR_ABOUT_HARDWARE_3 "de la carte Sky9x" + #define TR_ABOUT_HARDWARE_1 "Brent Nelson" + #define TR_ABOUT_HARDWARE_2 "Développeur/fabricant" + #define TR_ABOUT_HARDWARE_3 "de la carte Sky9x" #endif #define TR_ABOUT_PARENTS_1 "Projets parents" @@ -797,10 +803,10 @@ #define TR_ABOUT_PARENTS_3 "ER9X (Erez Raviv)" #define TR_ABOUT_PARENTS_4 "TH9X (Thomas Husterer)" -#define TR_CHR_SHORT 's' -#define TR_CHR_LONG 'l' -#define TR_CHR_TOGGLE 't' -#define TR_CHR_HOUR 'h' +#define TR_CHR_SHORT 's' +#define TR_CHR_LONG 'l' +#define TR_CHR_TOGGLE 't' +#define TR_CHR_HOUR 'h' #define TR_CHR_INPUT 'E' // Values between A-I will work #define TR_BEEP_VOLUME "Beep Volume" From 13a2fdfc00df37859ba12c2f89e2de2e42a09b0b Mon Sep 17 00:00:00 2001 From: mhotar Date: Mon, 3 Mar 2014 23:48:49 +0100 Subject: [PATCH 011/285] indentations and ifdef corrected --- radio/src/gui/menu_model.cpp | 6 ++---- radio/src/translations/de.h.txt | 4 ++-- radio/src/translations/fi.h.txt | 4 ++-- radio/src/translations/fr.h.txt | 14 +++++++------- radio/src/translations/it.h.txt | 10 +++++----- radio/src/translations/pl.h.txt | 18 +++++++++--------- radio/src/translations/pt.h.txt | 12 ++++++------ radio/src/translations/se.h.txt | 14 +++++++------- 8 files changed, 40 insertions(+), 42 deletions(-) diff --git a/radio/src/gui/menu_model.cpp b/radio/src/gui/menu_model.cpp index 5e42edc11..61cba0a89 100644 --- a/radio/src/gui/menu_model.cpp +++ b/radio/src/gui/menu_model.cpp @@ -875,9 +875,7 @@ enum menuModelSetupItems { ITEM_MODEL_THROTTLE_TRACE, ITEM_MODEL_THROTTLE_TRIM, CASE_PCBTARANIS(ITEM_MODEL_PREFLIGHT_LABEL) -#if defined(PCBTARANIS) - ITEM_MODEL_CHECKLIST_DISPLAY, -#endif + CASE_PCBTARANIS(ITEM_MODEL_CHECKLIST_DISPLAY) ITEM_MODEL_THROTTLE_WARNING, ITEM_MODEL_SWITCHES_WARNING, CASE_PCBTARANIS(ITEM_MODEL_POT_WARNING) @@ -966,7 +964,7 @@ void menuModelSetup(uint8_t event) #define POT_WARN_ITEMS() ((g_model.nPotsToWarn >> 6) ? (uint8_t)NUM_POTS : (uint8_t)0) bool CURSOR_ON_CELL = (m_posHorz >= 0); - MENU_TAB({ 0, 0, CASE_PCBTARANIS(0) 2, IF_PERSISTENT_TIMERS(0) 0, 0, 2, IF_PERSISTENT_TIMERS(0) 0, 0, 0, 1, 0,LABEL(Throttle), 0, 0, 0,LABEL(PreflightCheck), CASE_PCBTARANIS(0) 0, 7, POT_WARN_ITEMS(), NAVIGATION_LINE_BY_LINE|(NUM_STICKS+NUM_POTS+NUM_ROTARY_ENCODERS-1), LABEL(InternalModule), 0, IF_PORT1_ON(1), IF_PORT1_ON(IS_D8_RX(0) ? (uint8_t)1 : (uint8_t)2), IF_PORT1_ON(FAILSAFE_ROWS(0)), LABEL(ExternalModule), (g_model.externalModule==MODULE_TYPE_XJT || IS_MODULE_DSM2(EXTERNAL_MODULE)) ? (uint8_t)1 : (uint8_t)0, PORT2_CHANNELS_ROWS(), (IS_MODULE_XJT(1) && IS_D8_RX(1)) ? (uint8_t)1 : (IS_MODULE_PPM(1) || IS_MODULE_XJT(1) || IS_MODULE_DSM2(1)) ? (uint8_t)2 : HIDDEN_ROW, IF_PORT2_XJT(FAILSAFE_ROWS(1)), LABEL(Trainer), 0, TRAINER_CHANNELS_ROWS(), IF_TRAINER_ON(2)}); + MENU_TAB({ 0, 0, CASE_PCBTARANIS(0) 2, IF_PERSISTENT_TIMERS(0) 0, 0, 2, IF_PERSISTENT_TIMERS(0) 0, 0, 0, 1, 0,CASE_PCBTARANIS(LABEL(Throttle)) 0, 0, 0,CASE_PCBTARANIS(LABEL(PreflightCheck)) CASE_PCBTARANIS(0) 0, 7, POT_WARN_ITEMS(), NAVIGATION_LINE_BY_LINE|(NUM_STICKS+NUM_POTS+NUM_ROTARY_ENCODERS-1), LABEL(InternalModule), 0, IF_PORT1_ON(1), IF_PORT1_ON(IS_D8_RX(0) ? (uint8_t)1 : (uint8_t)2), IF_PORT1_ON(FAILSAFE_ROWS(0)), LABEL(ExternalModule), (g_model.externalModule==MODULE_TYPE_XJT || IS_MODULE_DSM2(EXTERNAL_MODULE)) ? (uint8_t)1 : (uint8_t)0, PORT2_CHANNELS_ROWS(), (IS_MODULE_XJT(1) && IS_D8_RX(1)) ? (uint8_t)1 : (IS_MODULE_PPM(1) || IS_MODULE_XJT(1) || IS_MODULE_DSM2(1)) ? (uint8_t)2 : HIDDEN_ROW, IF_PORT2_XJT(FAILSAFE_ROWS(1)), LABEL(Trainer), 0, TRAINER_CHANNELS_ROWS(), IF_TRAINER_ON(2)}); #elif defined(CPUM64) #define CURSOR_ON_CELL (true) #define MODEL_SETUP_MAX_LINES ((IS_PPM_PROTOCOL(protocol)||IS_DSM2_PROTOCOL(protocol)||IS_PXX_PROTOCOL(protocol)) ? 1+ITEM_MODEL_SETUP_MAX : ITEM_MODEL_SETUP_MAX) diff --git a/radio/src/translations/de.h.txt b/radio/src/translations/de.h.txt index e93fcd68f..5cb0c795e 100644 --- a/radio/src/translations/de.h.txt +++ b/radio/src/translations/de.h.txt @@ -441,7 +441,7 @@ #define TR_ETRIMS TR("Erw.Trims","Erweit. Trimmung") #define TR_TRIMINC TR("Trim Schr.","Trimm Schritte") #define TR_TTRACE TR("Gasquelle", INDENT "Gas Quelle") -#define TR_TTRIM TR("Gastrim",INDENT "Gas Trimmung") +#define TR_TTRIM TR("Gastrim", INDENT "Gas Trimmung") #define TR_BEEPCTR TR("Mitt.Piep","Mittelst. Pieps") #define TR_PROTO TR(INDENT"Proto.",INDENT"Protokoll") #define TR_PPMFRAME "PPM Einst." @@ -515,7 +515,7 @@ #define TR_BLOFFBRIGHTNESS INDENT"Aus Helligkeit" #define TR_SPLASHSCREEN "Startbild" #define TR_THROTTLEWARNING TR("Gas Alarm", INDENT "Gas Alarm") -#define TR_SWITCHWARNING TR("Sch. Alarm",INDENT "Schalter Alarm") +#define TR_SWITCHWARNING TR("Sch. Alarm", INDENT "Schalter Alarm") #define TR_POTWARNING TR("Pot Warn.", INDENT "Pot Warning") #define TR_TIMEZONE TR("Zeitzone","GPS Zeit Zone") #define TR_RXCHANNELORD TR("Kanalanordnung","Kanalvoreinstellung") diff --git a/radio/src/translations/fi.h.txt b/radio/src/translations/fi.h.txt index d0541e7f2..ced15354b 100644 --- a/radio/src/translations/fi.h.txt +++ b/radio/src/translations/fi.h.txt @@ -515,8 +515,8 @@ #define TR_BLOFFBRIGHTNESS INDENT"OFF Brightness" #define TR_SPLASHSCREEN "Splash screen" #define TR_THROTTLEWARNING TR("T-Warning", INDENT "Throttle Warning") -#define TR_SWITCHWARNING TR("S-Warning",INDENT "Switch Warning") -#define TR_POTWARNING TR("Pot Warn.",INDENT "Pot Warning") +#define TR_SWITCHWARNING TR("S-Warning", INDENT "Switch Warning") +#define TR_POTWARNING TR("Pot Warn.", INDENT "Pot Warning") #define TR_TIMEZONE TR("Time Zone","GPS Time zone") #define TR_RXCHANNELORD TR("Rx Channel Ord","Default channel order") #define TR_SLAVE "Slave" diff --git a/radio/src/translations/fr.h.txt b/radio/src/translations/fr.h.txt index 6fec8a7d7..6bbf97318 100644 --- a/radio/src/translations/fr.h.txt +++ b/radio/src/translations/fr.h.txt @@ -440,8 +440,8 @@ #define TR_ELIMITS TR("Limites ét","Limites étendues") #define TR_ETRIMS TR("Trims ét.","Trims étendus") #define TR_TRIMINC TR("Pas Trim","Pas des trims") -#define TR_TTRACE TR("Source gaz",INDENT"Source gaz") -#define TR_TTRIM TR("Trim gaz",INDENT"Trim gaz") +#define TR_TTRACE TR("Source gaz", INDENT "Source gaz") +#define TR_TTRIM TR("Trim gaz", INDENT "Trim gaz") #define TR_BEEPCTR TR("Bips centr","Bips centrage") #define TR_PROTO TR(INDENT"Proto.",INDENT"Protocole") #define TR_PPMFRAME INDENT"Trame PPM" @@ -505,7 +505,7 @@ #define TR_ALARMWARNING TR(INDENT"Silence",INDENT"Sons désactivés") #define TR_RENAVIG "Navig EncRot" #define TR_THROTTLE_LABEL "Gaz" -#define TR_THROTTLEREVERSE TR("Inv. gaz",INDENT"Inversion gaz") +#define TR_THROTTLEREVERSE TR("Inv. gaz", INDENT "Inversion gaz") #define TR_MINUTEBEEP TR(INDENT"Bip min.",INDENT"Annonces minutes") #define TR_BEEPCOUNTDOWN TR(INDENT"Bip fin",INDENT"Compte à rebours") #define TR_PERSISTENT TR(INDENT"Persist.",INDENT"Persistant") @@ -514,9 +514,9 @@ #define TR_BLONBRIGHTNESS INDENT"Luminosité ON" #define TR_BLOFFBRIGHTNESS INDENT"Luminosité OFF" #define TR_SPLASHSCREEN "Logo d'accueil" -#define TR_THROTTLEWARNING TR("Alerte gaz",INDENT"Alerte gaz") -#define TR_SWITCHWARNING TR("Alerte int",INDENT"Alerte interrupt.") -#define TR_POTWARNING TR("Alerte pot",INDENT"Alerte potentiom.") +#define TR_THROTTLEWARNING TR("Alerte gaz", INDENT "Alerte gaz") +#define TR_SWITCHWARNING TR("Alerte int", INDENT "Alerte interrupt.") +#define TR_POTWARNING TR("Alerte pot", INDENT "Alerte potentiom.") #define TR_TIMEZONE "Fuseau horaire" #define TR_RXCHANNELORD TR("Ordre voies RX","Ordre des voies préféré") #define TR_SLAVE "Elève" @@ -712,7 +712,7 @@ #define TR_CRITICALALARM INDENT "Alarme critique" #define TR_PERSISTENT_MAH TR(INDENT "Enr. mAh",INDENT "Enregistrer mAh") #define TR_PREFLIGHT "Preflight Checks" -#define TR_CHECKLIST INDENT"Afficher notes" +#define TR_CHECKLIST INDENT "Afficher notes" #define TR_FAS_OFFSET TR(INDENT "Corr FAS", INDENT "Correction FAS") #define TR_UART3MODE "Port série" #define TR_POT1TYPE "Type S1" diff --git a/radio/src/translations/it.h.txt b/radio/src/translations/it.h.txt index 7e3283647..555ce7bb9 100644 --- a/radio/src/translations/it.h.txt +++ b/radio/src/translations/it.h.txt @@ -440,8 +440,8 @@ #define TR_ELIMITS TR("Limiti.E","Limiti Estesi") #define TR_ETRIMS TR("Trim Ext","Trim Estesi") #define TR_TRIMINC "Trim Step" -#define TR_TTRACE TR("T-Source",INDENT "Throttle Source") -#define TR_TTRIM TR("T-Trim",INDENT "Throttle Trim") +#define TR_TTRACE TR("T-Source", INDENT "Throttle Source") +#define TR_TTRIM TR("T-Trim", INDENT "Throttle Trim") #define TR_BEEPCTR TR("Ctr Beep","Center Beep") #define TR_PROTO TR(INDENT "Proto", INDENT "Protocollo") #define TR_PPMFRAME TR("PPM frame", INDENT "PPM frame") @@ -514,9 +514,9 @@ #define TR_BLONBRIGHTNESS TR(INDENT"Lumin. ON",INDENT"Luminosità ON") #define TR_BLOFFBRIGHTNESS TR(INDENT"Lumin. OFF",INDENT"Luminosità OFF") #define TR_SPLASHSCREEN TR("Schermo avvio", "Schermata di avvio") -#define TR_THROTTLEWARNING TR("All. Thr", INDENT"Allarme Throttle") -#define TR_SWITCHWARNING TR("Avv. Int.", INDENT"Avviso Interr.") -#define TR_POTWARNING TR("Pot Warn.", INDENT"Pot Warning") +#define TR_THROTTLEWARNING TR("All. Thr", INDENT "Allarme Throttle") +#define TR_SWITCHWARNING TR("Avv. Int.", INDENT "Avviso Interr.") +#define TR_POTWARNING TR("Pot Warn.", INDENT "Pot Warning") #define TR_TIMEZONE "Ora locale" #define TR_RXCHANNELORD "Ordine ch RX" #define TR_SLAVE "Allievo" diff --git a/radio/src/translations/pl.h.txt b/radio/src/translations/pl.h.txt index 065201e6d..e81b30c8a 100644 --- a/radio/src/translations/pl.h.txt +++ b/radio/src/translations/pl.h.txt @@ -440,8 +440,8 @@ #define TR_ELIMITS TR("Limit+25%", "Kanał +/- 125%") #define TR_ETRIMS TR("Trymery 100%", "Poszerzone Trymery") #define TR_TRIMINC TR("Krok Trymera", "Krok trymera") -#define TR_TTRACE TR("Źródło gazu", INDENT"Źródło gazu") -#define TR_TTRIM TR("Trymer gazu", INDENT"Trymer gazu") +#define TR_TTRACE TR("Źródło gazu", INDENT "Źródło gazu") +#define TR_TTRIM TR("Trymer gazu", INDENT "Trymer gazu") #define TR_BEEPCTR "(\043)Pikanie środka" #define TR_PROTO INDENT"Protokól" #define TR_PPMFRAME "Ramka PPM" @@ -505,18 +505,18 @@ #define TR_ALARMWARNING INDENT"Wyłącz dźwięk" #define TR_RENAVIG "Nawigacja potencjometrem" #define TR_THROTTLE_LABEL "Throttle" -#define TR_THROTTLEREVERSE TR("Odwróć gaz", INDENT"Odwróć gaz") -#define TR_MINUTEBEEP TR(INDENT"Minuta", INDENT"Pik co minutę") -#define TR_BEEPCOUNTDOWN TR(INDENT"Odliczanie", INDENT"Odliczanie") +#define TR_THROTTLEREVERSE TR("Odwróć gaz", INDENT "Odwróć gaz") +#define TR_MINUTEBEEP TR(INDENT "Minuta", INDENT "Pik co minutę") +#define TR_BEEPCOUNTDOWN TR(INDENT "Odliczanie", INDENT "Odliczanie") #define TR_PERSISTENT INDENT"Dokładny" #define TR_BACKLIGHT_LABEL "Podświetlenie" #define TR_BLDELAY INDENT"Czas trwania" #define TR_BLONBRIGHTNESS INDENT"Jasnośc wł." #define TR_BLOFFBRIGHTNESS INDENT"Jasność wył." #define TR_SPLASHSCREEN "Logo ekranu" -#define TR_THROTTLEWARNING TR("(\043)Gaz",INDENT"(\043)Gaz") -#define TR_SWITCHWARNING TR("(\043)Przełącznik",INDENT"(\043)Przełącznik") -#define TR_POTWARNING TR("Pot Warn.",INDENT"Pot Warning") +#define TR_THROTTLEWARNING TR("(\043)Gaz", INDENT "(\043)Gaz") +#define TR_SWITCHWARNING TR("(\043)Przełącznik", INDENT "(\043)Przełącznik") +#define TR_POTWARNING TR("Pot Warn.", INDENT "Pot Warning") #define TR_TIMEZONE "Strefa czasowa" #define TR_RXCHANNELORD TR("Kolejność kanałów", "Bazowa kolejność kanałów") #define TR_SLAVE "Uczeń" @@ -712,7 +712,7 @@ #define TR_CRITICALALARM INDENT "Alarm krytyczny" #define TR_PERSISTENT_MAH INDENT "Zapisz mAh" #define TR_PREFLIGHT "Preflight Checks" -#define TR_CHECKLIST INDENT"Display Checklist" +#define TR_CHECKLIST INDENT "Display Checklist" #define TR_FAS_OFFSET TR(INDENT "FAS Ofs", INDENT "FAS Offset") #define TR_UART3MODE "Port szreg." #define TR_POT1TYPE "Typ S1" diff --git a/radio/src/translations/pt.h.txt b/radio/src/translations/pt.h.txt index aa6662795..6b6b9c89f 100644 --- a/radio/src/translations/pt.h.txt +++ b/radio/src/translations/pt.h.txt @@ -440,8 +440,8 @@ #define TR_ELIMITS "E.Limits" #define TR_ETRIMS "E.Trims" #define TR_TRIMINC "Trim Step" -#define TR_TTRACE TR("T-Trace",INDENT"T-Trace") -#define TR_TTRIM TR("T-Trim",INDENT"T-Trim") +#define TR_TTRACE TR("T-Trace", INDENT "T-Trace") +#define TR_TTRIM TR("T-Trim", INDENT "T-Trim") #define TR_BEEPCTR "Ctr Beep" #define TR_PROTO INDENT"Proto" #define TR_PPMFRAME "PPM frame" @@ -505,7 +505,7 @@ #define TR_ALARMWARNING INDENT"Som Off" #define TR_RENAVIG "RotEnc Navig" #define TR_THROTTLE_LABEL "Throttle" -#define TR_THROTTLEREVERSE TR("Inverte Acel.",INDENT"Inverte Acel.") +#define TR_THROTTLEREVERSE TR("Inverte Acel.", INDENT "Inverte Acel.") #define TR_MINUTEBEEP INDENT"Beep Minuto" #define TR_BEEPCOUNTDOWN INDENT"Beep Regressivo" #define TR_PERSISTENT INDENT"Persist." @@ -514,9 +514,9 @@ #define TR_BLONBRIGHTNESS INDENT"ON Brightness" #define TR_BLOFFBRIGHTNESS INDENT"OFF Brightness" #define TR_SPLASHSCREEN "Splash screen" -#define TR_THROTTLEWARNING TR("Avisa Acel",INDENT"Avisa Acel") -#define TR_SWITCHWARNING TR("Avisa Chav",INDENT"Avisa Chav") -#define TR_POTWARNING TR("Pot Warn.",INDENT"Pot Warning") +#define TR_THROTTLEWARNING TR("Avisa Acel", INDENT "Avisa Acel") +#define TR_SWITCHWARNING TR("Avisa Chav", INDENT "Avisa Chav") +#define TR_POTWARNING TR("Pot Warn.", INDENT "Pot Warning") #define TR_TIMEZONE "Time Zone" #define TR_RXCHANNELORD "Ordem Canal RX" #define TR_SLAVE "Escravo" diff --git a/radio/src/translations/se.h.txt b/radio/src/translations/se.h.txt index 024726df1..3d2e0df7b 100644 --- a/radio/src/translations/se.h.txt +++ b/radio/src/translations/se.h.txt @@ -440,10 +440,10 @@ #define TR_ELIMITS TR("Gränser++","Utökade Gränser") #define TR_ETRIMS TR("Trimmar++","Utökade Trimmar") #define TR_TRIMINC TR("Trimning","Trimökning") -#define TR_TTRACE TR("Följ Gas",INDENT"Följ Gas") -#define TR_TTRIM TR("Gastrim",INDENT"Gastrim") +#define TR_TTRACE TR("Följ Gas", INDENT "Följ Gas") +#define TR_TTRIM TR("Gastrim", INDENT "Gastrim") #define TR_BEEPCTR TR("Cent.pip", "Centerpip") -#define TR_PROTO TR(INDENT"Proto",INDENT"Protokoll") +#define TR_PROTO TR(INDENT "Proto", INDENT "Protokoll") #define TR_PPMFRAME "PPM-paket" #define TR_MS "ms" #define TR_SWITCH "Brytare" @@ -505,7 +505,7 @@ #define TR_ALARMWARNING INDENT"Ljud Av" #define TR_RENAVIG "RotEnc Navig" #define TR_THROTTLE_LABEL "Throttle" -#define TR_THROTTLEREVERSE TR("Revers.Gas",INDENT"Revers.Gas") +#define TR_THROTTLEREVERSE TR("Revers.Gas", INDENT "Revers.Gas") #define TR_MINUTEBEEP INDENT"Minutpip" #define TR_BEEPCOUNTDOWN INDENT"Räkna Ned" #define TR_PERSISTENT TR("Jämt på ",INDENT"Alltid På") @@ -514,9 +514,9 @@ #define TR_BLONBRIGHTNESS INDENT"På Ljusstyrka" #define TR_BLOFFBRIGHTNESS INDENT"Av Ljusstyrka" #define TR_SPLASHSCREEN "Startbild" -#define TR_THROTTLEWARNING TR("Gasvarning",INDENT"Gasvarning") -#define TR_SWITCHWARNING TR("Bryt.varn.",INDENT"Brytarvarning") -#define TR_POTWARNING TR("Pot Warn.",INDENT"Pot Warning") +#define TR_THROTTLEWARNING TR("Gasvarning", INDENT "Gasvarning") +#define TR_SWITCHWARNING TR("Bryt.varn.", INDENT "Brytarvarning") +#define TR_POTWARNING TR("Pot Warn.", INDENT "Pot Warning") #define TR_TIMEZONE TR("Tidszon","GPS Tidszon") #define TR_RXCHANNELORD "Kanaler i RX" #define TR_SLAVE "Elev" From 92436f47f78480bc92e5c24d24415bc5edc8531e Mon Sep 17 00:00:00 2001 From: bsongis Date: Tue, 4 Mar 2014 09:26:52 +0100 Subject: [PATCH 012/285] PCBX9D replaced everywhere by PCBTARANIS --- companion/src/eeprominterface.h | 22 --------------- radio/bootloader/Makefile | 13 --------- radio/bootloader/boot.cpp | 44 +++++++++++++++--------------- radio/bootloader/driversboot.cpp | 2 +- radio/bootloader/include/diskio.h | 9 ++---- radio/bootloader/include/ersky9x.h | 20 +++++++------- radio/bootloader/include/lcd.h | 4 +-- radio/bootloader/include/logicio.h | 4 +-- radio/bootloader/include/radio.h | 4 +-- radio/bootloader/include/timers.h | 2 +- radio/bootloader/lcdboot.cpp | 4 +-- radio/bootloader/logicioboot.cpp | 8 +++--- radio/bootloader/power.cpp | 4 +-- radio/src/loadboot.cpp | 15 ++++------ 14 files changed, 56 insertions(+), 99 deletions(-) diff --git a/companion/src/eeprominterface.h b/companion/src/eeprominterface.h index f4a2bc7dc..e79d9f4ae 100644 --- a/companion/src/eeprominterface.h +++ b/companion/src/eeprominterface.h @@ -125,28 +125,6 @@ const uint8_t chout_ar[] = { //First number is 0..23 -> template setup, Second #define BC_BIT_REA (0x80) #define BC_BIT_REB (0x100) -// TODO remove this enum! -enum EnumKeys { - KEY_MENU, - KEY_EXIT, -#if defined(PCBACT) - KEY_CLR, - KEY_PAGE, - KEY_PLUS, /* Fake, used for rotary encoder */ - KEY_MINUS, /* Fake, used for rotary encoder */ -#elif defined(PCBX9D) - KEY_ENTER, - KEY_PAGE, - KEY_PLUS, - KEY_MINUS, -#else - KEY_DOWN, - KEY_UP, - KEY_RIGHT, - KEY_LEFT, -#endif -}; - #define CHAR_FOR_NAMES " ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789_-." #define CHAR_FOR_NAMES_REGEX "[ A-Za-z0-9_.-,]*" diff --git a/radio/bootloader/Makefile b/radio/bootloader/Makefile index 3b87b4ff5..22b73105f 100644 --- a/radio/bootloader/Makefile +++ b/radio/bootloader/Makefile @@ -91,32 +91,19 @@ ifeq ($(RUN_FROM_FLASH), 1) CPPDEFS += -DPCBSKY UDEFS = -Dat91sam3s8 else - ifeq ($(PCB), X9D) - ARCH = ARM - LDSCRIPT = stm32_ramBoot.ld - TRGT = arm-none-eabi- - CPPDEFS += -DHSE_VALUE=12000000 - CPPDEFS += -DPCBX9D - FULL_PRJ = $(PROJECT)_ramBoot - EXTRAINCDIRS += include -# EXTRAINCDIRS += ../x9d - else ifeq ($(PCB), TARANIS) ARCH = ARM LDSCRIPT = stm32_ramBoot.ld TRGT = arm-none-eabi- CPPDEFS += -DHSE_VALUE=12000000 - CPPDEFS += -DPCBX9D CPPDEFS += -DPCBTARANIS FULL_PRJ = $(PROJECT)_ramBoot EXTRAINCDIRS += include # EXTRAINCDIRS += ../targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include endif - endif endif - # List all user C define here, like -D_DEBUG=1 # Define ASM defines here diff --git a/radio/bootloader/boot.cpp b/radio/bootloader/boot.cpp index ae8627f11..26d320632 100644 --- a/radio/bootloader/boot.cpp +++ b/radio/bootloader/boot.cpp @@ -58,7 +58,7 @@ #include "core_cm3.h" #endif -#ifdef PCBX9D +#ifdef PCBTARANIS #include "stm32f2xx.h" #include "stm32f2xx_flash.h" #include "i2c_ee.h" @@ -96,7 +96,7 @@ extern void usbMassStorage( void ) ; #define DISPLAY_CHAR_WIDTH 21 #endif -#ifdef PCBX9D +#ifdef PCBTARANIS #define BOOT_KEY_UP KEY_PLUS #define BOOT_KEY_DOWN KEY_MINUS #define BOOT_KEY_LEFT KEY_MENU @@ -208,12 +208,12 @@ static bool usbPlugged(void) return PIOC->PIO_PDSR & 0x02000000 ; #endif -#ifdef PCBX9D +#ifdef PCBTARANIS return GPIOA->IDR & 0x0200 ; #endif } -#ifdef PCBX9D +#ifdef PCBTARANIS extern "C" { USB_OTG_CORE_HANDLE USB_OTG_dev; @@ -399,7 +399,7 @@ extern "C" void TC2_IRQHandler() } #endif -#ifdef PCBX9D +#ifdef PCBTARANIS void init10msTimer() { // Timer14 @@ -686,7 +686,7 @@ uint8_t flashFile( uint32_t index ) if ( Valid == 2 ) { lcd_puts_Pleft( 3*FH,"NOT A VALID FIRMWARE") ; -#ifdef PCBX9D +#ifdef PCBTARANIS lcd_puts_Pleft( 6*FH,"\015[EXIT]") ; #else lcd_puts_Pleft( 6*FH,"\007[EXIT]") ; @@ -700,7 +700,7 @@ uint8_t flashFile( uint32_t index ) } lcd_putsn_P( 0, 2*FH, Filenames[index], DISPLAY_CHAR_WIDTH ) ; -#ifdef PCBX9D +#ifdef PCBTARANIS lcd_puts_Pleft( 6*FH,"\010[ENTER]\021[EXIT]") ; lcd_puts_Pleft( 5*FH,"\010YES\021NO") ; #else @@ -736,7 +736,7 @@ int main() { uint32_t i ; uint8_t index = 0 ; -#ifdef PCBX9D +#ifdef PCBTARANIS uint8_t TenCount = 2 ; #endif uint8_t maxhsize = DISPLAY_CHAR_WIDTH ; @@ -745,7 +745,7 @@ int main() uint32_t nameCount = 0 ; uint32_t vpos = 0 ; uint32_t hpos = 0 ; -#ifdef PCBX9D +#ifdef PCBTARANIS uint32_t firmwareAddress = 0x08000000 ; #endif #ifdef PCBSKY @@ -753,7 +753,7 @@ int main() #endif uint32_t firmwareWritten = 0 ; -#ifdef PCBX9D +#ifdef PCBTARANIS wdt_reset() ; RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ; // Enable portA clock #endif @@ -776,7 +776,7 @@ extern uint8_t OptrexDisplay ; OptrexDisplay = 1 ; #endif lcd_clear() ; -#ifdef PCBX9D +#ifdef PCBTARANIS lcd_puts_Pleft( 0, "\006Boot Loader" ) ; #endif refreshDisplay() ; @@ -785,7 +785,7 @@ extern uint8_t OptrexDisplay ; refreshDisplay() ; #endif -#ifdef PCBX9D +#ifdef PCBTARANIS init_keys() ; I2C_EE_Init() ; init_hw_timer() ; @@ -805,7 +805,7 @@ extern uint8_t OptrexDisplay ; FlashSize = ( (chip_id >> 8 ) & 0x000F ) == 9 ? 256 : 512 ; #endif -#ifdef PCBX9D +#ifdef PCBTARANIS FlashSize = 512 ; #endif @@ -817,7 +817,7 @@ extern uint8_t OptrexDisplay ; } #endif -#ifdef PCBX9D +#ifdef PCBTARANIS // SD card detect pin configure_pins( GPIO_Pin_CP, PIN_PORTD | PIN_INPUT | PIN_PULLUP ) ; disk_initialize( 0 ) ; @@ -855,7 +855,7 @@ extern uint8_t OptrexDisplay ; #ifdef PCBSKY lcd_puts_Pleft( 0, "Boot Loader" ) ; #endif -#ifdef PCBX9D +#ifdef PCBTARANIS lcd_puts_Pleft( 0, "\006Boot Loader" ) ; #endif @@ -864,7 +864,7 @@ extern uint8_t OptrexDisplay ; #ifdef PCBSKY lcd_puts_Pleft( 0, "\014Ready" ) ; #endif -#ifdef PCBX9D +#ifdef PCBTARANIS lcd_puts_Pleft( 0, "\022Ready" ) ; #endif @@ -878,7 +878,7 @@ extern uint8_t OptrexDisplay ; #ifdef PCBSKY lcd_puts_Pleft( 3*FH, "\010BUSY" ) ; #endif -#ifdef PCBX9D +#ifdef PCBTARANIS lcd_puts_Pleft( 3*FH, "\016BUSY" ) ; #endif if ( usbPlugged() == 0 ) @@ -923,7 +923,7 @@ extern uint8_t OptrexDisplay ; #ifdef PCBSKY lcd_puts_Pleft( 16, "\005No Firmware" ) ; #endif -#ifdef PCBX9D +#ifdef PCBTARANIS lcd_puts_Pleft( 16, "\013No Firmware" ) ; #endif } @@ -1045,7 +1045,7 @@ extern uint8_t OptrexDisplay ; #ifdef PCBSKY firmwareAddress = 0x00408000 ; #endif -#ifdef PCBX9D +#ifdef PCBTARANIS firmwareAddress = 0x08008000 ; #endif firmwareWritten = 0 ; @@ -1106,13 +1106,13 @@ extern uint8_t OptrexDisplay ; } } -#ifdef PCBX9D +#ifdef PCBTARANIS if ( --TenCount == 0 ) { TenCount = 2 ; #endif refreshDisplay() ; -#ifdef PCBX9D +#ifdef PCBTARANIS } #endif if ( PowerUpDelay < 20 ) // 200 mS @@ -1124,7 +1124,7 @@ extern uint8_t OptrexDisplay ; #ifdef PCBSKY sd_poll_10mS() ; #endif -#ifdef PCBX9D +#ifdef PCBTARANIS sdPoll10ms() ; #endif } diff --git a/radio/bootloader/driversboot.cpp b/radio/bootloader/driversboot.cpp index a848981b0..ca3c917d9 100644 --- a/radio/bootloader/driversboot.cpp +++ b/radio/bootloader/driversboot.cpp @@ -27,7 +27,7 @@ #endif -#ifdef PCBX9D +#ifdef PCBTARANIS #include "radio.h" #include "hal.h" #include "stm32f2xx.h" diff --git a/radio/bootloader/include/diskio.h b/radio/bootloader/include/diskio.h index d36db188d..b05e8073c 100644 --- a/radio/bootloader/include/diskio.h +++ b/radio/bootloader/include/diskio.h @@ -41,7 +41,8 @@ #ifdef PCBSKY #include "board.h" #endif -#ifdef PCBX9D + +#ifdef PCBTARANIS #include "stm32f2xx.h" #endif @@ -133,10 +134,6 @@ void disk_timerproc (void); volatile extern BYTE Timer1, Timer2; /* 100Hz decrement timer */ #endif -//#ifdef PCBX9D -//volatile extern DWORD Timer1, Timer2; /* 100Hz decrement timer */ -//#endif - //------------------------------------------------------------------------------ /// Detect if SD card is connected //------------------------------------------------------------------------------ @@ -164,7 +161,7 @@ extern uint32_t sd_acmd6( void ) ; extern uint32_t sd_acmd51( uint32_t *presult ) ; extern uint32_t sd_cmd13( uint32_t *status) ; extern void sd_poll_10mS( void ) ; -#ifdef PCBX9D +#ifdef PCBTARANIS extern void sdPoll10ms( void ) ; extern void sdInit( void ) ; #endif diff --git a/radio/bootloader/include/ersky9x.h b/radio/bootloader/include/ersky9x.h index 207188b22..e0e0b8640 100644 --- a/radio/bootloader/include/ersky9x.h +++ b/radio/bootloader/include/ersky9x.h @@ -33,7 +33,7 @@ #ifdef PCBSKY #define wdt_reset() (WDT->WDT_CR = 0xA5000001) #endif -#ifdef PCBX9D +#ifdef PCBTARANIS #define wdt_reset() (IWDG->KR = 0x0000AAAAL) #endif #endif @@ -83,7 +83,7 @@ extern const char * const Swedish[] ; #define pgm_read_byte(p) (*(p)) -#ifdef PCBX9D +#ifdef PCBTARANIS #define NUMBER_ANALOG 9 #else #ifdef REVX @@ -132,7 +132,7 @@ enum EnumKeys { SW_Trainer #endif -#ifdef PCBX9D +#ifdef PCBTARANIS SW_SA0, SW_SA1, SW_SA2, @@ -197,7 +197,7 @@ enum EnumKeys { #define MAX_SKYDRSWITCH (1+SW_Trainer-SW_ThrCt+1+NUM_SKYCSW) #endif -#ifdef PCBX9D +#ifdef PCBTARANIS #define SW_BASE SW_SA0 #define SW_BASE_DIAG SW_SA0 #define MAX_PSWITCH (SW_SH2-SW_SA0+1) // 9 physical switches @@ -238,7 +238,7 @@ enum EnumKeys { #ifdef PCBSKY #define CSW_INDEX 9 // Index of first custom switch #endif -#ifdef PCBX9D +#ifdef PCBTARANIS #define CSW_INDEX 22 // Index of first custom switch #endif @@ -312,7 +312,7 @@ enum EnumKeys { #define MIX_CYC2 11 #define MIX_CYC3 12 #endif -#ifdef PCBX9D +#ifdef PCBTARANIS #define MIX_P3 7 #define MIX_P4 8 #define MIX_MAX 9 @@ -497,7 +497,7 @@ extern uint8_t convert_mode_helper(uint8_t x) ; #define BACKLIGHT_OFF (PWM->PWM_CH_NUM[0].PWM_CDTY = 100) #endif -#ifdef PCBX9D +#ifdef PCBTARANIS extern void backlight_on( void ) ; extern void backlight_off( void ) ; #define BACKLIGHT_ON backlight_on() @@ -731,13 +731,13 @@ extern struct t_p1 P1values ; #ifdef PCBSKY extern uint16_t ResetReason ; #endif -#ifdef PCBX9D +#ifdef PCBTARANIS extern uint32_t ResetReason ; #endif extern uint8_t unexpectedShutdown ; extern uint8_t SdMounted ; -#ifdef PCBX9D +#ifdef PCBTARANIS #include "stm32f2xx.h" #include "rtc.h" #include "stm32f2xx_rtc.h" @@ -749,7 +749,7 @@ void rtcInit( void ) ; extern void setVolume( uint8_t value ) ; extern uint8_t HoldVolume ; -#ifdef PCBX9D +#ifdef PCBTARANIS #define INTERNAL_MODULE 0 #define EXTERNAL_MODULE 1 #define TRAINER_MODULE 2 diff --git a/radio/bootloader/include/lcd.h b/radio/bootloader/include/lcd.h index cbea7fd2e..a9e39d09e 100644 --- a/radio/bootloader/include/lcd.h +++ b/radio/bootloader/include/lcd.h @@ -21,7 +21,7 @@ #ifndef lcd_h #define lcd_h -#ifdef PCBX9D +#ifdef PCBTARANIS #define DISPLAY_W 212 #define DISPLAY_H 64 #endif @@ -110,7 +110,7 @@ extern void putsTime(uint8_t x,uint8_t y,int16_t tme,uint8_t att,uint8_t att2) ; extern void putsVolts(uint8_t x,uint8_t y, uint8_t volts, uint8_t att) ; extern void putsVBat(uint8_t x,uint8_t y,uint8_t att) ; -#ifdef PCBX9D +#ifdef PCBTARANIS extern void backlight_set( uint16_t brightness ) ; #endif diff --git a/radio/bootloader/include/logicio.h b/radio/bootloader/include/logicio.h index aa2720a24..a8b004eca 100644 --- a/radio/bootloader/include/logicio.h +++ b/radio/bootloader/include/logicio.h @@ -13,7 +13,7 @@ * ****************************************************************************/ -#ifdef PCBX9D +#ifdef PCBTARANIS #define PIN_MODE_MASK 0x0003 #define PIN_INPUT 0x0000 #define PIN_OUTPUT 0x0001 @@ -117,7 +117,7 @@ extern void config_free_pins( void ) ; #define GPIO_SetBits( port, bits ) (port->BSRRL = bits) #define GPIO_ReadInputDataBit( port, bit) ( (port->IDR & bit) ? Bit_SET : Bit_RESET) -#ifdef PCBX9D +#ifdef PCBTARANIS uint32_t switchPosition( uint32_t swtch ) ; #endif diff --git a/radio/bootloader/include/radio.h b/radio/bootloader/include/radio.h index dc6e1993c..afc5e5b46 100644 --- a/radio/bootloader/include/radio.h +++ b/radio/bootloader/include/radio.h @@ -5,7 +5,7 @@ #ifdef PCBSKY #define wdt_reset() (WDT->WDT_CR = 0xA5000001) #endif -#ifdef PCBX9D +#ifdef PCBTARANIS #define wdt_reset() (IWDG->KR = 0x0000AAAAL) #endif @@ -43,7 +43,7 @@ enum EnumKeys { } ; #endif -#ifdef PCBX9D +#ifdef PCBTARANIS enum EnumKeys { KEY_MENU , KEY_EXIT , diff --git a/radio/bootloader/include/timers.h b/radio/bootloader/include/timers.h index 9352f1c5a..d617d0df4 100644 --- a/radio/bootloader/include/timers.h +++ b/radio/bootloader/include/timers.h @@ -25,7 +25,7 @@ extern void stop_timer0( void ) ; extern void init_pwm( void ) ; #endif -#ifdef PCBX9D +#ifdef PCBTARANIS extern uint32_t Peri1_frequency ; extern uint32_t Peri2_frequency ; extern uint32_t Timer_mult1 ; diff --git a/radio/bootloader/lcdboot.cpp b/radio/bootloader/lcdboot.cpp index 741f80002..06d23bffe 100644 --- a/radio/bootloader/lcdboot.cpp +++ b/radio/bootloader/lcdboot.cpp @@ -28,7 +28,7 @@ //#include "myeeprom.h" #endif -#ifdef PCBX9D +#ifdef PCBTARANIS #include "radio.h" #endif @@ -48,7 +48,7 @@ uint8_t Lcd_lastPos ; uint8_t DisplayBuf[DISPLAY_W*DISPLAY_H/8] ; #define DISPLAY_END (DisplayBuf+sizeof(DisplayBuf)) -#ifdef PCBX9D +#ifdef PCBTARANIS #define X9D_OFFSET 0 #define DISPLAY_START (DisplayBuf + X9D_OFFSET) #else diff --git a/radio/bootloader/logicioboot.cpp b/radio/bootloader/logicioboot.cpp index cc6be1b84..67f44866a 100644 --- a/radio/bootloader/logicioboot.cpp +++ b/radio/bootloader/logicioboot.cpp @@ -25,7 +25,7 @@ #include "drivers.h" #endif -#ifdef PCBX9D +#ifdef PCBTARANIS #include "stm32f2xx.h" #include "stm32f2xx_gpio.h" #include "radio.h" @@ -118,7 +118,7 @@ void configure_pins( uint32_t pins, uint16_t config ) #endif -#ifdef PCBX9D +#ifdef PCBTARANIS void configure_pins( uint32_t pins, uint16_t config ) { uint32_t address ; @@ -389,7 +389,7 @@ uint32_t initReadTrims( void ) } #endif // PCBSKY -#ifdef PCBX9D +#ifdef PCBTARANIS void init_keys() { // Buttons PE10, 11, 12, PD2, 3, 7 @@ -453,5 +453,5 @@ void setup_switches() } -#endif // PCBX9D +#endif // PCBTARANIS diff --git a/radio/bootloader/power.cpp b/radio/bootloader/power.cpp index 9d3ef80ef..5873d62e1 100644 --- a/radio/bootloader/power.cpp +++ b/radio/bootloader/power.cpp @@ -38,7 +38,7 @@ #endif -#ifdef PCBX9D +#ifdef PCBTARANIS #include "stm32f2xx_gpio.h" #include "stm32f2xx_rcc.h" #include "hal.h" @@ -80,7 +80,7 @@ void soft_power_off() #endif -#ifdef PCBX9D +#ifdef PCBTARANIS void soft_power_off() { diff --git a/radio/src/loadboot.cpp b/radio/src/loadboot.cpp index 9093076e8..b06241019 100644 --- a/radio/src/loadboot.cpp +++ b/radio/src/loadboot.cpp @@ -54,21 +54,16 @@ #ifdef PCBTARANIS #include "stm32f2xx.h" #include "stm32f2xx_gpio.h" -#else - #ifdef PCBX9D - #include "x9d\stm32f2xx.h" - #include "x9d\stm32f2xx_gpio.h" - #endif #endif -#if defined(PCBX9D) || defined(PCBTARANIS) +#if defined(PCBTARANIS) void bwdt_reset() { - IWDG->KR = 0xAAAA ; // reload + IWDG->KR = 0xAAAA ; // reload } #endif -#if defined(PCBX9D) || defined(PCBTARANIS) +#if defined(PCBTARANIS) __attribute__ ((section(".bootrodata"), used)) void _bootStart( void ) ; @@ -80,7 +75,7 @@ const uint32_t BootVectors[] = { } ; #endif -#if defined(PCBX9D) || defined(PCBTARANIS) +#if defined(PCBTARANIS) __attribute__ ((section(".bootrodata.*"), used)) #endif @@ -93,7 +88,7 @@ const uint8_t BootCode[] = { } ; -#if defined(PCBX9D) || defined(PCBTARANIS) +#if defined(PCBTARANIS) __attribute__ ((section(".bootrodata"), used)) From d5b83e1b4ea37d6410da22a4b0a010e9743c6dde Mon Sep 17 00:00:00 2001 From: bsongis Date: Tue, 4 Mar 2014 10:41:04 +0100 Subject: [PATCH 013/285] 7 files removed --- radio/bootloader/Makefile | 9 +- radio/bootloader/include/stm32f2xx_gpio.h | 411 ---- radio/bootloader/include/stm32f2xx_rcc.h | 515 ----- radio/bootloader/include/stm32f2xx_rtc.h | 650 ------ radio/bootloader/include/stm32f2xx_spi.h | 526 ----- radio/bootloader/stm32f2xx_gpio.c | 566 ----- radio/bootloader/stm32f2xx_rcc.c | 1817 ----------------- radio/bootloader/stm32f2xx_spi.c | 1185 ----------- .../src/stm32f2xx_spi.c | 4 +- 9 files changed, 7 insertions(+), 5676 deletions(-) delete mode 100644 radio/bootloader/include/stm32f2xx_gpio.h delete mode 100644 radio/bootloader/include/stm32f2xx_rcc.h delete mode 100644 radio/bootloader/include/stm32f2xx_rtc.h delete mode 100644 radio/bootloader/include/stm32f2xx_spi.h delete mode 100644 radio/bootloader/stm32f2xx_gpio.c delete mode 100644 radio/bootloader/stm32f2xx_rcc.c delete mode 100644 radio/bootloader/stm32f2xx_spi.c diff --git a/radio/bootloader/Makefile b/radio/bootloader/Makefile index 22b73105f..9971b9d5b 100644 --- a/radio/bootloader/Makefile +++ b/radio/bootloader/Makefile @@ -99,7 +99,8 @@ else CPPDEFS += -DPCBTARANIS FULL_PRJ = $(PROJECT)_ramBoot EXTRAINCDIRS += include -# EXTRAINCDIRS += ../targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include + EXTRAINCDIRS += ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc + EXTRAINCDIRS += ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include endif endif @@ -111,9 +112,9 @@ UADEFS = ifeq ($(PCB), TARANIS) SRC = system_stm32f2xx.c \ - stm32f2xx_rcc.c \ - stm32f2xx_gpio.c \ - stm32f2xx_spi.c \ + ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rcc.c \ + ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_gpio.c \ + ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_spi.c \ misc.c \ ccsbcs.c \ ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/src/usb_core.c \ diff --git a/radio/bootloader/include/stm32f2xx_gpio.h b/radio/bootloader/include/stm32f2xx_gpio.h deleted file mode 100644 index b0c6b5f7c..000000000 --- a/radio/bootloader/include/stm32f2xx_gpio.h +++ /dev/null @@ -1,411 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_gpio.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the GPIO firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_GPIO_H -#define __STM32F2xx_GPIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup GPIO - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ - ((PERIPH) == GPIOB) || \ - ((PERIPH) == GPIOC) || \ - ((PERIPH) == GPIOD) || \ - ((PERIPH) == GPIOE) || \ - ((PERIPH) == GPIOF) || \ - ((PERIPH) == GPIOG) || \ - ((PERIPH) == GPIOH) || \ - ((PERIPH) == GPIOI)) - -/** - * @brief GPIO Configuration Mode enumeration - */ -typedef enum -{ - GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */ - GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */ - GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */ - GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */ -}GPIOMode_TypeDef; -#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \ - ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN)) - -/** - * @brief GPIO Output type enumeration - */ -typedef enum -{ - GPIO_OType_PP = 0x00, - GPIO_OType_OD = 0x01 -}GPIOOType_TypeDef; -#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD)) - - -/** - * @brief GPIO Output Maximum frequency enumeration - */ -typedef enum -{ - GPIO_Speed_2MHz = 0x00, /*!< Low speed */ - GPIO_Speed_25MHz = 0x01, /*!< Medium speed */ - GPIO_Speed_50MHz = 0x02, /*!< Fast speed */ - GPIO_Speed_100MHz = 0x03 /*!< High speed on 30 pF (80 MHz Output max speed on 15 pF) */ -}GPIOSpeed_TypeDef; -#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_2MHz) || ((SPEED) == GPIO_Speed_25MHz) || \ - ((SPEED) == GPIO_Speed_50MHz)|| ((SPEED) == GPIO_Speed_100MHz)) - -/** - * @brief GPIO Configuration PullUp PullDown enumeration - */ -typedef enum -{ - GPIO_PuPd_NOPULL = 0x00, - GPIO_PuPd_UP = 0x01, - GPIO_PuPd_DOWN = 0x02 -}GPIOPuPd_TypeDef; -#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \ - ((PUPD) == GPIO_PuPd_DOWN)) - -/** - * @brief GPIO Bit SET and Bit RESET enumeration - */ -typedef enum -{ - Bit_RESET = 0, - Bit_SET -}BitAction; -#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) - - -/** - * @brief GPIO Init structure definition - */ -typedef struct -{ - uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ - - GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIOMode_TypeDef */ - - GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIOSpeed_TypeDef */ - - GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins. - This parameter can be a value of @ref GPIOOType_TypeDef */ - - GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins. - This parameter can be a value of @ref GPIOPuPd_TypeDef */ -}GPIO_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup GPIO_Exported_Constants - * @{ - */ - -/** @defgroup GPIO_pins_define - * @{ - */ -#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ -#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ -#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ -#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ -#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ -#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ -#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ -#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ -#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ -#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ -#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ -#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ -#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ -#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ -#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ -#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ -#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ - -#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) -#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ - ((PIN) == GPIO_Pin_1) || \ - ((PIN) == GPIO_Pin_2) || \ - ((PIN) == GPIO_Pin_3) || \ - ((PIN) == GPIO_Pin_4) || \ - ((PIN) == GPIO_Pin_5) || \ - ((PIN) == GPIO_Pin_6) || \ - ((PIN) == GPIO_Pin_7) || \ - ((PIN) == GPIO_Pin_8) || \ - ((PIN) == GPIO_Pin_9) || \ - ((PIN) == GPIO_Pin_10) || \ - ((PIN) == GPIO_Pin_11) || \ - ((PIN) == GPIO_Pin_12) || \ - ((PIN) == GPIO_Pin_13) || \ - ((PIN) == GPIO_Pin_14) || \ - ((PIN) == GPIO_Pin_15)) -/** - * @} - */ - - -/** @defgroup GPIO_Pin_sources - * @{ - */ -#define GPIO_PinSource0 ((uint8_t)0x00) -#define GPIO_PinSource1 ((uint8_t)0x01) -#define GPIO_PinSource2 ((uint8_t)0x02) -#define GPIO_PinSource3 ((uint8_t)0x03) -#define GPIO_PinSource4 ((uint8_t)0x04) -#define GPIO_PinSource5 ((uint8_t)0x05) -#define GPIO_PinSource6 ((uint8_t)0x06) -#define GPIO_PinSource7 ((uint8_t)0x07) -#define GPIO_PinSource8 ((uint8_t)0x08) -#define GPIO_PinSource9 ((uint8_t)0x09) -#define GPIO_PinSource10 ((uint8_t)0x0A) -#define GPIO_PinSource11 ((uint8_t)0x0B) -#define GPIO_PinSource12 ((uint8_t)0x0C) -#define GPIO_PinSource13 ((uint8_t)0x0D) -#define GPIO_PinSource14 ((uint8_t)0x0E) -#define GPIO_PinSource15 ((uint8_t)0x0F) - -#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ - ((PINSOURCE) == GPIO_PinSource1) || \ - ((PINSOURCE) == GPIO_PinSource2) || \ - ((PINSOURCE) == GPIO_PinSource3) || \ - ((PINSOURCE) == GPIO_PinSource4) || \ - ((PINSOURCE) == GPIO_PinSource5) || \ - ((PINSOURCE) == GPIO_PinSource6) || \ - ((PINSOURCE) == GPIO_PinSource7) || \ - ((PINSOURCE) == GPIO_PinSource8) || \ - ((PINSOURCE) == GPIO_PinSource9) || \ - ((PINSOURCE) == GPIO_PinSource10) || \ - ((PINSOURCE) == GPIO_PinSource11) || \ - ((PINSOURCE) == GPIO_PinSource12) || \ - ((PINSOURCE) == GPIO_PinSource13) || \ - ((PINSOURCE) == GPIO_PinSource14) || \ - ((PINSOURCE) == GPIO_PinSource15)) -/** - * @} - */ - -/** @defgroup GPIO_Alternat_function_selection_define - * @{ - */ -/** - * @brief AF 0 selection - */ -#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ -#define GPIO_AF_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#define GPIO_AF_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ -#define GPIO_AF_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ -#define GPIO_AF_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ -#define GPIO_AF_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ -#define GPIO_AF_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ -#define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ - -/** - * @brief AF 9 selection - */ -#define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ -#define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ -#define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ -#define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ - -/** - * @brief AF 10 selection - */ -#define GPIO_AF_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */ -#define GPIO_AF_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */ - -/** - * @brief AF 11 selection - */ -#define GPIO_AF_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */ -#define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */ -#define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */ - -/** - * @brief AF 13 selection - */ -#define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ - ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ - ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ - ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ - ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ - ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ - ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ - ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ - ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ - ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ - ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ - ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \ - ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \ - ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \ - ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ - ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_FSMC) || \ - ((AF) == GPIO_AF_OTG_HS_FS) || ((AF) == GPIO_AF_SDIO) || \ - ((AF) == GPIO_AF_DCMI) || ((AF) == GPIO_AF_EVENTOUT)) -/** - * @} - */ - -/** @defgroup GPIO_Legacy - * @{ - */ - -#define GPIO_Mode_AIN GPIO_Mode_AN - -#define GPIO_AF_OTG1_FS GPIO_AF_OTG_FS -#define GPIO_AF_OTG2_HS GPIO_AF_OTG_HS -#define GPIO_AF_OTG2_FS GPIO_AF_OTG_HS_FS - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the GPIO configuration to the default reset state ****/ -void GPIO_DeInit(GPIO_TypeDef* GPIOx); - -/* Initialization and Configuration functions *********************************/ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); - -/* GPIO Read and Write functions **********************************************/ -//uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); -//void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -//void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); -void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); - -/* GPIO Alternate functions configuration function ****************************/ -void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F2xx_GPIO_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/include/stm32f2xx_rcc.h b/radio/bootloader/include/stm32f2xx_rcc.h deleted file mode 100644 index b87733e32..000000000 --- a/radio/bootloader/include/stm32f2xx_rcc.h +++ /dev/null @@ -1,515 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_rcc.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the RCC firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_RCC_H -#define __STM32F2xx_RCC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RCC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -typedef struct -{ - uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */ - uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */ - uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */ - uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */ -}RCC_ClocksTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Constants - * @{ - */ - -/** @defgroup RCC_HSE_configuration - * @{ - */ -#define RCC_HSE_OFF ((uint8_t)0x00) -#define RCC_HSE_ON ((uint8_t)0x01) -#define RCC_HSE_Bypass ((uint8_t)0x05) -#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ - ((HSE) == RCC_HSE_Bypass)) -/** - * @} - */ - -/** @defgroup RCC_PLL_Clock_Source - * @{ - */ -#define RCC_PLLSource_HSI ((uint32_t)0x00000000) -#define RCC_PLLSource_HSE ((uint32_t)0x00400000) -#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \ - ((SOURCE) == RCC_PLLSource_HSE)) -#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63) -#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) -#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) -#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15)) - -#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) -#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source - * @{ - */ -#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) -#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) -#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) -#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ - ((SOURCE) == RCC_SYSCLKSource_HSE) || \ - ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) -/** - * @} - */ - -/** @defgroup RCC_AHB_Clock_Source - * @{ - */ -#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) -#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) -#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) -#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) -#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) -#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) -#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) -#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) -#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) -#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ - ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ - ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ - ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ - ((HCLK) == RCC_SYSCLK_Div512)) -/** - * @} - */ - -/** @defgroup RCC_APB1_APB2_Clock_Source - * @{ - */ -#define RCC_HCLK_Div1 ((uint32_t)0x00000000) -#define RCC_HCLK_Div2 ((uint32_t)0x00001000) -#define RCC_HCLK_Div4 ((uint32_t)0x00001400) -#define RCC_HCLK_Div8 ((uint32_t)0x00001800) -#define RCC_HCLK_Div16 ((uint32_t)0x00001C00) -#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ - ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ - ((PCLK) == RCC_HCLK_Div16)) -/** - * @} - */ - -/** @defgroup RCC_Interrupt_Source - * @{ - */ -#define RCC_IT_LSIRDY ((uint8_t)0x01) -#define RCC_IT_LSERDY ((uint8_t)0x02) -#define RCC_IT_HSIRDY ((uint8_t)0x04) -#define RCC_IT_HSERDY ((uint8_t)0x08) -#define RCC_IT_PLLRDY ((uint8_t)0x10) -#define RCC_IT_PLLI2SRDY ((uint8_t)0x20) -#define RCC_IT_CSS ((uint8_t)0x80) -#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00)) -#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ - ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ - ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ - ((IT) == RCC_IT_PLLI2SRDY)) -#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_LSE_Configuration - * @{ - */ -#define RCC_LSE_OFF ((uint8_t)0x00) -#define RCC_LSE_ON ((uint8_t)0x01) -#define RCC_LSE_Bypass ((uint8_t)0x04) -#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ - ((LSE) == RCC_LSE_Bypass)) -/** - * @} - */ - -/** @defgroup RCC_RTC_Clock_Source - * @{ - */ -#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) -#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) -#define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300) -#define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300) -#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300) -#define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300) -#define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300) -#define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300) -#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300) -#define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300) -#define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300) -#define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300) -#define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300) -#define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300) -#define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300) -#define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300) -#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300) -#define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300) -#define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300) -#define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300) -#define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300) -#define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300) -#define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300) -#define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300) -#define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300) -#define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300) -#define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300) -#define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300) -#define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300) -#define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300) -#define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300) -#define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300) -#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ - ((SOURCE) == RCC_RTCCLKSource_LSI) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div31)) -/** - * @} - */ - -/** @defgroup RCC_I2S_Clock_Source - * @{ - */ -#define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00) -#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01) - -#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext)) -/** - * @} - */ - -/** @defgroup RCC_AHB1_Peripherals - * @{ - */ -#define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001) -#define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002) -#define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004) -#define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008) -#define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010) -#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020) -#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040) -#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080) -#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100) -#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000) -#define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000) -#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000) -#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000) -#define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000) -#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000) -#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000) -#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000) -#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000) -#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000) -#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000) -#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000) -#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000) -#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x819BEE00) == 0x00) && ((PERIPH) != 0x00)) -#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00)) -#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81986E00) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_AHB2_Peripherals - * @{ - */ -#define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001) -#define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010) -#define RCC_AHB2Periph_HASH ((uint32_t)0x00000020) -#define RCC_AHB2Periph_RNG ((uint32_t)0x00000040) -#define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080) -#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_AHB3_Peripherals - * @{ - */ -#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001) -#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_APB1_Peripherals - * @{ - */ -#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) -#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) -#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) -#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) -#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) -#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) -#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) -#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) -#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) -#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) -#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) -#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) -#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) -#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) -#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) -#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) -#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) -#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) -#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000) -#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) -#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) -#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) -#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) -#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC9013600) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_APB2_Peripherals - * @{ - */ -#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001) -#define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002) -#define RCC_APB2Periph_USART1 ((uint32_t)0x00000010) -#define RCC_APB2Periph_USART6 ((uint32_t)0x00000020) -#define RCC_APB2Periph_ADC ((uint32_t)0x00000100) -#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100) -#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200) -#define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400) -#define RCC_APB2Periph_SDIO ((uint32_t)0x00000800) -#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) -#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000) -#define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000) -#define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000) -#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000) -#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A0CC) == 0x00) && ((PERIPH) != 0x00)) -#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A6CC) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_MCO1_Clock_Source_Prescaler - * @{ - */ -#define RCC_MCO1Source_HSI ((uint32_t)0x00000000) -#define RCC_MCO1Source_LSE ((uint32_t)0x00200000) -#define RCC_MCO1Source_HSE ((uint32_t)0x00400000) -#define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000) -#define RCC_MCO1Div_1 ((uint32_t)0x00000000) -#define RCC_MCO1Div_2 ((uint32_t)0x04000000) -#define RCC_MCO1Div_3 ((uint32_t)0x05000000) -#define RCC_MCO1Div_4 ((uint32_t)0x06000000) -#define RCC_MCO1Div_5 ((uint32_t)0x07000000) -#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \ - ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK)) - -#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \ - ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \ - ((DIV) == RCC_MCO1Div_5)) -/** - * @} - */ - -/** @defgroup RCC_MCO2_Clock_Source_Prescaler - * @{ - */ -#define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000) -#define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000) -#define RCC_MCO2Source_HSE ((uint32_t)0x80000000) -#define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000) -#define RCC_MCO2Div_1 ((uint32_t)0x00000000) -#define RCC_MCO2Div_2 ((uint32_t)0x20000000) -#define RCC_MCO2Div_3 ((uint32_t)0x28000000) -#define RCC_MCO2Div_4 ((uint32_t)0x30000000) -#define RCC_MCO2Div_5 ((uint32_t)0x38000000) -#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \ - ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK)) - -#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \ - ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \ - ((DIV) == RCC_MCO2Div_5)) -/** - * @} - */ - -/** @defgroup RCC_Flag - * @{ - */ -#define RCC_FLAG_HSIRDY ((uint8_t)0x21) -#define RCC_FLAG_HSERDY ((uint8_t)0x31) -#define RCC_FLAG_PLLRDY ((uint8_t)0x39) -#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) -#define RCC_FLAG_LSERDY ((uint8_t)0x41) -#define RCC_FLAG_LSIRDY ((uint8_t)0x61) -#define RCC_FLAG_BORRST ((uint8_t)0x79) -#define RCC_FLAG_PINRST ((uint8_t)0x7A) -#define RCC_FLAG_PORRST ((uint8_t)0x7B) -#define RCC_FLAG_SFTRST ((uint8_t)0x7C) -#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) -#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) -#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) -#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ - ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ - ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \ - ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ - ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ - ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \ - ((FLAG) == RCC_FLAG_PLLI2SRDY)) -#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the RCC clock configuration to the default reset state */ -void RCC_DeInit(void); - -/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ -void RCC_HSEConfig(uint8_t RCC_HSE); -ErrorStatus RCC_WaitForHSEStartUp(void); -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); -void RCC_HSICmd(FunctionalState NewState); -void RCC_LSEConfig(uint8_t RCC_LSE); -void RCC_LSICmd(FunctionalState NewState); - -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ); -void RCC_PLLCmd(FunctionalState NewState); -void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR); -void RCC_PLLI2SCmd(FunctionalState NewState); - -void RCC_ClockSecuritySystemCmd(FunctionalState NewState); -void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div); -void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div); - -/* System, AHB and APB busses clocks configuration functions ******************/ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); -uint8_t RCC_GetSYSCLKSource(void); -void RCC_HCLKConfig(uint32_t RCC_SYSCLK); -void RCC_PCLK1Config(uint32_t RCC_HCLK); -void RCC_PCLK2Config(uint32_t RCC_HCLK); -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); - -/* Peripheral clocks configuration functions **********************************/ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); -void RCC_RTCCLKCmd(FunctionalState NewState); -void RCC_BackupResetCmd(FunctionalState NewState); -void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); - -void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); -void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); -void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); - -void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); -void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); -void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); - -void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); -void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); -void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); -void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); -void RCC_ClearFlag(void); -ITStatus RCC_GetITStatus(uint8_t RCC_IT); -void RCC_ClearITPendingBit(uint8_t RCC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F2xx_RCC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/include/stm32f2xx_rtc.h b/radio/bootloader/include/stm32f2xx_rtc.h deleted file mode 100644 index 677f9783b..000000000 --- a/radio/bootloader/include/stm32f2xx_rtc.h +++ /dev/null @@ -1,650 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_rtc.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the RTC firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_RTC_H -#define __STM32F2xx_RTC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -//#include "X9D/stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RTC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief RTC Init structures definition - */ -typedef struct -{ - uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format. - This parameter can be a value of @ref RTC_Hour_Formats */ - - uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. - This parameter must be set to a value lower than 0x7F */ - - uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. - This parameter must be set to a value lower than 0x1FFF */ -}RTC_InitTypeDef; - -/** - * @brief RTC Time structure definition - */ -typedef struct -{ - uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour. - This parameter must be set to a value in the 0-12 range - if the RTC_HourFormat_12 is selected or 0-23 range if - the RTC_HourFormat_24 is selected. */ - - uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes. - This parameter must be set to a value in the 0-59 range. */ - - uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds. - This parameter must be set to a value in the 0-59 range. */ - - uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time. - This parameter can be a value of @ref RTC_AM_PM_Definitions */ -}RTC_TimeTypeDef; - -/** - * @brief RTC Date structure definition - */ -typedef struct -{ - uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay. - This parameter can be a value of @ref RTC_WeekDay_Definitions */ - - uint8_t RTC_Month; /*!< Specifies the RTC Date Month (in BCD format). - This parameter can be a value of @ref RTC_Month_Date_Definitions */ - - uint8_t RTC_Date; /*!< Specifies the RTC Date. - This parameter must be set to a value in the 1-31 range. */ - - uint8_t RTC_Year; /*!< Specifies the RTC Date Year. - This parameter must be set to a value in the 0-99 range. */ -}RTC_DateTypeDef; - -/** - * @brief RTC Alarm structure definition - */ -typedef struct -{ - RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */ - - uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks. - This parameter can be a value of @ref RTC_AlarmMask_Definitions */ - - uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. - This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ - - uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. - If the Alarm Date is selected, this parameter - must be set to a value in the 1-31 range. - If the Alarm WeekDay is selected, this - parameter can be a value of @ref RTC_WeekDay_Definitions */ -}RTC_AlarmTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RTC_Exported_Constants - * @{ - */ - - -/** @defgroup RTC_Hour_Formats - * @{ - */ -#define RTC_HourFormat_24 ((uint32_t)0x00000000) -#define RTC_HourFormat_12 ((uint32_t)0x00000040) -#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \ - ((FORMAT) == RTC_HourFormat_24)) -/** - * @} - */ - -/** @defgroup RTC_Asynchronous_Predivider - * @{ - */ -#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F) - -/** - * @} - */ - - -/** @defgroup RTC_Synchronous_Predivider - * @{ - */ -#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x1FFF) - -/** - * @} - */ - -/** @defgroup RTC_Time_Definitions - * @{ - */ -#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12)) -#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23) -#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59) -#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59) - -/** - * @} - */ - -/** @defgroup RTC_AM_PM_Definitions - * @{ - */ -#define RTC_H12_AM ((uint8_t)0x00) -#define RTC_H12_PM ((uint8_t)0x40) -#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM)) - -/** - * @} - */ - -/** @defgroup RTC_Year_Date_Definitions - * @{ - */ -#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99) - -/** - * @} - */ - -/** @defgroup RTC_Month_Date_Definitions - * @{ - */ - -/* Coded in BCD format */ -#define RTC_Month_January ((uint8_t)0x01) -#define RTC_Month_February ((uint8_t)0x02) -#define RTC_Month_March ((uint8_t)0x03) -#define RTC_Month_April ((uint8_t)0x04) -#define RTC_Month_May ((uint8_t)0x05) -#define RTC_Month_June ((uint8_t)0x06) -#define RTC_Month_July ((uint8_t)0x07) -#define RTC_Month_August ((uint8_t)0x08) -#define RTC_Month_September ((uint8_t)0x09) -#define RTC_Month_October ((uint8_t)0x10) -#define RTC_Month_November ((uint8_t)0x11) -#define RTC_Month_December ((uint8_t)0x12) -#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12)) -#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31)) - -/** - * @} - */ - -/** @defgroup RTC_WeekDay_Definitions - * @{ - */ - -#define RTC_Weekday_Monday ((uint8_t)0x01) -#define RTC_Weekday_Tuesday ((uint8_t)0x02) -#define RTC_Weekday_Wednesday ((uint8_t)0x03) -#define RTC_Weekday_Thursday ((uint8_t)0x04) -#define RTC_Weekday_Friday ((uint8_t)0x05) -#define RTC_Weekday_Saturday ((uint8_t)0x06) -#define RTC_Weekday_Sunday ((uint8_t)0x07) -#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ - ((WEEKDAY) == RTC_Weekday_Tuesday) || \ - ((WEEKDAY) == RTC_Weekday_Wednesday) || \ - ((WEEKDAY) == RTC_Weekday_Thursday) || \ - ((WEEKDAY) == RTC_Weekday_Friday) || \ - ((WEEKDAY) == RTC_Weekday_Saturday) || \ - ((WEEKDAY) == RTC_Weekday_Sunday)) -/** - * @} - */ - - -/** @defgroup RTC_Alarm_Definitions - * @{ - */ -#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31)) -#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ - ((WEEKDAY) == RTC_Weekday_Tuesday) || \ - ((WEEKDAY) == RTC_Weekday_Wednesday) || \ - ((WEEKDAY) == RTC_Weekday_Thursday) || \ - ((WEEKDAY) == RTC_Weekday_Friday) || \ - ((WEEKDAY) == RTC_Weekday_Saturday) || \ - ((WEEKDAY) == RTC_Weekday_Sunday)) - -/** - * @} - */ - - -/** @defgroup RTC_AlarmDateWeekDay_Definitions - * @{ - */ -#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000) -#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000) - -#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \ - ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay)) - -/** - * @} - */ - - -/** @defgroup RTC_AlarmMask_Definitions - * @{ - */ -#define RTC_AlarmMask_None ((uint32_t)0x00000000) -#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000) -#define RTC_AlarmMask_Hours ((uint32_t)0x00800000) -#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000) -#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080) -#define RTC_AlarmMask_All ((uint32_t)0x80808080) -#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) - -/** - * @} - */ - -/** @defgroup RTC_Alarms_Definitions - * @{ - */ -#define RTC_Alarm_A ((uint32_t)0x00000100) -#define RTC_Alarm_B ((uint32_t)0x00000200) -#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B)) -#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET) - -/** - * @} - */ - -/** @defgroup RTC_Wakeup_Timer_Definitions - * @{ - */ -#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000) -#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001) -#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002) -#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003) -#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004) -#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006) -#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \ - ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \ - ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \ - ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \ - ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \ - ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits)) -#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) -/** - * @} - */ - -/** @defgroup RTC_Time_Stamp_Edges_definitions - * @{ - */ -#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000) -#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008) -#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \ - ((EDGE) == RTC_TimeStampEdge_Falling)) -/** - * @} - */ - -/** @defgroup RTC_Output_selection_Definitions - * @{ - */ -#define RTC_Output_Disable ((uint32_t)0x00000000) -#define RTC_Output_AlarmA ((uint32_t)0x00200000) -#define RTC_Output_AlarmB ((uint32_t)0x00400000) -#define RTC_Output_WakeUp ((uint32_t)0x00600000) - -#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \ - ((OUTPUT) == RTC_Output_AlarmA) || \ - ((OUTPUT) == RTC_Output_AlarmB) || \ - ((OUTPUT) == RTC_Output_WakeUp)) - -/** - * @} - */ - -/** @defgroup RTC_Output_Polarity_Definitions - * @{ - */ -#define RTC_OutputPolarity_High ((uint32_t)0x00000000) -#define RTC_OutputPolarity_Low ((uint32_t)0x00100000) -#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \ - ((POL) == RTC_OutputPolarity_Low)) -/** - * @} - */ - - -/** @defgroup RTC_Digital_Calibration_Definitions - * @{ - */ -#define RTC_CalibSign_Positive ((uint32_t)0x00000000) -#define RTC_CalibSign_Negative ((uint32_t)0x00000080) -#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \ - ((SIGN) == RTC_CalibSign_Negative)) -#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20) - -/** - * @} - */ - - -/** @defgroup RTC_DayLightSaving_Definitions - * @{ - */ -#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000) -#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000) -#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \ - ((SAVE) == RTC_DayLightSaving_ADD1H)) - -#define RTC_StoreOperation_Reset ((uint32_t)0x00000000) -#define RTC_StoreOperation_Set ((uint32_t)0x00040000) -#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \ - ((OPERATION) == RTC_StoreOperation_Set)) -/** - * @} - */ - -/** @defgroup RTC_Tamper_Trigger_Definitions - * @{ - */ -#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000) -#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001) -#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \ - ((TRIGGER) == RTC_TamperTrigger_FallingEdge)) - -/** - * @} - */ - -/** @defgroup RTC_Tamper_Pins_Definitions - * @{ - */ -#define RTC_Tamper_1 RTC_TAFCR_TAMP1E -#define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1)) - -/** - * @} - */ - -/** @defgroup RTC_Tamper_Pin_Selection - * @{ - */ -#define RTC_TamperPin_PC13 ((uint32_t)0x00000000) -#define RTC_TamperPin_PI8 ((uint32_t)0x00010000) -#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TamperPin_PC13) || \ - ((PIN) == RTC_TamperPin_PI8)) -/** - * @} - */ - -/** @defgroup RTC_TimeStamp_Pin_Selection - * @{ - */ -#define RTC_TimeStampPin_PC13 ((uint32_t)0x00000000) -#define RTC_TimeStampPin_PI8 ((uint32_t)0x00020000) -#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TimeStampPin_PC13) || \ - ((PIN) == RTC_TimeStampPin_PI8)) -/** - * @} - */ - -/** @defgroup RTC_Output_Type_ALARM_OUT - * @{ - */ -#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000) -#define RTC_OutputType_PushPull ((uint32_t)0x00040000) -#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \ - ((TYPE) == RTC_OutputType_PushPull)) - -/** - * @} - */ - -/** @defgroup RTC_Backup_Registers_Definitions - * @{ - */ - -#define RTC_BKP_DR0 ((uint32_t)0x00000000) -#define RTC_BKP_DR1 ((uint32_t)0x00000001) -#define RTC_BKP_DR2 ((uint32_t)0x00000002) -#define RTC_BKP_DR3 ((uint32_t)0x00000003) -#define RTC_BKP_DR4 ((uint32_t)0x00000004) -#define RTC_BKP_DR5 ((uint32_t)0x00000005) -#define RTC_BKP_DR6 ((uint32_t)0x00000006) -#define RTC_BKP_DR7 ((uint32_t)0x00000007) -#define RTC_BKP_DR8 ((uint32_t)0x00000008) -#define RTC_BKP_DR9 ((uint32_t)0x00000009) -#define RTC_BKP_DR10 ((uint32_t)0x0000000A) -#define RTC_BKP_DR11 ((uint32_t)0x0000000B) -#define RTC_BKP_DR12 ((uint32_t)0x0000000C) -#define RTC_BKP_DR13 ((uint32_t)0x0000000D) -#define RTC_BKP_DR14 ((uint32_t)0x0000000E) -#define RTC_BKP_DR15 ((uint32_t)0x0000000F) -#define RTC_BKP_DR16 ((uint32_t)0x00000010) -#define RTC_BKP_DR17 ((uint32_t)0x00000011) -#define RTC_BKP_DR18 ((uint32_t)0x00000012) -#define RTC_BKP_DR19 ((uint32_t)0x00000013) -#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \ - ((BKP) == RTC_BKP_DR1) || \ - ((BKP) == RTC_BKP_DR2) || \ - ((BKP) == RTC_BKP_DR3) || \ - ((BKP) == RTC_BKP_DR4) || \ - ((BKP) == RTC_BKP_DR5) || \ - ((BKP) == RTC_BKP_DR6) || \ - ((BKP) == RTC_BKP_DR7) || \ - ((BKP) == RTC_BKP_DR8) || \ - ((BKP) == RTC_BKP_DR9) || \ - ((BKP) == RTC_BKP_DR10) || \ - ((BKP) == RTC_BKP_DR11) || \ - ((BKP) == RTC_BKP_DR12) || \ - ((BKP) == RTC_BKP_DR13) || \ - ((BKP) == RTC_BKP_DR14) || \ - ((BKP) == RTC_BKP_DR15) || \ - ((BKP) == RTC_BKP_DR16) || \ - ((BKP) == RTC_BKP_DR17) || \ - ((BKP) == RTC_BKP_DR18) || \ - ((BKP) == RTC_BKP_DR19)) -/** - * @} - */ - -/** @defgroup RTC_Input_parameter_format_definitions - * @{ - */ -#define RTC_Format_BIN ((uint32_t)0x000000000) -#define RTC_Format_BCD ((uint32_t)0x000000001) -#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD)) - -/** - * @} - */ - -/** @defgroup RTC_Flags_Definitions - * @{ - */ -#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000) -#define RTC_FLAG_TSOVF ((uint32_t)0x00001000) -#define RTC_FLAG_TSF ((uint32_t)0x00000800) -#define RTC_FLAG_WUTF ((uint32_t)0x00000400) -#define RTC_FLAG_ALRBF ((uint32_t)0x00000200) -#define RTC_FLAG_ALRAF ((uint32_t)0x00000100) -#define RTC_FLAG_INITF ((uint32_t)0x00000040) -#define RTC_FLAG_RSF ((uint32_t)0x00000020) -#define RTC_FLAG_INITS ((uint32_t)0x00000010) -#define RTC_FLAG_WUTWF ((uint32_t)0x00000004) -#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002) -#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001) -#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \ - ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \ - ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \ - ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \ - ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \ - ((FLAG) == RTC_FLAG_TAMP1F)) -#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFFC0DF) == (uint32_t)RESET)) - -/** - * @} - */ - -/** @defgroup RTC_Interrupts_Definitions - * @{ - */ -#define RTC_IT_TS ((uint32_t)0x00008000) -#define RTC_IT_WUT ((uint32_t)0x00004000) -#define RTC_IT_ALRB ((uint32_t)0x00002000) -#define RTC_IT_ALRA ((uint32_t)0x00001000) -#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */ -#define RTC_IT_TAMP1 ((uint32_t)0x00020000) - -#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET)) -#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \ - ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \ - ((IT) == RTC_IT_TAMP1)) -#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFD0FFF) == (uint32_t)RESET)) - -/** - * @} - */ - -/** @defgroup RTC_Legacy - * @{ - */ -#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig -#define RTC_DigitalCalibCmd RTC_CoarseCalibCmd - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the RTC configuration to the default reset state *****/ -ErrorStatus RTC_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct); -void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct); -void RTC_WriteProtectionCmd(FunctionalState NewState); -ErrorStatus RTC_EnterInitMode(void); -void RTC_ExitInitMode(void); -ErrorStatus RTC_WaitForSynchro(void); -ErrorStatus RTC_RefClockCmd(FunctionalState NewState); - -/* Time and Date configuration functions **************************************/ -ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); -void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct); -void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); -ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); -void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct); -void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); - -/* Alarms (Alarm A and Alarm B) configuration functions **********************/ -void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); -void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct); -void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); -ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState); - -/* WakeUp Timer configuration functions ***************************************/ -void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock); -void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter); -uint32_t RTC_GetWakeUpCounter(void); -ErrorStatus RTC_WakeUpCmd(FunctionalState NewState); - -/* Daylight Saving configuration functions ************************************/ -void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation); -uint32_t RTC_GetStoreOperation(void); - -/* Output pin Configuration function ******************************************/ -void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity); - -/* Coarse Calibration configuration functions *********************************/ -ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value); -ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState); -void RTC_CalibOutputCmd(FunctionalState NewState); - -/* TimeStamp configuration functions ******************************************/ -void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState); -void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, - RTC_DateTypeDef* RTC_StampDateStruct); - -/* Tampers configuration functions ********************************************/ -void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger); -void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState); - -/* Backup Data Registers configuration functions ******************************/ -void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data); -uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR); - -/* RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration - functions ******************************************************************/ -void RTC_TamperPinSelection(uint32_t RTC_TamperPin); -void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin); -void RTC_OutputTypeConfig(uint32_t RTC_OutputType); - -/* Interrupts and flags management functions **********************************/ -void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState); -FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG); -void RTC_ClearFlag(uint32_t RTC_FLAG); -ITStatus RTC_GetITStatus(uint32_t RTC_IT); -void RTC_ClearITPendingBit(uint32_t RTC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F2xx_RTC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/include/stm32f2xx_spi.h b/radio/bootloader/include/stm32f2xx_spi.h deleted file mode 100644 index 7a56a23f9..000000000 --- a/radio/bootloader/include/stm32f2xx_spi.h +++ /dev/null @@ -1,526 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_spi.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the SPI - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_SPI_H -#define __STM32F2xx_SPI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -//#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SPI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief SPI Init structure definition - */ - -typedef struct -{ - uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. - This parameter can be a value of @ref SPI_data_direction */ - - uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. - This parameter can be a value of @ref SPI_mode */ - - uint16_t SPI_DataSize; /*!< Specifies the SPI data size. - This parameter can be a value of @ref SPI_data_size */ - - uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_Clock_Polarity */ - - uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. - This parameter can be a value of @ref SPI_Clock_Phase */ - - uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by - hardware (NSS pin) or by software using the SSI bit. - This parameter can be a value of @ref SPI_Slave_Select_management */ - - uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be - used to configure the transmit and receive SCK clock. - This parameter can be a value of @ref SPI_BaudRate_Prescaler - @note The communication clock is derived from the master - clock. The slave clock does not need to be set. */ - - uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SPI_MSB_LSB_transmission */ - - uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ -}SPI_InitTypeDef; - -/** - * @brief I2S Init structure definition - */ - -typedef struct -{ - - uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. - This parameter can be a value of @ref I2S_Mode */ - - uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. - This parameter can be a value of @ref I2S_Standard */ - - uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. - This parameter can be a value of @ref I2S_Data_Format */ - - uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. - This parameter can be a value of @ref I2S_MCLK_Output */ - - uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. - This parameter can be a value of @ref I2S_Audio_Frequency */ - - uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. - This parameter can be a value of @ref I2S_Clock_Polarity */ -}I2S_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SPI_Exported_Constants - * @{ - */ - -#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ - ((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3)) - -#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3)) - -/** @defgroup SPI_data_direction - * @{ - */ - -#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) -#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) -#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) -#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) -#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ - ((MODE) == SPI_Direction_2Lines_RxOnly) || \ - ((MODE) == SPI_Direction_1Line_Rx) || \ - ((MODE) == SPI_Direction_1Line_Tx)) -/** - * @} - */ - -/** @defgroup SPI_mode - * @{ - */ - -#define SPI_Mode_Master ((uint16_t)0x0104) -#define SPI_Mode_Slave ((uint16_t)0x0000) -#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ - ((MODE) == SPI_Mode_Slave)) -/** - * @} - */ - -/** @defgroup SPI_data_size - * @{ - */ - -#define SPI_DataSize_16b ((uint16_t)0x0800) -#define SPI_DataSize_8b ((uint16_t)0x0000) -#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ - ((DATASIZE) == SPI_DataSize_8b)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Polarity - * @{ - */ - -#define SPI_CPOL_Low ((uint16_t)0x0000) -#define SPI_CPOL_High ((uint16_t)0x0002) -#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ - ((CPOL) == SPI_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Phase - * @{ - */ - -#define SPI_CPHA_1Edge ((uint16_t)0x0000) -#define SPI_CPHA_2Edge ((uint16_t)0x0001) -#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ - ((CPHA) == SPI_CPHA_2Edge)) -/** - * @} - */ - -/** @defgroup SPI_Slave_Select_management - * @{ - */ - -#define SPI_NSS_Soft ((uint16_t)0x0200) -#define SPI_NSS_Hard ((uint16_t)0x0000) -#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ - ((NSS) == SPI_NSS_Hard)) -/** - * @} - */ - -/** @defgroup SPI_BaudRate_Prescaler - * @{ - */ - -#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) -#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) -#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) -#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) -#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) -#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) -#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) -#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) -#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_256)) -/** - * @} - */ - -/** @defgroup SPI_MSB_LSB_transmission - * @{ - */ - -#define SPI_FirstBit_MSB ((uint16_t)0x0000) -#define SPI_FirstBit_LSB ((uint16_t)0x0080) -#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ - ((BIT) == SPI_FirstBit_LSB)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Mode - * @{ - */ - -#define I2S_Mode_SlaveTx ((uint16_t)0x0000) -#define I2S_Mode_SlaveRx ((uint16_t)0x0100) -#define I2S_Mode_MasterTx ((uint16_t)0x0200) -#define I2S_Mode_MasterRx ((uint16_t)0x0300) -#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ - ((MODE) == I2S_Mode_SlaveRx) || \ - ((MODE) == I2S_Mode_MasterTx)|| \ - ((MODE) == I2S_Mode_MasterRx)) -/** - * @} - */ - - -/** @defgroup SPI_I2S_Standard - * @{ - */ - -#define I2S_Standard_Phillips ((uint16_t)0x0000) -#define I2S_Standard_MSB ((uint16_t)0x0010) -#define I2S_Standard_LSB ((uint16_t)0x0020) -#define I2S_Standard_PCMShort ((uint16_t)0x0030) -#define I2S_Standard_PCMLong ((uint16_t)0x00B0) -#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ - ((STANDARD) == I2S_Standard_MSB) || \ - ((STANDARD) == I2S_Standard_LSB) || \ - ((STANDARD) == I2S_Standard_PCMShort) || \ - ((STANDARD) == I2S_Standard_PCMLong)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Data_Format - * @{ - */ - -#define I2S_DataFormat_16b ((uint16_t)0x0000) -#define I2S_DataFormat_16bextended ((uint16_t)0x0001) -#define I2S_DataFormat_24b ((uint16_t)0x0003) -#define I2S_DataFormat_32b ((uint16_t)0x0005) -#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ - ((FORMAT) == I2S_DataFormat_16bextended) || \ - ((FORMAT) == I2S_DataFormat_24b) || \ - ((FORMAT) == I2S_DataFormat_32b)) -/** - * @} - */ - -/** @defgroup SPI_I2S_MCLK_Output - * @{ - */ - -#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) -#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) -#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ - ((OUTPUT) == I2S_MCLKOutput_Disable)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Audio_Frequency - * @{ - */ - -#define I2S_AudioFreq_192k ((uint32_t)192000) -#define I2S_AudioFreq_96k ((uint32_t)96000) -#define I2S_AudioFreq_48k ((uint32_t)48000) -#define I2S_AudioFreq_44k ((uint32_t)44100) -#define I2S_AudioFreq_32k ((uint32_t)32000) -#define I2S_AudioFreq_22k ((uint32_t)22050) -#define I2S_AudioFreq_16k ((uint32_t)16000) -#define I2S_AudioFreq_11k ((uint32_t)11025) -#define I2S_AudioFreq_8k ((uint32_t)8000) -#define I2S_AudioFreq_Default ((uint32_t)2) - -#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ - ((FREQ) <= I2S_AudioFreq_192k)) || \ - ((FREQ) == I2S_AudioFreq_Default)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Clock_Polarity - * @{ - */ - -#define I2S_CPOL_Low ((uint16_t)0x0000) -#define I2S_CPOL_High ((uint16_t)0x0008) -#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ - ((CPOL) == I2S_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_I2S_DMA_transfer_requests - * @{ - */ - -#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) -#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) -#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) -/** - * @} - */ - -/** @defgroup SPI_NSS_internal_software_management - * @{ - */ - -#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) -#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) -#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ - ((INTERNAL) == SPI_NSSInternalSoft_Reset)) -/** - * @} - */ - -/** @defgroup SPI_CRC_Transmit_Receive - * @{ - */ - -#define SPI_CRC_Tx ((uint8_t)0x00) -#define SPI_CRC_Rx ((uint8_t)0x01) -#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) -/** - * @} - */ - -/** @defgroup SPI_direction_transmit_receive - * @{ - */ - -#define SPI_Direction_Rx ((uint16_t)0xBFFF) -#define SPI_Direction_Tx ((uint16_t)0x4000) -#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ - ((DIRECTION) == SPI_Direction_Tx)) -/** - * @} - */ - -/** @defgroup SPI_I2S_interrupts_definition - * @{ - */ - -#define SPI_I2S_IT_TXE ((uint8_t)0x71) -#define SPI_I2S_IT_RXNE ((uint8_t)0x60) -#define SPI_I2S_IT_ERR ((uint8_t)0x50) -#define I2S_IT_UDR ((uint8_t)0x53) -#define SPI_I2S_IT_TIFRFE ((uint8_t)0x58) - -#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == SPI_I2S_IT_RXNE) || \ - ((IT) == SPI_I2S_IT_ERR)) - -#define SPI_I2S_IT_OVR ((uint8_t)0x56) -#define SPI_IT_MODF ((uint8_t)0x55) -#define SPI_IT_CRCERR ((uint8_t)0x54) - -#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) - -#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE)|| ((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \ - ((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\ - ((IT) == SPI_I2S_IT_TIFRFE)) -/** - * @} - */ - -/** @defgroup SPI_I2S_flags_definition - * @{ - */ - -#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) -#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) -#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) -#define I2S_FLAG_UDR ((uint16_t)0x0008) -#define SPI_FLAG_CRCERR ((uint16_t)0x0010) -#define SPI_FLAG_MODF ((uint16_t)0x0020) -#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) -#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) -#define SPI_I2S_FLAG_TIFRFE ((uint16_t)0x0100) - -#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) -#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ - ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ - ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ - ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \ - ((FLAG) == SPI_I2S_FLAG_TIFRFE)) -/** - * @} - */ - -/** @defgroup SPI_CRC_polynomial - * @{ - */ - -#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) -/** - * @} - */ - -/** @defgroup SPI_I2S_Legacy - * @{ - */ - -#define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx -#define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx -#define SPI_IT_TXE SPI_I2S_IT_TXE -#define SPI_IT_RXNE SPI_I2S_IT_RXNE -#define SPI_IT_ERR SPI_I2S_IT_ERR -#define SPI_IT_OVR SPI_I2S_IT_OVR -#define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE -#define SPI_FLAG_TXE SPI_I2S_FLAG_TXE -#define SPI_FLAG_OVR SPI_I2S_FLAG_OVR -#define SPI_FLAG_BSY SPI_I2S_FLAG_BSY -#define SPI_DeInit SPI_I2S_DeInit -#define SPI_ITConfig SPI_I2S_ITConfig -#define SPI_DMACmd SPI_I2S_DMACmd -#define SPI_SendData SPI_I2S_SendData -#define SPI_ReceiveData SPI_I2S_ReceiveData -#define SPI_GetFlagStatus SPI_I2S_GetFlagStatus -#define SPI_ClearFlag SPI_I2S_ClearFlag -#define SPI_GetITStatus SPI_I2S_GetITStatus -#define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the SPI configuration to the default reset state *****/ -void SPI_I2S_DeInit(SPI_TypeDef* SPIx); - -/* Initialization and Configuration functions *********************************/ -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); -void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); -void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); - -/* Data transfers functions ***************************************************/ -void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); - -/* Hardware CRC Calculation functions *****************************************/ -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_TransmitCRC(SPI_TypeDef* SPIx); -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); - -/* DMA transfers management functions *****************************************/ -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); -void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F2xx_SPI_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/stm32f2xx_gpio.c b/radio/bootloader/stm32f2xx_gpio.c deleted file mode 100644 index c53371e3d..000000000 --- a/radio/bootloader/stm32f2xx_gpio.c +++ /dev/null @@ -1,566 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_gpio.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the GPIO peripheral: - * - Initialization and Configuration - * - GPIO Read and Write - * - GPIO Alternate functions configuration - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable the GPIO AHB clock using the following function - * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - * - * 2. Configure the GPIO pin(s) using GPIO_Init() - * Four possible configuration are available for each pin: - * - Input: Floating, Pull-up, Pull-down. - * - Output: Push-Pull (Pull-up, Pull-down or no Pull) - * Open Drain (Pull-up, Pull-down or no Pull). - * In output mode, the speed is configurable: 2 MHz, 25 MHz, - * 50 MHz or 100 MHz. - * - Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) - * Open Drain (Pull-up, Pull-down or no Pull). - * - Analog: required mode when a pin is to be used as ADC channel - * or DAC output. - * - * 3- Peripherals alternate function: - * - For ADC and DAC, configure the desired pin in analog mode using - * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN; - * - For other peripherals (TIM, USART...): - * - Connect the pin to the desired peripherals' Alternate - * Function (AF) using GPIO_PinAFConfig() function - * - Configure the desired pin in alternate function mode using - * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - * - Select the type, pull-up/pull-down and output speed via - * GPIO_PuPd, GPIO_OType and GPIO_Speed members - * - Call GPIO_Init() function - * - * 4. To get the level of a pin configured in input mode use GPIO_ReadInputDataBit() - * - * 5. To set/reset the level of a pin configured in output mode use - * GPIO_SetBits()/GPIO_ResetBits() - * - * 6. During and just after reset, the alternate functions are not - * active and the GPIO pins are configured in input floating mode - * (except JTAG pins). - * - * 7. The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as - * general-purpose (PC14 and PC15, respectively) when the LSE - * oscillator is off. The LSE has priority over the GPIO function. - * - * 8. The HSE oscillator pins OSC_IN/OSC_OUT can be used as - * general-purpose PH0 and PH1, respectively, when the HSE - * oscillator is off. The HSE has priority over the GPIO function. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_gpio.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup GPIO - * @brief GPIO driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup GPIO_Private_Functions - * @{ - */ - -/** @defgroup GPIO_Group1 Initialization and Configuration - * @brief Initialization and Configuration - * -@verbatim - =============================================================================== - Initialization and Configuration - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the GPIOx peripheral registers to their default reset values. - * @note By default, The GPIO pins are configured in input floating mode (except JTAG pins). - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @retval None - */ -void GPIO_DeInit(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - if (GPIOx == GPIOA) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE); - } - else if (GPIOx == GPIOB) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE); - } - else if (GPIOx == GPIOC) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE); - } - else if (GPIOx == GPIOD) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE); - } - else if (GPIOx == GPIOE) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE); - } - else if (GPIOx == GPIOF) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE); - } - else if (GPIOx == GPIOG) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE); - } - else if (GPIOx == GPIOH) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE); - } - else - { - if (GPIOx == GPIOI) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE); - } - } -} - -/** - * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains - * the configuration information for the specified GPIO peripheral. - * @retval None - */ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) -{ - uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); - assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); - assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); - - /* -------------------------Configure the port pins---------------- */ - /*-- GPIO Mode Configuration --*/ - for (pinpos = 0x00; pinpos < 0x10; pinpos++) - { - pos = ((uint32_t)0x01) << pinpos; - /* Get the port pins position */ - currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; - - if (currentpin == pos) - { - GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2)); - GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2)); - - if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF)) - { - /* Check Speed mode parameters */ - assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); - - /* Speed mode configuration */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2)); - GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2)); - - /* Check Output mode parameters */ - assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType)); - - /* Output mode configuration*/ - GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ; - GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos)); - } - - /* Pull-up Pull down resistor configuration*/ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2)); - GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2)); - } - } -} - -/** - * @brief Fills each GPIO_InitStruct member with its default value. - * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized. - * @retval None - */ -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) -{ - /* Reset GPIO init structure parameters values */ - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStruct->GPIO_OType = GPIO_OType_PP; - GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL; -} - -/** - * @brief Locks GPIO Pins configuration registers. - * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, - * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. - * @note The configuration of the locked GPIO pins can no longer be modified - * until the next reset. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be locked. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - __IO uint32_t tmp = 0x00010000; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - tmp |= GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Reset LCKK bit */ - GPIOx->LCKR = GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; -} - -/** - * @} - */ - -/** @defgroup GPIO_Group2 GPIO Read and Write - * @brief GPIO Read and Write - * -@verbatim - =============================================================================== - GPIO Read and Write - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Reads the specified input port pin. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * @retval The input port pin value. - */ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO input data port. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @retval GPIO input data port value. - */ -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->IDR); -} - -/** - * @brief Reads the specified output data port bit. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * @retval The output port pin value. - */ -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO output data port. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @retval GPIO output data port value. - */ -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->ODR); -} - -/** - * @brief Sets the selected data port bits. - * @note This functions uses GPIOx_BSRR register to allow atomic read/modify - * accesses. In this way, there is no risk of an IRQ occurring between - * the read and the modify access. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BSRRL = GPIO_Pin; -} - -/** - * @brief Clears the selected data port bits. - * @note This functions uses GPIOx_BSRR register to allow atomic read/modify - * accesses. In this way, there is no risk of an IRQ occurring between - * the read and the modify access. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BSRRH = GPIO_Pin; -} - -/** - * @brief Sets or clears the selected data port bit. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be one of GPIO_Pin_x where x can be (0..15). - * @param BitVal: specifies the value to be written to the selected bit. - * This parameter can be one of the BitAction enum values: - * @arg Bit_RESET: to clear the port pin - * @arg Bit_SET: to set the port pin - * @retval None - */ -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_BIT_ACTION(BitVal)); - - if (BitVal != Bit_RESET) - { - GPIOx->BSRRL = GPIO_Pin; - } - else - { - GPIOx->BSRRH = GPIO_Pin ; - } -} - -/** - * @brief Writes data to the specified GPIO data port. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param PortVal: specifies the value to be written to the port output data register. - * @retval None - */ -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - GPIOx->ODR = PortVal; -} - -/** - * @brief Toggles the specified GPIO pins.. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: Specifies the pins to be toggled. - * @retval None - */ -void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - GPIOx->ODR ^= GPIO_Pin; -} - -/** - * @} - */ - -/** @defgroup GPIO_Group3 GPIO Alternate functions configuration function - * @brief GPIO Alternate functions configuration function - * -@verbatim - =============================================================================== - GPIO Alternate functions configuration function - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Changes the mapping of the specified pin. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_PinSource: specifies the pin for the Alternate function. - * This parameter can be GPIO_PinSourcex where x can be (0..15). - * @param GPIO_AFSelection: selects the pin to used as Alternate function. - * This parameter can be one of the following values: - * @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset) - * @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset) - * @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset) - * @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset) - * @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset) - * @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1 - * @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1 - * @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2 - * @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2 - * @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2 - * @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3 - * @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3 - * @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3 - * @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3 - * @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4 - * @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4 - * @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4 - * @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5 - * @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5 - * @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6 - * @arg GPIO_AF_USART1: Connect USART1 pins to AF7 - * @arg GPIO_AF_USART2: Connect USART2 pins to AF7 - * @arg GPIO_AF_USART3: Connect USART3 pins to AF7 - * @arg GPIO_AF_UART4: Connect UART4 pins to AF8 - * @arg GPIO_AF_UART5: Connect UART5 pins to AF8 - * @arg GPIO_AF_USART6: Connect USART6 pins to AF8 - * @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9 - * @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9 - * @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9 - * @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9 - * @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9 - * @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10 - * @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10 - * @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11 - * @arg GPIO_AF_FSMC: Connect FSMC pins to AF12 - * @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12 - * @arg GPIO_AF_SDIO: Connect SDIO pins to AF12 - * @arg GPIO_AF_DCMI: Connect DCMI pins to AF13 - * @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15 - * @retval None - */ -void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF) -{ - uint32_t temp = 0x00; - uint32_t temp_2 = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); - assert_param(IS_GPIO_AF(GPIO_AF)); - - temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; - GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; - temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp; - GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/stm32f2xx_rcc.c b/radio/bootloader/stm32f2xx_rcc.c deleted file mode 100644 index 0376f7f55..000000000 --- a/radio/bootloader/stm32f2xx_rcc.c +++ /dev/null @@ -1,1817 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_rcc.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the Reset and clock control (RCC) peripheral: - * - Internal/external clocks, PLL, CSS and MCO configuration - * - System, AHB and APB busses clocks configuration - * - Peripheral clocks configuration - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * RCC specific features - * =================================================================== - * - * After reset the device is running from Internal High Speed oscillator - * (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache - * and I-Cache are disabled, and all peripherals are off except internal - * SRAM, Flash and JTAG. - * - There is no prescaler on High speed (AHB) and Low speed (APB) busses; - * all peripherals mapped on these busses are running at HSI speed. - * - The clock for all peripherals is switched off, except the SRAM and FLASH. - * - All GPIOs are in input floating state, except the JTAG pins which - * are assigned to be used for debug purpose. - * - * Once the device started from reset, the user application has to: - * - Configure the clock source to be used to drive the System clock - * (if the application needs higher frequency/performance) - * - Configure the System clock frequency and Flash settings - * - Configure the AHB and APB busses prescalers - * - Enable the clock for the peripheral(s) to be used - * - Configure the clock source(s) for peripherals which clocks are not - * derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup RCC - * @brief RCC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* ------------ RCC registers bit address in the alias region ----------- */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) -/* --- CR Register ---*/ -/* Alias word address of HSION bit */ -#define CR_OFFSET (RCC_OFFSET + 0x00) -#define HSION_BitNumber 0x00 -#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) -/* Alias word address of CSSON bit */ -#define CSSON_BitNumber 0x13 -#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) -/* Alias word address of PLLON bit */ -#define PLLON_BitNumber 0x18 -#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) -/* Alias word address of PLLI2SON bit */ -#define PLLI2SON_BitNumber 0x1A -#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4)) - -/* --- CFGR Register ---*/ -/* Alias word address of I2SSRC bit */ -#define CFGR_OFFSET (RCC_OFFSET + 0x08) -#define I2SSRC_BitNumber 0x17 -#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4)) - -/* --- BDCR Register ---*/ -/* Alias word address of RTCEN bit */ -#define BDCR_OFFSET (RCC_OFFSET + 0x70) -#define RTCEN_BitNumber 0x0F -#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) -/* Alias word address of BDRST bit */ -#define BDRST_BitNumber 0x10 -#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) -/* --- CSR Register ---*/ -/* Alias word address of LSION bit */ -#define CSR_OFFSET (RCC_OFFSET + 0x74) -#define LSION_BitNumber 0x00 -#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) -/* ---------------------- RCC registers bit mask ------------------------ */ -/* CFGR register bit mask */ -#define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF) -#define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF) - -/* RCC Flag Mask */ -#define FLAG_MASK ((uint8_t)0x1F) - -/* CR register byte 3 (Bits[23:16]) base address */ -#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802) - -/* CIR register byte 2 (Bits[15:8]) base address */ -#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01)) - -/* CIR register byte 3 (Bits[23:16]) base address */ -#define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) - -/* BDCR register base address */ -#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RCC_Private_Functions - * @{ - */ - -/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions - * @brief Internal and external clocks, PLL, CSS and MCO configuration functions - * -@verbatim - =============================================================================== - Internal/external clocks, PLL, CSS and MCO configuration functions - =============================================================================== - - This section provide functions allowing to configure the internal/external clocks, - PLLs, CSS and MCO pins. - - 1. HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through - the PLL as System clock source. - - 2. LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC - clock source. - - 3. HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or - through the PLL as System clock source. Can be used also as RTC clock source. - - 4. LSE (low-speed external), 32 KHz oscillator used as RTC clock source. - - 5. PLL (clocked by HSI or HSE), featuring two different output clocks: - - The first output is used to generate the high speed system clock (up to 120 MHz) - - The second output is used to generate the clock for the USB OTG FS (48 MHz), - the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). - - 6. PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve - high-quality audio performance on the I2S interface. - - 7. CSS (Clock security system), once enable and if a HSE clock failure occurs - (HSE used directly or through PLL as System clock source), the System clock - is automatically switched to HSI and an interrupt is generated if enabled. - The interrupt is linked to the Cortex-M3 NMI (Non-Maskable Interrupt) - exception vector. - - 8. MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL - clock (through a configurable prescaler) on PA8 pin. - - 9. MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S - clock (through a configurable prescaler) on PC9 pin. - -@endverbatim - * @{ - */ - -/** - * @brief Resets the RCC clock configuration to the default reset state. - * @note The default reset state of the clock configuration is given below: - * - HSI ON and used as system clock source - * - HSE, PLL and PLLI2S OFF - * - AHB, APB1 and APB2 prescaler set to 1. - * - CSS, MCO1 and MCO2 OFF - * - All interrupts disabled - * @note This function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks - * @param None - * @retval None - */ -void RCC_DeInit(void) -{ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x24003010; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; -} - -/** - * @brief Configures the External High Speed oscillator (HSE). - * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application - * software should wait on HSERDY flag to be set indicating that HSE clock - * is stable and can be used to clock the PLL and/or system clock. - * @note HSE state can not be changed if it is used directly or through the - * PLL as system clock. In this case, you have to select another source - * of the system clock then change the HSE state (ex. disable it). - * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. - * @note This function reset the CSSON bit, so if the Clock security system(CSS) - * was previously enabled you have to enable it again after calling this - * function. - * @param RCC_HSE: specifies the new state of the HSE. - * This parameter can be one of the following values: - * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after - * 6 HSE oscillator clock cycles. - * @arg RCC_HSE_ON: turn ON the HSE oscillator - * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock - * @retval None - */ -void RCC_HSEConfig(uint8_t RCC_HSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_HSE)); - - /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ - *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF; - - /* Set the new HSE configuration -------------------------------------------*/ - *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE; -} - -/** - * @brief Waits for HSE start-up. - * @note This functions waits on HSERDY flag to be set and return SUCCESS if - * this flag is set, otherwise returns ERROR if the timeout is reached - * and this flag is not set. The timeout value is defined by the constant - * HSE_STARTUP_TIMEOUT in stm32f2xx.h file. You can tailor it depending - * on the HSE crystal used in your application. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: HSE oscillator is stable and ready to use - * - ERROR: HSE oscillator not yet ready - */ -ErrorStatus RCC_WaitForHSEStartUp(void) -{ - __IO uint32_t startupcounter = 0; - ErrorStatus status = ERROR; - FlagStatus hsestatus = RESET; - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); - startupcounter++; - } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET)); - - if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - return (status); -} - -/** - * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI RC. - * @param HSICalibrationValue: specifies the calibration trimming value. - * This parameter must be a number between 0 and 0x1F. - * @retval None - */ -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); - - tmpreg = RCC->CR; - - /* Clear HSITRIM[4:0] bits */ - tmpreg &= ~RCC_CR_HSITRIM; - - /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ - tmpreg |= (uint32_t)HSICalibrationValue << 3; - - /* Store the new value */ - RCC->CR = tmpreg; -} - -/** - * @brief Enables or disables the Internal High Speed oscillator (HSI). - * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. - * It is used (enabled by hardware) as system clock source after startup - * from Reset, wakeup from STOP and STANDBY mode, or in case of failure - * of the HSE used directly or indirectly as system clock (if the Clock - * Security System CSS is enabled). - * @note HSI can not be stopped if it is used as system clock source. In this case, - * you have to select another source of the system clock then stop the HSI. - * @note After enabling the HSI, the application software should wait on HSIRDY - * flag to be set indicating that HSI clock is stable and can be used as - * system clock source. - * @param NewState: new state of the HSI. - * This parameter can be: ENABLE or DISABLE. - * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator - * clock cycles. - * @retval None - */ -void RCC_HSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the External Low Speed oscillator (LSE). - * @note As the LSE is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using - * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE - * (to be done once after reset). - * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application - * software should wait on LSERDY flag to be set indicating that LSE clock - * is stable and can be used to clock the RTC. - * @param RCC_LSE: specifies the new state of the LSE. - * This parameter can be one of the following values: - * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after - * 6 LSE oscillator clock cycles. - * @arg RCC_LSE_ON: turn ON the LSE oscillator - * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock - * @retval None - */ -void RCC_LSEConfig(uint8_t RCC_LSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_LSE)); - - /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ - /* Reset LSEON bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; - - /* Reset LSEBYP bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; - - /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ - switch (RCC_LSE) - { - case RCC_LSE_ON: - /* Set LSEON bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; - break; - case RCC_LSE_Bypass: - /* Set LSEBYP and LSEON bits */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; - break; - default: - break; - } -} - -/** - * @brief Enables or disables the Internal Low Speed oscillator (LSI). - * @note After enabling the LSI, the application software should wait on - * LSIRDY flag to be set indicating that LSI clock is stable and can - * be used to clock the IWDG and/or the RTC. - * @note LSI can not be disabled if the IWDG is running. - * @param NewState: new state of the LSI. - * This parameter can be: ENABLE or DISABLE. - * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator - * clock cycles. - * @retval None - */ -void RCC_LSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the main PLL clock source, multiplication and division factors. - * @note This function must be used only when the main PLL is disabled. - * - * @param RCC_PLLSource: specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry - * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry - * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. - * - * @param PLLM: specifies the division factor for PLL VCO input clock - * This parameter must be a number between 0 and 63. - * @note You have to set the PLLM parameter correctly to ensure that the VCO input - * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency - * of 2 MHz to limit PLL jitter. - * - * @param PLLN: specifies the multiplication factor for PLL VCO output clock - * This parameter must be a number between 192 and 432. - * @note You have to set the PLLN parameter correctly to ensure that the VCO - * output frequency is between 192 and 432 MHz. - * - * @param PLLP: specifies the division factor for main system clock (SYSCLK) - * This parameter must be a number in the range {2, 4, 6, or 8}. - * @note You have to set the PLLP parameter correctly to not exceed 120 MHz on - * the System clock frequency. - * - * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks - * This parameter must be a number between 4 and 15. - * @note If the USB OTG FS is used in your application, you have to set the - * PLLQ parameter correctly to have 48 MHz clock for the USB. However, - * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work - * correctly. - * - * @retval None - */ -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ) -{ - /* Check the parameters */ - assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); - assert_param(IS_RCC_PLLM_VALUE(PLLM)); - assert_param(IS_RCC_PLLN_VALUE(PLLN)); - assert_param(IS_RCC_PLLP_VALUE(PLLP)); - assert_param(IS_RCC_PLLQ_VALUE(PLLQ)); - - RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) | - (PLLQ << 24); -} - -/** - * @brief Enables or disables the main PLL. - * @note After enabling the main PLL, the application software should wait on - * PLLRDY flag to be set indicating that PLL clock is stable and can - * be used as system clock source. - * @note The main PLL can not be disabled if it is used as system clock source - * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. - * @param NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLLCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the PLLI2S clock multiplication and division factors. - * - * @note PLLI2S is available only in Silicon RevisionB and RevisionY. - * @note This function must be used only when the PLLI2S is disabled. - * @note PLLI2S clock source is common with the main PLL (configured in - * RCC_PLLConfig function ) - * - * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock - * This parameter must be a number between 192 and 432. - * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO - * output frequency is between 192 and 432 MHz. - * - * @param PLLI2SR: specifies the division factor for I2S clock - * This parameter must be a number between 2 and 7. - * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz - * on the I2S clock frequency. - * - * @retval None - */ -void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR) -{ - /* Check the parameters */ - assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN)); - assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR)); - - RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28); -} - -/** - * @brief Enables or disables the PLLI2S. - * @note PLLI2S is available only in RevisionB and RevisionY - * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. - * @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLLI2SCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Clock Security System. - * @note If a failure is detected on the HSE oscillator clock, this oscillator - * is automatically disabled and an interrupt is generated to inform the - * software about the failure (Clock Security System Interrupt, CSSI), - * allowing the MCU to perform rescue operations. The CSSI is linked to - * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. - * @param NewState: new state of the Clock Security System. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ClockSecuritySystemCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; -} - -/** - * @brief Selects the clock source to output on MCO1 pin(PA8). - * @note PA8 should be configured in alternate function mode. - * @param RCC_MCO1Source: specifies the clock source to output. - * This parameter can be one of the following values: - * @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source - * @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source - * @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source - * @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source - * @param RCC_MCO1Div: specifies the MCO1 prescaler. - * This parameter can be one of the following values: - * @arg RCC_MCO1Div_1: no division applied to MCO1 clock - * @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock - * @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock - * @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock - * @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock - * @retval None - */ -void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source)); - assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div)); - - tmpreg = RCC->CFGR; - - /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */ - tmpreg &= CFGR_MCO1_RESET_MASK; - - /* Select MCO1 clock source and prescaler */ - tmpreg |= RCC_MCO1Source | RCC_MCO1Div; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Selects the clock source to output on MCO2 pin(PC9). - * @note PC9 should be configured in alternate function mode. - * @param RCC_MCO2Source: specifies the clock source to output. - * This parameter can be one of the following values: - * @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source - * @arg RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source - * @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source - * @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source - * @param RCC_MCO2Div: specifies the MCO2 prescaler. - * This parameter can be one of the following values: - * @arg RCC_MCO2Div_1: no division applied to MCO2 clock - * @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock - * @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock - * @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock - * @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock - * @retval None - */ -void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source)); - assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div)); - - tmpreg = RCC->CFGR; - - /* Clear MCO2 and MCO2PRE[2:0] bits */ - tmpreg &= CFGR_MCO2_RESET_MASK; - - /* Select MCO2 clock source and prescaler */ - tmpreg |= RCC_MCO2Source | RCC_MCO2Div; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @} - */ - -/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions - * @brief System, AHB and APB busses clocks configuration functions - * -@verbatim - =============================================================================== - System, AHB and APB busses clocks configuration functions - =============================================================================== - - This section provide functions allowing to configure the System, AHB, APB1 and - APB2 busses clocks. - - 1. Several clock sources can be used to drive the System clock (SYSCLK): HSI, - HSE and PLL. - The AHB clock (HCLK) is derived from System clock through configurable prescaler - and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA, GPIO...). - APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through - configurable prescalers and used to clock the peripherals mapped on these busses. - You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks. - -@note All the peripheral clocks are derived from the System clock (SYSCLK) except: - - I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or - from an external clock mapped on the I2S_CKIN pin. - You have to use RCC_I2SCLKConfig() function to configure this clock. - - RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock - divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd() - functions to configure this clock. - - USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz - to work correctly, while the SDIO require a frequency equal or lower than - to 48. This clock is derived of the main PLL through PLLQ divider. - - IWDG clock which is always the LSI clock. - - 2. The maximum frequency of the SYSCLK and HCLK is 120 MHz, PCLK2 60 MHz and PCLK1 30 MHz. - Depending on the device voltage range, the maximum frequency should be - adapted accordingly: - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)| NA |96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 108 |80 < HCLK <= 96 | - |---------------|----------------|----------------|-----------------|-----------------| - |6WS(7CPU cycle)| NA | NA |108 < HCLK <= 120|96 < HCLK <= 112 | - |---------------|----------------|----------------|-----------------|-----------------| - |7WS(8CPU cycle)| NA | NA | NA |112 < HCLK <= 120| - +-------------------------------------------------------------------------------------+ - - -@endverbatim - * @{ - */ - -/** - * @brief Configures the system clock (SYSCLK). - * @note The HSI is used (enabled by hardware) as system clock source after - * startup from Reset, wake-up from STOP and STANDBY mode, or in case - * of failure of the HSE used directly or indirectly as system clock - * (if the Clock Security System CSS is enabled). - * @note A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after startup delay or PLL locked). - * If a clock source which is not yet ready is selected, the switch will - * occur when the clock source will be ready. - * You can use RCC_GetSYSCLKSource() function to know which clock is - * currently used as system clock source. - * @param RCC_SYSCLKSource: specifies the clock source used as system clock. - * This parameter can be one of the following values: - * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source - * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source - * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source - * @retval None - */ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); - - tmpreg = RCC->CFGR; - - /* Clear SW[1:0] bits */ - tmpreg &= ~RCC_CFGR_SW; - - /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ - tmpreg |= RCC_SYSCLKSource; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Returns the clock source used as system clock. - * @param None - * @retval The clock source used as system clock. The returned value can be one - * of the following: - * - 0x00: HSI used as system clock - * - 0x04: HSE used as system clock - * - 0x08: PLL used as system clock - */ -uint8_t RCC_GetSYSCLKSource(void) -{ - return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS)); -} - -/** - * @brief Configures the AHB clock (HCLK). - * @note Depending on the device voltage range, the software has to set correctly - * these bits to ensure that HCLK not exceed the maximum allowed frequency - * (for more details refer to section above - * "CPU, AHB and APB busses clocks configuration functions") - * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from - * the system clock (SYSCLK). - * This parameter can be one of the following values: - * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK - * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 - * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 - * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 - * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 - * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 - * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 - * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 - * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 - * @retval None - */ -void RCC_HCLKConfig(uint32_t RCC_SYSCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_HCLK(RCC_SYSCLK)); - - tmpreg = RCC->CFGR; - - /* Clear HPRE[3:0] bits */ - tmpreg &= ~RCC_CFGR_HPRE; - - /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ - tmpreg |= RCC_SYSCLK; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - - -/** - * @brief Configures the Low Speed APB clock (PCLK1). - * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB1 clock = HCLK - * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 - * @retval None - */ -void RCC_PCLK1Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - - tmpreg = RCC->CFGR; - - /* Clear PPRE1[2:0] bits */ - tmpreg &= ~RCC_CFGR_PPRE1; - - /* Set PPRE1[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Configures the High Speed APB clock (PCLK2). - * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB2 clock = HCLK - * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 - * @retval None - */ -void RCC_PCLK2Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - - tmpreg = RCC->CFGR; - - /* Clear PPRE2[2:0] bits */ - tmpreg &= ~RCC_CFGR_PPRE2; - - /* Set PPRE2[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK << 3; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK, - * PCLK1 and PCLK2. - * - * @note The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) - * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) - * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * @note (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * @note (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value - * 25 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * @note The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold - * the clocks frequencies. - * - * @note This function can be used by the user application to compute the - * baudrate for the communication peripherals or configure other parameters. - * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function - * must be called to update the structure's field. Otherwise, any - * configuration based on this function will be incorrect. - * - * @retval None - */ -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) -{ - uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock source */ - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock source */ - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN - SYSCLK = PLL_VCO / PLLP - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - RCC_Clocks->SYSCLK_Frequency = pllvco/pllp; - break; - default: - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - } - /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/ - - /* Get HCLK prescaler */ - tmp = RCC->CFGR & RCC_CFGR_HPRE; - tmp = tmp >> 4; - presc = APBAHBPrescTable[tmp]; - /* HCLK clock frequency */ - RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; - - /* Get PCLK1 prescaler */ - tmp = RCC->CFGR & RCC_CFGR_PPRE1; - tmp = tmp >> 10; - presc = APBAHBPrescTable[tmp]; - /* PCLK1 clock frequency */ - RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - - /* Get PCLK2 prescaler */ - tmp = RCC->CFGR & RCC_CFGR_PPRE2; - tmp = tmp >> 13; - presc = APBAHBPrescTable[tmp]; - /* PCLK2 clock frequency */ - RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; -} - -/** - * @} - */ - -/** @defgroup RCC_Group3 Peripheral clocks configuration functions - * @brief Peripheral clocks configuration functions - * -@verbatim - =============================================================================== - Peripheral clocks configuration functions - =============================================================================== - - This section provide functions allowing to configure the Peripheral clocks. - - 1. The RTC clock which is derived from the LSI, LSE or HSE clock divided by 2 to 31. - - 2. After restart from Reset or wakeup from STANDBY, all peripherals are off - except internal SRAM, Flash and JTAG. Before to start using a peripheral you - have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd() - , RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions. - - 3. To reset the peripherals configuration (to the default state after device reset) - you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and - RCC_APB1PeriphResetCmd() functions. - - 4. To further reduce power consumption in SLEEP mode the peripheral clocks can - be disabled prior to executing the WFI or WFE instructions. You can do this - using RCC_AHBPeriphClockLPModeCmd(), RCC_APB2PeriphClockLPModeCmd() and - RCC_APB1PeriphClockLPModeCmd() functions. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the RTC clock (RTCCLK). - * @note As the RTC clock configuration bits are in the Backup domain and write - * access is denied to this domain after reset, you have to enable write - * access using PWR_BackupAccessCmd(ENABLE) function before to configure - * the RTC clock source (to be done once after reset). - * @note Once the RTC clock is configured it can't be changed unless the - * Backup domain is reset using RCC_BackupResetCmd() function, or by - * a Power On Reset (POR). - * - * @param RCC_RTCCLKSource: specifies the RTC clock source. - * This parameter can be one of the following values: - * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock - * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock - * @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected - * as RTC clock, where x:[2,31] - * - * @note If the LSE or LSI is used as RTC clock source, the RTC continues to - * work in STOP and STANDBY modes, and can be used as wakeup source. - * However, when the HSE clock is used as RTC clock source, the RTC - * cannot be used in STOP and STANDBY modes. - * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as - * RTC clock source). - * - * @retval None - */ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); - - if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300) - { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */ - tmpreg = RCC->CFGR; - - /* Clear RTCPRE[4:0] bits */ - tmpreg &= ~RCC_CFGR_RTCPRE; - - /* Configure HSE division factor for RTC clock */ - tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF); - - /* Store the new value */ - RCC->CFGR = tmpreg; - } - - /* Select the RTC clock source */ - RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF); -} - -/** - * @brief Enables or disables the RTC clock. - * @note This function must be used only after the RTC clock source was selected - * using the RCC_RTCCLKConfig function. - * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_RTCCLKCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; -} - -/** - * @brief Forces or releases the Backup domain reset. - * @note This function resets the RTC peripheral (including the backup registers) - * and the RTC clock source selection in RCC_CSR register. - * @note The BKPSRAM is not affected by this reset. - * @param NewState: new state of the Backup domain reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_BackupResetCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the I2S clock source (I2SCLK). - * - * @note This function must be called before enabling the I2S APB clock. - * @note This function applies only to Silicon RevisionB and RevisionY. - * - * @param RCC_I2SCLKSource: specifies the I2S clock source. - * This parameter can be one of the following values: - * @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source - * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin - * used as I2S clock source - * @retval None - */ -void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource)); - - *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource; -} - -/** - * @brief Enables or disables the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHB1Periph_GPIOA: GPIOA clock - * @arg RCC_AHB1Periph_GPIOB: GPIOB clock - * @arg RCC_AHB1Periph_GPIOC: GPIOC clock - * @arg RCC_AHB1Periph_GPIOD: GPIOD clock - * @arg RCC_AHB1Periph_GPIOE: GPIOE clock - * @arg RCC_AHB1Periph_GPIOF: GPIOF clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOI: GPIOI clock - * @arg RCC_AHB1Periph_CRC: CRC clock - * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock - * @arg RCC_AHB1Periph_DMA1: DMA1 clock - * @arg RCC_AHB1Periph_DMA2: DMA2 clock - * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock - * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock - * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock - * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock - * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock - * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph)); - - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->AHB1ENR |= RCC_AHB1Periph; - } - else - { - RCC->AHB1ENR &= ~RCC_AHB1Periph; - } -} - -/** - * @brief Enables or disables the AHB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHB2Periph_DCMI: DCMI clock - * @arg RCC_AHB2Periph_CRYP: CRYP clock - * @arg RCC_AHB2Periph_HASH: HASH clock - * @arg RCC_AHB2Periph_RNG: RNG clock - * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB2ENR |= RCC_AHB2Periph; - } - else - { - RCC->AHB2ENR &= ~RCC_AHB2Periph; - } -} - -/** - * @brief Enables or disables the AHB3 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. - * This parameter must be: RCC_AHB3Periph_FSMC - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB3ENR |= RCC_AHB3Periph; - } - else - { - RCC->AHB3ENR &= ~RCC_AHB3Periph; - } -} - -/** - * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2: TIM2 clock - * @arg RCC_APB1Periph_TIM3: TIM3 clock - * @arg RCC_APB1Periph_TIM4: TIM4 clock - * @arg RCC_APB1Periph_TIM5: TIM5 clock - * @arg RCC_APB1Periph_TIM6: TIM6 clock - * @arg RCC_APB1Periph_TIM7: TIM7 clock - * @arg RCC_APB1Periph_TIM12: TIM12 clock - * @arg RCC_APB1Periph_TIM13: TIM13 clock - * @arg RCC_APB1Periph_TIM14: TIM14 clock - * @arg RCC_APB1Periph_WWDG: WWDG clock - * @arg RCC_APB1Periph_SPI2: SPI2 clock - * @arg RCC_APB1Periph_SPI3: SPI3 clock - * @arg RCC_APB1Periph_USART2: USART2 clock - * @arg RCC_APB1Periph_USART3: USART3 clock - * @arg RCC_APB1Periph_UART4: UART4 clock - * @arg RCC_APB1Periph_UART5: UART5 clock - * @arg RCC_APB1Periph_I2C1: I2C1 clock - * @arg RCC_APB1Periph_I2C2: I2C2 clock - * @arg RCC_APB1Periph_I2C3: I2C3 clock - * @arg RCC_APB1Periph_CAN1: CAN1 clock - * @arg RCC_APB1Periph_CAN2: CAN2 clock - * @arg RCC_APB1Periph_PWR: PWR clock - * @arg RCC_APB1Periph_DAC: DAC clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB1ENR |= RCC_APB1Periph; - } - else - { - RCC->APB1ENR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Enables or disables the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_TIM1: TIM1 clock - * @arg RCC_APB2Periph_TIM8: TIM8 clock - * @arg RCC_APB2Periph_USART1: USART1 clock - * @arg RCC_APB2Periph_USART6: USART6 clock - * @arg RCC_APB2Periph_ADC1: ADC1 clock - * @arg RCC_APB2Periph_ADC2: ADC2 clock - * @arg RCC_APB2Periph_ADC3: ADC3 clock - * @arg RCC_APB2Periph_SDIO: SDIO clock - * @arg RCC_APB2Periph_SPI1: SPI1 clock - * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock - * @arg RCC_APB2Periph_TIM9: TIM9 clock - * @arg RCC_APB2Periph_TIM10: TIM10 clock - * @arg RCC_APB2Periph_TIM11: TIM11 clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB2ENR |= RCC_APB2Periph; - } - else - { - RCC->APB2ENR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Forces or releases AHB1 peripheral reset. - * @param RCC_AHB1Periph: specifies the AHB1 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_AHB1Periph_GPIOA: GPIOA clock - * @arg RCC_AHB1Periph_GPIOB: GPIOB clock - * @arg RCC_AHB1Periph_GPIOC: GPIOC clock - * @arg RCC_AHB1Periph_GPIOD: GPIOD clock - * @arg RCC_AHB1Periph_GPIOE: GPIOE clock - * @arg RCC_AHB1Periph_GPIOF: GPIOF clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOI: GPIOI clock - * @arg RCC_AHB1Periph_CRC: CRC clock - * @arg RCC_AHB1Periph_DMA1: DMA1 clock - * @arg RCC_AHB1Periph_DMA2: DMA2 clock - * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock - * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock - * - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB1RSTR |= RCC_AHB1Periph; - } - else - { - RCC->AHB1RSTR &= ~RCC_AHB1Periph; - } -} - -/** - * @brief Forces or releases AHB2 peripheral reset. - * @param RCC_AHB2Periph: specifies the AHB2 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_AHB2Periph_DCMI: DCMI clock - * @arg RCC_AHB2Periph_CRYP: CRYP clock - * @arg RCC_AHB2Periph_HASH: HASH clock - * @arg RCC_AHB2Periph_RNG: RNG clock - * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB2RSTR |= RCC_AHB2Periph; - } - else - { - RCC->AHB2RSTR &= ~RCC_AHB2Periph; - } -} - -/** - * @brief Forces or releases AHB3 peripheral reset. - * @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset. - * This parameter must be: RCC_AHB3Periph_FSMC - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB3RSTR |= RCC_AHB3Periph; - } - else - { - RCC->AHB3RSTR &= ~RCC_AHB3Periph; - } -} - -/** - * @brief Forces or releases Low Speed APB (APB1) peripheral reset. - * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2: TIM2 clock - * @arg RCC_APB1Periph_TIM3: TIM3 clock - * @arg RCC_APB1Periph_TIM4: TIM4 clock - * @arg RCC_APB1Periph_TIM5: TIM5 clock - * @arg RCC_APB1Periph_TIM6: TIM6 clock - * @arg RCC_APB1Periph_TIM7: TIM7 clock - * @arg RCC_APB1Periph_TIM12: TIM12 clock - * @arg RCC_APB1Periph_TIM13: TIM13 clock - * @arg RCC_APB1Periph_TIM14: TIM14 clock - * @arg RCC_APB1Periph_WWDG: WWDG clock - * @arg RCC_APB1Periph_SPI2: SPI2 clock - * @arg RCC_APB1Periph_SPI3: SPI3 clock - * @arg RCC_APB1Periph_USART2: USART2 clock - * @arg RCC_APB1Periph_USART3: USART3 clock - * @arg RCC_APB1Periph_UART4: UART4 clock - * @arg RCC_APB1Periph_UART5: UART5 clock - * @arg RCC_APB1Periph_I2C1: I2C1 clock - * @arg RCC_APB1Periph_I2C2: I2C2 clock - * @arg RCC_APB1Periph_I2C3: I2C3 clock - * @arg RCC_APB1Periph_CAN1: CAN1 clock - * @arg RCC_APB1Periph_CAN2: CAN2 clock - * @arg RCC_APB1Periph_PWR: PWR clock - * @arg RCC_APB1Periph_DAC: DAC clock - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB1RSTR |= RCC_APB1Periph; - } - else - { - RCC->APB1RSTR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Forces or releases High Speed APB (APB2) peripheral reset. - * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_TIM1: TIM1 clock - * @arg RCC_APB2Periph_TIM8: TIM8 clock - * @arg RCC_APB2Periph_USART1: USART1 clock - * @arg RCC_APB2Periph_USART6: USART6 clock - * @arg RCC_APB2Periph_ADC1: ADC1 clock - * @arg RCC_APB2Periph_ADC2: ADC2 clock - * @arg RCC_APB2Periph_ADC3: ADC3 clock - * @arg RCC_APB2Periph_SDIO: SDIO clock - * @arg RCC_APB2Periph_SPI1: SPI1 clock - * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock - * @arg RCC_APB2Periph_TIM9: TIM9 clock - * @arg RCC_APB2Periph_TIM10: TIM10 clock - * @arg RCC_APB2Periph_TIM11: TIM11 clock - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB2RSTR |= RCC_APB2Periph; - } - else - { - RCC->APB2RSTR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHB1Periph_GPIOA: GPIOA clock - * @arg RCC_AHB1Periph_GPIOB: GPIOB clock - * @arg RCC_AHB1Periph_GPIOC: GPIOC clock - * @arg RCC_AHB1Periph_GPIOD: GPIOD clock - * @arg RCC_AHB1Periph_GPIOE: GPIOE clock - * @arg RCC_AHB1Periph_GPIOF: GPIOF clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOI: GPIOI clock - * @arg RCC_AHB1Periph_CRC: CRC clock - * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock - * @arg RCC_AHB1Periph_DMA1: DMA1 clock - * @arg RCC_AHB1Periph_DMA2: DMA2 clock - * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock - * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock - * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock - * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock - * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock - * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->AHB1LPENR |= RCC_AHB1Periph; - } - else - { - RCC->AHB1LPENR &= ~RCC_AHB1Periph; - } -} - -/** - * @brief Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHB2Periph_DCMI: DCMI clock - * @arg RCC_AHB2Periph_CRYP: CRYP clock - * @arg RCC_AHB2Periph_HASH: HASH clock - * @arg RCC_AHB2Periph_RNG: RNG clock - * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->AHB2LPENR |= RCC_AHB2Periph; - } - else - { - RCC->AHB2LPENR &= ~RCC_AHB2Periph; - } -} - -/** - * @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. - * This parameter must be: RCC_AHB3Periph_FSMC - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->AHB3LPENR |= RCC_AHB3Periph; - } - else - { - RCC->AHB3LPENR &= ~RCC_AHB3Periph; - } -} - -/** - * @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2: TIM2 clock - * @arg RCC_APB1Periph_TIM3: TIM3 clock - * @arg RCC_APB1Periph_TIM4: TIM4 clock - * @arg RCC_APB1Periph_TIM5: TIM5 clock - * @arg RCC_APB1Periph_TIM6: TIM6 clock - * @arg RCC_APB1Periph_TIM7: TIM7 clock - * @arg RCC_APB1Periph_TIM12: TIM12 clock - * @arg RCC_APB1Periph_TIM13: TIM13 clock - * @arg RCC_APB1Periph_TIM14: TIM14 clock - * @arg RCC_APB1Periph_WWDG: WWDG clock - * @arg RCC_APB1Periph_SPI2: SPI2 clock - * @arg RCC_APB1Periph_SPI3: SPI3 clock - * @arg RCC_APB1Periph_USART2: USART2 clock - * @arg RCC_APB1Periph_USART3: USART3 clock - * @arg RCC_APB1Periph_UART4: UART4 clock - * @arg RCC_APB1Periph_UART5: UART5 clock - * @arg RCC_APB1Periph_I2C1: I2C1 clock - * @arg RCC_APB1Periph_I2C2: I2C2 clock - * @arg RCC_APB1Periph_I2C3: I2C3 clock - * @arg RCC_APB1Periph_CAN1: CAN1 clock - * @arg RCC_APB1Periph_CAN2: CAN2 clock - * @arg RCC_APB1Periph_PWR: PWR clock - * @arg RCC_APB1Periph_DAC: DAC clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB1LPENR |= RCC_APB1Periph; - } - else - { - RCC->APB1LPENR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_TIM1: TIM1 clock - * @arg RCC_APB2Periph_TIM8: TIM8 clock - * @arg RCC_APB2Periph_USART1: USART1 clock - * @arg RCC_APB2Periph_USART6: USART6 clock - * @arg RCC_APB2Periph_ADC1: ADC1 clock - * @arg RCC_APB2Periph_ADC2: ADC2 clock - * @arg RCC_APB2Periph_ADC3: ADC3 clock - * @arg RCC_APB2Periph_SDIO: SDIO clock - * @arg RCC_APB2Periph_SPI1: SPI1 clock - * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock - * @arg RCC_APB2Periph_TIM9: TIM9 clock - * @arg RCC_APB2Periph_TIM10: TIM10 clock - * @arg RCC_APB2Periph_TIM11: TIM11 clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB2LPENR |= RCC_APB2Periph; - } - else - { - RCC->APB2LPENR &= ~RCC_APB2Periph; - } -} - -/** - * @} - */ - -/** @defgroup RCC_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified RCC interrupts. - * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: main PLL ready interrupt - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt - * @param NewState: new state of the specified RCC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_IT(RCC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; - } - else - { - /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; - } -} - -/** - * @brief Checks whether the specified RCC flag is set or not. - * @param RCC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready - * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready - * @arg RCC_FLAG_PLLRDY: main PLL clock ready - * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready - * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready - * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready - * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset - * @arg RCC_FLAG_PINRST: Pin reset - * @arg RCC_FLAG_PORRST: POR/PDR reset - * @arg RCC_FLAG_SFTRST: Software reset - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset - * @arg RCC_FLAG_LPWRRST: Low Power reset - * @retval The new state of RCC_FLAG (SET or RESET). - */ -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) -{ - uint32_t tmp = 0; - uint32_t statusreg = 0; - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_FLAG(RCC_FLAG)); - - /* Get the RCC register index */ - tmp = RCC_FLAG >> 5; - if (tmp == 1) /* The flag to check is in CR register */ - { - statusreg = RCC->CR; - } - else if (tmp == 2) /* The flag to check is in BDCR register */ - { - statusreg = RCC->BDCR; - } - else /* The flag to check is in CSR register */ - { - statusreg = RCC->CSR; - } - - /* Get the flag position */ - tmp = RCC_FLAG & FLAG_MASK; - if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the RCC reset flags. - * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, - * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST - * @param None - * @retval None - */ -void RCC_ClearFlag(void) -{ - /* Set RMVF bit to clear the reset flags */ - RCC->CSR |= RCC_CSR_RMVF; -} - -/** - * @brief Checks whether the specified RCC interrupt has occurred or not. - * @param RCC_IT: specifies the RCC interrupt source to check. - * This parameter can be one of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: main PLL ready interrupt - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval The new state of RCC_IT (SET or RESET). - */ -ITStatus RCC_GetITStatus(uint8_t RCC_IT) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_GET_IT(RCC_IT)); - - /* Check the status of the specified RCC interrupt */ - if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the RCC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the RCC's interrupt pending bits. - * @param RCC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: main PLL ready interrupt - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval None - */ -void RCC_ClearITPendingBit(uint8_t RCC_IT) -{ - /* Check the parameters */ - assert_param(IS_RCC_CLEAR_IT(RCC_IT)); - - /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt - pending bits */ - *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/stm32f2xx_spi.c b/radio/bootloader/stm32f2xx_spi.c deleted file mode 100644 index de0bc99a2..000000000 --- a/radio/bootloader/stm32f2xx_spi.c +++ /dev/null @@ -1,1185 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_spi.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the Serial peripheral interface (SPI): - * - Initialization and Configuration - * - Data transfers functions - * - Hardware CRC Calculation - * - DMA transfers management - * - Interrupts and flags management - * - * @verbatim - * - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable peripheral clock using the following functions - * RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) for SPI1 - * RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) for SPI2 - * RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI3. - * - * 2. Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHB1PeriphClockCmd() - * function. - * In I2S mode, if an external clock source is used then the I2S CKIN pin GPIO - * clock should also be enabled. - * - * 3. Peripherals alternate function: - * - Connect the pin to the desired peripherals' Alternate - * Function (AF) using GPIO_PinAFConfig() function - * - Configure the desired pin in alternate function by: - * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - * - Select the type, pull-up/pull-down and output speed via - * GPIO_PuPd, GPIO_OType and GPIO_Speed members - * - Call GPIO_Init() function - * In I2S mode, if an external clock source is used then the I2S CKIN pin - * should be also configured in Alternate function Push-pull pull-up mode. - * - * 4. Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave - * Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() - * function. - * In I2S mode, program the Mode, Standard, Data Format, MCLK Output, Audio - * frequency and Polarity using I2S_Init() function. - * For I2S mode, make sure that either: - * - I2S PLL is configured using the functions RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S), - * RCC_PLLI2SCmd(ENABLE) and RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY). - * or - * - External clock source is configured using the function - * RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly the define constant - * I2S_EXTERNAL_CLOCK_VAL in the stm32f2xx_conf.h file. - * - * 5. Enable the NVIC and the corresponding interrupt using the function - * SPI_ITConfig() if you need to use interrupt mode. - * - * 6. When using the DMA mode - * - Configure the DMA using DMA_Init() function - * - Active the needed channel Request using SPI_I2S_DMACmd() function - * - * 7. Enable the SPI using the SPI_Cmd() function or enable the I2S using - * I2S_Cmd(). - * - * 8. Enable the DMA using the DMA_Cmd() function when using DMA mode. - * - * 9. Optionally, you can enable/configure the following parameters without - * re-initialization (i.e there is no need to call again SPI_Init() function): - * - When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx) - * is programmed as Data direction parameter using the SPI_Init() function - * it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx - * using the SPI_BiDirectionalLineConfig() function. - * - When SPI_NSS_Soft is selected as Slave Select Management parameter - * using the SPI_Init() function it can be possible to manage the - * NSS internal signal using the SPI_NSSInternalSoftwareConfig() function. - * - Reconfigure the data size using the SPI_DataSizeConfig() function - * - Enable or disable the SS output using the SPI_SSOutputCmd() function - * - * 10. To use the CRC Hardware calculation feature refer to the Peripheral - * CRC hardware Calculation subsection. - * - * - * @note This driver supports only the I2S clock scheme available in Silicon - * RevisionB and RevisionY. - * - * @note In I2S mode: if an external clock is used as source clock for the I2S, - * then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f2xx_conf.h should - * be enabled and set to the value of the source clock frequency (in Hz). - * - * @note In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd() - * just after calling the function SPI_Init(). - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include -#include "stm32f2xx.h" -#include "stm32f2xx_spi.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup SPI - * @brief SPI driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* SPI registers Masks */ -#define CR1_CLEAR_MASK ((uint16_t)0x3040) -#define I2SCFGR_CLEAR_MASK ((uint16_t)0xF040) - -/* RCC PLLs masks */ -#define PLLCFGR_PPLR_MASK ((uint32_t)0x70000000) -#define PLLCFGR_PPLN_MASK ((uint32_t)0x00007FC0) - -#define SPI_CR2_FRF ((uint16_t)0x0010) -#define SPI_SR_TIFRFE ((uint16_t)0x0100) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SPI_Private_Functions - * @{ - */ - -/** @defgroup SPI_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - - This section provides a set of functions allowing to initialize the SPI Direction, - SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud - Rate Prescaler, SPI First Bit and SPI CRC Polynomial. - - The SPI_Init() function follows the SPI configuration procedures for Master mode - and Slave mode (details for these procedures are available in reference manual - (RM0033)). - -@endverbatim - * @{ - */ - -/** - * @brief Deinitialize the SPIx peripheral registers to their default reset values. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode. - * @retval None - */ -void SPI_I2S_DeInit(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - if (SPIx == SPI1) - { - /* Enable SPI1 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); - /* Release SPI1 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); - } - else if (SPIx == SPI2) - { - /* Enable SPI2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); - /* Release SPI2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); - } - else - { - if (SPIx == SPI3) - { - /* Enable SPI3 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); - /* Release SPI3 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); - } - } -} - -/** - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the SPI_InitStruct. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral. - * @retval None - */ -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) -{ - uint16_t tmpreg = 0; - - /* check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Check the SPI parameters */ - assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); - assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); - assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); - assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); - assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); - assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); - assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); - assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); - assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); - -/*---------------------------- SPIx CR1 Configuration ------------------------*/ - /* Get the SPIx CR1 value */ - tmpreg = SPIx->CR1; - /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ - tmpreg &= CR1_CLEAR_MASK; - /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler - master/salve mode, CPOL and CPHA */ - /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ - /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ - /* Set LSBFirst bit according to SPI_FirstBit value */ - /* Set BR bits according to SPI_BaudRatePrescaler value */ - /* Set CPOL bit according to SPI_CPOL value */ - /* Set CPHA bit according to SPI_CPHA value */ - tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | - SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | - SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | - SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); - /* Write to SPIx CR1 */ - SPIx->CR1 = tmpreg; - - /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ - SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD); -/*---------------------------- SPIx CRCPOLY Configuration --------------------*/ - /* Write to SPIx CRCPOLY */ - SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; -} - -/** - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the I2S_InitStruct. - * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (configured in I2S mode). - * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral - * configured in I2S mode. - * - * @note The function calculates the optimal prescaler needed to obtain the most - * accurate audio frequency (depending on the I2S clock source, the PLL values - * and the product configuration). But in case the prescaler value is greater - * than 511, the default value (0x02) will be configured instead. - * - * @note if an external clock is used as source clock for the I2S, then the define - * I2S_EXTERNAL_CLOCK_VAL in file stm32f2xx_conf.h should be enabled and set - * to the value of the the source clock frequency (in Hz). - * - * @retval None - */ -void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) -{ - uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; - uint32_t tmp = 0, i2sclk = 0; -#ifndef I2S_EXTERNAL_CLOCK_VAL - uint32_t pllm = 0, plln = 0, pllr = 0; -#endif /* I2S_EXTERNAL_CLOCK_VAL */ - - /* Check the I2S parameters */ - assert_param(IS_SPI_23_PERIPH(SPIx)); - assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); - assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); - assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); - assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); - assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); - assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); - -/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ - /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ - SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK; - SPIx->I2SPR = 0x0002; - - /* Get the I2SCFGR register value */ - tmpreg = SPIx->I2SCFGR; - - /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ - if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) - { - i2sodd = (uint16_t)0; - i2sdiv = (uint16_t)2; - } - /* If the requested audio frequency is not the default, compute the prescaler */ - else - { - /* Check the frame length (For the Prescaler computing) *******************/ - if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) - { - /* Packet length is 16 bits */ - packetlength = 1; - } - else - { - /* Packet length is 32 bits */ - packetlength = 2; - } - - /* Get I2S source Clock frequency (only in Silicon RevisionB and RevisionY) */ - - /* If an external I2S clock has to be used, this define should be set - in the project configuration or in the stm32f2xx_conf.h file */ - #ifdef I2S_EXTERNAL_CLOCK_VAL - /* Set external clock as I2S clock source */ - if ((RCC->CFGR & RCC_CFGR_I2SSRC) == 0) - { - RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC; - } - - /* Set the I2S clock to the external clock value */ - i2sclk = I2S_EXTERNAL_CLOCK_VAL; - - #else /* There is no define for External I2S clock source */ - /* Set PLLI2S as I2S clock source */ - if ((RCC->CFGR & RCC_CFGR_I2SSRC) != 0) - { - RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC; - } - - /* Get the PLLI2SN value */ - plln = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & \ - (RCC_PLLI2SCFGR_PLLI2SN >> 6)); - - /* Get the PLLI2SR value */ - pllr = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & \ - (RCC_PLLI2SCFGR_PLLI2SR >> 28)); - - /* Get the PLLM value */ - pllm = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); - - /* Get the I2S source clock value */ - i2sclk = (uint32_t)(((HSE_VALUE / pllm) * plln) / pllr); - #endif /* I2S_EXTERNAL_CLOCK_VAL */ - - /* Compute the Real divider depending on the MCLK output state, with a floating point */ - if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) - { - /* MCLK output is enabled */ - tmp = (uint16_t)(((((i2sclk / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - else - { - /* MCLK output is disabled */ - tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - - /* Remove the flatting point */ - tmp = tmp / 10; - - /* Check the parity of the divider */ - i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); - - /* Compute the i2sdiv prescaler */ - i2sdiv = (uint16_t)((tmp - i2sodd) / 2); - - /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ - i2sodd = (uint16_t) (i2sodd << 8); - } - - /* Test if the divider is 1 or 0 or greater than 0xFF */ - if ((i2sdiv < 2) || (i2sdiv > 0xFF)) - { - /* Set the default values */ - i2sdiv = 2; - i2sodd = 0; - } - - /* Write to SPIx I2SPR register the computed value */ - SPIx->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); - - /* Configure the I2S with the SPI_InitStruct values */ - tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \ - (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ - (uint16_t)I2S_InitStruct->I2S_CPOL)))); - - /* Write to SPIx I2SCFGR */ - SPIx->I2SCFGR = tmpreg; -} - -/** - * @brief Fills each SPI_InitStruct member with its default value. - * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized. - * @retval None - */ -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) -{ -/*--------------- Reset SPI init structure parameters values -----------------*/ - /* Initialize the SPI_Direction member */ - SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; - /* initialize the SPI_Mode member */ - SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; - /* initialize the SPI_DataSize member */ - SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; - /* Initialize the SPI_CPOL member */ - SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; - /* Initialize the SPI_CPHA member */ - SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; - /* Initialize the SPI_NSS member */ - SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; - /* Initialize the SPI_BaudRatePrescaler member */ - SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - /* Initialize the SPI_FirstBit member */ - SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; - /* Initialize the SPI_CRCPolynomial member */ - SPI_InitStruct->SPI_CRCPolynomial = 7; -} - -/** - * @brief Fills each I2S_InitStruct member with its default value. - * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized. - * @retval None - */ -void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) -{ -/*--------------- Reset I2S init structure parameters values -----------------*/ - /* Initialize the I2S_Mode member */ - I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; - - /* Initialize the I2S_Standard member */ - I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; - - /* Initialize the I2S_DataFormat member */ - I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; - - /* Initialize the I2S_MCLKOutput member */ - I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; - - /* Initialize the I2S_AudioFreq member */ - I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; - - /* Initialize the I2S_CPOL member */ - I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; -} - -/** - * @brief Enables or disables the specified SPI peripheral. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI peripheral */ - SPIx->CR1 |= SPI_CR1_SPE; - } - else - { - /* Disable the selected SPI peripheral */ - SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE); - } -} - -/** - * @brief Enables or disables the specified SPI peripheral (in I2S mode). - * @param SPIx: where x can be 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_23_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected SPI peripheral (in I2S mode) */ - SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE; - } - else - { - /* Disable the selected SPI peripheral in I2S mode */ - SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE); - } -} - -/** - * @brief Configures the data size for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_DataSize: specifies the SPI data size. - * This parameter can be one of the following values: - * @arg SPI_DataSize_16b: Set data frame format to 16bit - * @arg SPI_DataSize_8b: Set data frame format to 8bit - * @retval None - */ -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DATASIZE(SPI_DataSize)); - /* Clear DFF bit */ - SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b; - /* Set new DFF bit value */ - SPIx->CR1 |= SPI_DataSize; -} - -/** - * @brief Selects the data transfer direction in bidirectional mode for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_Direction: specifies the data transfer direction in bidirectional mode. - * This parameter can be one of the following values: - * @arg SPI_Direction_Tx: Selects Tx transmission direction - * @arg SPI_Direction_Rx: Selects Rx receive direction - * @retval None - */ -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DIRECTION(SPI_Direction)); - if (SPI_Direction == SPI_Direction_Tx) - { - /* Set the Tx only mode */ - SPIx->CR1 |= SPI_Direction_Tx; - } - else - { - /* Set the Rx only mode */ - SPIx->CR1 &= SPI_Direction_Rx; - } -} - -/** - * @brief Configures internally by software the NSS pin for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. - * This parameter can be one of the following values: - * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally - * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally - * @retval None - */ -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); - if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) - { - /* Set NSS pin internally by software */ - SPIx->CR1 |= SPI_NSSInternalSoft_Set; - } - else - { - /* Reset NSS pin internally by software */ - SPIx->CR1 &= SPI_NSSInternalSoft_Reset; - } -} - -/** - * @brief Enables or disables the SS output for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx SS output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI SS output */ - SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE; - } - else - { - /* Disable the selected SPI SS output */ - SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE); - } -} - -/** - * @brief Enables or disables the SPIx/I2Sx DMA interface. - * - * @note This function can be called only after the SPI_Init() function has - * been called. - * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA - * are not taken into consideration and are configured by hardware - * respectively to the TI mode requirements. - * - * @param SPIx: where x can be 1, 2 or 3 - * @param NewState: new state of the selected SPI TI communication mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TI mode for the selected SPI peripheral */ - SPIx->CR2 |= SPI_CR2_FRF; - } - else - { - /* Disable the TI mode for the selected SPI peripheral */ - SPIx->CR2 &= (uint16_t)~SPI_CR2_FRF; - } -} - -/** - * @} - */ - -/** @defgroup SPI_Group2 Data transfers functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - Data transfers functions - =============================================================================== - - This section provides a set of functions allowing to manage the SPI data transfers - - In reception, data are received and then stored into an internal Rx buffer while - In transmission, data are first stored into an internal Tx buffer before being - transmitted. - - The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData() - function and returns the Rx buffered value. Whereas a write access to the SPI_DR - can be done using SPI_I2S_SendData() function and stores the written data into - Tx buffer. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode. - * @retval The value of the received data. - */ -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Return the data in the DR register */ - return SPIx->DR; -} - -/** - * @brief Transmits a Data through the SPIx/I2Sx peripheral. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode. - * @param Data: Data to be transmitted. - * @retval None - */ -void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Write in the DR register the data to be sent */ - SPIx->DR = Data; -} - -/** - * @} - */ - -/** @defgroup SPI_Group3 Hardware CRC Calculation functions - * @brief Hardware CRC Calculation functions - * -@verbatim - =============================================================================== - Hardware CRC Calculation functions - =============================================================================== - - This section provides a set of functions allowing to manage the SPI CRC hardware - calculation - - SPI communication using CRC is possible through the following procedure: - 1. Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, - Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() - function. - 2. Enable the CRC calculation using the SPI_CalculateCRC() function. - 3. Enable the SPI using the SPI_Cmd() function - 4. Before writing the last data to the TX buffer, set the CRCNext bit using the - SPI_TransmitCRC() function to indicate that after transmission of the last - data, the CRC should be transmitted. - 5. After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT - bit is reset. The CRC is also received and compared against the SPI_RXCRCR - value. - If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt - can be generated when the SPI_I2S_IT_ERR interrupt is enabled. - -@note It is advised not to read the calculated CRC values during the communication. - -@note When the SPI is in slave mode, be careful to enable CRC calculation only - when the clock is stable, that is, when the clock is in the steady state. - If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive - to the SCK slave input clock as soon as CRCEN is set, and this, whatever - the value of the SPE bit. - -@note With high bitrate frequencies, be careful when transmitting the CRC. - As the number of used CPU cycles has to be as low as possible in the CRC - transfer phase, it is forbidden to call software functions in the CRC - transmission sequence to avoid errors in the last data and CRC reception. - In fact, CRCNEXT bit has to be written before the end of the transmission/reception - of the last data. - -@note For high bit rate frequencies, it is advised to use the DMA mode to avoid the - degradation of the SPI speed performance due to CPU accesses impacting the - SPI bandwidth. - -@note When the STM32F2xx is configured as slave and the NSS hardware mode is - used, the NSS pin needs to be kept low between the data phase and the CRC - phase. - -@note When the SPI is configured in slave mode with the CRC feature enabled, CRC - calculation takes place even if a high level is applied on the NSS pin. - This may happen for example in case of a multi-slave environment where the - communication master addresses slaves alternately. - -@note Between a slave de-selection (high level on NSS) and a new slave selection - (low level on NSS), the CRC value should be cleared on both master and slave - sides in order to resynchronize the master and slave for their respective - CRC calculation. - -@note To clear the CRC, follow the procedure below: - 1. Disable SPI using the SPI_Cmd() function - 2. Disable the CRC calculation using the SPI_CalculateCRC() function. - 3. Enable the CRC calculation using the SPI_CalculateCRC() function. - 4. Enable SPI using the SPI_Cmd() function. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the CRC value calculation of the transferred bytes. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx CRC value calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI CRC calculation */ - SPIx->CR1 |= SPI_CR1_CRCEN; - } - else - { - /* Disable the selected SPI CRC calculation */ - SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN); - } -} - -/** - * @brief Transmit the SPIx CRC value. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @retval None - */ -void SPI_TransmitCRC(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Enable the selected SPI CRC transmission */ - SPIx->CR1 |= SPI_CR1_CRCNEXT; -} - -/** - * @brief Returns the transmit or the receive CRC register value for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_CRC: specifies the CRC register to be read. - * This parameter can be one of the following values: - * @arg SPI_CRC_Tx: Selects Tx CRC register - * @arg SPI_CRC_Rx: Selects Rx CRC register - * @retval The selected CRC register value.. - */ -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) -{ - uint16_t crcreg = 0; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_CRC(SPI_CRC)); - if (SPI_CRC != SPI_CRC_Rx) - { - /* Get the Tx CRC register */ - crcreg = SPIx->TXCRCR; - } - else - { - /* Get the Rx CRC register */ - crcreg = SPIx->RXCRCR; - } - /* Return the selected CRC register */ - return crcreg; -} - -/** - * @brief Returns the CRC Polynomial register value for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @retval The CRC Polynomial register value. - */ -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Return the CRC polynomial register */ - return SPIx->CRCPR; -} - -/** - * @} - */ - -/** @defgroup SPI_Group4 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - DMA transfers management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the SPIx/I2Sx DMA interface. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode. - * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request - * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request - * @param NewState: new state of the selected SPI DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq)); - - if (NewState != DISABLE) - { - /* Enable the selected SPI DMA requests */ - SPIx->CR2 |= SPI_I2S_DMAReq; - } - else - { - /* Disable the selected SPI DMA requests */ - SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; - } -} - -/** - * @} - */ - -/** @defgroup SPI_Group5 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - This section provides a set of functions allowing to configure the SPI Interrupts - sources and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode. - - Polling Mode - ============= - In Polling Mode, the SPI/I2S communication can be managed by 9 flags: - 1. SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register - 2. SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register - 3. SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI. - 4. SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur - 5. SPI_FLAG_MODF : to indicate if a Mode Fault error occur - 6. SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur - 7. I2S_FLAG_TIFRFE: to indicate a Frame Format error occurs. - 8. I2S_FLAG_UDR: to indicate an Underrun error occurs. - 9. I2S_FLAG_CHSIDE: to indicate Channel Side. - -@note Do not use the BSY flag to handle each data transmission or reception. It is - better to use the TXE and RXNE flags instead. - - In this Mode it is advised to use the following functions: - - FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); - - void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); - - Interrupt Mode - =============== - In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources - and 7 pending bits: - Pending Bits: - ------------- - 1. SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register - 2. SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register - 3. SPI_IT_CRCERR : to indicate if a CRC Calculation error occur (available in SPI mode only) - 4. SPI_IT_MODF : to indicate if a Mode Fault error occur (available in SPI mode only) - 5. SPI_I2S_IT_OVR : to indicate if an Overrun error occur - 6. I2S_IT_UDR : to indicate an Underrun Error occurs (available in I2S mode only). - 7. I2S_FLAG_TIFRFE : to indicate a Frame Format error occurs (available in TI mode only). - - Interrupt Source: - ----------------- - 1. SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty - interrupt. - 2. SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not - empty interrupt. - 3. SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt. - - In this Mode it is advised to use the following functions: - - void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); - - ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - - void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - - DMA Mode - ======== - In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests: - 1. SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request - 2. SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request - - In this Mode it is advised to use the following function: - - void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified SPI/I2S interrupts. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode. - * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask - * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask - * @arg SPI_I2S_IT_ERR: Error interrupt mask - * @param NewState: new state of the specified SPI interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) -{ - uint16_t itpos = 0, itmask = 0 ; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); - - /* Get the SPI IT index */ - itpos = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = (uint16_t)1 << (uint16_t)itpos; - - if (NewState != DISABLE) - { - /* Enable the selected SPI interrupt */ - SPIx->CR2 |= itmask; - } - else - { - /* Disable the selected SPI interrupt */ - SPIx->CR2 &= (uint16_t)~itmask; - } -} - -/** - * @brief Checks whether the specified SPIx/I2Sx flag is set or not. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode. - * @param SPI_I2S_FLAG: specifies the SPI flag to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. - * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. - * @arg SPI_I2S_FLAG_BSY: Busy flag. - * @arg SPI_I2S_FLAG_OVR: Overrun flag. - * @arg SPI_FLAG_MODF: Mode Fault flag. - * @arg SPI_FLAG_CRCERR: CRC Error flag. - * @arg SPI_I2S_FLAG_TIFRFE: Format Error. - * @arg I2S_FLAG_UDR: Underrun Error flag. - * @arg I2S_FLAG_CHSIDE: Channel Side flag. - * @retval The new state of SPI_I2S_FLAG (SET or RESET). - */ -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); - - /* Check the status of the specified SPI flag */ - if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) - { - /* SPI_I2S_FLAG is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_FLAG is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the SPIx CRC Error (CRCERR) flag. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode. - * @param SPI_I2S_FLAG: specifies the SPI flag to clear. - * This function clears only CRCERR flag. - * @arg SPI_FLAG_CRCERR: CRC Error flag. - * - * @note OVR (OverRun error) flag is cleared by software sequence: a read - * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read - * operation to SPI_SR register (SPI_I2S_GetFlagStatus()). - * @note UDR (UnderRun error) flag is cleared by a read operation to - * SPI_SR register (SPI_I2S_GetFlagStatus()). - * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write - * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a - * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). - * - * @retval None - */ -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG)); - - /* Clear the selected SPI CRC Error (CRCERR) flag */ - SPIx->SR = (uint16_t)~SPI_I2S_FLAG; -} - -/** - * @brief Checks whether the specified SPIx/I2Sx interrupt has occurred or not. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode. - * @param SPI_I2S_IT: specifies the SPI interrupt source to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. - * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. - * @arg SPI_I2S_IT_OVR: Overrun interrupt. - * @arg SPI_IT_MODF: Mode Fault interrupt. - * @arg SPI_IT_CRCERR: CRC Error interrupt. - * @arg I2S_IT_UDR: Underrun interrupt. - * @arg SPI_I2S_IT_TIFRFE: Format Error interrupt. - * @retval The new state of SPI_I2S_IT (SET or RESET). - */ -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itpos = 0, itmask = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); - - /* Get the SPI_I2S_IT index */ - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - - /* Get the SPI_I2S_IT IT mask */ - itmask = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = 0x01 << itmask; - - /* Get the SPI_I2S_IT enable bit status */ - enablestatus = (SPIx->CR2 & itmask) ; - - /* Check the status of the specified SPI interrupt */ - if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) - { - /* SPI_I2S_IT is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_IT is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_IT status */ - return bitstatus; -} - -/** - * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode. - * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. - * This function clears only CRCERR interrupt pending bit. - * @arg SPI_IT_CRCERR: CRC Error interrupt. - * - * @note OVR (OverRun Error) interrupt pending bit is cleared by software - * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) - * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()). - * @note UDR (UnderRun Error) interrupt pending bit is cleared by a read - * operation to SPI_SR register (SPI_I2S_GetITStatus()). - * @note MODF (Mode Fault) interrupt pending bit is cleared by software sequence: - * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) - * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable - * the SPI). - * @retval None - */ -void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) -{ - uint16_t itpos = 0; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT)); - - /* Get the SPI_I2S IT index */ - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - - /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ - SPIx->SR = (uint16_t)~itpos; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_spi.c b/radio/src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_spi.c index 033475e68..0a42a0f2c 100644 --- a/radio/src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_spi.c +++ b/radio/src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_spi.c @@ -113,8 +113,8 @@ */ /* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_spi.h" -#include "stm32f2xx_rcc.h" +#include "../inc/stm32f2xx_spi.h" +#include "../inc/stm32f2xx_rcc.h" /** @addtogroup STM32F2xx_StdPeriph_Driver * @{ From c482eef8d24afe0d890825b6eb4d0a30af97fad9 Mon Sep 17 00:00:00 2001 From: bsongis Date: Tue, 4 Mar 2014 10:50:15 +0100 Subject: [PATCH 014/285] 2 other files removed --- radio/bootloader/Makefile | 24 +- radio/bootloader/ccsbcs.c | 540 -------------------------------------- radio/bootloader/misc.c | 249 ------------------ 3 files changed, 12 insertions(+), 801 deletions(-) delete mode 100644 radio/bootloader/ccsbcs.c delete mode 100644 radio/bootloader/misc.c diff --git a/radio/bootloader/Makefile b/radio/bootloader/Makefile index 9971b9d5b..6c6944ed2 100644 --- a/radio/bootloader/Makefile +++ b/radio/bootloader/Makefile @@ -115,8 +115,8 @@ SRC = system_stm32f2xx.c \ ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rcc.c \ ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_gpio.c \ ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_spi.c \ - misc.c \ - ccsbcs.c \ + ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/misc.c \ + ../src/FatFs/option/ccsbcs.c \ ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/src/usb_core.c \ ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/src/usb_dcd.c \ ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/src/usb_dcd_int.c \ @@ -131,17 +131,17 @@ SRC = system_stm32f2xx.c \ ../src/targets/taranis/usb_bsp.c CPPSRC = ../src/targets/taranis/aspi.cpp \ - lcd_driver.cpp \ - driversboot.cpp \ - logicioboot.cpp \ - ff.cpp \ - x9ddiskio.cpp \ - ../src/targets/taranis/usbd_usr.cpp \ - usbd_storage_msd.cpp \ + lcd_driver.cpp \ + driversboot.cpp \ + logicioboot.cpp \ + ff.cpp \ + x9ddiskio.cpp \ + ../src/targets/taranis/usbd_usr.cpp \ + usbd_storage_msd.cpp \ i2c_ee.cpp \ - lcdboot.cpp \ - power.cpp \ - boot.cpp + lcdboot.cpp \ + power.cpp \ + boot.cpp # List ASM source files here ASRC = startup_stm32f2xx.s diff --git a/radio/bootloader/ccsbcs.c b/radio/bootloader/ccsbcs.c deleted file mode 100644 index e5634173b..000000000 --- a/radio/bootloader/ccsbcs.c +++ /dev/null @@ -1,540 +0,0 @@ -/*------------------------------------------------------------------------*/ -/* Unicode - Local code bidirectional converter (C)ChaN, 2012 */ -/* (SBCS code pages) */ -/*------------------------------------------------------------------------*/ -/* 437 U.S. (OEM) -/ 720 Arabic (OEM) -/ 1256 Arabic (Windows) -/ 737 Greek (OEM) -/ 1253 Greek (Windows) -/ 1250 Central Europe (Windows) -/ 775 Baltic (OEM) -/ 1257 Baltic (Windows) -/ 850 Multilingual Latin 1 (OEM) -/ 852 Latin 2 (OEM) -/ 1252 Latin 1 (Windows) -/ 855 Cyrillic (OEM) -/ 1251 Cyrillic (Windows) -/ 866 Russian (OEM) -/ 857 Turkish (OEM) -/ 1254 Turkish (Windows) -/ 858 Multilingual Latin 1 + Euro (OEM) -/ 862 Hebrew (OEM) -/ 1255 Hebrew (Windows) -/ 874 Thai (OEM, Windows) -/ 1258 Vietnam (OEM, Windows) -*/ - -#include "ff.h" - - -#if _CODE_PAGE == 437 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP437(0x80-0xFF) to Unicode conversion table */ - 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, - 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, - 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, - 0x00FF, 0x00D6, 0x00DC, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, - 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, - 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, - 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, - 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, - 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, - 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 720 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP720(0x80-0xFF) to Unicode conversion table */ - 0x0000, 0x0000, 0x00E9, 0x00E2, 0x0000, 0x00E0, 0x0000, 0x00E7, - 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0651, 0x0652, 0x00F4, 0x00A4, 0x0640, 0x00FB, 0x00F9, - 0x0621, 0x0622, 0x0623, 0x0624, 0x00A3, 0x0625, 0x0626, 0x0627, - 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, - 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, - 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, - 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x0636, 0x0637, 0x0638, 0x0639, 0x063A, 0x0641, 0x00B5, 0x0642, - 0x0643, 0x0644, 0x0645, 0x0646, 0x0647, 0x0648, 0x0649, 0x064A, - 0x2261, 0x064B, 0x064C, 0x064D, 0x064E, 0x064F, 0x0650, 0x2248, - 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 737 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP737(0x80-0xFF) to Unicode conversion table */ - 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x0398, - 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, 0x03A0, - 0x03A1, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, - 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, 0x03B8, - 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, - 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x03C5, 0x03C6, 0x03C7, 0x03C8, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, - 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, - 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x03C9, 0x03AC, 0x03AD, 0x03AE, 0x03CA, 0x03AF, 0x03CC, 0x03CD, - 0x03CB, 0x03CE, 0x0386, 0x0388, 0x0389, 0x038A, 0x038C, 0x038E, - 0x038F, 0x00B1, 0x2265, 0x2264, 0x03AA, 0x03AB, 0x00F7, 0x2248, - 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 775 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP775(0x80-0xFF) to Unicode conversion table */ - 0x0106, 0x00FC, 0x00E9, 0x0101, 0x00E4, 0x0123, 0x00E5, 0x0107, - 0x0142, 0x0113, 0x0156, 0x0157, 0x012B, 0x0179, 0x00C4, 0x00C5, - 0x00C9, 0x00E6, 0x00C6, 0x014D, 0x00F6, 0x0122, 0x00A2, 0x015A, - 0x015B, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x00A4, - 0x0100, 0x012A, 0x00F3, 0x017B, 0x017C, 0x017A, 0x201D, 0x00A6, - 0x00A9, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x0141, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0104, 0x010C, 0x0118, - 0x0116, 0x2563, 0x2551, 0x2557, 0x255D, 0x012E, 0x0160, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0172, 0x016A, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x017D, - 0x0105, 0x010D, 0x0119, 0x0117, 0x012F, 0x0161, 0x0173, 0x016B, - 0x017E, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x00D3, 0x00DF, 0x014C, 0x0143, 0x00F5, 0x00D5, 0x00B5, 0x0144, - 0x0136, 0x0137, 0x013B, 0x013C, 0x0146, 0x0112, 0x0145, 0x2019, - 0x00AD, 0x00B1, 0x201C, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x201E, - 0x00B0, 0x2219, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 850 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP850(0x80-0xFF) to Unicode conversion table */ - 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, - 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, - 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, - 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, - 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, - 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, - 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x0131, 0x00CD, 0x00CE, - 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, - 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, - 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4, - 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, - 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 852 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP852(0x80-0xFF) to Unicode conversion table */ - 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x016F, 0x0107, 0x00E7, - 0x0142, 0x00EB, 0x0150, 0x0151, 0x00EE, 0x0179, 0x00C4, 0x0106, - 0x00C9, 0x0139, 0x013A, 0x00F4, 0x00F6, 0x013D, 0x013E, 0x015A, - 0x015B, 0x00D6, 0x00DC, 0x0164, 0x0165, 0x0141, 0x00D7, 0x010D, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x0104, 0x0105, 0x017D, 0x017E, - 0x0118, 0x0119, 0x00AC, 0x017A, 0x010C, 0x015F, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x011A, - 0x015E, 0x2563, 0x2551, 0x2557, 0x255D, 0x017B, 0x017C, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0102, 0x0103, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, - 0x0111, 0x0110, 0x010E, 0x00CB, 0x010F, 0x0147, 0x00CD, 0x00CE, - 0x011B, 0x2518, 0x250C, 0x2588, 0x2584, 0x0162, 0x016E, 0x2580, - 0x00D3, 0x00DF, 0x00D4, 0x0143, 0x0144, 0x0148, 0x0160, 0x0161, - 0x0154, 0x00DA, 0x0155, 0x0170, 0x00FD, 0x00DD, 0x0163, 0x00B4, - 0x00AD, 0x02DD, 0x02DB, 0x02C7, 0x02D8, 0x00A7, 0x00F7, 0x00B8, - 0x00B0, 0x00A8, 0x02D9, 0x0171, 0x0158, 0x0159, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 855 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP855(0x80-0xFF) to Unicode conversion table */ - 0x0452, 0x0402, 0x0453, 0x0403, 0x0451, 0x0401, 0x0454, 0x0404, - 0x0455, 0x0405, 0x0456, 0x0406, 0x0457, 0x0407, 0x0458, 0x0408, - 0x0459, 0x0409, 0x045A, 0x040A, 0x045B, 0x040B, 0x045C, 0x040C, - 0x045E, 0x040E, 0x045F, 0x040F, 0x044E, 0x042E, 0x044A, 0x042A, - 0x0430, 0x0410, 0x0431, 0x0411, 0x0446, 0x0426, 0x0434, 0x0414, - 0x0435, 0x0415, 0x0444, 0x0424, 0x0433, 0x0413, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0445, 0x0425, 0x0438, - 0x0418, 0x2563, 0x2551, 0x2557, 0x255D, 0x0439, 0x0419, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x043A, 0x041A, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, - 0x043B, 0x041B, 0x043C, 0x041C, 0x043D, 0x041D, 0x043E, 0x041E, - 0x043F, 0x2518, 0x250C, 0x2588, 0x2584, 0x041F, 0x044F, 0x2580, - 0x042F, 0x0440, 0x0420, 0x0441, 0x0421, 0x0442, 0x0422, 0x0443, - 0x0423, 0x0436, 0x0416, 0x0432, 0x0412, 0x044C, 0x042C, 0x2116, - 0x00AD, 0x044B, 0x042B, 0x0437, 0x0417, 0x0448, 0x0428, 0x044D, - 0x042D, 0x0449, 0x0429, 0x0447, 0x0427, 0x00A7, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 857 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP857(0x80-0xFF) to Unicode conversion table */ - 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, - 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0131, 0x00C4, 0x00C5, - 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, - 0x0130, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x015E, 0x015F, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x011E, 0x011F, - 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, - 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, - 0x00BA, 0x00AA, 0x00CA, 0x00CB, 0x00C8, 0x0000, 0x00CD, 0x00CE, - 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, - 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x0000, - 0x00D7, 0x00DA, 0x00DB, 0x00D9, 0x00EC, 0x00FF, 0x00AF, 0x00B4, - 0x00AD, 0x00B1, 0x0000, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, - 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 858 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP858(0x80-0xFF) to Unicode conversion table */ - 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, - 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, - 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, - 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, - 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, - 0x00A9, 0x2563, 0x2551, 0x2557, 0x2550, 0x00A2, 0x00A5, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, - 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x20AC, 0x00CD, 0x00CE, - 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00C6, 0x00CC, 0x2580, - 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, - 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4, - 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, - 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 862 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP862(0x80-0xFF) to Unicode conversion table */ - 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, - 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF, - 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, - 0x05E8, 0x05E9, 0x05EA, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, - 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, - 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, - 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, - 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, - 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, - 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 866 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP866(0x80-0xFF) to Unicode conversion table */ - 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, - 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, - 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, - 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, - 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, - 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, - 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, - 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, - 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F, - 0x0401, 0x0451, 0x0404, 0x0454, 0x0407, 0x0457, 0x040E, 0x045E, - 0x00B0, 0x2219, 0x00B7, 0x221A, 0x2116, 0x00A4, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 874 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP874(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x0000, 0x0000, 0x0000, 0x2026, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x00A0, 0x0E01, 0x0E02, 0x0E03, 0x0E04, 0x0E05, 0x0E06, 0x0E07, - 0x0E08, 0x0E09, 0x0E0A, 0x0E0B, 0x0E0C, 0x0E0D, 0x0E0E, 0x0E0F, - 0x0E10, 0x0E11, 0x0E12, 0x0E13, 0x0E14, 0x0E15, 0x0E16, 0x0E17, - 0x0E18, 0x0E19, 0x0E1A, 0x0E1B, 0x0E1C, 0x0E1D, 0x0E1E, 0x0E1F, - 0x0E20, 0x0E21, 0x0E22, 0x0E23, 0x0E24, 0x0E25, 0x0E26, 0x0E27, - 0x0E28, 0x0E29, 0x0E2A, 0x0E2B, 0x0E2C, 0x0E2D, 0x0E2E, 0x0E2F, - 0x0E30, 0x0E31, 0x0E32, 0x0E33, 0x0E34, 0x0E35, 0x0E36, 0x0E37, - 0x0E38, 0x0E39, 0x0E3A, 0x0000, 0x0000, 0x0000, 0x0000, 0x0E3F, - 0x0E40, 0x0E41, 0x0E42, 0x0E43, 0x0E44, 0x0E45, 0x0E46, 0x0E47, - 0x0E48, 0x0E49, 0x0E4A, 0x0E4B, 0x0E4C, 0x0E4D, 0x0E4E, 0x0E4F, - 0x0E50, 0x0E51, 0x0E52, 0x0E53, 0x0E54, 0x0E55, 0x0E56, 0x0E57, - 0x0E58, 0x0E59, 0x0E5A, 0x0E5B, 0x0000, 0x0000, 0x0000, 0x0000 -}; - -#elif _CODE_PAGE == 1250 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1250(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021, - 0x0000, 0x2030, 0x0160, 0x2039, 0x015A, 0x0164, 0x017D, 0x0179, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x0000, 0x2122, 0x0161, 0x203A, 0x015B, 0x0165, 0x017E, 0x017A, - 0x00A0, 0x02C7, 0x02D8, 0x0141, 0x00A4, 0x0104, 0x00A6, 0x00A7, - 0x00A8, 0x00A9, 0x015E, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x017B, - 0x00B0, 0x00B1, 0x02DB, 0x0142, 0x00B4, 0x00B5, 0x00B6, 0x00B7, - 0x00B8, 0x0105, 0x015F, 0x00BB, 0x013D, 0x02DD, 0x013E, 0x017C, - 0x0154, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x0139, 0x0106, 0x00C7, - 0x010C, 0x00C9, 0x0118, 0x00CB, 0x011A, 0x00CD, 0x00CE, 0x010E, - 0x0110, 0x0143, 0x0147, 0x00D3, 0x00D4, 0x0150, 0x00D6, 0x00D7, - 0x0158, 0x016E, 0x00DA, 0x0170, 0x00DC, 0x00DD, 0x0162, 0x00DF, - 0x0155, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x013A, 0x0107, 0x00E7, - 0x010D, 0x00E9, 0x0119, 0x00EB, 0x011B, 0x00ED, 0x00EE, 0x010F, - 0x0111, 0x0144, 0x0148, 0x00F3, 0x00F4, 0x0151, 0x00F6, 0x00F7, - 0x0159, 0x016F, 0x00FA, 0x0171, 0x00FC, 0x00FD, 0x0163, 0x02D9 -}; - -#elif _CODE_PAGE == 1251 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1251(0x80-0xFF) to Unicode conversion table */ - 0x0402, 0x0403, 0x201A, 0x0453, 0x201E, 0x2026, 0x2020, 0x2021, - 0x20AC, 0x2030, 0x0409, 0x2039, 0x040A, 0x040C, 0x040B, 0x040F, - 0x0452, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x0000, 0x2111, 0x0459, 0x203A, 0x045A, 0x045C, 0x045B, 0x045F, - 0x00A0, 0x040E, 0x045E, 0x0408, 0x00A4, 0x0490, 0x00A6, 0x00A7, - 0x0401, 0x00A9, 0x0404, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x0407, - 0x00B0, 0x00B1, 0x0406, 0x0456, 0x0491, 0x00B5, 0x00B6, 0x00B7, - 0x0451, 0x2116, 0x0454, 0x00BB, 0x0458, 0x0405, 0x0455, 0x0457, - 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, - 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, - 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, - 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, - 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, - 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, - 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, - 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F -}; - -#elif _CODE_PAGE == 1252 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1252(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, - 0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x017D, 0x0000, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x017E, 0x0178, - 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, - 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, - 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, - 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, - 0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7, - 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF, - 0x00D0, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7, - 0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x00DD, 0x00DE, 0x00DF, - 0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7, - 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF, - 0x00F0, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7, - 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x00FD, 0x00FE, 0x00FF -}; - -#elif _CODE_PAGE == 1253 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1253(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, - 0x0000, 0x2030, 0x0000, 0x2039, 0x000C, 0x0000, 0x0000, 0x0000, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000, - 0x00A0, 0x0385, 0x0386, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, - 0x00A8, 0x00A9, 0x0000, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x2015, - 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x0384, 0x00B5, 0x00B6, 0x00B7, - 0x0388, 0x0389, 0x038A, 0x00BB, 0x038C, 0x00BD, 0x038E, 0x038F, - 0x0390, 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, - 0x0398, 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, - 0x03A0, 0x03A1, 0x0000, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, - 0x03A8, 0x03A9, 0x03AA, 0x03AD, 0x03AC, 0x03AD, 0x03AE, 0x03AF, - 0x03B0, 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, - 0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, - 0x03C0, 0x03C1, 0x03C2, 0x03C3, 0x03C4, 0x03C5, 0x03C6, 0x03C7, - 0x03C8, 0x03C9, 0x03CA, 0x03CB, 0x03CC, 0x03CD, 0x03CE, 0x0000 -}; - -#elif _CODE_PAGE == 1254 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1254(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x210A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, - 0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178, - 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, - 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, - 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, - 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, - 0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7, - 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF, - 0x011E, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7, - 0x00D8, 0x00D9, 0x00DA, 0x00BD, 0x00DC, 0x0130, 0x015E, 0x00DF, - 0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7, - 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF, - 0x011F, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7, - 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x0131, 0x015F, 0x00FF -}; - -#elif _CODE_PAGE == 1255 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1255(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, - 0x02C6, 0x2030, 0x0000, 0x2039, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x02DC, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000, - 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, - 0x00A8, 0x00A9, 0x00D7, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, - 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, - 0x00B8, 0x00B9, 0x00F7, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, - 0x05B0, 0x05B1, 0x05B2, 0x05B3, 0x05B4, 0x05B5, 0x05B6, 0x05B7, - 0x05B8, 0x05B9, 0x0000, 0x05BB, 0x05BC, 0x05BD, 0x05BE, 0x05BF, - 0x05C0, 0x05C1, 0x05C2, 0x05C3, 0x05F0, 0x05F1, 0x05F2, 0x05F3, - 0x05F4, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, - 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF, - 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, - 0x05E8, 0x05E9, 0x05EA, 0x0000, 0x0000, 0x200E, 0x200F, 0x0000 -}; - -#elif _CODE_PAGE == 1256 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1256(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x067E, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, - 0x02C6, 0x2030, 0x0679, 0x2039, 0x0152, 0x0686, 0x0698, 0x0688, - 0x06AF, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x06A9, 0x2122, 0x0691, 0x203A, 0x0153, 0x200C, 0x200D, 0x06BA, - 0x00A0, 0x060C, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, - 0x00A8, 0x00A9, 0x06BE, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, - 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, - 0x00B8, 0x00B9, 0x061B, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x061F, - 0x06C1, 0x0621, 0x0622, 0x0623, 0x0624, 0x0625, 0x0626, 0x0627, - 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, - 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x0636, 0x00D7, - 0x0637, 0x0638, 0x0639, 0x063A, 0x0640, 0x0640, 0x0642, 0x0643, - 0x00E0, 0x0644, 0x00E2, 0x0645, 0x0646, 0x0647, 0x0648, 0x00E7, - 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0649, 0x064A, 0x00EE, 0x00EF, - 0x064B, 0x064C, 0x064D, 0x064E, 0x00F4, 0x064F, 0x0650, 0x00F7, - 0x0651, 0x00F9, 0x0652, 0x00FB, 0x00FC, 0x200E, 0x200F, 0x06D2 -} - -#elif _CODE_PAGE == 1257 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1257(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021, - 0x0000, 0x2030, 0x0000, 0x2039, 0x0000, 0x00A8, 0x02C7, 0x00B8, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x00AF, 0x02DB, 0x0000, - 0x00A0, 0x0000, 0x00A2, 0x00A3, 0x00A4, 0x0000, 0x00A6, 0x00A7, - 0x00D8, 0x00A9, 0x0156, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, - 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, - 0x00B8, 0x00B9, 0x0157, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00E6, - 0x0104, 0x012E, 0x0100, 0x0106, 0x00C4, 0x00C5, 0x0118, 0x0112, - 0x010C, 0x00C9, 0x0179, 0x0116, 0x0122, 0x0136, 0x012A, 0x013B, - 0x0160, 0x0143, 0x0145, 0x00D3, 0x014C, 0x00D5, 0x00D6, 0x00D7, - 0x0172, 0x0141, 0x015A, 0x016A, 0x00DC, 0x017B, 0x017D, 0x00DF, - 0x0105, 0x012F, 0x0101, 0x0107, 0x00E4, 0x00E5, 0x0119, 0x0113, - 0x010D, 0x00E9, 0x017A, 0x0117, 0x0123, 0x0137, 0x012B, 0x013C, - 0x0161, 0x0144, 0x0146, 0x00F3, 0x014D, 0x00F5, 0x00F6, 0x00F7, - 0x0173, 0x014E, 0x015B, 0x016B, 0x00FC, 0x017C, 0x017E, 0x02D9 -}; - -#elif _CODE_PAGE == 1258 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1258(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, - 0x02C6, 0x2030, 0x0000, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x02DC, 0x2122, 0x0000, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178, - 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, - 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, - 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, - 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, - 0x00C0, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x00C5, 0x00C6, 0x00C7, - 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x0300, 0x00CD, 0x00CE, 0x00CF, - 0x0110, 0x00D1, 0x0309, 0x00D3, 0x00D4, 0x01A0, 0x00D6, 0x00D7, - 0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x01AF, 0x0303, 0x00DF, - 0x00E0, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x00E5, 0x00E6, 0x00E7, - 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0301, 0x00ED, 0x00EE, 0x00EF, - 0x0111, 0x00F1, 0x0323, 0x00F3, 0x00F4, 0x01A1, 0x00F6, 0x00F7, - 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x01B0, 0x20AB, 0x00FF -}; - -#endif - - -#if !_TBLDEF || !_USE_LFN -#error This file is not needed in current configuration. Remove from the project. -#endif - - -WCHAR ff_convert ( /* Converted character, Returns zero on error */ - WCHAR chr, /* Character code to be converted */ - UINT dir /* 0: Unicode to OEMCP, 1: OEMCP to Unicode */ -) -{ - WCHAR c; - - - if (chr < 0x80) { /* ASCII */ - c = chr; - - } else { - if (dir) { /* OEMCP to Unicode */ - c = (chr >= 0x100) ? 0 : Tbl[chr - 0x80]; - - } else { /* Unicode to OEMCP */ - for (c = 0; c < 0x80; c++) { - if (chr == Tbl[c]) break; - } - c = (c + 0x80) & 0xFF; - } - } - - return c; -} - - -WCHAR ff_wtoupper ( /* Upper converted character */ - WCHAR chr /* Input character */ -) -{ - static const WCHAR tbl_lower[] = { 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0xA1, 0x00A2, 0x00A3, 0x00A5, 0x00AC, 0x00AF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0x0FF, 0x101, 0x103, 0x105, 0x107, 0x109, 0x10B, 0x10D, 0x10F, 0x111, 0x113, 0x115, 0x117, 0x119, 0x11B, 0x11D, 0x11F, 0x121, 0x123, 0x125, 0x127, 0x129, 0x12B, 0x12D, 0x12F, 0x131, 0x133, 0x135, 0x137, 0x13A, 0x13C, 0x13E, 0x140, 0x142, 0x144, 0x146, 0x148, 0x14B, 0x14D, 0x14F, 0x151, 0x153, 0x155, 0x157, 0x159, 0x15B, 0x15D, 0x15F, 0x161, 0x163, 0x165, 0x167, 0x169, 0x16B, 0x16D, 0x16F, 0x171, 0x173, 0x175, 0x177, 0x17A, 0x17C, 0x17E, 0x192, 0x3B1, 0x3B2, 0x3B3, 0x3B4, 0x3B5, 0x3B6, 0x3B7, 0x3B8, 0x3B9, 0x3BA, 0x3BB, 0x3BC, 0x3BD, 0x3BE, 0x3BF, 0x3C0, 0x3C1, 0x3C3, 0x3C4, 0x3C5, 0x3C6, 0x3C7, 0x3C8, 0x3C9, 0x3CA, 0x430, 0x431, 0x432, 0x433, 0x434, 0x435, 0x436, 0x437, 0x438, 0x439, 0x43A, 0x43B, 0x43C, 0x43D, 0x43E, 0x43F, 0x440, 0x441, 0x442, 0x443, 0x444, 0x445, 0x446, 0x447, 0x448, 0x449, 0x44A, 0x44B, 0x44C, 0x44D, 0x44E, 0x44F, 0x451, 0x452, 0x453, 0x454, 0x455, 0x456, 0x457, 0x458, 0x459, 0x45A, 0x45B, 0x45C, 0x45E, 0x45F, 0x2170, 0x2171, 0x2172, 0x2173, 0x2174, 0x2175, 0x2176, 0x2177, 0x2178, 0x2179, 0x217A, 0x217B, 0x217C, 0x217D, 0x217E, 0x217F, 0xFF41, 0xFF42, 0xFF43, 0xFF44, 0xFF45, 0xFF46, 0xFF47, 0xFF48, 0xFF49, 0xFF4A, 0xFF4B, 0xFF4C, 0xFF4D, 0xFF4E, 0xFF4F, 0xFF50, 0xFF51, 0xFF52, 0xFF53, 0xFF54, 0xFF55, 0xFF56, 0xFF57, 0xFF58, 0xFF59, 0xFF5A, 0 }; - static const WCHAR tbl_upper[] = { 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x21, 0xFFE0, 0xFFE1, 0xFFE5, 0xFFE2, 0xFFE3, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0x178, 0x100, 0x102, 0x104, 0x106, 0x108, 0x10A, 0x10C, 0x10E, 0x110, 0x112, 0x114, 0x116, 0x118, 0x11A, 0x11C, 0x11E, 0x120, 0x122, 0x124, 0x126, 0x128, 0x12A, 0x12C, 0x12E, 0x130, 0x132, 0x134, 0x136, 0x139, 0x13B, 0x13D, 0x13F, 0x141, 0x143, 0x145, 0x147, 0x14A, 0x14C, 0x14E, 0x150, 0x152, 0x154, 0x156, 0x158, 0x15A, 0x15C, 0x15E, 0x160, 0x162, 0x164, 0x166, 0x168, 0x16A, 0x16C, 0x16E, 0x170, 0x172, 0x174, 0x176, 0x179, 0x17B, 0x17D, 0x191, 0x391, 0x392, 0x393, 0x394, 0x395, 0x396, 0x397, 0x398, 0x399, 0x39A, 0x39B, 0x39C, 0x39D, 0x39E, 0x39F, 0x3A0, 0x3A1, 0x3A3, 0x3A4, 0x3A5, 0x3A6, 0x3A7, 0x3A8, 0x3A9, 0x3AA, 0x410, 0x411, 0x412, 0x413, 0x414, 0x415, 0x416, 0x417, 0x418, 0x419, 0x41A, 0x41B, 0x41C, 0x41D, 0x41E, 0x41F, 0x420, 0x421, 0x422, 0x423, 0x424, 0x425, 0x426, 0x427, 0x428, 0x429, 0x42A, 0x42B, 0x42C, 0x42D, 0x42E, 0x42F, 0x401, 0x402, 0x403, 0x404, 0x405, 0x406, 0x407, 0x408, 0x409, 0x40A, 0x40B, 0x40C, 0x40E, 0x40F, 0x2160, 0x2161, 0x2162, 0x2163, 0x2164, 0x2165, 0x2166, 0x2167, 0x2168, 0x2169, 0x216A, 0x216B, 0x216C, 0x216D, 0x216E, 0x216F, 0xFF21, 0xFF22, 0xFF23, 0xFF24, 0xFF25, 0xFF26, 0xFF27, 0xFF28, 0xFF29, 0xFF2A, 0xFF2B, 0xFF2C, 0xFF2D, 0xFF2E, 0xFF2F, 0xFF30, 0xFF31, 0xFF32, 0xFF33, 0xFF34, 0xFF35, 0xFF36, 0xFF37, 0xFF38, 0xFF39, 0xFF3A, 0 }; - int i; - - - for (i = 0; tbl_lower[i] && chr != tbl_lower[i]; i++) ; - - return tbl_lower[i] ? tbl_upper[i] : chr; -} diff --git a/radio/bootloader/misc.c b/radio/bootloader/misc.c deleted file mode 100644 index 7d011629b..000000000 --- a/radio/bootloader/misc.c +++ /dev/null @@ -1,249 +0,0 @@ -/** - ****************************************************************************** - * @file misc.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides all the miscellaneous firmware functions (add-on - * to CMSIS functions). - * - * @verbatim - * - * =================================================================== - * How to configure Interrupts using driver - * =================================================================== - * - * This section provide functions allowing to configure the NVIC interrupts (IRQ). - * The Cortex-M3 exceptions are managed by CMSIS functions. - * - * 1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig() - * function according to the following table. - - * The table below gives the allowed values of the pre-emption priority and subpriority according - * to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function - * ========================================================================================================================== - * NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description - * ========================================================================================================================== - * NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority - * | | | 4 bits for subpriority - * -------------------------------------------------------------------------------------------------------------------------- - * NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority - * | | | 3 bits for subpriority - * -------------------------------------------------------------------------------------------------------------------------- - * NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority - * | | | 2 bits for subpriority - * -------------------------------------------------------------------------------------------------------------------------- - * NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority - * | | | 1 bits for subpriority - * -------------------------------------------------------------------------------------------------------------------------- - * NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority - * | | | 0 bits for subpriority - * ========================================================================================================================== - * - * 2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init() - * - * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. - * The pending IRQ priority will be managed only by the subpriority. - * - * @note IRQ priority order (sorted by highest to lowest priority): - * - Lowest pre-emption priority - * - Lowest subpriority - * - Lowest hardware priority (IRQ number) - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "misc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup MISC - * @brief MISC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup MISC_Private_Functions - * @{ - */ - -/** - * @brief Configures the priority grouping: pre-emption priority and subpriority. - * @param NVIC_PriorityGroup: specifies the priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority - * 4 bits for subpriority - * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority - * 3 bits for subpriority - * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority - * 2 bits for subpriority - * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority - * 1 bits for subpriority - * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority - * 0 bits for subpriority - * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. - * The pending IRQ priority will be managed only by the subpriority. - * @retval None - */ -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); - - /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ - SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; -} - -/** - * @brief Initializes the NVIC peripheral according to the specified - * parameters in the NVIC_InitStruct. - * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() - * function should be called before. - * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains - * the configuration information for the specified NVIC peripheral. - * @retval None - */ -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) -{ - uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); - assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); - assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); - - if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) - { - /* Compute the Corresponding IRQ Priority --------------------------------*/ - tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; - tmppre = (0x4 - tmppriority); - tmpsub = tmpsub >> tmppriority; - - tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; - tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub); - - tmppriority = tmppriority << 0x04; - - NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; - - /* Enable the Selected IRQ Channels --------------------------------------*/ - NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = - (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } - else - { - /* Disable the Selected IRQ Channels -------------------------------------*/ - NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = - (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } -} - -/** - * @brief Sets the vector table location and Offset. - * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. - * This parameter can be one of the following values: - * @arg NVIC_VectTab_RAM: Vector Table in internal SRAM. - * @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH. - * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200. - * @retval None - */ -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) -{ - /* Check the parameters */ - assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); - assert_param(IS_NVIC_OFFSET(Offset)); - - SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); -} - -/** - * @brief Selects the condition for the system to enter low power mode. - * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. - * This parameter can be one of the following values: - * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend. - * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request. - * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit. - * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_NVIC_LP(LowPowerMode)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - SCB->SCR |= LowPowerMode; - } - else - { - SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); - } -} - -/** - * @brief Configures the SysTick clock source. - * @param SysTick_CLKSource: specifies the SysTick clock source. - * This parameter can be one of the following values: - * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. - * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. - * @retval None - */ -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) -{ - /* Check the parameters */ - assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); - if (SysTick_CLKSource == SysTick_CLKSource_HCLK) - { - SysTick->CTRL |= SysTick_CLKSource_HCLK; - } - else - { - SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ From 8c06e0d8ace90fb01de1ac4c6561ab39f73a7232 Mon Sep 17 00:00:00 2001 From: bsongis Date: Tue, 4 Mar 2014 11:23:33 +0100 Subject: [PATCH 015/285] Sky9x files removed for now --- .../common/core/USBConfigurationDescriptor.c | 162 -- .../common/core/USBConfigurationDescriptor.h | 150 -- .../usb/common/core/USBDeviceDescriptor.h | 125 -- .../core/USBDeviceQualifierDescriptor.h | 89 - .../usb/common/core/USBEndpointDescriptor.c | 109 -- .../usb/common/core/USBEndpointDescriptor.h | 224 --- .../usb/common/core/USBFeatureRequest.c | 70 - .../usb/common/core/USBFeatureRequest.h | 146 -- .../usb/common/core/USBGenericDescriptor.c | 80 - .../usb/common/core/USBGenericDescriptor.h | 133 -- .../usb/common/core/USBGenericRequest.c | 138 -- .../usb/common/core/USBGenericRequest.h | 244 --- .../usb/common/core/USBGetDescriptorRequest.c | 72 - .../usb/common/core/USBGetDescriptorRequest.h | 67 - .../core/USBInterfaceAssociationDescriptor.h | 86 - .../usb/common/core/USBInterfaceDescriptor.h | 87 - .../usb/common/core/USBInterfaceRequest.c | 69 - .../usb/common/core/USBInterfaceRequest.h | 68 - .../usb/common/core/USBIrqHandler.c | 62 - .../usb/common/core/USBIrqHandler.h | 52 - .../usb/common/core/USBSetAddressRequest.c | 56 - .../usb/common/core/USBSetAddressRequest.h | 60 - .../common/core/USBSetConfigurationRequest.c | 58 - .../common/core/USBSetConfigurationRequest.h | 61 - .../usb/common/core/USBStringDescriptor.h | 74 - .../common/massstorage/MSDeviceDescriptor.h | 73 - .../massstorage/MSInterfaceDescriptor.h | 75 - radio/bootloader/usb/device/core/USBD.h | 275 --- .../usb/device/core/USBDCallbacks.c | 81 - .../usb/device/core/USBDCallbacks.h | 65 - radio/bootloader/usb/device/core/USBDDriver.c | 753 ------- radio/bootloader/usb/device/core/USBDDriver.h | 101 - .../usb/device/core/USBDDriverCallbacks.h | 61 - .../usb/device/core/USBDDriverDescriptors.h | 86 - radio/bootloader/usb/device/core/USBD_UDP.c | 1734 ----------------- radio/bootloader/usb/device/massstorage/MSD.h | 233 --- .../usb/device/massstorage/MSDDStateMachine.c | 609 ------ .../usb/device/massstorage/MSDDStateMachine.h | 264 --- .../usb/device/massstorage/MSDDriver.c | 343 ---- .../usb/device/massstorage/MSDDriver.h | 75 - .../device/massstorage/MSDDriverDescriptors.c | 395 ---- .../device/massstorage/MSDDriverDescriptors.h | 83 - .../usb/device/massstorage/MSDIOFifo.h | 135 -- .../usb/device/massstorage/MSDLun.c | 368 ---- .../usb/device/massstorage/MSDLun.h | 161 -- radio/bootloader/usb/device/massstorage/SBC.h | 653 ------- .../usb/device/massstorage/SBCMethods.c | 1624 --------------- .../usb/device/massstorage/SBCMethods.h | 111 -- 48 files changed, 10900 deletions(-) delete mode 100644 radio/bootloader/usb/common/core/USBConfigurationDescriptor.c delete mode 100644 radio/bootloader/usb/common/core/USBConfigurationDescriptor.h delete mode 100644 radio/bootloader/usb/common/core/USBDeviceDescriptor.h delete mode 100644 radio/bootloader/usb/common/core/USBDeviceQualifierDescriptor.h delete mode 100644 radio/bootloader/usb/common/core/USBEndpointDescriptor.c delete mode 100644 radio/bootloader/usb/common/core/USBEndpointDescriptor.h delete mode 100644 radio/bootloader/usb/common/core/USBFeatureRequest.c delete mode 100644 radio/bootloader/usb/common/core/USBFeatureRequest.h delete mode 100644 radio/bootloader/usb/common/core/USBGenericDescriptor.c delete mode 100644 radio/bootloader/usb/common/core/USBGenericDescriptor.h delete mode 100644 radio/bootloader/usb/common/core/USBGenericRequest.c delete mode 100644 radio/bootloader/usb/common/core/USBGenericRequest.h delete mode 100644 radio/bootloader/usb/common/core/USBGetDescriptorRequest.c delete mode 100644 radio/bootloader/usb/common/core/USBGetDescriptorRequest.h delete mode 100644 radio/bootloader/usb/common/core/USBInterfaceAssociationDescriptor.h delete mode 100644 radio/bootloader/usb/common/core/USBInterfaceDescriptor.h delete mode 100644 radio/bootloader/usb/common/core/USBInterfaceRequest.c delete mode 100644 radio/bootloader/usb/common/core/USBInterfaceRequest.h delete mode 100644 radio/bootloader/usb/common/core/USBIrqHandler.c delete mode 100644 radio/bootloader/usb/common/core/USBIrqHandler.h delete mode 100644 radio/bootloader/usb/common/core/USBSetAddressRequest.c delete mode 100644 radio/bootloader/usb/common/core/USBSetAddressRequest.h delete mode 100644 radio/bootloader/usb/common/core/USBSetConfigurationRequest.c delete mode 100644 radio/bootloader/usb/common/core/USBSetConfigurationRequest.h delete mode 100644 radio/bootloader/usb/common/core/USBStringDescriptor.h delete mode 100644 radio/bootloader/usb/common/massstorage/MSDeviceDescriptor.h delete mode 100644 radio/bootloader/usb/common/massstorage/MSInterfaceDescriptor.h delete mode 100644 radio/bootloader/usb/device/core/USBD.h delete mode 100644 radio/bootloader/usb/device/core/USBDCallbacks.c delete mode 100644 radio/bootloader/usb/device/core/USBDCallbacks.h delete mode 100644 radio/bootloader/usb/device/core/USBDDriver.c delete mode 100644 radio/bootloader/usb/device/core/USBDDriver.h delete mode 100644 radio/bootloader/usb/device/core/USBDDriverCallbacks.h delete mode 100644 radio/bootloader/usb/device/core/USBDDriverDescriptors.h delete mode 100644 radio/bootloader/usb/device/core/USBD_UDP.c delete mode 100644 radio/bootloader/usb/device/massstorage/MSD.h delete mode 100644 radio/bootloader/usb/device/massstorage/MSDDStateMachine.c delete mode 100644 radio/bootloader/usb/device/massstorage/MSDDStateMachine.h delete mode 100644 radio/bootloader/usb/device/massstorage/MSDDriver.c delete mode 100644 radio/bootloader/usb/device/massstorage/MSDDriver.h delete mode 100644 radio/bootloader/usb/device/massstorage/MSDDriverDescriptors.c delete mode 100644 radio/bootloader/usb/device/massstorage/MSDDriverDescriptors.h delete mode 100644 radio/bootloader/usb/device/massstorage/MSDIOFifo.h delete mode 100644 radio/bootloader/usb/device/massstorage/MSDLun.c delete mode 100644 radio/bootloader/usb/device/massstorage/MSDLun.h delete mode 100644 radio/bootloader/usb/device/massstorage/SBC.h delete mode 100644 radio/bootloader/usb/device/massstorage/SBCMethods.c delete mode 100644 radio/bootloader/usb/device/massstorage/SBCMethods.h diff --git a/radio/bootloader/usb/common/core/USBConfigurationDescriptor.c b/radio/bootloader/usb/common/core/USBConfigurationDescriptor.c deleted file mode 100644 index 7dd995c62..000000000 --- a/radio/bootloader/usb/common/core/USBConfigurationDescriptor.c +++ /dev/null @@ -1,162 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBConfigurationDescriptor implementation - - About: Purpose - Implementation of the USBConfigurationDescriptor class. -*/ - -//----------------------------------------------------------------------------- -// Headers -//----------------------------------------------------------------------------- - -#include "USBConfigurationDescriptor.h" - -//----------------------------------------------------------------------------- -// Exported functions -//----------------------------------------------------------------------------- - -//----------------------------------------------------------------------------- -/// Returns the total length of a configuration, i.e. including the -/// descriptors following it. -/// \param configuration Pointer to a USBConfigurationDescriptor instance. -/// \return Total length (in bytes) of the configuration. -//----------------------------------------------------------------------------- -unsigned int USBConfigurationDescriptor_GetTotalLength( - const USBConfigurationDescriptor *configuration) -{ - return configuration->wTotalLength; -} - -//----------------------------------------------------------------------------- -/// Returns the number of interfaces in a configuration. -/// \param configuration Pointer to a USBConfigurationDescriptor instance. -/// \return Number of interfaces in configuration. -//----------------------------------------------------------------------------- -unsigned char USBConfigurationDescriptor_GetNumInterfaces( - const USBConfigurationDescriptor *configuration) -{ - return configuration->bNumInterfaces; -} - -//----------------------------------------------------------------------------- -/// Indicates if the device is self-powered when in a given configuration. -/// \param configuration Pointer to a USBConfigurationDescriptor instance. -/// \return 1 if the device is self-powered when in the given configuration; -/// otherwise 0. -//----------------------------------------------------------------------------- -unsigned char USBConfigurationDescriptor_IsSelfPowered( - const USBConfigurationDescriptor *configuration) -{ - if ((configuration->bmAttributes & (1 << 6)) != 0) { - - return 1; - } - else { - - return 0; - } -} - -//----------------------------------------------------------------------------- -/// Parses the given Configuration descriptor (followed by relevant -/// interface, endpoint and class-specific descriptors) into three arrays. -/// *Each array must have its size equal or greater to the number of -/// descriptors it stores plus one*. A null-value is inserted after the last -/// descriptor of each type to indicate the array end. -/// -/// Note that if the pointer to an array is null (0), nothing is stored in -/// it. -/// \param configuration Pointer to the start of the whole Configuration -/// descriptor. -/// \param interfaces Pointer to the Interface descriptor array. -/// \param endpoints Pointer to the Endpoint descriptor array. -/// \param others Pointer to the class-specific descriptor array. -//----------------------------------------------------------------------------- -void USBConfigurationDescriptor_Parse( - const USBConfigurationDescriptor *configuration, - USBInterfaceDescriptor **interfaces, - USBEndpointDescriptor **endpoints, - USBGenericDescriptor **others) -{ - // Get size of configuration to parse - int size = USBConfigurationDescriptor_GetTotalLength(configuration); - size -= sizeof(USBConfigurationDescriptor); - - // Start parsing descriptors - USBGenericDescriptor *descriptor = (USBGenericDescriptor *) configuration; - while (size > 0) { - - // Get next descriptor - descriptor = USBGenericDescriptor_GetNextDescriptor(descriptor); - size -= USBGenericDescriptor_GetLength(descriptor); - - // Store descriptor in correponding array - if (USBGenericDescriptor_GetType(descriptor) - == USBGenericDescriptor_INTERFACE) { - - if (interfaces) { - - *interfaces = (USBInterfaceDescriptor *) descriptor; - interfaces++; - } - } - else if (USBGenericDescriptor_GetType(descriptor) - == USBGenericDescriptor_ENDPOINT) { - - if (endpoints) { - - *endpoints = (USBEndpointDescriptor *) descriptor; - endpoints++; - } - } - else if (others) { - - *others = descriptor; - others++; - } - } - - // Null-terminate arrays - if (interfaces) { - - *interfaces = 0; - } - if (endpoints) { - - *endpoints = 0; - } - if (others) { - - *others = 0; - } -} - diff --git a/radio/bootloader/usb/common/core/USBConfigurationDescriptor.h b/radio/bootloader/usb/common/core/USBConfigurationDescriptor.h deleted file mode 100644 index b7a867d64..000000000 --- a/radio/bootloader/usb/common/core/USBConfigurationDescriptor.h +++ /dev/null @@ -1,150 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - !!!Purpose - - Definitions and methods for USB configuration descriptor structures - described by the USB specification. - - !!!Usage - - -# Declare USBConfigurationDescriptor instance as a part - of the configuration descriptors of a USB device. - -# To get useful information (field values) from the defined USB device - configuration descriptor, use - - USBConfigurationDescriptor_GetTotalLength - - USBConfigurationDescriptor_GetNumInterfaces - - USBConfigurationDescriptor_IsSelfPowered - -# To pase the defined USB device configuration descriptor, use - - USBConfigurationDescriptor_Parse -*/ - -#ifndef USBCONFIGURATIONDESCRIPTOR_H -#define USBCONFIGURATIONDESCRIPTOR_H - -//----------------------------------------------------------------------------- -// Headers -//----------------------------------------------------------------------------- - -#include "USBGenericDescriptor.h" -#include "USBInterfaceDescriptor.h" -#include "USBEndpointDescriptor.h" - -//----------------------------------------------------------------------------- -// Definitions -//----------------------------------------------------------------------------- - -//----------------------------------------------------------------------------- -/// \page "USB device Attributes" -/// -/// This page lists the codes of the usb attributes. -/// -/// !Attributes -/// - USBConfigurationDescriptor_BUSPOWERED_NORWAKEUP -/// - USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP -/// - USBConfigurationDescriptor_BUSPOWERED_RWAKEUP -/// - USBConfigurationDescriptor_SELFPOWERED_RWAKEUP -/// - USBConfigurationDescriptor_POWER - -/// Device is bus-powered and not support remote wake-up. -#define USBConfigurationDescriptor_BUSPOWERED_NORWAKEUP 0x80 -/// Device is self-powered and not support remote wake-up. -#define USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP 0xC0 -/// Device is bus-powered and supports remote wake-up. -#define USBConfigurationDescriptor_BUSPOWERED_RWAKEUP 0xA0 -/// Device is self-powered and supports remote wake-up. -#define USBConfigurationDescriptor_SELFPOWERED_RWAKEUP 0xE0 - -/// Calculates the value of the power consumption field given the value in mA. -/// \param power The power consumption value in mA -/// \return The value that should be set to the field in descriptor -#define USBConfigurationDescriptor_POWER(power) (power / 2) -//----------------------------------------------------------------------------- - -//----------------------------------------------------------------------------- -// Types -//----------------------------------------------------------------------------- - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -//----------------------------------------------------------------------------- -/// USB standard configuration descriptor structure. -//----------------------------------------------------------------------------- -typedef struct { - - /// Size of the descriptor in bytes. - unsigned char bLength; - /// Descriptor type (USBDESC_CONFIGURATION of "USB Descriptor types"). - unsigned char bDescriptorType; - /// Length of all descriptors returned along with this configuration - /// descriptor. - unsigned short wTotalLength; - /// Number of interfaces in this configuration. - unsigned char bNumInterfaces; - /// Value for selecting this configuration. - unsigned char bConfigurationValue; - /// Index of the configuration string descriptor. - unsigned char iConfiguration; - /// Configuration characteristics. - unsigned char bmAttributes; - /// Maximum power consumption of the device when in this configuration. - unsigned char bMaxPower; - -} __attribute__ ((packed)) USBConfigurationDescriptor; // GCC - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -//----------------------------------------------------------------------------- -// Exported functions -//----------------------------------------------------------------------------- - -extern unsigned int USBConfigurationDescriptor_GetTotalLength( - const USBConfigurationDescriptor *configuration); - -extern unsigned char USBConfigurationDescriptor_GetNumInterfaces( - const USBConfigurationDescriptor *configuration); - -extern unsigned char USBConfigurationDescriptor_IsSelfPowered( - const USBConfigurationDescriptor *configuration); - -extern void USBConfigurationDescriptor_Parse( - const USBConfigurationDescriptor *configuration, - USBInterfaceDescriptor **interfaces, - USBEndpointDescriptor **endpoints, - USBGenericDescriptor **others); - -#endif //#ifndef USBCONFIGURATIONDESCRIPTOR_H - diff --git a/radio/bootloader/usb/common/core/USBDeviceDescriptor.h b/radio/bootloader/usb/common/core/USBDeviceDescriptor.h deleted file mode 100644 index 6b633fe99..000000000 --- a/radio/bootloader/usb/common/core/USBDeviceDescriptor.h +++ /dev/null @@ -1,125 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - !!!Purpose - - Class for manipulating USB device descriptors. - - !!!Usage - - - Declare a USBDeviceDescriptor instance as the device descriptor of a - USB device. -*/ - -#ifndef USBDEVICEDESCRIPTOR_H -#define USBDEVICEDESCRIPTOR_H - -#include -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB release numbers" -/// -/// This page lists the codes of USB release numbers. -/// -/// !Code -/// - USBDeviceDescriptor_USB2_00 - -/// The device supports USB 2.00. -#define USBDeviceDescriptor_USB2_00 0x0200 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -/// USB standard device descriptor structure. -//------------------------------------------------------------------------------ -typedef struct { - - /// Size of this descriptor in bytes. - unsigned char bLength; - /// Descriptor type (USBGenericDescriptor_DEVICE). - unsigned char bDescriptorType; - /// USB specification release number in BCD format. - unsigned short bcdUSB; - /// Device class code. - unsigned char bDeviceClass; - /// Device subclass code. - unsigned char bDeviceSubClass; - /// Device protocol code. - unsigned char bDeviceProtocol; - /// Maximum packet size of endpoint 0 (in bytes). - unsigned char bMaxPacketSize0; - /// Vendor ID. - unsigned short idVendor; - /// Product ID. - unsigned short idProduct; - /// Device release number in BCD format. - unsigned short bcdDevice; - /// Index of the manufacturer string descriptor. - unsigned char iManufacturer; - /// Index of the product string descriptor. - unsigned char iProduct; - /// Index of the serial number string descriptor. - unsigned char iSerialNumber; - /// Number of possible configurations for the device. - unsigned char bNumConfigurations; - -} __attribute__ ((packed)) USBDeviceDescriptor; // GCC - -#if defined(CHIP_USB_OTGHS) -typedef struct { - - /// Size of this descriptor in bytes. - unsigned char bLength; - /// Descriptor type (USBGenericDescriptor_OTG). - unsigned char bDescriptorType; - /// Attribute Fields D72: Reserved D1: HNP support D0: SRP support - unsigned char bmAttributes; - -} __attribute__ ((packed)) USBOtgDescriptor; // GCC -#endif - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -#endif //#ifndef USBDEVICEDESCRIPTOR_H - diff --git a/radio/bootloader/usb/common/core/USBDeviceQualifierDescriptor.h b/radio/bootloader/usb/common/core/USBDeviceQualifierDescriptor.h deleted file mode 100644 index 5632e18c5..000000000 --- a/radio/bootloader/usb/common/core/USBDeviceQualifierDescriptor.h +++ /dev/null @@ -1,89 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Class for manipulating USB device qualifier descriptors. - - !!!Usage - - - Declare a USBDeviceQualifierDescriptor instance as the device qualifier - descriptor of a USB device. -*/ - -#ifndef USBDEVICEQUALIFIERDESCRIPTOR_H -#define USBDEVICEQUALIFIERDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -/// Alternate device descriptor indicating the capabilities of the device -/// in full-speed, if currently in high-speed; or in high-speed, if it is -/// currently in full-speed. Only relevant for devices supporting the -/// high-speed mode. -//------------------------------------------------------------------------------ -typedef struct { - - /// Size of the descriptor in bytes. - unsigned char bLength; - /// Descriptor type (USBDESC_DEVICE_QUALIFIER or "USB device types"). - unsigned char bDescriptorType; - /// USB specification release number (in BCD format). - unsigned short bcdUSB; - /// Device class code. - unsigned char bDeviceClass; - /// Device subclass code. - unsigned char bDeviceSubClass; - /// Device protocol code. - unsigned char bDeviceProtocol; - /// Maximum packet size of endpoint 0. - unsigned char bMaxPacketSize0; - /// Number of possible configurations for the device. - unsigned char bNumConfigurations; - /// Reserved. - unsigned char bReserved; - -} __attribute__ ((packed)) USBDeviceQualifierDescriptor; // GCC - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -#endif //#ifndef USBDEVICEQUALIFIERDESCRIPTOR_H - diff --git a/radio/bootloader/usb/common/core/USBEndpointDescriptor.c b/radio/bootloader/usb/common/core/USBEndpointDescriptor.c deleted file mode 100644 index c60be2ac1..000000000 --- a/radio/bootloader/usb/common/core/USBEndpointDescriptor.c +++ /dev/null @@ -1,109 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBEndpointDescriptor implementation - - About: Purpose - Implementation of the USBEndpointDescriptor class. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBEndpointDescriptor.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Returns the number of an endpoint given its descriptor. -/// \param endpoint Pointer to a USBEndpointDescriptor instance. -/// \return Endpoint number. -//------------------------------------------------------------------------------ -unsigned char USBEndpointDescriptor_GetNumber( - const USBEndpointDescriptor *endpoint) -{ - return endpoint->bEndpointAddress & 0xF; -} - -//------------------------------------------------------------------------------ -/// Returns the direction of an endpoint given its descriptor. -/// \param endpoint Pointer to a USBEndpointDescriptor instance. -/// \return Endpoint direction (see ). -//------------------------------------------------------------------------------ -unsigned char USBEndpointDescriptor_GetDirection( - const USBEndpointDescriptor *endpoint) -{ - if ((endpoint->bEndpointAddress & 0x80) != 0) { - - return USBEndpointDescriptor_IN; - } - else { - - return USBEndpointDescriptor_OUT; - } -} - -//------------------------------------------------------------------------------ -/// Returns the type of an endpoint given its descriptor. -/// \param endpoint Pointer to a USBEndpointDescriptor instance. -/// \return Endpoint type (see ). -//------------------------------------------------------------------------------ -unsigned char USBEndpointDescriptor_GetType( - const USBEndpointDescriptor *endpoint) -{ - return endpoint->bmAttributes & 0x3; -} - -//------------------------------------------------------------------------------ -/// Returns the maximum size of a packet (in bytes) on an endpoint given -/// its descriptor. -/// \param endpoint - Pointer to a USBEndpointDescriptor instance. -/// \return Maximum packet size of endpoint. -//------------------------------------------------------------------------------ -unsigned short USBEndpointDescriptor_GetMaxPacketSize( - const USBEndpointDescriptor *endpoint) -{ - return endpoint->wMaxPacketSize; -} - -//------------------------------------------------------------------------------ -/// Returns the polling interval on an endpoint given its descriptor. -/// \param endpoint - Pointer to a USBEndpointDescriptor instance. -/// \return Polling interval of endpoint. -//------------------------------------------------------------------------------ -unsigned char USBEndpointDescriptor_GetInterval( - const USBEndpointDescriptor *endpoint) -{ - return endpoint->bInterval; -} - diff --git a/radio/bootloader/usb/common/core/USBEndpointDescriptor.h b/radio/bootloader/usb/common/core/USBEndpointDescriptor.h deleted file mode 100644 index 8a691eec2..000000000 --- a/radio/bootloader/usb/common/core/USBEndpointDescriptor.h +++ /dev/null @@ -1,224 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of a class for handling USB endpoint descriptors. - - !!!Usage - - -# Declare USBEndpointDescriptor instance as a part of the - configuration descriptors of a USB device. - -# To get useful information (field values) from the defined USB device - endpoint descriptor (to configure hardware for endpoints, etc), use - - USBEndpointDescriptor_GetNumber - - USBEndpointDescriptor_GetDirection - - USBEndpointDescriptor_GetType - - USBEndpointDescriptor_GetMaxPacketSize -*/ - -#ifndef USBENDPOINTDESCRIPTOR_H -#define USBENDPOINTDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Endpoint definitions" -/// -/// This page lists definitions and macro for endpoint descriptors. -/// -/// - USB Endpoint directions -/// - USBEndpointDescriptor_OUT -/// - USBEndpointDescriptor_IN -/// -/// - USB Endpoint types -/// - USBEndpointDescriptor_CONTROL -/// - USBEndpointDescriptor_ISOCHRONOUS -/// - USBEndpointDescriptor_BULK -/// - USBEndpointDescriptor_INTERRUPT -/// -/// - USB Endpoint maximun sizes -/// - USBEndpointDescriptor_MAXCTRLSIZE_FS -/// - USBEndpointDescriptor_MAXCTRLSIZE_HS -/// - USBEndpointDescriptor_MAXBULKSIZE_FS -/// - USBEndpointDescriptor_MAXBULKSIZE_HS -/// - USBEndpointDescriptor_MAXINTERRUPTSIZE_FS -/// - USBEndpointDescriptor_MAXINTERRUPTSIZE_HS -/// - USBEndpointDescriptor_MAXISOCHRONOUSSIZE_FS -/// - USBEndpointDescriptor_MAXISOCHRONOUSSIZE_HS -/// -/// - USB Endpoint address define -/// - USBEndpointDescriptor_ADDRESS -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Endpoint directions" -/// -/// This page lists definitions of USB endpoint directions. -/// -/// !Directions -/// - USBEndpointDescriptor_OUT -/// - USBEndpointDescriptor_IN - -/// Endpoint receives data from the host. -#define USBEndpointDescriptor_OUT 0 -/// Endpoint sends data to the host. -#define USBEndpointDescriptor_IN 1 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Endpoint types" -/// -/// This page lists definitions of USB endpoint types. -/// -/// !Types -/// - USBEndpointDescriptor_CONTROL -/// - USBEndpointDescriptor_ISOCHRONOUS -/// - USBEndpointDescriptor_BULK -/// - USBEndpointDescriptor_INTERRUPT - -/// Control endpoint type. -#define USBEndpointDescriptor_CONTROL 0 -/// Isochronous endpoint type. -#define USBEndpointDescriptor_ISOCHRONOUS 1 -/// Bulk endpoint type. -#define USBEndpointDescriptor_BULK 2 -/// Interrupt endpoint type. -#define USBEndpointDescriptor_INTERRUPT 3 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Endpoint maximun sizes" -/// -/// This page lists definitions of USB endpoint maximun sizes. -/// -/// !Sizes -/// - USBEndpointDescriptor_MAXCTRLSIZE_FS -/// - USBEndpointDescriptor_MAXCTRLSIZE_HS -/// - USBEndpointDescriptor_MAXBULKSIZE_FS -/// - USBEndpointDescriptor_MAXBULKSIZE_HS -/// - USBEndpointDescriptor_MAXINTERRUPTSIZE_FS -/// - USBEndpointDescriptor_MAXINTERRUPTSIZE_HS -/// - USBEndpointDescriptor_MAXISOCHRONOUSSIZE_FS -/// - USBEndpointDescriptor_MAXISOCHRONOUSSIZE_HS - -/// Maximum size for a full-speed control endpoint. -#define USBEndpointDescriptor_MAXCTRLSIZE_FS 64 -/// Maximum size for a high-speed control endpoint. -#define USBEndpointDescriptor_MAXCTRLSIZE_HS 64 -/// Maximum size for a full-speed bulk endpoint. -#define USBEndpointDescriptor_MAXBULKSIZE_FS 64 -/// Maximum size for a high-speed bulk endpoint. -#define USBEndpointDescriptor_MAXBULKSIZE_HS 512 -/// Maximum size for a full-speed interrupt endpoint. -#define USBEndpointDescriptor_MAXINTERRUPTSIZE_FS 64 -/// Maximum size for a high-speed interrupt endpoint. -#define USBEndpointDescriptor_MAXINTERRUPTSIZE_HS 1024 -/// Maximum size for a full-speed isochronous endpoint. -#define USBEndpointDescriptor_MAXISOCHRONOUSSIZE_FS 1023 -/// Maximum size for a high-speed isochronous endpoint. -#define USBEndpointDescriptor_MAXISOCHRONOUSSIZE_HS 1024 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Endpoint address define" -/// -/// This page lists macro for USB endpoint address definition. -/// -/// !Macro -/// - USBEndpointDescriptor_ADDRESS - -/// Calculates the address of an endpoint given its number and direction -/// \param direction USB endpoint direction definition -/// \param number USB endpoint number -/// \return The value used to set the endpoint descriptor based on input number -/// and direction -#define USBEndpointDescriptor_ADDRESS(direction, number) \ - (((direction & 0x01) << 7) | (number & 0xF)) -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -/// USB standard endpoint descriptor structure. -//------------------------------------------------------------------------------ -typedef struct { - - /// Size of the descriptor in bytes. - unsigned char bLength; - /// Descriptor type (). - unsigned char bDescriptorType; - /// Address and direction of the endpoint. - unsigned char bEndpointAddress; - /// Endpoint type and additional characteristics (for isochronous endpoints). - unsigned char bmAttributes; - /// Maximum packet size (in bytes) of the endpoint. - unsigned short wMaxPacketSize; - /// Polling rate of the endpoint. - unsigned char bInterval; - -} __attribute__ ((packed)) USBEndpointDescriptor; // GCC - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char USBEndpointDescriptor_GetNumber( - const USBEndpointDescriptor *endpoint); - -extern unsigned char USBEndpointDescriptor_GetDirection( - const USBEndpointDescriptor *endpoint); - -extern unsigned char USBEndpointDescriptor_GetType( - const USBEndpointDescriptor *endpoint); - -extern unsigned short USBEndpointDescriptor_GetMaxPacketSize( - const USBEndpointDescriptor *endpoint); - -extern unsigned char USBEndpointDescriptor_GetInterval( - const USBEndpointDescriptor *endpoint); - -#endif //#ifndef USBENDPOINTDESCRIPTOR_H - diff --git a/radio/bootloader/usb/common/core/USBFeatureRequest.c b/radio/bootloader/usb/common/core/USBFeatureRequest.c deleted file mode 100644 index 6276f6d5a..000000000 --- a/radio/bootloader/usb/common/core/USBFeatureRequest.c +++ /dev/null @@ -1,70 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBFeatureRequest implementation - - About: Purpose - Implementation of the USBFeatureRequest class. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBFeatureRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Returns the feature selector of a given CLEAR_FEATURE or SET_FEATURE -/// request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Feature selector. -//------------------------------------------------------------------------------ -unsigned char USBFeatureRequest_GetFeatureSelector( - const USBGenericRequest *request) -{ - return USBGenericRequest_GetValue(request); -} - -//------------------------------------------------------------------------------ -/// Indicates the test that the device must undertake following a -/// SET_FEATURE request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Test selector. -//------------------------------------------------------------------------------ -unsigned char USBFeatureRequest_GetTestSelector( - const USBGenericRequest *request) -{ - return (USBGenericRequest_GetIndex(request) >> 8) & 0xFF; -} - diff --git a/radio/bootloader/usb/common/core/USBFeatureRequest.h b/radio/bootloader/usb/common/core/USBFeatureRequest.h deleted file mode 100644 index 49493c732..000000000 --- a/radio/bootloader/usb/common/core/USBFeatureRequest.h +++ /dev/null @@ -1,146 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of a class for manipulating CLEAR_FEATURE and SET_FEATURE - requests. - - !!!Usage - - - To get USB feature request information (field values) from the - USBGenericRequest instance, use - - USBFeatureRequest_GetFeatureSelector - - USBFeatureRequest_GetTestSelector -*/ - -#ifndef USBFEATUREREQUEST_H -#define USBFEATUREREQUEST_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBGenericRequest.h" - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Feature Request definitions" -/// -/// This page lists codes of USB Feature Request -/// -/// - USB Feature selectors -/// - USBFeatureRequest_ENDPOINTHALT -/// - USBFeatureRequest_DEVICEREMOTEWAKEUP -/// - USBFeatureRequest_TESTMODE -/// -/// - USB Test mode selectors -/// - USBFeatureRequest_TESTJ -/// - USBFeatureRequest_TESTK -/// - USBFeatureRequest_TESTSE0NAK -/// - USBFeatureRequest_TESTPACKET -/// - USBFeatureRequest_TESTFORCEENABLE -/// - USBFeatureRequest_TESTSENDZLP -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Feature selectors" -/// -/// This page lists codes of USB feature selectors. -/// -/// !Selectors -/// - USBFeatureRequest_ENDPOINTHALT -/// - USBFeatureRequest_DEVICEREMOTEWAKEUP -/// - USBFeatureRequest_TESTMODE - -/// Halt feature of an endpoint. -#define USBFeatureRequest_ENDPOINTHALT 0 -/// Remote wake-up feature of the device. -#define USBFeatureRequest_DEVICEREMOTEWAKEUP 1 -/// Test mode of the device. -#define USBFeatureRequest_TESTMODE 2 -/// OTG set feature -#define USBFeatureRequest_OTG 0x0B -//------------------------------------------------------------------------------ - -/// On The Go Feature Selectors -/// b_hnp_enable 3 -/// a_hnp_support 4 -/// a_alt_hnp_support 5 -#define USBFeatureRequest_OTG_B_HNP_ENABLE 3 -#define USBFeatureRequest_OTG_A_HNP_SUPPORT 4 -#define USBFeatureRequest_OTG_A_ALT_HNP_SUPPORT 5 - -//------------------------------------------------------------------------------ -/// \page "USB Test mode selectors" -/// -/// This page lists codes of USB high speed test mode selectors. -/// -/// !Selectors -/// - USBFeatureRequest_TESTJ -/// - USBFeatureRequest_TESTK -/// - USBFeatureRequest_TESTSE0NAK -/// - USBFeatureRequest_TESTPACKET -/// - USBFeatureRequest_TESTFORCEENABLE -/// - USBFeatureRequest_TESTSENDZLP - -/// Tests the high-output drive level on the D+ line. -#define USBFeatureRequest_TESTJ 1 -/// Tests the high-output drive level on the D- line. -#define USBFeatureRequest_TESTK 2 -/// Tests the output impedance, low-level output voltage and loading -/// characteristics. -#define USBFeatureRequest_TESTSE0NAK 3 -/// Tests rise and fall times, eye patterns and jitter. -#define USBFeatureRequest_TESTPACKET 4 -/// Tests the hub disconnect detection. -#define USBFeatureRequest_TESTFORCEENABLE 5 -/// Send a ZLP in Test Mode. -#define USBFeatureRequest_TESTSENDZLP 6 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char USBFeatureRequest_GetFeatureSelector( - const USBGenericRequest *request); - - -extern unsigned char USBFeatureRequest_GetTestSelector( - const USBGenericRequest *request); - -#endif //#ifndef USBFEATUREREQUEST_H - diff --git a/radio/bootloader/usb/common/core/USBGenericDescriptor.c b/radio/bootloader/usb/common/core/USBGenericDescriptor.c deleted file mode 100644 index 298bad6c5..000000000 --- a/radio/bootloader/usb/common/core/USBGenericDescriptor.c +++ /dev/null @@ -1,80 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBGenericDescriptor implementation - - About: Purpose - Implementation of the USBGenericDescriptor class. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBGenericDescriptor.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Returns the length of a descriptor. -/// \param descriptor Pointer to a USBGenericDescriptor instance. -/// \return Length of descriptor in bytes. -//------------------------------------------------------------------------------ -unsigned int USBGenericDescriptor_GetLength( - const USBGenericDescriptor *descriptor) -{ - return descriptor->bLength; -} - -//------------------------------------------------------------------------------ -/// Returns the type of a descriptor. -/// \param descriptor Pointer to a USBGenericDescriptor instance. -/// \return Type of descriptor. -//------------------------------------------------------------------------------ -unsigned char USBGenericDescriptor_GetType( - const USBGenericDescriptor *descriptor) -{ - return descriptor->bDescriptorType; -} - -//------------------------------------------------------------------------------ -/// Returns a pointer to the descriptor right after the given one, when -/// parsing a Configuration descriptor. -/// \param descriptor - Pointer to a USBGenericDescriptor instance. -/// \return Pointer to the next descriptor. -//------------------------------------------------------------------------------ -USBGenericDescriptor *USBGenericDescriptor_GetNextDescriptor( - const USBGenericDescriptor *descriptor) -{ - return (USBGenericDescriptor *) - (((char *) descriptor) + USBGenericDescriptor_GetLength(descriptor)); -} diff --git a/radio/bootloader/usb/common/core/USBGenericDescriptor.h b/radio/bootloader/usb/common/core/USBGenericDescriptor.h deleted file mode 100644 index 01318f431..000000000 --- a/radio/bootloader/usb/common/core/USBGenericDescriptor.h +++ /dev/null @@ -1,133 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !!!Purpose -/// -/// Definition of a generic USB descriptor class. -/// -/// !!!Usage -/// -/// -# Declare or access USB descriptors by USBGenericDescriptor instance. -/// -# To get usful information (field values) from the USB descriptors, use -/// - USBGenericDescriptor_GetLength -/// - USBGenericDescriptor_GetType -/// -# To scan the descriptors, use -/// - USBGenericDescriptor_GetNextDescriptor -//------------------------------------------------------------------------------ - -#ifndef USBGENERICDESCRIPTOR_H -#define USBGENERICDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Descriptor types" -/// -/// This page lists the codes of the usb descriptor types -/// -/// !Types -/// - USBGenericDescriptor_DEVICE -/// - USBGenericDescriptor_CONFIGURATION -/// - USBGenericDescriptor_STRING -/// - USBGenericDescriptor_INTERFACE -/// - USBGenericDescriptor_ENDPOINT -/// - USBGenericDescriptor_DEVICEQUALIFIER -/// - USBGenericDescriptor_OTHERSPEEDCONFIGURATION -/// - USBGenericDescriptor_INTERFACEPOWER -/// - USBGenericDescriptor_OTG -/// - USBGenericDescriptor_DEBUG -/// - USBGenericDescriptor_INTERFACEASSOCIATION - -/// Device descriptor type. -#define USBGenericDescriptor_DEVICE 1 -/// Configuration descriptor type. -#define USBGenericDescriptor_CONFIGURATION 2 -/// String descriptor type. -#define USBGenericDescriptor_STRING 3 -/// Interface descriptor type. -#define USBGenericDescriptor_INTERFACE 4 -/// Endpoint descriptor type. -#define USBGenericDescriptor_ENDPOINT 5 -/// Device qualifier descriptor type. -#define USBGenericDescriptor_DEVICEQUALIFIER 6 -/// Other speed configuration descriptor type. -#define USBGenericDescriptor_OTHERSPEEDCONFIGURATION 7 -/// Interface power descriptor type. -#define USBGenericDescriptor_INTERFACEPOWER 8 -/// On-The-Go descriptor type. -#define USBGenericDescriptor_OTG 9 -/// Debug descriptor type. -#define USBGenericDescriptor_DEBUG 10 -/// Interface association descriptor type. -#define USBGenericDescriptor_INTERFACEASSOCIATION 11 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -/// Holds the few fields shared by all USB descriptors. -typedef struct { - - /// Length of the descriptor in bytes. - unsigned char bLength; - /// Descriptor type. - unsigned char bDescriptorType; - -} __attribute__ ((packed)) USBGenericDescriptor; // GCC - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned int USBGenericDescriptor_GetLength( - const USBGenericDescriptor *descriptor); - -extern unsigned char USBGenericDescriptor_GetType( - const USBGenericDescriptor *descriptor); - -extern USBGenericDescriptor *USBGenericDescriptor_GetNextDescriptor( - const USBGenericDescriptor *descriptor); - -#endif //#ifndef USBGENERICDESCRIPTOR_H - diff --git a/radio/bootloader/usb/common/core/USBGenericRequest.c b/radio/bootloader/usb/common/core/USBGenericRequest.c deleted file mode 100644 index 9e902422a..000000000 --- a/radio/bootloader/usb/common/core/USBGenericRequest.c +++ /dev/null @@ -1,138 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBGenericRequest implementation - - About: Purpose - Implementation of the USBGenericRequest class. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBGenericRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -//------------------------------------------------------------------------------ -/// Returns the type of the given request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return "USB Request Types" -//------------------------------------------------------------------------------ -extern unsigned char USBGenericRequest_GetType(const USBGenericRequest *request) -{ - return ((request->bmRequestType >> 5) & 0x3); -} - -//------------------------------------------------------------------------------ -/// Returns the request code of the given request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Request code. -/// \sa "USB Request Codes" -//------------------------------------------------------------------------------ -unsigned char USBGenericRequest_GetRequest(const USBGenericRequest *request) -{ - return request->bRequest; -} - -//------------------------------------------------------------------------------ -/// Returns the wValue field of the given request. -/// \param request - Pointer to a USBGenericRequest instance. -/// \return Request value. -//------------------------------------------------------------------------------ -unsigned short USBGenericRequest_GetValue(const USBGenericRequest *request) -{ - return request->wValue; -} - -//------------------------------------------------------------------------------ -/// Returns the wIndex field of the given request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Request index; -//------------------------------------------------------------------------------ -unsigned short USBGenericRequest_GetIndex(const USBGenericRequest *request) -{ - return request->wIndex; -} - -//------------------------------------------------------------------------------ -/// Returns the expected length of the data phase following a request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Length of data phase. -//------------------------------------------------------------------------------ -unsigned short USBGenericRequest_GetLength(const USBGenericRequest *request) -{ - return request->wLength; -} - -//------------------------------------------------------------------------------ -/// Returns the endpoint number targetted by a given request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Endpoint number. -//------------------------------------------------------------------------------ -unsigned char USBGenericRequest_GetEndpointNumber( - const USBGenericRequest *request) -{ - return USBGenericRequest_GetIndex(request) & 0xF; -} - -//------------------------------------------------------------------------------ -/// Returns the intended recipient of a given request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Request recipient. -/// \sa "USB Request Recipients" -//------------------------------------------------------------------------------ -unsigned char USBGenericRequest_GetRecipient(const USBGenericRequest *request) -{ - // Recipient is in bits [0..4] of the bmRequestType field - return request->bmRequestType & 0xF; -} - -//------------------------------------------------------------------------------ -/// Returns the direction of the data transfer following the given request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Transfer direction. -/// \sa "USB Request Directions" -//------------------------------------------------------------------------------ -unsigned char USBGenericRequest_GetDirection(const USBGenericRequest *request) -{ - // Transfer direction is located in bit D7 of the bmRequestType field - if ((request->bmRequestType & 0x80) != 0) { - - return USBGenericRequest_IN; - } - else { - - return USBGenericRequest_OUT; - } -} - diff --git a/radio/bootloader/usb/common/core/USBGenericRequest.h b/radio/bootloader/usb/common/core/USBGenericRequest.h deleted file mode 100644 index 0e7895436..000000000 --- a/radio/bootloader/usb/common/core/USBGenericRequest.h +++ /dev/null @@ -1,244 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of the USBGenericRequest class and its methods. - - !!!Usage - - -# Declare or access USB requests by USBGenericRequest instance. - -# To get usful information (field values) from the USB requests, use - - USBGenericRequest_GetType - - USBGenericRequest_GetRequest - - USBGenericRequest_GetValue - - USBGenericRequest_GetIndex - - USBGenericRequest_GetLength - - USBGenericRequest_GetEndpointNumber - - USBGenericRequest_GetRecipient - - USBGenericRequest_GetDirection -*/ - -#ifndef USBGENERICREQUEST_H -#define USBGENERICREQUEST_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Generic Request definitions" -/// -/// This page lists the codes of USB generic request. -/// -/// - USB Request codes -/// - USBGenericRequest_GETSTATUS -/// - USBGenericRequest_CLEARFEATURE -/// - USBGenericRequest_SETFEATURE -/// - USBGenericRequest_SETADDRESS -/// - USBGenericRequest_GETDESCRIPTOR -/// - USBGenericRequest_SETDESCRIPTOR -/// - USBGenericRequest_GETCONFIGURATION -/// - USBGenericRequest_SETCONFIGURATION -/// - USBGenericRequest_GETINTERFACE -/// - USBGenericRequest_SETINTERFACE -/// - USBGenericRequest_SYNCHFRAME -/// -/// - USB Request Recipients -/// - USBGenericRequest_DEVICE -/// - USBGenericRequest_INTERFACE -/// - USBGenericRequest_ENDPOINT -/// - USBGenericRequest_OTHER -/// -/// - USB Request Types -/// - USBGenericRequest_STANDARD -/// - USBGenericRequest_CLASS -/// - USBGenericRequest_VENDOR -/// -/// - USB Request Directions -/// - USBGenericRequest_IN -/// - USBGenericRequest_OUT -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Request codes" -/// -/// This page lists the USB generic request codes. -/// -/// !Codes -/// - USBGenericRequest_GETSTATUS -/// - USBGenericRequest_CLEARFEATURE -/// - USBGenericRequest_SETFEATURE -/// - USBGenericRequest_SETADDRESS -/// - USBGenericRequest_GETDESCRIPTOR -/// - USBGenericRequest_SETDESCRIPTOR -/// - USBGenericRequest_GETCONFIGURATION -/// - USBGenericRequest_SETCONFIGURATION -/// - USBGenericRequest_GETINTERFACE -/// - USBGenericRequest_SETINTERFACE -/// - USBGenericRequest_SYNCHFRAME - -/// GET_STATUS request code. -#define USBGenericRequest_GETSTATUS 0 -/// CLEAR_FEATURE request code. -#define USBGenericRequest_CLEARFEATURE 1 -/// SET_FEATURE request code. -#define USBGenericRequest_SETFEATURE 3 -/// SET_ADDRESS request code. -#define USBGenericRequest_SETADDRESS 5 -/// GET_DESCRIPTOR request code. -#define USBGenericRequest_GETDESCRIPTOR 6 -/// SET_DESCRIPTOR request code. -#define USBGenericRequest_SETDESCRIPTOR 7 -/// GET_CONFIGURATION request code. -#define USBGenericRequest_GETCONFIGURATION 8 -/// SET_CONFIGURATION request code. -#define USBGenericRequest_SETCONFIGURATION 9 -/// GET_INTERFACE request code. -#define USBGenericRequest_GETINTERFACE 10 -/// SET_INTERFACE request code. -#define USBGenericRequest_SETINTERFACE 11 -/// SYNCH_FRAME request code. -#define USBGenericRequest_SYNCHFRAME 12 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Request Recipients" -/// -/// This page lists codes of USB request recipients. -/// -/// !Recipients -/// - USBGenericRequest_DEVICE -/// - USBGenericRequest_INTERFACE -/// - USBGenericRequest_ENDPOINT -/// - USBGenericRequest_OTHER - -/// Recipient is the whole device. -#define USBGenericRequest_DEVICE 0 -/// Recipient is an interface. -#define USBGenericRequest_INTERFACE 1 -/// Recipient is an endpoint. -#define USBGenericRequest_ENDPOINT 2 -/// Recipient is another entity. -#define USBGenericRequest_OTHER 3 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Request Types" -/// -/// This page lists codes of USB request types. -/// -/// !Types -/// - USBGenericRequest_STANDARD -/// - USBGenericRequest_CLASS -/// - USBGenericRequest_VENDOR - -/// Request is standard. -#define USBGenericRequest_STANDARD 0 -/// Request is class-specific. -#define USBGenericRequest_CLASS 1 -/// Request is vendor-specific. -#define USBGenericRequest_VENDOR 2 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Request Directions" -/// -/// This page lists codes of USB request directions. -/// -/// !Directions -/// - USBGenericRequest_IN -/// - USBGenericRequest_OUT - -/// Transfer occurs from device to the host. -#define USBGenericRequest_OUT 0 -/// Transfer occurs from the host to the device. -#define USBGenericRequest_IN 1 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Generic USB SETUP request sent over Control endpoints. -//------------------------------------------------------------------------------ -typedef struct { - - /// Type of request - /// \sa "USB Request Recipients" - /// \sa "USB Request Types" - /// \sa "USB Request Directions" - unsigned char bmRequestType:8; - /// Request code - /// \sa "USB Request Codes" - unsigned char bRequest:8; - /// Request-specific value parameter. - unsigned short wValue:16; - /// Request-specific index parameter. - unsigned short wIndex:16; - /// Expected length (in bytes) of the data phase. - unsigned short wLength:16; - -} USBGenericRequest; - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char USBGenericRequest_GetType( - const USBGenericRequest *request); - - -extern unsigned char USBGenericRequest_GetRequest( - const USBGenericRequest *request); - -extern unsigned short USBGenericRequest_GetValue( - const USBGenericRequest *request); - -extern unsigned short USBGenericRequest_GetIndex( - const USBGenericRequest *request); - -extern unsigned short USBGenericRequest_GetLength( - const USBGenericRequest *request); - -extern unsigned char USBGenericRequest_GetEndpointNumber( - const USBGenericRequest *request); - -extern unsigned char USBGenericRequest_GetRecipient( - const USBGenericRequest *request); - -extern unsigned char USBGenericRequest_GetDirection( - const USBGenericRequest *request); - -#endif //#ifndef USBGENERICREQUEST_H - diff --git a/radio/bootloader/usb/common/core/USBGetDescriptorRequest.c b/radio/bootloader/usb/common/core/USBGetDescriptorRequest.c deleted file mode 100644 index 39c4127c7..000000000 --- a/radio/bootloader/usb/common/core/USBGetDescriptorRequest.c +++ /dev/null @@ -1,72 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBGetDescriptorRequest implementation - - About: Purpose - Implementation of the USBGetDescriptorRequest class. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBGetDescriptorRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Returns the type of the descriptor requested by the host given the -/// corresponding GET_DESCRIPTOR request. -/// \param request Pointer to a USBGenericDescriptor instance. -/// \return Type of the requested descriptor. -//------------------------------------------------------------------------------ -unsigned char USBGetDescriptorRequest_GetDescriptorType( - const USBGenericRequest *request) -{ - // Requested descriptor type is in the high-byte of the wValue field - return (USBGenericRequest_GetValue(request) >> 8) & 0xFF; -} - -//------------------------------------------------------------------------------ -/// Returns the index of the requested descriptor, given the corresponding -/// GET_DESCRIPTOR request. -/// \param request Pointer to a USBGenericDescriptor instance. -/// \return Index of the requested descriptor. -//------------------------------------------------------------------------------ -unsigned char USBGetDescriptorRequest_GetDescriptorIndex( - const USBGenericRequest *request) -{ - // Requested descriptor index if in the low byte of the wValue field - return USBGenericRequest_GetValue(request) & 0xFF; -} - diff --git a/radio/bootloader/usb/common/core/USBGetDescriptorRequest.h b/radio/bootloader/usb/common/core/USBGetDescriptorRequest.h deleted file mode 100644 index 5aef6320a..000000000 --- a/radio/bootloader/usb/common/core/USBGetDescriptorRequest.h +++ /dev/null @@ -1,67 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of the USBGetDescriptorRequest class. - - !!!Usage - - - After a GET_DESCRIPTOR request has been received, retrive the useful - values with following functions: - - USBGetDescriptorRequest_GetDescriptorType: the descriptor type - - USBGetDescriptorRequest_GetDescriptorIndex: the index of the requested - descriptor - -*/ - -#ifndef USBGETDESCRIPTORREQUEST_H -#define USBGETDESCRIPTORREQUEST_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBGenericRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char USBGetDescriptorRequest_GetDescriptorType( - const USBGenericRequest *request); - -extern unsigned char USBGetDescriptorRequest_GetDescriptorIndex( - const USBGenericRequest *request); - -#endif //#ifndef USBGETDESCRIPTORREQUEST_H - diff --git a/radio/bootloader/usb/common/core/USBInterfaceAssociationDescriptor.h b/radio/bootloader/usb/common/core/USBInterfaceAssociationDescriptor.h deleted file mode 100644 index 7f3376d01..000000000 --- a/radio/bootloader/usb/common/core/USBInterfaceAssociationDescriptor.h +++ /dev/null @@ -1,86 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \page USBInterfaceAssociateDescriptor - * !!!Purpose - * - * Class for manipulating USB IAD descriptors. - * - * !!!Usage - * - * -# Test - */ - -#ifndef USBDIADDESCRIPTOR_H -#define USBDIADDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -/* - Type: USBDeviceDescriptor - USB standard device descriptor structure. - - Variables: - bLength - Size of this descriptor in bytes. - bDescriptorType - Descriptor type (). - bFirstInterface - Interface number of the first interface that is - associated with this function. - bInterfaceCount - Number of contiguous interfaces that are - associated with this function. - bFunctionClass - Class code (assigned by USB-IF). - bFunctionSubClass - Subclass code (assigned by USB-IF). - bFunctionProtocol - Protocol code (assigned by USB-IF) - iFunction - Index of string descriptor describing this function. -*/ -typedef struct { - - unsigned char bLength; - unsigned char bDescriptorType; - unsigned char bFirstInterface; - unsigned char bInterfaceCount; - unsigned char bFunctionClass; - unsigned char bFunctionSubClass; - unsigned char bFunctionProtocol; - unsigned char iFunction; -} __attribute__ ((packed)) USBInterfaceAssociationDescriptor; // GCC - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -#endif //#ifndef USBDIADDESCRIPTOR_H - diff --git a/radio/bootloader/usb/common/core/USBInterfaceDescriptor.h b/radio/bootloader/usb/common/core/USBInterfaceDescriptor.h deleted file mode 100644 index 0d897a865..000000000 --- a/radio/bootloader/usb/common/core/USBInterfaceDescriptor.h +++ /dev/null @@ -1,87 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of a class for manipulating USB interface descriptors. - - !!!Usage - - - Declare USBInterfaceDescriptor instance as a part of the configuration - descriptors of a USB device. - -*/ - -#ifndef USBINTERFACEDESCRIPTOR_H -#define USBINTERFACEDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -/// USB standard interface descriptor structure. -//------------------------------------------------------------------------------ -typedef struct { - - /// Size of the descriptor in bytes. - unsigned char bLength; - /// Descriptor type (USBGenericDescriptor_INTERFACE). - unsigned char bDescriptorType; - /// Number of the interface in its configuration. - unsigned char bInterfaceNumber; - /// Value to select this alternate interface setting. - unsigned char bAlternateSetting; - /// Number of endpoints used by the inteface (excluding endpoint 0). - unsigned char bNumEndpoints; - /// Interface class code. - unsigned char bInterfaceClass; - /// Interface subclass code. - unsigned char bInterfaceSubClass; - /// Interface protocol code. - unsigned char bInterfaceProtocol; - /// Index of the interface string descriptor. - unsigned char iInterface; - -} __attribute__ ((packed)) USBInterfaceDescriptor; // GCC - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -#endif //#ifndef USBINTERFACEDESCRIPTOR_H - diff --git a/radio/bootloader/usb/common/core/USBInterfaceRequest.c b/radio/bootloader/usb/common/core/USBInterfaceRequest.c deleted file mode 100644 index 837e5f6d9..000000000 --- a/radio/bootloader/usb/common/core/USBInterfaceRequest.c +++ /dev/null @@ -1,69 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBInterfaceRequest - - About: Purpose - Implementation of USBInterfaceRequest class methods. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBInterfaceRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Indicates which interface is targetted by a GET_INTERFACE or -/// SET_INTERFACE request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Interface number. -//------------------------------------------------------------------------------ -unsigned char USBInterfaceRequest_GetInterface(const USBGenericRequest *request) -{ - return (USBGenericRequest_GetIndex(request) & 0xFF); -} - -//------------------------------------------------------------------------------ -/// Indicates the new alternate setting that the interface targetted by a -/// SET_INTERFACE request should use. -/// \param request Pointer to a USBGenericRequest instance. -/// \return New active setting for the interface. -//------------------------------------------------------------------------------ -unsigned char USBInterfaceRequest_GetAlternateSetting( - const USBGenericRequest *request) -{ - return (USBGenericRequest_GetValue(request) & 0xFF); -} - diff --git a/radio/bootloader/usb/common/core/USBInterfaceRequest.h b/radio/bootloader/usb/common/core/USBInterfaceRequest.h deleted file mode 100644 index dff2bdf8f..000000000 --- a/radio/bootloader/usb/common/core/USBInterfaceRequest.h +++ /dev/null @@ -1,68 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definitions for manipulating SET_INTERFACE and GET_INTERFACE request. - - !!!Usage - - -# After a SET_INTERFACE request has been received, retrieve the - target interface using USBInterfaceRequest_GetInterface and its - new alternate setting with USBInterfaceRequest_GetAlternateSetting. - -# After a GET_INTERFACE request has been received, retrieve the target - interface using USBInterfaceRequest_GetInterface. - -*/ - -#ifndef USBINTERFACEREQUEST_H -#define USBINTERFACEREQUEST_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBGenericRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char USBInterfaceRequest_GetInterface( - const USBGenericRequest *request); - - -extern unsigned char USBInterfaceRequest_GetAlternateSetting( - const USBGenericRequest *request); - -#endif //#ifndef USBINTERFACEREQUEST_H - diff --git a/radio/bootloader/usb/common/core/USBIrqHandler.c b/radio/bootloader/usb/common/core/USBIrqHandler.c deleted file mode 100644 index b5f54f2ad..000000000 --- a/radio/bootloader/usb/common/core/USBIrqHandler.c +++ /dev/null @@ -1,62 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBIrqHandler implementation - - About: Purpose - Implementation of the USB Interrupt Handler. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ -#include -#include - -#include - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -//------------------------------------------------------------------------------ -/// Call Arbitrer, device and host interrupt handler. -/// The IRQ functions are defined with weak and can be surcharged if needed. -//------------------------------------------------------------------------------ -void USB_IrqHandler( void ) -{ - // Most arbitrer interrupt - usb_general_interrupt(); - // Device interrupt - USBD_IrqHandler(); - // Host interrupt - usb_pipe_interrupt(); -} - - diff --git a/radio/bootloader/usb/common/core/USBIrqHandler.h b/radio/bootloader/usb/common/core/USBIrqHandler.h deleted file mode 100644 index 3e6771ddc..000000000 --- a/radio/bootloader/usb/common/core/USBIrqHandler.h +++ /dev/null @@ -1,52 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Implementation of the USB Interrupt Handler. - - !!!Usage - - -# The IRQ functions are defined with weak and can be surcharged if needed. - -*/ - -#ifndef USBIRQHANDLER_H -#define USBIRQHANDLER_H - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -extern void USB_IrqHandler( void ); - -#endif //#ifndef USBIRQHANDLER_H - diff --git a/radio/bootloader/usb/common/core/USBSetAddressRequest.c b/radio/bootloader/usb/common/core/USBSetAddressRequest.c deleted file mode 100644 index d955d7a87..000000000 --- a/radio/bootloader/usb/common/core/USBSetAddressRequest.c +++ /dev/null @@ -1,56 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBSetAddressRequest implementation - - About: Purpose - Implementation of the USBSetAddressRequest class. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBSetAddressRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -//------------------------------------------------------------------------------ -/// Returns the address that the device must take in response to a -/// SET_ADDRESS request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return New device address. -//------------------------------------------------------------------------------ -unsigned char USBSetAddressRequest_GetAddress(const USBGenericRequest *request) -{ - return USBGenericRequest_GetValue(request) & 0x7F; -} - diff --git a/radio/bootloader/usb/common/core/USBSetAddressRequest.h b/radio/bootloader/usb/common/core/USBSetAddressRequest.h deleted file mode 100644 index 2a73d7939..000000000 --- a/radio/bootloader/usb/common/core/USBSetAddressRequest.h +++ /dev/null @@ -1,60 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of a class for manipulating SET_ADDRESS USB requests. - - !!!Usage - - - After a SET_ADDRESS request has been received, retrive the new address - value with USBSetAddressRequest_GetAddress. -*/ - -#ifndef USBSETADDRESSREQUEST_H -#define USBSETADDRESSREQUEST_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBGenericRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char USBSetAddressRequest_GetAddress( - const USBGenericRequest *request); - -#endif //#ifndef USBSETADDRESSREQUEST_H - diff --git a/radio/bootloader/usb/common/core/USBSetConfigurationRequest.c b/radio/bootloader/usb/common/core/USBSetConfigurationRequest.c deleted file mode 100644 index 4910739bb..000000000 --- a/radio/bootloader/usb/common/core/USBSetConfigurationRequest.c +++ /dev/null @@ -1,58 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBSetConfigurationRequest implementation - - About: Purpose - Implementation of the USBSetConfigurationRequest class. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBSetConfigurationRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Returns the number of the configuration that should be set in response -/// to the given SET_CONFIGURATION request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Number of the requested configuration. -//------------------------------------------------------------------------------ -unsigned char USBSetConfigurationRequest_GetConfiguration( - const USBGenericRequest *request) -{ - return USBGenericRequest_GetValue(request); -} - diff --git a/radio/bootloader/usb/common/core/USBSetConfigurationRequest.h b/radio/bootloader/usb/common/core/USBSetConfigurationRequest.h deleted file mode 100644 index f70ad8aef..000000000 --- a/radio/bootloader/usb/common/core/USBSetConfigurationRequest.h +++ /dev/null @@ -1,61 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of a class for the Set Configuration request. - - !!!Usage - - - After a SET_CONFIGURATION request has been received, retrive the new - configuration value with USBSetConfigurationRequest_GetConfiguration. - -*/ - -#ifndef USBSETCONFIGURATIONREQUEST_H -#define USBSETCONFIGURATIONREQUEST_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBGenericRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char USBSetConfigurationRequest_GetConfiguration( - const USBGenericRequest *request); - -#endif //#ifndef USBSETCONFIGURATIONREQUEST_H - diff --git a/radio/bootloader/usb/common/core/USBStringDescriptor.h b/radio/bootloader/usb/common/core/USBStringDescriptor.h deleted file mode 100644 index e3da4b405..000000000 --- a/radio/bootloader/usb/common/core/USBStringDescriptor.h +++ /dev/null @@ -1,74 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !!!Purpose -/// -/// Definition of a class for manipulating String descriptors. -//------------------------------------------------------------------------------ - -#ifndef USBSTRINGDESCRIPTOR_H -#define USBSTRINGDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB String Descriptor definitions" -/// -/// This page lists the codes and macros for USB string descriptor definition. -/// -/// !Language IDs -/// - USBStringDescriptor_ENGLISH_US -/// -/// !String Descriptor Length -/// - USBStringDescriptor_LENGTH -/// -/// !ASCII to UNICODE convertion -/// - USBStringDescriptor_UNICODE - -/// Language ID for US english. -#define USBStringDescriptor_ENGLISH_US 0x09, 0x04 - -/// Calculates the length of a string descriptor given the number of ascii -/// characters/language IDs in it. -/// \param length The ascii format string length. -/// \return The actual data length in bytes. -#define USBStringDescriptor_LENGTH(length) ((length) * 2 + 2) -/// Converts an ascii character to its unicode representation. -/// \param ascii The ASCII character to convert -/// \return A 2-byte-array for the UNICODE based on given ASCII -#define USBStringDescriptor_UNICODE(ascii) (ascii), 0 -//------------------------------------------------------------------------------ - -#endif //#ifndef USBSTRINGDESCRIPTOR_H - diff --git a/radio/bootloader/usb/common/massstorage/MSDeviceDescriptor.h b/radio/bootloader/usb/common/massstorage/MSDeviceDescriptor.h deleted file mode 100644 index f85833ee0..000000000 --- a/radio/bootloader/usb/common/massstorage/MSDeviceDescriptor.h +++ /dev/null @@ -1,73 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Declaration of constants for using Device Descriptors with a Mass Storage -/// driver. -/// -/// !Usage -/// -/// - For a USB device: -/// -# When declaring a USBDeviceDescriptor instance, use the Mass Storage -/// codes defined in this file (see "MS device codes"). -//------------------------------------------------------------------------------ - -#ifndef MSDEVICEDESCRIPTOR_H -#define MSDEVICEDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MS device codes" -/// This page lists the class, subclass & protocol codes used by a device with -/// a Mass Storage driver. -/// -/// !Codes -/// -/// - MSDeviceDescriptor_CLASS -/// - MSDeviceDescriptor_SUBCLASS -/// - MSDeviceDescriptor_PROTOCOL - -/// Class code for a Mass Storage device. -#define MSDeviceDescriptor_CLASS 0 - -/// Subclass code for a Mass Storage device. -#define MSDeviceDescriptor_SUBCLASS 0 - -/// Protocol code for a Mass Storage device. -#define MSDeviceDescriptor_PROTOCOL 0 -//------------------------------------------------------------------------------ - -#endif //#ifndef MSDEVICEDESCRIPTOR_H - diff --git a/radio/bootloader/usb/common/massstorage/MSInterfaceDescriptor.h b/radio/bootloader/usb/common/massstorage/MSInterfaceDescriptor.h deleted file mode 100644 index b5033e24e..000000000 --- a/radio/bootloader/usb/common/massstorage/MSInterfaceDescriptor.h +++ /dev/null @@ -1,75 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Definition of several constants used when manipulating Mass Storage interface -/// descriptors. -/// -/// !Usage -/// -/// - For a USB device: -/// -# When declaring an interface descriptor for a Mass Storage device, use -/// the class, subclass and protocol codes defined here (see -/// "MS interface codes"). -//------------------------------------------------------------------------------ - -#ifndef MSINTERFACEDESCRIPTOR_H -#define MSINTERFACEDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MS interface codes" -/// This page lists the available class, subclass & protocol codes for a Mass -/// Storage interface. -/// -/// !Codes -/// -/// - MSInterfaceDescriptor_CLASS -/// - MSInterfaceDescriptor_SCSI -/// - MSInterfaceDescriptor_BULKONLY - -/// Class code for a Mass Storage interface. -#define MSInterfaceDescriptor_CLASS 0x08 - -/// Subclass code for a Mass Storage interface using the SCSI protocol. -#define MSInterfaceDescriptor_SCSI 0x06 - -/// Protocol code for a Mass Storage interface using Bulk-Only Transport. -#define MSInterfaceDescriptor_BULKONLY 0x50 -//------------------------------------------------------------------------------ - - -#endif //#ifndef MSINTERFACEDESCRIPTOR_H - diff --git a/radio/bootloader/usb/device/core/USBD.h b/radio/bootloader/usb/device/core/USBD.h deleted file mode 100644 index 27c26f229..000000000 --- a/radio/bootloader/usb/device/core/USBD.h +++ /dev/null @@ -1,275 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !!!Purpose -/// -/// Collection of methods for using the USB device controller on AT91 -/// microcontrollers. -/// -/// !!!Usage -/// -/// Please refer to the corresponding application note. -/// - "AT91 USB device framework" -/// - "USBD API" . "USBD API Methods" -//------------------------------------------------------------------------------ - -#ifndef USBD_H -#define USBD_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -// #include -#include -#include - -//------------------------------------------------------------------------------ -// Compile Options -//------------------------------------------------------------------------------ - -/// Compile option for HS or OTG, use DMA. Remove this define for not use DMA. -#if defined(CHIP_USB_OTGHS) || defined(CHIP_USB_UDPHS) -#define DMA -#endif - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB device API return values" -/// -/// This page lists the return values of the USB %device driver API -/// -/// !Return codes -/// - USBD_STATUS_SUCCESS -/// - USBD_STATUS_LOCKED -/// - USBD_STATUS_ABORTED -/// - USBD_STATUS_RESET - -/// Indicates the operation was successful. -#define USBD_STATUS_SUCCESS 0 -/// Endpoint/device is already busy. -#define USBD_STATUS_LOCKED 1 -/// Operation has been aborted. -#define USBD_STATUS_ABORTED 2 -/// Operation has been aborted because the device has been reset. -#define USBD_STATUS_RESET 3 -/// Part ot operation successfully done. -#define USBD_STATUS_PARTIAL_DONE 4 -/// Operation failed because parameter error -#define USBD_STATUS_INVALID_PARAMETER 5 -/// Operation failed because in unexpected state -#define USBD_STATUS_WRONG_STATE 6 -/// Operation failed because HW not supported -#define USBD_STATUS_HW_NOT_SUPPORTED 0xFE -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB device states" -/// -/// This page lists the %device states of the USB %device driver. -/// -/// !States -/// - USBD_STATE_SUSPENDED -/// - USBD_STATE_ATTACHED -/// - USBD_STATE_POWERED -/// - USBD_STATE_DEFAULT -/// - USBD_STATE_ADDRESS -/// - USBD_STATE_CONFIGURED - -/// The device is currently suspended. -#define USBD_STATE_SUSPENDED 0 -/// USB cable is plugged into the device. -#define USBD_STATE_ATTACHED 1 -/// Host is providing +5V through the USB cable. -#define USBD_STATE_POWERED 2 -/// Device has been reset. -#define USBD_STATE_DEFAULT 3 -/// The device has been given an address on the bus. -#define USBD_STATE_ADDRESS 4 -/// A valid configuration has been selected. -#define USBD_STATE_CONFIGURED 5 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB device LEDs" -/// -/// This page lists the LEDs used in the USB %device driver. -/// -/// !LEDs -/// - USBD_LEDPOWER -/// - USBD_LEDUSB -/// - USBD_LEDOTHER - -/// LED for indicating that the device is powered. -#define USBD_LEDPOWER 0 -/// LED for indicating USB activity. -#define USBD_LEDUSB 1 -/// LED for custom usage. -#define USBD_LEDOTHER 2 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Buffer struct used for multi-buffer-listed transfer. -/// The driver can process 255 bytes of buffers or buffer list window. -//------------------------------------------------------------------------------ -typedef struct _USBDTransferBuffer { - /// Pointer to frame buffer - unsigned char * pBuffer; - /// Size of the frame (up to 64K-1) - unsigned short size; - /// Bytes transferred - unsigned short transferred; - /// Bytes in FIFO - unsigned short buffered; - /// Bytes remaining - unsigned short remaining; -} USBDTransferBuffer; - -#ifdef __ICCARM__ // IAR -#define __attribute__(...) // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -/// Struct used for USBD DMA Link List Transfer Descriptor, must be 16-bytes -/// aligned. -/// (For USB, DMA transfer is linked to EPs and FIFO address is EP defined) -//------------------------------------------------------------------------------ -typedef struct _USBDDmaDescriptor { - /// Pointer to Next Descriptor - void* pNxtDesc; - /// Pointer to data buffer address - void* pDataAddr; - /// DMA Control setting register value - unsigned int ctrlSettings:8, /// Control settings - reserved:8, /// Not used - bufferLength:16; /// Length of buffer - /// Loaded to DMA register, OK to modify - unsigned int used; -} __attribute__((aligned(16))) USBDDmaDescriptor; - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -/// Callback used by transfer functions (USBD_Read & USBD_Write) to notify -/// that a transaction is complete. -//------------------------------------------------------------------------------ -typedef void (*TransferCallback)(void *pArg, - unsigned char status, - unsigned int transferred, - unsigned int remaining); - -//------------------------------------------------------------------------------ -/// Callback used by MBL transfer functions (USBD_Read & USBD_Write) to notify -/// that a transaction is complete. -/// \param pArg Pointer to callback arguments. -/// \param status USBD status. -/// \param nbFreed Number of buffers that is freed since last callback. -//------------------------------------------------------------------------------ -typedef void (*MblTransferCallback)(void *pArg, - unsigned char status, - unsigned int nbFreed); - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern void USBD_IrqHandler(void); - -extern void USBD_Init(void); - -extern void USBD_ConfigureSpeed(unsigned char forceFS); - -extern void USBD_Connect(void); - -extern void USBD_Disconnect(void); - -extern char USBD_Write( - unsigned char bEndpoint, - const void *pData, - unsigned int size, - TransferCallback callback, - void *pArg); - -extern char USBD_MblWrite( - unsigned char bEndpoint, - void * pMbl, - unsigned short wListSize, - unsigned char bCircList, - unsigned short wStartNdx, - MblTransferCallback fCallback, - void * pArgument); - -extern char USBD_MblReuse( - unsigned char bEndpoint, - unsigned char * pNewBuffer, - unsigned short wNewSize); - -extern char USBD_Read( - unsigned char bEndpoint, - void *pData, - unsigned int dLength, - TransferCallback fCallback, - void *pArg); - -extern unsigned char USBD_Stall(unsigned char bEndpoint); - -extern void USBD_Halt(unsigned char bEndpoint); - -extern void USBD_Unhalt(unsigned char bEndpoint); - -extern void USBD_ConfigureEndpoint(const USBEndpointDescriptor *pDescriptor); - -extern unsigned char USBD_IsHalted(unsigned char bEndpoint); - -extern void USBD_RemoteWakeUp(void); - -extern void USBD_SetAddress(unsigned char address); - -extern void USBD_SetConfiguration(unsigned char cfgnum); - -extern unsigned char USBD_GetState(void); - -extern unsigned char USBD_IsHighSpeed(void); - -extern void USBD_Test(unsigned char bIndex); - -#endif //#ifndef USBD_H - diff --git a/radio/bootloader/usb/device/core/USBDCallbacks.c b/radio/bootloader/usb/device/core/USBDCallbacks.c deleted file mode 100644 index cc0463a2e..000000000 --- a/radio/bootloader/usb/device/core/USBDCallbacks.c +++ /dev/null @@ -1,81 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBDCallbacks.h" -#include "USBD.h" -#include -#include -#include "debug.h" - -void USBDCallbacks_Initialized(void) -{ - UDP->UDP_ICR = 0x00000200 ; // CLear RXRSM flag - NVIC_EnableIRQ(UDP_IRQn); -} - -#if 0 -void USBDCallbacks_RequestReceived(const USBGenericRequest *pRequest) -{ - // Does nothing -} -#endif - -void USBDCallbacks_Reset(void) -{ - // Does nothing -} - -void USBDCallbacks_Resumed(void) -{ - // Does nothing -} - -void USBDCallbacks_Suspended(void) -{ - // Does nothing -} - -#if 0 -void USBDDriverCallbacks_ConfigurationChanged(unsigned char cfgnum) -{ - TRACE_INFO_WP("ConfigurationChanged "); -} -#endif - -void USBDDriverCallbacks_InterfaceSettingChanged( - unsigned char interface, - unsigned char setting) -{ - // TRACE_INFO_WP("InterfaceSettingChanged "); -} - diff --git a/radio/bootloader/usb/device/core/USBDCallbacks.h b/radio/bootloader/usb/device/core/USBDCallbacks.h deleted file mode 100644 index e18bece3e..000000000 --- a/radio/bootloader/usb/device/core/USBDCallbacks.h +++ /dev/null @@ -1,65 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definitions of callbacks used by the USBD API to notify the user - application of incoming events. These functions are declared as 'weak', - so they can be re-implemented elsewhere in the application in a - transparent way. -*/ - -#ifndef USBDCALLBACKS_H -#define USBDCALLBACKS_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern void USBDCallbacks_Initialized(void); - -extern void USBDCallbacks_Reset(void); - -extern void USBDCallbacks_Suspended(void); - -extern void USBDCallbacks_Resumed(void); - -extern void USBDCallbacks_RequestReceived(const USBGenericRequest *request); - -#endif //#ifndef USBDCALLBACKS_H - diff --git a/radio/bootloader/usb/device/core/USBDDriver.c b/radio/bootloader/usb/device/core/USBDDriver.c deleted file mode 100644 index 7e826435c..000000000 --- a/radio/bootloader/usb/device/core/USBDDriver.c +++ /dev/null @@ -1,753 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBDDriver.h" -#include "USBDDriverCallbacks.h" -#include "USBD.h" -#include -#include "debug.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -//------------------------------------------------------------------------------ -// Local functions -//------------------------------------------------------------------------------ -#if defined(CHIP_USB_OTGHS) -static unsigned char otg_features_supported = 0; -#endif - -//------------------------------------------------------------------------------ -/// Send a NULL packet -//------------------------------------------------------------------------------ -static void TerminateCtrlInWithNull(void *pArg, - unsigned char status, - unsigned int transferred, - unsigned int remaining) -{ - USBD_Write(0, // Endpoint #0 - 0, // No data buffer - 0, // No data buffer - (TransferCallback) 0, - (void *) 0); -} - -//------------------------------------------------------------------------------ -/// Configures the device by setting it into the Configured state and -/// initializing all endpoints. -/// \param pDriver Pointer to a USBDDriver instance. -/// \param cfgnum Configuration number to set. -//------------------------------------------------------------------------------ -static void SetConfiguration(USBDDriver *pDriver, unsigned char cfgnum) -{ - USBEndpointDescriptor *pEndpoints[CHIP_USB_NUMENDPOINTS+1]; - const USBConfigurationDescriptor *pConfiguration; - - // Use different descriptor depending on device speed - if (USBD_IsHighSpeed()) { - - pConfiguration = pDriver->pDescriptors->pHsConfiguration; - } - else { - - pConfiguration = pDriver->pDescriptors->pFsConfiguration; - } - - // Set & save the desired configuration - USBD_SetConfiguration(cfgnum); - pDriver->cfgnum = cfgnum; - - // If the configuration is not 0, configure endpoints - if (cfgnum != 0) { - - // Parse configuration to get endpoint descriptors - USBConfigurationDescriptor_Parse(pConfiguration, 0, pEndpoints, 0); - - // Configure endpoints - int i = 0; - while (pEndpoints[i] != 0) { - - USBD_ConfigureEndpoint(pEndpoints[i]); - i++; - } - } - // Should be done before send the ZLP - USBDDriverCallbacks_ConfigurationChanged(cfgnum); - - // Acknowledge the request - USBD_Write(0, // Endpoint #0 - 0, // No data buffer - 0, // No data buffer - (TransferCallback) 0, - (void *) 0); -} - -//------------------------------------------------------------------------------ -/// Sends the current configuration number to the host. -/// \param pDriver Pointer to a USBDDriver instance. -//------------------------------------------------------------------------------ -static void GetConfiguration(const USBDDriver *pDriver) -{ - USBD_Write(0, &(pDriver->cfgnum), 1, 0, 0); -} - -//------------------------------------------------------------------------------ -/// Sends the current status of the device to the host. -/// \param pDriver Pointer to a USBDDriver instance. -//------------------------------------------------------------------------------ -static void GetDeviceStatus(const USBDDriver *pDriver) -{ - static unsigned short data; - const USBConfigurationDescriptor *pConfiguration; - - data = 0; - // Use different configuration depending on device speed - if (USBD_IsHighSpeed()) { - - pConfiguration = pDriver->pDescriptors->pHsConfiguration; - } - else { - - pConfiguration = pDriver->pDescriptors->pFsConfiguration; - } - - // Check current configuration for power mode (if device is configured) - if (pDriver->cfgnum != 0) { - - if (USBConfigurationDescriptor_IsSelfPowered(pConfiguration)) { - - data |= 1; - } - } - - // Check if remote wake-up is enabled - if (pDriver->isRemoteWakeUpEnabled) { - - data |= 2; - } - - // Send the device status - USBD_Write(0, &data, 2, 0, 0); -} - -//------------------------------------------------------------------------------ -/// Sends the current status of an endpoints to the USB host. -/// \param bEndpoint Endpoint number. -//------------------------------------------------------------------------------ -static void GetEndpointStatus(unsigned char bEndpoint) -{ - static unsigned short data; - - data = 0; - // Check if the endpoint exists - if (bEndpoint > CHIP_USB_NUMENDPOINTS) { - - USBD_Stall(0); - } - else { - - // Check if the endpoint if currently halted - if (USBD_IsHalted(bEndpoint)) { - - data = 1; - } - - // Send the endpoint status - USBD_Write(0, &data, 2, 0, 0); - } -} - -//------------------------------------------------------------------------------ -/// Sends the requested USB descriptor to the host if available, or STALLs the -/// request. -/// \param pDriver Pointer to a USBDDriver instance. -/// \param type Type of the requested descriptor -/// \param index Index of the requested descriptor. -/// \param length Maximum number of bytes to return. -//------------------------------------------------------------------------------ -static void GetDescriptor( - const USBDDriver *pDriver, - unsigned char type, - unsigned char indexRDesc, - unsigned int length) -{ - const USBDeviceDescriptor *pDevice; - const USBConfigurationDescriptor *pConfiguration; - const USBDeviceQualifierDescriptor *pQualifier; - const USBConfigurationDescriptor *pOtherSpeed; - const USBGenericDescriptor **pStrings = - (const USBGenericDescriptor **) pDriver->pDescriptors->pStrings; - const USBGenericDescriptor *pString; - unsigned char numStrings = pDriver->pDescriptors->numStrings; - unsigned char terminateWithNull = 0; - - // Use different set of descriptors depending on device speed - if (USBD_IsHighSpeed()) { - - TRACE_DEBUG("HS "); - pDevice = pDriver->pDescriptors->pHsDevice; - pConfiguration = pDriver->pDescriptors->pHsConfiguration; - pQualifier = pDriver->pDescriptors->pHsQualifier; - pOtherSpeed = pDriver->pDescriptors->pHsOtherSpeed; - } - else { - - TRACE_DEBUG("FS "); - pDevice = pDriver->pDescriptors->pFsDevice; - pConfiguration = pDriver->pDescriptors->pFsConfiguration; - pQualifier = pDriver->pDescriptors->pFsQualifier; - pOtherSpeed = pDriver->pDescriptors->pFsOtherSpeed; - } - - // Check the descriptor type - switch (type) { - - case USBGenericDescriptor_DEVICE: - TRACE_INFO_WP("Dev "); - - // Adjust length and send descriptor - if (length > USBGenericDescriptor_GetLength((USBGenericDescriptor *) pDevice)) { - - length = USBGenericDescriptor_GetLength((USBGenericDescriptor *) pDevice); - } - USBD_Write(0, pDevice, length, 0, 0); - break; - - case USBGenericDescriptor_CONFIGURATION: - TRACE_INFO_WP("Cfg "); - - // Adjust length and send descriptor - if (length > USBConfigurationDescriptor_GetTotalLength(pConfiguration)) { - - length = USBConfigurationDescriptor_GetTotalLength(pConfiguration); - terminateWithNull = ((length % pDevice->bMaxPacketSize0) == 0); - } - USBD_Write(0, - pConfiguration, - length, - terminateWithNull ? TerminateCtrlInWithNull : 0, - 0); - break; - - case USBGenericDescriptor_DEVICEQUALIFIER: - TRACE_INFO_WP("Qua "); - - // Check if descriptor exists - if (!pQualifier) { - - USBD_Stall(0); - } - else { - - // Adjust length and send descriptor - if (length > USBGenericDescriptor_GetLength((USBGenericDescriptor *) pQualifier)) { - - length = USBGenericDescriptor_GetLength((USBGenericDescriptor *) pQualifier); - } - USBD_Write(0, pQualifier, length, 0, 0); - } - break; - - case USBGenericDescriptor_OTHERSPEEDCONFIGURATION: - TRACE_INFO_WP("OSC "); - - // Check if descriptor exists - if (!pOtherSpeed) { - - USBD_Stall(0); - } - else { - - // Adjust length and send descriptor - if (length > USBConfigurationDescriptor_GetTotalLength(pOtherSpeed)) { - - length = USBConfigurationDescriptor_GetTotalLength(pOtherSpeed); - terminateWithNull = ((length % pDevice->bMaxPacketSize0) == 0); - } - USBD_Write(0, - pOtherSpeed, - length, - terminateWithNull ? TerminateCtrlInWithNull : 0, - 0); - } - break; - - case USBGenericDescriptor_STRING: - TRACE_INFO_WP("Str%d ", indexRDesc); - - // Check if descriptor exists - if (indexRDesc > numStrings) { - - USBD_Stall(0); - } - else { - - pString = pStrings[indexRDesc]; - - // Adjust length and send descriptor - if (length > USBGenericDescriptor_GetLength(pString)) { - - length = USBGenericDescriptor_GetLength(pString); - terminateWithNull = ((length % pDevice->bMaxPacketSize0) == 0); - } - USBD_Write(0, - pString, - length, - terminateWithNull ? TerminateCtrlInWithNull : 0, - 0); - } - break; - - default: - TRACE_WARNING( - "USBDDriver_GetDescriptor: Unknown descriptor type (%d)\n\r", - type); - USBD_Stall(0); - } -} - -//------------------------------------------------------------------------------ -/// Sets the active setting of the given interface if the configuration supports -/// it; otherwise, the control pipe is STALLed. If the setting of an interface -/// changes. -/// \parma pDriver Pointer to a USBDDriver instance. -/// \parma infnum Interface number. -/// \parma setting New active setting for the interface. -//------------------------------------------------------------------------------ -static void SetInterface( - USBDDriver *pDriver, - unsigned char infnum, - unsigned char setting) -{ - // Make sure alternate settings are supported - if (!pDriver->pInterfaces) { - - USBD_Stall(0); - } - else { - - // Change the current setting of the interface and trigger the callback - // if necessary - if (pDriver->pInterfaces[infnum] != setting) { - - pDriver->pInterfaces[infnum] = setting; - USBDDriverCallbacks_InterfaceSettingChanged(infnum, setting); - } - - // Acknowledge the request - USBD_Write(0, 0, 0, 0, 0); - } -} - -//------------------------------------------------------------------------------ -/// Sends the currently active setting of the given interface to the USB -/// host. If alternate settings are not supported, this function STALLs the -/// control pipe. -/// \param pDriver Pointer to a USBDDriver instance. -/// \param infnum Interface number. -//------------------------------------------------------------------------------ -static void GetInterface( - const USBDDriver *pDriver, - unsigned char infnum) -{ - // Make sure alternate settings are supported, or STALL the control pipe - if (!pDriver->pInterfaces) { - - USBD_Stall(0); - } - else { - - // Sends the current interface setting to the host - USBD_Write(0, &(pDriver->pInterfaces[infnum]), 1, 0, 0); - } -} - -#if defined(CHIP_USB_UDPHS) || defined(CHIP_USB_OTGHS) -//------------------------------------------------------------------------------ -// Performs the selected test on the USB device (high-speed only). -// \param test Test selector value. -//------------------------------------------------------------------------------ -static void USBDDriver_Test(unsigned char test) -{ - TRACE_DEBUG("UDPHS_Test\n\r"); - - // the lower byte of wIndex must be zero - // the most significant byte of wIndex is used to specify the specific test mode - switch (test) { - case USBFeatureRequest_TESTPACKET: - //Test mode Test_Packet: - //Upon command, a port must repetitively transmit the following test packet until - //the exit action is taken. This enables the testing of rise and fall times, eye - //patterns, jitter, and any other dynamic waveform specifications. - //The test packet is made up by concatenating the following strings. - //(Note: For J/K NRZI data, and for NRZ data, the bit on the left is the first one - //transmitted. S indicates that a bit stuff occurs, which inserts an extra NRZI data bit. - //* N is used to indicate N occurrences of a string of bits or symbols.) - //A port in Test_Packet mode must send this packet repetitively. The inter-packet timing - //must be no less than the minimum allowable inter-packet gap as defined in Section 7.1.18 and - //no greater than 125 us. - // Send ZLP - USBD_Test(USBFeatureRequest_TESTSENDZLP); - // Tst PACKET - USBD_Test(USBFeatureRequest_TESTPACKET); - while (1); - //break; not reached - - case USBFeatureRequest_TESTJ: - //Test mode Test_J: - //Upon command, a ports transceiver must enter the high-speed J state and remain in that - //state until the exit action is taken. This enables the testing of the high output drive - //level on the D+ line. - // Send ZLP - USBD_Test(USBFeatureRequest_TESTSENDZLP); - // Tst J - USBD_Test(USBFeatureRequest_TESTJ); - while (1); - //break; not reached - - case USBFeatureRequest_TESTK: - //Test mode Test_K: - //Upon command, a ports transceiver must enter the high-speed K state and remain in - //that state until the exit action is taken. This enables the testing of the high output drive - //level on the D- line. - // Send a ZLP - USBD_Test(USBFeatureRequest_TESTSENDZLP); - USBD_Test(USBFeatureRequest_TESTK); - while (1); - //break; not reached - - case USBFeatureRequest_TESTSE0NAK: - //Test mode Test_SE0_NAK: - //Upon command, a ports transceiver must enter the high-speed receive mode - //and remain in that mode until the exit action is taken. This enables the testing - //of output impedance, low level output voltage, and loading characteristics. - //In addition, while in this mode, upstream facing ports (and only upstream facing ports) - //must respond to any IN token packet with a NAK handshake (only if the packet CRC is - //determined to be correct) within the normal allowed device response time. This enables testing of - //the device squelch level circuitry and, additionally, provides a general purpose stimulus/response - //test for basic functional testing. - // Send a ZLP - USBD_Test(USBFeatureRequest_TESTSENDZLP); - // Test SE0_NAK - USBD_Test(USBFeatureRequest_TESTSE0NAK); - while (1); - //break; not reached - - default: - USBD_Stall(0); - break; - - } - // The exit action is to power cycle the device. - // The device must be disconnected from the host -} -#endif - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Initializes a USBDDriver instance with a list of descriptors. If -/// interfaces can have multiple alternate settings, an array to store the -/// current setting for each interface must be provided. -/// \param pDriver Pointer to a USBDDriver instance. -/// \param pDescriptors Pointer to a USBDDriverDescriptors instance. -/// \param pInterfaces Pointer to an array for storing the current alternate -/// setting of each interface (optional). -//------------------------------------------------------------------------------ -void USBDDriver_Initialize( - USBDDriver *pDriver, - const USBDDriverDescriptors *pDescriptors, - unsigned char *pInterfaces) -{ - - pDriver->cfgnum = 0; -#if (BOARD_USB_BMATTRIBUTES == USBConfigurationDescriptor_SELFPOWERED_RWAKEUP) \ - || (BOARD_USB_BMATTRIBUTES == USBConfigurationDescriptor_BUSPOWERED_RWAKEUP) - pDriver->isRemoteWakeUpEnabled = 1; -#else - pDriver->isRemoteWakeUpEnabled = 0; -#endif - - pDriver->pDescriptors = pDescriptors; - pDriver->pInterfaces = pInterfaces; - - // Initialize interfaces array if not null - if (pInterfaces != 0) { - - memset(pInterfaces, sizeof(pInterfaces), 0); - } -} - -//------------------------------------------------------------------------------ -/// Handles the given request if it is standard, otherwise STALLs it. -/// \param pDriver Pointer to a USBDDriver instance. -/// \param pRequest Pointer to a USBGenericRequest instance. -//------------------------------------------------------------------------------ -void USBDDriver_RequestHandler( - USBDDriver *pDriver, - const USBGenericRequest *pRequest) -{ - unsigned char cfgnum; - unsigned char infnum; - unsigned char eptnum; - unsigned char setting; - unsigned char type; - unsigned char indexDesc; - unsigned int length; - unsigned int address; - - TRACE_INFO_WP("Std "); - - // Check request code - switch (USBGenericRequest_GetRequest(pRequest)) { - - case USBGenericRequest_GETDESCRIPTOR: - TRACE_INFO_WP("gDesc "); - - // Send the requested descriptor - type = USBGetDescriptorRequest_GetDescriptorType(pRequest); - indexDesc = USBGetDescriptorRequest_GetDescriptorIndex(pRequest); - length = USBGenericRequest_GetLength(pRequest); - GetDescriptor(pDriver, type, indexDesc, length); - break; - - case USBGenericRequest_SETADDRESS: - TRACE_INFO_WP("sAddr "); - - // Sends a zero-length packet and then set the device address - address = USBSetAddressRequest_GetAddress(pRequest); - USBD_Write(0, 0, 0, (TransferCallback) USBD_SetAddress, (void *) address); - break; - - case USBGenericRequest_SETCONFIGURATION: - TRACE_INFO_WP("sCfg "); - - // Set the requested configuration - cfgnum = USBSetConfigurationRequest_GetConfiguration(pRequest); - SetConfiguration(pDriver, cfgnum); - break; - - case USBGenericRequest_GETCONFIGURATION: - TRACE_INFO_WP("gCfg "); - - // Send the current configuration number - GetConfiguration(pDriver); - break; - - case USBGenericRequest_GETSTATUS: - TRACE_INFO_WP("gSta "); - - // Check who is the recipient - switch (USBGenericRequest_GetRecipient(pRequest)) { - - case USBGenericRequest_DEVICE: - TRACE_INFO_WP("Dev "); - - // Send the device status - GetDeviceStatus(pDriver); - break; - - case USBGenericRequest_ENDPOINT: - TRACE_INFO_WP("Ept "); - - // Send the endpoint status - eptnum = USBGenericRequest_GetEndpointNumber(pRequest); - GetEndpointStatus(eptnum); - break; - - default: - TRACE_WARNING( - "USBDDriver_RequestHandler: Unknown recipient (%d)\n\r", - USBGenericRequest_GetRecipient(pRequest)); - USBD_Stall(0); - } - break; - - case USBGenericRequest_CLEARFEATURE: - TRACE_INFO_WP("cFeat "); - - // Check which is the requested feature - switch (USBFeatureRequest_GetFeatureSelector(pRequest)) { - - case USBFeatureRequest_ENDPOINTHALT: - TRACE_INFO_WP("Hlt "); - - // Unhalt endpoint and send a zero-length packet - USBD_Unhalt(USBGenericRequest_GetEndpointNumber(pRequest)); - USBD_Write(0, 0, 0, 0, 0); - break; - - case USBFeatureRequest_DEVICEREMOTEWAKEUP: - TRACE_INFO_WP("RmWU "); - - // Disable remote wake-up and send a zero-length packet - pDriver->isRemoteWakeUpEnabled = 0; - USBD_Write(0, 0, 0, 0, 0); - break; - - default: - TRACE_WARNING( - "USBDDriver_RequestHandler: Unknown feature selector (%d)\n\r", - USBFeatureRequest_GetFeatureSelector(pRequest)); - USBD_Stall(0); - } - break; - - case USBGenericRequest_SETFEATURE: - TRACE_INFO_WP("sFeat "); - - // Check which is the selected feature - switch (USBFeatureRequest_GetFeatureSelector(pRequest)) { - - case USBFeatureRequest_DEVICEREMOTEWAKEUP: - TRACE_INFO_WP("RmWU "); - - // Enable remote wake-up and send a ZLP - pDriver->isRemoteWakeUpEnabled = 1; - USBD_Write(0, 0, 0, 0, 0); - break; - - case USBFeatureRequest_ENDPOINTHALT: - TRACE_INFO_WP("Halt "); - // Halt endpoint - USBD_Halt(USBGenericRequest_GetEndpointNumber(pRequest)); - USBD_Write(0, 0, 0, 0, 0); - break; - -#if defined(CHIP_USB_UDPHS) || defined(CHIP_USB_OTGHS) - - case USBFeatureRequest_TESTMODE: - // 7.1.20 Test Mode Support - if ((USBGenericRequest_GetType(pRequest) == USBGenericRequest_DEVICE) - && ((USBGenericRequest_GetIndex(pRequest) & 0x000F) == 0)) { - - // Handle test request - USBDDriver_Test(USBFeatureRequest_GetTestSelector(pRequest)); - } - else { - - USBD_Stall(0); - } - break; -#endif -#if defined(CHIP_USB_OTGHS) - case USBFeatureRequest_OTG_B_HNP_ENABLE: - TRACE_INFO_WP("OTG_B_HNP_ENABLE "); - otg_features_supported |= 1<isRemoteWakeUpEnabled; -} - -#if defined(CHIP_USB_OTGHS) -//------------------------------------------------------------------------------ -/// Return OTG features supported -/// \return the OTG features -//------------------------------------------------------------------------------ -unsigned char USBDDriver_returnOTGFeatures(void) -{ - return otg_features_supported; -} - -//------------------------------------------------------------------------------ -/// Clear OTG features supported -/// \return none -//------------------------------------------------------------------------------ -void USBDDriver_clearOTGFeatures(void) -{ - otg_features_supported = 0; -} -#endif - diff --git a/radio/bootloader/usb/device/core/USBDDriver.h b/radio/bootloader/usb/device/core/USBDDriver.h deleted file mode 100644 index 7f5a0b693..000000000 --- a/radio/bootloader/usb/device/core/USBDDriver.h +++ /dev/null @@ -1,101 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - USB Device Driver class definition. - - !!!Usage - - -# Instanciate a USBDDriver object and initialize it using - USBDDriver_Initialize. - -# When a USB SETUP request is received, forward it to the standard - driver using USBDDriver_RequestHandler. - -# Check the Remote Wakeup setting via USBDDriver_IsRemoteWakeUpEnabled. -*/ - -#ifndef USBDDRIVER_H -#define USBDDRIVER_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBDDriverDescriptors.h" -#include - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// USB device driver structure, holding a list of descriptors identifying -/// the device as well as the driver current state. -//------------------------------------------------------------------------------ -typedef struct { - - /// List of descriptors used by the device. - const USBDDriverDescriptors *pDescriptors; - /// Current setting for each interface. - unsigned char *pInterfaces; - /// Current configuration number (0 -> device is not configured). - unsigned char cfgnum; - /// Indicates if remote wake up has been enabled by the host. - unsigned char isRemoteWakeUpEnabled; -#if defined(CHIP_USB_OTGHS) - /// Features supported by OTG - unsigned char otg_features_supported; -#endif -} USBDDriver; - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern void USBDDriver_Initialize( - USBDDriver *pDriver, - const USBDDriverDescriptors *pDescriptors, - unsigned char *pInterfaces); - -extern void USBDDriver_RequestHandler( - USBDDriver *pDriver, - const USBGenericRequest *pRequest); - -extern unsigned char USBDDriver_IsRemoteWakeUpEnabled(const USBDDriver *pDriver); - -#if defined(CHIP_USB_OTGHS) -extern unsigned char USBDDriver_returnOTGFeatures(void); -extern void USBDDriver_clearOTGFeatures(void); -#endif - -#endif //#ifndef USBDDRIVER_H - diff --git a/radio/bootloader/usb/device/core/USBDDriverCallbacks.h b/radio/bootloader/usb/device/core/USBDDriverCallbacks.h deleted file mode 100644 index 9393dcc51..000000000 --- a/radio/bootloader/usb/device/core/USBDDriverCallbacks.h +++ /dev/null @@ -1,61 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of several callbacks which are triggered by the USB software - driver after receiving specific requests. - - !!!Usage - - -# Re-implement the USBDDriverCallbacks_ConfigurationChanged - callback to know when the hosts changes the active configuration of - the device. - -# Re-implement the USBDDriverCallbacks_InterfaceSettingChanged - callback to get notified whenever the active setting of an interface - is changed by the host. -*/ - -#ifndef USBDDRIVERCALLBACKS_H -#define USBDDRIVERCALLBACKS_H - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern void USBDDriverCallbacks_ConfigurationChanged(unsigned char cfgnum); - -extern void USBDDriverCallbacks_InterfaceSettingChanged(unsigned char interface, - unsigned char setting); - -#endif //#ifndef USBDDRIVERCALLBACKS_H - diff --git a/radio/bootloader/usb/device/core/USBDDriverDescriptors.h b/radio/bootloader/usb/device/core/USBDDriverDescriptors.h deleted file mode 100644 index e75197bec..000000000 --- a/radio/bootloader/usb/device/core/USBDDriverDescriptors.h +++ /dev/null @@ -1,86 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of a class for declaring USB descriptors required by the - device driver. -*/ - -#ifndef USBDDRIVERDESCRIPTORS_H -#define USBDDRIVERDESCRIPTORS_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include -#include -#include - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// List of all descriptors used by a USB device driver. Each descriptor can -/// be provided in two versions: full-speed and high-speed. Devices which are -/// not high-speed capable do not need to provided high-speed descriptors and -/// the full-speed qualifier & other speed descriptors. -//------------------------------------------------------------------------------ -typedef struct { - - /// Pointer to the full-speed device descriptor. - const USBDeviceDescriptor *pFsDevice; - /// Pointer to the full-speed configuration descriptor. - const USBConfigurationDescriptor *pFsConfiguration; - /// Pointer to the full-speed qualifier descriptor. - const USBDeviceQualifierDescriptor *pFsQualifier; - /// Pointer to the full-speed other speed configuration descriptor. - const USBConfigurationDescriptor *pFsOtherSpeed; - /// Pointer to the high-speed device descriptor. - const USBDeviceDescriptor *pHsDevice; - /// Pointer to the high-speed configuration descriptor. - const USBConfigurationDescriptor *pHsConfiguration; - /// Pointer to the high-speed qualifier descriptor. - const USBDeviceQualifierDescriptor *pHsQualifier; - /// Pointer to the high-speed other speed configuration descriptor. - const USBConfigurationDescriptor *pHsOtherSpeed; - /// Pointer to the list of string descriptors. - const unsigned char **pStrings; - /// Number of string descriptors in list. - unsigned char numStrings; - -} USBDDriverDescriptors; - -#endif //#ifndef USBDDRIVERDESCRIPTORS_H - diff --git a/radio/bootloader/usb/device/core/USBD_UDP.c b/radio/bootloader/usb/device/core/USBD_UDP.c deleted file mode 100644 index c525e35bf..000000000 --- a/radio/bootloader/usb/device/core/USBD_UDP.c +++ /dev/null @@ -1,1734 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Implementation of USB device functions on a UDP controller. - - See "USBD API Methods". -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBD.h" -#include "USBDCallbacks.h" -#include -//#include -#include "debug.h" -//#include -//#include -#include -#include - - -//------------------------------------------------------------------------------ -// Local definitions -//------------------------------------------------------------------------------ -#define MASK_STATUS0 0xFFFFFFFC -#define MASK_STATUS1 0xFFFFFFFF - - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Enables the clock of a peripheral. The peripheral ID is used - * to identify which peripheral is targetted. - * \note The ID must NOT be shifted (i.e. 1 << ID_xxx). - * \param id Peripheral ID (ID_xxx). - */ -void PMC_EnablePeripheral(unsigned int id) -{ - // SANITY_CHECK(id < 35); - - if (id < 32) { - if ((PMC->PMC_PCSR0 & (1 << id)) == (1 << id)) { - - TRACE_DEBUG("PMC_EnablePeripheral: clock of peripheral" " %u is already enabled\n\r", id); - } - else { - PMC->PMC_PCER0 = 1 << id; - } - } - else { - id -= 32; - if ((PMC->PMC_PCSR1 & (1 << id)) == (1 << id)) { - - TRACE_DEBUG("PMC_EnablePeripheral: clock of peripheral" " %u is already enabled\n\r", id + 32); - } - else { - PMC->PMC_PCER1 = 1 << id; - } - } -} - -/** - * \brief Disables the clock of a peripheral. The peripheral ID is used - * to identify which peripheral is targetted. - * \note The ID must NOT be shifted (i.e. 1 << ID_xxx). - * \param id Peripheral ID (ID_xxx). - */ -void PMC_DisablePeripheral(unsigned int id) -{ - // SANITY_CHECK(id < 35); - if (id < 32) { - if ((PMC->PMC_PCSR0 & (1 << id)) != (1 << id)) { - TRACE_DEBUG("PMC_DisablePeripheral: clock of peripheral" " %u is not enabled\n\r", id); - } - else { - PMC->PMC_PCDR0 = 1 << id; - } - } - else { - id -= 32; - if ((PMC->PMC_PCSR1 & (1 << id)) != (1 << id)) { - TRACE_DEBUG("PMC_DisablePeripheral: clock of peripheral" " %u is not enabled\n\r", id + 32); - } - else { - PMC->PMC_PCDR1 = 1 << id; - } - } -} - -/** - * \brief Enable all the periph clock via PMC - */ -void PMC_EnableAllPeripherals(void) -{ - PMC->PMC_PCER0 = MASK_STATUS0; - while( (PMC->PMC_PCSR0 & MASK_STATUS0) != MASK_STATUS0); - PMC->PMC_PCER1 = MASK_STATUS1; - while( (PMC->PMC_PCSR1 & MASK_STATUS1) != MASK_STATUS1); - TRACE_DEBUG("Enable all periph clocks\n\r"); -} -/** - * \brief Disable all the periph clock via PMC - */ -void PMC_DisableAllPeripherals(void) -{ - PMC->PMC_PCDR0 = MASK_STATUS0; - while((PMC->PMC_PCSR0 & MASK_STATUS0) != 0); - PMC->PMC_PCDR1 = MASK_STATUS1; - while((PMC->PMC_PCSR1 & MASK_STATUS1) != 0); - TRACE_DEBUG("Disable all periph clocks\n\r"); -} - -/** - * \brief Get Periph Status for the given peripheral ID. - * \param id Peripheral ID (ID_xxx). - */ -unsigned int PMC_IsPeriphEnabled(unsigned int id) -{ - // SANITY_CHECK(id < 35); - - if (id < 32) { - return (PMC->PMC_PCSR0 & (1 << id)); - } - else { - return (PMC->PMC_PCSR1 & (1 << (id - 32))); - } -} - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "UDP register field values" -/// -/// This page lists the initialize values of UDP registers. -/// -/// !Values -/// - UDP_RXDATA - -/// Bit mask for both banks of the UDP_CSR register. -#define UDP_CSR_RXDATA_BK (UDP_CSR_RX_DATA_BK0 | UDP_CSR_RX_DATA_BK1) -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "Endpoint states" -/// -/// This page lists the endpoint states. -/// -/// !States -// - UDP_ENDPOINT_DISABLED -// - UDP_ENDPOINT_HALTED -// - UDP_ENDPOINT_IDLE -// - UDP_ENDPOINT_SENDING -// - UDP_ENDPOINT_RECEIVING -// - UDP_ENDPOINT_SENDINGM -// - UDP_ENDPOINT_RECEIVINGM - -/// Endpoint states: Endpoint is disabled -#define UDP_ENDPOINT_DISABLED 0 -/// Endpoint states: Endpoint is halted (i.e. STALLs every request) -#define UDP_ENDPOINT_HALTED 1 -/// Endpoint states: Endpoint is idle (i.e. ready for transmission) -#define UDP_ENDPOINT_IDLE 2 -/// Endpoint states: Endpoint is sending data -#define UDP_ENDPOINT_SENDING 3 -/// Endpoint states: Endpoint is receiving data -#define UDP_ENDPOINT_RECEIVING 4 -/// Endpoint states: Endpoint is sending MBL -#define UDP_ENDPOINT_SENDINGM 5 -/// Endpoint states: Endpoint is receiving MBL -#define UDP_ENDPOINT_RECEIVINGM 6 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "UDP_CSR register access" -/// -/// This page lists the macroes to access UDP CSR register. -/// -/// !Macros -/// - CLEAR_CSR -/// - SET_CSR - -/// Bitmap for all status bits in CSR. -#define REG_NO_EFFECT_1_ALL UDP_CSR_RX_DATA_BK0 | UDP_CSR_RX_DATA_BK1 \ - |UDP_CSR_STALLSENTISOERROR | UDP_CSR_RXSETUP \ - |UDP_CSR_TXCOMP - -/// Clears the specified bit(s) in the UDP_CSR register. -/// \param endpoint The endpoint number of the CSR to process. -/// \param flags The bitmap to set to 1. -#define SET_CSR(endpoint, flags) \ - { \ - volatile unsigned int reg; \ - int timeOut = 200; \ - reg = UDP->UDP_CSR[endpoint] ; \ - reg |= REG_NO_EFFECT_1_ALL; \ - reg |= (flags); \ - UDP->UDP_CSR[endpoint] = reg; \ - while ( (UDP->UDP_CSR[endpoint] & (flags)) != (flags)) \ - { \ - if (-- timeOut <= 0) break; \ - } \ - } - -/// Sets the specified bit(s) in the UDP_CSR register. -/// \param endpoint The endpoint number of the CSR to process. -/// \param flags The bitmap to clear to 0. -#define CLEAR_CSR(endpoint, flags) \ - { \ - volatile unsigned int reg; \ - reg = UDP->UDP_CSR[endpoint]; \ - reg |= REG_NO_EFFECT_1_ALL; \ - reg &= ~(flags); \ - UDP->UDP_CSR[endpoint] = reg; \ - while ( (UDP->UDP_CSR[endpoint] & (flags)) == (flags)); \ - } -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -/// Describes an ongoing transfer on a UDP endpoint. -typedef struct { - - /// Pointer to a data buffer used for emission/reception. - char *pData; - /// Number of bytes which have been written into the UDP internal FIFO - /// buffers. - volatile int buffered; - /// Number of bytes which have been sent/received. - volatile int transferred; - /// Number of bytes which have not been buffered/transferred yet. - volatile int remaining; - /// Optional callback to invoke when the transfer completes. - volatile TransferCallback fCallback; - /// Optional argument to the callback function. - void *pArgument; -} Transfer; - -/// Describes Multi Buffer List transfer on a UDP endpoint. -typedef struct { - /// Pointer to frame list - USBDTransferBuffer *pMbl; - /// Pointer to last loaded buffer - USBDTransferBuffer *pLastLoaded; - /// List size - unsigned short listSize; - /// Current processing frame - unsigned short currBuffer; - /// First freed frame to re-use - unsigned short freedBuffer; - /// Frame setting, circle frame list - unsigned char circList; - /// All buffer listed is used - unsigned char allUsed; - /// Optional callback to invoke when the transfer completes. - MblTransferCallback fCallback; - /// Optional argument to the callback function. - void *pArgument; -} MblTransfer; - -//------------------------------------------------------------------------------ -/// Describes the state of an endpoint of the UDP controller. -//------------------------------------------------------------------------------ -typedef struct { - - /// Current endpoint state. - volatile unsigned char state; - /// Current reception bank (0 or 1). - volatile unsigned char bank; - /// Maximum packet size for the endpoint. - volatile unsigned short size; - /// Describes an ongoing transfer (if current state is either - /// or ) - union { - Transfer singleTransfer; - MblTransfer mblTransfer; - } transfer; -} Endpoint; - -//------------------------------------------------------------------------------ -// Internal variables -//------------------------------------------------------------------------------ - -/// Holds the internal state for each endpoint of the UDP. -static Endpoint endpoints[CHIP_USB_NUMENDPOINTS]; - -/// Device current state. -static unsigned char deviceState; -/// Indicates the previous device state -static unsigned char previousDeviceState; - -//------------------------------------------------------------------------------ -// Internal Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Enables the clock of the UDP peripheral. -/// \return 1 if peripheral status changed. -//------------------------------------------------------------------------------ -static unsigned char UDP_EnablePeripheralClock(void) -{ - if (!PMC_IsPeriphEnabled(ID_UDP)) { - PMC_EnablePeripheral(ID_UDP); - return 1; - } - return 0; -} - -//------------------------------------------------------------------------------ -/// Disables the UDP peripheral clock. -//------------------------------------------------------------------------------ -static inline void UDP_DisablePeripheralClock(void) -{ - PMC_DisablePeripheral(ID_UDP); -} - -//------------------------------------------------------------------------------ -/// Enables the 48MHz USB clock. -//------------------------------------------------------------------------------ -static inline void UDP_EnableUsbClock(void) -{ - REG_PMC_SCER = PMC_SCER_UDP; -} - -//------------------------------------------------------------------------------ -/// Disables the 48MHz USB clock. -//------------------------------------------------------------------------------ -static inline void UDP_DisableUsbClock(void) -{ - REG_PMC_SCDR = PMC_SCER_UDP; -} - -//------------------------------------------------------------------------------ -/// Enables the UDP transceiver. -//------------------------------------------------------------------------------ -static inline void UDP_EnableTransceiver(void) -{ - UDP->UDP_TXVC &= ~UDP_TXVC_TXVDIS; -} - -//------------------------------------------------------------------------------ -/// Disables the UDP transceiver. -//------------------------------------------------------------------------------ -static inline void UDP_DisableTransceiver(void) -{ - UDP->UDP_TXVC |= UDP_TXVC_TXVDIS; -} - -//------------------------------------------------------------------------------ -/// Handles a completed transfer on the given endpoint, invoking the -/// configured callback if any. -/// \param bEndpoint Number of the endpoint for which the transfer has completed. -/// \param bStatus Status code returned by the transfer operation -//------------------------------------------------------------------------------ -static void UDP_EndOfTransfer(unsigned char bEndpoint, char bStatus) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - - // Check that endpoint was sending or receiving data - if( (pEndpoint->state == UDP_ENDPOINT_RECEIVING) - || (pEndpoint->state == UDP_ENDPOINT_SENDING)) { - - Transfer *pTransfer = (Transfer *)&(pEndpoint->transfer); - - TRACE_DEBUG_WP("EoT "); - - // Endpoint returns in Idle state - pEndpoint->state = UDP_ENDPOINT_IDLE; - - // Invoke callback is present - if (pTransfer->fCallback != 0) { - - ((TransferCallback) pTransfer->fCallback) - (pTransfer->pArgument, - bStatus, - pTransfer->transferred, - pTransfer->remaining + pTransfer->buffered); - } - else { - TRACE_DEBUG_WP("NoCB "); - } - } - else if ( (pEndpoint->state == UDP_ENDPOINT_RECEIVINGM) - || (pEndpoint->state == UDP_ENDPOINT_SENDINGM) ) { - - MblTransfer *pTransfer = (MblTransfer*)&(pEndpoint->transfer); - - TRACE_DEBUG_WP("EoMT "); - - // Endpoint returns in Idle state - pEndpoint->state = UDP_ENDPOINT_IDLE; - // Invoke callback - if (pTransfer->fCallback != 0) { - - ((MblTransferCallback) pTransfer->fCallback) - (pTransfer->pArgument, - bStatus, - 0); - } - else { - TRACE_DEBUG_WP("NoCB "); - } - } -} - -//------------------------------------------------------------------------------ -/// Clears the correct reception flag (bank 0 or bank 1) of an endpoint -/// \param bEndpoint Index of endpoint -//------------------------------------------------------------------------------ -static void UDP_ClearRxFlag(unsigned char bEndpoint) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - - // Clear flag and change banks - if (pEndpoint->bank == 0) { - - CLEAR_CSR(bEndpoint, UDP_CSR_RX_DATA_BK0); - // Swap bank if in dual-fifo mode - if (CHIP_USB_ENDPOINTS_BANKS(bEndpoint) > 1) { - - pEndpoint->bank = 1; - } - } - else { - - CLEAR_CSR(bEndpoint, UDP_CSR_RX_DATA_BK1); - pEndpoint->bank = 0; - } -} - -//------------------------------------------------------------------------------ -/// Update multi-buffer-transfer descriptors. -/// \param pTransfer Pointer to instance MblTransfer. -/// \param size Size of bytes that processed. -/// \param forceEnd Force the buffer END. -/// \return 1 if current buffer ended. -//------------------------------------------------------------------------------ -static char UDP_MblUpdate(MblTransfer *pTransfer, - USBDTransferBuffer * pBi, - unsigned short size, - unsigned char forceEnd) -{ - // Update transfer descriptor - pBi->remaining -= size; - // Check if current buffer ended - if (pBi->remaining == 0 || forceEnd) { - - // Process to next buffer - if ((++ pTransfer->currBuffer) == pTransfer->listSize) { - if (pTransfer->circList) { - pTransfer->currBuffer = 0; - } - else { - pTransfer->allUsed = 1; - } - } - // All buffer in the list is processed - if (pTransfer->currBuffer == pTransfer->freedBuffer) { - pTransfer->allUsed = 1; - } - // Continue transfer, prepare for next operation - if (pTransfer->allUsed == 0) { - pBi = &pTransfer->pMbl[pTransfer->currBuffer]; - pBi->buffered = 0; - pBi->transferred = 0; - pBi->remaining = pBi->size; - } - return 1; - } - return 0; -} - -//------------------------------------------------------------------------------ -/// Transfers a data payload from the current tranfer buffer to the endpoint -/// FIFO -/// \param bEndpoint Number of the endpoint which is sending data. -//------------------------------------------------------------------------------ -static char UDP_MblWriteFifo(unsigned char bEndpoint) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - MblTransfer *pTransfer = (MblTransfer*)&(pEndpoint->transfer); - USBDTransferBuffer *pBi = &(pTransfer->pMbl[pTransfer->currBuffer]); - signed int size; - - volatile unsigned char * pBytes; - volatile char bufferEnd = 1; - - // Get the number of bytes to send - size = pEndpoint->size; - if (size > pBi->remaining) { - - size = pBi->remaining; - } - - TRACE_DEBUG_WP("w%d.%d ", pTransfer->currBuffer, size); - if (size == 0) { - - return 1; - } - - pTransfer->pLastLoaded = pBi; - pBytes = &(pBi->pBuffer[pBi->transferred + pBi->buffered]); - pBi->buffered += size; - bufferEnd = UDP_MblUpdate(pTransfer, pBi, size, 0); - - // Write packet in the FIFO buffer - if (size) { - signed int c8 = size >> 3; - signed int c1 = size & 0x7; - //printf("%d[%x] ", pBi->transferred, pBytes); - for (; c8; c8 --) { - UDP->UDP_FDR[bEndpoint] = *(pBytes ++); - UDP->UDP_FDR[bEndpoint] = *(pBytes ++); - UDP->UDP_FDR[bEndpoint] = *(pBytes ++); - UDP->UDP_FDR[bEndpoint] = *(pBytes ++); - - UDP->UDP_FDR[bEndpoint] = *(pBytes ++); - UDP->UDP_FDR[bEndpoint] = *(pBytes ++); - UDP->UDP_FDR[bEndpoint] = *(pBytes ++); - UDP->UDP_FDR[bEndpoint] = *(pBytes ++); - } - for (; c1; c1 --) { - UDP->UDP_FDR[bEndpoint] = *(pBytes ++); - } - } - return bufferEnd; -} -/* -//------------------------------------------------------------------------------ -/// Transfers a data payload from an endpoint FIFO to the current transfer -/// buffer, if NULL packet received, the current buffer is ENDed. -/// \param bEndpoint Endpoint number. -/// \param wPacketSize Size of received data packet -/// \return 1 if the buffer ENDed. -//------------------------------------------------------------------------------ -static char UDP_MblReadFifo(unsigned char bEndpoint, unsigned short wPacketSize) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - MblTransfer *pTransfer = (MblTransfer*)&(pEndpoint->transfer); - USBDTransferBuffer *pBi = &(pTransfer->pMbl[pTransfer->currBuffer]); - char bufferEnd; - - // Check that the requested size is not bigger than the remaining transfer - if (wPacketSize > pTransfer->remaining) { - - pTransfer->buffered += wPacketSize - pTransfer->remaining; - wPacketSize = pTransfer->remaining; - } - - // Update transfer descriptor information - pBi->transferred += wPacketSize; - bufferEnd = UDP_MblUpdate(pTransfer, - wPacketSize, - (wPacketSize < pEndpoint->size)); - - // Retrieve packet - if (wPacketSize) { - unsigned char * pBytes = &pBi->pBuffer[pBi->transferred]; - signed int c8 = wPacketSize >> 3; - signed int c1 = wPacketSize & 0x7; - for (; c8; c8 --) { - *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; - *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; - *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; - *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; - - *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; - *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; - *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; - *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; - } - for (; c1; c1 --) { - *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; - } - } - return bufferEnd; -} -*/ -//------------------------------------------------------------------------------ -/// Transfers a data payload from the current tranfer buffer to the endpoint -/// FIFO -/// \param bEndpoint Number of the endpoint which is sending data. -//------------------------------------------------------------------------------ -static void UDP_WritePayload(unsigned char bEndpoint) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - Transfer *pTransfer = (Transfer*)&(pEndpoint->transfer); - signed int size; - - // Get the number of bytes to send - size = pEndpoint->size; - if (size > pTransfer->remaining) { - - size = pTransfer->remaining; - } - - // Update transfer descriptor information - pTransfer->buffered += size; - pTransfer->remaining -= size; - - // Write packet in the FIFO buffer - while (size > 0) { - - UDP->UDP_FDR[bEndpoint] = *(pTransfer->pData); - pTransfer->pData++; - size--; - } -} - - -//------------------------------------------------------------------------------ -/// Transfers a data payload from an endpoint FIFO to the current transfer buffer -/// \param bEndpoint Endpoint number. -/// \param wPacketSize Size of received data packet -//------------------------------------------------------------------------------ -static void UDP_ReadPayload(unsigned char bEndpoint, int wPacketSize) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - Transfer *pTransfer = (Transfer*)&(pEndpoint->transfer); - - // Check that the requested size is not bigger than the remaining transfer - if (wPacketSize > pTransfer->remaining) { - - pTransfer->buffered += wPacketSize - pTransfer->remaining; - wPacketSize = pTransfer->remaining; - } - - // Update transfer descriptor information - pTransfer->remaining -= wPacketSize; - pTransfer->transferred += wPacketSize; - - // Retrieve packet - while (wPacketSize > 0) { - - *(pTransfer->pData) = (char) UDP->UDP_FDR[bEndpoint]; - pTransfer->pData++; - wPacketSize--; - } -} - -//------------------------------------------------------------------------------ -/// Received SETUP packet from endpoint 0 FIFO -/// \param pRequest Generic USB SETUP request sent over Control endpoints -//------------------------------------------------------------------------------ -static void UDP_ReadRequest(USBGenericRequest *pRequest) -{ - unsigned char *pData = (unsigned char *)pRequest; - unsigned int i; - - // Copy packet - for (i = 0; i < 8; i++) { - - *pData = (unsigned char) UDP->UDP_FDR[0]; - pData++; - } -} - -//------------------------------------------------------------------------------ -/// Reset all endpoint transfer descriptors -//------------------------------------------------------------------------------ -static void UDP_ResetEndpoints( void ) -{ - Endpoint *pEndpoint; - Transfer *pTransfer; - unsigned char bEndpoint; - - // Reset the transfer descriptor of every endpoint - for (bEndpoint = 0; bEndpoint < CHIP_USB_NUMENDPOINTS; bEndpoint++) { - - pEndpoint = &(endpoints[bEndpoint]); - pTransfer = (Transfer*)&(pEndpoint->transfer); - - // Reset endpoint transfer descriptor - pTransfer->pData = 0; - pTransfer->transferred = -1; - pTransfer->buffered = -1; - pTransfer->remaining = -1; - pTransfer->fCallback = 0; - pTransfer->pArgument = 0; - - // Reset endpoint state - pEndpoint->bank = 0; - pEndpoint->state = UDP_ENDPOINT_DISABLED; - } -} - -//------------------------------------------------------------------------------ -/// Disable all endpoints (except control endpoint 0), aborting current -/// transfers if necessary -//------------------------------------------------------------------------------ -static void UDP_DisableEndpoints( void ) - -{ - unsigned char bEndpoint; - - // Disable each endpoint, terminating any pending transfer - // Control endpoint 0 is not disabled - for (bEndpoint = 1; bEndpoint < CHIP_USB_NUMENDPOINTS; bEndpoint++) { - - UDP_EndOfTransfer(bEndpoint, USBD_STATUS_ABORTED); - endpoints[bEndpoint].state = UDP_ENDPOINT_DISABLED; - } -} - -//------------------------------------------------------------------------------ -/// Checks if an ongoing transfer on an endpoint has been completed. -/// \param bEndpoint Endpoint number. -/// \return 1 if the current transfer on the given endpoint is complete; -/// otherwise 0. -//------------------------------------------------------------------------------ -static unsigned char UDP_IsTransferFinished(unsigned char bEndpoint) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - Transfer *pTransfer = (Transfer*)&(pEndpoint->transfer); - - // Check if it is a Control endpoint - // -> Control endpoint must always finish their transfer with a zero-length - // packet - if ((UDP->UDP_CSR[bEndpoint] & UDP_CSR_EPTYPE) - == UDP_CSR_EPTYPE_CTRL) { - - return (pTransfer->buffered < pEndpoint->size); - } - // Other endpoints only need to transfer all the data - else { - - return (pTransfer->buffered <= pEndpoint->size) - && (pTransfer->remaining == 0); - } -} - -//------------------------------------------------------------------------------ -/// Endpoint interrupt handler. -/// Handle IN/OUT transfers, received SETUP packets and STALLing -/// \param bEndpoint Index of endpoint -//------------------------------------------------------------------------------ -static void UDP_EndpointHandler(unsigned char bEndpoint) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - Transfer *pTransfer = (Transfer*)&(pEndpoint->transfer); - MblTransfer *pMblt = (MblTransfer*)&(pEndpoint->transfer); - unsigned int status = UDP->UDP_CSR[bEndpoint]; - unsigned short wPacketSize; - USBGenericRequest request; - - TRACE_DEBUG_WP("E%d ", bEndpoint); - TRACE_DEBUG_WP("st:0x%X ", status); - - // Handle interrupts - // IN packet sent - if ((status & UDP_CSR_TXCOMP) != 0) { - - TRACE_DEBUG_WP("Wr "); - - // Check that endpoint was in MBL Sending state - if (pEndpoint->state == UDP_ENDPOINT_SENDINGM) { - - USBDTransferBuffer * pMbli = pMblt->pLastLoaded; - unsigned char bufferEnd = 0; - - TRACE_DEBUG_WP("TxM%d.%d ", pMblt->allUsed, pMbli->buffered); - - // End of transfer ? - if (pMblt->allUsed && pMbli->buffered == 0) { - - pMbli->transferred += pMbli->buffered; - pMbli->buffered = 0; - - // Disable interrupt - UDP->UDP_IDR = 1 << bEndpoint; - UDP_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); - CLEAR_CSR(bEndpoint, UDP_CSR_TXCOMP); - } - else { - - // Transfer remaining data - TRACE_DEBUG_WP("%d ", pEndpoint->size); - - if (pMbli->buffered > pEndpoint->size) { - pMbli->transferred += pEndpoint->size; - pMbli->buffered -= pEndpoint->size; - } - else { - pMbli->transferred += pMbli->buffered; - pMbli->buffered = 0; - } - - // Send next packet - if (CHIP_USB_ENDPOINTS_BANKS(bEndpoint) == 1) { - - // No double buffering - bufferEnd = UDP_MblWriteFifo(bEndpoint); - SET_CSR(bEndpoint, UDP_CSR_TXPKTRDY); - CLEAR_CSR(bEndpoint, UDP_CSR_TXCOMP); - } - else { - // Double buffering - SET_CSR(bEndpoint, UDP_CSR_TXPKTRDY); - CLEAR_CSR(bEndpoint, UDP_CSR_TXCOMP); - bufferEnd = UDP_MblWriteFifo(bEndpoint); - } - - if (bufferEnd && pMblt->fCallback) { - ((MblTransferCallback) pTransfer->fCallback) - (pTransfer->pArgument, - USBD_STATUS_PARTIAL_DONE, - 1); - } - } - } - // Check that endpoint was in Sending state - else if (pEndpoint->state == UDP_ENDPOINT_SENDING) { - - // End of transfer ? - if (UDP_IsTransferFinished(bEndpoint)) { - - pTransfer->transferred += pTransfer->buffered; - pTransfer->buffered = 0; - - // Disable interrupt if this is not a control endpoint - if ((status & UDP_CSR_EPTYPE) != UDP_CSR_EPTYPE_CTRL) { - - UDP->UDP_IDR = 1 << bEndpoint; - } - - UDP_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); - CLEAR_CSR(bEndpoint, UDP_CSR_TXCOMP); - } - else { - - // Transfer remaining data - TRACE_DEBUG_WP(" %d ", pEndpoint->size); - - pTransfer->transferred += pEndpoint->size; - pTransfer->buffered -= pEndpoint->size; - - // Send next packet - if (CHIP_USB_ENDPOINTS_BANKS(bEndpoint) == 1) { - - // No double buffering - UDP_WritePayload(bEndpoint); - SET_CSR(bEndpoint, UDP_CSR_TXPKTRDY); - CLEAR_CSR(bEndpoint, UDP_CSR_TXCOMP); - } - else { - // Double buffering - SET_CSR(bEndpoint, UDP_CSR_TXPKTRDY); - CLEAR_CSR(bEndpoint, UDP_CSR_TXCOMP); - UDP_WritePayload(bEndpoint); - } - } - } - else { - // Acknowledge interrupt - TRACE_ERROR("Error Wr"); - CLEAR_CSR(bEndpoint, UDP_CSR_TXCOMP); - } - } - - // OUT packet received - if ((status & UDP_CSR_RXDATA_BK) != 0) { - - TRACE_DEBUG_WP("Rd "); - - // Check that the endpoint is in Receiving state - if (pEndpoint->state != UDP_ENDPOINT_RECEIVING) { - - // Check if an ACK has been received on a Control endpoint - if (((status & UDP_CSR_EPTYPE) == UDP_CSR_EPTYPE_CTRL) - && ((status & UDP_CSR_RXBYTECNT) == 0)) { - - // Acknowledge the data and finish the current transfer - UDP_ClearRxFlag(bEndpoint); - UDP_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); - } - // Check if the data has been STALLed - else if ((status & UDP_CSR_FORCESTALL) != 0) { - - // Discard STALLed data - TRACE_DEBUG_WP("Discard "); - UDP_ClearRxFlag(bEndpoint); - } - // NAK the data - else { - - TRACE_DEBUG_WP("Nak "); - UDP->UDP_IDR = 1 << bEndpoint; - } - } - // Endpoint is in Read state - else { - - // Retrieve data and store it into the current transfer buffer - wPacketSize = (unsigned short) (status >> 16); - TRACE_DEBUG_WP("%d ", wPacketSize); - UDP_ReadPayload(bEndpoint, wPacketSize); - UDP_ClearRxFlag(bEndpoint); - - // Check if the transfer is finished - if ((pTransfer->remaining == 0) || (wPacketSize < pEndpoint->size)) { - - // Disable interrupt if this is not a control endpoint - if ((status & UDP_CSR_EPTYPE) != UDP_CSR_EPTYPE_CTRL) { - - UDP->UDP_IDR = 1 << bEndpoint; - } - UDP_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); - } - } - } - - // STALL sent - if ((status & UDP_CSR_STALLSENTISOERROR) != 0) { - - TRACE_WARNING( "Sta 0x%X [%d] ", status, bEndpoint); - - // If the endpoint is not halted, clear the STALL condition - CLEAR_CSR(bEndpoint, UDP_CSR_STALLSENTISOERROR); - if (pEndpoint->state != UDP_ENDPOINT_HALTED) { - - TRACE_WARNING( "_ " ); - CLEAR_CSR(bEndpoint, UDP_CSR_FORCESTALL); - } - } - - // SETUP packet received - if ((status & UDP_CSR_RXSETUP) != 0) { - - TRACE_DEBUG_WP("Stp "); - - // If a transfer was pending, complete it - // Handles the case where during the status phase of a control write - // transfer, the host receives the device ZLP and ack it, but the ack - // is not received by the device - if ((pEndpoint->state == UDP_ENDPOINT_RECEIVING) - || (pEndpoint->state == UDP_ENDPOINT_SENDING)) { - - UDP_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); - } - // Copy the setup packet - UDP_ReadRequest(&request); - - // Set the DIR bit before clearing RXSETUP in Control IN sequence - if (USBGenericRequest_GetDirection(&request) == USBGenericRequest_IN) { - - SET_CSR(bEndpoint, UDP_CSR_DIR); - } - // Acknowledge setup packet - CLEAR_CSR(bEndpoint, UDP_CSR_RXSETUP); - - // Forward the request to the upper layer - USBDCallbacks_RequestReceived(&request); - } - -} - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -//------------------------------------------------------------------------------ -/// USB device interrupt handler -/// Manages device resume, suspend, end of bus reset. -/// Forwards endpoint interrupts to the appropriate handler. -//------------------------------------------------------------------------------ -void USBD_IRQHandler(void) -{ - unsigned int status; - int eptnum = 0; - - // Get interrupt status - // Some interrupts may get masked depending on the device state - status = UDP->UDP_ISR; - status &= UDP->UDP_IMR; - - if (deviceState < USBD_STATE_POWERED) { - - status &= UDP_ICR_WAKEUP | UDP_ICR_RXRSM; - UDP->UDP_ICR = ~status; - } - - // Return immediately if there is no interrupt to service - if (status == 0) { - - TRACE_DEBUG_WP(".\n\r"); - return; - } - - // Toggle USB LED if the device is active - if (deviceState >= USBD_STATE_POWERED) { - - // LED_Set(USBD_LEDUSB); - } - - // Service interrupts - - //// Start Of Frame (SOF) - //if (ISSET(dStatus, UDP_ISR_SOFINT)) { - // - // TRACE_DEBUG("SOF"); - // - // // Invoke the SOF callback - // USB_StartOfFrameCallback(pUsb); - // - // // Acknowledge interrupt - // UDP->UDP_ICR = UDP_ICR_SOFINT; - // dStatus &= ~UDP_ISR_SOFINT; - //} - - // Suspend - // This interrupt is always treated last (hence the '==') - if (status == UDP_ISR_RXSUSP) { - - TRACE_INFO_WP("Susp "); - - // Don't do anything if the device is already suspended - if (deviceState != USBD_STATE_SUSPENDED) { - - // The device enters the Suspended state - // Enable wakeup - UDP->UDP_IER = UDP_IER_WAKEUP | UDP_IER_RXRSM; - - // Acknowledge interrupt - UDP->UDP_ICR = UDP_ICR_RXSUSP; - - // Switch to the Suspended state - previousDeviceState = deviceState; - deviceState = USBD_STATE_SUSPENDED; - // Invoke the Suspended callback - USBDCallbacks_Suspended(); - UDP_DisableTransceiver(); - UDP_DisablePeripheralClock(); - UDP_DisableUsbClock(); - } - } - // Resume - else if ((status & (UDP_ISR_WAKEUP | UDP_ISR_RXRSM)) != 0) { - - TRACE_INFO_WP("Res "); - - // Don't do anything if the device was not suspended - if (deviceState == USBD_STATE_SUSPENDED) { - - // The device enters its previous state - UDP_EnablePeripheralClock(); - UDP_EnableUsbClock(); - - // Enable the transceiver if the device was past the Default - // state - deviceState = previousDeviceState; - if (deviceState >= USBD_STATE_DEFAULT) { - - UDP_EnableTransceiver(); - - // Invoke the Resume callback - USBDCallbacks_Resumed(); - } - } - - // Clear and disable resume interrupts - UDP->UDP_ICR = UDP_ICR_WAKEUP | UDP_ICR_RXRSM | UDP_ICR_RXSUSP; - UDP->UDP_IDR = UDP_IDR_WAKEUP | UDP_IDR_RXRSM; - } - // End of bus reset - else if ((status & UDP_ISR_ENDBUSRES) != 0) { - - TRACE_INFO_WP("EoBRes "); - - // The device enters the Default state - deviceState = USBD_STATE_DEFAULT; - UDP_EnableTransceiver(); - UDP_ResetEndpoints(); - UDP_DisableEndpoints(); - USBD_ConfigureEndpoint(0); - - // Flush and enable the Suspend interrupt - UDP->UDP_ICR = UDP_ICR_WAKEUP | UDP_ICR_RXRSM | UDP_ICR_RXSUSP; - UDP->UDP_IER = UDP_IER_RXSUSP; - - //// Enable the Start Of Frame (SOF) interrupt if needed - //if (pUsb->pCallbacks->startOfFrame != 0) { - // - // UDP->UDP_IER = UDP_IER_SOFINT; - //} - - // Invoke the Reset callback - USBDCallbacks_Reset(); - - // Acknowledge end of bus reset interrupt - UDP->UDP_ICR = UDP_ICR_ENDBUSRES; - } - // Endpoint interrupts - else { - - while (status != 0) { - - // Check if endpoint has a pending interrupt - if ((status & (1 << eptnum)) != 0) { - - UDP_EndpointHandler(eptnum); - status &= ~(1 << eptnum); - - if (status != 0) { - - TRACE_INFO_WP("\n\r - "); - } - } - eptnum++; - } - } - - // Toggle LED back to its previous state - TRACE_DEBUG_WP("!"); - TRACE_INFO_WP("\n\r"); - if (deviceState >= USBD_STATE_POWERED) { - - // LED_Clear(USBD_LEDUSB); - } -} - -//------------------------------------------------------------------------------ -/// Configures an endpoint according to its Endpoint Descriptor. -/// \param pDescriptor Pointer to an Endpoint descriptor. -//------------------------------------------------------------------------------ -void USBD_ConfigureEndpoint(const USBEndpointDescriptor *pDescriptor) -{ - Endpoint *pEndpoint; - unsigned char bEndpoint; - unsigned char bType; - unsigned char bEndpointDir; - - // NULL descriptor -> Control endpoint 0 - if (pDescriptor == 0) { - - bEndpoint = 0; - pEndpoint = &(endpoints[bEndpoint]); - bType= USBEndpointDescriptor_CONTROL; - bEndpointDir = 0; - pEndpoint->size = CHIP_USB_ENDPOINTS_MAXPACKETSIZE(0); - } - else { - - bEndpoint = USBEndpointDescriptor_GetNumber(pDescriptor); - pEndpoint = &(endpoints[bEndpoint]); - bType = USBEndpointDescriptor_GetType(pDescriptor); - bEndpointDir = USBEndpointDescriptor_GetDirection(pDescriptor); - pEndpoint->size = USBEndpointDescriptor_GetMaxPacketSize(pDescriptor); - } - - // Abort the current transfer is the endpoint was configured and in - // Write or Read state - if ((pEndpoint->state == UDP_ENDPOINT_RECEIVING) - || (pEndpoint->state == UDP_ENDPOINT_SENDING) - || (pEndpoint->state == UDP_ENDPOINT_RECEIVINGM) - || (pEndpoint->state == UDP_ENDPOINT_SENDINGM)) { - - UDP_EndOfTransfer(bEndpoint, USBD_STATUS_RESET); - } - pEndpoint->state = UDP_ENDPOINT_IDLE; - - // Reset Endpoint Fifos - UDP->UDP_RST_EP |= (1 << bEndpoint); - UDP->UDP_RST_EP &= ~(1 << bEndpoint); - - // Configure endpoint - SET_CSR(bEndpoint, (unsigned int)UDP_CSR_EPEDS - | (bType << 8) | (bEndpointDir << 10)); - if (bType != USBEndpointDescriptor_CONTROL) { - - } - else { - - UDP->UDP_IER = (1 << bEndpoint); - } - - TRACE_INFO_WP("CfgEpt%d ", bEndpoint); -} - -//------------------------------------------------------------------------------ -/// Sends data through a USB endpoint. Sets up the transfer descriptor, -/// writes one or two data payloads (depending on the number of FIFO bank -/// for the endpoint) and then starts the actual transfer. The operation is -/// complete when all the data has been sent. -/// -/// *If the size of the buffer is greater than the size of the endpoint -/// (or twice the size if the endpoint has two FIFO banks), then the buffer -/// must be kept allocated until the transfer is finished*. This means that -/// it is not possible to declare it on the stack (i.e. as a local variable -/// of a function which returns after starting a transfer). -/// -/// \param bEndpoint Endpoint number. -/// \param pData Pointer to a buffer with the data to send. -/// \param dLength Size of the data buffer. -/// \param fCallback Optional callback function to invoke when the transfer is -/// complete. -/// \param pArgument Optional argument to the callback function. -/// \return USBD_STATUS_SUCCESS if the transfer has been started; -/// otherwise, the corresponding error status code. -//------------------------------------------------------------------------------ -char USBD_Write( unsigned char bEndpoint, - const void *pData, - unsigned int dLength, - TransferCallback fCallback, - void *pArgument ) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - Transfer *pTransfer = (Transfer*)&(pEndpoint->transfer); - - // Check that the endpoint is in Idle state - if (pEndpoint->state != UDP_ENDPOINT_IDLE) { - - return USBD_STATUS_LOCKED; - } - TRACE_DEBUG_WP("Write%d(%d) ", bEndpoint, dLength); - - // Setup the transfer descriptor - pTransfer->pData = (void *) pData; - pTransfer->remaining = dLength; - pTransfer->buffered = 0; - pTransfer->transferred = 0; - pTransfer->fCallback = fCallback; - pTransfer->pArgument = pArgument; - - // Send the first packet - pEndpoint->state = UDP_ENDPOINT_SENDING; - while((UDP->UDP_CSR[bEndpoint]&UDP_CSR_TXPKTRDY)==UDP_CSR_TXPKTRDY); - UDP_WritePayload(bEndpoint); - SET_CSR(bEndpoint, UDP_CSR_TXPKTRDY); - - // If double buffering is enabled and there is data remaining, - // prepare another packet - if ((CHIP_USB_ENDPOINTS_BANKS(bEndpoint) > 1) && (pTransfer->remaining > 0)) { - - UDP_WritePayload(bEndpoint); - } - - // Enable interrupt on endpoint - UDP->UDP_IER = 1 << bEndpoint; - - return USBD_STATUS_SUCCESS; -} - -//------------------------------------------------------------------------------ -/// Sends data frames through a USB endpoint. Sets up the transfer descriptor -/// list, writes one or two data payloads (depending on the number of FIFO bank -/// for the endpoint) and then starts the actual transfer. The operation is -/// complete when all the data has been sent. -/// -/// *If the size of the frame is greater than the size of the endpoint -/// (or twice the size if the endpoint has two FIFO banks), then the buffer -/// must be kept allocated until the frame is finished*. This means that -/// it is not possible to declare it on the stack (i.e. as a local variable -/// of a function which returns after starting a transfer). -/// -/// \param bEndpoint Endpoint number. -/// \param pMbl Pointer to a frame (USBDTransferBuffer) list that describes -/// the buffer list to send. -/// \param wListSize Size of the frame list. -/// \param bCircList Circle the list. -/// \param wStartNdx For circled list only, the first buffer index to transfer. -/// \param fCallback Optional callback function to invoke when the transfer is -/// complete. -/// \param pArgument Optional argument to the callback function. -/// \return USBD_STATUS_SUCCESS if the transfer has been started; -/// otherwise, the corresponding error status code. -/// \see USBDTransferBuffer, MblTransferCallback, USBD_MblReuse -//------------------------------------------------------------------------------ -char USBD_MblWrite( unsigned char bEndpoint, - void *pMbl, - unsigned short wListSize, - unsigned char bCircList, - unsigned short wStartNdx, - MblTransferCallback fCallback, - void *pArgument ) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - MblTransfer *pTransfer = (MblTransfer*)&(pEndpoint->transfer); - unsigned short i; - - // EP0 is not suitable for Mbl - if (bEndpoint == 0) { - - return USBD_STATUS_INVALID_PARAMETER; - } - - // Check that the endpoint is in Idle state - if (pEndpoint->state != UDP_ENDPOINT_IDLE) { - - return USBD_STATUS_LOCKED; - } - pEndpoint->state = UDP_ENDPOINT_SENDINGM; - - TRACE_DEBUG_WP("WriteM%d(0x%x,%d) ", bEndpoint, pMbl, wListSize); - - // Start from first if not circled list - if (!bCircList) wStartNdx = 0; - - // Setup the transfer descriptor - pTransfer->pMbl = (USBDTransferBuffer*)pMbl; - pTransfer->listSize = wListSize; - pTransfer->fCallback = fCallback; - pTransfer->pArgument = pArgument; - pTransfer->currBuffer = wStartNdx; - pTransfer->freedBuffer = 0; - pTransfer->pLastLoaded = &(((USBDTransferBuffer*)pMbl)[wStartNdx]); - pTransfer->circList = bCircList; - pTransfer->allUsed = 0; - - // Clear all buffer - for (i = 0; i < wListSize; i ++) { - - pTransfer->pMbl[i].transferred = 0; - pTransfer->pMbl[i].buffered = 0; - pTransfer->pMbl[i].remaining = pTransfer->pMbl[i].size; - } - - // Send the first packet - while((UDP->UDP_CSR[bEndpoint]&UDP_CSR_TXPKTRDY)==UDP_CSR_TXPKTRDY); - UDP_MblWriteFifo(bEndpoint); - SET_CSR(bEndpoint, UDP_CSR_TXPKTRDY); - - // If double buffering is enabled and there is data remaining, - // prepare another packet - if ((CHIP_USB_ENDPOINTS_BANKS(bEndpoint) > 1) - && (pTransfer->pMbl[pTransfer->currBuffer].remaining > 0)) { - - UDP_MblWriteFifo(bEndpoint); - } - - // Enable interrupt on endpoint - UDP->UDP_IER = 1 << bEndpoint; - - return USBD_STATUS_SUCCESS; -} - -//------------------------------------------------------------------------------ -/// Reads incoming data on an USB endpoint This methods sets the transfer -/// descriptor and activate the endpoint interrupt. The actual transfer is -/// then carried out by the endpoint interrupt handler. The Read operation -/// finishes either when the buffer is full, or a short packet (inferior to -/// endpoint maximum size) is received. -/// -/// *The buffer must be kept allocated until the transfer is finished*. -/// \param bEndpoint Endpoint number. -/// \param pData Pointer to a data buffer. -/// \param dLength Size of the data buffer in bytes. -/// \param fCallback Optional end-of-transfer callback function. -/// \param pArgument Optional argument to the callback function. -/// \return USBD_STATUS_SUCCESS if the read operation has been started; -/// otherwise, the corresponding error code. -//------------------------------------------------------------------------------ -char USBD_Read(unsigned char bEndpoint, - void *pData, - unsigned int dLength, - TransferCallback fCallback, - void *pArgument) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - Transfer *pTransfer = (Transfer*)&(pEndpoint->transfer); - - // Return if the endpoint is not in IDLE state - if (pEndpoint->state != UDP_ENDPOINT_IDLE) { - - return USBD_STATUS_LOCKED; - } - - // Endpoint enters Receiving state - pEndpoint->state = UDP_ENDPOINT_RECEIVING; - TRACE_DEBUG_WP("Read%d(%d) ", bEndpoint, dLength); - - // Set the transfer descriptor - pTransfer->pData = pData; - pTransfer->remaining = dLength; - pTransfer->buffered = 0; - pTransfer->transferred = 0; - pTransfer->fCallback = fCallback; - pTransfer->pArgument = pArgument; - - // Enable interrupt on endpoint - UDP->UDP_IER = 1 << bEndpoint; - - return USBD_STATUS_SUCCESS; -} - -//------------------------------------------------------------------------------ -/// Reuse first used/released buffer with new buffer address and size to be used -/// in transfer again. Only valid when frame list is ringed. Can be used for -/// both read & write. -/// \param bEndpoint Endpoint number. -/// \param pNewBuffer Pointer to new buffer with data to send (0 to keep last). -/// \param wNewSize Size of the data buffer -//------------------------------------------------------------------------------ -char USBD_MblReuse( unsigned char bEndpoint, - unsigned char *pNewBuffer, - unsigned short wNewSize ) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - MblTransfer *pTransfer = (MblTransfer*)&(pEndpoint->transfer); - USBDTransferBuffer *pBi = &(pTransfer->pMbl[pTransfer->freedBuffer]); - - TRACE_DEBUG_WP("MblReuse(%d), st%x, circ%d\n\r", - bEndpoint, pEndpoint->state, pTransfer->circList); - - // Only for Multi-buffer-circle list - if (bEndpoint != 0 - && (pEndpoint->state == UDP_ENDPOINT_RECEIVINGM - || pEndpoint->state == UDP_ENDPOINT_SENDINGM) - && pTransfer->circList) { - } - else { - - return USBD_STATUS_WRONG_STATE; - } - - // Check if there is freed buffer - if (pTransfer->freedBuffer == pTransfer->currBuffer - && !pTransfer->allUsed) { - - return USBD_STATUS_LOCKED; - } - - // Update transfer information - if ((++ pTransfer->freedBuffer) == pTransfer->listSize) - pTransfer->freedBuffer = 0; - if (pNewBuffer) { - pBi->pBuffer = pNewBuffer; - pBi->size = wNewSize; - } - pBi->buffered = 0; - pBi->transferred = 0; - pBi->remaining = pBi->size; - - // At least one buffer is not processed - pTransfer->allUsed = 0; - return USBD_STATUS_SUCCESS; -} - -//------------------------------------------------------------------------------ -/// Sets the HALT feature on the given endpoint (if not already in this state). -/// \param bEndpoint Endpoint number. -//------------------------------------------------------------------------------ -void USBD_Halt(unsigned char bEndpoint) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - - // Check that endpoint is enabled and not already in Halt state - if ((pEndpoint->state != UDP_ENDPOINT_DISABLED) - && (pEndpoint->state != UDP_ENDPOINT_HALTED)) { - - TRACE_DEBUG_WP("Halt%d ", bEndpoint); - - // Abort the current transfer if necessary - UDP_EndOfTransfer(bEndpoint, USBD_STATUS_ABORTED); - - // Put endpoint into Halt state - SET_CSR(bEndpoint, UDP_CSR_FORCESTALL); - pEndpoint->state = UDP_ENDPOINT_HALTED; - - // Enable the endpoint interrupt - UDP->UDP_IER = 1 << bEndpoint; - } -} - -//------------------------------------------------------------------------------ -/// Clears the Halt feature on the given endpoint. -/// \param bEndpoint Index of endpoint -//------------------------------------------------------------------------------ -void USBD_Unhalt(unsigned char bEndpoint) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - - // Check if the endpoint is enabled - if (pEndpoint->state != UDP_ENDPOINT_DISABLED) { - - TRACE_DEBUG_WP("Unhalt%d ", bEndpoint); - - // Return endpoint to Idle state - pEndpoint->state = UDP_ENDPOINT_IDLE; - - // Clear FORCESTALL flag - CLEAR_CSR(bEndpoint, UDP_CSR_FORCESTALL); - - // Reset Endpoint Fifos, beware this is a 2 steps operation - UDP->UDP_RST_EP |= 1 << bEndpoint; - UDP->UDP_RST_EP &= ~(1 << bEndpoint); - } -} - -//------------------------------------------------------------------------------ -/// Returns the current Halt status of an endpoint. -/// \param bEndpoint Index of endpoint -/// \return 1 if the endpoint is currently halted; otherwise 0 -//------------------------------------------------------------------------------ -unsigned char USBD_IsHalted(unsigned char bEndpoint) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - unsigned char status = 0; - - if (pEndpoint->state == UDP_ENDPOINT_HALTED) { - - status = 1; - } - return( status ); -} - -//------------------------------------------------------------------------------ -/// Indicates if the device is running in high or full-speed. Always returns 0 -/// since UDP does not support high-speed mode. -//------------------------------------------------------------------------------ -unsigned char USBD_IsHighSpeed(void) -{ - return 0; -} - -//------------------------------------------------------------------------------ -/// Causes the given endpoint to acknowledge the next packet it receives -/// with a STALL handshake. -/// \param bEndpoint Endpoint number. -/// \return USBD_STATUS_SUCCESS or USBD_STATUS_LOCKED. -//------------------------------------------------------------------------------ -unsigned char USBD_Stall(unsigned char bEndpoint) - -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - - // Check that endpoint is in Idle state - if (pEndpoint->state != UDP_ENDPOINT_IDLE) { - - TRACE_WARNING("UDP_Stall: Endpoint%d locked\n\r", bEndpoint); - return USBD_STATUS_LOCKED; - } - - TRACE_DEBUG_WP("Stall%d ", bEndpoint); - SET_CSR(bEndpoint, UDP_CSR_FORCESTALL); - - return USBD_STATUS_SUCCESS; -} - -//------------------------------------------------------------------------------ -/// Starts a remote wake-up procedure. -//------------------------------------------------------------------------------ -void USBD_RemoteWakeUp(void) -{ - // Device is NOT suspended - if (deviceState != USBD_STATE_SUSPENDED) { - - TRACE_WARNING("USBD_RemoteWakeUp: Device is not suspended\n\r"); - return; - } - - - UDP_EnablePeripheralClock(); - UDP_EnableUsbClock(); - UDP_EnableTransceiver(); - - TRACE_INFO_WP("RWUp "); - - // Activates a remote wakeup (edge on ESR), then clear ESR - UDP->UDP_GLB_STAT |= UDP_GLB_STAT_ESR; - UDP->UDP_GLB_STAT &= ~UDP_GLB_STAT_ESR; -} - -//------------------------------------------------------------------------------ -/// Sets the device address to the given value. -/// \param address New device address. -//------------------------------------------------------------------------------ -void USBD_SetAddress(unsigned char address) -{ - TRACE_INFO_WP("SetAddr(%d) ", address); - - // Set address - UDP->UDP_FADDR = UDP_FADDR_FEN | (address & UDP_FADDR_FADD); - - // If the address is 0, the device returns to the Default state - if (address == 0) { - - UDP->UDP_GLB_STAT = 0; - deviceState = USBD_STATE_DEFAULT; - } - // If the address is non-zero, the device enters the Address state - else { - - UDP->UDP_GLB_STAT = UDP_GLB_STAT_FADDEN; - deviceState = USBD_STATE_ADDRESS; - } -} - -//------------------------------------------------------------------------------ -/// Sets the current device configuration. -/// \param cfgnum - Configuration number to set. -//------------------------------------------------------------------------------ -void USBD_SetConfiguration(unsigned char cfgnum) -{ - TRACE_INFO_WP("SetCfg(%d) ", cfgnum); - - // If the configuration number if non-zero, the device enters the - // Configured state - if (cfgnum != 0) { - - // Enter Configured state - deviceState = USBD_STATE_CONFIGURED; - UDP->UDP_GLB_STAT |= UDP_GLB_STAT_CONFG; - } - // If the configuration number is zero, the device goes back to the Address - // state - else { - - deviceState = USBD_STATE_ADDRESS; - UDP->UDP_GLB_STAT = UDP_FADDR_FEN; - - // Abort all transfers - UDP_DisableEndpoints(); - } -} - -//------------------------------------------------------------------------------ -/// Connects the pull-up on the D+ line of the USB. -//------------------------------------------------------------------------------ -void USBD_Connect(void) -{ - unsigned char dis = UDP_EnablePeripheralClock(); - - TRACE_DEBUG("Conn "); - UDP->UDP_TXVC |= UDP_TXVC_PUON; - - if (dis) UDP_DisablePeripheralClock(); -} - -//------------------------------------------------------------------------------ -/// Disconnects the pull-up from the D+ line of the USB. -//------------------------------------------------------------------------------ -void USBD_Disconnect(void) -{ - unsigned char dis = UDP_EnablePeripheralClock(); - - TRACE_DEBUG("Disc "); - UDP->UDP_TXVC &= ~UDP_TXVC_PUON; - - if (dis) UDP_DisablePeripheralClock(); - - // Device returns to the Powered state - if (deviceState > USBD_STATE_POWERED) { - - deviceState = USBD_STATE_POWERED; - } - - if (previousDeviceState > USBD_STATE_POWERED) { - - previousDeviceState = USBD_STATE_POWERED; - } -} - -//------------------------------------------------------------------------------ -/// Initializes the USB driver. -//------------------------------------------------------------------------------ -void USBD_Init(void) -{ - TRACE_INFO_WP("USBD_Init\n\r"); - // Reset endpoint structures - UDP_ResetEndpoints(); - - // Must before TXVC access! - UDP_EnablePeripheralClock(); - - // Configure the pull-up on D+ and disconnect it - UDP->UDP_TXVC &= ~UDP_TXVC_PUON; - - // Device is in the Attached state - deviceState = USBD_STATE_SUSPENDED; - previousDeviceState = USBD_STATE_POWERED; - UDP_EnableUsbClock(); - - UDP->UDP_IDR = 0xFE; - - UDP->UDP_IER = UDP_IER_WAKEUP; - - // Configure interrupts - USBDCallbacks_Initialized(); -} - -//------------------------------------------------------------------------------ -/// Configure USB Speed, should be invoked before USB attachment. -/// \param forceFS Force to use FS mode. -//------------------------------------------------------------------------------ -void USBD_ConfigureSpeed(unsigned char forceFS) -{ -} - -//------------------------------------------------------------------------------ -/// Returns the current state of the USB device. -/// \return Device current state. -//------------------------------------------------------------------------------ -unsigned char USBD_GetState(void) -{ - return deviceState; -} - diff --git a/radio/bootloader/usb/device/massstorage/MSD.h b/radio/bootloader/usb/device/massstorage/MSD.h deleted file mode 100644 index 23a934d35..000000000 --- a/radio/bootloader/usb/device/massstorage/MSD.h +++ /dev/null @@ -1,233 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Mass Storage class definitions. -/// -/// See -/// - -/// USB Mass Storage Class Spec. Overview -/// - -/// USB Mass Storage Class Bulk-Only Transport -/// -/// !Usage -/// -/// -# Uses "MSD Requests" to check incoming requests from USB Host. -/// -# Uses "MSD Subclass Codes" and "MSD Protocol Codes" to fill %device -/// interface descriptors for a MSD %device. -/// -# Handle the incoming Bulk data with "MSD CBW Definitions" and MSCbw -/// structure. -/// -# Prepare the outgoing Bulk data with "MSD CSW Definitions" and MSCsw -/// structure. -//------------------------------------------------------------------------------ - -#ifndef MSD_H -#define MSD_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Requests" -/// This page lists MSD-specific requests ( Actually for Bulk-only protocol ). -/// -/// !Requests -/// - MSD_BULK_ONLY_RESET -/// - MSD_GET_MAX_LUN - -/// Reset the mass storage %device and its associated interface. -#define MSD_BULK_ONLY_RESET 0xFF -/// Return the maximum LUN number supported by the %device. -#define MSD_GET_MAX_LUN 0xFE -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Subclass Codes" -/// This page lists the Subclass Codes for bInterfaceSubClass field. -/// (Table 2.1, USB Mass Storage Class Spec. Overview) -/// -/// !SubClasses -/// - MSD_SUBCLASS_RBC -/// - MSD_SUBCLASS_SFF_MCC -/// - MSD_SUBCLASS_QIC -/// - MSD_SUBCLASS_UFI -/// - MSD_SUBCLASS_SFF -/// - MSD_SUBCLASS_SCSI - -/// Reduced Block Commands (RBC) T10 -#define MSD_SUBCLASS_RBC 0x01 -/// C/DVD devices -#define MSD_SUBCLASS_SFF_MCC 0x02 -/// Tape device -#define MSD_SUBCLASS_QIC 0x03 -/// Floppy disk drive (FDD) device -#define MSD_SUBCLASS_UFI 0x04 -/// Floppy disk drive (FDD) device -#define MSD_SUBCLASS_SFF 0x05 -/// SCSI transparent command set -#define MSD_SUBCLASS_SCSI 0x06 -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -/// \page "MSD Protocol Codes" -/// This page lists the Transport Protocol codes for MSD. -/// (Table 3.1, USB Mass Storage Class Spec. Overview) -/// -/// !Protocols -/// - MSD_PROTOCOL_CBI_COMPLETION -/// - MSD_PROTOCOL_CBI -/// - MSD_PROTOCOL_BULK_ONLY - -/// Control/Bulk/Interrupt (CBI) Transport (with command complete interrupt) -#define MSD_PROTOCOL_CBI_COMPLETION 0x00 -/// Control/Bulk/Interrupt (CBI) Transport (no command complete interrupt) -#define MSD_PROTOCOL_CBI 0x01 -/// Bulk-Only Transport -#define MSD_PROTOCOL_BULK_ONLY 0x50 -//------------------------------------------------------------------------------ - -/// Test unit control: -#define CTRL_NOT_READY 0x00 -#define CTRL_GOOD 0x01 -#define CTRL_BUSY 0x02 - -//------------------------------------------------------------------------------ -/// \page "MSD CBW Definitions" -/// This page lists the Command Block Wrapper (CBW) definitions. -/// -/// !Constants -/// - MSD_CBW_SIZE -/// - MSD_CBW_SIGNATURE -/// -/// !Fields -/// - MSD_CBW_DEVICE_TO_HOST - -/// Command Block Wrapper Size -#define MSD_CBW_SIZE 31 -/// 'USBC' 0x43425355 -#define MSD_CBW_SIGNATURE 0x43425355 - -/// CBW bmCBWFlags field -#define MSD_CBW_DEVICE_TO_HOST (1 << 7) -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD CSW Definitions" -/// This page lists the Command Status Wrapper (CSW) definitions. -/// -/// !Constants -/// - MSD_CSW_SIZE -/// - MSD_CSW_SIGNATURE -/// -/// !Command Block Status Values -/// (Table 5.3 , USB Mass Storage Class Bulk-Only Transport) -/// - MSD_CSW_COMMAND_PASSED -/// - MSD_CSW_COMMAND_FAILED -/// - MSD_CSW_PHASE_ERROR - -/// Command Status Wrapper Size -#define MSD_CSW_SIZE 13 -/// 'USBS' 0x53425355 -#define MSD_CSW_SIGNATURE 0x53425355 - -/// Command Passed (good status) -#define MSD_CSW_COMMAND_PASSED 0 -/// Command Failed -#define MSD_CSW_COMMAND_FAILED 1 -/// Phase Error -#define MSD_CSW_PHASE_ERROR 2 -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// Structures -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Command Block Wrapper (CBW), -/// See Table 5.1, USB Mass Storage Class Bulk-Only Transport. -/// -/// The CBW shall start on a packet boundary and shall end as a -/// short packet with exactly 31 (1Fh) bytes transferred. -//------------------------------------------------------------------------------ -typedef struct { - - /// 'USBC' 0x43425355 (little endian) - unsigned int dCBWSignature; - /// Must be the same as dCSWTag - unsigned int dCBWTag; - /// Number of bytes transfer - unsigned int dCBWDataTransferLength; - /// Indicates the directin of the transfer: - /// 0x80=IN=device-to-host, - /// 0x00=OUT=host-to-device - unsigned char bmCBWFlags; - /// bits 0->3: bCBWLUN - unsigned char bCBWLUN :4, - bReserved1:4; /// reserved - /// bits 0->4: bCBWCBLength - unsigned char bCBWCBLength:5, - bReserved2 :3; /// reserved - /// Command block - unsigned char pCommand[16]; - -} MSCbw; - -//------------------------------------------------------------------------------ -/// Command Status Wrapper (CSW), -/// See Table 5.2, USB Mass Storage Class Bulk-Only Transport. -//------------------------------------------------------------------------------ -typedef struct -{ - /// 'USBS' 0x53425355 (little endian) - unsigned int dCSWSignature; - /// Must be the same as dCBWTag - unsigned int dCSWTag; - /// For Data-Out the device shall report in the dCSWDataResidue the - /// difference between the amount of data expected as stated in the - /// dCBWDataTransferLength, and the actual amount of data processed by - /// the device. For Data-In the device shall report in the dCSWDataResidue - /// the difference between the amount of data expected as stated in the - /// dCBWDataTransferLength and the actual amount of relevant data sent by - /// the device. The dCSWDataResidue shall not exceed the value sent in the - /// dCBWDataTransferLength. - unsigned int dCSWDataResidue; - /// Indicates the success or failure of the command. - unsigned char bCSWStatus; - -} MSCsw; - -#endif //#ifndef MSD_H - diff --git a/radio/bootloader/usb/device/massstorage/MSDDStateMachine.c b/radio/bootloader/usb/device/massstorage/MSDDStateMachine.c deleted file mode 100644 index 849440730..000000000 --- a/radio/bootloader/usb/device/massstorage/MSDDStateMachine.c +++ /dev/null @@ -1,609 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//----------------------------------------------------------------------------- -// Includes -//----------------------------------------------------------------------------- - -#include "SBCMethods.h" -#include "MSDDStateMachine.h" - -//----------------------------------------------------------------------------- -// Internal functions -//----------------------------------------------------------------------------- -//----------------------------------------------------------------------------- -/// Returns the expected transfer length and direction (IN, OUT or don't care) -/// from the host point-of-view. -/// \param cbw Pointer to the CBW to examinate -/// \param pLength Expected length of command -/// \param pType Expected direction of command -//----------------------------------------------------------------------------- -static void MSDD_GetCommandInformation(MSCbw *cbw, - unsigned int *length, - unsigned char *type) -{ - // Expected host transfer direction and length - (*length) = cbw->dCBWDataTransferLength; - - if (*length == 0) { - - (*type) = MSDD_NO_TRANSFER; - } - else if ((cbw->bmCBWFlags & MSD_CBW_DEVICE_TO_HOST) != 0) { - - (*type) = MSDD_DEVICE_TO_HOST; - } - else { - - (*type) = MSDD_HOST_TO_DEVICE; - } -} - -//----------------------------------------------------------------------------- -/// Pre-processes a command by checking the differences between the host and -/// device expectations in term of transfer type and length. -/// Once one of the thirteen cases is identified, the actions to do during the -/// post-processing phase are stored in the dCase variable of the command -/// state. -/// \param pMsdDriver Pointer to a MSDDriver instance -/// \return 1 if the command is supported, false otherwise -//----------------------------------------------------------------------------- -static unsigned char MSDD_PreProcessCommand(MSDDriver *pMsdDriver) -{ - unsigned int hostLength = 0; - unsigned int deviceLength = 0; - unsigned char hostType; - unsigned char deviceType; - unsigned char isCommandSupported; - MSDCommandState *commandState = &(pMsdDriver->commandState); - MSCsw *csw = &(commandState->csw); - MSCbw *cbw = &(commandState->cbw); - MSDLun *lun = &(pMsdDriver->luns[(unsigned char) cbw->bCBWLUN]); - - // Get information about the command - // Host-side - MSDD_GetCommandInformation(cbw, &hostLength, &hostType); - - // Device-side - isCommandSupported = SBC_GetCommandInformation(cbw->pCommand, - &deviceLength, - &deviceType, - lun); - - // Initialize data residue and result status - csw->dCSWDataResidue = 0; - csw->bCSWStatus = MSD_CSW_COMMAND_PASSED; - - // Check if the command is supported - if (isCommandSupported) { - - // Identify the command case - if(hostType == MSDD_NO_TRANSFER) { - - // Case 1 (Hn = Dn) - if(deviceType == MSDD_NO_TRANSFER) { - - //TRACE_WARNING("Case 1\n\r"); - commandState->postprocess = 0; - commandState->length = 0; - } - else if(deviceType == MSDD_DEVICE_TO_HOST) { - - // Case 2 (Hn < Di) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 2\n\r"); - commandState->postprocess = MSDD_CASE_PHASE_ERROR; - commandState->length = 0; - } - else { //if(deviceType == MSDD_HOST_TO_DEVICE) { - - // Case 3 (Hn < Do) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 3\n\r"); - commandState->postprocess = MSDD_CASE_PHASE_ERROR; - commandState->length = 0; - } - } - - // Case 4 (Hi > Dn) - else if(hostType == MSDD_DEVICE_TO_HOST) { - - if(deviceType == MSDD_NO_TRANSFER) { - - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 4\n\r"); - commandState->postprocess = MSDD_CASE_STALL_IN; - commandState->length = 0; - csw->dCSWDataResidue = hostLength; - } - else if(deviceType == MSDD_DEVICE_TO_HOST) { - - TRACE_ERROR("cmd=0x%0x h=%d d=%d", cbw->pCommand[0], hostLength, deviceLength); - - if(hostLength > deviceLength) { - - // Case 5 (Hi > Di) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 5\n\r"); - commandState->postprocess = MSDD_CASE_STALL_IN; - commandState->length = deviceLength; - csw->dCSWDataResidue = hostLength - deviceLength; - } - else if(hostLength == deviceLength) { - - // Case 6 (Hi = Di) - commandState->postprocess = 0; - commandState->length = deviceLength; - } - else { //if(hostLength < deviceLength) { - - // Case 7 (Hi < Di) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 7\n\r"); - commandState->postprocess = MSDD_CASE_PHASE_ERROR; - commandState->length = hostLength; - } - } - else { //if(deviceType == MSDD_HOST_TO_DEVICE) { - - // Case 8 (Hi <> Do) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 8\n\r"); - commandState->postprocess = - MSDD_CASE_STALL_IN | MSDD_CASE_PHASE_ERROR; - commandState->length = 0; - } - } - else if(hostType == MSDD_HOST_TO_DEVICE) { - - if(deviceType == MSDD_NO_TRANSFER) { - - // Case 9 (Ho > Dn) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 9\n\r"); - commandState->postprocess = MSDD_CASE_STALL_OUT; - commandState->length = 0; - csw->dCSWDataResidue = hostLength; - } - else if(deviceType == MSDD_DEVICE_TO_HOST) { - - // Case 10 (Ho <> Di) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 10\n\r"); - commandState->postprocess = - MSDD_CASE_STALL_OUT | MSDD_CASE_PHASE_ERROR; - commandState->length = 0; - } - else { //if(deviceType == MSDD_HOST_TO_DEVICE) { - - if(hostLength > deviceLength) { - - // Case 11 (Ho > Do) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 11\n\r"); - commandState->postprocess = MSDD_CASE_STALL_OUT; -// commandState->length = deviceLength; -// csw->dCSWDataResidue = hostLength - deviceLength; - commandState->length = 0; - csw->dCSWDataResidue = deviceLength; - } - else if(hostLength == deviceLength) { - - // Case 12 (Ho = Do) - //TRACE_WARNING( - // "MSDD_PreProcessCommand: Case 12\n\r"); - commandState->postprocess = 0; - commandState->length = deviceLength; - } - else { //if(hostLength < deviceLength) { - - // Case 13 (Ho < Do) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 13\n\r"); - commandState->postprocess = MSDD_CASE_PHASE_ERROR; - commandState->length = hostLength; - } - } - } - } - - return isCommandSupported; -} - -//----------------------------------------------------------------------------- -/// Post-processes a command given the case identified during the -/// pre-processing step. -/// Depending on the case, one of the following actions can be done: -/// - Bulk IN endpoint is stalled -/// - Bulk OUT endpoint is stalled -/// - CSW status set to phase error -/// \param pMsdDriver Pointer to a MSDDriver instance -/// \return If the device is halted -//----------------------------------------------------------------------------- -static unsigned char MSDD_PostProcessCommand(MSDDriver *pMsdDriver) -{ - MSDCommandState *commandState = &(pMsdDriver->commandState); - MSCsw *csw = &(commandState->csw); - unsigned char haltStatus = 0; - - // STALL Bulk IN endpoint ? - if ((commandState->postprocess & MSDD_CASE_STALL_IN) != 0) { - - TRACE_INFO_WP("StallIn "); - MSDD_Halt(MSDD_CASE_STALL_IN); - haltStatus = 1; - } - - // STALL Bulk OUT endpoint ? - if ((commandState->postprocess & MSDD_CASE_STALL_OUT) != 0) { - - TRACE_INFO_WP("StallOut "); - MSDD_Halt(MSDD_CASE_STALL_OUT); - haltStatus = 1; - } - - // Set CSW status code to phase error ? - if ((commandState->postprocess & MSDD_CASE_PHASE_ERROR) != 0) { - - TRACE_INFO_WP("PhaseErr "); - csw->bCSWStatus = MSD_CSW_PHASE_ERROR; - } - - return haltStatus; -} - -//----------------------------------------------------------------------------- -/// Processes the latest command received by the %device. -/// \param pMsdDriver Pointer to a MSDDriver instance -/// \return 1 if the command has been completed, false otherwise. -//----------------------------------------------------------------------------- -static unsigned char MSDD_ProcessCommand(MSDDriver * pMsdDriver) -{ - unsigned char status; - MSDCommandState *commandState = &(pMsdDriver->commandState); - MSCbw *cbw = &(commandState->cbw); - MSCsw *csw = &(commandState->csw); - MSDLun *lun = &(pMsdDriver->luns[(unsigned char) cbw->bCBWLUN]); - unsigned char isCommandComplete = 0; - - // Check if LUN is valid - if (cbw->bCBWLUN > pMsdDriver->maxLun) { - - TRACE_WARNING( - "MSDD_ProcessCommand: LUN %d not exist\n\r", cbw->bCBWLUN); - status = MSDD_STATUS_ERROR; - } - else { - - // Process command - if (pMsdDriver->maxLun > 0) { - - TRACE_INFO_WP("LUN%d ", cbw->bCBWLUN); - } - - status = SBC_ProcessCommand(lun, commandState); - } - - // Check command result code - if (status == MSDD_STATUS_PARAMETER) { - - TRACE_WARNING( - "MSDD_ProcessCommand: Unknown cmd 0x%02X\n\r", - cbw->pCommand[0]); - - // Update sense data - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_ILLEGAL_REQUEST, - SBC_ASC_INVALID_FIELD_IN_CDB, - 0); - - // Result codes - csw->bCSWStatus = MSD_CSW_COMMAND_FAILED; - isCommandComplete = 1; - - // stall the request, IN or OUT - if (((cbw->bmCBWFlags & MSD_CBW_DEVICE_TO_HOST) == 0) - && (cbw->dCBWDataTransferLength > 0)) { - - // Stall the OUT endpoint : host to device - // MSDD_Halt(MSDD_CASE_STALL_OUT); - commandState->postprocess = MSDD_CASE_STALL_OUT; - TRACE_INFO_WP("StaOUT "); - } - else { - - // Stall the IN endpoint : device to host - // MSDD_Halt(MSDD_CASE_STALL_IN); - commandState->postprocess = MSDD_CASE_STALL_IN; - TRACE_INFO_WP("StaIN "); - } - } - else if (status == MSDD_STATUS_ERROR) { - - TRACE_WARNING("MSD_ProcessCommand: Cmd %x fail\n\r", - ((SBCCommand*)commandState->cbw.pCommand)->bOperationCode); - - // Update sense data - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_MEDIUM_ERROR, - SBC_ASC_INVALID_FIELD_IN_CDB, - 0); - - // Result codes - csw->bCSWStatus = MSD_CSW_COMMAND_FAILED; - isCommandComplete = 1; - } - else if (status == MSDD_STATUS_RW) { - - csw->bCSWStatus = MSD_CSW_COMMAND_FAILED; - isCommandComplete = 1; - } - else { - - // Update sense data - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_NO_SENSE, - 0, - 0); - - // Is command complete ? - if (status == MSDD_STATUS_SUCCESS) { - - isCommandComplete = 1; - } - } - - // Check if command has been completed - if (isCommandComplete) { - - TRACE_INFO_WP("Cplt "); - - // Adjust data residue - if (commandState->length != 0) { - - csw->dCSWDataResidue += commandState->length; - - // STALL the endpoint waiting for data - if ((cbw->bmCBWFlags & MSD_CBW_DEVICE_TO_HOST) == 0) { - - // Stall the OUT endpoint : host to device - // MSDD_Halt(MSDD_CASE_STALL_OUT); - commandState->postprocess = MSDD_CASE_STALL_OUT; - TRACE_INFO_WP("StaOUT "); - } - else { - - // Stall the IN endpoint : device to host - // MSDD_Halt(MSDD_CASE_STALL_IN); - commandState->postprocess = MSDD_CASE_STALL_IN; - TRACE_INFO_WP("StaIN "); - } - } - - // Reset command state - commandState->state = 0; - } - - return isCommandComplete; -} - -//----------------------------------------------------------------------------- -/// State machine for the MSD %device driver -/// \param pMsdDriver Pointer to a MSDDriver instance -//----------------------------------------------------------------------------- -void MSDD_StateMachine(MSDDriver * pMsdDriver) -{ - MSDCommandState *commandState = &(pMsdDriver->commandState); - MSCbw *cbw = &(commandState->cbw); - MSCsw *csw = &(commandState->csw); - MSDTransfer *transfer = &(commandState->transfer); - unsigned char status; - - // Identify current driver state - switch (pMsdDriver->state) { - //---------------------- - case MSDD_STATE_READ_CBW: - //---------------------- - // Start the CBW read operation - transfer->semaphore = 0; - status = MSDD_Read(cbw, - MSD_CBW_SIZE, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - - // Check operation result code - if (status == USBD_STATUS_SUCCESS) { - - // If the command was successful, wait for transfer - pMsdDriver->state = MSDD_STATE_WAIT_CBW; - } - break; - - //---------------------- - case MSDD_STATE_WAIT_CBW: - //---------------------- - // Check transfer semaphore - if (transfer->semaphore > 0) { - - // Take semaphore and terminate transfer - transfer->semaphore--; - - // Check if transfer was successful - if (transfer->status == USBD_STATUS_SUCCESS) { - - TRACE_INFO_WP("------------------------------\n\r"); - - // Process received command - pMsdDriver->state = MSDD_STATE_PROCESS_CBW; - } - else if (transfer->status == USBD_STATUS_RESET) { - - TRACE_INFO("MSDD_StateMachine: EP resetted\n\r"); - pMsdDriver->state = MSDD_STATE_READ_CBW; - } - else { - - TRACE_WARNING( - "MSDD_StateMachine: Failed to read CBW\n\r"); - pMsdDriver->state = MSDD_STATE_READ_CBW; - } - } - break; - - //------------------------- - case MSDD_STATE_PROCESS_CBW: - //------------------------- - // Check if this is a new command - if (commandState->state == 0) { - - // Copy the CBW tag - csw->dCSWTag = cbw->dCBWTag; - - // Check that the CBW is 31 bytes long - if ((transfer->transferred != MSD_CBW_SIZE) || - (transfer->remaining != 0)) { - - TRACE_WARNING( - "MSDD_StateMachine: Invalid CBW (len %d)\n\r", - (int)transfer->transferred); - - // Wait for a reset recovery - pMsdDriver->waitResetRecovery = 1; - - // Halt the Bulk-IN and Bulk-OUT pipes - MSDD_Halt(MSDD_CASE_STALL_OUT | MSDD_CASE_STALL_IN); - - csw->bCSWStatus = MSD_CSW_COMMAND_FAILED; - pMsdDriver->state = MSDD_STATE_READ_CBW; - - } - // Check the CBW Signature - else if (cbw->dCBWSignature != MSD_CBW_SIGNATURE) { - - TRACE_WARNING( - "MSD_BOTStateMachine: Invalid CBW (Bad signature)\n\r"); - - // Wait for a reset recovery - pMsdDriver->waitResetRecovery = 1; - - // Halt the Bulk-IN and Bulk-OUT pipes - MSDD_Halt(MSDD_CASE_STALL_OUT | MSDD_CASE_STALL_IN); - - csw->bCSWStatus = MSD_CSW_COMMAND_FAILED; - pMsdDriver->state = MSDD_STATE_READ_CBW; - } - else { - - // Pre-process command - MSDD_PreProcessCommand(pMsdDriver); - } - } - - // Process command - if (csw->bCSWStatus == MSDD_STATUS_SUCCESS) { - - if (MSDD_ProcessCommand(pMsdDriver)) { - - // Post-process command if it is finished - if (MSDD_PostProcessCommand(pMsdDriver)) { - - TRACE_INFO_WP("WaitHALT "); - pMsdDriver->state = MSDD_STATE_WAIT_HALT; - } - else { - - pMsdDriver->state = MSDD_STATE_SEND_CSW; - } - } - TRACE_INFO_WP("\n\r"); - } - - break; - - //---------------------- - case MSDD_STATE_SEND_CSW: - //---------------------- - // Set signature - csw->dCSWSignature = MSD_CSW_SIGNATURE; - - // Start the CSW write operation - status = MSDD_Write(csw, - MSD_CSW_SIZE, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - - // Check operation result code - if (status == USBD_STATUS_SUCCESS) { - - TRACE_INFO_WP("SendCSW "); - - // Wait for end of transfer - pMsdDriver->state = MSDD_STATE_WAIT_CSW; - } - break; - - //---------------------- - case MSDD_STATE_WAIT_CSW: - //---------------------- - // Check transfer semaphore - if (transfer->semaphore > 0) { - - // Take semaphore and terminate transfer - transfer->semaphore--; - - // Check if transfer was successful - if (transfer->status == USBD_STATUS_RESET) { - - TRACE_INFO("MSDD_StateMachine: EP resetted\n\r"); - } - else if (transfer->status == USBD_STATUS_ABORTED) { - - TRACE_WARNING( - "MSDD_StateMachine: Failed to send CSW\n\r"); - } - else { - - TRACE_INFO_WP("ok"); - } - - // Read new CBW - pMsdDriver->state = MSDD_STATE_READ_CBW; - } - break; - - //---------------------- - case MSDD_STATE_WAIT_HALT: - //---------------------- - if (MSDD_IsHalted() == 0) { - - pMsdDriver->state = MSDD_STATE_SEND_CSW; - } - break; - } -} diff --git a/radio/bootloader/usb/device/massstorage/MSDDStateMachine.h b/radio/bootloader/usb/device/massstorage/MSDDStateMachine.h deleted file mode 100644 index ad096d83d..000000000 --- a/radio/bootloader/usb/device/massstorage/MSDDStateMachine.h +++ /dev/null @@ -1,264 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//----------------------------------------------------------------------------- -/// \unit -/// !Purpose -/// -/// Definitions, structs, functions required by a Mass Storage device driver -/// state machine.. -/// -/// !Usage -/// -/// - For a USB device: -/// -# MSDD_Write, MSDD_Read, MSDD_Halt should be defined for -/// usage in the state machine procedure. -/// -/// -# MSDD_StateMachine is invoked to run the MSD state machine. -/// -//----------------------------------------------------------------------------- - -#ifndef MSDDSTATEMACHINE_H -#define MSDDSTATEMACHINE_H - -//----------------------------------------------------------------------------- -// Headers -//----------------------------------------------------------------------------- - -#include "MSD.h" -#include "MSDLun.h" -#include "debug.h" - -//----------------------------------------------------------------------------- -// Definitions -//----------------------------------------------------------------------------- - -//------------------------------------------------------------------------------ -/// \page "MSD Driver Possible states" -/// ... -/// -/// !States -/// - MSDD_STATE_READ_CBW -/// - MSDD_STATE_WAIT_CBW -/// - MSDD_STATE_PROCESS_CBW -/// - MSDD_STATE_WAIT_HALT -/// - MSDD_STATE_SEND_CSW -/// - MSDD_STATE_WAIT_CSW -/// - MSDD_STATE_WAIT_RESET - -//! \brief Driver is expecting a command block wrapper -#define MSDD_STATE_READ_CBW (1 << 0) - -//! \brief Driver is waiting for the transfer to finish -#define MSDD_STATE_WAIT_CBW (1 << 1) - -//! \brief Driver is processing the received command -#define MSDD_STATE_PROCESS_CBW (1 << 2) - -//! \brief Driver is halted because pipe halt or wait reset -#define MSDD_STATE_WAIT_HALT (1 << 3) - -//! \brief Driver is starting the transmission of a command status wrapper -#define MSDD_STATE_SEND_CSW (1 << 4) - -//! \brief Driver is waiting for the CSW transmission to finish -#define MSDD_STATE_WAIT_CSW (1 << 5) - -//! \brief Driver is waiting for the MassStorageReset -#define MSDD_STATE_WAIT_RESET (1 << 6) -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Driver Result Codes" -/// This page lists result codes for MSD functions. -/// -/// !Codes -/// - MSDD_STATUS_SUCCESS -/// - MSDD_STATUS_ERROR -/// - MSDD_STATUS_INCOMPLETE -/// - MSDD_STATUS_PARAMETER -/// - MSDD_STATUS_RW - -//! \brief Method was successful -#define MSDD_STATUS_SUCCESS 0x00 - -//! \brief There was an error when trying to perform a method -#define MSDD_STATUS_ERROR 0x01 - -//! \brief No error was encountered but the application should call the -//! method again to continue the operation -#define MSDD_STATUS_INCOMPLETE 0x02 - -//! \brief A wrong parameter has been passed to the method -#define MSDD_STATUS_PARAMETER 0x03 - -//! \brief An error when reading/writing disk (protected or not present) -#define MSDD_STATUS_RW 0x04 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Driver Action Cases" -/// This page lists actions to perform during the post-processing phase of a -/// command. -/// -/// !Actions -/// - MSDD_CASE_PHASE_ERROR -/// - MSDD_CASE_STALL_IN -/// - MSDD_CASE_STALL_OUT - -//! \brief Indicates that the CSW should report a phase error -#define MSDD_CASE_PHASE_ERROR (1 << 0) - -//! \brief The driver should halt the Bulk IN pipe after the transfer -#define MSDD_CASE_STALL_IN (1 << 1) - -//! \brief The driver should halt the Bulk OUT pipe after the transfer -#define MSDD_CASE_STALL_OUT (1 << 2) - -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Driver Xfr Directions" -/// This page lists possible direction values for a data transfer -/// -/// !Directions -/// - MSDD_DEVICE_TO_HOST -/// - MSDD_HOST_TO_DEVICE -/// - MSDD_NO_TRANSFER - -#define MSDD_DEVICE_TO_HOST 0 -#define MSDD_HOST_TO_DEVICE 1 -#define MSDD_NO_TRANSFER 2 -//------------------------------------------------------------------------------ - -//----------------------------------------------------------------------------- -// Types -//----------------------------------------------------------------------------- - -//------------------------------------------------------------------------------ -//! \brief Structure for holding the result of a USB transfer -//! \see MSDDriver_Callback -//------------------------------------------------------------------------------ -typedef struct { - - volatile unsigned int transferred; /// Number of bytes transferred - volatile unsigned int remaining; /// Number of bytes not transferred - volatile unsigned short semaphore; /// Semaphore to indicate transfer completion - volatile unsigned short status; /// Operation result code - -} MSDTransfer; - -//------------------------------------------------------------------------------ -//! \brief Status of an executing command -//! \see MSDCbw -//! \see MSDCsw -//! \see MSDTransfer -//------------------------------------------------------------------------------ -typedef struct { - - MSDTransfer transfer; /// Current transfer status (USB) - MSDTransfer disktransfer;/// Current transfer status (Disk) - unsigned int length; /// Remaining length of command - MSCbw cbw; /// Received CBW (31 bytes) - unsigned char state; /// Current command state - MSCsw csw; /// CSW to send (13 bytes) - unsigned char postprocess; /// Actions to perform when command is complete - -} MSDCommandState; - -//------------------------------------------------------------------------------ -/// \brief MSD driver state variables -/// \see MSDCommandState -/// \see MSDLun -//------------------------------------------------------------------------------ -typedef struct { - - /// LUN list for the %device. - MSDLun *luns; - /// State of the currently executing command - MSDCommandState commandState; - /// Maximum LUN index - unsigned char maxLun; - /// Current state of the driver - unsigned char state; - /// Indicates if the driver is waiting for a reset recovery - unsigned char waitResetRecovery; - -} MSDDriver; - -//----------------------------------------------------------------------------- -// Inline functions -//----------------------------------------------------------------------------- -//----------------------------------------------------------------------------- -/// This function is to be used as a callback for USB or LUN transfers. -/// \param transfer Pointer to the transfer structure to update -/// \param status Operation result code -/// \param transferred Number of bytes transferred by the command -/// \param remaining Number of bytes not transferred -//----------------------------------------------------------------------------- -static inline void MSDDriver_Callback(MSDTransfer *transfer, - unsigned char status, - unsigned int transferred, - unsigned int remaining) -{ - TRACE_DEBUG("Cbk "); - transfer->semaphore++; - transfer->status = status; - transfer->transferred = transferred; - transfer->remaining = remaining; -} - -//----------------------------------------------------------------------------- -// Driver functions -//----------------------------------------------------------------------------- -//- MSD General support function -extern char MSDD_Read( - void* pData, - unsigned int dLength, - TransferCallback fCallback, - void* pArgument); - -extern char MSDD_Write( - void* pData, - unsigned int dLength, - TransferCallback fCallback, - void* pArgument); - -extern void MSDD_Halt(unsigned int stallCase); - -extern unsigned int MSDD_IsHalted(void); - -//----------------------------------------------------------------------------- -// Exported functions -//----------------------------------------------------------------------------- - -extern void MSDD_StateMachine(MSDDriver * pMsdDriver); - -#endif // #define MSDDSTATEMACHINE_H - diff --git a/radio/bootloader/usb/device/massstorage/MSDDriver.c b/radio/bootloader/usb/device/massstorage/MSDDriver.c deleted file mode 100644 index a93c85f94..000000000 --- a/radio/bootloader/usb/device/massstorage/MSDDriver.c +++ /dev/null @@ -1,343 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ - -#include -#include "MSDDriver.h" -#include "MSDDriverDescriptors.h" -#include "SBCMethods.h" -#include "debug.h" -#include -#include -#include -#include -#include -#include - -//----------------------------------------------------------------------------- -// Internal variables -//----------------------------------------------------------------------------- - -/// Mass storage device driver instance. -static MSDDriver msdDriver; - -/// Standard device driver instance. -static USBDDriver usbdDriver; - -//----------------------------------------------------------------------------- -// Internal functions -//----------------------------------------------------------------------------- - -//----------------------------------------------------------------------------- -/// Resets the state of the MSD driver -//----------------------------------------------------------------------------- -static void MSDDriver_Reset(void) -{ - TRACE_INFO_WP("MSDReset "); - - msdDriver.state = MSDD_STATE_READ_CBW; - msdDriver.waitResetRecovery = 0; - msdDriver.commandState.state = 0; -} - -//----------------------------------------------------------------------------- -// Callback re-implementation -//----------------------------------------------------------------------------- -//----------------------------------------------------------------------------- -/// Invoked when a new SETUP request is received from the host. Forwards the -/// request to the Mass Storage device driver handler function. -/// \param request Pointer to a USBGenericRequest instance. -//----------------------------------------------------------------------------- -void USBDCallbacks_RequestReceived(const USBGenericRequest *request) -{ - MSDDriver_RequestHandler(request); -} - -//----------------------------------------------------------------------------- -/// Invoked when the configuration of the device changes. Resets the mass -/// storage driver. -/// \param cfgnum New configuration number. -//----------------------------------------------------------------------------- -void USBDDriverCallbacks_ConfigurationChanged(unsigned char cfgnum) -{ - if (cfgnum > 0) { - - MSDDriver_Reset(); - } -} - -//----------------------------------------------------------------------------- -// Driver functions -//----------------------------------------------------------------------------- - -//----------------------------------------------------------------------------- -/// Reads from host through MSD defined bulk OUT pipe. Act as USBD_Read but by -/// a fixed OUT endpoint. -/// \param data Pointer to the data buffer that contains data read from host. -/// \param size The number of bytes should be read (buffer size). -/// \param callback Pointer to the function invoked on end of reading. -/// \param argument Pointer to additional argument data struct. -//----------------------------------------------------------------------------- -char MSDD_Read(void *data, - unsigned int size, - TransferCallback callback, - void *argument) - -{ - return USBD_Read(MSDDriverDescriptors_BULKOUT, - data, - size, - callback, - argument); -} - -//----------------------------------------------------------------------------- -/// Writes to host through MSD defined bulk IN pipe. Act as USBD_Write but by -/// a fixed IN endpoint. -/// \param data Pointer to the data that writes to the host. -/// \param size The number of bytes should be write. -/// \param callback Pointer to the function invoked on end of writing. -/// \param argument Pointer to additional argument data struct. -//----------------------------------------------------------------------------- -char MSDD_Write(void *data, - unsigned int size, - TransferCallback callback, - void *argument) -{ - return USBD_Write(MSDDriverDescriptors_BULKIN, - data, - size, - callback, - argument); -} - -//----------------------------------------------------------------------------- -/// HALT Specified USB pipe. -/// \param stallCASE Case of the stall condition (Bulk In/Out/Both). -//----------------------------------------------------------------------------- -void MSDD_Halt(unsigned int stallCASE) -{ - if (stallCASE & MSDD_CASE_STALL_OUT) { - - USBD_Halt(MSDDriverDescriptors_BULKOUT); - } - - if (stallCASE & MSDD_CASE_STALL_IN) { - - USBD_Halt(MSDDriverDescriptors_BULKIN); - } -} - -//----------------------------------------------------------------------------- -/// Return halted status -/// \return stallCASE bitmap, case of the stall condition -/// (bit: MSDD_CASE_STALL_OUT or MSDD_CASE_STALL_IN) -//----------------------------------------------------------------------------- -unsigned int MSDD_IsHalted(void) -{ - unsigned int stallCASE = 0; - if (USBD_IsHalted(MSDDriverDescriptors_BULKOUT)) { - - stallCASE |= MSDD_CASE_STALL_OUT; - } - if (USBD_IsHalted(MSDDriverDescriptors_BULKIN)) { - - stallCASE |= MSDD_CASE_STALL_IN; - } - return stallCASE; -} - -//----------------------------------------------------------------------------- -// Exported functions -//----------------------------------------------------------------------------- - -//----------------------------------------------------------------------------- -/// Initializes the MSD driver and the associated USB driver. -/// \param luns Pointer to a list of LUNs -/// \param numLuns Number of LUN in list -/// \see MSDLun -//----------------------------------------------------------------------------- -void MSDDriver_Initialize(MSDLun *defLuns, unsigned char numLuns) -{ - - TRACE_INFO("MSD init\n\r"); - - // Command state initialization - msdDriver.commandState.state = 0; - msdDriver.commandState.postprocess = 0; - msdDriver.commandState.length = 0; - msdDriver.commandState.transfer.semaphore = 0; - - // LUNs - msdDriver.luns = defLuns; - msdDriver.maxLun = (unsigned char) (numLuns - 1); - - // Reset BOT driver - MSDDriver_Reset(); - - // Init the USB driver - USBDDriver_Initialize(&usbdDriver, &msdDriverDescriptors, 0); - USBD_Init(); -} - -//----------------------------------------------------------------------------- -/// Handler for incoming SETUP requests on default Control endpoint 0. -/// -/// Standard requests are forwarded to the USBDDriver_RequestHandler -/// method. -/// \param request Pointer to a USBGenericRequest instance -//----------------------------------------------------------------------------- -void MSDDriver_RequestHandler(const USBGenericRequest *request) -{ - TRACE_INFO_WP("NewReq "); - - // Handle requests - switch (USBGenericRequest_GetRequest(request)) { - //--------------------- - case USBGenericRequest_CLEARFEATURE: - //--------------------- - TRACE_INFO_WP("ClrFeat "); - - switch (USBFeatureRequest_GetFeatureSelector(request)) { - - //--------------------- - case USBFeatureRequest_ENDPOINTHALT: - //--------------------- - TRACE_INFO_WP("Hlt "); - - // Do not clear the endpoint halt status if the device is waiting - // for a reset recovery sequence - if (!msdDriver.waitResetRecovery) { - - // Forward the request to the standard handler - USBDDriver_RequestHandler(&usbdDriver, request); - } - else { - - TRACE_INFO_WP("No "); - } - - USBD_Write(0, 0, 0, 0, 0); - break; - - //------ - default: - //------ - // Forward the request to the standard handler - USBDDriver_RequestHandler(&usbdDriver, request); - } - break; - - //------------------- - case MSD_GET_MAX_LUN: - //------------------- - TRACE_INFO_WP("gMaxLun "); - - // Check request parameters - if ((request->wValue == 0) - && (request->wIndex == 0) - && (request->wLength == 1)) { - - USBD_Write(0, &(msdDriver.maxLun), 1, 0, 0); - - } - else { - - TRACE_WARNING( - "MSDDriver_RequestHandler: GetMaxLUN(%d,%d,%d)\n\r", - request->wValue, request->wIndex, request->wLength); - USBD_Stall(0); - } - break; - - //----------------------- - case MSD_BULK_ONLY_RESET: - //----------------------- - TRACE_INFO_WP("Rst "); - - // Check parameters - if ((request->wValue == 0) - && (request->wIndex == 0) - && (request->wLength == 0)) { - - // Reset the MSD driver - MSDDriver_Reset(); - USBD_Write(0, 0, 0, 0, 0); - } - else { - - TRACE_WARNING( - "MSDDriver_RequestHandler: Reset(%d,%d,%d)\n\r", - request->wValue, request->wIndex, request->wLength); - USBD_Stall(0); - } - break; - - //------ - default: - //------ - // Forward request to standard handler - USBDDriver_RequestHandler(&usbdDriver, request); - - break; - } -} - -//----------------------------------------------------------------------------- -/// State machine for the MSD driver -//----------------------------------------------------------------------------- -void MSDDriver_StateMachine(void) -{ - if (USBD_GetState() < USBD_STATE_CONFIGURED){} - else MSDD_StateMachine(&msdDriver); - -} - -//----------------------------------------------------------------------------- -/// Starts a remote wake-up sequence if the host has explicitely enabled it -/// by sending the appropriate SET_FEATURE request. -//----------------------------------------------------------------------------- -void MSDDriver_RemoteWakeUp(void) -{ - // Remote wake-up has been enabled - if (USBDDriver_IsRemoteWakeUpEnabled(&usbdDriver)) { - - USBD_RemoteWakeUp(); - } - // Remote wake-up NOT enabled - else { - - TRACE_WARNING( - "MSD..RemoteWakeUp: Host has not enabled remote wake-up\n\r"); - } -} - diff --git a/radio/bootloader/usb/device/massstorage/MSDDriver.h b/radio/bootloader/usb/device/massstorage/MSDDriver.h deleted file mode 100644 index 30e6b087c..000000000 --- a/radio/bootloader/usb/device/massstorage/MSDDriver.h +++ /dev/null @@ -1,75 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Mass storage %device driver implementation. -/// -/// !Usage -/// -/// -# Enable and setup USB related pins (see pio & board.h). -/// -# Configure the memory interfaces used for Mass Storage LUNs -/// (see memories, MSDLun.h). -/// -# Configure the USB MSD %driver using MSDDriver_Initialize. -/// -# Invoke MSDDriver_StateMachine in main loop to handle all Mass Storage -/// operations. -//------------------------------------------------------------------------------ - -#ifndef MSDDRIVER_H -#define MSDDRIVER_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "MSD.h" -#include "MSDLun.h" -// #include - -//------------------------------------------------------------------------------ -// Global functions -//------------------------------------------------------------------------------ - -extern void MSDDriver_Initialize(MSDLun *luns, unsigned char numLuns); - -extern void MSDDriver_RequestHandler(const USBGenericRequest *request); - -extern void MSDDriver_StateMachine(void); - -extern void MSDDriver_RemoteWakeUp(void); - -extern void MSDDriver_DataCallback(unsigned char isRead, - unsigned int dataLength, - unsigned int nullCnt, - unsigned int fullCnt); - -#endif // #ifndef MSDDRIVER_H - diff --git a/radio/bootloader/usb/device/massstorage/MSDDriverDescriptors.c b/radio/bootloader/usb/device/massstorage/MSDDriverDescriptors.c deleted file mode 100644 index b37653bc5..000000000 --- a/radio/bootloader/usb/device/massstorage/MSDDriverDescriptors.c +++ /dev/null @@ -1,395 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "MSDDriverDescriptors.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include - -//------------------------------------------------------------------------------ -// Internal definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Device Descriptor IDs" -/// ... -/// !IDs -/// - MSDDriverDescriptors_VENDORID -/// - MSDDriverDescriptors_PRODUCTID -/// - MSDDriverDescriptors_RELEASE - -/// Vendor ID for the Mass Storage device driver. -#define MSDDriverDescriptors_VENDORID 0x03EB -/// Product ID for the Mass Storage device driver. -#ifdef HID -#define HIDMSDDDriverDescriptors_PRODUCTID 0x6135 -#else -#define MSDDriverDescriptors_PRODUCTID 0x6129 -#endif -/// Device release number for the Mass Storage device driver. -#define MSDDriverDescriptors_RELEASE 0x0100 - -#ifdef HID -/** Address of the HID interrupt IN endpoint. */ -#define HIDD_Descriptors_INTERRUPTIN 1 -/** Address of the HID interrupt OUT endpoint. */ -#define HIDD_Descriptors_INTERRUPTOUT 2 -/** Address of the Mass Storage bulk-out endpoint. */ -#define MSDD_Descriptors_BULKOUT 4 -/** Address of the Mass Storage bulk-in endpoint. */ -#define MSDD_Descriptors_BULKIN 5 -#endif - -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Macros -//------------------------------------------------------------------------------ - -/// Returns the minimum between two values. -#define MIN(a, b) ((a < b) ? a : b) - -//------------------------------------------------------------------------------ -// Internal types -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// List of configuration descriptors used by a Mass Storage device driver. -//------------------------------------------------------------------------------ -#ifndef HID -typedef struct { - - /// Standard configuration descriptor. - USBConfigurationDescriptor configuration; - /// Mass storage interface descriptor. - USBInterfaceDescriptor interface; - /// Bulk-out endpoint descriptor. - USBEndpointDescriptor bulkOut; - /// Bulk-in endpoint descriptor. - USBEndpointDescriptor bulkIn; - -} __attribute__ ((packed)) MSDConfigurationDescriptors; -#endif - -//------------------------------------------------------------------------------ -// Local variables -//------------------------------------------------------------------------------ - -#ifdef HID -/** Standard USB device descriptor for the composite device driver */ -static const USBDeviceDescriptor deviceDescriptor = -{ - - sizeof(USBDeviceDescriptor), - USBGenericDescriptor_DEVICE, - USBDeviceDescriptor_USB2_00, - 0x00, - 0x00, - 0x00, - CHIP_USB_ENDPOINTS_MAXPACKETSIZE(0), - HIDMSDDDriverDescriptors_VENDORID, - HIDMSDDDriverDescriptors_PRODUCTID, - HIDMSDDDriverDescriptors_RELEASE, -// 0, /* No string descriptor for manufacturer */ -// 1, /* Index of product string descriptor is #1 */ -// 0, /* No string descriptor for serial number */ - 1, // Manufacturer string descriptor index. - 2, // Product string descriptor index. - 3, // Serial number string descriptor index. - 1 /* Device has 1 possible configuration */ -}; -#else -/// Mass storage driver device descriptor. -static const USBDeviceDescriptor deviceDescriptor = { - - sizeof(USBDeviceDescriptor), - USBGenericDescriptor_DEVICE, - USBDeviceDescriptor_USB2_00, - MSDeviceDescriptor_CLASS, - MSDeviceDescriptor_SUBCLASS, - MSDeviceDescriptor_PROTOCOL, - CHIP_USB_ENDPOINTS_MAXPACKETSIZE(0), - MSDDriverDescriptors_VENDORID, - MSDDriverDescriptors_PRODUCTID, - MSDDriverDescriptors_RELEASE, - 1, // Manufacturer string descriptor index. - 2, // Product string descriptor index. - 3, // Serial number string descriptor index. - 1 // Device has one possible configuration. -}; -#endif - -#ifdef HID -/** USB FS configuration descriptors for the composite device driver */ -static const HidMsdDriverConfigurationDescriptors configurationDescriptorsFS = -{ - - /* Standard configuration descriptor */ - { - sizeof(USBConfigurationDescriptor), - USBGenericDescriptor_CONFIGURATION, - sizeof(HidMsdDriverConfigurationDescriptors), - HIDMSDDriverDescriptors_NUMINTERFACE, - 1, /* This is configuration #1 */ - 0, /* No string descriptor for this configuration */ - BOARD_USB_BMATTRIBUTES, - USBConfigurationDescriptor_POWER(100) - }, - - /* Interface descriptor */ - { - sizeof(USBInterfaceDescriptor), - USBGenericDescriptor_INTERFACE, - HIDMSDDriverDescriptors_HID_INTERFACE, - 0, /* This is alternate setting #0 */ - 2, /* Two endpoints used */ - HIDInterfaceDescriptor_CLASS, - HIDInterfaceDescriptor_SUBCLASS_NONE, - HIDInterfaceDescriptor_PROTOCOL_NONE, - 0 /* No associated string descriptor */ - }, - /* HID descriptor */ - { - sizeof(HIDDescriptor1), - HIDGenericDescriptor_HID, - HIDDescriptor_HID1_11, - 0, /* Device is not localized, no country code */ - 1, /* One HID-specific descriptor (apart from this one) */ - HIDGenericDescriptor_REPORT, - HIDDKeyboard_REPORTDESCRIPTORSIZE - }, - /* Interrupt IN endpoint descriptor */ - { - sizeof(USBEndpointDescriptor), - USBGenericDescriptor_ENDPOINT, - USBEndpointDescriptor_ADDRESS( - USBEndpointDescriptor_IN, - HIDD_Descriptors_INTERRUPTIN), - USBEndpointDescriptor_INTERRUPT, - sizeof(HIDDKeyboardInputReport), - HIDDKeyboardDescriptors_INTERRUPTIN_POLLING_FS - }, - /* Interrupt OUT endpoint descriptor */ - { - sizeof(USBEndpointDescriptor), - USBGenericDescriptor_ENDPOINT, - USBEndpointDescriptor_ADDRESS( - USBEndpointDescriptor_OUT, - HIDD_Descriptors_INTERRUPTOUT), - USBEndpointDescriptor_INTERRUPT, - sizeof(HIDDKeyboardOutputReport), - HIDDKeyboardDescriptors_INTERRUPTIN_POLLING_FS - }, - - /* Mass Storage interface descriptor. */ - { - sizeof(USBInterfaceDescriptor), - USBGenericDescriptor_INTERFACE, - HIDMSDDriverDescriptors_MSD_INTERFACE, - 0, /* This is alternate setting #0. */ - 2, /* Interface uses two endpoints. */ - MSInterfaceDescriptor_CLASS, - MSInterfaceDescriptor_SCSI, - MSInterfaceDescriptor_BULKONLY, - 0 /* No string descriptor for interface. */ - }, - /* Bulk-OUT endpoint descriptor */ - { - sizeof(USBEndpointDescriptor), - USBGenericDescriptor_ENDPOINT, - USBEndpointDescriptor_ADDRESS( - USBEndpointDescriptor_OUT, - MSDD_Descriptors_BULKOUT), //MSDDriverDescriptors_BULKOUT - USBEndpointDescriptor_BULK, - MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDD_Descriptors_BULKOUT),//MSDDriverDescriptors_BULKOUT - USBEndpointDescriptor_MAXBULKSIZE_FS), - 0 /* No string descriptor for endpoint. */ - }, - /* Bulk-IN endpoint descriptor */ - { - sizeof(USBEndpointDescriptor), - USBGenericDescriptor_ENDPOINT, - USBEndpointDescriptor_ADDRESS( - USBEndpointDescriptor_IN, - MSDD_Descriptors_BULKIN), //MSDDriverDescriptors_BULKIN - USBEndpointDescriptor_BULK, - MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDD_Descriptors_BULKIN),//MSDDriverDescriptors_BULKIN - USBEndpointDescriptor_MAXBULKSIZE_FS), - 0 /* No string descriptor for endpoint. */ - } - -}; - -#else -/// Full-speed configuration descriptor. -static const MSDConfigurationDescriptors configurationDescriptorsFS = { - - // Standard configuration descriptor. - { - sizeof(USBConfigurationDescriptor), - USBGenericDescriptor_CONFIGURATION, - sizeof(MSDConfigurationDescriptors), - 1, // Configuration has one interface. - 1, // This is configuration #1. - 0, // No string descriptor for configuration. - BOARD_USB_BMATTRIBUTES, - USBConfigurationDescriptor_POWER(100) - }, - // Mass Storage interface descriptor. - { - sizeof(USBInterfaceDescriptor), - USBGenericDescriptor_INTERFACE, - 0, // This is interface #0. - 0, // This is alternate setting #0. - 2, // Interface uses two endpoints. - MSInterfaceDescriptor_CLASS, - MSInterfaceDescriptor_SCSI, - MSInterfaceDescriptor_BULKONLY, - 0 // No string descriptor for interface. - }, - // Bulk-OUT endpoint descriptor - { - sizeof(USBEndpointDescriptor), - USBGenericDescriptor_ENDPOINT, - USBEndpointDescriptor_ADDRESS( - USBEndpointDescriptor_OUT, - MSDDriverDescriptors_BULKOUT), - USBEndpointDescriptor_BULK, - MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDDriverDescriptors_BULKOUT), - USBEndpointDescriptor_MAXBULKSIZE_FS), - 0 // Must be 0 for full-speed Bulk endpoints. - }, - // Bulk-IN endpoint descriptor - { - sizeof(USBEndpointDescriptor), - USBGenericDescriptor_ENDPOINT, - USBEndpointDescriptor_ADDRESS( - USBEndpointDescriptor_IN, - MSDDriverDescriptors_BULKIN), - USBEndpointDescriptor_BULK, - MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDDriverDescriptors_BULKIN), - USBEndpointDescriptor_MAXBULKSIZE_FS), - 0 // Must be 0 for full-speed Bulk endpoints. - } -}; -#endif - -/// Language ID string descriptor. -static const unsigned char languageIdDescriptor[] = { - - USBStringDescriptor_LENGTH(1), - USBGenericDescriptor_STRING, - USBStringDescriptor_ENGLISH_US -}; - -/// Manufacturer string descriptor. -static const unsigned char manufacturerDescriptor[] = { - - USBStringDescriptor_LENGTH(7), - USBGenericDescriptor_STRING, - USBStringDescriptor_UNICODE('9'), - USBStringDescriptor_UNICODE('X'), - USBStringDescriptor_UNICODE(' '), - USBStringDescriptor_UNICODE('T'), - USBStringDescriptor_UNICODE('E'), - USBStringDescriptor_UNICODE('A'), - USBStringDescriptor_UNICODE('M'), -}; - -/// Product string descriptor. -static const unsigned char productDescriptor[] = { - - USBStringDescriptor_LENGTH(5), - USBGenericDescriptor_STRING, - USBStringDescriptor_UNICODE('S'), - USBStringDescriptor_UNICODE('K'), - USBStringDescriptor_UNICODE('Y'), - USBStringDescriptor_UNICODE('9'), - USBStringDescriptor_UNICODE('X'), -}; - -/// Serial number string descriptor. The serial number must be at least 12 -/// characters long and made up of only letters & numbers to be compliant with -/// the MSD specification. -static const unsigned char serialNumberDescriptor[] = { - - USBStringDescriptor_LENGTH(12), - USBGenericDescriptor_STRING, - USBStringDescriptor_UNICODE('0'), - USBStringDescriptor_UNICODE('1'), - USBStringDescriptor_UNICODE('2'), - USBStringDescriptor_UNICODE('3'), - USBStringDescriptor_UNICODE('4'), - USBStringDescriptor_UNICODE('5'), - USBStringDescriptor_UNICODE('6'), - USBStringDescriptor_UNICODE('7'), - USBStringDescriptor_UNICODE('8'), - USBStringDescriptor_UNICODE('9'), - USBStringDescriptor_UNICODE('A'), - USBStringDescriptor_UNICODE('B') -}; - -/// List of all string descriptors used. -static const unsigned char *stringDescriptors[] = { - - languageIdDescriptor, - manufacturerDescriptor, - productDescriptor, - serialNumberDescriptor -}; - -//------------------------------------------------------------------------------ -// Global variables -//------------------------------------------------------------------------------ - -/// List of the standard descriptors used by the Mass Storage driver. -const USBDDriverDescriptors msdDriverDescriptors = { - - &deviceDescriptor, - (USBConfigurationDescriptor *) &configurationDescriptorsFS, - 0, // No full-speed device qualifier descriptor - 0, // No full-speed other speed configuration - 0, // No high-speed device descriptor - 0, // No high-speed configuration descriptor - 0, // No high-speed device qualifier descriptor - 0, // No high-speed other speed configuration descriptor - stringDescriptors, - 4 // Four string descriptors in array -}; - diff --git a/radio/bootloader/usb/device/massstorage/MSDDriverDescriptors.h b/radio/bootloader/usb/device/massstorage/MSDDriverDescriptors.h deleted file mode 100644 index 6f1f151f5..000000000 --- a/radio/bootloader/usb/device/massstorage/MSDDriverDescriptors.h +++ /dev/null @@ -1,83 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Definitions of the descriptors required by a Mass Storage device driver. -/// -/// !Usage -/// -/// - For a USB %device: -/// -# When initializing a USBDDriver instance, use msdDriverDescriptors as -/// the list of standard descriptors. -//------------------------------------------------------------------------------ - -#ifndef MSDDRIVERDESCRIPTORS_H -#define MSDDRIVERDESCRIPTORS_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD endpoint addresses" -/// This page lists the addresses used by the Mass Storage driver %endpoints. -/// -/// !Addresses -/// -/// - MSDDriverDescriptors_BULKOUT -/// - MSDDriverDescriptors_BULKIN - -/// Address of the Mass Storage bulk-out endpoint. -#define MSDDriverDescriptors_BULKOUT 1 - -/// Address of the Mass Storage bulk-in endpoint. -#if defined(at91sam9m10) - #define MSDDriverDescriptors_BULKIN 6 -#else - #define MSDDriverDescriptors_BULKIN 2 -#endif -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Exported variables -//------------------------------------------------------------------------------ - -extern const USBDDriverDescriptors msdDriverDescriptors; - -#endif //#ifndef MSDDRIVERDESCRIPTORS_H - diff --git a/radio/bootloader/usb/device/massstorage/MSDIOFifo.h b/radio/bootloader/usb/device/massstorage/MSDIOFifo.h deleted file mode 100644 index 5f7b7fba5..000000000 --- a/radio/bootloader/usb/device/massstorage/MSDIOFifo.h +++ /dev/null @@ -1,135 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef _MSDIOFIFO_H -#define _MSDIOFIFO_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -/// Idle state, do nothing -#define MSDIO_IDLE 0 -/// Start, to start IO operation -#define MSDIO_START 1 -/// Wait, waiting for IO operation done -#define MSDIO_WAIT 2 -/// Next, to check if the next block can be performed -#define MSDIO_NEXT 3 -/// Pause, to pause the process for buffer full or null -#define MSDIO_PAUSE 4 -/// Abort, to abort the process -#define MSDIO_ABORT 5 -/// Done, finish without error -#define MSDIO_DONE 6 -/// Error, any error happens -#define MSDIO_ERROR 7 - -/// FIFO offset before USB transmit start -//#define MSDIO_FIFO_OFFSET (4*512) - -/// FIFO trunk size (in each transfer, large amount of data) -#if !defined(MSD_OP_BUFFER) -#define MSDIO_READ10_CHUNK_SIZE (4*512) -#define MSDIO_WRITE10_CHUNK_SIZE (4*512) -#endif - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -/// FIFO buffer for READ/WRITE (disk) operation of a mass storage device -typedef struct _MSDIOFifo { - - /// Pointer to the ring buffer allocated for read/write - unsigned char * pBuffer; - /// The size of the buffer allocated - unsigned int bufferSize; -#ifdef MSDIO_FIFO_OFFSET - /// The offset to start USB transfer (READ10) - unsigned int bufferOffset; -#endif - /// The index of input data (loaded to fifo buffer) - unsigned int inputNdx; - /// The total size of the loaded data - unsigned int inputTotal; - /// The index of output data (sent from the fifo buffer) - unsigned int outputNdx; - /// The total size of the output data - unsigned int outputTotal; - - /// The total size of the data - unsigned int dataTotal; - /// The size of the block in bytes - unsigned short blockSize; -#if defined(MSDIO_READ10_CHUNK_SIZE) || defined(MSDIO_WRITE10_CHUNK_SIZE) - /// The size of one chunk - /// (1 block, or several blocks for large amount data R/W) - unsigned int chunkSize; -#endif - /// State of input & output - unsigned char inputState; - unsigned char outputState; - - //- Statistics - /// Times when fifo has no data to send - unsigned short nullCnt; - /// Times when fifo can not load more input data - unsigned short fullCnt; -} MSDIOFifo, *PMSDIOFifo; - -//------------------------------------------------------------------------------ -// MACROS -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Increase the index, by defined block size, in the ring buffer -/// \param ndx The index to be increased -/// \param sectSize The defined block size -/// \param bufSize The ring buffer size -//------------------------------------------------------------------------------ -#define MSDIOFifo_IncNdx(ndx, sectSize, bufSize) \ - if ((ndx) >= (bufSize) - (sectSize)) (ndx) = 0; \ - else (ndx) += (sectSize) - - -//------------------------------------------------------------------------------ -// Exported Functions -//------------------------------------------------------------------------------ - - -extern void MSDIOFifo_Init(MSDIOFifo *pFifo, - void * pBuffer, unsigned short bufferSize); - -#endif // _MSDIOFIFO_H - diff --git a/radio/bootloader/usb/device/massstorage/MSDLun.c b/radio/bootloader/usb/device/massstorage/MSDLun.c deleted file mode 100644 index 6b649b4d2..000000000 --- a/radio/bootloader/usb/device/massstorage/MSDLun.c +++ /dev/null @@ -1,368 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - - -#include "MSDLun.h" -#include "debug.h" -#include - -#include "usb/device/massstorage/MSDDriver.h" - - -//------------------------------------------------------------------------------ -// Constants -//------------------------------------------------------------------------------ - -/// Default LUN block size in bytes -#define DEFAULT_LUN_BLOCK_SIZE 512 - -//------------------------------------------------------------------------------ -// Internal variables -//------------------------------------------------------------------------------ - -/// Inquiry data to return to the host for the Lun. -static SBCInquiryData inquiryData = { - - SBC_DIRECT_ACCESS_BLOCK_DEVICE, // Direct-access block device - SBC_PERIPHERAL_DEVICE_CONNECTED,// Peripheral device is connected - 0x00, // Reserved bits - 0x01, // Media is removable - SBC_SPC_VERSION_4, // SPC-4 supported - 0x2, // Response data format, must be 0x2 - 0, // Hierarchical addressing not supported - 0, // ACA not supported - 0x0, // Obsolete bits - sizeof(SBCInquiryData) - 5, // Additional length - 0, // No embedded SCC - 0, // No access control coordinator - SBC_TPGS_NONE, // No target port support group - 0, // Third-party copy not supported - 0x0, // Reserved bits - 0, // Protection information not supported - 0x0, // Obsolete bit - 0, // No embedded enclosure service component - 0x0, // ??? - 0, // Device is not multi-port - 0x0, // Obsolete bits - 0x0, // Unused feature - 0x0, // Unused features - 0, // Task management model not supported - 0x0, // ??? - {'E','R','S','K','Y','9','X',' '}, - {'M','a','s','s',' ', - 'S','t','o','r','a','g','e',' ', - 'M','S','D'}, - {'0','.','0','1'}, - {'M','a','s','s',' ', - 'S','t','o','r','a','g','e',' ', - 'E','x','a','m','p','l','e'}, - 0x00, // Unused features - 0x00, // Reserved bits - {SBC_VERSION_DESCRIPTOR_SBC_3}, // SBC-3 compliant device - {0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0} // Reserved -}; - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -//! \brief Initializes a LUN instance. Must be invoked at least once even no -//! Media is linked. -//! \param lun Pointer to the MSDLun instance to initialize -//! \param media Media on which the LUN is constructed, set to 0 to -//! disconnect the Media or initialize an ejected LUN. -//! \param ioBuffer Pointer to a buffer used for read/write operation and -//! which must be blockSize bytes long. -//! \param ioBufferSize Size of the allocated IO buffer. -//! \param baseAddress Base address of the LUN in number of media blocks -//! \param size Total size of the LUN in number of media blocks -//! \param blockSize One block of the LUN in number of media blocks -//! \param protected The LUN area is forced to readonly even the media -//! is writable -//! \param dataMonitor Pointer to a Monitor Function to analyze the flow of -//! this LUN. -//------------------------------------------------------------------------------ -void LUN_Init(MSDLun *lun, - Media *media, - unsigned char *ioBuffer, - unsigned int ioBufferSize, - unsigned int baseAddress, - unsigned int size, - unsigned short blockSize, - unsigned char protected, - void (*dataMonitor)(unsigned char flowDirection, - unsigned int dataLength, - unsigned int fifoNullCount, - unsigned int fifoFullCount)) -{ - unsigned int logicalBlockAddress; - TRACE_INFO("LUN init\n\r"); - - // Initialize inquiry data - lun->inquiryData = &inquiryData; - - // Initialize request sense data - lun->requestSenseData.bResponseCode = SBC_SENSE_DATA_FIXED_CURRENT; - lun->requestSenseData.isValid = 1; - lun->requestSenseData.bObsolete1 = 0; - lun->requestSenseData.bSenseKey = SBC_SENSE_KEY_NO_SENSE; - lun->requestSenseData.bReserved1 = 0; - lun->requestSenseData.isILI = 0; - lun->requestSenseData.isEOM = 0; - lun->requestSenseData.isFilemark = 0; - lun->requestSenseData.pInformation[0] = 0; - lun->requestSenseData.pInformation[1] = 0; - lun->requestSenseData.pInformation[2] = 0; - lun->requestSenseData.pInformation[3] = 0; - lun->requestSenseData.bAdditionalSenseLength - = sizeof(SBCRequestSenseData) - 8; - lun->requestSenseData.bAdditionalSenseCode = 0; - lun->requestSenseData.bAdditionalSenseCodeQualifier = 0; - lun->requestSenseData.bFieldReplaceableUnitCode = 0; - lun->requestSenseData.bSenseKeySpecific = 0; - lun->requestSenseData.pSenseKeySpecific[0] = 0; - lun->requestSenseData.pSenseKeySpecific[0] = 0; - lun->requestSenseData.isSKSV = 0; - - STORE_DWORDB(0, lun->readCapacityData.pLogicalBlockAddress); - STORE_DWORDB(0, lun->readCapacityData.pLogicalBlockLength); - - // Initialize LUN - lun->media = media; - if (media == 0) { - lun->status = LUN_NOT_PRESENT; - return; - } - - lun->baseAddress = baseAddress; - - // Customized block size - if (blockSize) { - lun->blockSize = blockSize; - } - else { - if (media->blockSize < DEFAULT_LUN_BLOCK_SIZE) - lun->blockSize = DEFAULT_LUN_BLOCK_SIZE / media->blockSize; - else - lun->blockSize = 1; - } - - if (size) { - lun->size = size; - } - else { - lun->size = media->size; - //if (blockSize) - // lun->size = media->size / blockSize; - //else { - // if (media->blockSize < DEFAULT_LUN_BLOCK_SIZE) - // lun->size = media->size / lun->blockSize; - // else - // lun->size = media->size; - //} - } - - TRACE_INFO("LUN: blkSize %d, size %d\n\r", (int)lun->blockSize, (int)lun->size); - if (protected) lun->protected = 1; - else lun->protected = media->protected; - - lun->ioFifo.pBuffer = ioBuffer; - lun->ioFifo.bufferSize = ioBufferSize; - - lun->dataMonitor = dataMonitor; - - // Initialize read capacity data - logicalBlockAddress = lun->size / lun->blockSize - 1; - STORE_DWORDB(logicalBlockAddress, - lun->readCapacityData.pLogicalBlockAddress); - STORE_DWORDB(lun->blockSize * media->blockSize, - lun->readCapacityData.pLogicalBlockLength); - - // Indicate media change - lun->status = LUN_CHANGED; -} - -//------------------------------------------------------------------------------ -//! \brief Eject the media from a LUN -//! \param lun Pointer to the MSDLun instance to initialize -//! \return Operation result code -//------------------------------------------------------------------------------ -unsigned char LUN_Eject(MSDLun *lun) -{ - if (lun->media) { - - // Avoid any LUN R/W in progress - if (lun->media->state == MED_STATE_BUSY) { - - return USBD_STATUS_LOCKED; - } - - // Remove the link of the media - lun->media = 0; - } - // LUN is removed - lun->status = LUN_NOT_PRESENT; - - return USBD_STATUS_SUCCESS; -} - -//------------------------------------------------------------------------------ -//! \brief Writes data on the a LUN starting at the specified block address. -//! \param lun Pointer to a MSDLun instance -//! \param blockAddress First block address to write -//! \param data Pointer to the data to write -//! \param length Number of blocks to write -//! \param callback Optional callback to invoke when the write finishes -//! \return Operation result code -//------------------------------------------------------------------------------ -unsigned char LUN_Write(MSDLun *lun, - unsigned int blockAddress, - void *data, - unsigned int length, - TransferCallback callback, - void *argument) -{ - unsigned int medBlk, medLen; - unsigned char status; - - TRACE_INFO_WP("LUNWrite(%u) ", blockAddress); - - // Check that the data is not too big - if ((length + blockAddress) * lun->blockSize > lun->size) { - - TRACE_WARNING("LUN_Write: Data too big\n\r"); - status = USBD_STATUS_ABORTED; - } - else if (lun->media == 0 || lun->status != LUN_READY) { - - TRACE_WARNING("LUN_Write: Media not ready\n\r"); - status = USBD_STATUS_ABORTED; - } - else if (lun->protected) { - TRACE_WARNING("LUN_Write: LUN is readonly\n\r"); - status = USBD_STATUS_ABORTED; - } - else { - - // Compute write start address - medBlk = lun->baseAddress + blockAddress * lun->blockSize; - medLen = length * lun->blockSize; - - // Start write operation - status = MED_Write(lun->media, - medBlk, - data, - medLen, - (MediaCallback) callback, - argument); - - // Check operation result code - if (status == MED_STATUS_SUCCESS) { - - status = USBD_STATUS_SUCCESS; - } - else { - - TRACE_WARNING("LUN_Write: Cannot write media\n\r"); - status = USBD_STATUS_ABORTED; - } - } - - return status; -} - -//------------------------------------------------------------------------------ -//! \brief Reads data from a LUN, starting at the specified block address. -//! \param lun Pointer to a MSDLun instance -//! \param blockAddress First block address to read -//! \param data Pointer to a data buffer in which to store the data -//! \param length Number of blocks to read -//! \param callback Optional callback to invoke when the read finishes -//! \return Operation result code -//------------------------------------------------------------------------------ -unsigned char LUN_Read(MSDLun *lun, - unsigned int blockAddress, - void *data, - unsigned int length, - TransferCallback callback, - void *argument) -{ - unsigned int medBlk, medLen; - unsigned char status; - - // Check that the data is not too big - if ((length + blockAddress) * lun->blockSize > lun->size) { - TRACE_WARNING("LUN_Read: Area: (%d + %d)*%d > %d\n\r", - (int)length, (int)blockAddress, (int)lun->blockSize, (int)lun->size); - status = USBD_STATUS_ABORTED; - } - else if (lun->media == 0 || lun->status != LUN_READY) { - - TRACE_WARNING("LUN_Read: Media not present\n\r"); - status = USBD_STATUS_ABORTED; - } - else { - - TRACE_INFO_WP("LUNRead(%u) ", blockAddress); - - // Compute read start address - medBlk = lun->baseAddress + (blockAddress * lun->blockSize); - medLen = length * lun->blockSize; - - // Start write operation - status = MED_Read(lun->media, - medBlk, - data, - medLen, - (MediaCallback) callback, - argument); - - // Check result code - if (status == MED_STATUS_SUCCESS) { - - status = USBD_STATUS_SUCCESS; - } - else { - - TRACE_WARNING("LUN_Read: Cannot read media\n\r"); - status = USBD_STATUS_ABORTED; - } - } - - return status; -} diff --git a/radio/bootloader/usb/device/massstorage/MSDLun.h b/radio/bootloader/usb/device/massstorage/MSDLun.h deleted file mode 100644 index 799775541..000000000 --- a/radio/bootloader/usb/device/massstorage/MSDLun.h +++ /dev/null @@ -1,161 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Logical Unit Number (LUN) used by the Mass Storage driver and the SCSI -/// protocol. Represents a logical hard-drive. -/// -/// !Usage -/// -# Initialize Memory related pins (see pio & board.h). -/// -# Initialize a Media instance for the LUN (see memories). -/// -# Initlalize the LUN with LUN_Init, and link to the initialized Media. -/// -# To read data from the LUN linked media, uses LUN_Read. -/// -# To write data to the LUN linked media, uses LUN_Write. -/// -# To unlink the media, uses LUN_Eject. -//------------------------------------------------------------------------------ - -#ifndef MSDLUN_H -#define MSDLUN_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "SBC.h" -#include -#include -#include - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -/// LUN RC: success -#define LUN_STATUS_SUCCESS 0x00 -/// LUN RC: error -#define LUN_STATUS_ERROR 0x02 - -/// Media of LUN is removed -#define LUN_NOT_PRESENT 0x00 -/// LUN is ejected by host -#define LUN_EJECTED 0x01 -/// Media of LUN is changed -#define LUN_CHANGED 0x10 -/// LUN Not Ready to Ready transition -#define LUN_TRANS_READY LUN_CHANGED -/// Media of LUN is ready -#define LUN_READY 0x11 - -//------------------------------------------------------------------------------ -// Structures -//------------------------------------------------------------------------------ - -/// LUN structure -typedef struct { - - /// Pointer to a SBCInquiryData instance. - SBCInquiryData *inquiryData; - /// Fifo for USB transfer, must be assigned. - MSDIOFifo ioFifo; - /// Pointer to Media instance for the LUN. - Media *media; - /// Pointer to a Monitor Function to analyze the flow of LUN. - /// \param flowDirection 1 - device to host (READ10) - /// 0 - host to device (WRITE10) - /// \param dataLength Length of data transferred in bytes. - /// \param fifoNullCount Times that FIFO is NULL to wait - /// \param fifoFullCount Times that FIFO is filled to wait - void (*dataMonitor)(unsigned char flowDirection, - unsigned int dataLength, - unsigned int fifoNullCount, - unsigned int fifoFullCount); - /// The start position of the media (blocks) allocated to the LUN. - unsigned int baseAddress; - /// The size of the media (blocks) allocated to the LUN. - unsigned int size; - /// Sector size of the media in number of media blocks - unsigned short blockSize; - /// The LUN can be readonly even the media is writable -#ifdef __cplusplus - unsigned char protectd; -#else - unsigned char protected; -#endif - - /// The LUN status (Ejected/Changed/) - unsigned char status; - - /// Data for the RequestSense command. - SBCRequestSenseData requestSenseData; - /// Data for the ReadCapacity command. - SBCReadCapacity10Data readCapacityData; - -} MSDLun; - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -extern void LUN_Init(MSDLun *lun, - Media *media, - unsigned char *ioBuffer, - unsigned int ioBufferSize, - unsigned int baseAddress, - unsigned int size, - unsigned short blockSize, -#ifdef __cplusplus - unsigned char protectd, -#else - unsigned char protected, -#endif - void (*dataMonitor)(unsigned char flowDirection, - unsigned int dataLength, - unsigned int fifoNullCount, - unsigned int fifoFullCount)); - -extern unsigned char LUN_Eject(MSDLun *lun); - -extern unsigned char LUN_Write(MSDLun *lun, - unsigned int blockAddress, - void *data, - unsigned int length, - TransferCallback callback, - void *argument); - -extern unsigned char LUN_Read(MSDLun *lun, - unsigned int blockAddress, - void *data, - unsigned int length, - TransferCallback callback, - void *argument); - -#endif //#ifndef MSDLUN_H - diff --git a/radio/bootloader/usb/device/massstorage/SBC.h b/radio/bootloader/usb/device/massstorage/SBC.h deleted file mode 100644 index 3c3f93c69..000000000 --- a/radio/bootloader/usb/device/massstorage/SBC.h +++ /dev/null @@ -1,653 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// SCSI definitions. -/// -/// !Usage -/// -/// -# After command block received, Access and decode the SCSI command block -/// with SBCCommand structure. -//------------------------------------------------------------------------------ - -#ifndef SBC_H -#define SBC_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Operation Codes" -/// This page lists operation codes of commands described in the SBC-3 -/// standard. -/// -/// \note That most commands are actually defined in other standards, -/// like SPC-4. Optional commands are not included here. -/// -/// \see sbc3r07.pdf - Section 5.1 - Table 12 -/// \see spc4r06.pdf -/// \see SBCCommand -/// -/// !Codes -/// - SBC_INQUIRY -/// - SBC_READ_10 -/// - SBC_READ_CAPACITY_10 -/// - SBC_REQUEST_SENSE -/// - SBC_TEST_UNIT_READY -/// - SBC_WRITE_10 -/// -/// !Optional Codes but required by Windows -/// - SBC_PREVENT_ALLOW_MEDIUM_REMOVAL -/// - SBC_MODE_SENSE_6 -/// - SBC_VERIFY_10 -/// - SBC_READ_FORMAT_CAPACITIES - -/// Request information regarding parameters of the target and Logical Unit. -#define SBC_INQUIRY 0x12 -/// Request the transfer data to the host. -#define SBC_READ_10 0x28 -/// Request capacities of the currently installed medium. -#define SBC_READ_CAPACITY_10 0x25 -/// Request that the device server transfer sense data. -#define SBC_REQUEST_SENSE 0x03 -/// Check if the LUN is ready -#define SBC_TEST_UNIT_READY 0x00 -/// Request that the device write the data transferred by the host. -#define SBC_WRITE_10 0x2A - -/// Request that the target enable or disable the removal of the medium in -/// the Logical Unit. -#define SBC_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E -/// Report parameters. -#define SBC_MODE_SENSE_6 0x1A -/// Request that the %device verify the data on the medium. -#define SBC_VERIFY_10 0x2F -/// Request a list of the possible capacities that can be formatted on medium -#define SBC_READ_FORMAT_CAPACITIES 0x23 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Periph. Qualifiers" -/// This page lists the peripheral qualifier values specified in the INQUIRY -/// data -/// \see spc4r06.pdf - Section 6.4.2 - Table 83 -/// \see SBCInquiryData -/// -/// !Qualifiers -/// - SBC_PERIPHERAL_DEVICE_CONNECTED -/// - SBC_PERIPHERAL_DEVICE_NOT_CONNECTED -/// - SBC_PERIPHERAL_DEVICE_NOT_SUPPORTED - -#define SBC_PERIPHERAL_DEVICE_CONNECTED 0x00 -#define SBC_PERIPHERAL_DEVICE_NOT_CONNECTED 0x01 -#define SBC_PERIPHERAL_DEVICE_NOT_SUPPORTED 0x03 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Periph. Types" -/// This page lists peripheral device types specified in the INQUIRY data -/// \see spc4r06.pdf - Section 6.4.2 - Table 84 -/// \see SBCInquiryData -/// -/// !Types -/// - SBC_DIRECT_ACCESS_BLOCK_DEVICE -/// - SBC_SEQUENTIAL_ACCESS_DEVICE -/// - SBC_PRINTER_DEVICE -/// - SBC_PROCESSOR_DEVICE -/// - SBC_WRITE_ONCE_DEVICE -/// - SBC_CD_DVD_DEVICE -/// - SBC_SCANNER_DEVICE -/// - SBC_OPTICAL_MEMORY_DEVICE -/// - SBC_MEDIA_CHANGER_DEVICE -/// - SBC_COMMUNICATION_DEVICE -/// - SBC_STORAGE_ARRAY_CONTROLLER_DEVICE -/// - SBC_ENCLOSURE_SERVICES_DEVICE -/// - SBC_SIMPLIFIED_DIRECT_ACCESS_DEVICE -/// - SBC_OPTICAL_CARD_READER_WRITER_DEVICE -/// - SBC_BRIDGE_CONTROLLER_COMMANDS -/// - SBC_OBJECT_BASED_STORAGE_DEVICE - -#define SBC_DIRECT_ACCESS_BLOCK_DEVICE 0x00 -#define SBC_SEQUENTIAL_ACCESS_DEVICE 0x01 -#define SBC_PRINTER_DEVICE 0x02 -#define SBC_PROCESSOR_DEVICE 0x03 -#define SBC_WRITE_ONCE_DEVICE 0x04 -#define SBC_CD_DVD_DEVICE 0x05 -#define SBC_SCANNER_DEVICE 0x06 -#define SBC_OPTICAL_MEMORY_DEVICE 0x07 -#define SBC_MEDIA_CHANGER_DEVICE 0x08 -#define SBC_COMMUNICATION_DEVICE 0x09 -#define SBC_STORAGE_ARRAY_CONTROLLER_DEVICE 0x0C -#define SBC_ENCLOSURE_SERVICES_DEVICE 0x0D -#define SBC_SIMPLIFIED_DIRECT_ACCESS_DEVICE 0x0E -#define SBC_OPTICAL_CARD_READER_WRITER_DEVICE 0x0F -#define SBC_BRIDGE_CONTROLLER_COMMANDS 0x10 -#define SBC_OBJECT_BASED_STORAGE_DEVICE 0x11 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \brief Version value for the SBC-3 specification -/// \see spc4r06.pdf - Section 6.4.2 - Table 85 -#define SBC_SPC_VERSION_4 0x06 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \brief Values for the TPGS field returned in INQUIRY data -/// \see spc4r06.pdf - Section 6.4.2 - Table 86 -#define SBC_TPGS_NONE 0x0 -#define SBC_TPGS_ASYMMETRIC 0x1 -#define SBC_TPGS_SYMMETRIC 0x2 -#define SBC_TPGS_BOTH 0x3 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \brief Version descriptor value for the SBC-3 specification -/// \see spc4r06.pdf - Section 6.4.2 - Table 87 -#define SBC_VERSION_DESCRIPTOR_SBC_3 0x04C0 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Sense Response Codes" -/// This page lists sense data response codes returned in REQUEST SENSE data -/// \see spc4r06.pdf - Section 4.5.1 - Table 12 -/// -/// !Codes -/// - SBC_SENSE_DATA_FIXED_CURRENT -/// - SBC_SENSE_DATA_FIXED_DEFERRED -/// - SBC_SENSE_DATA_DESCRIPTOR_CURRENT -/// - SBC_SENSE_DATA_DESCRIPTOR_DEFERRED - -#define SBC_SENSE_DATA_FIXED_CURRENT 0x70 -#define SBC_SENSE_DATA_FIXED_DEFERRED 0x71 -#define SBC_SENSE_DATA_DESCRIPTOR_CURRENT 0x72 -#define SBC_SENSE_DATA_DESCRIPTOR_DEFERRED 0x73 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Sense Keys" -/// This page lists sense key values returned in the REQUEST SENSE data -/// \see spc4r06.pdf - Section 4.5.6 - Table 27 -/// -/// !Keys -/// - SBC_SENSE_KEY_NO_SENSE -/// - SBC_SENSE_KEY_RECOVERED_ERROR -/// - SBC_SENSE_KEY_NOT_READY -/// - SBC_SENSE_KEY_MEDIUM_ERROR -/// - SBC_SENSE_KEY_HARDWARE_ERROR -/// - SBC_SENSE_KEY_ILLEGAL_REQUEST -/// - SBC_SENSE_KEY_UNIT_ATTENTION -/// - SBC_SENSE_KEY_DATA_PROTECT -/// - SBC_SENSE_KEY_BLANK_CHECK -/// - SBC_SENSE_KEY_VENDOR_SPECIFIC -/// - SBC_SENSE_KEY_COPY_ABORTED -/// - SBC_SENSE_KEY_ABORTED_COMMAND -/// - SBC_SENSE_KEY_VOLUME_OVERFLOW -/// - SBC_SENSE_KEY_MISCOMPARE - -/// No specific sense key. Successful command. -#define SBC_SENSE_KEY_NO_SENSE 0x00 -/// Command completed succesfully with some recovery action by the %device. -#define SBC_SENSE_KEY_RECOVERED_ERROR 0x01 -/// The device can not be accessed. -#define SBC_SENSE_KEY_NOT_READY 0x02 -/// Command terminated with a error condition that was probably caused by a -/// flaw in the medium or an error in the recorded data. -#define SBC_SENSE_KEY_MEDIUM_ERROR 0x03 -/// Hardware failure while performing the command or during a self test. -#define SBC_SENSE_KEY_HARDWARE_ERROR 0x04 -/// Illegal parameter found in the command or additional parameters. -#define SBC_SENSE_KEY_ILLEGAL_REQUEST 0x05 -/// Removable medium may have been changed or the %device has been reset. -#define SBC_SENSE_KEY_UNIT_ATTENTION 0x06 -/// Write on a block that is protected. -#define SBC_SENSE_KEY_DATA_PROTECT 0x07 -/// Indicates that a write-once device or a sequential-access device -/// encountered blank medium or format-defined end-of-data indication while -/// reading or a write-once device encountered a non-blank medium while writing. -#define SBC_SENSE_KEY_BLANK_CHECK 0x08 -/// Reporting vendor specific conditions. -#define SBC_SENSE_KEY_VENDOR_SPECIFIC 0x09 -/// EXTENDED COPY command was aborted. -#define SBC_SENSE_KEY_COPY_ABORTED 0x0A -/// Device aborted the command. -#define SBC_SENSE_KEY_ABORTED_COMMAND 0x0B -/// A buffered peripheral device is overflow. -#define SBC_SENSE_KEY_VOLUME_OVERFLOW 0x0D -/// The source data did not match the data read from the medium. -#define SBC_SENSE_KEY_MISCOMPARE 0x0E -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Sense Additionals" -/// This page lists additional sense code values returned in REQUEST SENSE data -/// \see spc4r06.pdf - Section 4.5.6 - Table 28 -/// -/// !Additional Codes -/// - SBC_ASC_LOGICAL_UNIT_NOT_READY -/// - SBC_ASC_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE -/// - SBC_ASC_INVALID_FIELD_IN_CDB -/// - SBC_ASC_WRITE_PROTECTED -/// - SBC_ASC_FORMAT_CORRUPTED -/// - SBC_ASC_INVALID_COMMAND_OPERATION_CODE -/// - SBC_ASC_TOO_MUCH_WRITE_DATA -/// - SBC_ASC_NOT_READY_TO_READY_CHANGE -/// - SBC_ASC_MEDIUM_NOT_PRESENT - -#define SBC_ASC_LOGICAL_UNIT_NOT_READY 0x04 -#define SBC_ASC_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE 0x21 -#define SBC_ASC_INVALID_FIELD_IN_CDB 0x24 -#define SBC_ASC_WRITE_PROTECTED 0x27 -#define SBC_ASC_FORMAT_CORRUPTED 0x31 -#define SBC_ASC_INVALID_COMMAND_OPERATION_CODE 0x20 -#define SBC_ASC_TOO_MUCH_WRITE_DATA 0x26 -#define SBC_ASC_NOT_READY_TO_READY_CHANGE 0x28 -#define SBC_ASC_MEDIUM_NOT_PRESENT 0x3A -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \brief MEDIUM TYPE field value for direct-access block devices -/// \see sbc3r06.pdf - Section 6.3.1 -#define SBC_MEDIUM_TYPE_DIRECT_ACCESS_BLOCK_DEVICE 0x00 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \brief MRIE field values -/// \see sbc3r06.pdf - Section 7.4.11 - Table 286 -#define SBC_MRIE_NO_REPORTING 0x00 -#define SBC_MRIE_ASYNCHRONOUS 0x01 -#define SBC_MRIE_GENERATE_UNIT_ATTENTION 0x02 -#define SBC_MRIE_COND_GENERATE_RECOVERED_ERROR 0x03 -#define SBC_MRIE_UNCOND_GENERATE_RECOVERED_ERROR 0x04 -#define SBC_MRIE_GENERATE_NO_SENSE 0x05 -#define SBC_MRIE_ON_REQUEST 0x06 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \brief Supported mode pages -/// \see sbc3r06.pdf - Section 6.3.1 - Table 115 -#define SBC_PAGE_READ_WRITE_ERROR_RECOVERY 0x01 -#define SBC_PAGE_INFORMATIONAL_EXCEPTIONS_CONTROL 0x1C -#define SBC_PAGE_RETURN_ALL 0x3F -#define SBC_PAGE_VENDOR_SPECIFIC 0x00 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Endian Macros" -/// This page lists the macros for endianness conversion. -/// -/// !Macros -/// - WORDB -/// - DWORDB -/// - STORE_DWORDB -/// - STORE_WORDB -/// \brief Converts a byte array to a word value using the big endian format -#define WORDB(bytes) ((unsigned short) ((bytes[0] << 8) | bytes[1])) - -/// \brief Converts a byte array to a dword value using the big endian format -#define DWORDB(bytes) ((unsigned int) ((bytes[0] << 24) | (bytes[1] << 16) \ - | (bytes[2] << 8) | bytes[3])) - -/// \brief Stores a dword value in a byte array, in big endian format -#define STORE_DWORDB(dword, bytes) \ - bytes[0] = (unsigned char) (((dword) >> 24) & 0xFF); \ - bytes[1] = (unsigned char) (((dword) >> 16) & 0xFF); \ - bytes[2] = (unsigned char) (((dword) >> 8) & 0xFF); \ - bytes[3] = (unsigned char) ((dword) & 0xFF); - -/// \brief Stores a word value in a byte array, in big endian format -#define STORE_WORDB(word, bytes) \ - bytes[0] = (unsigned char) (((word) >> 8) & 0xFF); \ - bytes[1] = (unsigned char) ((word) & 0xFF); -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Structures -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -/// \brief Structure for the INQUIRY command -/// \see spc4r06.pdf - Section 6.4.1 - Table 81 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x12 : SBC_INQUIRY - unsigned char isEVPD:1, //!< Type of requested data - bReserved1:7; //!< Reserved bits - unsigned char bPageCode; //!< Specifies the VPD to return - unsigned char pAllocationLength[2]; //!< Size of host buffer - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCInquiry; // GCC - -//------------------------------------------------------------------------------ -/// \brief Standard INQUIRY data format returned by the device -/// \see spc4r06.pdf - Section 6.4.2 - Table 82 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bPeripheralDeviceType:5, //!< Peripheral device type - bPeripheralQualifier :3; //!< Peripheral qualifier - unsigned char bReserved1:7, //!< Reserved bits - isRMB :1; //!< Is media removable ? - unsigned char bVersion; //!< SPC version used - unsigned char bResponseDataFormat:4, //!< Must be 0x2 - isHIGHSUP :1, //!< Hierarchical addressing used ? - isNORMACA :1, //!< ACA attribute supported ? - bObsolete1 :2; //!< Obsolete bits - unsigned char bAdditionalLength; //!< Length of remaining INQUIRY data - unsigned char isSCCS :1, //!< Embedded SCC ? - isACC :1, //!< Access control coordinator ? - bTPGS :2, //!< Target port support group - is3PC :1, //!< Third-party copy supported ? - bReserved2:2, //!< Reserved bits - isProtect :1; //!< Protection info supported ? - unsigned char bObsolete2:1, //!< Obsolete bit - isEncServ :1, //!< Embedded enclosure service comp? - isVS :1, //!< ??? - isMultiP :1, //!< Multi-port device ? - bObsolete3:3, //!< Obsolete bits - bUnused1 :1; //!< Unused feature - unsigned char bUnused2:6, //!< Unused features - isCmdQue:1, //!< Task management model supported ? - isVS2 :1; //!< ??? - unsigned char pVendorID[8]; //!< T10 vendor identification - unsigned char pProductID[16]; //!< Vendor-defined product ID - unsigned char pProductRevisionLevel[4];//!< Vendor-defined product revision - unsigned char pVendorSpecific[20]; //!< Vendor-specific data - unsigned char bUnused3; //!< Unused features - unsigned char bReserved3; //!< Reserved bits - unsigned short pVersionDescriptors[8]; //!< Standards the device complies to - unsigned char pReserved4[22]; //!< Reserved bytes - -} __attribute__ ((packed)) SBCInquiryData; // GCC - -//------------------------------------------------------------------------------ -/// \brief Data structure for the READ (10) command -/// \see sbc3r07.pdf - Section 5.7 - Table 34 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x28 : SBC_READ_10 - unsigned char bObsolete1:1, //!< Obsolete bit - isFUA_NV:1, //!< Cache control bit - bReserved1:1, //!< Reserved bit - isFUA:1, //!< Cache control bit - isDPO:1, //!< Cache control bit - bRdProtect:3; //!< Protection information to send - unsigned char pLogicalBlockAddress[4]; //!< Index of first block to read - unsigned char bGroupNumber:5, //!< Information grouping - bReserved2:3; //!< Reserved bits - unsigned char pTransferLength[2]; //!< Number of blocks to transmit - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCRead10; // GCC - -//------------------------------------------------------------------------------ -/// \brief Structure for the READ CAPACITY (10) command -/// \see sbc3r07.pdf - Section 5.11.1 - Table 40 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x25 : RBC_READ_CAPACITY - unsigned char bObsolete1:1, //!< Obsolete bit - bReserved1:7; //!< Reserved bits - unsigned char pLogicalBlockAddress[4]; //!< Block to evaluate if PMI is set - unsigned char pReserved2[2]; //!< Reserved bytes - unsigned char isPMI:1, //!< Partial medium indicator bit - bReserved3:7; //!< Reserved bits - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCReadCapacity10; - -//------------------------------------------------------------------------------ -/// \brief Data returned by the device after a READ CAPACITY (10) command -/// \see sbc3r07.pdf - Section 5.11.2 - Table 41 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char pLogicalBlockAddress[4]; //!< Address of last logical block - unsigned char pLogicalBlockLength[4]; //!< Length of each logical block - -} __attribute__ ((packed)) SBCReadCapacity10Data; - -//------------------------------------------------------------------------------ -/// \brief Structure for the REQUEST SENSE command -/// \see spc4r06.pdf - Section 6.26 - Table 170 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x03 : SBC_REQUEST_SENSE - unsigned char isDesc :1, //!< Type of information expected - bReserved1:7; //!< Reserved bits - unsigned char pReserved2[2]; //!< Reserved bytes - unsigned char bAllocationLength; //!< Size of host buffer - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCRequestSense; - -//------------------------------------------------------------------------------ -/// \brief Fixed format sense data returned after a REQUEST SENSE command has -/// been received with a DESC bit cleared. -/// \see spc4r06.pdf - Section 4.5.3 - Table 26 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bResponseCode:7, //!< Sense data format - isValid :1; //!< Information field is standard - unsigned char bObsolete1; //!< Obsolete byte - unsigned char bSenseKey :4, //!< Generic error information - bReserved1:1, //!< Reserved bit - isILI :1, //!< SSC - isEOM :1, //!< SSC - isFilemark:1; //!< SSC - unsigned char pInformation[4]; //!< Command-specific - unsigned char bAdditionalSenseLength; //!< sizeof(SBCRequestSense_data)-8 - unsigned char pCommandSpecificInformation[4]; //!< Command-specific - unsigned char bAdditionalSenseCode; //!< Additional error information - unsigned char bAdditionalSenseCodeQualifier; //!< Further error information - unsigned char bFieldReplaceableUnitCode; //!< Specific component code - unsigned char bSenseKeySpecific:7, //!< Additional exception info - isSKSV :1; //!< Is sense key specific valid? - unsigned char pSenseKeySpecific[2]; //!< Additional exception info - -} __attribute__ ((packed)) SBCRequestSenseData; - -//------------------------------------------------------------------------------ -/// \brief Data structure for the TEST UNIT READY command -/// \see spc4r06.pdf - Section 6.34 - Table 192 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x00 : SBC_TEST_UNIT_READY - unsigned char pReserved1[4]; //!< Reserved bits - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCTestUnitReady; // GCC - -//------------------------------------------------------------------------------ -/// \brief Structure for the WRITE (10) command -/// \see sbc3r07.pdf - Section 5.26 - Table 70 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x2A : SBC_WRITE_10 - unsigned char bObsolete1:1, //!< Obsolete bit - isFUA_NV:1, //!< Cache control bit - bReserved1:1, //!< Reserved bit - isFUA:1, //!< Cache control bit - isDPO:1, //!< Cache control bit - bWrProtect:3; //!< Protection information to send - unsigned char pLogicalBlockAddress[4]; //!< First block to write - unsigned char bGroupNumber:5, //!< Information grouping - bReserved2:3; //!< Reserved bits - unsigned char pTransferLength[2]; //!< Number of blocks to write - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCWrite10; - -//------------------------------------------------------------------------------ -/// \brief Structure for the PREVENT/ALLOW MEDIUM REMOVAL command -/// \see sbc3r07.pdf - Section 5.5 - Table 30 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x1E : SBC_PREVENT_ALLOW_MEDIUM_REMOVAL - unsigned char pReserved1[3]; //!< Reserved bytes - unsigned char bPrevent:2, //!< Accept/prohibit removal - bReserved2:6; //!< Reserved bits - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCMediumRemoval; // GCC - -//------------------------------------------------------------------------------ -/// \brief Structure for the MODE SENSE (6) command -/// \see spc4r06 - Section 6.9.1 - Table 98 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x1A : SBC_MODE_SENSE_6 - unsigned char bReserved1:3, //!< Reserved bits - isDBD:1, //!< Disable block descriptors bit - bReserved2:4; //!< Reserved bits - unsigned char bPageCode:6, //!< Mode page to return - bPC:2; //!< Type of parameter values to return - unsigned char bSubpageCode; //!< Mode subpage to return - unsigned char bAllocationLength; //!< Host buffer allocated size - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCModeSense6; // GCC - -//------------------------------------------------------------------------------ -/// \brief Header for the data returned after a MODE SENSE (6) command -/// \see spc4r06.pdf - Section 7.4.3 - Table 268 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bModeDataLength; //!< Length of mode data to follow - unsigned char bMediumType; //!< Type of medium (SBC_MEDIUM_TYPE_DIRECT_ACCESS_BLOCK_DEVICE) - unsigned char bReserved1:4, //!< Reserved bits - isDPOFUA:1, //!< DPO/FUA bits supported ? - bReserved2:2, //!< Reserved bits - isWP:1; //!< Is medium write-protected ? - unsigned char bBlockDescriptorLength; //!< Length of all block descriptors - -} __attribute__ ((packed)) SBCModeParameterHeader6; // GCC - -//------------------------------------------------------------------------------ -/// \brief Informational exceptions control mode page -/// \see spc4r06.pdf - Section 7.4.11 - Table 285 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bPageCode:6, //!< 0x1C : SBC_PAGE_INFORMATIONAL_EXCEPTIONS_CONTROL - isSPF:1, //!< Page or subpage data format - isPS:1; //!< Parameters saveable ? - unsigned char bPageLength; //!< Length of page data (0x0A) - unsigned char isLogErr:1, //!< Should informational exceptions be logged ? - isEBackErr:1, //!< Enable background error bit - isTest:1, //!< Create a device test failure ? - isDExcpt:1, //!< Disable exception control bit - isEWasc:1, //!< Report warnings ? - isEBF:1, //!< Enable background function bit - bReserved1:1, //!< Reserved bit - isPerf:1; //!< Delay acceptable when treating exceptions ? - unsigned char bMRIE:4, //!< Method of reporting informational exceptions - bReserved2:4; //!< Reserved bits - unsigned char pIntervalTimer[4]; //!< Error reporting period - unsigned char pReportCount[4]; //!< Maximum number of time a report can be issued - -} __attribute__ ((packed)) SBCInformationalExceptionsControl; // GCC - -//------------------------------------------------------------------------------ -/// \brief Read/write error recovery mode page -/// \see sbc3r07.pdf - Section 6.3.5 - Table 122 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bPageCode:6, //!< 0x01 : SBC_PAGE_READ_WRITE_ERROR_RECOVERY - isSPF:1, //!< Page or subpage data format - isPS:1; //!< Parameters saveable ? - unsigned char bPageLength; //!< Length of page data (0x0A) - unsigned char isDCR:1, //!< Disable correction bit - isDTE:1, //!< Data terminate on error bit - isPER:1, //!< Post error bit - isEER:1, //!< Enable early recovery bit - isRC:1, //!< Read continuous bit - isTB:1, //!< Transfer block bit - isARRE:1, //!< Automatic read reallocation enabled bit - isAWRE:1; //!< Automatic write reallocation enabled bit - unsigned char bReadRetryCount; //!< Number of retries when reading - unsigned char pObsolete1[3]; //!< Obsolete bytes - unsigned char bReserved1; //!< Reserved byte - unsigned char bWriteRetryCount; //!< Number of retries when writing - unsigned char bReserved2; //!< Reserved byte - unsigned char pRecoveryTimeLimit[2]; //!< Maximum time duration for error recovery - -} __attribute__ ((packed)) SBCReadWriteErrorRecovery; // GCC - -//------------------------------------------------------------------------------ -/// \brief Generic structure for holding information about SBC commands -/// \see SBCInquiry -/// \see SBCRead10 -/// \see SBCReadCapacity10 -/// \see SBCRequestSense -/// \see SBCTestUnitReady -/// \see SBCWrite10 -/// \see SBCMediumRemoval -/// \see SBCModeSense6 -//------------------------------------------------------------------------------ -typedef union { - - unsigned char bOperationCode; //!< Operation code of the command - SBCInquiry inquiry; //!< INQUIRY command - SBCRead10 read10; //!< READ (10) command - SBCReadCapacity10 readCapacity10; //!< READ CAPACITY (10) command - SBCRequestSense requestSense; //!< REQUEST SENSE command - SBCTestUnitReady testUnitReady; //!< TEST UNIT READY command - SBCWrite10 write10; //!< WRITE (10) command - SBCMediumRemoval mediumRemoval; //!< PREVENT/ALLOW MEDIUM REMOVAL command - SBCModeSense6 modeSense6; //!< MODE SENSE (6) command - -} SBCCommand; - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -#endif //#ifndef SBC_H - diff --git a/radio/bootloader/usb/device/massstorage/SBCMethods.c b/radio/bootloader/usb/device/massstorage/SBCMethods.c deleted file mode 100644 index 26c85eedf..000000000 --- a/radio/bootloader/usb/device/massstorage/SBCMethods.c +++ /dev/null @@ -1,1624 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "SBCMethods.h" -#include "MSDDStateMachine.h" -#include - -#include "MSDIOFifo.h" - -//------------------------------------------------------------------------------ -// Global variables -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Macros -//------------------------------------------------------------------------------ - -#ifdef MSDIO_READ10_CHUNK_SIZE -/// READ10 - Read data from specific LUN to FIFO -#define SBC_READ_CHUNK(pLun, lba, pFifo, pCb, pArg) \ - LUN_Read((pLun), (lba), \ - &(pFifo)->pBuffer[(pFifo)->inputNdx], \ - ((pFifo)->chunkSize/(pFifo)->blockSize), \ - (TransferCallback)(pCb), (void*)pArg) -/// READ10 - Transfer data from FIFO to USB -#define SBC_TX_CHUNK(pFifo, pCb, pArg) \ - MSDD_Write(&(pFifo)->pBuffer[(pFifo)->outputNdx], \ - (pFifo)->chunkSize, \ - (TransferCallback)(pCb), (void*)(pArg)) -#endif - -#ifdef MSDIO_WRITE10_CHUNK_SIZE -/// WRITE10 - Read data from USB to FIFO -#define SBC_RX_CHUNK(pFifo,pCb,pArg) \ - MSDD_Read(&(pFifo)->pBuffer[(pFifo)->inputNdx], \ - (pFifo)->chunkSize, \ - (TransferCallback)(pCb), (void*)(pArg)) -/// WRITE10 - Write data from FIFO to LUN -#define SBC_WRITE_CHUNK(pLun, lba, pFifo, pCb, pArg) \ - LUN_Write((pLun), (lba), \ - &(pFifo)->pBuffer[(pFifo)->outputNdx], \ - ((pFifo)->chunkSize/(pFifo)->blockSize), \ - (TransferCallback)(pCb), (void*)(pArg)) -#endif - - -//------------------------------------------------------------------------------ -//! \brief Header for the mode pages data -//! \see SBCModeParameterHeader6 -//------------------------------------------------------------------------------ -static const SBCModeParameterHeader6 modeParameterHeader6 = { - - sizeof(SBCModeParameterHeader6) - 1, //! Length is 0x03 - SBC_MEDIUM_TYPE_DIRECT_ACCESS_BLOCK_DEVICE, //! Direct-access block device - 0, //! Reserved bits - 0, //! DPO/FUA not supported - 0, //! Reserved bits - 0, //! not write-protected - 0 //! No block descriptor -}; - -//------------------------------------------------------------------------------ -// Internal functions -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -//! \brief Check if the LUN is ready. -//! \param lun Pointer to the LUN affected by the command -//! \return 1 if the LUN is ready to be written -//! \see MSDLun -//------------------------------------------------------------------------------ -static unsigned char SBCLunIsReady(MSDLun *lun) -{ - unsigned char lunIsReady = 0; - Media *media = lun->media; - - if (media == 0 || lun->status < LUN_CHANGED) { - TRACE_INFO("SBCLunIsReady: Not Present!\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_NOT_READY, - SBC_ASC_MEDIUM_NOT_PRESENT, - 0); - - } - else if (lun->status < LUN_READY) { - TRACE_INFO("SBCLunIsReady: Changing!\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_UNIT_ATTENTION, - SBC_ASC_NOT_READY_TO_READY_CHANGE, - 0); - lun->status = LUN_READY; - } - else { - - lunIsReady = 1; - } - - return lunIsReady; -} -//------------------------------------------------------------------------------ -//! \brief Check if the LUN can write. -//! \param lun Pointer to the LUN affected by the command -//! \return 1 if the LUN is ready to be written -//! \see MSDLun -//------------------------------------------------------------------------------ -static unsigned char SBCLunCanBeWritten(MSDLun *lun) -{ - unsigned char canBeWritten = 0; - - if (!SBCLunIsReady(lun)) { - - TRACE_WARNING("SBCLunCanBeWritten: Not Ready!\n\r"); - } - else if (lun->protected) { - - TRACE_WARNING("SBCLunCanBeWritten: Protected!\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_DATA_PROTECT, - SBC_ASC_WRITE_PROTECTED, - 0); - } - else { - - canBeWritten = 1; - } - - return canBeWritten; -} - -//------------------------------------------------------------------------------ -//! \brief Performs a WRITE (10) command on the specified LUN. -//! -//! The data to write is first received from the USB host and then -//! actually written on the media. -//! This function operates asynchronously and must be called multiple -//! times to complete. A result code of MSDDriver_STATUS_INCOMPLETE -//! indicates that at least another call of the method is necessary. -//! \param lun Pointer to the LUN affected by the command -//! \param commandState Current state of the command -//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) -//! \see MSDLun -//! \see MSDCommandState -//------------------------------------------------------------------------------ -static unsigned char SBC_Write10(MSDLun *lun, - MSDCommandState *commandState) -{ - unsigned char status; - unsigned char result = MSDD_STATUS_INCOMPLETE; - SBCRead10 *command = (SBCRead10 *) commandState->cbw.pCommand; - MSDTransfer *transfer = &(commandState->transfer); - MSDTransfer *disktransfer = &(commandState->disktransfer); - MSDIOFifo *fifo = &lun->ioFifo; - Media *media = lun->media; - - // Init command state - if (commandState->state == 0) { - - commandState->state = SBC_STATE_WRITE; - - // The command should not be proceeded if READONLY - if (!SBCLunCanBeWritten(lun)) { - - return MSDD_STATUS_RW; - } - else { - - - // Initialize FIFO - fifo->dataTotal = commandState->length; - fifo->blockSize = lun->blockSize * media->blockSize; - #ifdef MSDIO_WRITE10_CHUNK_SIZE - if ( fifo->dataTotal >= 64 * 1024 - && fifo->blockSize < MSDIO_WRITE10_CHUNK_SIZE) - fifo->chunkSize = MSDIO_WRITE10_CHUNK_SIZE; - else - fifo->chunkSize = fifo->blockSize; - #endif - fifo->fullCnt = 0; - fifo->nullCnt = 0; - - // Initialize FIFO output (Disk) - fifo->outputNdx = 0; - fifo->outputTotal = 0; - fifo->outputState = MSDIO_IDLE; - transfer->semaphore = 0; - - // Initialize FIFO input (USB) - fifo->inputNdx = 0; - fifo->inputTotal = 0; - fifo->inputState = MSDIO_START; - disktransfer->semaphore = 0; - } - - } - - if (commandState->length == 0) { - - // Perform the callback! - if (lun->dataMonitor) { - - lun->dataMonitor(0, fifo->dataTotal, fifo->nullCnt, fifo->fullCnt); - } - return MSDD_STATUS_SUCCESS; - } - - // USB receive task - switch(fifo->inputState) { - - //------------------ - case MSDIO_IDLE: - //------------------ - if (fifo->inputTotal < fifo->dataTotal && - fifo->inputTotal - fifo->outputTotal < fifo->bufferSize) { - - fifo->inputState = MSDIO_START; - } - break; - - //------------------ - case MSDIO_START: - //------------------ - // Should not start if there is any disk error - if (fifo->outputState == MSDIO_ERROR) { - - TRACE_INFO_WP("udErr "); - fifo->inputState = MSDIO_ERROR; - break; - } - - // Read one block of data sent by the host - if (media->mappedWR) { - - // Directly read to memory - status = MSDD_Read((void*) - ((media->baseAddress - + (lun->baseAddress - + DWORDB(command->pLogicalBlockAddress) - * lun->blockSize - ) - ) * media->blockSize - ), - fifo->dataTotal, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - } - else { - #ifdef MSDIO_WRITE10_CHUNK_SIZE - status = SBC_RX_CHUNK(fifo, MSDDriver_Callback, transfer); - #else - // Read block to buffer - status = MSDD_Read((void*)&fifo->pBuffer[fifo->inputNdx], - fifo->blockSize, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - #endif - } - - // Check operation result code - if (status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_Write10: Failed to start receiving\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_HARDWARE_ERROR, - 0, - 0); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("uRx "); - - // Prepare next device state - fifo->inputState = MSDIO_WAIT; - } - break; // MSDIO_START - - //------------------ - case MSDIO_WAIT: - //------------------ - TRACE_INFO_WP("uWait "); - - // Check semaphore - if (transfer->semaphore > 0) { - - transfer->semaphore--; - fifo->inputState = MSDIO_NEXT; - } - break; - - //------------------ - case MSDIO_NEXT: - //------------------ - // Check the result code of the read operation - if (transfer->status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_Write10: Failed to received\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_HARDWARE_ERROR, - 0, - 0); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("uNxt "); - - // Mapped read, all data done - if (media->mappedWR) { - - fifo->inputTotal = fifo->dataTotal; - fifo->inputState = MSDIO_IDLE; - } - else { - - // Update input index - #ifdef MSDIO_WRITE10_CHUNK_SIZE - MSDIOFifo_IncNdx(fifo->inputNdx, - fifo->chunkSize, - fifo->bufferSize); - fifo->inputTotal += fifo->chunkSize; - #else - MSDIOFifo_IncNdx(fifo->inputNdx, - fifo->blockSize, - fifo->bufferSize); - fifo->inputTotal += fifo->blockSize; - #endif - - // Start Next block - // - All Data done? - if (fifo->inputTotal >= fifo->dataTotal) { - - fifo->inputState = MSDIO_IDLE; - } - // - Buffer full? - else if (fifo->inputNdx == fifo->outputNdx) { - fifo->inputState = MSDIO_IDLE; - fifo->fullCnt ++; - - TRACE_DEBUG_WP("ufFull%d ", fifo->inputNdx); - } - // - More data to transfer? - else if (fifo->inputTotal < fifo->dataTotal) { - fifo->inputState = MSDIO_START; - - TRACE_INFO_WP("uStart "); - } - // never executed ! - //else { - // fifo->inputState = MSDIO_IDLE; - // TRACE_INFO_WP("uDone "); - //} - } - - } - break; // MSDIO_NEXT - - //------------------ - case MSDIO_ERROR: - //------------------ - - TRACE_WARNING_WP("uErr "); - commandState->length -= fifo->inputTotal; - return MSDD_STATUS_RW; - - } - - // Disk write task - switch(fifo->outputState) { - - //------------------ - case MSDIO_IDLE: - //------------------ - if (fifo->outputTotal < fifo->inputTotal) { - - fifo->outputState = MSDIO_START; - } - break; - - //------------------ - case MSDIO_START: - //------------------ - - // Write the block to the media - if (media->mappedWR) { - - MSDDriver_Callback(disktransfer, MED_STATUS_SUCCESS, 0, 0); - status = LUN_STATUS_SUCCESS; - } - else { - #ifdef MSDIO_WRITE10_CHUNK_SIZE - status = SBC_WRITE_CHUNK(lun, DWORDB(command->pLogicalBlockAddress), - fifo, MSDDriver_Callback, disktransfer); - #else - status = LUN_Write(lun, - DWORDB(command->pLogicalBlockAddress), - &fifo->pBuffer[fifo->outputNdx], - 1, - (TransferCallback) MSDDriver_Callback, - (void *) disktransfer); - #endif - } - - // Check operation result code - if (status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_Write10: Failed to start write - "); - - if (!SBCLunCanBeWritten(lun)) { - - TRACE_WARNING("?\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_NOT_READY, - 0, - 0); - } - - fifo->outputState = MSDIO_ERROR; - } - else { - - // Prepare next state - fifo->outputState = MSDIO_WAIT; - } - break; // MSDIO_START - - //------------------ - case MSDIO_WAIT: - //------------------ - TRACE_INFO_WP("dWait "); - - // Check semaphore value - if (disktransfer->semaphore > 0) { - - // Take semaphore and move to next state - disktransfer->semaphore--; - fifo->outputState = MSDIO_NEXT; - } - break; - - //------------------ - case MSDIO_NEXT: - //------------------ - // Check operation result code - if (transfer->status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_Write10: Failed to write\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_RECOVERED_ERROR, - SBC_ASC_TOO_MUCH_WRITE_DATA, - 0); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("dNxt "); - - // Update transfer length and block address - - // Mapped memory, done - if (media->mappedWR) { - - commandState->length = 0; - fifo->outputState = MSDIO_IDLE; - } - else { - - // Update output index - #ifdef MSDIO_WRITE10_CHUNK_SIZE - STORE_DWORDB(DWORDB(command->pLogicalBlockAddress) - + fifo->chunkSize/fifo->blockSize, - command->pLogicalBlockAddress); - MSDIOFifo_IncNdx(fifo->outputNdx, - fifo->chunkSize, - fifo->bufferSize); - fifo->outputTotal += fifo->chunkSize; - #else - STORE_DWORDB(DWORDB(command->pLogicalBlockAddress) + 1, - command->pLogicalBlockAddress); - MSDIOFifo_IncNdx(fifo->outputNdx, - fifo->blockSize, - fifo->bufferSize); - fifo->outputTotal += fifo->blockSize; - #endif - - // Start Next block - // - All data done? - if (fifo->outputTotal >= fifo->dataTotal) { - - fifo->outputState = MSDIO_IDLE; - commandState->length = 0; - TRACE_INFO_WP("dDone "); - } - // - Send next? - else if (fifo->outputTotal < fifo->inputTotal) { - - fifo->outputState = MSDIO_START; - TRACE_INFO_WP("dStart "); - } - // - Buffer Null? - else { - fifo->outputState = MSDIO_IDLE; - fifo->nullCnt ++; - - TRACE_DEBUG_WP("dfNull%d ", fifo->outputNdx); - } - } - } - break; // MSDIO_NEXT - - //------------------ - case MSDIO_ERROR: - //------------------ - break; - } - - return result; -} - -//------------------------------------------------------------------------------ -//! \brief Performs a READ (10) command on specified LUN. -//! -//! The data is first read from the media and then sent to the USB host. -//! This function operates asynchronously and must be called multiple -//! times to complete. A result code of MSDDriver_STATUS_INCOMPLETE -//! indicates that at least another call of the method is necessary. -//! \param lun Pointer to the LUN affected by the command -//! \param commandState Current state of the command -//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) -//! \see MSDLun -//! \see MSDCommandState -//------------------------------------------------------------------------------ -static unsigned char SBC_Read10(MSDLun *lun, - MSDCommandState *commandState) -{ - unsigned char status; - unsigned char result = MSDD_STATUS_INCOMPLETE; - SBCRead10 *command = (SBCRead10 *) commandState->cbw.pCommand; - MSDTransfer *transfer = &(commandState->transfer); - MSDTransfer *disktransfer = &(commandState->disktransfer); - MSDIOFifo *fifo = &lun->ioFifo; - Media *media = lun->media; - - // Init command state - if (commandState->state == 0) { - - commandState->state = SBC_STATE_READ; - - if (!SBCLunIsReady(lun)) { - - return MSDD_STATUS_RW; - } - else { - - // Initialize FIFO - fifo->dataTotal = commandState->length; - fifo->blockSize = lun->blockSize * media->blockSize; - #ifdef MSDIO_READ10_CHUNK_SIZE - if ( fifo->dataTotal >= 64*1024 - && fifo->blockSize < MSDIO_READ10_CHUNK_SIZE) - fifo->chunkSize = MSDIO_READ10_CHUNK_SIZE; - else - fifo->chunkSize = fifo->blockSize; - #endif - fifo->fullCnt = 0; - fifo->nullCnt = 0; - - #ifdef MSDIO_FIFO_OFFSET - // Enable offset if total size >= 2*bufferSize - if (fifo->dataTotal / fifo->bufferSize >= 2) - fifo->bufferOffset = MSDIO_FIFO_OFFSET; - else - fifo->bufferOffset = 0; - #endif - - // Initialize FIFO output (USB) - fifo->outputNdx = 0; - fifo->outputTotal = 0; - fifo->outputState = MSDIO_IDLE; - transfer->semaphore = 0; - - // Initialize FIFO input (Disk) - fifo->inputNdx = 0; - fifo->inputTotal = 0; - fifo->inputState = MSDIO_START; - disktransfer->semaphore = 0; - } - } - - // Check length - if (commandState->length == 0) { - - // Perform the callback! - if (lun->dataMonitor) { - - lun->dataMonitor(1, fifo->dataTotal, fifo->nullCnt, fifo->fullCnt); - } - return MSDD_STATUS_SUCCESS; - } - - // Disk reading task - switch(fifo->inputState) { - - //------------------ - case MSDIO_IDLE: - //------------------ - if (fifo->inputTotal < fifo->dataTotal && - fifo->inputTotal - fifo->outputTotal < fifo->bufferSize) { - - fifo->inputState = MSDIO_START; - } - break; - - //------------------ - case MSDIO_START: - //------------------ - // Read one block of data from the media - if (media->mappedRD) { - - // Directly write, no read needed - MSDDriver_Callback(disktransfer, MED_STATUS_SUCCESS, 0, 0); - status = LUN_STATUS_SUCCESS; - } - else { - #ifdef MSDIO_READ10_CHUNK_SIZE - status = SBC_READ_CHUNK(lun, DWORDB(command->pLogicalBlockAddress), - fifo, MSDDriver_Callback, disktransfer); - #else - status = LUN_Read(lun, - DWORDB(command->pLogicalBlockAddress), - &fifo->pBuffer[fifo->inputNdx], - 1, - (TransferCallback) MSDDriver_Callback, - (void *)disktransfer); - #endif - } - - // Check operation result code - if (status != LUN_STATUS_SUCCESS) { - - TRACE_WARNING("RBC_Read10: Failed to start reading\n\r"); - - if (SBCLunIsReady(lun)) { - - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_NOT_READY, - SBC_ASC_LOGICAL_UNIT_NOT_READY, - 0); - } - - fifo->inputState = MSDIO_ERROR; - } - else { - - TRACE_INFO_WP("dRd "); - - // Move to next command state - fifo->inputState = MSDIO_WAIT; - } - break; // MSDIO_START - - //------------------ - case MSDIO_WAIT: - //------------------ - // Check semaphore value - if (disktransfer->semaphore > 0) { - - TRACE_INFO_WP("dOk "); - - // Take semaphore and move to next state - disktransfer->semaphore--; - fifo->inputState = MSDIO_NEXT; - } - break; - - //------------------ - case MSDIO_NEXT: - //------------------ - // Check the operation result code - if (disktransfer->status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_Read10: Failed to read media\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_RECOVERED_ERROR, - SBC_ASC_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, - 0); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("dNxt "); - - if (media->mappedRD) { - - // All data is ready - fifo->inputState = MSDIO_IDLE; - fifo->inputTotal = fifo->dataTotal; - } - else { - - // Update block address - #ifdef MSDIO_READ10_CHUNK_SIZE - STORE_DWORDB(DWORDB(command->pLogicalBlockAddress) - + fifo->chunkSize/fifo->blockSize, - command->pLogicalBlockAddress); - - // Update input index - MSDIOFifo_IncNdx(fifo->inputNdx, - fifo->chunkSize, - fifo->bufferSize); - fifo->inputTotal += fifo->chunkSize; - #else - // Update block address - STORE_DWORDB(DWORDB(command->pLogicalBlockAddress) + 1, - command->pLogicalBlockAddress); - - // Update input index - MSDIOFifo_IncNdx(fifo->inputNdx, - fifo->blockSize, - fifo->bufferSize); - fifo->inputTotal += fifo->blockSize; - #endif - - // Start Next block - // - All Data done? - if (fifo->inputTotal >= fifo->dataTotal) { - - TRACE_INFO_WP("dDone "); - fifo->inputState = MSDIO_IDLE; - } - // - Buffer full? - else if (fifo->inputNdx == fifo->outputNdx) { - - TRACE_INFO_WP("dfFull%d ", (int)fifo->inputNdx); - fifo->inputState = MSDIO_IDLE; - fifo->fullCnt ++; - } - // - More data to transfer? - else if (fifo->inputTotal < fifo->dataTotal) { - - TRACE_DEBUG_WP("dStart "); - fifo->inputState = MSDIO_START; - } - } - - } - - break; - - //------------------ - case MSDIO_ERROR: - //------------------ - break; - } - - // USB sending task - switch(fifo->outputState) { - - //------------------ - case MSDIO_IDLE: - //------------------ - if (fifo->outputTotal < fifo->inputTotal) { - - #ifdef MSDIO_FIFO_OFFSET - // Offset buffer the input data - if (fifo->bufferOffset) { - if (fifo->inputTotal < fifo->bufferOffset) { - break; - } - fifo->bufferOffset = 0; - } - #endif - fifo->outputState = MSDIO_START; - } - break; - - //------------------ - case MSDIO_START: - //------------------ - // Should not start if there is any disk error - if (fifo->outputState == MSDIO_ERROR) { - - fifo->inputState = MSDIO_ERROR; - break; - } - - // Send the block to the host - if (media->mappedRD) { - - status = MSDD_Write((void*) - ((media->baseAddress - + (lun->baseAddress - + DWORDB(command->pLogicalBlockAddress) - * lun->blockSize - ) - ) * media->blockSize - ), - commandState->length, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - } - else { - #ifdef MSDIO_READ10_CHUNK_SIZE - status = SBC_TX_CHUNK(fifo, MSDDriver_Callback, transfer); - #else - status = MSDD_Write(&fifo->pBuffer[fifo->outputNdx], - fifo->blockSize, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - #endif - } - // Check operation result code - if (status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_Read10: Failed to start to send\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_HARDWARE_ERROR, - 0, - 0); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("uTx "); - - // Move to next command state - fifo->outputState = MSDIO_WAIT; - } - break; // MSDIO_START - - //------------------ - case MSDIO_WAIT: - //------------------ - // Check semaphore value - if (transfer->semaphore > 0) { - - TRACE_INFO_WP("uOk "); - - // Take semaphore and move to next state - transfer->semaphore--; - fifo->outputState = MSDIO_NEXT; - } - break; - - //------------------ - case MSDIO_NEXT: - //------------------ - // Check operation result code - if (transfer->status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_Read10: Failed to send data\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_HARDWARE_ERROR, - 0, - 0); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("uNxt "); - - if (media->mappedRD) { - - commandState->length = 0; - } - else { - - // Update output index - #ifdef MSDIO_READ10_CHUNK_SIZE - MSDIOFifo_IncNdx(fifo->outputNdx, - fifo->chunkSize, - fifo->bufferSize); - fifo->outputTotal += fifo->chunkSize; - #else - MSDIOFifo_IncNdx(fifo->outputNdx, - fifo->blockSize, - fifo->bufferSize); - fifo->outputTotal += fifo->blockSize; - #endif - - // Start Next block - // - All data done? - if (fifo->outputTotal >= fifo->dataTotal) { - - fifo->outputState = MSDIO_IDLE; - commandState->length = 0; - TRACE_INFO_WP("uDone "); - } - // - Buffer Null? - else if (fifo->inputNdx == fifo->outputNdx) { - - TRACE_INFO_WP("ufNull%d ", (int)fifo->outputNdx); - fifo->outputState = MSDIO_IDLE; - fifo->nullCnt ++; - } - // - Send next? - else if (fifo->outputTotal < fifo->inputTotal) { - - TRACE_DEBUG_WP("uStart "); - fifo->outputState = MSDIO_START; - } - } - - } - break; - - //------------------ - case MSDIO_ERROR: - //------------------ - break; - } - - return result; -} - -//------------------------------------------------------------------------------ -//! \brief Performs a READ CAPACITY (10) command. -//! -//! This function operates asynchronously and must be called multiple -//! times to complete. A result code of MSDD_STATUS_INCOMPLETE -//! indicates that at least another call of the method is necessary. -//! \param lun Pointer to the LUN affected by the command -//! \param commandState Current state of the command -//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) -//! \see MSDLun -//! \see MSDCommandState -//------------------------------------------------------------------------------ -static unsigned char SBC_ReadCapacity10(MSDLun *lun, - MSDCommandState *commandState) -{ - unsigned char result = MSDD_STATUS_INCOMPLETE; - unsigned char status; - MSDTransfer *transfer = &(commandState->transfer); - - if (!SBCLunIsReady(lun)) { - - TRACE_INFO("SBC_ReadCapacity10: Not Ready!\n\r"); - return MSDD_STATUS_RW; - } - - // Initialize command state if needed - if (commandState->state == 0) { - - commandState->state = SBC_STATE_WRITE; - } - - // Identify current command state - switch (commandState->state) { - //------------------- - case SBC_STATE_WRITE: - //------------------- - // Start the write operation - status = MSDD_Write(&(lun->readCapacityData), - commandState->length, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - - // Check operation result code - if (status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_ReadCapacity: Cannot start sending data\n\r"); - result = MSDD_STATUS_ERROR; - } - else { - - // Proceed to next command state - TRACE_INFO_WP("Sending "); - commandState->state = SBC_STATE_WAIT_WRITE; - } - break; - - //------------------------ - case SBC_STATE_WAIT_WRITE: - //------------------------ - // Check semaphore value - if (transfer->semaphore > 0) { - - // Take semaphore and terminate command - transfer->semaphore--; - - if (transfer->status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING("RBC_ReadCapacity: Cannot send data\n\r"); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("Sent "); - result = MSDD_STATUS_SUCCESS; - } - commandState->length -= transfer->transferred; - } - break; - } - - return result; -} - -//------------------------------------------------------------------------------ -//! \brief Handles an INQUIRY command. -//! -//! This function operates asynchronously and must be called multiple -//! times to complete. A result code of MSDDriver_STATUS_INCOMPLETE -//! indicates that at least another call of the method is necessary. -//! \param lun Pointer to the LUN affected by the command -//! \param commandState Current state of the command -//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) -//! \see MSDLun -//! \see MSDCommandState -//------------------------------------------------------------------------------ -static unsigned char SBC_Inquiry(MSDLun *lun, - MSDCommandState *commandState) -{ - unsigned char result = MSDD_STATUS_INCOMPLETE; - unsigned char status; - MSDTransfer *transfer = &(commandState->transfer); - - // Check if required length is 0 - if (commandState->length == 0) { - - // Nothing to do - result = MSDD_STATUS_SUCCESS; - } - // Initialize command state if needed - else if (commandState->state == 0) { - - commandState->state = SBC_STATE_WRITE; - - // Change additional length field of inquiry data - lun->inquiryData->bAdditionalLength - = (unsigned char) (commandState->length - 5); - } - - // Identify current command state - switch (commandState->state) { - //------------------- - case SBC_STATE_WRITE: - //------------------- - // Start write operation - status = MSDD_Write((void *) lun->inquiryData, - commandState->length, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - - // Check operation result code - if (status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "SPC_Inquiry: Cannot start sending data\n\r"); - result = MSDD_STATUS_ERROR; - } - else { - - // Proceed to next state - TRACE_INFO_WP("Sending "); - commandState->state = SBC_STATE_WAIT_WRITE; - } - break; - - //------------------------ - case SBC_STATE_WAIT_WRITE: - //------------------------ - // Check the semaphore value - if (transfer->semaphore > 0) { - - // Take semaphore and terminate command - transfer->semaphore--; - - if (transfer->status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "SPC_Inquiry: Data transfer failed\n\r"); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("Sent "); - result = MSDD_STATUS_SUCCESS; - } - - // Update length field - commandState->length -= transfer->transferred; - } - break; - } - - return result; -} - -//------------------------------------------------------------------------------ -//! \brief Performs a REQUEST SENSE command. -//! -//! This function operates asynchronously and must be called multiple -//! times to complete. A result code of MSDDriver_STATUS_INCOMPLETE -//! indicates that at least another call of the method is necessary. -//! \param lun Pointer to the LUN affected by the command -//! \param commandState Current state of the command -//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) -//! \see MSDLun -//! \see MSDCommandState -//------------------------------------------------------------------------------ -static unsigned char SBC_RequestSense(MSDLun *lun, - MSDCommandState *commandState) -{ - unsigned char result = MSDD_STATUS_INCOMPLETE; - unsigned char status; - MSDTransfer *transfer = &(commandState->transfer); - - // Check if requested length is zero - if (commandState->length == 0) { - - // Nothing to do - result = MSDD_STATUS_SUCCESS; - } - // Initialize command state if needed - else if (commandState->state == 0) { - - commandState->state = SBC_STATE_WRITE; - } - - // Identify current command state - switch (commandState->state) { - //------------------- - case SBC_STATE_WRITE: - //------------------- - // Start transfer - status = MSDD_Write(&(lun->requestSenseData), - commandState->length, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - - // Check result code - if (status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_RequestSense: Cannot start sending data\n\r"); - result = MSDD_STATUS_ERROR; - } - else { - - // Change state - commandState->state = SBC_STATE_WAIT_WRITE; - } - break; - - //------------------------ - case SBC_STATE_WAIT_WRITE: - //------------------------ - // Check the transfer semaphore - if (transfer->semaphore > 0) { - - // Take semaphore and finish command - transfer->semaphore--; - - if (transfer->status != USBD_STATUS_SUCCESS) { - - result = MSDD_STATUS_ERROR; - } - else { - - result = MSDD_STATUS_SUCCESS; - } - - // Update length - commandState->length -= transfer->transferred; - } - break; - } - - return result; -} - -//------------------------------------------------------------------------------ -//! \brief Performs a MODE SENSE (6) command. -//! -//! This function operates asynchronously and must be called multiple -//! times to complete. A result code of MSDDriver_STATUS_INCOMPLETE -//! indicates that at least another call of the method is necessary. -//! \param lun Pointer to the LUN affected by the command -//! \param commandState Current state of the command -//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) -//! \see MSDLun -//! \see MSDCommandState -//------------------------------------------------------------------------------ -static unsigned char SBC_ModeSense6(MSDLun *lun, MSDCommandState *commandState) -{ - unsigned char result = MSDD_STATUS_INCOMPLETE; - unsigned char status; - MSDTransfer *transfer = &(commandState->transfer); - - if (!SBCLunIsReady(lun)) { - - TRACE_INFO("SBC_ModeSense6: Not Ready!\n\r"); - return MSDD_STATUS_RW; - } - - // Check if mode page is supported - if (((SBCCommand *) commandState->cbw.pCommand)->modeSense6.bPageCode - != SBC_PAGE_RETURN_ALL) { - - return MSDD_STATUS_PARAMETER; - } - - // Initialize command state if needed - if (commandState->state == 0) { - - commandState->state = SBC_STATE_WRITE; - } - - // Check current command state - switch (commandState->state) { - //------------------- - case SBC_STATE_WRITE: - //------------------- - // Start transfer - status = MSDD_Write((void *) &modeParameterHeader6, - commandState->length, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - - // Check operation result code - if (status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "SPC_ModeSense6: Cannot start data transfer\n\r"); - result = MSDD_STATUS_ERROR; - } - else { - - // Proceed to next state - commandState->state = SBC_STATE_WAIT_WRITE; - } - break; - - //------------------------ - case SBC_STATE_WAIT_WRITE: - //------------------------ - TRACE_INFO_WP("Wait "); - - // Check semaphore value - if (transfer->semaphore > 0) { - - // Take semaphore and terminate command - transfer->semaphore--; - - if (transfer->status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "SPC_ModeSense6: Data transfer failed\n\r"); - result = MSDD_STATUS_ERROR; - } - else { - - result = MSDD_STATUS_SUCCESS; - } - - // Update length field - commandState->length -= transfer->transferred; - - } - break; - } - - return result; -} - -//------------------------------------------------------------------------------ -//! \brief Performs a TEST UNIT READY COMMAND command. -//! \param lun Pointer to the LUN affected by the command -//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) -//! \see MSDLun -//------------------------------------------------------------------------------ -static unsigned char SBC_TestUnitReady(MSDLun *lun) -{ - unsigned char result = MSDD_STATUS_RW; - unsigned char senseKey = SBC_SENSE_KEY_NO_SENSE, - addSenseCode = 0, - addSenseCodeQual = 0; - Media *media = lun->media; - - // Check current media state - if (lun->status < LUN_CHANGED) { - - TRACE_INFO_WP("Ejc "); - senseKey = SBC_SENSE_KEY_NOT_READY; - addSenseCode = SBC_ASC_MEDIUM_NOT_PRESENT; - } - else if (lun->status == LUN_CHANGED) { - - TRACE_INFO_WP("Chg "); - senseKey = SBC_SENSE_KEY_UNIT_ATTENTION; - addSenseCode = SBC_ASC_NOT_READY_TO_READY_CHANGE; - lun->status = LUN_READY; - } - else { - - switch(media->state) { - //------------------- - case MED_STATE_READY: - //------------------- - // Nothing to do - TRACE_INFO_WP("Rdy "); - result = MSDD_STATUS_SUCCESS; - break; - - //------------------ - case MED_STATE_BUSY: - //------------------ - TRACE_INFO_WP("Bsy "); - senseKey = SBC_SENSE_KEY_NOT_READY; - break; - - //------ - default: - //------ - TRACE_INFO_WP("? "); - senseKey = SBC_SENSE_KEY_NOT_READY; - addSenseCode = SBC_ASC_MEDIUM_NOT_PRESENT; - break; - } - } - SBC_UpdateSenseData(&(lun->requestSenseData), - senseKey, - addSenseCode, - addSenseCodeQual); - - return result; -} - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -//------------------------------------------------------------------------------ -//! \brief Updates the sense data of a LUN with the given key and codes -//! \param requestSenseData Pointer to the sense data to update -//! \param senseKey Sense key -//! \param additionalSenseCode Additional sense code -//! \param additionalSenseCodeQualifier Additional sense code qualifier -//------------------------------------------------------------------------------ -void SBC_UpdateSenseData(SBCRequestSenseData *requestSenseData, - unsigned char senseKey, - unsigned char additionalSenseCode, - unsigned char additionalSenseCodeQualifier) -{ - requestSenseData->bSenseKey = senseKey; - requestSenseData->bAdditionalSenseCode = additionalSenseCode; - requestSenseData->bAdditionalSenseCodeQualifier - = additionalSenseCodeQualifier; -} - -//------------------------------------------------------------------------------ -//! \brief Return information about the transfer length and direction expected -//! by the device for a particular command. -//! \param command Pointer to a buffer holding the command to evaluate -//! \param length Expected length of the data transfer -//! \param type Expected direction of data transfer -//! \param lun Pointer to the LUN affected by the command -//------------------------------------------------------------------------------ -unsigned char SBC_GetCommandInformation(void *command, - unsigned int *length, - unsigned char *type, - MSDLun *lun) -{ - SBCCommand *sbcCommand = (SBCCommand *) command; - unsigned char isCommandSupported = 1; - Media *media = lun->media; - - // Identify command - switch (sbcCommand->bOperationCode) { - //--------------- - case SBC_INQUIRY: - //--------------- - (*type) = MSDD_DEVICE_TO_HOST; - - // Allocation length is stored in big-endian format - (*length) = WORDB(sbcCommand->inquiry.pAllocationLength); - break; - - //-------------------- - case SBC_MODE_SENSE_6: - //-------------------- - (*type) = MSDD_DEVICE_TO_HOST; - if (sbcCommand->modeSense6.bAllocationLength > - sizeof(SBCModeParameterHeader6)) { - - *length = sizeof(SBCModeParameterHeader6); - } - else { - - *length = sbcCommand->modeSense6.bAllocationLength; - } - break; - - //------------------------------------ - case SBC_PREVENT_ALLOW_MEDIUM_REMOVAL: - case 0x1B: - //------------------------------------ - (*type) = MSDD_NO_TRANSFER; - break; - - //--------------------- - case SBC_REQUEST_SENSE: - //--------------------- - (*type) = MSDD_DEVICE_TO_HOST; - (*length) = sbcCommand->requestSense.bAllocationLength; - break; - - //----------------------- - case SBC_TEST_UNIT_READY: - //----------------------- - (*type) = MSDD_NO_TRANSFER; - break; - - //--------------------- - case SBC_READ_CAPACITY_10: - //--------------------- - (*type) = MSDD_DEVICE_TO_HOST; - (*length) = sizeof(SBCReadCapacity10Data); - break; - - //--------------- - case SBC_READ_10: - //--------------- - (*type) = MSDD_DEVICE_TO_HOST; - (*length) = WORDB(sbcCommand->read10.pTransferLength) - * lun->blockSize * media->blockSize; - break; - - //---------------- - case SBC_WRITE_10: - //---------------- - (*type) = MSDD_HOST_TO_DEVICE; - (*length) = WORDB(sbcCommand->write10.pTransferLength) - * lun->blockSize * media->blockSize; - break; - - //----------------- - case SBC_VERIFY_10: - //----------------- - (*type) = MSDD_NO_TRANSFER; - break; - #if 0 - //--------------------- - case SBC_READ_FORMAT_CAPACITIES: - //--------------------- - (*type) = MSDD_DEVICE_TO_HOST; - (*length) = 1; - break; - #endif - //------ - default: - //------ - isCommandSupported = 0; - } - - // If length is 0, no transfer is expected - if ((*length) == 0) { - - (*type) = MSDD_NO_TRANSFER; - } - - return isCommandSupported; -} - -//------------------------------------------------------------------------------ -//! \brief Processes a SBC command by dispatching it to a subfunction. -//! \param lun Pointer to the affected LUN -//! \param commandState Pointer to the current command state -//! \return Operation result code -//------------------------------------------------------------------------------ -unsigned char SBC_ProcessCommand(MSDLun *lun, - MSDCommandState *commandState) -{ - unsigned char result = MSDD_STATUS_INCOMPLETE; - SBCCommand *command = (SBCCommand *) commandState->cbw.pCommand; - Media *media = lun->media; - - // Identify command - switch (command->bOperationCode) { - //--------------- - case SBC_READ_10: - //--------------- - TRACE_DEBUG_WP("Read(10) "); - - // Perform the Read10 command - result = SBC_Read10(lun, commandState); - break; - - //---------------- - case SBC_WRITE_10: - //---------------- - TRACE_DEBUG_WP("Write(10) "); - - // Perform the Write10 command - result = SBC_Write10(lun, commandState); - break; - - //--------------------- - case SBC_READ_CAPACITY_10: - //--------------------- - TRACE_INFO_WP("RdCapacity(10) "); - - // Perform the ReadCapacity command - result = SBC_ReadCapacity10(lun, commandState); - break; - - //--------------------- - case SBC_VERIFY_10: - //--------------------- - TRACE_INFO_WP("Verify(10) "); - - // Flush media - MED_Flush(media); - result = MSDD_STATUS_SUCCESS; - break; - - //--------------- - case SBC_INQUIRY: - //--------------- - TRACE_INFO_WP("Inquiry "); - - // Process Inquiry command - result = SBC_Inquiry(lun, commandState); - break; - - //-------------------- - case SBC_MODE_SENSE_6: - //-------------------- - TRACE_INFO_WP("ModeSense(6) "); - - // Process ModeSense6 command - result = SBC_ModeSense6(lun, commandState); - break; - - //----------------------- - case SBC_TEST_UNIT_READY: - //----------------------- - TRACE_INFO_WP("TstUnitRdy "); - - // Process TestUnitReady command - //MED_Flush(media); - result = SBC_TestUnitReady(lun); - break; - - //--------------------- - case SBC_REQUEST_SENSE: - //--------------------- - TRACE_INFO_WP("ReqSense "); - - // Perform the RequestSense command - result = SBC_RequestSense(lun, commandState); - break; - - //------------------------------------ - case SBC_PREVENT_ALLOW_MEDIUM_REMOVAL: - case 0x1B: - //------------------------------------ - TRACE_INFO_WP("PrevAllowRem "); - - // Check parameter - result = command->mediumRemoval.bPrevent ? - MSDD_STATUS_PARAMETER : MSDD_STATUS_SUCCESS; - result = MSDD_STATUS_SUCCESS; - break; - - #if 0 - //------------------------------------ - case SBC_READ_FORMAT_CAPACITIES: - //------------------------------------ - TRACE_INFO_WP("RdFmtCap "); - result = MSDD_STATUS_RW; - break; - /* TODO BSS Added if (!SBCLunIsReady(lun)) { - - result = MSDD_STATUS_RW; - break; - } */ - #endif - //------ - default: - //------ - result = MSDD_STATUS_PARAMETER; - } - - return result; -} diff --git a/radio/bootloader/usb/device/massstorage/SBCMethods.h b/radio/bootloader/usb/device/massstorage/SBCMethods.h deleted file mode 100644 index 7ba794e67..000000000 --- a/radio/bootloader/usb/device/massstorage/SBCMethods.h +++ /dev/null @@ -1,111 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// SCSI commands implementation. -/// -/// !Usage -/// -/// -# After a CBW is received from host, use SBC_GetCommandInformation to check -/// if the command is supported, and get the command length and type -/// information before processing it. -/// -# Then SBC_ProcessCommand can be used to handle a valid command, to -/// perform the command operations. -/// -# SBC_UpdateSenseData is used to update the sense data that will be sent -/// to host. -//------------------------------------------------------------------------------ - -#ifndef SBCMETHODS_H -#define SBCMETHODS_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "SBC.h" -// #include -#include "MSDDStateMachine.h" - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Command States" -/// This page lists the possible states of a SBC command. -/// -/// !States -/// - SBC_STATE_READ -/// - SBC_STATE_WAIT_READ -/// - SBC_STATE_WRITE -/// - SBC_STATE_WAIT_WRITE -/// - SBC_STATE_NEXT_BLOCK - -/// Start of reading bulk data -#define SBC_STATE_READ 0x01 -/// Waiting for the bulk data reading complete -#define SBC_STATE_WAIT_READ 0x02 -/// Read error state -#define SBC_STATE_READ_ERROR 0x03 -/// Start next read block -#define SBC_STATE_NEXT_READ 0x04 -/// Start writing bulk data to host -#define SBC_STATE_WRITE 0x05 -/// Waiting for the bulk data sending complete -#define SBC_STATE_WAIT_WRITE 0x06 -/// Write error state -#define SBC_STATE_WRITE_ERROR 0x07 -/// Start next write block -#define SBC_STATE_NEXT_WRITE 0x08 -/// Start next command block -#define SBC_STATE_NEXT_BLOCK 0x09 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -void SBC_UpdateSenseData(SBCRequestSenseData *requestSenseData, - unsigned char senseKey, - unsigned char additionalSenseCode, - unsigned char additionalSenseCodeQualifier); - -unsigned char SBC_GetCommandInformation(void *command, - unsigned int *length, - unsigned char *type, - MSDLun *lun); - -unsigned char SBC_ProcessCommand(MSDLun *lun, - MSDCommandState *commandState); - -#endif //#ifndef SBCMETHODS_H - From e7c08e56b2d50c8419d91bcbd760a7beafb1c854 Mon Sep 17 00:00:00 2001 From: bsongis Date: Tue, 4 Mar 2014 11:23:33 +0100 Subject: [PATCH 016/285] Sky9x files removed for now --- companion/src/eeprominterface.h | 22 + .../common/core/USBConfigurationDescriptor.c | 162 -- .../common/core/USBConfigurationDescriptor.h | 150 -- .../usb/common/core/USBDeviceDescriptor.h | 125 -- .../core/USBDeviceQualifierDescriptor.h | 89 - .../usb/common/core/USBEndpointDescriptor.c | 109 -- .../usb/common/core/USBEndpointDescriptor.h | 224 --- .../usb/common/core/USBFeatureRequest.c | 70 - .../usb/common/core/USBFeatureRequest.h | 146 -- .../usb/common/core/USBGenericDescriptor.c | 80 - .../usb/common/core/USBGenericDescriptor.h | 133 -- .../usb/common/core/USBGenericRequest.c | 138 -- .../usb/common/core/USBGenericRequest.h | 244 --- .../usb/common/core/USBGetDescriptorRequest.c | 72 - .../usb/common/core/USBGetDescriptorRequest.h | 67 - .../core/USBInterfaceAssociationDescriptor.h | 86 - .../usb/common/core/USBInterfaceDescriptor.h | 87 - .../usb/common/core/USBInterfaceRequest.c | 69 - .../usb/common/core/USBInterfaceRequest.h | 68 - .../usb/common/core/USBIrqHandler.c | 62 - .../usb/common/core/USBIrqHandler.h | 52 - .../usb/common/core/USBSetAddressRequest.c | 56 - .../usb/common/core/USBSetAddressRequest.h | 60 - .../common/core/USBSetConfigurationRequest.c | 58 - .../common/core/USBSetConfigurationRequest.h | 61 - .../usb/common/core/USBStringDescriptor.h | 74 - .../common/massstorage/MSDeviceDescriptor.h | 73 - .../massstorage/MSInterfaceDescriptor.h | 75 - radio/bootloader/usb/device/core/USBD.h | 275 --- .../usb/device/core/USBDCallbacks.c | 81 - .../usb/device/core/USBDCallbacks.h | 65 - radio/bootloader/usb/device/core/USBDDriver.c | 753 ------- radio/bootloader/usb/device/core/USBDDriver.h | 101 - .../usb/device/core/USBDDriverCallbacks.h | 61 - .../usb/device/core/USBDDriverDescriptors.h | 86 - radio/bootloader/usb/device/core/USBD_UDP.c | 1734 ----------------- radio/bootloader/usb/device/massstorage/MSD.h | 233 --- .../usb/device/massstorage/MSDDStateMachine.c | 609 ------ .../usb/device/massstorage/MSDDStateMachine.h | 264 --- .../usb/device/massstorage/MSDDriver.c | 343 ---- .../usb/device/massstorage/MSDDriver.h | 75 - .../device/massstorage/MSDDriverDescriptors.c | 395 ---- .../device/massstorage/MSDDriverDescriptors.h | 83 - .../usb/device/massstorage/MSDIOFifo.h | 135 -- .../usb/device/massstorage/MSDLun.c | 368 ---- .../usb/device/massstorage/MSDLun.h | 161 -- radio/bootloader/usb/device/massstorage/SBC.h | 653 ------- .../usb/device/massstorage/SBCMethods.c | 1624 --------------- .../usb/device/massstorage/SBCMethods.h | 111 -- 49 files changed, 22 insertions(+), 10900 deletions(-) delete mode 100644 radio/bootloader/usb/common/core/USBConfigurationDescriptor.c delete mode 100644 radio/bootloader/usb/common/core/USBConfigurationDescriptor.h delete mode 100644 radio/bootloader/usb/common/core/USBDeviceDescriptor.h delete mode 100644 radio/bootloader/usb/common/core/USBDeviceQualifierDescriptor.h delete mode 100644 radio/bootloader/usb/common/core/USBEndpointDescriptor.c delete mode 100644 radio/bootloader/usb/common/core/USBEndpointDescriptor.h delete mode 100644 radio/bootloader/usb/common/core/USBFeatureRequest.c delete mode 100644 radio/bootloader/usb/common/core/USBFeatureRequest.h delete mode 100644 radio/bootloader/usb/common/core/USBGenericDescriptor.c delete mode 100644 radio/bootloader/usb/common/core/USBGenericDescriptor.h delete mode 100644 radio/bootloader/usb/common/core/USBGenericRequest.c delete mode 100644 radio/bootloader/usb/common/core/USBGenericRequest.h delete mode 100644 radio/bootloader/usb/common/core/USBGetDescriptorRequest.c delete mode 100644 radio/bootloader/usb/common/core/USBGetDescriptorRequest.h delete mode 100644 radio/bootloader/usb/common/core/USBInterfaceAssociationDescriptor.h delete mode 100644 radio/bootloader/usb/common/core/USBInterfaceDescriptor.h delete mode 100644 radio/bootloader/usb/common/core/USBInterfaceRequest.c delete mode 100644 radio/bootloader/usb/common/core/USBInterfaceRequest.h delete mode 100644 radio/bootloader/usb/common/core/USBIrqHandler.c delete mode 100644 radio/bootloader/usb/common/core/USBIrqHandler.h delete mode 100644 radio/bootloader/usb/common/core/USBSetAddressRequest.c delete mode 100644 radio/bootloader/usb/common/core/USBSetAddressRequest.h delete mode 100644 radio/bootloader/usb/common/core/USBSetConfigurationRequest.c delete mode 100644 radio/bootloader/usb/common/core/USBSetConfigurationRequest.h delete mode 100644 radio/bootloader/usb/common/core/USBStringDescriptor.h delete mode 100644 radio/bootloader/usb/common/massstorage/MSDeviceDescriptor.h delete mode 100644 radio/bootloader/usb/common/massstorage/MSInterfaceDescriptor.h delete mode 100644 radio/bootloader/usb/device/core/USBD.h delete mode 100644 radio/bootloader/usb/device/core/USBDCallbacks.c delete mode 100644 radio/bootloader/usb/device/core/USBDCallbacks.h delete mode 100644 radio/bootloader/usb/device/core/USBDDriver.c delete mode 100644 radio/bootloader/usb/device/core/USBDDriver.h delete mode 100644 radio/bootloader/usb/device/core/USBDDriverCallbacks.h delete mode 100644 radio/bootloader/usb/device/core/USBDDriverDescriptors.h delete mode 100644 radio/bootloader/usb/device/core/USBD_UDP.c delete mode 100644 radio/bootloader/usb/device/massstorage/MSD.h delete mode 100644 radio/bootloader/usb/device/massstorage/MSDDStateMachine.c delete mode 100644 radio/bootloader/usb/device/massstorage/MSDDStateMachine.h delete mode 100644 radio/bootloader/usb/device/massstorage/MSDDriver.c delete mode 100644 radio/bootloader/usb/device/massstorage/MSDDriver.h delete mode 100644 radio/bootloader/usb/device/massstorage/MSDDriverDescriptors.c delete mode 100644 radio/bootloader/usb/device/massstorage/MSDDriverDescriptors.h delete mode 100644 radio/bootloader/usb/device/massstorage/MSDIOFifo.h delete mode 100644 radio/bootloader/usb/device/massstorage/MSDLun.c delete mode 100644 radio/bootloader/usb/device/massstorage/MSDLun.h delete mode 100644 radio/bootloader/usb/device/massstorage/SBC.h delete mode 100644 radio/bootloader/usb/device/massstorage/SBCMethods.c delete mode 100644 radio/bootloader/usb/device/massstorage/SBCMethods.h diff --git a/companion/src/eeprominterface.h b/companion/src/eeprominterface.h index e79d9f4ae..f4a2bc7dc 100644 --- a/companion/src/eeprominterface.h +++ b/companion/src/eeprominterface.h @@ -125,6 +125,28 @@ const uint8_t chout_ar[] = { //First number is 0..23 -> template setup, Second #define BC_BIT_REA (0x80) #define BC_BIT_REB (0x100) +// TODO remove this enum! +enum EnumKeys { + KEY_MENU, + KEY_EXIT, +#if defined(PCBACT) + KEY_CLR, + KEY_PAGE, + KEY_PLUS, /* Fake, used for rotary encoder */ + KEY_MINUS, /* Fake, used for rotary encoder */ +#elif defined(PCBX9D) + KEY_ENTER, + KEY_PAGE, + KEY_PLUS, + KEY_MINUS, +#else + KEY_DOWN, + KEY_UP, + KEY_RIGHT, + KEY_LEFT, +#endif +}; + #define CHAR_FOR_NAMES " ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789_-." #define CHAR_FOR_NAMES_REGEX "[ A-Za-z0-9_.-,]*" diff --git a/radio/bootloader/usb/common/core/USBConfigurationDescriptor.c b/radio/bootloader/usb/common/core/USBConfigurationDescriptor.c deleted file mode 100644 index 7dd995c62..000000000 --- a/radio/bootloader/usb/common/core/USBConfigurationDescriptor.c +++ /dev/null @@ -1,162 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBConfigurationDescriptor implementation - - About: Purpose - Implementation of the USBConfigurationDescriptor class. -*/ - -//----------------------------------------------------------------------------- -// Headers -//----------------------------------------------------------------------------- - -#include "USBConfigurationDescriptor.h" - -//----------------------------------------------------------------------------- -// Exported functions -//----------------------------------------------------------------------------- - -//----------------------------------------------------------------------------- -/// Returns the total length of a configuration, i.e. including the -/// descriptors following it. -/// \param configuration Pointer to a USBConfigurationDescriptor instance. -/// \return Total length (in bytes) of the configuration. -//----------------------------------------------------------------------------- -unsigned int USBConfigurationDescriptor_GetTotalLength( - const USBConfigurationDescriptor *configuration) -{ - return configuration->wTotalLength; -} - -//----------------------------------------------------------------------------- -/// Returns the number of interfaces in a configuration. -/// \param configuration Pointer to a USBConfigurationDescriptor instance. -/// \return Number of interfaces in configuration. -//----------------------------------------------------------------------------- -unsigned char USBConfigurationDescriptor_GetNumInterfaces( - const USBConfigurationDescriptor *configuration) -{ - return configuration->bNumInterfaces; -} - -//----------------------------------------------------------------------------- -/// Indicates if the device is self-powered when in a given configuration. -/// \param configuration Pointer to a USBConfigurationDescriptor instance. -/// \return 1 if the device is self-powered when in the given configuration; -/// otherwise 0. -//----------------------------------------------------------------------------- -unsigned char USBConfigurationDescriptor_IsSelfPowered( - const USBConfigurationDescriptor *configuration) -{ - if ((configuration->bmAttributes & (1 << 6)) != 0) { - - return 1; - } - else { - - return 0; - } -} - -//----------------------------------------------------------------------------- -/// Parses the given Configuration descriptor (followed by relevant -/// interface, endpoint and class-specific descriptors) into three arrays. -/// *Each array must have its size equal or greater to the number of -/// descriptors it stores plus one*. A null-value is inserted after the last -/// descriptor of each type to indicate the array end. -/// -/// Note that if the pointer to an array is null (0), nothing is stored in -/// it. -/// \param configuration Pointer to the start of the whole Configuration -/// descriptor. -/// \param interfaces Pointer to the Interface descriptor array. -/// \param endpoints Pointer to the Endpoint descriptor array. -/// \param others Pointer to the class-specific descriptor array. -//----------------------------------------------------------------------------- -void USBConfigurationDescriptor_Parse( - const USBConfigurationDescriptor *configuration, - USBInterfaceDescriptor **interfaces, - USBEndpointDescriptor **endpoints, - USBGenericDescriptor **others) -{ - // Get size of configuration to parse - int size = USBConfigurationDescriptor_GetTotalLength(configuration); - size -= sizeof(USBConfigurationDescriptor); - - // Start parsing descriptors - USBGenericDescriptor *descriptor = (USBGenericDescriptor *) configuration; - while (size > 0) { - - // Get next descriptor - descriptor = USBGenericDescriptor_GetNextDescriptor(descriptor); - size -= USBGenericDescriptor_GetLength(descriptor); - - // Store descriptor in correponding array - if (USBGenericDescriptor_GetType(descriptor) - == USBGenericDescriptor_INTERFACE) { - - if (interfaces) { - - *interfaces = (USBInterfaceDescriptor *) descriptor; - interfaces++; - } - } - else if (USBGenericDescriptor_GetType(descriptor) - == USBGenericDescriptor_ENDPOINT) { - - if (endpoints) { - - *endpoints = (USBEndpointDescriptor *) descriptor; - endpoints++; - } - } - else if (others) { - - *others = descriptor; - others++; - } - } - - // Null-terminate arrays - if (interfaces) { - - *interfaces = 0; - } - if (endpoints) { - - *endpoints = 0; - } - if (others) { - - *others = 0; - } -} - diff --git a/radio/bootloader/usb/common/core/USBConfigurationDescriptor.h b/radio/bootloader/usb/common/core/USBConfigurationDescriptor.h deleted file mode 100644 index b7a867d64..000000000 --- a/radio/bootloader/usb/common/core/USBConfigurationDescriptor.h +++ /dev/null @@ -1,150 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - !!!Purpose - - Definitions and methods for USB configuration descriptor structures - described by the USB specification. - - !!!Usage - - -# Declare USBConfigurationDescriptor instance as a part - of the configuration descriptors of a USB device. - -# To get useful information (field values) from the defined USB device - configuration descriptor, use - - USBConfigurationDescriptor_GetTotalLength - - USBConfigurationDescriptor_GetNumInterfaces - - USBConfigurationDescriptor_IsSelfPowered - -# To pase the defined USB device configuration descriptor, use - - USBConfigurationDescriptor_Parse -*/ - -#ifndef USBCONFIGURATIONDESCRIPTOR_H -#define USBCONFIGURATIONDESCRIPTOR_H - -//----------------------------------------------------------------------------- -// Headers -//----------------------------------------------------------------------------- - -#include "USBGenericDescriptor.h" -#include "USBInterfaceDescriptor.h" -#include "USBEndpointDescriptor.h" - -//----------------------------------------------------------------------------- -// Definitions -//----------------------------------------------------------------------------- - -//----------------------------------------------------------------------------- -/// \page "USB device Attributes" -/// -/// This page lists the codes of the usb attributes. -/// -/// !Attributes -/// - USBConfigurationDescriptor_BUSPOWERED_NORWAKEUP -/// - USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP -/// - USBConfigurationDescriptor_BUSPOWERED_RWAKEUP -/// - USBConfigurationDescriptor_SELFPOWERED_RWAKEUP -/// - USBConfigurationDescriptor_POWER - -/// Device is bus-powered and not support remote wake-up. -#define USBConfigurationDescriptor_BUSPOWERED_NORWAKEUP 0x80 -/// Device is self-powered and not support remote wake-up. -#define USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP 0xC0 -/// Device is bus-powered and supports remote wake-up. -#define USBConfigurationDescriptor_BUSPOWERED_RWAKEUP 0xA0 -/// Device is self-powered and supports remote wake-up. -#define USBConfigurationDescriptor_SELFPOWERED_RWAKEUP 0xE0 - -/// Calculates the value of the power consumption field given the value in mA. -/// \param power The power consumption value in mA -/// \return The value that should be set to the field in descriptor -#define USBConfigurationDescriptor_POWER(power) (power / 2) -//----------------------------------------------------------------------------- - -//----------------------------------------------------------------------------- -// Types -//----------------------------------------------------------------------------- - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -//----------------------------------------------------------------------------- -/// USB standard configuration descriptor structure. -//----------------------------------------------------------------------------- -typedef struct { - - /// Size of the descriptor in bytes. - unsigned char bLength; - /// Descriptor type (USBDESC_CONFIGURATION of "USB Descriptor types"). - unsigned char bDescriptorType; - /// Length of all descriptors returned along with this configuration - /// descriptor. - unsigned short wTotalLength; - /// Number of interfaces in this configuration. - unsigned char bNumInterfaces; - /// Value for selecting this configuration. - unsigned char bConfigurationValue; - /// Index of the configuration string descriptor. - unsigned char iConfiguration; - /// Configuration characteristics. - unsigned char bmAttributes; - /// Maximum power consumption of the device when in this configuration. - unsigned char bMaxPower; - -} __attribute__ ((packed)) USBConfigurationDescriptor; // GCC - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -//----------------------------------------------------------------------------- -// Exported functions -//----------------------------------------------------------------------------- - -extern unsigned int USBConfigurationDescriptor_GetTotalLength( - const USBConfigurationDescriptor *configuration); - -extern unsigned char USBConfigurationDescriptor_GetNumInterfaces( - const USBConfigurationDescriptor *configuration); - -extern unsigned char USBConfigurationDescriptor_IsSelfPowered( - const USBConfigurationDescriptor *configuration); - -extern void USBConfigurationDescriptor_Parse( - const USBConfigurationDescriptor *configuration, - USBInterfaceDescriptor **interfaces, - USBEndpointDescriptor **endpoints, - USBGenericDescriptor **others); - -#endif //#ifndef USBCONFIGURATIONDESCRIPTOR_H - diff --git a/radio/bootloader/usb/common/core/USBDeviceDescriptor.h b/radio/bootloader/usb/common/core/USBDeviceDescriptor.h deleted file mode 100644 index 6b633fe99..000000000 --- a/radio/bootloader/usb/common/core/USBDeviceDescriptor.h +++ /dev/null @@ -1,125 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - !!!Purpose - - Class for manipulating USB device descriptors. - - !!!Usage - - - Declare a USBDeviceDescriptor instance as the device descriptor of a - USB device. -*/ - -#ifndef USBDEVICEDESCRIPTOR_H -#define USBDEVICEDESCRIPTOR_H - -#include -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB release numbers" -/// -/// This page lists the codes of USB release numbers. -/// -/// !Code -/// - USBDeviceDescriptor_USB2_00 - -/// The device supports USB 2.00. -#define USBDeviceDescriptor_USB2_00 0x0200 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -/// USB standard device descriptor structure. -//------------------------------------------------------------------------------ -typedef struct { - - /// Size of this descriptor in bytes. - unsigned char bLength; - /// Descriptor type (USBGenericDescriptor_DEVICE). - unsigned char bDescriptorType; - /// USB specification release number in BCD format. - unsigned short bcdUSB; - /// Device class code. - unsigned char bDeviceClass; - /// Device subclass code. - unsigned char bDeviceSubClass; - /// Device protocol code. - unsigned char bDeviceProtocol; - /// Maximum packet size of endpoint 0 (in bytes). - unsigned char bMaxPacketSize0; - /// Vendor ID. - unsigned short idVendor; - /// Product ID. - unsigned short idProduct; - /// Device release number in BCD format. - unsigned short bcdDevice; - /// Index of the manufacturer string descriptor. - unsigned char iManufacturer; - /// Index of the product string descriptor. - unsigned char iProduct; - /// Index of the serial number string descriptor. - unsigned char iSerialNumber; - /// Number of possible configurations for the device. - unsigned char bNumConfigurations; - -} __attribute__ ((packed)) USBDeviceDescriptor; // GCC - -#if defined(CHIP_USB_OTGHS) -typedef struct { - - /// Size of this descriptor in bytes. - unsigned char bLength; - /// Descriptor type (USBGenericDescriptor_OTG). - unsigned char bDescriptorType; - /// Attribute Fields D72: Reserved D1: HNP support D0: SRP support - unsigned char bmAttributes; - -} __attribute__ ((packed)) USBOtgDescriptor; // GCC -#endif - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -#endif //#ifndef USBDEVICEDESCRIPTOR_H - diff --git a/radio/bootloader/usb/common/core/USBDeviceQualifierDescriptor.h b/radio/bootloader/usb/common/core/USBDeviceQualifierDescriptor.h deleted file mode 100644 index 5632e18c5..000000000 --- a/radio/bootloader/usb/common/core/USBDeviceQualifierDescriptor.h +++ /dev/null @@ -1,89 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Class for manipulating USB device qualifier descriptors. - - !!!Usage - - - Declare a USBDeviceQualifierDescriptor instance as the device qualifier - descriptor of a USB device. -*/ - -#ifndef USBDEVICEQUALIFIERDESCRIPTOR_H -#define USBDEVICEQUALIFIERDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -/// Alternate device descriptor indicating the capabilities of the device -/// in full-speed, if currently in high-speed; or in high-speed, if it is -/// currently in full-speed. Only relevant for devices supporting the -/// high-speed mode. -//------------------------------------------------------------------------------ -typedef struct { - - /// Size of the descriptor in bytes. - unsigned char bLength; - /// Descriptor type (USBDESC_DEVICE_QUALIFIER or "USB device types"). - unsigned char bDescriptorType; - /// USB specification release number (in BCD format). - unsigned short bcdUSB; - /// Device class code. - unsigned char bDeviceClass; - /// Device subclass code. - unsigned char bDeviceSubClass; - /// Device protocol code. - unsigned char bDeviceProtocol; - /// Maximum packet size of endpoint 0. - unsigned char bMaxPacketSize0; - /// Number of possible configurations for the device. - unsigned char bNumConfigurations; - /// Reserved. - unsigned char bReserved; - -} __attribute__ ((packed)) USBDeviceQualifierDescriptor; // GCC - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -#endif //#ifndef USBDEVICEQUALIFIERDESCRIPTOR_H - diff --git a/radio/bootloader/usb/common/core/USBEndpointDescriptor.c b/radio/bootloader/usb/common/core/USBEndpointDescriptor.c deleted file mode 100644 index c60be2ac1..000000000 --- a/radio/bootloader/usb/common/core/USBEndpointDescriptor.c +++ /dev/null @@ -1,109 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBEndpointDescriptor implementation - - About: Purpose - Implementation of the USBEndpointDescriptor class. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBEndpointDescriptor.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Returns the number of an endpoint given its descriptor. -/// \param endpoint Pointer to a USBEndpointDescriptor instance. -/// \return Endpoint number. -//------------------------------------------------------------------------------ -unsigned char USBEndpointDescriptor_GetNumber( - const USBEndpointDescriptor *endpoint) -{ - return endpoint->bEndpointAddress & 0xF; -} - -//------------------------------------------------------------------------------ -/// Returns the direction of an endpoint given its descriptor. -/// \param endpoint Pointer to a USBEndpointDescriptor instance. -/// \return Endpoint direction (see ). -//------------------------------------------------------------------------------ -unsigned char USBEndpointDescriptor_GetDirection( - const USBEndpointDescriptor *endpoint) -{ - if ((endpoint->bEndpointAddress & 0x80) != 0) { - - return USBEndpointDescriptor_IN; - } - else { - - return USBEndpointDescriptor_OUT; - } -} - -//------------------------------------------------------------------------------ -/// Returns the type of an endpoint given its descriptor. -/// \param endpoint Pointer to a USBEndpointDescriptor instance. -/// \return Endpoint type (see ). -//------------------------------------------------------------------------------ -unsigned char USBEndpointDescriptor_GetType( - const USBEndpointDescriptor *endpoint) -{ - return endpoint->bmAttributes & 0x3; -} - -//------------------------------------------------------------------------------ -/// Returns the maximum size of a packet (in bytes) on an endpoint given -/// its descriptor. -/// \param endpoint - Pointer to a USBEndpointDescriptor instance. -/// \return Maximum packet size of endpoint. -//------------------------------------------------------------------------------ -unsigned short USBEndpointDescriptor_GetMaxPacketSize( - const USBEndpointDescriptor *endpoint) -{ - return endpoint->wMaxPacketSize; -} - -//------------------------------------------------------------------------------ -/// Returns the polling interval on an endpoint given its descriptor. -/// \param endpoint - Pointer to a USBEndpointDescriptor instance. -/// \return Polling interval of endpoint. -//------------------------------------------------------------------------------ -unsigned char USBEndpointDescriptor_GetInterval( - const USBEndpointDescriptor *endpoint) -{ - return endpoint->bInterval; -} - diff --git a/radio/bootloader/usb/common/core/USBEndpointDescriptor.h b/radio/bootloader/usb/common/core/USBEndpointDescriptor.h deleted file mode 100644 index 8a691eec2..000000000 --- a/radio/bootloader/usb/common/core/USBEndpointDescriptor.h +++ /dev/null @@ -1,224 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of a class for handling USB endpoint descriptors. - - !!!Usage - - -# Declare USBEndpointDescriptor instance as a part of the - configuration descriptors of a USB device. - -# To get useful information (field values) from the defined USB device - endpoint descriptor (to configure hardware for endpoints, etc), use - - USBEndpointDescriptor_GetNumber - - USBEndpointDescriptor_GetDirection - - USBEndpointDescriptor_GetType - - USBEndpointDescriptor_GetMaxPacketSize -*/ - -#ifndef USBENDPOINTDESCRIPTOR_H -#define USBENDPOINTDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Endpoint definitions" -/// -/// This page lists definitions and macro for endpoint descriptors. -/// -/// - USB Endpoint directions -/// - USBEndpointDescriptor_OUT -/// - USBEndpointDescriptor_IN -/// -/// - USB Endpoint types -/// - USBEndpointDescriptor_CONTROL -/// - USBEndpointDescriptor_ISOCHRONOUS -/// - USBEndpointDescriptor_BULK -/// - USBEndpointDescriptor_INTERRUPT -/// -/// - USB Endpoint maximun sizes -/// - USBEndpointDescriptor_MAXCTRLSIZE_FS -/// - USBEndpointDescriptor_MAXCTRLSIZE_HS -/// - USBEndpointDescriptor_MAXBULKSIZE_FS -/// - USBEndpointDescriptor_MAXBULKSIZE_HS -/// - USBEndpointDescriptor_MAXINTERRUPTSIZE_FS -/// - USBEndpointDescriptor_MAXINTERRUPTSIZE_HS -/// - USBEndpointDescriptor_MAXISOCHRONOUSSIZE_FS -/// - USBEndpointDescriptor_MAXISOCHRONOUSSIZE_HS -/// -/// - USB Endpoint address define -/// - USBEndpointDescriptor_ADDRESS -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Endpoint directions" -/// -/// This page lists definitions of USB endpoint directions. -/// -/// !Directions -/// - USBEndpointDescriptor_OUT -/// - USBEndpointDescriptor_IN - -/// Endpoint receives data from the host. -#define USBEndpointDescriptor_OUT 0 -/// Endpoint sends data to the host. -#define USBEndpointDescriptor_IN 1 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Endpoint types" -/// -/// This page lists definitions of USB endpoint types. -/// -/// !Types -/// - USBEndpointDescriptor_CONTROL -/// - USBEndpointDescriptor_ISOCHRONOUS -/// - USBEndpointDescriptor_BULK -/// - USBEndpointDescriptor_INTERRUPT - -/// Control endpoint type. -#define USBEndpointDescriptor_CONTROL 0 -/// Isochronous endpoint type. -#define USBEndpointDescriptor_ISOCHRONOUS 1 -/// Bulk endpoint type. -#define USBEndpointDescriptor_BULK 2 -/// Interrupt endpoint type. -#define USBEndpointDescriptor_INTERRUPT 3 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Endpoint maximun sizes" -/// -/// This page lists definitions of USB endpoint maximun sizes. -/// -/// !Sizes -/// - USBEndpointDescriptor_MAXCTRLSIZE_FS -/// - USBEndpointDescriptor_MAXCTRLSIZE_HS -/// - USBEndpointDescriptor_MAXBULKSIZE_FS -/// - USBEndpointDescriptor_MAXBULKSIZE_HS -/// - USBEndpointDescriptor_MAXINTERRUPTSIZE_FS -/// - USBEndpointDescriptor_MAXINTERRUPTSIZE_HS -/// - USBEndpointDescriptor_MAXISOCHRONOUSSIZE_FS -/// - USBEndpointDescriptor_MAXISOCHRONOUSSIZE_HS - -/// Maximum size for a full-speed control endpoint. -#define USBEndpointDescriptor_MAXCTRLSIZE_FS 64 -/// Maximum size for a high-speed control endpoint. -#define USBEndpointDescriptor_MAXCTRLSIZE_HS 64 -/// Maximum size for a full-speed bulk endpoint. -#define USBEndpointDescriptor_MAXBULKSIZE_FS 64 -/// Maximum size for a high-speed bulk endpoint. -#define USBEndpointDescriptor_MAXBULKSIZE_HS 512 -/// Maximum size for a full-speed interrupt endpoint. -#define USBEndpointDescriptor_MAXINTERRUPTSIZE_FS 64 -/// Maximum size for a high-speed interrupt endpoint. -#define USBEndpointDescriptor_MAXINTERRUPTSIZE_HS 1024 -/// Maximum size for a full-speed isochronous endpoint. -#define USBEndpointDescriptor_MAXISOCHRONOUSSIZE_FS 1023 -/// Maximum size for a high-speed isochronous endpoint. -#define USBEndpointDescriptor_MAXISOCHRONOUSSIZE_HS 1024 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Endpoint address define" -/// -/// This page lists macro for USB endpoint address definition. -/// -/// !Macro -/// - USBEndpointDescriptor_ADDRESS - -/// Calculates the address of an endpoint given its number and direction -/// \param direction USB endpoint direction definition -/// \param number USB endpoint number -/// \return The value used to set the endpoint descriptor based on input number -/// and direction -#define USBEndpointDescriptor_ADDRESS(direction, number) \ - (((direction & 0x01) << 7) | (number & 0xF)) -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -/// USB standard endpoint descriptor structure. -//------------------------------------------------------------------------------ -typedef struct { - - /// Size of the descriptor in bytes. - unsigned char bLength; - /// Descriptor type (). - unsigned char bDescriptorType; - /// Address and direction of the endpoint. - unsigned char bEndpointAddress; - /// Endpoint type and additional characteristics (for isochronous endpoints). - unsigned char bmAttributes; - /// Maximum packet size (in bytes) of the endpoint. - unsigned short wMaxPacketSize; - /// Polling rate of the endpoint. - unsigned char bInterval; - -} __attribute__ ((packed)) USBEndpointDescriptor; // GCC - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char USBEndpointDescriptor_GetNumber( - const USBEndpointDescriptor *endpoint); - -extern unsigned char USBEndpointDescriptor_GetDirection( - const USBEndpointDescriptor *endpoint); - -extern unsigned char USBEndpointDescriptor_GetType( - const USBEndpointDescriptor *endpoint); - -extern unsigned short USBEndpointDescriptor_GetMaxPacketSize( - const USBEndpointDescriptor *endpoint); - -extern unsigned char USBEndpointDescriptor_GetInterval( - const USBEndpointDescriptor *endpoint); - -#endif //#ifndef USBENDPOINTDESCRIPTOR_H - diff --git a/radio/bootloader/usb/common/core/USBFeatureRequest.c b/radio/bootloader/usb/common/core/USBFeatureRequest.c deleted file mode 100644 index 6276f6d5a..000000000 --- a/radio/bootloader/usb/common/core/USBFeatureRequest.c +++ /dev/null @@ -1,70 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBFeatureRequest implementation - - About: Purpose - Implementation of the USBFeatureRequest class. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBFeatureRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Returns the feature selector of a given CLEAR_FEATURE or SET_FEATURE -/// request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Feature selector. -//------------------------------------------------------------------------------ -unsigned char USBFeatureRequest_GetFeatureSelector( - const USBGenericRequest *request) -{ - return USBGenericRequest_GetValue(request); -} - -//------------------------------------------------------------------------------ -/// Indicates the test that the device must undertake following a -/// SET_FEATURE request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Test selector. -//------------------------------------------------------------------------------ -unsigned char USBFeatureRequest_GetTestSelector( - const USBGenericRequest *request) -{ - return (USBGenericRequest_GetIndex(request) >> 8) & 0xFF; -} - diff --git a/radio/bootloader/usb/common/core/USBFeatureRequest.h b/radio/bootloader/usb/common/core/USBFeatureRequest.h deleted file mode 100644 index 49493c732..000000000 --- a/radio/bootloader/usb/common/core/USBFeatureRequest.h +++ /dev/null @@ -1,146 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of a class for manipulating CLEAR_FEATURE and SET_FEATURE - requests. - - !!!Usage - - - To get USB feature request information (field values) from the - USBGenericRequest instance, use - - USBFeatureRequest_GetFeatureSelector - - USBFeatureRequest_GetTestSelector -*/ - -#ifndef USBFEATUREREQUEST_H -#define USBFEATUREREQUEST_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBGenericRequest.h" - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Feature Request definitions" -/// -/// This page lists codes of USB Feature Request -/// -/// - USB Feature selectors -/// - USBFeatureRequest_ENDPOINTHALT -/// - USBFeatureRequest_DEVICEREMOTEWAKEUP -/// - USBFeatureRequest_TESTMODE -/// -/// - USB Test mode selectors -/// - USBFeatureRequest_TESTJ -/// - USBFeatureRequest_TESTK -/// - USBFeatureRequest_TESTSE0NAK -/// - USBFeatureRequest_TESTPACKET -/// - USBFeatureRequest_TESTFORCEENABLE -/// - USBFeatureRequest_TESTSENDZLP -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Feature selectors" -/// -/// This page lists codes of USB feature selectors. -/// -/// !Selectors -/// - USBFeatureRequest_ENDPOINTHALT -/// - USBFeatureRequest_DEVICEREMOTEWAKEUP -/// - USBFeatureRequest_TESTMODE - -/// Halt feature of an endpoint. -#define USBFeatureRequest_ENDPOINTHALT 0 -/// Remote wake-up feature of the device. -#define USBFeatureRequest_DEVICEREMOTEWAKEUP 1 -/// Test mode of the device. -#define USBFeatureRequest_TESTMODE 2 -/// OTG set feature -#define USBFeatureRequest_OTG 0x0B -//------------------------------------------------------------------------------ - -/// On The Go Feature Selectors -/// b_hnp_enable 3 -/// a_hnp_support 4 -/// a_alt_hnp_support 5 -#define USBFeatureRequest_OTG_B_HNP_ENABLE 3 -#define USBFeatureRequest_OTG_A_HNP_SUPPORT 4 -#define USBFeatureRequest_OTG_A_ALT_HNP_SUPPORT 5 - -//------------------------------------------------------------------------------ -/// \page "USB Test mode selectors" -/// -/// This page lists codes of USB high speed test mode selectors. -/// -/// !Selectors -/// - USBFeatureRequest_TESTJ -/// - USBFeatureRequest_TESTK -/// - USBFeatureRequest_TESTSE0NAK -/// - USBFeatureRequest_TESTPACKET -/// - USBFeatureRequest_TESTFORCEENABLE -/// - USBFeatureRequest_TESTSENDZLP - -/// Tests the high-output drive level on the D+ line. -#define USBFeatureRequest_TESTJ 1 -/// Tests the high-output drive level on the D- line. -#define USBFeatureRequest_TESTK 2 -/// Tests the output impedance, low-level output voltage and loading -/// characteristics. -#define USBFeatureRequest_TESTSE0NAK 3 -/// Tests rise and fall times, eye patterns and jitter. -#define USBFeatureRequest_TESTPACKET 4 -/// Tests the hub disconnect detection. -#define USBFeatureRequest_TESTFORCEENABLE 5 -/// Send a ZLP in Test Mode. -#define USBFeatureRequest_TESTSENDZLP 6 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char USBFeatureRequest_GetFeatureSelector( - const USBGenericRequest *request); - - -extern unsigned char USBFeatureRequest_GetTestSelector( - const USBGenericRequest *request); - -#endif //#ifndef USBFEATUREREQUEST_H - diff --git a/radio/bootloader/usb/common/core/USBGenericDescriptor.c b/radio/bootloader/usb/common/core/USBGenericDescriptor.c deleted file mode 100644 index 298bad6c5..000000000 --- a/radio/bootloader/usb/common/core/USBGenericDescriptor.c +++ /dev/null @@ -1,80 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBGenericDescriptor implementation - - About: Purpose - Implementation of the USBGenericDescriptor class. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBGenericDescriptor.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Returns the length of a descriptor. -/// \param descriptor Pointer to a USBGenericDescriptor instance. -/// \return Length of descriptor in bytes. -//------------------------------------------------------------------------------ -unsigned int USBGenericDescriptor_GetLength( - const USBGenericDescriptor *descriptor) -{ - return descriptor->bLength; -} - -//------------------------------------------------------------------------------ -/// Returns the type of a descriptor. -/// \param descriptor Pointer to a USBGenericDescriptor instance. -/// \return Type of descriptor. -//------------------------------------------------------------------------------ -unsigned char USBGenericDescriptor_GetType( - const USBGenericDescriptor *descriptor) -{ - return descriptor->bDescriptorType; -} - -//------------------------------------------------------------------------------ -/// Returns a pointer to the descriptor right after the given one, when -/// parsing a Configuration descriptor. -/// \param descriptor - Pointer to a USBGenericDescriptor instance. -/// \return Pointer to the next descriptor. -//------------------------------------------------------------------------------ -USBGenericDescriptor *USBGenericDescriptor_GetNextDescriptor( - const USBGenericDescriptor *descriptor) -{ - return (USBGenericDescriptor *) - (((char *) descriptor) + USBGenericDescriptor_GetLength(descriptor)); -} diff --git a/radio/bootloader/usb/common/core/USBGenericDescriptor.h b/radio/bootloader/usb/common/core/USBGenericDescriptor.h deleted file mode 100644 index 01318f431..000000000 --- a/radio/bootloader/usb/common/core/USBGenericDescriptor.h +++ /dev/null @@ -1,133 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !!!Purpose -/// -/// Definition of a generic USB descriptor class. -/// -/// !!!Usage -/// -/// -# Declare or access USB descriptors by USBGenericDescriptor instance. -/// -# To get usful information (field values) from the USB descriptors, use -/// - USBGenericDescriptor_GetLength -/// - USBGenericDescriptor_GetType -/// -# To scan the descriptors, use -/// - USBGenericDescriptor_GetNextDescriptor -//------------------------------------------------------------------------------ - -#ifndef USBGENERICDESCRIPTOR_H -#define USBGENERICDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Descriptor types" -/// -/// This page lists the codes of the usb descriptor types -/// -/// !Types -/// - USBGenericDescriptor_DEVICE -/// - USBGenericDescriptor_CONFIGURATION -/// - USBGenericDescriptor_STRING -/// - USBGenericDescriptor_INTERFACE -/// - USBGenericDescriptor_ENDPOINT -/// - USBGenericDescriptor_DEVICEQUALIFIER -/// - USBGenericDescriptor_OTHERSPEEDCONFIGURATION -/// - USBGenericDescriptor_INTERFACEPOWER -/// - USBGenericDescriptor_OTG -/// - USBGenericDescriptor_DEBUG -/// - USBGenericDescriptor_INTERFACEASSOCIATION - -/// Device descriptor type. -#define USBGenericDescriptor_DEVICE 1 -/// Configuration descriptor type. -#define USBGenericDescriptor_CONFIGURATION 2 -/// String descriptor type. -#define USBGenericDescriptor_STRING 3 -/// Interface descriptor type. -#define USBGenericDescriptor_INTERFACE 4 -/// Endpoint descriptor type. -#define USBGenericDescriptor_ENDPOINT 5 -/// Device qualifier descriptor type. -#define USBGenericDescriptor_DEVICEQUALIFIER 6 -/// Other speed configuration descriptor type. -#define USBGenericDescriptor_OTHERSPEEDCONFIGURATION 7 -/// Interface power descriptor type. -#define USBGenericDescriptor_INTERFACEPOWER 8 -/// On-The-Go descriptor type. -#define USBGenericDescriptor_OTG 9 -/// Debug descriptor type. -#define USBGenericDescriptor_DEBUG 10 -/// Interface association descriptor type. -#define USBGenericDescriptor_INTERFACEASSOCIATION 11 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -/// Holds the few fields shared by all USB descriptors. -typedef struct { - - /// Length of the descriptor in bytes. - unsigned char bLength; - /// Descriptor type. - unsigned char bDescriptorType; - -} __attribute__ ((packed)) USBGenericDescriptor; // GCC - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned int USBGenericDescriptor_GetLength( - const USBGenericDescriptor *descriptor); - -extern unsigned char USBGenericDescriptor_GetType( - const USBGenericDescriptor *descriptor); - -extern USBGenericDescriptor *USBGenericDescriptor_GetNextDescriptor( - const USBGenericDescriptor *descriptor); - -#endif //#ifndef USBGENERICDESCRIPTOR_H - diff --git a/radio/bootloader/usb/common/core/USBGenericRequest.c b/radio/bootloader/usb/common/core/USBGenericRequest.c deleted file mode 100644 index 9e902422a..000000000 --- a/radio/bootloader/usb/common/core/USBGenericRequest.c +++ /dev/null @@ -1,138 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBGenericRequest implementation - - About: Purpose - Implementation of the USBGenericRequest class. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBGenericRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -//------------------------------------------------------------------------------ -/// Returns the type of the given request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return "USB Request Types" -//------------------------------------------------------------------------------ -extern unsigned char USBGenericRequest_GetType(const USBGenericRequest *request) -{ - return ((request->bmRequestType >> 5) & 0x3); -} - -//------------------------------------------------------------------------------ -/// Returns the request code of the given request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Request code. -/// \sa "USB Request Codes" -//------------------------------------------------------------------------------ -unsigned char USBGenericRequest_GetRequest(const USBGenericRequest *request) -{ - return request->bRequest; -} - -//------------------------------------------------------------------------------ -/// Returns the wValue field of the given request. -/// \param request - Pointer to a USBGenericRequest instance. -/// \return Request value. -//------------------------------------------------------------------------------ -unsigned short USBGenericRequest_GetValue(const USBGenericRequest *request) -{ - return request->wValue; -} - -//------------------------------------------------------------------------------ -/// Returns the wIndex field of the given request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Request index; -//------------------------------------------------------------------------------ -unsigned short USBGenericRequest_GetIndex(const USBGenericRequest *request) -{ - return request->wIndex; -} - -//------------------------------------------------------------------------------ -/// Returns the expected length of the data phase following a request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Length of data phase. -//------------------------------------------------------------------------------ -unsigned short USBGenericRequest_GetLength(const USBGenericRequest *request) -{ - return request->wLength; -} - -//------------------------------------------------------------------------------ -/// Returns the endpoint number targetted by a given request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Endpoint number. -//------------------------------------------------------------------------------ -unsigned char USBGenericRequest_GetEndpointNumber( - const USBGenericRequest *request) -{ - return USBGenericRequest_GetIndex(request) & 0xF; -} - -//------------------------------------------------------------------------------ -/// Returns the intended recipient of a given request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Request recipient. -/// \sa "USB Request Recipients" -//------------------------------------------------------------------------------ -unsigned char USBGenericRequest_GetRecipient(const USBGenericRequest *request) -{ - // Recipient is in bits [0..4] of the bmRequestType field - return request->bmRequestType & 0xF; -} - -//------------------------------------------------------------------------------ -/// Returns the direction of the data transfer following the given request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Transfer direction. -/// \sa "USB Request Directions" -//------------------------------------------------------------------------------ -unsigned char USBGenericRequest_GetDirection(const USBGenericRequest *request) -{ - // Transfer direction is located in bit D7 of the bmRequestType field - if ((request->bmRequestType & 0x80) != 0) { - - return USBGenericRequest_IN; - } - else { - - return USBGenericRequest_OUT; - } -} - diff --git a/radio/bootloader/usb/common/core/USBGenericRequest.h b/radio/bootloader/usb/common/core/USBGenericRequest.h deleted file mode 100644 index 0e7895436..000000000 --- a/radio/bootloader/usb/common/core/USBGenericRequest.h +++ /dev/null @@ -1,244 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of the USBGenericRequest class and its methods. - - !!!Usage - - -# Declare or access USB requests by USBGenericRequest instance. - -# To get usful information (field values) from the USB requests, use - - USBGenericRequest_GetType - - USBGenericRequest_GetRequest - - USBGenericRequest_GetValue - - USBGenericRequest_GetIndex - - USBGenericRequest_GetLength - - USBGenericRequest_GetEndpointNumber - - USBGenericRequest_GetRecipient - - USBGenericRequest_GetDirection -*/ - -#ifndef USBGENERICREQUEST_H -#define USBGENERICREQUEST_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Generic Request definitions" -/// -/// This page lists the codes of USB generic request. -/// -/// - USB Request codes -/// - USBGenericRequest_GETSTATUS -/// - USBGenericRequest_CLEARFEATURE -/// - USBGenericRequest_SETFEATURE -/// - USBGenericRequest_SETADDRESS -/// - USBGenericRequest_GETDESCRIPTOR -/// - USBGenericRequest_SETDESCRIPTOR -/// - USBGenericRequest_GETCONFIGURATION -/// - USBGenericRequest_SETCONFIGURATION -/// - USBGenericRequest_GETINTERFACE -/// - USBGenericRequest_SETINTERFACE -/// - USBGenericRequest_SYNCHFRAME -/// -/// - USB Request Recipients -/// - USBGenericRequest_DEVICE -/// - USBGenericRequest_INTERFACE -/// - USBGenericRequest_ENDPOINT -/// - USBGenericRequest_OTHER -/// -/// - USB Request Types -/// - USBGenericRequest_STANDARD -/// - USBGenericRequest_CLASS -/// - USBGenericRequest_VENDOR -/// -/// - USB Request Directions -/// - USBGenericRequest_IN -/// - USBGenericRequest_OUT -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Request codes" -/// -/// This page lists the USB generic request codes. -/// -/// !Codes -/// - USBGenericRequest_GETSTATUS -/// - USBGenericRequest_CLEARFEATURE -/// - USBGenericRequest_SETFEATURE -/// - USBGenericRequest_SETADDRESS -/// - USBGenericRequest_GETDESCRIPTOR -/// - USBGenericRequest_SETDESCRIPTOR -/// - USBGenericRequest_GETCONFIGURATION -/// - USBGenericRequest_SETCONFIGURATION -/// - USBGenericRequest_GETINTERFACE -/// - USBGenericRequest_SETINTERFACE -/// - USBGenericRequest_SYNCHFRAME - -/// GET_STATUS request code. -#define USBGenericRequest_GETSTATUS 0 -/// CLEAR_FEATURE request code. -#define USBGenericRequest_CLEARFEATURE 1 -/// SET_FEATURE request code. -#define USBGenericRequest_SETFEATURE 3 -/// SET_ADDRESS request code. -#define USBGenericRequest_SETADDRESS 5 -/// GET_DESCRIPTOR request code. -#define USBGenericRequest_GETDESCRIPTOR 6 -/// SET_DESCRIPTOR request code. -#define USBGenericRequest_SETDESCRIPTOR 7 -/// GET_CONFIGURATION request code. -#define USBGenericRequest_GETCONFIGURATION 8 -/// SET_CONFIGURATION request code. -#define USBGenericRequest_SETCONFIGURATION 9 -/// GET_INTERFACE request code. -#define USBGenericRequest_GETINTERFACE 10 -/// SET_INTERFACE request code. -#define USBGenericRequest_SETINTERFACE 11 -/// SYNCH_FRAME request code. -#define USBGenericRequest_SYNCHFRAME 12 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Request Recipients" -/// -/// This page lists codes of USB request recipients. -/// -/// !Recipients -/// - USBGenericRequest_DEVICE -/// - USBGenericRequest_INTERFACE -/// - USBGenericRequest_ENDPOINT -/// - USBGenericRequest_OTHER - -/// Recipient is the whole device. -#define USBGenericRequest_DEVICE 0 -/// Recipient is an interface. -#define USBGenericRequest_INTERFACE 1 -/// Recipient is an endpoint. -#define USBGenericRequest_ENDPOINT 2 -/// Recipient is another entity. -#define USBGenericRequest_OTHER 3 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Request Types" -/// -/// This page lists codes of USB request types. -/// -/// !Types -/// - USBGenericRequest_STANDARD -/// - USBGenericRequest_CLASS -/// - USBGenericRequest_VENDOR - -/// Request is standard. -#define USBGenericRequest_STANDARD 0 -/// Request is class-specific. -#define USBGenericRequest_CLASS 1 -/// Request is vendor-specific. -#define USBGenericRequest_VENDOR 2 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Request Directions" -/// -/// This page lists codes of USB request directions. -/// -/// !Directions -/// - USBGenericRequest_IN -/// - USBGenericRequest_OUT - -/// Transfer occurs from device to the host. -#define USBGenericRequest_OUT 0 -/// Transfer occurs from the host to the device. -#define USBGenericRequest_IN 1 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Generic USB SETUP request sent over Control endpoints. -//------------------------------------------------------------------------------ -typedef struct { - - /// Type of request - /// \sa "USB Request Recipients" - /// \sa "USB Request Types" - /// \sa "USB Request Directions" - unsigned char bmRequestType:8; - /// Request code - /// \sa "USB Request Codes" - unsigned char bRequest:8; - /// Request-specific value parameter. - unsigned short wValue:16; - /// Request-specific index parameter. - unsigned short wIndex:16; - /// Expected length (in bytes) of the data phase. - unsigned short wLength:16; - -} USBGenericRequest; - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char USBGenericRequest_GetType( - const USBGenericRequest *request); - - -extern unsigned char USBGenericRequest_GetRequest( - const USBGenericRequest *request); - -extern unsigned short USBGenericRequest_GetValue( - const USBGenericRequest *request); - -extern unsigned short USBGenericRequest_GetIndex( - const USBGenericRequest *request); - -extern unsigned short USBGenericRequest_GetLength( - const USBGenericRequest *request); - -extern unsigned char USBGenericRequest_GetEndpointNumber( - const USBGenericRequest *request); - -extern unsigned char USBGenericRequest_GetRecipient( - const USBGenericRequest *request); - -extern unsigned char USBGenericRequest_GetDirection( - const USBGenericRequest *request); - -#endif //#ifndef USBGENERICREQUEST_H - diff --git a/radio/bootloader/usb/common/core/USBGetDescriptorRequest.c b/radio/bootloader/usb/common/core/USBGetDescriptorRequest.c deleted file mode 100644 index 39c4127c7..000000000 --- a/radio/bootloader/usb/common/core/USBGetDescriptorRequest.c +++ /dev/null @@ -1,72 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBGetDescriptorRequest implementation - - About: Purpose - Implementation of the USBGetDescriptorRequest class. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBGetDescriptorRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Returns the type of the descriptor requested by the host given the -/// corresponding GET_DESCRIPTOR request. -/// \param request Pointer to a USBGenericDescriptor instance. -/// \return Type of the requested descriptor. -//------------------------------------------------------------------------------ -unsigned char USBGetDescriptorRequest_GetDescriptorType( - const USBGenericRequest *request) -{ - // Requested descriptor type is in the high-byte of the wValue field - return (USBGenericRequest_GetValue(request) >> 8) & 0xFF; -} - -//------------------------------------------------------------------------------ -/// Returns the index of the requested descriptor, given the corresponding -/// GET_DESCRIPTOR request. -/// \param request Pointer to a USBGenericDescriptor instance. -/// \return Index of the requested descriptor. -//------------------------------------------------------------------------------ -unsigned char USBGetDescriptorRequest_GetDescriptorIndex( - const USBGenericRequest *request) -{ - // Requested descriptor index if in the low byte of the wValue field - return USBGenericRequest_GetValue(request) & 0xFF; -} - diff --git a/radio/bootloader/usb/common/core/USBGetDescriptorRequest.h b/radio/bootloader/usb/common/core/USBGetDescriptorRequest.h deleted file mode 100644 index 5aef6320a..000000000 --- a/radio/bootloader/usb/common/core/USBGetDescriptorRequest.h +++ /dev/null @@ -1,67 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of the USBGetDescriptorRequest class. - - !!!Usage - - - After a GET_DESCRIPTOR request has been received, retrive the useful - values with following functions: - - USBGetDescriptorRequest_GetDescriptorType: the descriptor type - - USBGetDescriptorRequest_GetDescriptorIndex: the index of the requested - descriptor - -*/ - -#ifndef USBGETDESCRIPTORREQUEST_H -#define USBGETDESCRIPTORREQUEST_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBGenericRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char USBGetDescriptorRequest_GetDescriptorType( - const USBGenericRequest *request); - -extern unsigned char USBGetDescriptorRequest_GetDescriptorIndex( - const USBGenericRequest *request); - -#endif //#ifndef USBGETDESCRIPTORREQUEST_H - diff --git a/radio/bootloader/usb/common/core/USBInterfaceAssociationDescriptor.h b/radio/bootloader/usb/common/core/USBInterfaceAssociationDescriptor.h deleted file mode 100644 index 7f3376d01..000000000 --- a/radio/bootloader/usb/common/core/USBInterfaceAssociationDescriptor.h +++ /dev/null @@ -1,86 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \page USBInterfaceAssociateDescriptor - * !!!Purpose - * - * Class for manipulating USB IAD descriptors. - * - * !!!Usage - * - * -# Test - */ - -#ifndef USBDIADDESCRIPTOR_H -#define USBDIADDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -/* - Type: USBDeviceDescriptor - USB standard device descriptor structure. - - Variables: - bLength - Size of this descriptor in bytes. - bDescriptorType - Descriptor type (). - bFirstInterface - Interface number of the first interface that is - associated with this function. - bInterfaceCount - Number of contiguous interfaces that are - associated with this function. - bFunctionClass - Class code (assigned by USB-IF). - bFunctionSubClass - Subclass code (assigned by USB-IF). - bFunctionProtocol - Protocol code (assigned by USB-IF) - iFunction - Index of string descriptor describing this function. -*/ -typedef struct { - - unsigned char bLength; - unsigned char bDescriptorType; - unsigned char bFirstInterface; - unsigned char bInterfaceCount; - unsigned char bFunctionClass; - unsigned char bFunctionSubClass; - unsigned char bFunctionProtocol; - unsigned char iFunction; -} __attribute__ ((packed)) USBInterfaceAssociationDescriptor; // GCC - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -#endif //#ifndef USBDIADDESCRIPTOR_H - diff --git a/radio/bootloader/usb/common/core/USBInterfaceDescriptor.h b/radio/bootloader/usb/common/core/USBInterfaceDescriptor.h deleted file mode 100644 index 0d897a865..000000000 --- a/radio/bootloader/usb/common/core/USBInterfaceDescriptor.h +++ /dev/null @@ -1,87 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of a class for manipulating USB interface descriptors. - - !!!Usage - - - Declare USBInterfaceDescriptor instance as a part of the configuration - descriptors of a USB device. - -*/ - -#ifndef USBINTERFACEDESCRIPTOR_H -#define USBINTERFACEDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -/// USB standard interface descriptor structure. -//------------------------------------------------------------------------------ -typedef struct { - - /// Size of the descriptor in bytes. - unsigned char bLength; - /// Descriptor type (USBGenericDescriptor_INTERFACE). - unsigned char bDescriptorType; - /// Number of the interface in its configuration. - unsigned char bInterfaceNumber; - /// Value to select this alternate interface setting. - unsigned char bAlternateSetting; - /// Number of endpoints used by the inteface (excluding endpoint 0). - unsigned char bNumEndpoints; - /// Interface class code. - unsigned char bInterfaceClass; - /// Interface subclass code. - unsigned char bInterfaceSubClass; - /// Interface protocol code. - unsigned char bInterfaceProtocol; - /// Index of the interface string descriptor. - unsigned char iInterface; - -} __attribute__ ((packed)) USBInterfaceDescriptor; // GCC - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -#endif //#ifndef USBINTERFACEDESCRIPTOR_H - diff --git a/radio/bootloader/usb/common/core/USBInterfaceRequest.c b/radio/bootloader/usb/common/core/USBInterfaceRequest.c deleted file mode 100644 index 837e5f6d9..000000000 --- a/radio/bootloader/usb/common/core/USBInterfaceRequest.c +++ /dev/null @@ -1,69 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBInterfaceRequest - - About: Purpose - Implementation of USBInterfaceRequest class methods. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBInterfaceRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Indicates which interface is targetted by a GET_INTERFACE or -/// SET_INTERFACE request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Interface number. -//------------------------------------------------------------------------------ -unsigned char USBInterfaceRequest_GetInterface(const USBGenericRequest *request) -{ - return (USBGenericRequest_GetIndex(request) & 0xFF); -} - -//------------------------------------------------------------------------------ -/// Indicates the new alternate setting that the interface targetted by a -/// SET_INTERFACE request should use. -/// \param request Pointer to a USBGenericRequest instance. -/// \return New active setting for the interface. -//------------------------------------------------------------------------------ -unsigned char USBInterfaceRequest_GetAlternateSetting( - const USBGenericRequest *request) -{ - return (USBGenericRequest_GetValue(request) & 0xFF); -} - diff --git a/radio/bootloader/usb/common/core/USBInterfaceRequest.h b/radio/bootloader/usb/common/core/USBInterfaceRequest.h deleted file mode 100644 index dff2bdf8f..000000000 --- a/radio/bootloader/usb/common/core/USBInterfaceRequest.h +++ /dev/null @@ -1,68 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definitions for manipulating SET_INTERFACE and GET_INTERFACE request. - - !!!Usage - - -# After a SET_INTERFACE request has been received, retrieve the - target interface using USBInterfaceRequest_GetInterface and its - new alternate setting with USBInterfaceRequest_GetAlternateSetting. - -# After a GET_INTERFACE request has been received, retrieve the target - interface using USBInterfaceRequest_GetInterface. - -*/ - -#ifndef USBINTERFACEREQUEST_H -#define USBINTERFACEREQUEST_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBGenericRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char USBInterfaceRequest_GetInterface( - const USBGenericRequest *request); - - -extern unsigned char USBInterfaceRequest_GetAlternateSetting( - const USBGenericRequest *request); - -#endif //#ifndef USBINTERFACEREQUEST_H - diff --git a/radio/bootloader/usb/common/core/USBIrqHandler.c b/radio/bootloader/usb/common/core/USBIrqHandler.c deleted file mode 100644 index b5f54f2ad..000000000 --- a/radio/bootloader/usb/common/core/USBIrqHandler.c +++ /dev/null @@ -1,62 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBIrqHandler implementation - - About: Purpose - Implementation of the USB Interrupt Handler. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ -#include -#include - -#include - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -//------------------------------------------------------------------------------ -/// Call Arbitrer, device and host interrupt handler. -/// The IRQ functions are defined with weak and can be surcharged if needed. -//------------------------------------------------------------------------------ -void USB_IrqHandler( void ) -{ - // Most arbitrer interrupt - usb_general_interrupt(); - // Device interrupt - USBD_IrqHandler(); - // Host interrupt - usb_pipe_interrupt(); -} - - diff --git a/radio/bootloader/usb/common/core/USBIrqHandler.h b/radio/bootloader/usb/common/core/USBIrqHandler.h deleted file mode 100644 index 3e6771ddc..000000000 --- a/radio/bootloader/usb/common/core/USBIrqHandler.h +++ /dev/null @@ -1,52 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Implementation of the USB Interrupt Handler. - - !!!Usage - - -# The IRQ functions are defined with weak and can be surcharged if needed. - -*/ - -#ifndef USBIRQHANDLER_H -#define USBIRQHANDLER_H - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -extern void USB_IrqHandler( void ); - -#endif //#ifndef USBIRQHANDLER_H - diff --git a/radio/bootloader/usb/common/core/USBSetAddressRequest.c b/radio/bootloader/usb/common/core/USBSetAddressRequest.c deleted file mode 100644 index d955d7a87..000000000 --- a/radio/bootloader/usb/common/core/USBSetAddressRequest.c +++ /dev/null @@ -1,56 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBSetAddressRequest implementation - - About: Purpose - Implementation of the USBSetAddressRequest class. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBSetAddressRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -//------------------------------------------------------------------------------ -/// Returns the address that the device must take in response to a -/// SET_ADDRESS request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return New device address. -//------------------------------------------------------------------------------ -unsigned char USBSetAddressRequest_GetAddress(const USBGenericRequest *request) -{ - return USBGenericRequest_GetValue(request) & 0x7F; -} - diff --git a/radio/bootloader/usb/common/core/USBSetAddressRequest.h b/radio/bootloader/usb/common/core/USBSetAddressRequest.h deleted file mode 100644 index 2a73d7939..000000000 --- a/radio/bootloader/usb/common/core/USBSetAddressRequest.h +++ /dev/null @@ -1,60 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of a class for manipulating SET_ADDRESS USB requests. - - !!!Usage - - - After a SET_ADDRESS request has been received, retrive the new address - value with USBSetAddressRequest_GetAddress. -*/ - -#ifndef USBSETADDRESSREQUEST_H -#define USBSETADDRESSREQUEST_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBGenericRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char USBSetAddressRequest_GetAddress( - const USBGenericRequest *request); - -#endif //#ifndef USBSETADDRESSREQUEST_H - diff --git a/radio/bootloader/usb/common/core/USBSetConfigurationRequest.c b/radio/bootloader/usb/common/core/USBSetConfigurationRequest.c deleted file mode 100644 index 4910739bb..000000000 --- a/radio/bootloader/usb/common/core/USBSetConfigurationRequest.c +++ /dev/null @@ -1,58 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBSetConfigurationRequest implementation - - About: Purpose - Implementation of the USBSetConfigurationRequest class. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBSetConfigurationRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Returns the number of the configuration that should be set in response -/// to the given SET_CONFIGURATION request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Number of the requested configuration. -//------------------------------------------------------------------------------ -unsigned char USBSetConfigurationRequest_GetConfiguration( - const USBGenericRequest *request) -{ - return USBGenericRequest_GetValue(request); -} - diff --git a/radio/bootloader/usb/common/core/USBSetConfigurationRequest.h b/radio/bootloader/usb/common/core/USBSetConfigurationRequest.h deleted file mode 100644 index f70ad8aef..000000000 --- a/radio/bootloader/usb/common/core/USBSetConfigurationRequest.h +++ /dev/null @@ -1,61 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of a class for the Set Configuration request. - - !!!Usage - - - After a SET_CONFIGURATION request has been received, retrive the new - configuration value with USBSetConfigurationRequest_GetConfiguration. - -*/ - -#ifndef USBSETCONFIGURATIONREQUEST_H -#define USBSETCONFIGURATIONREQUEST_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBGenericRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char USBSetConfigurationRequest_GetConfiguration( - const USBGenericRequest *request); - -#endif //#ifndef USBSETCONFIGURATIONREQUEST_H - diff --git a/radio/bootloader/usb/common/core/USBStringDescriptor.h b/radio/bootloader/usb/common/core/USBStringDescriptor.h deleted file mode 100644 index e3da4b405..000000000 --- a/radio/bootloader/usb/common/core/USBStringDescriptor.h +++ /dev/null @@ -1,74 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !!!Purpose -/// -/// Definition of a class for manipulating String descriptors. -//------------------------------------------------------------------------------ - -#ifndef USBSTRINGDESCRIPTOR_H -#define USBSTRINGDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB String Descriptor definitions" -/// -/// This page lists the codes and macros for USB string descriptor definition. -/// -/// !Language IDs -/// - USBStringDescriptor_ENGLISH_US -/// -/// !String Descriptor Length -/// - USBStringDescriptor_LENGTH -/// -/// !ASCII to UNICODE convertion -/// - USBStringDescriptor_UNICODE - -/// Language ID for US english. -#define USBStringDescriptor_ENGLISH_US 0x09, 0x04 - -/// Calculates the length of a string descriptor given the number of ascii -/// characters/language IDs in it. -/// \param length The ascii format string length. -/// \return The actual data length in bytes. -#define USBStringDescriptor_LENGTH(length) ((length) * 2 + 2) -/// Converts an ascii character to its unicode representation. -/// \param ascii The ASCII character to convert -/// \return A 2-byte-array for the UNICODE based on given ASCII -#define USBStringDescriptor_UNICODE(ascii) (ascii), 0 -//------------------------------------------------------------------------------ - -#endif //#ifndef USBSTRINGDESCRIPTOR_H - diff --git a/radio/bootloader/usb/common/massstorage/MSDeviceDescriptor.h b/radio/bootloader/usb/common/massstorage/MSDeviceDescriptor.h deleted file mode 100644 index f85833ee0..000000000 --- a/radio/bootloader/usb/common/massstorage/MSDeviceDescriptor.h +++ /dev/null @@ -1,73 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Declaration of constants for using Device Descriptors with a Mass Storage -/// driver. -/// -/// !Usage -/// -/// - For a USB device: -/// -# When declaring a USBDeviceDescriptor instance, use the Mass Storage -/// codes defined in this file (see "MS device codes"). -//------------------------------------------------------------------------------ - -#ifndef MSDEVICEDESCRIPTOR_H -#define MSDEVICEDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MS device codes" -/// This page lists the class, subclass & protocol codes used by a device with -/// a Mass Storage driver. -/// -/// !Codes -/// -/// - MSDeviceDescriptor_CLASS -/// - MSDeviceDescriptor_SUBCLASS -/// - MSDeviceDescriptor_PROTOCOL - -/// Class code for a Mass Storage device. -#define MSDeviceDescriptor_CLASS 0 - -/// Subclass code for a Mass Storage device. -#define MSDeviceDescriptor_SUBCLASS 0 - -/// Protocol code for a Mass Storage device. -#define MSDeviceDescriptor_PROTOCOL 0 -//------------------------------------------------------------------------------ - -#endif //#ifndef MSDEVICEDESCRIPTOR_H - diff --git a/radio/bootloader/usb/common/massstorage/MSInterfaceDescriptor.h b/radio/bootloader/usb/common/massstorage/MSInterfaceDescriptor.h deleted file mode 100644 index b5033e24e..000000000 --- a/radio/bootloader/usb/common/massstorage/MSInterfaceDescriptor.h +++ /dev/null @@ -1,75 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Definition of several constants used when manipulating Mass Storage interface -/// descriptors. -/// -/// !Usage -/// -/// - For a USB device: -/// -# When declaring an interface descriptor for a Mass Storage device, use -/// the class, subclass and protocol codes defined here (see -/// "MS interface codes"). -//------------------------------------------------------------------------------ - -#ifndef MSINTERFACEDESCRIPTOR_H -#define MSINTERFACEDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MS interface codes" -/// This page lists the available class, subclass & protocol codes for a Mass -/// Storage interface. -/// -/// !Codes -/// -/// - MSInterfaceDescriptor_CLASS -/// - MSInterfaceDescriptor_SCSI -/// - MSInterfaceDescriptor_BULKONLY - -/// Class code for a Mass Storage interface. -#define MSInterfaceDescriptor_CLASS 0x08 - -/// Subclass code for a Mass Storage interface using the SCSI protocol. -#define MSInterfaceDescriptor_SCSI 0x06 - -/// Protocol code for a Mass Storage interface using Bulk-Only Transport. -#define MSInterfaceDescriptor_BULKONLY 0x50 -//------------------------------------------------------------------------------ - - -#endif //#ifndef MSINTERFACEDESCRIPTOR_H - diff --git a/radio/bootloader/usb/device/core/USBD.h b/radio/bootloader/usb/device/core/USBD.h deleted file mode 100644 index 27c26f229..000000000 --- a/radio/bootloader/usb/device/core/USBD.h +++ /dev/null @@ -1,275 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !!!Purpose -/// -/// Collection of methods for using the USB device controller on AT91 -/// microcontrollers. -/// -/// !!!Usage -/// -/// Please refer to the corresponding application note. -/// - "AT91 USB device framework" -/// - "USBD API" . "USBD API Methods" -//------------------------------------------------------------------------------ - -#ifndef USBD_H -#define USBD_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -// #include -#include -#include - -//------------------------------------------------------------------------------ -// Compile Options -//------------------------------------------------------------------------------ - -/// Compile option for HS or OTG, use DMA. Remove this define for not use DMA. -#if defined(CHIP_USB_OTGHS) || defined(CHIP_USB_UDPHS) -#define DMA -#endif - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB device API return values" -/// -/// This page lists the return values of the USB %device driver API -/// -/// !Return codes -/// - USBD_STATUS_SUCCESS -/// - USBD_STATUS_LOCKED -/// - USBD_STATUS_ABORTED -/// - USBD_STATUS_RESET - -/// Indicates the operation was successful. -#define USBD_STATUS_SUCCESS 0 -/// Endpoint/device is already busy. -#define USBD_STATUS_LOCKED 1 -/// Operation has been aborted. -#define USBD_STATUS_ABORTED 2 -/// Operation has been aborted because the device has been reset. -#define USBD_STATUS_RESET 3 -/// Part ot operation successfully done. -#define USBD_STATUS_PARTIAL_DONE 4 -/// Operation failed because parameter error -#define USBD_STATUS_INVALID_PARAMETER 5 -/// Operation failed because in unexpected state -#define USBD_STATUS_WRONG_STATE 6 -/// Operation failed because HW not supported -#define USBD_STATUS_HW_NOT_SUPPORTED 0xFE -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB device states" -/// -/// This page lists the %device states of the USB %device driver. -/// -/// !States -/// - USBD_STATE_SUSPENDED -/// - USBD_STATE_ATTACHED -/// - USBD_STATE_POWERED -/// - USBD_STATE_DEFAULT -/// - USBD_STATE_ADDRESS -/// - USBD_STATE_CONFIGURED - -/// The device is currently suspended. -#define USBD_STATE_SUSPENDED 0 -/// USB cable is plugged into the device. -#define USBD_STATE_ATTACHED 1 -/// Host is providing +5V through the USB cable. -#define USBD_STATE_POWERED 2 -/// Device has been reset. -#define USBD_STATE_DEFAULT 3 -/// The device has been given an address on the bus. -#define USBD_STATE_ADDRESS 4 -/// A valid configuration has been selected. -#define USBD_STATE_CONFIGURED 5 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB device LEDs" -/// -/// This page lists the LEDs used in the USB %device driver. -/// -/// !LEDs -/// - USBD_LEDPOWER -/// - USBD_LEDUSB -/// - USBD_LEDOTHER - -/// LED for indicating that the device is powered. -#define USBD_LEDPOWER 0 -/// LED for indicating USB activity. -#define USBD_LEDUSB 1 -/// LED for custom usage. -#define USBD_LEDOTHER 2 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Buffer struct used for multi-buffer-listed transfer. -/// The driver can process 255 bytes of buffers or buffer list window. -//------------------------------------------------------------------------------ -typedef struct _USBDTransferBuffer { - /// Pointer to frame buffer - unsigned char * pBuffer; - /// Size of the frame (up to 64K-1) - unsigned short size; - /// Bytes transferred - unsigned short transferred; - /// Bytes in FIFO - unsigned short buffered; - /// Bytes remaining - unsigned short remaining; -} USBDTransferBuffer; - -#ifdef __ICCARM__ // IAR -#define __attribute__(...) // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -/// Struct used for USBD DMA Link List Transfer Descriptor, must be 16-bytes -/// aligned. -/// (For USB, DMA transfer is linked to EPs and FIFO address is EP defined) -//------------------------------------------------------------------------------ -typedef struct _USBDDmaDescriptor { - /// Pointer to Next Descriptor - void* pNxtDesc; - /// Pointer to data buffer address - void* pDataAddr; - /// DMA Control setting register value - unsigned int ctrlSettings:8, /// Control settings - reserved:8, /// Not used - bufferLength:16; /// Length of buffer - /// Loaded to DMA register, OK to modify - unsigned int used; -} __attribute__((aligned(16))) USBDDmaDescriptor; - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -/// Callback used by transfer functions (USBD_Read & USBD_Write) to notify -/// that a transaction is complete. -//------------------------------------------------------------------------------ -typedef void (*TransferCallback)(void *pArg, - unsigned char status, - unsigned int transferred, - unsigned int remaining); - -//------------------------------------------------------------------------------ -/// Callback used by MBL transfer functions (USBD_Read & USBD_Write) to notify -/// that a transaction is complete. -/// \param pArg Pointer to callback arguments. -/// \param status USBD status. -/// \param nbFreed Number of buffers that is freed since last callback. -//------------------------------------------------------------------------------ -typedef void (*MblTransferCallback)(void *pArg, - unsigned char status, - unsigned int nbFreed); - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern void USBD_IrqHandler(void); - -extern void USBD_Init(void); - -extern void USBD_ConfigureSpeed(unsigned char forceFS); - -extern void USBD_Connect(void); - -extern void USBD_Disconnect(void); - -extern char USBD_Write( - unsigned char bEndpoint, - const void *pData, - unsigned int size, - TransferCallback callback, - void *pArg); - -extern char USBD_MblWrite( - unsigned char bEndpoint, - void * pMbl, - unsigned short wListSize, - unsigned char bCircList, - unsigned short wStartNdx, - MblTransferCallback fCallback, - void * pArgument); - -extern char USBD_MblReuse( - unsigned char bEndpoint, - unsigned char * pNewBuffer, - unsigned short wNewSize); - -extern char USBD_Read( - unsigned char bEndpoint, - void *pData, - unsigned int dLength, - TransferCallback fCallback, - void *pArg); - -extern unsigned char USBD_Stall(unsigned char bEndpoint); - -extern void USBD_Halt(unsigned char bEndpoint); - -extern void USBD_Unhalt(unsigned char bEndpoint); - -extern void USBD_ConfigureEndpoint(const USBEndpointDescriptor *pDescriptor); - -extern unsigned char USBD_IsHalted(unsigned char bEndpoint); - -extern void USBD_RemoteWakeUp(void); - -extern void USBD_SetAddress(unsigned char address); - -extern void USBD_SetConfiguration(unsigned char cfgnum); - -extern unsigned char USBD_GetState(void); - -extern unsigned char USBD_IsHighSpeed(void); - -extern void USBD_Test(unsigned char bIndex); - -#endif //#ifndef USBD_H - diff --git a/radio/bootloader/usb/device/core/USBDCallbacks.c b/radio/bootloader/usb/device/core/USBDCallbacks.c deleted file mode 100644 index cc0463a2e..000000000 --- a/radio/bootloader/usb/device/core/USBDCallbacks.c +++ /dev/null @@ -1,81 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBDCallbacks.h" -#include "USBD.h" -#include -#include -#include "debug.h" - -void USBDCallbacks_Initialized(void) -{ - UDP->UDP_ICR = 0x00000200 ; // CLear RXRSM flag - NVIC_EnableIRQ(UDP_IRQn); -} - -#if 0 -void USBDCallbacks_RequestReceived(const USBGenericRequest *pRequest) -{ - // Does nothing -} -#endif - -void USBDCallbacks_Reset(void) -{ - // Does nothing -} - -void USBDCallbacks_Resumed(void) -{ - // Does nothing -} - -void USBDCallbacks_Suspended(void) -{ - // Does nothing -} - -#if 0 -void USBDDriverCallbacks_ConfigurationChanged(unsigned char cfgnum) -{ - TRACE_INFO_WP("ConfigurationChanged "); -} -#endif - -void USBDDriverCallbacks_InterfaceSettingChanged( - unsigned char interface, - unsigned char setting) -{ - // TRACE_INFO_WP("InterfaceSettingChanged "); -} - diff --git a/radio/bootloader/usb/device/core/USBDCallbacks.h b/radio/bootloader/usb/device/core/USBDCallbacks.h deleted file mode 100644 index e18bece3e..000000000 --- a/radio/bootloader/usb/device/core/USBDCallbacks.h +++ /dev/null @@ -1,65 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definitions of callbacks used by the USBD API to notify the user - application of incoming events. These functions are declared as 'weak', - so they can be re-implemented elsewhere in the application in a - transparent way. -*/ - -#ifndef USBDCALLBACKS_H -#define USBDCALLBACKS_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern void USBDCallbacks_Initialized(void); - -extern void USBDCallbacks_Reset(void); - -extern void USBDCallbacks_Suspended(void); - -extern void USBDCallbacks_Resumed(void); - -extern void USBDCallbacks_RequestReceived(const USBGenericRequest *request); - -#endif //#ifndef USBDCALLBACKS_H - diff --git a/radio/bootloader/usb/device/core/USBDDriver.c b/radio/bootloader/usb/device/core/USBDDriver.c deleted file mode 100644 index 7e826435c..000000000 --- a/radio/bootloader/usb/device/core/USBDDriver.c +++ /dev/null @@ -1,753 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBDDriver.h" -#include "USBDDriverCallbacks.h" -#include "USBD.h" -#include -#include "debug.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -//------------------------------------------------------------------------------ -// Local functions -//------------------------------------------------------------------------------ -#if defined(CHIP_USB_OTGHS) -static unsigned char otg_features_supported = 0; -#endif - -//------------------------------------------------------------------------------ -/// Send a NULL packet -//------------------------------------------------------------------------------ -static void TerminateCtrlInWithNull(void *pArg, - unsigned char status, - unsigned int transferred, - unsigned int remaining) -{ - USBD_Write(0, // Endpoint #0 - 0, // No data buffer - 0, // No data buffer - (TransferCallback) 0, - (void *) 0); -} - -//------------------------------------------------------------------------------ -/// Configures the device by setting it into the Configured state and -/// initializing all endpoints. -/// \param pDriver Pointer to a USBDDriver instance. -/// \param cfgnum Configuration number to set. -//------------------------------------------------------------------------------ -static void SetConfiguration(USBDDriver *pDriver, unsigned char cfgnum) -{ - USBEndpointDescriptor *pEndpoints[CHIP_USB_NUMENDPOINTS+1]; - const USBConfigurationDescriptor *pConfiguration; - - // Use different descriptor depending on device speed - if (USBD_IsHighSpeed()) { - - pConfiguration = pDriver->pDescriptors->pHsConfiguration; - } - else { - - pConfiguration = pDriver->pDescriptors->pFsConfiguration; - } - - // Set & save the desired configuration - USBD_SetConfiguration(cfgnum); - pDriver->cfgnum = cfgnum; - - // If the configuration is not 0, configure endpoints - if (cfgnum != 0) { - - // Parse configuration to get endpoint descriptors - USBConfigurationDescriptor_Parse(pConfiguration, 0, pEndpoints, 0); - - // Configure endpoints - int i = 0; - while (pEndpoints[i] != 0) { - - USBD_ConfigureEndpoint(pEndpoints[i]); - i++; - } - } - // Should be done before send the ZLP - USBDDriverCallbacks_ConfigurationChanged(cfgnum); - - // Acknowledge the request - USBD_Write(0, // Endpoint #0 - 0, // No data buffer - 0, // No data buffer - (TransferCallback) 0, - (void *) 0); -} - -//------------------------------------------------------------------------------ -/// Sends the current configuration number to the host. -/// \param pDriver Pointer to a USBDDriver instance. -//------------------------------------------------------------------------------ -static void GetConfiguration(const USBDDriver *pDriver) -{ - USBD_Write(0, &(pDriver->cfgnum), 1, 0, 0); -} - -//------------------------------------------------------------------------------ -/// Sends the current status of the device to the host. -/// \param pDriver Pointer to a USBDDriver instance. -//------------------------------------------------------------------------------ -static void GetDeviceStatus(const USBDDriver *pDriver) -{ - static unsigned short data; - const USBConfigurationDescriptor *pConfiguration; - - data = 0; - // Use different configuration depending on device speed - if (USBD_IsHighSpeed()) { - - pConfiguration = pDriver->pDescriptors->pHsConfiguration; - } - else { - - pConfiguration = pDriver->pDescriptors->pFsConfiguration; - } - - // Check current configuration for power mode (if device is configured) - if (pDriver->cfgnum != 0) { - - if (USBConfigurationDescriptor_IsSelfPowered(pConfiguration)) { - - data |= 1; - } - } - - // Check if remote wake-up is enabled - if (pDriver->isRemoteWakeUpEnabled) { - - data |= 2; - } - - // Send the device status - USBD_Write(0, &data, 2, 0, 0); -} - -//------------------------------------------------------------------------------ -/// Sends the current status of an endpoints to the USB host. -/// \param bEndpoint Endpoint number. -//------------------------------------------------------------------------------ -static void GetEndpointStatus(unsigned char bEndpoint) -{ - static unsigned short data; - - data = 0; - // Check if the endpoint exists - if (bEndpoint > CHIP_USB_NUMENDPOINTS) { - - USBD_Stall(0); - } - else { - - // Check if the endpoint if currently halted - if (USBD_IsHalted(bEndpoint)) { - - data = 1; - } - - // Send the endpoint status - USBD_Write(0, &data, 2, 0, 0); - } -} - -//------------------------------------------------------------------------------ -/// Sends the requested USB descriptor to the host if available, or STALLs the -/// request. -/// \param pDriver Pointer to a USBDDriver instance. -/// \param type Type of the requested descriptor -/// \param index Index of the requested descriptor. -/// \param length Maximum number of bytes to return. -//------------------------------------------------------------------------------ -static void GetDescriptor( - const USBDDriver *pDriver, - unsigned char type, - unsigned char indexRDesc, - unsigned int length) -{ - const USBDeviceDescriptor *pDevice; - const USBConfigurationDescriptor *pConfiguration; - const USBDeviceQualifierDescriptor *pQualifier; - const USBConfigurationDescriptor *pOtherSpeed; - const USBGenericDescriptor **pStrings = - (const USBGenericDescriptor **) pDriver->pDescriptors->pStrings; - const USBGenericDescriptor *pString; - unsigned char numStrings = pDriver->pDescriptors->numStrings; - unsigned char terminateWithNull = 0; - - // Use different set of descriptors depending on device speed - if (USBD_IsHighSpeed()) { - - TRACE_DEBUG("HS "); - pDevice = pDriver->pDescriptors->pHsDevice; - pConfiguration = pDriver->pDescriptors->pHsConfiguration; - pQualifier = pDriver->pDescriptors->pHsQualifier; - pOtherSpeed = pDriver->pDescriptors->pHsOtherSpeed; - } - else { - - TRACE_DEBUG("FS "); - pDevice = pDriver->pDescriptors->pFsDevice; - pConfiguration = pDriver->pDescriptors->pFsConfiguration; - pQualifier = pDriver->pDescriptors->pFsQualifier; - pOtherSpeed = pDriver->pDescriptors->pFsOtherSpeed; - } - - // Check the descriptor type - switch (type) { - - case USBGenericDescriptor_DEVICE: - TRACE_INFO_WP("Dev "); - - // Adjust length and send descriptor - if (length > USBGenericDescriptor_GetLength((USBGenericDescriptor *) pDevice)) { - - length = USBGenericDescriptor_GetLength((USBGenericDescriptor *) pDevice); - } - USBD_Write(0, pDevice, length, 0, 0); - break; - - case USBGenericDescriptor_CONFIGURATION: - TRACE_INFO_WP("Cfg "); - - // Adjust length and send descriptor - if (length > USBConfigurationDescriptor_GetTotalLength(pConfiguration)) { - - length = USBConfigurationDescriptor_GetTotalLength(pConfiguration); - terminateWithNull = ((length % pDevice->bMaxPacketSize0) == 0); - } - USBD_Write(0, - pConfiguration, - length, - terminateWithNull ? TerminateCtrlInWithNull : 0, - 0); - break; - - case USBGenericDescriptor_DEVICEQUALIFIER: - TRACE_INFO_WP("Qua "); - - // Check if descriptor exists - if (!pQualifier) { - - USBD_Stall(0); - } - else { - - // Adjust length and send descriptor - if (length > USBGenericDescriptor_GetLength((USBGenericDescriptor *) pQualifier)) { - - length = USBGenericDescriptor_GetLength((USBGenericDescriptor *) pQualifier); - } - USBD_Write(0, pQualifier, length, 0, 0); - } - break; - - case USBGenericDescriptor_OTHERSPEEDCONFIGURATION: - TRACE_INFO_WP("OSC "); - - // Check if descriptor exists - if (!pOtherSpeed) { - - USBD_Stall(0); - } - else { - - // Adjust length and send descriptor - if (length > USBConfigurationDescriptor_GetTotalLength(pOtherSpeed)) { - - length = USBConfigurationDescriptor_GetTotalLength(pOtherSpeed); - terminateWithNull = ((length % pDevice->bMaxPacketSize0) == 0); - } - USBD_Write(0, - pOtherSpeed, - length, - terminateWithNull ? TerminateCtrlInWithNull : 0, - 0); - } - break; - - case USBGenericDescriptor_STRING: - TRACE_INFO_WP("Str%d ", indexRDesc); - - // Check if descriptor exists - if (indexRDesc > numStrings) { - - USBD_Stall(0); - } - else { - - pString = pStrings[indexRDesc]; - - // Adjust length and send descriptor - if (length > USBGenericDescriptor_GetLength(pString)) { - - length = USBGenericDescriptor_GetLength(pString); - terminateWithNull = ((length % pDevice->bMaxPacketSize0) == 0); - } - USBD_Write(0, - pString, - length, - terminateWithNull ? TerminateCtrlInWithNull : 0, - 0); - } - break; - - default: - TRACE_WARNING( - "USBDDriver_GetDescriptor: Unknown descriptor type (%d)\n\r", - type); - USBD_Stall(0); - } -} - -//------------------------------------------------------------------------------ -/// Sets the active setting of the given interface if the configuration supports -/// it; otherwise, the control pipe is STALLed. If the setting of an interface -/// changes. -/// \parma pDriver Pointer to a USBDDriver instance. -/// \parma infnum Interface number. -/// \parma setting New active setting for the interface. -//------------------------------------------------------------------------------ -static void SetInterface( - USBDDriver *pDriver, - unsigned char infnum, - unsigned char setting) -{ - // Make sure alternate settings are supported - if (!pDriver->pInterfaces) { - - USBD_Stall(0); - } - else { - - // Change the current setting of the interface and trigger the callback - // if necessary - if (pDriver->pInterfaces[infnum] != setting) { - - pDriver->pInterfaces[infnum] = setting; - USBDDriverCallbacks_InterfaceSettingChanged(infnum, setting); - } - - // Acknowledge the request - USBD_Write(0, 0, 0, 0, 0); - } -} - -//------------------------------------------------------------------------------ -/// Sends the currently active setting of the given interface to the USB -/// host. If alternate settings are not supported, this function STALLs the -/// control pipe. -/// \param pDriver Pointer to a USBDDriver instance. -/// \param infnum Interface number. -//------------------------------------------------------------------------------ -static void GetInterface( - const USBDDriver *pDriver, - unsigned char infnum) -{ - // Make sure alternate settings are supported, or STALL the control pipe - if (!pDriver->pInterfaces) { - - USBD_Stall(0); - } - else { - - // Sends the current interface setting to the host - USBD_Write(0, &(pDriver->pInterfaces[infnum]), 1, 0, 0); - } -} - -#if defined(CHIP_USB_UDPHS) || defined(CHIP_USB_OTGHS) -//------------------------------------------------------------------------------ -// Performs the selected test on the USB device (high-speed only). -// \param test Test selector value. -//------------------------------------------------------------------------------ -static void USBDDriver_Test(unsigned char test) -{ - TRACE_DEBUG("UDPHS_Test\n\r"); - - // the lower byte of wIndex must be zero - // the most significant byte of wIndex is used to specify the specific test mode - switch (test) { - case USBFeatureRequest_TESTPACKET: - //Test mode Test_Packet: - //Upon command, a port must repetitively transmit the following test packet until - //the exit action is taken. This enables the testing of rise and fall times, eye - //patterns, jitter, and any other dynamic waveform specifications. - //The test packet is made up by concatenating the following strings. - //(Note: For J/K NRZI data, and for NRZ data, the bit on the left is the first one - //transmitted. S indicates that a bit stuff occurs, which inserts an extra NRZI data bit. - //* N is used to indicate N occurrences of a string of bits or symbols.) - //A port in Test_Packet mode must send this packet repetitively. The inter-packet timing - //must be no less than the minimum allowable inter-packet gap as defined in Section 7.1.18 and - //no greater than 125 us. - // Send ZLP - USBD_Test(USBFeatureRequest_TESTSENDZLP); - // Tst PACKET - USBD_Test(USBFeatureRequest_TESTPACKET); - while (1); - //break; not reached - - case USBFeatureRequest_TESTJ: - //Test mode Test_J: - //Upon command, a ports transceiver must enter the high-speed J state and remain in that - //state until the exit action is taken. This enables the testing of the high output drive - //level on the D+ line. - // Send ZLP - USBD_Test(USBFeatureRequest_TESTSENDZLP); - // Tst J - USBD_Test(USBFeatureRequest_TESTJ); - while (1); - //break; not reached - - case USBFeatureRequest_TESTK: - //Test mode Test_K: - //Upon command, a ports transceiver must enter the high-speed K state and remain in - //that state until the exit action is taken. This enables the testing of the high output drive - //level on the D- line. - // Send a ZLP - USBD_Test(USBFeatureRequest_TESTSENDZLP); - USBD_Test(USBFeatureRequest_TESTK); - while (1); - //break; not reached - - case USBFeatureRequest_TESTSE0NAK: - //Test mode Test_SE0_NAK: - //Upon command, a ports transceiver must enter the high-speed receive mode - //and remain in that mode until the exit action is taken. This enables the testing - //of output impedance, low level output voltage, and loading characteristics. - //In addition, while in this mode, upstream facing ports (and only upstream facing ports) - //must respond to any IN token packet with a NAK handshake (only if the packet CRC is - //determined to be correct) within the normal allowed device response time. This enables testing of - //the device squelch level circuitry and, additionally, provides a general purpose stimulus/response - //test for basic functional testing. - // Send a ZLP - USBD_Test(USBFeatureRequest_TESTSENDZLP); - // Test SE0_NAK - USBD_Test(USBFeatureRequest_TESTSE0NAK); - while (1); - //break; not reached - - default: - USBD_Stall(0); - break; - - } - // The exit action is to power cycle the device. - // The device must be disconnected from the host -} -#endif - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Initializes a USBDDriver instance with a list of descriptors. If -/// interfaces can have multiple alternate settings, an array to store the -/// current setting for each interface must be provided. -/// \param pDriver Pointer to a USBDDriver instance. -/// \param pDescriptors Pointer to a USBDDriverDescriptors instance. -/// \param pInterfaces Pointer to an array for storing the current alternate -/// setting of each interface (optional). -//------------------------------------------------------------------------------ -void USBDDriver_Initialize( - USBDDriver *pDriver, - const USBDDriverDescriptors *pDescriptors, - unsigned char *pInterfaces) -{ - - pDriver->cfgnum = 0; -#if (BOARD_USB_BMATTRIBUTES == USBConfigurationDescriptor_SELFPOWERED_RWAKEUP) \ - || (BOARD_USB_BMATTRIBUTES == USBConfigurationDescriptor_BUSPOWERED_RWAKEUP) - pDriver->isRemoteWakeUpEnabled = 1; -#else - pDriver->isRemoteWakeUpEnabled = 0; -#endif - - pDriver->pDescriptors = pDescriptors; - pDriver->pInterfaces = pInterfaces; - - // Initialize interfaces array if not null - if (pInterfaces != 0) { - - memset(pInterfaces, sizeof(pInterfaces), 0); - } -} - -//------------------------------------------------------------------------------ -/// Handles the given request if it is standard, otherwise STALLs it. -/// \param pDriver Pointer to a USBDDriver instance. -/// \param pRequest Pointer to a USBGenericRequest instance. -//------------------------------------------------------------------------------ -void USBDDriver_RequestHandler( - USBDDriver *pDriver, - const USBGenericRequest *pRequest) -{ - unsigned char cfgnum; - unsigned char infnum; - unsigned char eptnum; - unsigned char setting; - unsigned char type; - unsigned char indexDesc; - unsigned int length; - unsigned int address; - - TRACE_INFO_WP("Std "); - - // Check request code - switch (USBGenericRequest_GetRequest(pRequest)) { - - case USBGenericRequest_GETDESCRIPTOR: - TRACE_INFO_WP("gDesc "); - - // Send the requested descriptor - type = USBGetDescriptorRequest_GetDescriptorType(pRequest); - indexDesc = USBGetDescriptorRequest_GetDescriptorIndex(pRequest); - length = USBGenericRequest_GetLength(pRequest); - GetDescriptor(pDriver, type, indexDesc, length); - break; - - case USBGenericRequest_SETADDRESS: - TRACE_INFO_WP("sAddr "); - - // Sends a zero-length packet and then set the device address - address = USBSetAddressRequest_GetAddress(pRequest); - USBD_Write(0, 0, 0, (TransferCallback) USBD_SetAddress, (void *) address); - break; - - case USBGenericRequest_SETCONFIGURATION: - TRACE_INFO_WP("sCfg "); - - // Set the requested configuration - cfgnum = USBSetConfigurationRequest_GetConfiguration(pRequest); - SetConfiguration(pDriver, cfgnum); - break; - - case USBGenericRequest_GETCONFIGURATION: - TRACE_INFO_WP("gCfg "); - - // Send the current configuration number - GetConfiguration(pDriver); - break; - - case USBGenericRequest_GETSTATUS: - TRACE_INFO_WP("gSta "); - - // Check who is the recipient - switch (USBGenericRequest_GetRecipient(pRequest)) { - - case USBGenericRequest_DEVICE: - TRACE_INFO_WP("Dev "); - - // Send the device status - GetDeviceStatus(pDriver); - break; - - case USBGenericRequest_ENDPOINT: - TRACE_INFO_WP("Ept "); - - // Send the endpoint status - eptnum = USBGenericRequest_GetEndpointNumber(pRequest); - GetEndpointStatus(eptnum); - break; - - default: - TRACE_WARNING( - "USBDDriver_RequestHandler: Unknown recipient (%d)\n\r", - USBGenericRequest_GetRecipient(pRequest)); - USBD_Stall(0); - } - break; - - case USBGenericRequest_CLEARFEATURE: - TRACE_INFO_WP("cFeat "); - - // Check which is the requested feature - switch (USBFeatureRequest_GetFeatureSelector(pRequest)) { - - case USBFeatureRequest_ENDPOINTHALT: - TRACE_INFO_WP("Hlt "); - - // Unhalt endpoint and send a zero-length packet - USBD_Unhalt(USBGenericRequest_GetEndpointNumber(pRequest)); - USBD_Write(0, 0, 0, 0, 0); - break; - - case USBFeatureRequest_DEVICEREMOTEWAKEUP: - TRACE_INFO_WP("RmWU "); - - // Disable remote wake-up and send a zero-length packet - pDriver->isRemoteWakeUpEnabled = 0; - USBD_Write(0, 0, 0, 0, 0); - break; - - default: - TRACE_WARNING( - "USBDDriver_RequestHandler: Unknown feature selector (%d)\n\r", - USBFeatureRequest_GetFeatureSelector(pRequest)); - USBD_Stall(0); - } - break; - - case USBGenericRequest_SETFEATURE: - TRACE_INFO_WP("sFeat "); - - // Check which is the selected feature - switch (USBFeatureRequest_GetFeatureSelector(pRequest)) { - - case USBFeatureRequest_DEVICEREMOTEWAKEUP: - TRACE_INFO_WP("RmWU "); - - // Enable remote wake-up and send a ZLP - pDriver->isRemoteWakeUpEnabled = 1; - USBD_Write(0, 0, 0, 0, 0); - break; - - case USBFeatureRequest_ENDPOINTHALT: - TRACE_INFO_WP("Halt "); - // Halt endpoint - USBD_Halt(USBGenericRequest_GetEndpointNumber(pRequest)); - USBD_Write(0, 0, 0, 0, 0); - break; - -#if defined(CHIP_USB_UDPHS) || defined(CHIP_USB_OTGHS) - - case USBFeatureRequest_TESTMODE: - // 7.1.20 Test Mode Support - if ((USBGenericRequest_GetType(pRequest) == USBGenericRequest_DEVICE) - && ((USBGenericRequest_GetIndex(pRequest) & 0x000F) == 0)) { - - // Handle test request - USBDDriver_Test(USBFeatureRequest_GetTestSelector(pRequest)); - } - else { - - USBD_Stall(0); - } - break; -#endif -#if defined(CHIP_USB_OTGHS) - case USBFeatureRequest_OTG_B_HNP_ENABLE: - TRACE_INFO_WP("OTG_B_HNP_ENABLE "); - otg_features_supported |= 1<isRemoteWakeUpEnabled; -} - -#if defined(CHIP_USB_OTGHS) -//------------------------------------------------------------------------------ -/// Return OTG features supported -/// \return the OTG features -//------------------------------------------------------------------------------ -unsigned char USBDDriver_returnOTGFeatures(void) -{ - return otg_features_supported; -} - -//------------------------------------------------------------------------------ -/// Clear OTG features supported -/// \return none -//------------------------------------------------------------------------------ -void USBDDriver_clearOTGFeatures(void) -{ - otg_features_supported = 0; -} -#endif - diff --git a/radio/bootloader/usb/device/core/USBDDriver.h b/radio/bootloader/usb/device/core/USBDDriver.h deleted file mode 100644 index 7f5a0b693..000000000 --- a/radio/bootloader/usb/device/core/USBDDriver.h +++ /dev/null @@ -1,101 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - USB Device Driver class definition. - - !!!Usage - - -# Instanciate a USBDDriver object and initialize it using - USBDDriver_Initialize. - -# When a USB SETUP request is received, forward it to the standard - driver using USBDDriver_RequestHandler. - -# Check the Remote Wakeup setting via USBDDriver_IsRemoteWakeUpEnabled. -*/ - -#ifndef USBDDRIVER_H -#define USBDDRIVER_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBDDriverDescriptors.h" -#include - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// USB device driver structure, holding a list of descriptors identifying -/// the device as well as the driver current state. -//------------------------------------------------------------------------------ -typedef struct { - - /// List of descriptors used by the device. - const USBDDriverDescriptors *pDescriptors; - /// Current setting for each interface. - unsigned char *pInterfaces; - /// Current configuration number (0 -> device is not configured). - unsigned char cfgnum; - /// Indicates if remote wake up has been enabled by the host. - unsigned char isRemoteWakeUpEnabled; -#if defined(CHIP_USB_OTGHS) - /// Features supported by OTG - unsigned char otg_features_supported; -#endif -} USBDDriver; - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern void USBDDriver_Initialize( - USBDDriver *pDriver, - const USBDDriverDescriptors *pDescriptors, - unsigned char *pInterfaces); - -extern void USBDDriver_RequestHandler( - USBDDriver *pDriver, - const USBGenericRequest *pRequest); - -extern unsigned char USBDDriver_IsRemoteWakeUpEnabled(const USBDDriver *pDriver); - -#if defined(CHIP_USB_OTGHS) -extern unsigned char USBDDriver_returnOTGFeatures(void); -extern void USBDDriver_clearOTGFeatures(void); -#endif - -#endif //#ifndef USBDDRIVER_H - diff --git a/radio/bootloader/usb/device/core/USBDDriverCallbacks.h b/radio/bootloader/usb/device/core/USBDDriverCallbacks.h deleted file mode 100644 index 9393dcc51..000000000 --- a/radio/bootloader/usb/device/core/USBDDriverCallbacks.h +++ /dev/null @@ -1,61 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of several callbacks which are triggered by the USB software - driver after receiving specific requests. - - !!!Usage - - -# Re-implement the USBDDriverCallbacks_ConfigurationChanged - callback to know when the hosts changes the active configuration of - the device. - -# Re-implement the USBDDriverCallbacks_InterfaceSettingChanged - callback to get notified whenever the active setting of an interface - is changed by the host. -*/ - -#ifndef USBDDRIVERCALLBACKS_H -#define USBDDRIVERCALLBACKS_H - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern void USBDDriverCallbacks_ConfigurationChanged(unsigned char cfgnum); - -extern void USBDDriverCallbacks_InterfaceSettingChanged(unsigned char interface, - unsigned char setting); - -#endif //#ifndef USBDDRIVERCALLBACKS_H - diff --git a/radio/bootloader/usb/device/core/USBDDriverDescriptors.h b/radio/bootloader/usb/device/core/USBDDriverDescriptors.h deleted file mode 100644 index e75197bec..000000000 --- a/radio/bootloader/usb/device/core/USBDDriverDescriptors.h +++ /dev/null @@ -1,86 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of a class for declaring USB descriptors required by the - device driver. -*/ - -#ifndef USBDDRIVERDESCRIPTORS_H -#define USBDDRIVERDESCRIPTORS_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include -#include -#include - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// List of all descriptors used by a USB device driver. Each descriptor can -/// be provided in two versions: full-speed and high-speed. Devices which are -/// not high-speed capable do not need to provided high-speed descriptors and -/// the full-speed qualifier & other speed descriptors. -//------------------------------------------------------------------------------ -typedef struct { - - /// Pointer to the full-speed device descriptor. - const USBDeviceDescriptor *pFsDevice; - /// Pointer to the full-speed configuration descriptor. - const USBConfigurationDescriptor *pFsConfiguration; - /// Pointer to the full-speed qualifier descriptor. - const USBDeviceQualifierDescriptor *pFsQualifier; - /// Pointer to the full-speed other speed configuration descriptor. - const USBConfigurationDescriptor *pFsOtherSpeed; - /// Pointer to the high-speed device descriptor. - const USBDeviceDescriptor *pHsDevice; - /// Pointer to the high-speed configuration descriptor. - const USBConfigurationDescriptor *pHsConfiguration; - /// Pointer to the high-speed qualifier descriptor. - const USBDeviceQualifierDescriptor *pHsQualifier; - /// Pointer to the high-speed other speed configuration descriptor. - const USBConfigurationDescriptor *pHsOtherSpeed; - /// Pointer to the list of string descriptors. - const unsigned char **pStrings; - /// Number of string descriptors in list. - unsigned char numStrings; - -} USBDDriverDescriptors; - -#endif //#ifndef USBDDRIVERDESCRIPTORS_H - diff --git a/radio/bootloader/usb/device/core/USBD_UDP.c b/radio/bootloader/usb/device/core/USBD_UDP.c deleted file mode 100644 index c525e35bf..000000000 --- a/radio/bootloader/usb/device/core/USBD_UDP.c +++ /dev/null @@ -1,1734 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Implementation of USB device functions on a UDP controller. - - See "USBD API Methods". -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "USBD.h" -#include "USBDCallbacks.h" -#include -//#include -#include "debug.h" -//#include -//#include -#include -#include - - -//------------------------------------------------------------------------------ -// Local definitions -//------------------------------------------------------------------------------ -#define MASK_STATUS0 0xFFFFFFFC -#define MASK_STATUS1 0xFFFFFFFF - - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Enables the clock of a peripheral. The peripheral ID is used - * to identify which peripheral is targetted. - * \note The ID must NOT be shifted (i.e. 1 << ID_xxx). - * \param id Peripheral ID (ID_xxx). - */ -void PMC_EnablePeripheral(unsigned int id) -{ - // SANITY_CHECK(id < 35); - - if (id < 32) { - if ((PMC->PMC_PCSR0 & (1 << id)) == (1 << id)) { - - TRACE_DEBUG("PMC_EnablePeripheral: clock of peripheral" " %u is already enabled\n\r", id); - } - else { - PMC->PMC_PCER0 = 1 << id; - } - } - else { - id -= 32; - if ((PMC->PMC_PCSR1 & (1 << id)) == (1 << id)) { - - TRACE_DEBUG("PMC_EnablePeripheral: clock of peripheral" " %u is already enabled\n\r", id + 32); - } - else { - PMC->PMC_PCER1 = 1 << id; - } - } -} - -/** - * \brief Disables the clock of a peripheral. The peripheral ID is used - * to identify which peripheral is targetted. - * \note The ID must NOT be shifted (i.e. 1 << ID_xxx). - * \param id Peripheral ID (ID_xxx). - */ -void PMC_DisablePeripheral(unsigned int id) -{ - // SANITY_CHECK(id < 35); - if (id < 32) { - if ((PMC->PMC_PCSR0 & (1 << id)) != (1 << id)) { - TRACE_DEBUG("PMC_DisablePeripheral: clock of peripheral" " %u is not enabled\n\r", id); - } - else { - PMC->PMC_PCDR0 = 1 << id; - } - } - else { - id -= 32; - if ((PMC->PMC_PCSR1 & (1 << id)) != (1 << id)) { - TRACE_DEBUG("PMC_DisablePeripheral: clock of peripheral" " %u is not enabled\n\r", id + 32); - } - else { - PMC->PMC_PCDR1 = 1 << id; - } - } -} - -/** - * \brief Enable all the periph clock via PMC - */ -void PMC_EnableAllPeripherals(void) -{ - PMC->PMC_PCER0 = MASK_STATUS0; - while( (PMC->PMC_PCSR0 & MASK_STATUS0) != MASK_STATUS0); - PMC->PMC_PCER1 = MASK_STATUS1; - while( (PMC->PMC_PCSR1 & MASK_STATUS1) != MASK_STATUS1); - TRACE_DEBUG("Enable all periph clocks\n\r"); -} -/** - * \brief Disable all the periph clock via PMC - */ -void PMC_DisableAllPeripherals(void) -{ - PMC->PMC_PCDR0 = MASK_STATUS0; - while((PMC->PMC_PCSR0 & MASK_STATUS0) != 0); - PMC->PMC_PCDR1 = MASK_STATUS1; - while((PMC->PMC_PCSR1 & MASK_STATUS1) != 0); - TRACE_DEBUG("Disable all periph clocks\n\r"); -} - -/** - * \brief Get Periph Status for the given peripheral ID. - * \param id Peripheral ID (ID_xxx). - */ -unsigned int PMC_IsPeriphEnabled(unsigned int id) -{ - // SANITY_CHECK(id < 35); - - if (id < 32) { - return (PMC->PMC_PCSR0 & (1 << id)); - } - else { - return (PMC->PMC_PCSR1 & (1 << (id - 32))); - } -} - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "UDP register field values" -/// -/// This page lists the initialize values of UDP registers. -/// -/// !Values -/// - UDP_RXDATA - -/// Bit mask for both banks of the UDP_CSR register. -#define UDP_CSR_RXDATA_BK (UDP_CSR_RX_DATA_BK0 | UDP_CSR_RX_DATA_BK1) -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "Endpoint states" -/// -/// This page lists the endpoint states. -/// -/// !States -// - UDP_ENDPOINT_DISABLED -// - UDP_ENDPOINT_HALTED -// - UDP_ENDPOINT_IDLE -// - UDP_ENDPOINT_SENDING -// - UDP_ENDPOINT_RECEIVING -// - UDP_ENDPOINT_SENDINGM -// - UDP_ENDPOINT_RECEIVINGM - -/// Endpoint states: Endpoint is disabled -#define UDP_ENDPOINT_DISABLED 0 -/// Endpoint states: Endpoint is halted (i.e. STALLs every request) -#define UDP_ENDPOINT_HALTED 1 -/// Endpoint states: Endpoint is idle (i.e. ready for transmission) -#define UDP_ENDPOINT_IDLE 2 -/// Endpoint states: Endpoint is sending data -#define UDP_ENDPOINT_SENDING 3 -/// Endpoint states: Endpoint is receiving data -#define UDP_ENDPOINT_RECEIVING 4 -/// Endpoint states: Endpoint is sending MBL -#define UDP_ENDPOINT_SENDINGM 5 -/// Endpoint states: Endpoint is receiving MBL -#define UDP_ENDPOINT_RECEIVINGM 6 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "UDP_CSR register access" -/// -/// This page lists the macroes to access UDP CSR register. -/// -/// !Macros -/// - CLEAR_CSR -/// - SET_CSR - -/// Bitmap for all status bits in CSR. -#define REG_NO_EFFECT_1_ALL UDP_CSR_RX_DATA_BK0 | UDP_CSR_RX_DATA_BK1 \ - |UDP_CSR_STALLSENTISOERROR | UDP_CSR_RXSETUP \ - |UDP_CSR_TXCOMP - -/// Clears the specified bit(s) in the UDP_CSR register. -/// \param endpoint The endpoint number of the CSR to process. -/// \param flags The bitmap to set to 1. -#define SET_CSR(endpoint, flags) \ - { \ - volatile unsigned int reg; \ - int timeOut = 200; \ - reg = UDP->UDP_CSR[endpoint] ; \ - reg |= REG_NO_EFFECT_1_ALL; \ - reg |= (flags); \ - UDP->UDP_CSR[endpoint] = reg; \ - while ( (UDP->UDP_CSR[endpoint] & (flags)) != (flags)) \ - { \ - if (-- timeOut <= 0) break; \ - } \ - } - -/// Sets the specified bit(s) in the UDP_CSR register. -/// \param endpoint The endpoint number of the CSR to process. -/// \param flags The bitmap to clear to 0. -#define CLEAR_CSR(endpoint, flags) \ - { \ - volatile unsigned int reg; \ - reg = UDP->UDP_CSR[endpoint]; \ - reg |= REG_NO_EFFECT_1_ALL; \ - reg &= ~(flags); \ - UDP->UDP_CSR[endpoint] = reg; \ - while ( (UDP->UDP_CSR[endpoint] & (flags)) == (flags)); \ - } -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -/// Describes an ongoing transfer on a UDP endpoint. -typedef struct { - - /// Pointer to a data buffer used for emission/reception. - char *pData; - /// Number of bytes which have been written into the UDP internal FIFO - /// buffers. - volatile int buffered; - /// Number of bytes which have been sent/received. - volatile int transferred; - /// Number of bytes which have not been buffered/transferred yet. - volatile int remaining; - /// Optional callback to invoke when the transfer completes. - volatile TransferCallback fCallback; - /// Optional argument to the callback function. - void *pArgument; -} Transfer; - -/// Describes Multi Buffer List transfer on a UDP endpoint. -typedef struct { - /// Pointer to frame list - USBDTransferBuffer *pMbl; - /// Pointer to last loaded buffer - USBDTransferBuffer *pLastLoaded; - /// List size - unsigned short listSize; - /// Current processing frame - unsigned short currBuffer; - /// First freed frame to re-use - unsigned short freedBuffer; - /// Frame setting, circle frame list - unsigned char circList; - /// All buffer listed is used - unsigned char allUsed; - /// Optional callback to invoke when the transfer completes. - MblTransferCallback fCallback; - /// Optional argument to the callback function. - void *pArgument; -} MblTransfer; - -//------------------------------------------------------------------------------ -/// Describes the state of an endpoint of the UDP controller. -//------------------------------------------------------------------------------ -typedef struct { - - /// Current endpoint state. - volatile unsigned char state; - /// Current reception bank (0 or 1). - volatile unsigned char bank; - /// Maximum packet size for the endpoint. - volatile unsigned short size; - /// Describes an ongoing transfer (if current state is either - /// or ) - union { - Transfer singleTransfer; - MblTransfer mblTransfer; - } transfer; -} Endpoint; - -//------------------------------------------------------------------------------ -// Internal variables -//------------------------------------------------------------------------------ - -/// Holds the internal state for each endpoint of the UDP. -static Endpoint endpoints[CHIP_USB_NUMENDPOINTS]; - -/// Device current state. -static unsigned char deviceState; -/// Indicates the previous device state -static unsigned char previousDeviceState; - -//------------------------------------------------------------------------------ -// Internal Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Enables the clock of the UDP peripheral. -/// \return 1 if peripheral status changed. -//------------------------------------------------------------------------------ -static unsigned char UDP_EnablePeripheralClock(void) -{ - if (!PMC_IsPeriphEnabled(ID_UDP)) { - PMC_EnablePeripheral(ID_UDP); - return 1; - } - return 0; -} - -//------------------------------------------------------------------------------ -/// Disables the UDP peripheral clock. -//------------------------------------------------------------------------------ -static inline void UDP_DisablePeripheralClock(void) -{ - PMC_DisablePeripheral(ID_UDP); -} - -//------------------------------------------------------------------------------ -/// Enables the 48MHz USB clock. -//------------------------------------------------------------------------------ -static inline void UDP_EnableUsbClock(void) -{ - REG_PMC_SCER = PMC_SCER_UDP; -} - -//------------------------------------------------------------------------------ -/// Disables the 48MHz USB clock. -//------------------------------------------------------------------------------ -static inline void UDP_DisableUsbClock(void) -{ - REG_PMC_SCDR = PMC_SCER_UDP; -} - -//------------------------------------------------------------------------------ -/// Enables the UDP transceiver. -//------------------------------------------------------------------------------ -static inline void UDP_EnableTransceiver(void) -{ - UDP->UDP_TXVC &= ~UDP_TXVC_TXVDIS; -} - -//------------------------------------------------------------------------------ -/// Disables the UDP transceiver. -//------------------------------------------------------------------------------ -static inline void UDP_DisableTransceiver(void) -{ - UDP->UDP_TXVC |= UDP_TXVC_TXVDIS; -} - -//------------------------------------------------------------------------------ -/// Handles a completed transfer on the given endpoint, invoking the -/// configured callback if any. -/// \param bEndpoint Number of the endpoint for which the transfer has completed. -/// \param bStatus Status code returned by the transfer operation -//------------------------------------------------------------------------------ -static void UDP_EndOfTransfer(unsigned char bEndpoint, char bStatus) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - - // Check that endpoint was sending or receiving data - if( (pEndpoint->state == UDP_ENDPOINT_RECEIVING) - || (pEndpoint->state == UDP_ENDPOINT_SENDING)) { - - Transfer *pTransfer = (Transfer *)&(pEndpoint->transfer); - - TRACE_DEBUG_WP("EoT "); - - // Endpoint returns in Idle state - pEndpoint->state = UDP_ENDPOINT_IDLE; - - // Invoke callback is present - if (pTransfer->fCallback != 0) { - - ((TransferCallback) pTransfer->fCallback) - (pTransfer->pArgument, - bStatus, - pTransfer->transferred, - pTransfer->remaining + pTransfer->buffered); - } - else { - TRACE_DEBUG_WP("NoCB "); - } - } - else if ( (pEndpoint->state == UDP_ENDPOINT_RECEIVINGM) - || (pEndpoint->state == UDP_ENDPOINT_SENDINGM) ) { - - MblTransfer *pTransfer = (MblTransfer*)&(pEndpoint->transfer); - - TRACE_DEBUG_WP("EoMT "); - - // Endpoint returns in Idle state - pEndpoint->state = UDP_ENDPOINT_IDLE; - // Invoke callback - if (pTransfer->fCallback != 0) { - - ((MblTransferCallback) pTransfer->fCallback) - (pTransfer->pArgument, - bStatus, - 0); - } - else { - TRACE_DEBUG_WP("NoCB "); - } - } -} - -//------------------------------------------------------------------------------ -/// Clears the correct reception flag (bank 0 or bank 1) of an endpoint -/// \param bEndpoint Index of endpoint -//------------------------------------------------------------------------------ -static void UDP_ClearRxFlag(unsigned char bEndpoint) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - - // Clear flag and change banks - if (pEndpoint->bank == 0) { - - CLEAR_CSR(bEndpoint, UDP_CSR_RX_DATA_BK0); - // Swap bank if in dual-fifo mode - if (CHIP_USB_ENDPOINTS_BANKS(bEndpoint) > 1) { - - pEndpoint->bank = 1; - } - } - else { - - CLEAR_CSR(bEndpoint, UDP_CSR_RX_DATA_BK1); - pEndpoint->bank = 0; - } -} - -//------------------------------------------------------------------------------ -/// Update multi-buffer-transfer descriptors. -/// \param pTransfer Pointer to instance MblTransfer. -/// \param size Size of bytes that processed. -/// \param forceEnd Force the buffer END. -/// \return 1 if current buffer ended. -//------------------------------------------------------------------------------ -static char UDP_MblUpdate(MblTransfer *pTransfer, - USBDTransferBuffer * pBi, - unsigned short size, - unsigned char forceEnd) -{ - // Update transfer descriptor - pBi->remaining -= size; - // Check if current buffer ended - if (pBi->remaining == 0 || forceEnd) { - - // Process to next buffer - if ((++ pTransfer->currBuffer) == pTransfer->listSize) { - if (pTransfer->circList) { - pTransfer->currBuffer = 0; - } - else { - pTransfer->allUsed = 1; - } - } - // All buffer in the list is processed - if (pTransfer->currBuffer == pTransfer->freedBuffer) { - pTransfer->allUsed = 1; - } - // Continue transfer, prepare for next operation - if (pTransfer->allUsed == 0) { - pBi = &pTransfer->pMbl[pTransfer->currBuffer]; - pBi->buffered = 0; - pBi->transferred = 0; - pBi->remaining = pBi->size; - } - return 1; - } - return 0; -} - -//------------------------------------------------------------------------------ -/// Transfers a data payload from the current tranfer buffer to the endpoint -/// FIFO -/// \param bEndpoint Number of the endpoint which is sending data. -//------------------------------------------------------------------------------ -static char UDP_MblWriteFifo(unsigned char bEndpoint) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - MblTransfer *pTransfer = (MblTransfer*)&(pEndpoint->transfer); - USBDTransferBuffer *pBi = &(pTransfer->pMbl[pTransfer->currBuffer]); - signed int size; - - volatile unsigned char * pBytes; - volatile char bufferEnd = 1; - - // Get the number of bytes to send - size = pEndpoint->size; - if (size > pBi->remaining) { - - size = pBi->remaining; - } - - TRACE_DEBUG_WP("w%d.%d ", pTransfer->currBuffer, size); - if (size == 0) { - - return 1; - } - - pTransfer->pLastLoaded = pBi; - pBytes = &(pBi->pBuffer[pBi->transferred + pBi->buffered]); - pBi->buffered += size; - bufferEnd = UDP_MblUpdate(pTransfer, pBi, size, 0); - - // Write packet in the FIFO buffer - if (size) { - signed int c8 = size >> 3; - signed int c1 = size & 0x7; - //printf("%d[%x] ", pBi->transferred, pBytes); - for (; c8; c8 --) { - UDP->UDP_FDR[bEndpoint] = *(pBytes ++); - UDP->UDP_FDR[bEndpoint] = *(pBytes ++); - UDP->UDP_FDR[bEndpoint] = *(pBytes ++); - UDP->UDP_FDR[bEndpoint] = *(pBytes ++); - - UDP->UDP_FDR[bEndpoint] = *(pBytes ++); - UDP->UDP_FDR[bEndpoint] = *(pBytes ++); - UDP->UDP_FDR[bEndpoint] = *(pBytes ++); - UDP->UDP_FDR[bEndpoint] = *(pBytes ++); - } - for (; c1; c1 --) { - UDP->UDP_FDR[bEndpoint] = *(pBytes ++); - } - } - return bufferEnd; -} -/* -//------------------------------------------------------------------------------ -/// Transfers a data payload from an endpoint FIFO to the current transfer -/// buffer, if NULL packet received, the current buffer is ENDed. -/// \param bEndpoint Endpoint number. -/// \param wPacketSize Size of received data packet -/// \return 1 if the buffer ENDed. -//------------------------------------------------------------------------------ -static char UDP_MblReadFifo(unsigned char bEndpoint, unsigned short wPacketSize) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - MblTransfer *pTransfer = (MblTransfer*)&(pEndpoint->transfer); - USBDTransferBuffer *pBi = &(pTransfer->pMbl[pTransfer->currBuffer]); - char bufferEnd; - - // Check that the requested size is not bigger than the remaining transfer - if (wPacketSize > pTransfer->remaining) { - - pTransfer->buffered += wPacketSize - pTransfer->remaining; - wPacketSize = pTransfer->remaining; - } - - // Update transfer descriptor information - pBi->transferred += wPacketSize; - bufferEnd = UDP_MblUpdate(pTransfer, - wPacketSize, - (wPacketSize < pEndpoint->size)); - - // Retrieve packet - if (wPacketSize) { - unsigned char * pBytes = &pBi->pBuffer[pBi->transferred]; - signed int c8 = wPacketSize >> 3; - signed int c1 = wPacketSize & 0x7; - for (; c8; c8 --) { - *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; - *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; - *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; - *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; - - *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; - *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; - *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; - *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; - } - for (; c1; c1 --) { - *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; - } - } - return bufferEnd; -} -*/ -//------------------------------------------------------------------------------ -/// Transfers a data payload from the current tranfer buffer to the endpoint -/// FIFO -/// \param bEndpoint Number of the endpoint which is sending data. -//------------------------------------------------------------------------------ -static void UDP_WritePayload(unsigned char bEndpoint) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - Transfer *pTransfer = (Transfer*)&(pEndpoint->transfer); - signed int size; - - // Get the number of bytes to send - size = pEndpoint->size; - if (size > pTransfer->remaining) { - - size = pTransfer->remaining; - } - - // Update transfer descriptor information - pTransfer->buffered += size; - pTransfer->remaining -= size; - - // Write packet in the FIFO buffer - while (size > 0) { - - UDP->UDP_FDR[bEndpoint] = *(pTransfer->pData); - pTransfer->pData++; - size--; - } -} - - -//------------------------------------------------------------------------------ -/// Transfers a data payload from an endpoint FIFO to the current transfer buffer -/// \param bEndpoint Endpoint number. -/// \param wPacketSize Size of received data packet -//------------------------------------------------------------------------------ -static void UDP_ReadPayload(unsigned char bEndpoint, int wPacketSize) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - Transfer *pTransfer = (Transfer*)&(pEndpoint->transfer); - - // Check that the requested size is not bigger than the remaining transfer - if (wPacketSize > pTransfer->remaining) { - - pTransfer->buffered += wPacketSize - pTransfer->remaining; - wPacketSize = pTransfer->remaining; - } - - // Update transfer descriptor information - pTransfer->remaining -= wPacketSize; - pTransfer->transferred += wPacketSize; - - // Retrieve packet - while (wPacketSize > 0) { - - *(pTransfer->pData) = (char) UDP->UDP_FDR[bEndpoint]; - pTransfer->pData++; - wPacketSize--; - } -} - -//------------------------------------------------------------------------------ -/// Received SETUP packet from endpoint 0 FIFO -/// \param pRequest Generic USB SETUP request sent over Control endpoints -//------------------------------------------------------------------------------ -static void UDP_ReadRequest(USBGenericRequest *pRequest) -{ - unsigned char *pData = (unsigned char *)pRequest; - unsigned int i; - - // Copy packet - for (i = 0; i < 8; i++) { - - *pData = (unsigned char) UDP->UDP_FDR[0]; - pData++; - } -} - -//------------------------------------------------------------------------------ -/// Reset all endpoint transfer descriptors -//------------------------------------------------------------------------------ -static void UDP_ResetEndpoints( void ) -{ - Endpoint *pEndpoint; - Transfer *pTransfer; - unsigned char bEndpoint; - - // Reset the transfer descriptor of every endpoint - for (bEndpoint = 0; bEndpoint < CHIP_USB_NUMENDPOINTS; bEndpoint++) { - - pEndpoint = &(endpoints[bEndpoint]); - pTransfer = (Transfer*)&(pEndpoint->transfer); - - // Reset endpoint transfer descriptor - pTransfer->pData = 0; - pTransfer->transferred = -1; - pTransfer->buffered = -1; - pTransfer->remaining = -1; - pTransfer->fCallback = 0; - pTransfer->pArgument = 0; - - // Reset endpoint state - pEndpoint->bank = 0; - pEndpoint->state = UDP_ENDPOINT_DISABLED; - } -} - -//------------------------------------------------------------------------------ -/// Disable all endpoints (except control endpoint 0), aborting current -/// transfers if necessary -//------------------------------------------------------------------------------ -static void UDP_DisableEndpoints( void ) - -{ - unsigned char bEndpoint; - - // Disable each endpoint, terminating any pending transfer - // Control endpoint 0 is not disabled - for (bEndpoint = 1; bEndpoint < CHIP_USB_NUMENDPOINTS; bEndpoint++) { - - UDP_EndOfTransfer(bEndpoint, USBD_STATUS_ABORTED); - endpoints[bEndpoint].state = UDP_ENDPOINT_DISABLED; - } -} - -//------------------------------------------------------------------------------ -/// Checks if an ongoing transfer on an endpoint has been completed. -/// \param bEndpoint Endpoint number. -/// \return 1 if the current transfer on the given endpoint is complete; -/// otherwise 0. -//------------------------------------------------------------------------------ -static unsigned char UDP_IsTransferFinished(unsigned char bEndpoint) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - Transfer *pTransfer = (Transfer*)&(pEndpoint->transfer); - - // Check if it is a Control endpoint - // -> Control endpoint must always finish their transfer with a zero-length - // packet - if ((UDP->UDP_CSR[bEndpoint] & UDP_CSR_EPTYPE) - == UDP_CSR_EPTYPE_CTRL) { - - return (pTransfer->buffered < pEndpoint->size); - } - // Other endpoints only need to transfer all the data - else { - - return (pTransfer->buffered <= pEndpoint->size) - && (pTransfer->remaining == 0); - } -} - -//------------------------------------------------------------------------------ -/// Endpoint interrupt handler. -/// Handle IN/OUT transfers, received SETUP packets and STALLing -/// \param bEndpoint Index of endpoint -//------------------------------------------------------------------------------ -static void UDP_EndpointHandler(unsigned char bEndpoint) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - Transfer *pTransfer = (Transfer*)&(pEndpoint->transfer); - MblTransfer *pMblt = (MblTransfer*)&(pEndpoint->transfer); - unsigned int status = UDP->UDP_CSR[bEndpoint]; - unsigned short wPacketSize; - USBGenericRequest request; - - TRACE_DEBUG_WP("E%d ", bEndpoint); - TRACE_DEBUG_WP("st:0x%X ", status); - - // Handle interrupts - // IN packet sent - if ((status & UDP_CSR_TXCOMP) != 0) { - - TRACE_DEBUG_WP("Wr "); - - // Check that endpoint was in MBL Sending state - if (pEndpoint->state == UDP_ENDPOINT_SENDINGM) { - - USBDTransferBuffer * pMbli = pMblt->pLastLoaded; - unsigned char bufferEnd = 0; - - TRACE_DEBUG_WP("TxM%d.%d ", pMblt->allUsed, pMbli->buffered); - - // End of transfer ? - if (pMblt->allUsed && pMbli->buffered == 0) { - - pMbli->transferred += pMbli->buffered; - pMbli->buffered = 0; - - // Disable interrupt - UDP->UDP_IDR = 1 << bEndpoint; - UDP_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); - CLEAR_CSR(bEndpoint, UDP_CSR_TXCOMP); - } - else { - - // Transfer remaining data - TRACE_DEBUG_WP("%d ", pEndpoint->size); - - if (pMbli->buffered > pEndpoint->size) { - pMbli->transferred += pEndpoint->size; - pMbli->buffered -= pEndpoint->size; - } - else { - pMbli->transferred += pMbli->buffered; - pMbli->buffered = 0; - } - - // Send next packet - if (CHIP_USB_ENDPOINTS_BANKS(bEndpoint) == 1) { - - // No double buffering - bufferEnd = UDP_MblWriteFifo(bEndpoint); - SET_CSR(bEndpoint, UDP_CSR_TXPKTRDY); - CLEAR_CSR(bEndpoint, UDP_CSR_TXCOMP); - } - else { - // Double buffering - SET_CSR(bEndpoint, UDP_CSR_TXPKTRDY); - CLEAR_CSR(bEndpoint, UDP_CSR_TXCOMP); - bufferEnd = UDP_MblWriteFifo(bEndpoint); - } - - if (bufferEnd && pMblt->fCallback) { - ((MblTransferCallback) pTransfer->fCallback) - (pTransfer->pArgument, - USBD_STATUS_PARTIAL_DONE, - 1); - } - } - } - // Check that endpoint was in Sending state - else if (pEndpoint->state == UDP_ENDPOINT_SENDING) { - - // End of transfer ? - if (UDP_IsTransferFinished(bEndpoint)) { - - pTransfer->transferred += pTransfer->buffered; - pTransfer->buffered = 0; - - // Disable interrupt if this is not a control endpoint - if ((status & UDP_CSR_EPTYPE) != UDP_CSR_EPTYPE_CTRL) { - - UDP->UDP_IDR = 1 << bEndpoint; - } - - UDP_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); - CLEAR_CSR(bEndpoint, UDP_CSR_TXCOMP); - } - else { - - // Transfer remaining data - TRACE_DEBUG_WP(" %d ", pEndpoint->size); - - pTransfer->transferred += pEndpoint->size; - pTransfer->buffered -= pEndpoint->size; - - // Send next packet - if (CHIP_USB_ENDPOINTS_BANKS(bEndpoint) == 1) { - - // No double buffering - UDP_WritePayload(bEndpoint); - SET_CSR(bEndpoint, UDP_CSR_TXPKTRDY); - CLEAR_CSR(bEndpoint, UDP_CSR_TXCOMP); - } - else { - // Double buffering - SET_CSR(bEndpoint, UDP_CSR_TXPKTRDY); - CLEAR_CSR(bEndpoint, UDP_CSR_TXCOMP); - UDP_WritePayload(bEndpoint); - } - } - } - else { - // Acknowledge interrupt - TRACE_ERROR("Error Wr"); - CLEAR_CSR(bEndpoint, UDP_CSR_TXCOMP); - } - } - - // OUT packet received - if ((status & UDP_CSR_RXDATA_BK) != 0) { - - TRACE_DEBUG_WP("Rd "); - - // Check that the endpoint is in Receiving state - if (pEndpoint->state != UDP_ENDPOINT_RECEIVING) { - - // Check if an ACK has been received on a Control endpoint - if (((status & UDP_CSR_EPTYPE) == UDP_CSR_EPTYPE_CTRL) - && ((status & UDP_CSR_RXBYTECNT) == 0)) { - - // Acknowledge the data and finish the current transfer - UDP_ClearRxFlag(bEndpoint); - UDP_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); - } - // Check if the data has been STALLed - else if ((status & UDP_CSR_FORCESTALL) != 0) { - - // Discard STALLed data - TRACE_DEBUG_WP("Discard "); - UDP_ClearRxFlag(bEndpoint); - } - // NAK the data - else { - - TRACE_DEBUG_WP("Nak "); - UDP->UDP_IDR = 1 << bEndpoint; - } - } - // Endpoint is in Read state - else { - - // Retrieve data and store it into the current transfer buffer - wPacketSize = (unsigned short) (status >> 16); - TRACE_DEBUG_WP("%d ", wPacketSize); - UDP_ReadPayload(bEndpoint, wPacketSize); - UDP_ClearRxFlag(bEndpoint); - - // Check if the transfer is finished - if ((pTransfer->remaining == 0) || (wPacketSize < pEndpoint->size)) { - - // Disable interrupt if this is not a control endpoint - if ((status & UDP_CSR_EPTYPE) != UDP_CSR_EPTYPE_CTRL) { - - UDP->UDP_IDR = 1 << bEndpoint; - } - UDP_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); - } - } - } - - // STALL sent - if ((status & UDP_CSR_STALLSENTISOERROR) != 0) { - - TRACE_WARNING( "Sta 0x%X [%d] ", status, bEndpoint); - - // If the endpoint is not halted, clear the STALL condition - CLEAR_CSR(bEndpoint, UDP_CSR_STALLSENTISOERROR); - if (pEndpoint->state != UDP_ENDPOINT_HALTED) { - - TRACE_WARNING( "_ " ); - CLEAR_CSR(bEndpoint, UDP_CSR_FORCESTALL); - } - } - - // SETUP packet received - if ((status & UDP_CSR_RXSETUP) != 0) { - - TRACE_DEBUG_WP("Stp "); - - // If a transfer was pending, complete it - // Handles the case where during the status phase of a control write - // transfer, the host receives the device ZLP and ack it, but the ack - // is not received by the device - if ((pEndpoint->state == UDP_ENDPOINT_RECEIVING) - || (pEndpoint->state == UDP_ENDPOINT_SENDING)) { - - UDP_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); - } - // Copy the setup packet - UDP_ReadRequest(&request); - - // Set the DIR bit before clearing RXSETUP in Control IN sequence - if (USBGenericRequest_GetDirection(&request) == USBGenericRequest_IN) { - - SET_CSR(bEndpoint, UDP_CSR_DIR); - } - // Acknowledge setup packet - CLEAR_CSR(bEndpoint, UDP_CSR_RXSETUP); - - // Forward the request to the upper layer - USBDCallbacks_RequestReceived(&request); - } - -} - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -//------------------------------------------------------------------------------ -/// USB device interrupt handler -/// Manages device resume, suspend, end of bus reset. -/// Forwards endpoint interrupts to the appropriate handler. -//------------------------------------------------------------------------------ -void USBD_IRQHandler(void) -{ - unsigned int status; - int eptnum = 0; - - // Get interrupt status - // Some interrupts may get masked depending on the device state - status = UDP->UDP_ISR; - status &= UDP->UDP_IMR; - - if (deviceState < USBD_STATE_POWERED) { - - status &= UDP_ICR_WAKEUP | UDP_ICR_RXRSM; - UDP->UDP_ICR = ~status; - } - - // Return immediately if there is no interrupt to service - if (status == 0) { - - TRACE_DEBUG_WP(".\n\r"); - return; - } - - // Toggle USB LED if the device is active - if (deviceState >= USBD_STATE_POWERED) { - - // LED_Set(USBD_LEDUSB); - } - - // Service interrupts - - //// Start Of Frame (SOF) - //if (ISSET(dStatus, UDP_ISR_SOFINT)) { - // - // TRACE_DEBUG("SOF"); - // - // // Invoke the SOF callback - // USB_StartOfFrameCallback(pUsb); - // - // // Acknowledge interrupt - // UDP->UDP_ICR = UDP_ICR_SOFINT; - // dStatus &= ~UDP_ISR_SOFINT; - //} - - // Suspend - // This interrupt is always treated last (hence the '==') - if (status == UDP_ISR_RXSUSP) { - - TRACE_INFO_WP("Susp "); - - // Don't do anything if the device is already suspended - if (deviceState != USBD_STATE_SUSPENDED) { - - // The device enters the Suspended state - // Enable wakeup - UDP->UDP_IER = UDP_IER_WAKEUP | UDP_IER_RXRSM; - - // Acknowledge interrupt - UDP->UDP_ICR = UDP_ICR_RXSUSP; - - // Switch to the Suspended state - previousDeviceState = deviceState; - deviceState = USBD_STATE_SUSPENDED; - // Invoke the Suspended callback - USBDCallbacks_Suspended(); - UDP_DisableTransceiver(); - UDP_DisablePeripheralClock(); - UDP_DisableUsbClock(); - } - } - // Resume - else if ((status & (UDP_ISR_WAKEUP | UDP_ISR_RXRSM)) != 0) { - - TRACE_INFO_WP("Res "); - - // Don't do anything if the device was not suspended - if (deviceState == USBD_STATE_SUSPENDED) { - - // The device enters its previous state - UDP_EnablePeripheralClock(); - UDP_EnableUsbClock(); - - // Enable the transceiver if the device was past the Default - // state - deviceState = previousDeviceState; - if (deviceState >= USBD_STATE_DEFAULT) { - - UDP_EnableTransceiver(); - - // Invoke the Resume callback - USBDCallbacks_Resumed(); - } - } - - // Clear and disable resume interrupts - UDP->UDP_ICR = UDP_ICR_WAKEUP | UDP_ICR_RXRSM | UDP_ICR_RXSUSP; - UDP->UDP_IDR = UDP_IDR_WAKEUP | UDP_IDR_RXRSM; - } - // End of bus reset - else if ((status & UDP_ISR_ENDBUSRES) != 0) { - - TRACE_INFO_WP("EoBRes "); - - // The device enters the Default state - deviceState = USBD_STATE_DEFAULT; - UDP_EnableTransceiver(); - UDP_ResetEndpoints(); - UDP_DisableEndpoints(); - USBD_ConfigureEndpoint(0); - - // Flush and enable the Suspend interrupt - UDP->UDP_ICR = UDP_ICR_WAKEUP | UDP_ICR_RXRSM | UDP_ICR_RXSUSP; - UDP->UDP_IER = UDP_IER_RXSUSP; - - //// Enable the Start Of Frame (SOF) interrupt if needed - //if (pUsb->pCallbacks->startOfFrame != 0) { - // - // UDP->UDP_IER = UDP_IER_SOFINT; - //} - - // Invoke the Reset callback - USBDCallbacks_Reset(); - - // Acknowledge end of bus reset interrupt - UDP->UDP_ICR = UDP_ICR_ENDBUSRES; - } - // Endpoint interrupts - else { - - while (status != 0) { - - // Check if endpoint has a pending interrupt - if ((status & (1 << eptnum)) != 0) { - - UDP_EndpointHandler(eptnum); - status &= ~(1 << eptnum); - - if (status != 0) { - - TRACE_INFO_WP("\n\r - "); - } - } - eptnum++; - } - } - - // Toggle LED back to its previous state - TRACE_DEBUG_WP("!"); - TRACE_INFO_WP("\n\r"); - if (deviceState >= USBD_STATE_POWERED) { - - // LED_Clear(USBD_LEDUSB); - } -} - -//------------------------------------------------------------------------------ -/// Configures an endpoint according to its Endpoint Descriptor. -/// \param pDescriptor Pointer to an Endpoint descriptor. -//------------------------------------------------------------------------------ -void USBD_ConfigureEndpoint(const USBEndpointDescriptor *pDescriptor) -{ - Endpoint *pEndpoint; - unsigned char bEndpoint; - unsigned char bType; - unsigned char bEndpointDir; - - // NULL descriptor -> Control endpoint 0 - if (pDescriptor == 0) { - - bEndpoint = 0; - pEndpoint = &(endpoints[bEndpoint]); - bType= USBEndpointDescriptor_CONTROL; - bEndpointDir = 0; - pEndpoint->size = CHIP_USB_ENDPOINTS_MAXPACKETSIZE(0); - } - else { - - bEndpoint = USBEndpointDescriptor_GetNumber(pDescriptor); - pEndpoint = &(endpoints[bEndpoint]); - bType = USBEndpointDescriptor_GetType(pDescriptor); - bEndpointDir = USBEndpointDescriptor_GetDirection(pDescriptor); - pEndpoint->size = USBEndpointDescriptor_GetMaxPacketSize(pDescriptor); - } - - // Abort the current transfer is the endpoint was configured and in - // Write or Read state - if ((pEndpoint->state == UDP_ENDPOINT_RECEIVING) - || (pEndpoint->state == UDP_ENDPOINT_SENDING) - || (pEndpoint->state == UDP_ENDPOINT_RECEIVINGM) - || (pEndpoint->state == UDP_ENDPOINT_SENDINGM)) { - - UDP_EndOfTransfer(bEndpoint, USBD_STATUS_RESET); - } - pEndpoint->state = UDP_ENDPOINT_IDLE; - - // Reset Endpoint Fifos - UDP->UDP_RST_EP |= (1 << bEndpoint); - UDP->UDP_RST_EP &= ~(1 << bEndpoint); - - // Configure endpoint - SET_CSR(bEndpoint, (unsigned int)UDP_CSR_EPEDS - | (bType << 8) | (bEndpointDir << 10)); - if (bType != USBEndpointDescriptor_CONTROL) { - - } - else { - - UDP->UDP_IER = (1 << bEndpoint); - } - - TRACE_INFO_WP("CfgEpt%d ", bEndpoint); -} - -//------------------------------------------------------------------------------ -/// Sends data through a USB endpoint. Sets up the transfer descriptor, -/// writes one or two data payloads (depending on the number of FIFO bank -/// for the endpoint) and then starts the actual transfer. The operation is -/// complete when all the data has been sent. -/// -/// *If the size of the buffer is greater than the size of the endpoint -/// (or twice the size if the endpoint has two FIFO banks), then the buffer -/// must be kept allocated until the transfer is finished*. This means that -/// it is not possible to declare it on the stack (i.e. as a local variable -/// of a function which returns after starting a transfer). -/// -/// \param bEndpoint Endpoint number. -/// \param pData Pointer to a buffer with the data to send. -/// \param dLength Size of the data buffer. -/// \param fCallback Optional callback function to invoke when the transfer is -/// complete. -/// \param pArgument Optional argument to the callback function. -/// \return USBD_STATUS_SUCCESS if the transfer has been started; -/// otherwise, the corresponding error status code. -//------------------------------------------------------------------------------ -char USBD_Write( unsigned char bEndpoint, - const void *pData, - unsigned int dLength, - TransferCallback fCallback, - void *pArgument ) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - Transfer *pTransfer = (Transfer*)&(pEndpoint->transfer); - - // Check that the endpoint is in Idle state - if (pEndpoint->state != UDP_ENDPOINT_IDLE) { - - return USBD_STATUS_LOCKED; - } - TRACE_DEBUG_WP("Write%d(%d) ", bEndpoint, dLength); - - // Setup the transfer descriptor - pTransfer->pData = (void *) pData; - pTransfer->remaining = dLength; - pTransfer->buffered = 0; - pTransfer->transferred = 0; - pTransfer->fCallback = fCallback; - pTransfer->pArgument = pArgument; - - // Send the first packet - pEndpoint->state = UDP_ENDPOINT_SENDING; - while((UDP->UDP_CSR[bEndpoint]&UDP_CSR_TXPKTRDY)==UDP_CSR_TXPKTRDY); - UDP_WritePayload(bEndpoint); - SET_CSR(bEndpoint, UDP_CSR_TXPKTRDY); - - // If double buffering is enabled and there is data remaining, - // prepare another packet - if ((CHIP_USB_ENDPOINTS_BANKS(bEndpoint) > 1) && (pTransfer->remaining > 0)) { - - UDP_WritePayload(bEndpoint); - } - - // Enable interrupt on endpoint - UDP->UDP_IER = 1 << bEndpoint; - - return USBD_STATUS_SUCCESS; -} - -//------------------------------------------------------------------------------ -/// Sends data frames through a USB endpoint. Sets up the transfer descriptor -/// list, writes one or two data payloads (depending on the number of FIFO bank -/// for the endpoint) and then starts the actual transfer. The operation is -/// complete when all the data has been sent. -/// -/// *If the size of the frame is greater than the size of the endpoint -/// (or twice the size if the endpoint has two FIFO banks), then the buffer -/// must be kept allocated until the frame is finished*. This means that -/// it is not possible to declare it on the stack (i.e. as a local variable -/// of a function which returns after starting a transfer). -/// -/// \param bEndpoint Endpoint number. -/// \param pMbl Pointer to a frame (USBDTransferBuffer) list that describes -/// the buffer list to send. -/// \param wListSize Size of the frame list. -/// \param bCircList Circle the list. -/// \param wStartNdx For circled list only, the first buffer index to transfer. -/// \param fCallback Optional callback function to invoke when the transfer is -/// complete. -/// \param pArgument Optional argument to the callback function. -/// \return USBD_STATUS_SUCCESS if the transfer has been started; -/// otherwise, the corresponding error status code. -/// \see USBDTransferBuffer, MblTransferCallback, USBD_MblReuse -//------------------------------------------------------------------------------ -char USBD_MblWrite( unsigned char bEndpoint, - void *pMbl, - unsigned short wListSize, - unsigned char bCircList, - unsigned short wStartNdx, - MblTransferCallback fCallback, - void *pArgument ) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - MblTransfer *pTransfer = (MblTransfer*)&(pEndpoint->transfer); - unsigned short i; - - // EP0 is not suitable for Mbl - if (bEndpoint == 0) { - - return USBD_STATUS_INVALID_PARAMETER; - } - - // Check that the endpoint is in Idle state - if (pEndpoint->state != UDP_ENDPOINT_IDLE) { - - return USBD_STATUS_LOCKED; - } - pEndpoint->state = UDP_ENDPOINT_SENDINGM; - - TRACE_DEBUG_WP("WriteM%d(0x%x,%d) ", bEndpoint, pMbl, wListSize); - - // Start from first if not circled list - if (!bCircList) wStartNdx = 0; - - // Setup the transfer descriptor - pTransfer->pMbl = (USBDTransferBuffer*)pMbl; - pTransfer->listSize = wListSize; - pTransfer->fCallback = fCallback; - pTransfer->pArgument = pArgument; - pTransfer->currBuffer = wStartNdx; - pTransfer->freedBuffer = 0; - pTransfer->pLastLoaded = &(((USBDTransferBuffer*)pMbl)[wStartNdx]); - pTransfer->circList = bCircList; - pTransfer->allUsed = 0; - - // Clear all buffer - for (i = 0; i < wListSize; i ++) { - - pTransfer->pMbl[i].transferred = 0; - pTransfer->pMbl[i].buffered = 0; - pTransfer->pMbl[i].remaining = pTransfer->pMbl[i].size; - } - - // Send the first packet - while((UDP->UDP_CSR[bEndpoint]&UDP_CSR_TXPKTRDY)==UDP_CSR_TXPKTRDY); - UDP_MblWriteFifo(bEndpoint); - SET_CSR(bEndpoint, UDP_CSR_TXPKTRDY); - - // If double buffering is enabled and there is data remaining, - // prepare another packet - if ((CHIP_USB_ENDPOINTS_BANKS(bEndpoint) > 1) - && (pTransfer->pMbl[pTransfer->currBuffer].remaining > 0)) { - - UDP_MblWriteFifo(bEndpoint); - } - - // Enable interrupt on endpoint - UDP->UDP_IER = 1 << bEndpoint; - - return USBD_STATUS_SUCCESS; -} - -//------------------------------------------------------------------------------ -/// Reads incoming data on an USB endpoint This methods sets the transfer -/// descriptor and activate the endpoint interrupt. The actual transfer is -/// then carried out by the endpoint interrupt handler. The Read operation -/// finishes either when the buffer is full, or a short packet (inferior to -/// endpoint maximum size) is received. -/// -/// *The buffer must be kept allocated until the transfer is finished*. -/// \param bEndpoint Endpoint number. -/// \param pData Pointer to a data buffer. -/// \param dLength Size of the data buffer in bytes. -/// \param fCallback Optional end-of-transfer callback function. -/// \param pArgument Optional argument to the callback function. -/// \return USBD_STATUS_SUCCESS if the read operation has been started; -/// otherwise, the corresponding error code. -//------------------------------------------------------------------------------ -char USBD_Read(unsigned char bEndpoint, - void *pData, - unsigned int dLength, - TransferCallback fCallback, - void *pArgument) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - Transfer *pTransfer = (Transfer*)&(pEndpoint->transfer); - - // Return if the endpoint is not in IDLE state - if (pEndpoint->state != UDP_ENDPOINT_IDLE) { - - return USBD_STATUS_LOCKED; - } - - // Endpoint enters Receiving state - pEndpoint->state = UDP_ENDPOINT_RECEIVING; - TRACE_DEBUG_WP("Read%d(%d) ", bEndpoint, dLength); - - // Set the transfer descriptor - pTransfer->pData = pData; - pTransfer->remaining = dLength; - pTransfer->buffered = 0; - pTransfer->transferred = 0; - pTransfer->fCallback = fCallback; - pTransfer->pArgument = pArgument; - - // Enable interrupt on endpoint - UDP->UDP_IER = 1 << bEndpoint; - - return USBD_STATUS_SUCCESS; -} - -//------------------------------------------------------------------------------ -/// Reuse first used/released buffer with new buffer address and size to be used -/// in transfer again. Only valid when frame list is ringed. Can be used for -/// both read & write. -/// \param bEndpoint Endpoint number. -/// \param pNewBuffer Pointer to new buffer with data to send (0 to keep last). -/// \param wNewSize Size of the data buffer -//------------------------------------------------------------------------------ -char USBD_MblReuse( unsigned char bEndpoint, - unsigned char *pNewBuffer, - unsigned short wNewSize ) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - MblTransfer *pTransfer = (MblTransfer*)&(pEndpoint->transfer); - USBDTransferBuffer *pBi = &(pTransfer->pMbl[pTransfer->freedBuffer]); - - TRACE_DEBUG_WP("MblReuse(%d), st%x, circ%d\n\r", - bEndpoint, pEndpoint->state, pTransfer->circList); - - // Only for Multi-buffer-circle list - if (bEndpoint != 0 - && (pEndpoint->state == UDP_ENDPOINT_RECEIVINGM - || pEndpoint->state == UDP_ENDPOINT_SENDINGM) - && pTransfer->circList) { - } - else { - - return USBD_STATUS_WRONG_STATE; - } - - // Check if there is freed buffer - if (pTransfer->freedBuffer == pTransfer->currBuffer - && !pTransfer->allUsed) { - - return USBD_STATUS_LOCKED; - } - - // Update transfer information - if ((++ pTransfer->freedBuffer) == pTransfer->listSize) - pTransfer->freedBuffer = 0; - if (pNewBuffer) { - pBi->pBuffer = pNewBuffer; - pBi->size = wNewSize; - } - pBi->buffered = 0; - pBi->transferred = 0; - pBi->remaining = pBi->size; - - // At least one buffer is not processed - pTransfer->allUsed = 0; - return USBD_STATUS_SUCCESS; -} - -//------------------------------------------------------------------------------ -/// Sets the HALT feature on the given endpoint (if not already in this state). -/// \param bEndpoint Endpoint number. -//------------------------------------------------------------------------------ -void USBD_Halt(unsigned char bEndpoint) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - - // Check that endpoint is enabled and not already in Halt state - if ((pEndpoint->state != UDP_ENDPOINT_DISABLED) - && (pEndpoint->state != UDP_ENDPOINT_HALTED)) { - - TRACE_DEBUG_WP("Halt%d ", bEndpoint); - - // Abort the current transfer if necessary - UDP_EndOfTransfer(bEndpoint, USBD_STATUS_ABORTED); - - // Put endpoint into Halt state - SET_CSR(bEndpoint, UDP_CSR_FORCESTALL); - pEndpoint->state = UDP_ENDPOINT_HALTED; - - // Enable the endpoint interrupt - UDP->UDP_IER = 1 << bEndpoint; - } -} - -//------------------------------------------------------------------------------ -/// Clears the Halt feature on the given endpoint. -/// \param bEndpoint Index of endpoint -//------------------------------------------------------------------------------ -void USBD_Unhalt(unsigned char bEndpoint) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - - // Check if the endpoint is enabled - if (pEndpoint->state != UDP_ENDPOINT_DISABLED) { - - TRACE_DEBUG_WP("Unhalt%d ", bEndpoint); - - // Return endpoint to Idle state - pEndpoint->state = UDP_ENDPOINT_IDLE; - - // Clear FORCESTALL flag - CLEAR_CSR(bEndpoint, UDP_CSR_FORCESTALL); - - // Reset Endpoint Fifos, beware this is a 2 steps operation - UDP->UDP_RST_EP |= 1 << bEndpoint; - UDP->UDP_RST_EP &= ~(1 << bEndpoint); - } -} - -//------------------------------------------------------------------------------ -/// Returns the current Halt status of an endpoint. -/// \param bEndpoint Index of endpoint -/// \return 1 if the endpoint is currently halted; otherwise 0 -//------------------------------------------------------------------------------ -unsigned char USBD_IsHalted(unsigned char bEndpoint) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - unsigned char status = 0; - - if (pEndpoint->state == UDP_ENDPOINT_HALTED) { - - status = 1; - } - return( status ); -} - -//------------------------------------------------------------------------------ -/// Indicates if the device is running in high or full-speed. Always returns 0 -/// since UDP does not support high-speed mode. -//------------------------------------------------------------------------------ -unsigned char USBD_IsHighSpeed(void) -{ - return 0; -} - -//------------------------------------------------------------------------------ -/// Causes the given endpoint to acknowledge the next packet it receives -/// with a STALL handshake. -/// \param bEndpoint Endpoint number. -/// \return USBD_STATUS_SUCCESS or USBD_STATUS_LOCKED. -//------------------------------------------------------------------------------ -unsigned char USBD_Stall(unsigned char bEndpoint) - -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - - // Check that endpoint is in Idle state - if (pEndpoint->state != UDP_ENDPOINT_IDLE) { - - TRACE_WARNING("UDP_Stall: Endpoint%d locked\n\r", bEndpoint); - return USBD_STATUS_LOCKED; - } - - TRACE_DEBUG_WP("Stall%d ", bEndpoint); - SET_CSR(bEndpoint, UDP_CSR_FORCESTALL); - - return USBD_STATUS_SUCCESS; -} - -//------------------------------------------------------------------------------ -/// Starts a remote wake-up procedure. -//------------------------------------------------------------------------------ -void USBD_RemoteWakeUp(void) -{ - // Device is NOT suspended - if (deviceState != USBD_STATE_SUSPENDED) { - - TRACE_WARNING("USBD_RemoteWakeUp: Device is not suspended\n\r"); - return; - } - - - UDP_EnablePeripheralClock(); - UDP_EnableUsbClock(); - UDP_EnableTransceiver(); - - TRACE_INFO_WP("RWUp "); - - // Activates a remote wakeup (edge on ESR), then clear ESR - UDP->UDP_GLB_STAT |= UDP_GLB_STAT_ESR; - UDP->UDP_GLB_STAT &= ~UDP_GLB_STAT_ESR; -} - -//------------------------------------------------------------------------------ -/// Sets the device address to the given value. -/// \param address New device address. -//------------------------------------------------------------------------------ -void USBD_SetAddress(unsigned char address) -{ - TRACE_INFO_WP("SetAddr(%d) ", address); - - // Set address - UDP->UDP_FADDR = UDP_FADDR_FEN | (address & UDP_FADDR_FADD); - - // If the address is 0, the device returns to the Default state - if (address == 0) { - - UDP->UDP_GLB_STAT = 0; - deviceState = USBD_STATE_DEFAULT; - } - // If the address is non-zero, the device enters the Address state - else { - - UDP->UDP_GLB_STAT = UDP_GLB_STAT_FADDEN; - deviceState = USBD_STATE_ADDRESS; - } -} - -//------------------------------------------------------------------------------ -/// Sets the current device configuration. -/// \param cfgnum - Configuration number to set. -//------------------------------------------------------------------------------ -void USBD_SetConfiguration(unsigned char cfgnum) -{ - TRACE_INFO_WP("SetCfg(%d) ", cfgnum); - - // If the configuration number if non-zero, the device enters the - // Configured state - if (cfgnum != 0) { - - // Enter Configured state - deviceState = USBD_STATE_CONFIGURED; - UDP->UDP_GLB_STAT |= UDP_GLB_STAT_CONFG; - } - // If the configuration number is zero, the device goes back to the Address - // state - else { - - deviceState = USBD_STATE_ADDRESS; - UDP->UDP_GLB_STAT = UDP_FADDR_FEN; - - // Abort all transfers - UDP_DisableEndpoints(); - } -} - -//------------------------------------------------------------------------------ -/// Connects the pull-up on the D+ line of the USB. -//------------------------------------------------------------------------------ -void USBD_Connect(void) -{ - unsigned char dis = UDP_EnablePeripheralClock(); - - TRACE_DEBUG("Conn "); - UDP->UDP_TXVC |= UDP_TXVC_PUON; - - if (dis) UDP_DisablePeripheralClock(); -} - -//------------------------------------------------------------------------------ -/// Disconnects the pull-up from the D+ line of the USB. -//------------------------------------------------------------------------------ -void USBD_Disconnect(void) -{ - unsigned char dis = UDP_EnablePeripheralClock(); - - TRACE_DEBUG("Disc "); - UDP->UDP_TXVC &= ~UDP_TXVC_PUON; - - if (dis) UDP_DisablePeripheralClock(); - - // Device returns to the Powered state - if (deviceState > USBD_STATE_POWERED) { - - deviceState = USBD_STATE_POWERED; - } - - if (previousDeviceState > USBD_STATE_POWERED) { - - previousDeviceState = USBD_STATE_POWERED; - } -} - -//------------------------------------------------------------------------------ -/// Initializes the USB driver. -//------------------------------------------------------------------------------ -void USBD_Init(void) -{ - TRACE_INFO_WP("USBD_Init\n\r"); - // Reset endpoint structures - UDP_ResetEndpoints(); - - // Must before TXVC access! - UDP_EnablePeripheralClock(); - - // Configure the pull-up on D+ and disconnect it - UDP->UDP_TXVC &= ~UDP_TXVC_PUON; - - // Device is in the Attached state - deviceState = USBD_STATE_SUSPENDED; - previousDeviceState = USBD_STATE_POWERED; - UDP_EnableUsbClock(); - - UDP->UDP_IDR = 0xFE; - - UDP->UDP_IER = UDP_IER_WAKEUP; - - // Configure interrupts - USBDCallbacks_Initialized(); -} - -//------------------------------------------------------------------------------ -/// Configure USB Speed, should be invoked before USB attachment. -/// \param forceFS Force to use FS mode. -//------------------------------------------------------------------------------ -void USBD_ConfigureSpeed(unsigned char forceFS) -{ -} - -//------------------------------------------------------------------------------ -/// Returns the current state of the USB device. -/// \return Device current state. -//------------------------------------------------------------------------------ -unsigned char USBD_GetState(void) -{ - return deviceState; -} - diff --git a/radio/bootloader/usb/device/massstorage/MSD.h b/radio/bootloader/usb/device/massstorage/MSD.h deleted file mode 100644 index 23a934d35..000000000 --- a/radio/bootloader/usb/device/massstorage/MSD.h +++ /dev/null @@ -1,233 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Mass Storage class definitions. -/// -/// See -/// - -/// USB Mass Storage Class Spec. Overview -/// - -/// USB Mass Storage Class Bulk-Only Transport -/// -/// !Usage -/// -/// -# Uses "MSD Requests" to check incoming requests from USB Host. -/// -# Uses "MSD Subclass Codes" and "MSD Protocol Codes" to fill %device -/// interface descriptors for a MSD %device. -/// -# Handle the incoming Bulk data with "MSD CBW Definitions" and MSCbw -/// structure. -/// -# Prepare the outgoing Bulk data with "MSD CSW Definitions" and MSCsw -/// structure. -//------------------------------------------------------------------------------ - -#ifndef MSD_H -#define MSD_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Requests" -/// This page lists MSD-specific requests ( Actually for Bulk-only protocol ). -/// -/// !Requests -/// - MSD_BULK_ONLY_RESET -/// - MSD_GET_MAX_LUN - -/// Reset the mass storage %device and its associated interface. -#define MSD_BULK_ONLY_RESET 0xFF -/// Return the maximum LUN number supported by the %device. -#define MSD_GET_MAX_LUN 0xFE -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Subclass Codes" -/// This page lists the Subclass Codes for bInterfaceSubClass field. -/// (Table 2.1, USB Mass Storage Class Spec. Overview) -/// -/// !SubClasses -/// - MSD_SUBCLASS_RBC -/// - MSD_SUBCLASS_SFF_MCC -/// - MSD_SUBCLASS_QIC -/// - MSD_SUBCLASS_UFI -/// - MSD_SUBCLASS_SFF -/// - MSD_SUBCLASS_SCSI - -/// Reduced Block Commands (RBC) T10 -#define MSD_SUBCLASS_RBC 0x01 -/// C/DVD devices -#define MSD_SUBCLASS_SFF_MCC 0x02 -/// Tape device -#define MSD_SUBCLASS_QIC 0x03 -/// Floppy disk drive (FDD) device -#define MSD_SUBCLASS_UFI 0x04 -/// Floppy disk drive (FDD) device -#define MSD_SUBCLASS_SFF 0x05 -/// SCSI transparent command set -#define MSD_SUBCLASS_SCSI 0x06 -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -/// \page "MSD Protocol Codes" -/// This page lists the Transport Protocol codes for MSD. -/// (Table 3.1, USB Mass Storage Class Spec. Overview) -/// -/// !Protocols -/// - MSD_PROTOCOL_CBI_COMPLETION -/// - MSD_PROTOCOL_CBI -/// - MSD_PROTOCOL_BULK_ONLY - -/// Control/Bulk/Interrupt (CBI) Transport (with command complete interrupt) -#define MSD_PROTOCOL_CBI_COMPLETION 0x00 -/// Control/Bulk/Interrupt (CBI) Transport (no command complete interrupt) -#define MSD_PROTOCOL_CBI 0x01 -/// Bulk-Only Transport -#define MSD_PROTOCOL_BULK_ONLY 0x50 -//------------------------------------------------------------------------------ - -/// Test unit control: -#define CTRL_NOT_READY 0x00 -#define CTRL_GOOD 0x01 -#define CTRL_BUSY 0x02 - -//------------------------------------------------------------------------------ -/// \page "MSD CBW Definitions" -/// This page lists the Command Block Wrapper (CBW) definitions. -/// -/// !Constants -/// - MSD_CBW_SIZE -/// - MSD_CBW_SIGNATURE -/// -/// !Fields -/// - MSD_CBW_DEVICE_TO_HOST - -/// Command Block Wrapper Size -#define MSD_CBW_SIZE 31 -/// 'USBC' 0x43425355 -#define MSD_CBW_SIGNATURE 0x43425355 - -/// CBW bmCBWFlags field -#define MSD_CBW_DEVICE_TO_HOST (1 << 7) -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD CSW Definitions" -/// This page lists the Command Status Wrapper (CSW) definitions. -/// -/// !Constants -/// - MSD_CSW_SIZE -/// - MSD_CSW_SIGNATURE -/// -/// !Command Block Status Values -/// (Table 5.3 , USB Mass Storage Class Bulk-Only Transport) -/// - MSD_CSW_COMMAND_PASSED -/// - MSD_CSW_COMMAND_FAILED -/// - MSD_CSW_PHASE_ERROR - -/// Command Status Wrapper Size -#define MSD_CSW_SIZE 13 -/// 'USBS' 0x53425355 -#define MSD_CSW_SIGNATURE 0x53425355 - -/// Command Passed (good status) -#define MSD_CSW_COMMAND_PASSED 0 -/// Command Failed -#define MSD_CSW_COMMAND_FAILED 1 -/// Phase Error -#define MSD_CSW_PHASE_ERROR 2 -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// Structures -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Command Block Wrapper (CBW), -/// See Table 5.1, USB Mass Storage Class Bulk-Only Transport. -/// -/// The CBW shall start on a packet boundary and shall end as a -/// short packet with exactly 31 (1Fh) bytes transferred. -//------------------------------------------------------------------------------ -typedef struct { - - /// 'USBC' 0x43425355 (little endian) - unsigned int dCBWSignature; - /// Must be the same as dCSWTag - unsigned int dCBWTag; - /// Number of bytes transfer - unsigned int dCBWDataTransferLength; - /// Indicates the directin of the transfer: - /// 0x80=IN=device-to-host, - /// 0x00=OUT=host-to-device - unsigned char bmCBWFlags; - /// bits 0->3: bCBWLUN - unsigned char bCBWLUN :4, - bReserved1:4; /// reserved - /// bits 0->4: bCBWCBLength - unsigned char bCBWCBLength:5, - bReserved2 :3; /// reserved - /// Command block - unsigned char pCommand[16]; - -} MSCbw; - -//------------------------------------------------------------------------------ -/// Command Status Wrapper (CSW), -/// See Table 5.2, USB Mass Storage Class Bulk-Only Transport. -//------------------------------------------------------------------------------ -typedef struct -{ - /// 'USBS' 0x53425355 (little endian) - unsigned int dCSWSignature; - /// Must be the same as dCBWTag - unsigned int dCSWTag; - /// For Data-Out the device shall report in the dCSWDataResidue the - /// difference between the amount of data expected as stated in the - /// dCBWDataTransferLength, and the actual amount of data processed by - /// the device. For Data-In the device shall report in the dCSWDataResidue - /// the difference between the amount of data expected as stated in the - /// dCBWDataTransferLength and the actual amount of relevant data sent by - /// the device. The dCSWDataResidue shall not exceed the value sent in the - /// dCBWDataTransferLength. - unsigned int dCSWDataResidue; - /// Indicates the success or failure of the command. - unsigned char bCSWStatus; - -} MSCsw; - -#endif //#ifndef MSD_H - diff --git a/radio/bootloader/usb/device/massstorage/MSDDStateMachine.c b/radio/bootloader/usb/device/massstorage/MSDDStateMachine.c deleted file mode 100644 index 849440730..000000000 --- a/radio/bootloader/usb/device/massstorage/MSDDStateMachine.c +++ /dev/null @@ -1,609 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//----------------------------------------------------------------------------- -// Includes -//----------------------------------------------------------------------------- - -#include "SBCMethods.h" -#include "MSDDStateMachine.h" - -//----------------------------------------------------------------------------- -// Internal functions -//----------------------------------------------------------------------------- -//----------------------------------------------------------------------------- -/// Returns the expected transfer length and direction (IN, OUT or don't care) -/// from the host point-of-view. -/// \param cbw Pointer to the CBW to examinate -/// \param pLength Expected length of command -/// \param pType Expected direction of command -//----------------------------------------------------------------------------- -static void MSDD_GetCommandInformation(MSCbw *cbw, - unsigned int *length, - unsigned char *type) -{ - // Expected host transfer direction and length - (*length) = cbw->dCBWDataTransferLength; - - if (*length == 0) { - - (*type) = MSDD_NO_TRANSFER; - } - else if ((cbw->bmCBWFlags & MSD_CBW_DEVICE_TO_HOST) != 0) { - - (*type) = MSDD_DEVICE_TO_HOST; - } - else { - - (*type) = MSDD_HOST_TO_DEVICE; - } -} - -//----------------------------------------------------------------------------- -/// Pre-processes a command by checking the differences between the host and -/// device expectations in term of transfer type and length. -/// Once one of the thirteen cases is identified, the actions to do during the -/// post-processing phase are stored in the dCase variable of the command -/// state. -/// \param pMsdDriver Pointer to a MSDDriver instance -/// \return 1 if the command is supported, false otherwise -//----------------------------------------------------------------------------- -static unsigned char MSDD_PreProcessCommand(MSDDriver *pMsdDriver) -{ - unsigned int hostLength = 0; - unsigned int deviceLength = 0; - unsigned char hostType; - unsigned char deviceType; - unsigned char isCommandSupported; - MSDCommandState *commandState = &(pMsdDriver->commandState); - MSCsw *csw = &(commandState->csw); - MSCbw *cbw = &(commandState->cbw); - MSDLun *lun = &(pMsdDriver->luns[(unsigned char) cbw->bCBWLUN]); - - // Get information about the command - // Host-side - MSDD_GetCommandInformation(cbw, &hostLength, &hostType); - - // Device-side - isCommandSupported = SBC_GetCommandInformation(cbw->pCommand, - &deviceLength, - &deviceType, - lun); - - // Initialize data residue and result status - csw->dCSWDataResidue = 0; - csw->bCSWStatus = MSD_CSW_COMMAND_PASSED; - - // Check if the command is supported - if (isCommandSupported) { - - // Identify the command case - if(hostType == MSDD_NO_TRANSFER) { - - // Case 1 (Hn = Dn) - if(deviceType == MSDD_NO_TRANSFER) { - - //TRACE_WARNING("Case 1\n\r"); - commandState->postprocess = 0; - commandState->length = 0; - } - else if(deviceType == MSDD_DEVICE_TO_HOST) { - - // Case 2 (Hn < Di) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 2\n\r"); - commandState->postprocess = MSDD_CASE_PHASE_ERROR; - commandState->length = 0; - } - else { //if(deviceType == MSDD_HOST_TO_DEVICE) { - - // Case 3 (Hn < Do) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 3\n\r"); - commandState->postprocess = MSDD_CASE_PHASE_ERROR; - commandState->length = 0; - } - } - - // Case 4 (Hi > Dn) - else if(hostType == MSDD_DEVICE_TO_HOST) { - - if(deviceType == MSDD_NO_TRANSFER) { - - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 4\n\r"); - commandState->postprocess = MSDD_CASE_STALL_IN; - commandState->length = 0; - csw->dCSWDataResidue = hostLength; - } - else if(deviceType == MSDD_DEVICE_TO_HOST) { - - TRACE_ERROR("cmd=0x%0x h=%d d=%d", cbw->pCommand[0], hostLength, deviceLength); - - if(hostLength > deviceLength) { - - // Case 5 (Hi > Di) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 5\n\r"); - commandState->postprocess = MSDD_CASE_STALL_IN; - commandState->length = deviceLength; - csw->dCSWDataResidue = hostLength - deviceLength; - } - else if(hostLength == deviceLength) { - - // Case 6 (Hi = Di) - commandState->postprocess = 0; - commandState->length = deviceLength; - } - else { //if(hostLength < deviceLength) { - - // Case 7 (Hi < Di) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 7\n\r"); - commandState->postprocess = MSDD_CASE_PHASE_ERROR; - commandState->length = hostLength; - } - } - else { //if(deviceType == MSDD_HOST_TO_DEVICE) { - - // Case 8 (Hi <> Do) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 8\n\r"); - commandState->postprocess = - MSDD_CASE_STALL_IN | MSDD_CASE_PHASE_ERROR; - commandState->length = 0; - } - } - else if(hostType == MSDD_HOST_TO_DEVICE) { - - if(deviceType == MSDD_NO_TRANSFER) { - - // Case 9 (Ho > Dn) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 9\n\r"); - commandState->postprocess = MSDD_CASE_STALL_OUT; - commandState->length = 0; - csw->dCSWDataResidue = hostLength; - } - else if(deviceType == MSDD_DEVICE_TO_HOST) { - - // Case 10 (Ho <> Di) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 10\n\r"); - commandState->postprocess = - MSDD_CASE_STALL_OUT | MSDD_CASE_PHASE_ERROR; - commandState->length = 0; - } - else { //if(deviceType == MSDD_HOST_TO_DEVICE) { - - if(hostLength > deviceLength) { - - // Case 11 (Ho > Do) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 11\n\r"); - commandState->postprocess = MSDD_CASE_STALL_OUT; -// commandState->length = deviceLength; -// csw->dCSWDataResidue = hostLength - deviceLength; - commandState->length = 0; - csw->dCSWDataResidue = deviceLength; - } - else if(hostLength == deviceLength) { - - // Case 12 (Ho = Do) - //TRACE_WARNING( - // "MSDD_PreProcessCommand: Case 12\n\r"); - commandState->postprocess = 0; - commandState->length = deviceLength; - } - else { //if(hostLength < deviceLength) { - - // Case 13 (Ho < Do) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 13\n\r"); - commandState->postprocess = MSDD_CASE_PHASE_ERROR; - commandState->length = hostLength; - } - } - } - } - - return isCommandSupported; -} - -//----------------------------------------------------------------------------- -/// Post-processes a command given the case identified during the -/// pre-processing step. -/// Depending on the case, one of the following actions can be done: -/// - Bulk IN endpoint is stalled -/// - Bulk OUT endpoint is stalled -/// - CSW status set to phase error -/// \param pMsdDriver Pointer to a MSDDriver instance -/// \return If the device is halted -//----------------------------------------------------------------------------- -static unsigned char MSDD_PostProcessCommand(MSDDriver *pMsdDriver) -{ - MSDCommandState *commandState = &(pMsdDriver->commandState); - MSCsw *csw = &(commandState->csw); - unsigned char haltStatus = 0; - - // STALL Bulk IN endpoint ? - if ((commandState->postprocess & MSDD_CASE_STALL_IN) != 0) { - - TRACE_INFO_WP("StallIn "); - MSDD_Halt(MSDD_CASE_STALL_IN); - haltStatus = 1; - } - - // STALL Bulk OUT endpoint ? - if ((commandState->postprocess & MSDD_CASE_STALL_OUT) != 0) { - - TRACE_INFO_WP("StallOut "); - MSDD_Halt(MSDD_CASE_STALL_OUT); - haltStatus = 1; - } - - // Set CSW status code to phase error ? - if ((commandState->postprocess & MSDD_CASE_PHASE_ERROR) != 0) { - - TRACE_INFO_WP("PhaseErr "); - csw->bCSWStatus = MSD_CSW_PHASE_ERROR; - } - - return haltStatus; -} - -//----------------------------------------------------------------------------- -/// Processes the latest command received by the %device. -/// \param pMsdDriver Pointer to a MSDDriver instance -/// \return 1 if the command has been completed, false otherwise. -//----------------------------------------------------------------------------- -static unsigned char MSDD_ProcessCommand(MSDDriver * pMsdDriver) -{ - unsigned char status; - MSDCommandState *commandState = &(pMsdDriver->commandState); - MSCbw *cbw = &(commandState->cbw); - MSCsw *csw = &(commandState->csw); - MSDLun *lun = &(pMsdDriver->luns[(unsigned char) cbw->bCBWLUN]); - unsigned char isCommandComplete = 0; - - // Check if LUN is valid - if (cbw->bCBWLUN > pMsdDriver->maxLun) { - - TRACE_WARNING( - "MSDD_ProcessCommand: LUN %d not exist\n\r", cbw->bCBWLUN); - status = MSDD_STATUS_ERROR; - } - else { - - // Process command - if (pMsdDriver->maxLun > 0) { - - TRACE_INFO_WP("LUN%d ", cbw->bCBWLUN); - } - - status = SBC_ProcessCommand(lun, commandState); - } - - // Check command result code - if (status == MSDD_STATUS_PARAMETER) { - - TRACE_WARNING( - "MSDD_ProcessCommand: Unknown cmd 0x%02X\n\r", - cbw->pCommand[0]); - - // Update sense data - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_ILLEGAL_REQUEST, - SBC_ASC_INVALID_FIELD_IN_CDB, - 0); - - // Result codes - csw->bCSWStatus = MSD_CSW_COMMAND_FAILED; - isCommandComplete = 1; - - // stall the request, IN or OUT - if (((cbw->bmCBWFlags & MSD_CBW_DEVICE_TO_HOST) == 0) - && (cbw->dCBWDataTransferLength > 0)) { - - // Stall the OUT endpoint : host to device - // MSDD_Halt(MSDD_CASE_STALL_OUT); - commandState->postprocess = MSDD_CASE_STALL_OUT; - TRACE_INFO_WP("StaOUT "); - } - else { - - // Stall the IN endpoint : device to host - // MSDD_Halt(MSDD_CASE_STALL_IN); - commandState->postprocess = MSDD_CASE_STALL_IN; - TRACE_INFO_WP("StaIN "); - } - } - else if (status == MSDD_STATUS_ERROR) { - - TRACE_WARNING("MSD_ProcessCommand: Cmd %x fail\n\r", - ((SBCCommand*)commandState->cbw.pCommand)->bOperationCode); - - // Update sense data - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_MEDIUM_ERROR, - SBC_ASC_INVALID_FIELD_IN_CDB, - 0); - - // Result codes - csw->bCSWStatus = MSD_CSW_COMMAND_FAILED; - isCommandComplete = 1; - } - else if (status == MSDD_STATUS_RW) { - - csw->bCSWStatus = MSD_CSW_COMMAND_FAILED; - isCommandComplete = 1; - } - else { - - // Update sense data - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_NO_SENSE, - 0, - 0); - - // Is command complete ? - if (status == MSDD_STATUS_SUCCESS) { - - isCommandComplete = 1; - } - } - - // Check if command has been completed - if (isCommandComplete) { - - TRACE_INFO_WP("Cplt "); - - // Adjust data residue - if (commandState->length != 0) { - - csw->dCSWDataResidue += commandState->length; - - // STALL the endpoint waiting for data - if ((cbw->bmCBWFlags & MSD_CBW_DEVICE_TO_HOST) == 0) { - - // Stall the OUT endpoint : host to device - // MSDD_Halt(MSDD_CASE_STALL_OUT); - commandState->postprocess = MSDD_CASE_STALL_OUT; - TRACE_INFO_WP("StaOUT "); - } - else { - - // Stall the IN endpoint : device to host - // MSDD_Halt(MSDD_CASE_STALL_IN); - commandState->postprocess = MSDD_CASE_STALL_IN; - TRACE_INFO_WP("StaIN "); - } - } - - // Reset command state - commandState->state = 0; - } - - return isCommandComplete; -} - -//----------------------------------------------------------------------------- -/// State machine for the MSD %device driver -/// \param pMsdDriver Pointer to a MSDDriver instance -//----------------------------------------------------------------------------- -void MSDD_StateMachine(MSDDriver * pMsdDriver) -{ - MSDCommandState *commandState = &(pMsdDriver->commandState); - MSCbw *cbw = &(commandState->cbw); - MSCsw *csw = &(commandState->csw); - MSDTransfer *transfer = &(commandState->transfer); - unsigned char status; - - // Identify current driver state - switch (pMsdDriver->state) { - //---------------------- - case MSDD_STATE_READ_CBW: - //---------------------- - // Start the CBW read operation - transfer->semaphore = 0; - status = MSDD_Read(cbw, - MSD_CBW_SIZE, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - - // Check operation result code - if (status == USBD_STATUS_SUCCESS) { - - // If the command was successful, wait for transfer - pMsdDriver->state = MSDD_STATE_WAIT_CBW; - } - break; - - //---------------------- - case MSDD_STATE_WAIT_CBW: - //---------------------- - // Check transfer semaphore - if (transfer->semaphore > 0) { - - // Take semaphore and terminate transfer - transfer->semaphore--; - - // Check if transfer was successful - if (transfer->status == USBD_STATUS_SUCCESS) { - - TRACE_INFO_WP("------------------------------\n\r"); - - // Process received command - pMsdDriver->state = MSDD_STATE_PROCESS_CBW; - } - else if (transfer->status == USBD_STATUS_RESET) { - - TRACE_INFO("MSDD_StateMachine: EP resetted\n\r"); - pMsdDriver->state = MSDD_STATE_READ_CBW; - } - else { - - TRACE_WARNING( - "MSDD_StateMachine: Failed to read CBW\n\r"); - pMsdDriver->state = MSDD_STATE_READ_CBW; - } - } - break; - - //------------------------- - case MSDD_STATE_PROCESS_CBW: - //------------------------- - // Check if this is a new command - if (commandState->state == 0) { - - // Copy the CBW tag - csw->dCSWTag = cbw->dCBWTag; - - // Check that the CBW is 31 bytes long - if ((transfer->transferred != MSD_CBW_SIZE) || - (transfer->remaining != 0)) { - - TRACE_WARNING( - "MSDD_StateMachine: Invalid CBW (len %d)\n\r", - (int)transfer->transferred); - - // Wait for a reset recovery - pMsdDriver->waitResetRecovery = 1; - - // Halt the Bulk-IN and Bulk-OUT pipes - MSDD_Halt(MSDD_CASE_STALL_OUT | MSDD_CASE_STALL_IN); - - csw->bCSWStatus = MSD_CSW_COMMAND_FAILED; - pMsdDriver->state = MSDD_STATE_READ_CBW; - - } - // Check the CBW Signature - else if (cbw->dCBWSignature != MSD_CBW_SIGNATURE) { - - TRACE_WARNING( - "MSD_BOTStateMachine: Invalid CBW (Bad signature)\n\r"); - - // Wait for a reset recovery - pMsdDriver->waitResetRecovery = 1; - - // Halt the Bulk-IN and Bulk-OUT pipes - MSDD_Halt(MSDD_CASE_STALL_OUT | MSDD_CASE_STALL_IN); - - csw->bCSWStatus = MSD_CSW_COMMAND_FAILED; - pMsdDriver->state = MSDD_STATE_READ_CBW; - } - else { - - // Pre-process command - MSDD_PreProcessCommand(pMsdDriver); - } - } - - // Process command - if (csw->bCSWStatus == MSDD_STATUS_SUCCESS) { - - if (MSDD_ProcessCommand(pMsdDriver)) { - - // Post-process command if it is finished - if (MSDD_PostProcessCommand(pMsdDriver)) { - - TRACE_INFO_WP("WaitHALT "); - pMsdDriver->state = MSDD_STATE_WAIT_HALT; - } - else { - - pMsdDriver->state = MSDD_STATE_SEND_CSW; - } - } - TRACE_INFO_WP("\n\r"); - } - - break; - - //---------------------- - case MSDD_STATE_SEND_CSW: - //---------------------- - // Set signature - csw->dCSWSignature = MSD_CSW_SIGNATURE; - - // Start the CSW write operation - status = MSDD_Write(csw, - MSD_CSW_SIZE, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - - // Check operation result code - if (status == USBD_STATUS_SUCCESS) { - - TRACE_INFO_WP("SendCSW "); - - // Wait for end of transfer - pMsdDriver->state = MSDD_STATE_WAIT_CSW; - } - break; - - //---------------------- - case MSDD_STATE_WAIT_CSW: - //---------------------- - // Check transfer semaphore - if (transfer->semaphore > 0) { - - // Take semaphore and terminate transfer - transfer->semaphore--; - - // Check if transfer was successful - if (transfer->status == USBD_STATUS_RESET) { - - TRACE_INFO("MSDD_StateMachine: EP resetted\n\r"); - } - else if (transfer->status == USBD_STATUS_ABORTED) { - - TRACE_WARNING( - "MSDD_StateMachine: Failed to send CSW\n\r"); - } - else { - - TRACE_INFO_WP("ok"); - } - - // Read new CBW - pMsdDriver->state = MSDD_STATE_READ_CBW; - } - break; - - //---------------------- - case MSDD_STATE_WAIT_HALT: - //---------------------- - if (MSDD_IsHalted() == 0) { - - pMsdDriver->state = MSDD_STATE_SEND_CSW; - } - break; - } -} diff --git a/radio/bootloader/usb/device/massstorage/MSDDStateMachine.h b/radio/bootloader/usb/device/massstorage/MSDDStateMachine.h deleted file mode 100644 index ad096d83d..000000000 --- a/radio/bootloader/usb/device/massstorage/MSDDStateMachine.h +++ /dev/null @@ -1,264 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//----------------------------------------------------------------------------- -/// \unit -/// !Purpose -/// -/// Definitions, structs, functions required by a Mass Storage device driver -/// state machine.. -/// -/// !Usage -/// -/// - For a USB device: -/// -# MSDD_Write, MSDD_Read, MSDD_Halt should be defined for -/// usage in the state machine procedure. -/// -/// -# MSDD_StateMachine is invoked to run the MSD state machine. -/// -//----------------------------------------------------------------------------- - -#ifndef MSDDSTATEMACHINE_H -#define MSDDSTATEMACHINE_H - -//----------------------------------------------------------------------------- -// Headers -//----------------------------------------------------------------------------- - -#include "MSD.h" -#include "MSDLun.h" -#include "debug.h" - -//----------------------------------------------------------------------------- -// Definitions -//----------------------------------------------------------------------------- - -//------------------------------------------------------------------------------ -/// \page "MSD Driver Possible states" -/// ... -/// -/// !States -/// - MSDD_STATE_READ_CBW -/// - MSDD_STATE_WAIT_CBW -/// - MSDD_STATE_PROCESS_CBW -/// - MSDD_STATE_WAIT_HALT -/// - MSDD_STATE_SEND_CSW -/// - MSDD_STATE_WAIT_CSW -/// - MSDD_STATE_WAIT_RESET - -//! \brief Driver is expecting a command block wrapper -#define MSDD_STATE_READ_CBW (1 << 0) - -//! \brief Driver is waiting for the transfer to finish -#define MSDD_STATE_WAIT_CBW (1 << 1) - -//! \brief Driver is processing the received command -#define MSDD_STATE_PROCESS_CBW (1 << 2) - -//! \brief Driver is halted because pipe halt or wait reset -#define MSDD_STATE_WAIT_HALT (1 << 3) - -//! \brief Driver is starting the transmission of a command status wrapper -#define MSDD_STATE_SEND_CSW (1 << 4) - -//! \brief Driver is waiting for the CSW transmission to finish -#define MSDD_STATE_WAIT_CSW (1 << 5) - -//! \brief Driver is waiting for the MassStorageReset -#define MSDD_STATE_WAIT_RESET (1 << 6) -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Driver Result Codes" -/// This page lists result codes for MSD functions. -/// -/// !Codes -/// - MSDD_STATUS_SUCCESS -/// - MSDD_STATUS_ERROR -/// - MSDD_STATUS_INCOMPLETE -/// - MSDD_STATUS_PARAMETER -/// - MSDD_STATUS_RW - -//! \brief Method was successful -#define MSDD_STATUS_SUCCESS 0x00 - -//! \brief There was an error when trying to perform a method -#define MSDD_STATUS_ERROR 0x01 - -//! \brief No error was encountered but the application should call the -//! method again to continue the operation -#define MSDD_STATUS_INCOMPLETE 0x02 - -//! \brief A wrong parameter has been passed to the method -#define MSDD_STATUS_PARAMETER 0x03 - -//! \brief An error when reading/writing disk (protected or not present) -#define MSDD_STATUS_RW 0x04 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Driver Action Cases" -/// This page lists actions to perform during the post-processing phase of a -/// command. -/// -/// !Actions -/// - MSDD_CASE_PHASE_ERROR -/// - MSDD_CASE_STALL_IN -/// - MSDD_CASE_STALL_OUT - -//! \brief Indicates that the CSW should report a phase error -#define MSDD_CASE_PHASE_ERROR (1 << 0) - -//! \brief The driver should halt the Bulk IN pipe after the transfer -#define MSDD_CASE_STALL_IN (1 << 1) - -//! \brief The driver should halt the Bulk OUT pipe after the transfer -#define MSDD_CASE_STALL_OUT (1 << 2) - -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Driver Xfr Directions" -/// This page lists possible direction values for a data transfer -/// -/// !Directions -/// - MSDD_DEVICE_TO_HOST -/// - MSDD_HOST_TO_DEVICE -/// - MSDD_NO_TRANSFER - -#define MSDD_DEVICE_TO_HOST 0 -#define MSDD_HOST_TO_DEVICE 1 -#define MSDD_NO_TRANSFER 2 -//------------------------------------------------------------------------------ - -//----------------------------------------------------------------------------- -// Types -//----------------------------------------------------------------------------- - -//------------------------------------------------------------------------------ -//! \brief Structure for holding the result of a USB transfer -//! \see MSDDriver_Callback -//------------------------------------------------------------------------------ -typedef struct { - - volatile unsigned int transferred; /// Number of bytes transferred - volatile unsigned int remaining; /// Number of bytes not transferred - volatile unsigned short semaphore; /// Semaphore to indicate transfer completion - volatile unsigned short status; /// Operation result code - -} MSDTransfer; - -//------------------------------------------------------------------------------ -//! \brief Status of an executing command -//! \see MSDCbw -//! \see MSDCsw -//! \see MSDTransfer -//------------------------------------------------------------------------------ -typedef struct { - - MSDTransfer transfer; /// Current transfer status (USB) - MSDTransfer disktransfer;/// Current transfer status (Disk) - unsigned int length; /// Remaining length of command - MSCbw cbw; /// Received CBW (31 bytes) - unsigned char state; /// Current command state - MSCsw csw; /// CSW to send (13 bytes) - unsigned char postprocess; /// Actions to perform when command is complete - -} MSDCommandState; - -//------------------------------------------------------------------------------ -/// \brief MSD driver state variables -/// \see MSDCommandState -/// \see MSDLun -//------------------------------------------------------------------------------ -typedef struct { - - /// LUN list for the %device. - MSDLun *luns; - /// State of the currently executing command - MSDCommandState commandState; - /// Maximum LUN index - unsigned char maxLun; - /// Current state of the driver - unsigned char state; - /// Indicates if the driver is waiting for a reset recovery - unsigned char waitResetRecovery; - -} MSDDriver; - -//----------------------------------------------------------------------------- -// Inline functions -//----------------------------------------------------------------------------- -//----------------------------------------------------------------------------- -/// This function is to be used as a callback for USB or LUN transfers. -/// \param transfer Pointer to the transfer structure to update -/// \param status Operation result code -/// \param transferred Number of bytes transferred by the command -/// \param remaining Number of bytes not transferred -//----------------------------------------------------------------------------- -static inline void MSDDriver_Callback(MSDTransfer *transfer, - unsigned char status, - unsigned int transferred, - unsigned int remaining) -{ - TRACE_DEBUG("Cbk "); - transfer->semaphore++; - transfer->status = status; - transfer->transferred = transferred; - transfer->remaining = remaining; -} - -//----------------------------------------------------------------------------- -// Driver functions -//----------------------------------------------------------------------------- -//- MSD General support function -extern char MSDD_Read( - void* pData, - unsigned int dLength, - TransferCallback fCallback, - void* pArgument); - -extern char MSDD_Write( - void* pData, - unsigned int dLength, - TransferCallback fCallback, - void* pArgument); - -extern void MSDD_Halt(unsigned int stallCase); - -extern unsigned int MSDD_IsHalted(void); - -//----------------------------------------------------------------------------- -// Exported functions -//----------------------------------------------------------------------------- - -extern void MSDD_StateMachine(MSDDriver * pMsdDriver); - -#endif // #define MSDDSTATEMACHINE_H - diff --git a/radio/bootloader/usb/device/massstorage/MSDDriver.c b/radio/bootloader/usb/device/massstorage/MSDDriver.c deleted file mode 100644 index a93c85f94..000000000 --- a/radio/bootloader/usb/device/massstorage/MSDDriver.c +++ /dev/null @@ -1,343 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ - -#include -#include "MSDDriver.h" -#include "MSDDriverDescriptors.h" -#include "SBCMethods.h" -#include "debug.h" -#include -#include -#include -#include -#include -#include - -//----------------------------------------------------------------------------- -// Internal variables -//----------------------------------------------------------------------------- - -/// Mass storage device driver instance. -static MSDDriver msdDriver; - -/// Standard device driver instance. -static USBDDriver usbdDriver; - -//----------------------------------------------------------------------------- -// Internal functions -//----------------------------------------------------------------------------- - -//----------------------------------------------------------------------------- -/// Resets the state of the MSD driver -//----------------------------------------------------------------------------- -static void MSDDriver_Reset(void) -{ - TRACE_INFO_WP("MSDReset "); - - msdDriver.state = MSDD_STATE_READ_CBW; - msdDriver.waitResetRecovery = 0; - msdDriver.commandState.state = 0; -} - -//----------------------------------------------------------------------------- -// Callback re-implementation -//----------------------------------------------------------------------------- -//----------------------------------------------------------------------------- -/// Invoked when a new SETUP request is received from the host. Forwards the -/// request to the Mass Storage device driver handler function. -/// \param request Pointer to a USBGenericRequest instance. -//----------------------------------------------------------------------------- -void USBDCallbacks_RequestReceived(const USBGenericRequest *request) -{ - MSDDriver_RequestHandler(request); -} - -//----------------------------------------------------------------------------- -/// Invoked when the configuration of the device changes. Resets the mass -/// storage driver. -/// \param cfgnum New configuration number. -//----------------------------------------------------------------------------- -void USBDDriverCallbacks_ConfigurationChanged(unsigned char cfgnum) -{ - if (cfgnum > 0) { - - MSDDriver_Reset(); - } -} - -//----------------------------------------------------------------------------- -// Driver functions -//----------------------------------------------------------------------------- - -//----------------------------------------------------------------------------- -/// Reads from host through MSD defined bulk OUT pipe. Act as USBD_Read but by -/// a fixed OUT endpoint. -/// \param data Pointer to the data buffer that contains data read from host. -/// \param size The number of bytes should be read (buffer size). -/// \param callback Pointer to the function invoked on end of reading. -/// \param argument Pointer to additional argument data struct. -//----------------------------------------------------------------------------- -char MSDD_Read(void *data, - unsigned int size, - TransferCallback callback, - void *argument) - -{ - return USBD_Read(MSDDriverDescriptors_BULKOUT, - data, - size, - callback, - argument); -} - -//----------------------------------------------------------------------------- -/// Writes to host through MSD defined bulk IN pipe. Act as USBD_Write but by -/// a fixed IN endpoint. -/// \param data Pointer to the data that writes to the host. -/// \param size The number of bytes should be write. -/// \param callback Pointer to the function invoked on end of writing. -/// \param argument Pointer to additional argument data struct. -//----------------------------------------------------------------------------- -char MSDD_Write(void *data, - unsigned int size, - TransferCallback callback, - void *argument) -{ - return USBD_Write(MSDDriverDescriptors_BULKIN, - data, - size, - callback, - argument); -} - -//----------------------------------------------------------------------------- -/// HALT Specified USB pipe. -/// \param stallCASE Case of the stall condition (Bulk In/Out/Both). -//----------------------------------------------------------------------------- -void MSDD_Halt(unsigned int stallCASE) -{ - if (stallCASE & MSDD_CASE_STALL_OUT) { - - USBD_Halt(MSDDriverDescriptors_BULKOUT); - } - - if (stallCASE & MSDD_CASE_STALL_IN) { - - USBD_Halt(MSDDriverDescriptors_BULKIN); - } -} - -//----------------------------------------------------------------------------- -/// Return halted status -/// \return stallCASE bitmap, case of the stall condition -/// (bit: MSDD_CASE_STALL_OUT or MSDD_CASE_STALL_IN) -//----------------------------------------------------------------------------- -unsigned int MSDD_IsHalted(void) -{ - unsigned int stallCASE = 0; - if (USBD_IsHalted(MSDDriverDescriptors_BULKOUT)) { - - stallCASE |= MSDD_CASE_STALL_OUT; - } - if (USBD_IsHalted(MSDDriverDescriptors_BULKIN)) { - - stallCASE |= MSDD_CASE_STALL_IN; - } - return stallCASE; -} - -//----------------------------------------------------------------------------- -// Exported functions -//----------------------------------------------------------------------------- - -//----------------------------------------------------------------------------- -/// Initializes the MSD driver and the associated USB driver. -/// \param luns Pointer to a list of LUNs -/// \param numLuns Number of LUN in list -/// \see MSDLun -//----------------------------------------------------------------------------- -void MSDDriver_Initialize(MSDLun *defLuns, unsigned char numLuns) -{ - - TRACE_INFO("MSD init\n\r"); - - // Command state initialization - msdDriver.commandState.state = 0; - msdDriver.commandState.postprocess = 0; - msdDriver.commandState.length = 0; - msdDriver.commandState.transfer.semaphore = 0; - - // LUNs - msdDriver.luns = defLuns; - msdDriver.maxLun = (unsigned char) (numLuns - 1); - - // Reset BOT driver - MSDDriver_Reset(); - - // Init the USB driver - USBDDriver_Initialize(&usbdDriver, &msdDriverDescriptors, 0); - USBD_Init(); -} - -//----------------------------------------------------------------------------- -/// Handler for incoming SETUP requests on default Control endpoint 0. -/// -/// Standard requests are forwarded to the USBDDriver_RequestHandler -/// method. -/// \param request Pointer to a USBGenericRequest instance -//----------------------------------------------------------------------------- -void MSDDriver_RequestHandler(const USBGenericRequest *request) -{ - TRACE_INFO_WP("NewReq "); - - // Handle requests - switch (USBGenericRequest_GetRequest(request)) { - //--------------------- - case USBGenericRequest_CLEARFEATURE: - //--------------------- - TRACE_INFO_WP("ClrFeat "); - - switch (USBFeatureRequest_GetFeatureSelector(request)) { - - //--------------------- - case USBFeatureRequest_ENDPOINTHALT: - //--------------------- - TRACE_INFO_WP("Hlt "); - - // Do not clear the endpoint halt status if the device is waiting - // for a reset recovery sequence - if (!msdDriver.waitResetRecovery) { - - // Forward the request to the standard handler - USBDDriver_RequestHandler(&usbdDriver, request); - } - else { - - TRACE_INFO_WP("No "); - } - - USBD_Write(0, 0, 0, 0, 0); - break; - - //------ - default: - //------ - // Forward the request to the standard handler - USBDDriver_RequestHandler(&usbdDriver, request); - } - break; - - //------------------- - case MSD_GET_MAX_LUN: - //------------------- - TRACE_INFO_WP("gMaxLun "); - - // Check request parameters - if ((request->wValue == 0) - && (request->wIndex == 0) - && (request->wLength == 1)) { - - USBD_Write(0, &(msdDriver.maxLun), 1, 0, 0); - - } - else { - - TRACE_WARNING( - "MSDDriver_RequestHandler: GetMaxLUN(%d,%d,%d)\n\r", - request->wValue, request->wIndex, request->wLength); - USBD_Stall(0); - } - break; - - //----------------------- - case MSD_BULK_ONLY_RESET: - //----------------------- - TRACE_INFO_WP("Rst "); - - // Check parameters - if ((request->wValue == 0) - && (request->wIndex == 0) - && (request->wLength == 0)) { - - // Reset the MSD driver - MSDDriver_Reset(); - USBD_Write(0, 0, 0, 0, 0); - } - else { - - TRACE_WARNING( - "MSDDriver_RequestHandler: Reset(%d,%d,%d)\n\r", - request->wValue, request->wIndex, request->wLength); - USBD_Stall(0); - } - break; - - //------ - default: - //------ - // Forward request to standard handler - USBDDriver_RequestHandler(&usbdDriver, request); - - break; - } -} - -//----------------------------------------------------------------------------- -/// State machine for the MSD driver -//----------------------------------------------------------------------------- -void MSDDriver_StateMachine(void) -{ - if (USBD_GetState() < USBD_STATE_CONFIGURED){} - else MSDD_StateMachine(&msdDriver); - -} - -//----------------------------------------------------------------------------- -/// Starts a remote wake-up sequence if the host has explicitely enabled it -/// by sending the appropriate SET_FEATURE request. -//----------------------------------------------------------------------------- -void MSDDriver_RemoteWakeUp(void) -{ - // Remote wake-up has been enabled - if (USBDDriver_IsRemoteWakeUpEnabled(&usbdDriver)) { - - USBD_RemoteWakeUp(); - } - // Remote wake-up NOT enabled - else { - - TRACE_WARNING( - "MSD..RemoteWakeUp: Host has not enabled remote wake-up\n\r"); - } -} - diff --git a/radio/bootloader/usb/device/massstorage/MSDDriver.h b/radio/bootloader/usb/device/massstorage/MSDDriver.h deleted file mode 100644 index 30e6b087c..000000000 --- a/radio/bootloader/usb/device/massstorage/MSDDriver.h +++ /dev/null @@ -1,75 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Mass storage %device driver implementation. -/// -/// !Usage -/// -/// -# Enable and setup USB related pins (see pio & board.h). -/// -# Configure the memory interfaces used for Mass Storage LUNs -/// (see memories, MSDLun.h). -/// -# Configure the USB MSD %driver using MSDDriver_Initialize. -/// -# Invoke MSDDriver_StateMachine in main loop to handle all Mass Storage -/// operations. -//------------------------------------------------------------------------------ - -#ifndef MSDDRIVER_H -#define MSDDRIVER_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "MSD.h" -#include "MSDLun.h" -// #include - -//------------------------------------------------------------------------------ -// Global functions -//------------------------------------------------------------------------------ - -extern void MSDDriver_Initialize(MSDLun *luns, unsigned char numLuns); - -extern void MSDDriver_RequestHandler(const USBGenericRequest *request); - -extern void MSDDriver_StateMachine(void); - -extern void MSDDriver_RemoteWakeUp(void); - -extern void MSDDriver_DataCallback(unsigned char isRead, - unsigned int dataLength, - unsigned int nullCnt, - unsigned int fullCnt); - -#endif // #ifndef MSDDRIVER_H - diff --git a/radio/bootloader/usb/device/massstorage/MSDDriverDescriptors.c b/radio/bootloader/usb/device/massstorage/MSDDriverDescriptors.c deleted file mode 100644 index b37653bc5..000000000 --- a/radio/bootloader/usb/device/massstorage/MSDDriverDescriptors.c +++ /dev/null @@ -1,395 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "MSDDriverDescriptors.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include - -//------------------------------------------------------------------------------ -// Internal definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Device Descriptor IDs" -/// ... -/// !IDs -/// - MSDDriverDescriptors_VENDORID -/// - MSDDriverDescriptors_PRODUCTID -/// - MSDDriverDescriptors_RELEASE - -/// Vendor ID for the Mass Storage device driver. -#define MSDDriverDescriptors_VENDORID 0x03EB -/// Product ID for the Mass Storage device driver. -#ifdef HID -#define HIDMSDDDriverDescriptors_PRODUCTID 0x6135 -#else -#define MSDDriverDescriptors_PRODUCTID 0x6129 -#endif -/// Device release number for the Mass Storage device driver. -#define MSDDriverDescriptors_RELEASE 0x0100 - -#ifdef HID -/** Address of the HID interrupt IN endpoint. */ -#define HIDD_Descriptors_INTERRUPTIN 1 -/** Address of the HID interrupt OUT endpoint. */ -#define HIDD_Descriptors_INTERRUPTOUT 2 -/** Address of the Mass Storage bulk-out endpoint. */ -#define MSDD_Descriptors_BULKOUT 4 -/** Address of the Mass Storage bulk-in endpoint. */ -#define MSDD_Descriptors_BULKIN 5 -#endif - -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Macros -//------------------------------------------------------------------------------ - -/// Returns the minimum between two values. -#define MIN(a, b) ((a < b) ? a : b) - -//------------------------------------------------------------------------------ -// Internal types -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// List of configuration descriptors used by a Mass Storage device driver. -//------------------------------------------------------------------------------ -#ifndef HID -typedef struct { - - /// Standard configuration descriptor. - USBConfigurationDescriptor configuration; - /// Mass storage interface descriptor. - USBInterfaceDescriptor interface; - /// Bulk-out endpoint descriptor. - USBEndpointDescriptor bulkOut; - /// Bulk-in endpoint descriptor. - USBEndpointDescriptor bulkIn; - -} __attribute__ ((packed)) MSDConfigurationDescriptors; -#endif - -//------------------------------------------------------------------------------ -// Local variables -//------------------------------------------------------------------------------ - -#ifdef HID -/** Standard USB device descriptor for the composite device driver */ -static const USBDeviceDescriptor deviceDescriptor = -{ - - sizeof(USBDeviceDescriptor), - USBGenericDescriptor_DEVICE, - USBDeviceDescriptor_USB2_00, - 0x00, - 0x00, - 0x00, - CHIP_USB_ENDPOINTS_MAXPACKETSIZE(0), - HIDMSDDDriverDescriptors_VENDORID, - HIDMSDDDriverDescriptors_PRODUCTID, - HIDMSDDDriverDescriptors_RELEASE, -// 0, /* No string descriptor for manufacturer */ -// 1, /* Index of product string descriptor is #1 */ -// 0, /* No string descriptor for serial number */ - 1, // Manufacturer string descriptor index. - 2, // Product string descriptor index. - 3, // Serial number string descriptor index. - 1 /* Device has 1 possible configuration */ -}; -#else -/// Mass storage driver device descriptor. -static const USBDeviceDescriptor deviceDescriptor = { - - sizeof(USBDeviceDescriptor), - USBGenericDescriptor_DEVICE, - USBDeviceDescriptor_USB2_00, - MSDeviceDescriptor_CLASS, - MSDeviceDescriptor_SUBCLASS, - MSDeviceDescriptor_PROTOCOL, - CHIP_USB_ENDPOINTS_MAXPACKETSIZE(0), - MSDDriverDescriptors_VENDORID, - MSDDriverDescriptors_PRODUCTID, - MSDDriverDescriptors_RELEASE, - 1, // Manufacturer string descriptor index. - 2, // Product string descriptor index. - 3, // Serial number string descriptor index. - 1 // Device has one possible configuration. -}; -#endif - -#ifdef HID -/** USB FS configuration descriptors for the composite device driver */ -static const HidMsdDriverConfigurationDescriptors configurationDescriptorsFS = -{ - - /* Standard configuration descriptor */ - { - sizeof(USBConfigurationDescriptor), - USBGenericDescriptor_CONFIGURATION, - sizeof(HidMsdDriverConfigurationDescriptors), - HIDMSDDriverDescriptors_NUMINTERFACE, - 1, /* This is configuration #1 */ - 0, /* No string descriptor for this configuration */ - BOARD_USB_BMATTRIBUTES, - USBConfigurationDescriptor_POWER(100) - }, - - /* Interface descriptor */ - { - sizeof(USBInterfaceDescriptor), - USBGenericDescriptor_INTERFACE, - HIDMSDDriverDescriptors_HID_INTERFACE, - 0, /* This is alternate setting #0 */ - 2, /* Two endpoints used */ - HIDInterfaceDescriptor_CLASS, - HIDInterfaceDescriptor_SUBCLASS_NONE, - HIDInterfaceDescriptor_PROTOCOL_NONE, - 0 /* No associated string descriptor */ - }, - /* HID descriptor */ - { - sizeof(HIDDescriptor1), - HIDGenericDescriptor_HID, - HIDDescriptor_HID1_11, - 0, /* Device is not localized, no country code */ - 1, /* One HID-specific descriptor (apart from this one) */ - HIDGenericDescriptor_REPORT, - HIDDKeyboard_REPORTDESCRIPTORSIZE - }, - /* Interrupt IN endpoint descriptor */ - { - sizeof(USBEndpointDescriptor), - USBGenericDescriptor_ENDPOINT, - USBEndpointDescriptor_ADDRESS( - USBEndpointDescriptor_IN, - HIDD_Descriptors_INTERRUPTIN), - USBEndpointDescriptor_INTERRUPT, - sizeof(HIDDKeyboardInputReport), - HIDDKeyboardDescriptors_INTERRUPTIN_POLLING_FS - }, - /* Interrupt OUT endpoint descriptor */ - { - sizeof(USBEndpointDescriptor), - USBGenericDescriptor_ENDPOINT, - USBEndpointDescriptor_ADDRESS( - USBEndpointDescriptor_OUT, - HIDD_Descriptors_INTERRUPTOUT), - USBEndpointDescriptor_INTERRUPT, - sizeof(HIDDKeyboardOutputReport), - HIDDKeyboardDescriptors_INTERRUPTIN_POLLING_FS - }, - - /* Mass Storage interface descriptor. */ - { - sizeof(USBInterfaceDescriptor), - USBGenericDescriptor_INTERFACE, - HIDMSDDriverDescriptors_MSD_INTERFACE, - 0, /* This is alternate setting #0. */ - 2, /* Interface uses two endpoints. */ - MSInterfaceDescriptor_CLASS, - MSInterfaceDescriptor_SCSI, - MSInterfaceDescriptor_BULKONLY, - 0 /* No string descriptor for interface. */ - }, - /* Bulk-OUT endpoint descriptor */ - { - sizeof(USBEndpointDescriptor), - USBGenericDescriptor_ENDPOINT, - USBEndpointDescriptor_ADDRESS( - USBEndpointDescriptor_OUT, - MSDD_Descriptors_BULKOUT), //MSDDriverDescriptors_BULKOUT - USBEndpointDescriptor_BULK, - MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDD_Descriptors_BULKOUT),//MSDDriverDescriptors_BULKOUT - USBEndpointDescriptor_MAXBULKSIZE_FS), - 0 /* No string descriptor for endpoint. */ - }, - /* Bulk-IN endpoint descriptor */ - { - sizeof(USBEndpointDescriptor), - USBGenericDescriptor_ENDPOINT, - USBEndpointDescriptor_ADDRESS( - USBEndpointDescriptor_IN, - MSDD_Descriptors_BULKIN), //MSDDriverDescriptors_BULKIN - USBEndpointDescriptor_BULK, - MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDD_Descriptors_BULKIN),//MSDDriverDescriptors_BULKIN - USBEndpointDescriptor_MAXBULKSIZE_FS), - 0 /* No string descriptor for endpoint. */ - } - -}; - -#else -/// Full-speed configuration descriptor. -static const MSDConfigurationDescriptors configurationDescriptorsFS = { - - // Standard configuration descriptor. - { - sizeof(USBConfigurationDescriptor), - USBGenericDescriptor_CONFIGURATION, - sizeof(MSDConfigurationDescriptors), - 1, // Configuration has one interface. - 1, // This is configuration #1. - 0, // No string descriptor for configuration. - BOARD_USB_BMATTRIBUTES, - USBConfigurationDescriptor_POWER(100) - }, - // Mass Storage interface descriptor. - { - sizeof(USBInterfaceDescriptor), - USBGenericDescriptor_INTERFACE, - 0, // This is interface #0. - 0, // This is alternate setting #0. - 2, // Interface uses two endpoints. - MSInterfaceDescriptor_CLASS, - MSInterfaceDescriptor_SCSI, - MSInterfaceDescriptor_BULKONLY, - 0 // No string descriptor for interface. - }, - // Bulk-OUT endpoint descriptor - { - sizeof(USBEndpointDescriptor), - USBGenericDescriptor_ENDPOINT, - USBEndpointDescriptor_ADDRESS( - USBEndpointDescriptor_OUT, - MSDDriverDescriptors_BULKOUT), - USBEndpointDescriptor_BULK, - MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDDriverDescriptors_BULKOUT), - USBEndpointDescriptor_MAXBULKSIZE_FS), - 0 // Must be 0 for full-speed Bulk endpoints. - }, - // Bulk-IN endpoint descriptor - { - sizeof(USBEndpointDescriptor), - USBGenericDescriptor_ENDPOINT, - USBEndpointDescriptor_ADDRESS( - USBEndpointDescriptor_IN, - MSDDriverDescriptors_BULKIN), - USBEndpointDescriptor_BULK, - MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDDriverDescriptors_BULKIN), - USBEndpointDescriptor_MAXBULKSIZE_FS), - 0 // Must be 0 for full-speed Bulk endpoints. - } -}; -#endif - -/// Language ID string descriptor. -static const unsigned char languageIdDescriptor[] = { - - USBStringDescriptor_LENGTH(1), - USBGenericDescriptor_STRING, - USBStringDescriptor_ENGLISH_US -}; - -/// Manufacturer string descriptor. -static const unsigned char manufacturerDescriptor[] = { - - USBStringDescriptor_LENGTH(7), - USBGenericDescriptor_STRING, - USBStringDescriptor_UNICODE('9'), - USBStringDescriptor_UNICODE('X'), - USBStringDescriptor_UNICODE(' '), - USBStringDescriptor_UNICODE('T'), - USBStringDescriptor_UNICODE('E'), - USBStringDescriptor_UNICODE('A'), - USBStringDescriptor_UNICODE('M'), -}; - -/// Product string descriptor. -static const unsigned char productDescriptor[] = { - - USBStringDescriptor_LENGTH(5), - USBGenericDescriptor_STRING, - USBStringDescriptor_UNICODE('S'), - USBStringDescriptor_UNICODE('K'), - USBStringDescriptor_UNICODE('Y'), - USBStringDescriptor_UNICODE('9'), - USBStringDescriptor_UNICODE('X'), -}; - -/// Serial number string descriptor. The serial number must be at least 12 -/// characters long and made up of only letters & numbers to be compliant with -/// the MSD specification. -static const unsigned char serialNumberDescriptor[] = { - - USBStringDescriptor_LENGTH(12), - USBGenericDescriptor_STRING, - USBStringDescriptor_UNICODE('0'), - USBStringDescriptor_UNICODE('1'), - USBStringDescriptor_UNICODE('2'), - USBStringDescriptor_UNICODE('3'), - USBStringDescriptor_UNICODE('4'), - USBStringDescriptor_UNICODE('5'), - USBStringDescriptor_UNICODE('6'), - USBStringDescriptor_UNICODE('7'), - USBStringDescriptor_UNICODE('8'), - USBStringDescriptor_UNICODE('9'), - USBStringDescriptor_UNICODE('A'), - USBStringDescriptor_UNICODE('B') -}; - -/// List of all string descriptors used. -static const unsigned char *stringDescriptors[] = { - - languageIdDescriptor, - manufacturerDescriptor, - productDescriptor, - serialNumberDescriptor -}; - -//------------------------------------------------------------------------------ -// Global variables -//------------------------------------------------------------------------------ - -/// List of the standard descriptors used by the Mass Storage driver. -const USBDDriverDescriptors msdDriverDescriptors = { - - &deviceDescriptor, - (USBConfigurationDescriptor *) &configurationDescriptorsFS, - 0, // No full-speed device qualifier descriptor - 0, // No full-speed other speed configuration - 0, // No high-speed device descriptor - 0, // No high-speed configuration descriptor - 0, // No high-speed device qualifier descriptor - 0, // No high-speed other speed configuration descriptor - stringDescriptors, - 4 // Four string descriptors in array -}; - diff --git a/radio/bootloader/usb/device/massstorage/MSDDriverDescriptors.h b/radio/bootloader/usb/device/massstorage/MSDDriverDescriptors.h deleted file mode 100644 index 6f1f151f5..000000000 --- a/radio/bootloader/usb/device/massstorage/MSDDriverDescriptors.h +++ /dev/null @@ -1,83 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Definitions of the descriptors required by a Mass Storage device driver. -/// -/// !Usage -/// -/// - For a USB %device: -/// -# When initializing a USBDDriver instance, use msdDriverDescriptors as -/// the list of standard descriptors. -//------------------------------------------------------------------------------ - -#ifndef MSDDRIVERDESCRIPTORS_H -#define MSDDRIVERDESCRIPTORS_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD endpoint addresses" -/// This page lists the addresses used by the Mass Storage driver %endpoints. -/// -/// !Addresses -/// -/// - MSDDriverDescriptors_BULKOUT -/// - MSDDriverDescriptors_BULKIN - -/// Address of the Mass Storage bulk-out endpoint. -#define MSDDriverDescriptors_BULKOUT 1 - -/// Address of the Mass Storage bulk-in endpoint. -#if defined(at91sam9m10) - #define MSDDriverDescriptors_BULKIN 6 -#else - #define MSDDriverDescriptors_BULKIN 2 -#endif -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Exported variables -//------------------------------------------------------------------------------ - -extern const USBDDriverDescriptors msdDriverDescriptors; - -#endif //#ifndef MSDDRIVERDESCRIPTORS_H - diff --git a/radio/bootloader/usb/device/massstorage/MSDIOFifo.h b/radio/bootloader/usb/device/massstorage/MSDIOFifo.h deleted file mode 100644 index 5f7b7fba5..000000000 --- a/radio/bootloader/usb/device/massstorage/MSDIOFifo.h +++ /dev/null @@ -1,135 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef _MSDIOFIFO_H -#define _MSDIOFIFO_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -/// Idle state, do nothing -#define MSDIO_IDLE 0 -/// Start, to start IO operation -#define MSDIO_START 1 -/// Wait, waiting for IO operation done -#define MSDIO_WAIT 2 -/// Next, to check if the next block can be performed -#define MSDIO_NEXT 3 -/// Pause, to pause the process for buffer full or null -#define MSDIO_PAUSE 4 -/// Abort, to abort the process -#define MSDIO_ABORT 5 -/// Done, finish without error -#define MSDIO_DONE 6 -/// Error, any error happens -#define MSDIO_ERROR 7 - -/// FIFO offset before USB transmit start -//#define MSDIO_FIFO_OFFSET (4*512) - -/// FIFO trunk size (in each transfer, large amount of data) -#if !defined(MSD_OP_BUFFER) -#define MSDIO_READ10_CHUNK_SIZE (4*512) -#define MSDIO_WRITE10_CHUNK_SIZE (4*512) -#endif - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -/// FIFO buffer for READ/WRITE (disk) operation of a mass storage device -typedef struct _MSDIOFifo { - - /// Pointer to the ring buffer allocated for read/write - unsigned char * pBuffer; - /// The size of the buffer allocated - unsigned int bufferSize; -#ifdef MSDIO_FIFO_OFFSET - /// The offset to start USB transfer (READ10) - unsigned int bufferOffset; -#endif - /// The index of input data (loaded to fifo buffer) - unsigned int inputNdx; - /// The total size of the loaded data - unsigned int inputTotal; - /// The index of output data (sent from the fifo buffer) - unsigned int outputNdx; - /// The total size of the output data - unsigned int outputTotal; - - /// The total size of the data - unsigned int dataTotal; - /// The size of the block in bytes - unsigned short blockSize; -#if defined(MSDIO_READ10_CHUNK_SIZE) || defined(MSDIO_WRITE10_CHUNK_SIZE) - /// The size of one chunk - /// (1 block, or several blocks for large amount data R/W) - unsigned int chunkSize; -#endif - /// State of input & output - unsigned char inputState; - unsigned char outputState; - - //- Statistics - /// Times when fifo has no data to send - unsigned short nullCnt; - /// Times when fifo can not load more input data - unsigned short fullCnt; -} MSDIOFifo, *PMSDIOFifo; - -//------------------------------------------------------------------------------ -// MACROS -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Increase the index, by defined block size, in the ring buffer -/// \param ndx The index to be increased -/// \param sectSize The defined block size -/// \param bufSize The ring buffer size -//------------------------------------------------------------------------------ -#define MSDIOFifo_IncNdx(ndx, sectSize, bufSize) \ - if ((ndx) >= (bufSize) - (sectSize)) (ndx) = 0; \ - else (ndx) += (sectSize) - - -//------------------------------------------------------------------------------ -// Exported Functions -//------------------------------------------------------------------------------ - - -extern void MSDIOFifo_Init(MSDIOFifo *pFifo, - void * pBuffer, unsigned short bufferSize); - -#endif // _MSDIOFIFO_H - diff --git a/radio/bootloader/usb/device/massstorage/MSDLun.c b/radio/bootloader/usb/device/massstorage/MSDLun.c deleted file mode 100644 index 6b649b4d2..000000000 --- a/radio/bootloader/usb/device/massstorage/MSDLun.c +++ /dev/null @@ -1,368 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - - -#include "MSDLun.h" -#include "debug.h" -#include - -#include "usb/device/massstorage/MSDDriver.h" - - -//------------------------------------------------------------------------------ -// Constants -//------------------------------------------------------------------------------ - -/// Default LUN block size in bytes -#define DEFAULT_LUN_BLOCK_SIZE 512 - -//------------------------------------------------------------------------------ -// Internal variables -//------------------------------------------------------------------------------ - -/// Inquiry data to return to the host for the Lun. -static SBCInquiryData inquiryData = { - - SBC_DIRECT_ACCESS_BLOCK_DEVICE, // Direct-access block device - SBC_PERIPHERAL_DEVICE_CONNECTED,// Peripheral device is connected - 0x00, // Reserved bits - 0x01, // Media is removable - SBC_SPC_VERSION_4, // SPC-4 supported - 0x2, // Response data format, must be 0x2 - 0, // Hierarchical addressing not supported - 0, // ACA not supported - 0x0, // Obsolete bits - sizeof(SBCInquiryData) - 5, // Additional length - 0, // No embedded SCC - 0, // No access control coordinator - SBC_TPGS_NONE, // No target port support group - 0, // Third-party copy not supported - 0x0, // Reserved bits - 0, // Protection information not supported - 0x0, // Obsolete bit - 0, // No embedded enclosure service component - 0x0, // ??? - 0, // Device is not multi-port - 0x0, // Obsolete bits - 0x0, // Unused feature - 0x0, // Unused features - 0, // Task management model not supported - 0x0, // ??? - {'E','R','S','K','Y','9','X',' '}, - {'M','a','s','s',' ', - 'S','t','o','r','a','g','e',' ', - 'M','S','D'}, - {'0','.','0','1'}, - {'M','a','s','s',' ', - 'S','t','o','r','a','g','e',' ', - 'E','x','a','m','p','l','e'}, - 0x00, // Unused features - 0x00, // Reserved bits - {SBC_VERSION_DESCRIPTOR_SBC_3}, // SBC-3 compliant device - {0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0} // Reserved -}; - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -//! \brief Initializes a LUN instance. Must be invoked at least once even no -//! Media is linked. -//! \param lun Pointer to the MSDLun instance to initialize -//! \param media Media on which the LUN is constructed, set to 0 to -//! disconnect the Media or initialize an ejected LUN. -//! \param ioBuffer Pointer to a buffer used for read/write operation and -//! which must be blockSize bytes long. -//! \param ioBufferSize Size of the allocated IO buffer. -//! \param baseAddress Base address of the LUN in number of media blocks -//! \param size Total size of the LUN in number of media blocks -//! \param blockSize One block of the LUN in number of media blocks -//! \param protected The LUN area is forced to readonly even the media -//! is writable -//! \param dataMonitor Pointer to a Monitor Function to analyze the flow of -//! this LUN. -//------------------------------------------------------------------------------ -void LUN_Init(MSDLun *lun, - Media *media, - unsigned char *ioBuffer, - unsigned int ioBufferSize, - unsigned int baseAddress, - unsigned int size, - unsigned short blockSize, - unsigned char protected, - void (*dataMonitor)(unsigned char flowDirection, - unsigned int dataLength, - unsigned int fifoNullCount, - unsigned int fifoFullCount)) -{ - unsigned int logicalBlockAddress; - TRACE_INFO("LUN init\n\r"); - - // Initialize inquiry data - lun->inquiryData = &inquiryData; - - // Initialize request sense data - lun->requestSenseData.bResponseCode = SBC_SENSE_DATA_FIXED_CURRENT; - lun->requestSenseData.isValid = 1; - lun->requestSenseData.bObsolete1 = 0; - lun->requestSenseData.bSenseKey = SBC_SENSE_KEY_NO_SENSE; - lun->requestSenseData.bReserved1 = 0; - lun->requestSenseData.isILI = 0; - lun->requestSenseData.isEOM = 0; - lun->requestSenseData.isFilemark = 0; - lun->requestSenseData.pInformation[0] = 0; - lun->requestSenseData.pInformation[1] = 0; - lun->requestSenseData.pInformation[2] = 0; - lun->requestSenseData.pInformation[3] = 0; - lun->requestSenseData.bAdditionalSenseLength - = sizeof(SBCRequestSenseData) - 8; - lun->requestSenseData.bAdditionalSenseCode = 0; - lun->requestSenseData.bAdditionalSenseCodeQualifier = 0; - lun->requestSenseData.bFieldReplaceableUnitCode = 0; - lun->requestSenseData.bSenseKeySpecific = 0; - lun->requestSenseData.pSenseKeySpecific[0] = 0; - lun->requestSenseData.pSenseKeySpecific[0] = 0; - lun->requestSenseData.isSKSV = 0; - - STORE_DWORDB(0, lun->readCapacityData.pLogicalBlockAddress); - STORE_DWORDB(0, lun->readCapacityData.pLogicalBlockLength); - - // Initialize LUN - lun->media = media; - if (media == 0) { - lun->status = LUN_NOT_PRESENT; - return; - } - - lun->baseAddress = baseAddress; - - // Customized block size - if (blockSize) { - lun->blockSize = blockSize; - } - else { - if (media->blockSize < DEFAULT_LUN_BLOCK_SIZE) - lun->blockSize = DEFAULT_LUN_BLOCK_SIZE / media->blockSize; - else - lun->blockSize = 1; - } - - if (size) { - lun->size = size; - } - else { - lun->size = media->size; - //if (blockSize) - // lun->size = media->size / blockSize; - //else { - // if (media->blockSize < DEFAULT_LUN_BLOCK_SIZE) - // lun->size = media->size / lun->blockSize; - // else - // lun->size = media->size; - //} - } - - TRACE_INFO("LUN: blkSize %d, size %d\n\r", (int)lun->blockSize, (int)lun->size); - if (protected) lun->protected = 1; - else lun->protected = media->protected; - - lun->ioFifo.pBuffer = ioBuffer; - lun->ioFifo.bufferSize = ioBufferSize; - - lun->dataMonitor = dataMonitor; - - // Initialize read capacity data - logicalBlockAddress = lun->size / lun->blockSize - 1; - STORE_DWORDB(logicalBlockAddress, - lun->readCapacityData.pLogicalBlockAddress); - STORE_DWORDB(lun->blockSize * media->blockSize, - lun->readCapacityData.pLogicalBlockLength); - - // Indicate media change - lun->status = LUN_CHANGED; -} - -//------------------------------------------------------------------------------ -//! \brief Eject the media from a LUN -//! \param lun Pointer to the MSDLun instance to initialize -//! \return Operation result code -//------------------------------------------------------------------------------ -unsigned char LUN_Eject(MSDLun *lun) -{ - if (lun->media) { - - // Avoid any LUN R/W in progress - if (lun->media->state == MED_STATE_BUSY) { - - return USBD_STATUS_LOCKED; - } - - // Remove the link of the media - lun->media = 0; - } - // LUN is removed - lun->status = LUN_NOT_PRESENT; - - return USBD_STATUS_SUCCESS; -} - -//------------------------------------------------------------------------------ -//! \brief Writes data on the a LUN starting at the specified block address. -//! \param lun Pointer to a MSDLun instance -//! \param blockAddress First block address to write -//! \param data Pointer to the data to write -//! \param length Number of blocks to write -//! \param callback Optional callback to invoke when the write finishes -//! \return Operation result code -//------------------------------------------------------------------------------ -unsigned char LUN_Write(MSDLun *lun, - unsigned int blockAddress, - void *data, - unsigned int length, - TransferCallback callback, - void *argument) -{ - unsigned int medBlk, medLen; - unsigned char status; - - TRACE_INFO_WP("LUNWrite(%u) ", blockAddress); - - // Check that the data is not too big - if ((length + blockAddress) * lun->blockSize > lun->size) { - - TRACE_WARNING("LUN_Write: Data too big\n\r"); - status = USBD_STATUS_ABORTED; - } - else if (lun->media == 0 || lun->status != LUN_READY) { - - TRACE_WARNING("LUN_Write: Media not ready\n\r"); - status = USBD_STATUS_ABORTED; - } - else if (lun->protected) { - TRACE_WARNING("LUN_Write: LUN is readonly\n\r"); - status = USBD_STATUS_ABORTED; - } - else { - - // Compute write start address - medBlk = lun->baseAddress + blockAddress * lun->blockSize; - medLen = length * lun->blockSize; - - // Start write operation - status = MED_Write(lun->media, - medBlk, - data, - medLen, - (MediaCallback) callback, - argument); - - // Check operation result code - if (status == MED_STATUS_SUCCESS) { - - status = USBD_STATUS_SUCCESS; - } - else { - - TRACE_WARNING("LUN_Write: Cannot write media\n\r"); - status = USBD_STATUS_ABORTED; - } - } - - return status; -} - -//------------------------------------------------------------------------------ -//! \brief Reads data from a LUN, starting at the specified block address. -//! \param lun Pointer to a MSDLun instance -//! \param blockAddress First block address to read -//! \param data Pointer to a data buffer in which to store the data -//! \param length Number of blocks to read -//! \param callback Optional callback to invoke when the read finishes -//! \return Operation result code -//------------------------------------------------------------------------------ -unsigned char LUN_Read(MSDLun *lun, - unsigned int blockAddress, - void *data, - unsigned int length, - TransferCallback callback, - void *argument) -{ - unsigned int medBlk, medLen; - unsigned char status; - - // Check that the data is not too big - if ((length + blockAddress) * lun->blockSize > lun->size) { - TRACE_WARNING("LUN_Read: Area: (%d + %d)*%d > %d\n\r", - (int)length, (int)blockAddress, (int)lun->blockSize, (int)lun->size); - status = USBD_STATUS_ABORTED; - } - else if (lun->media == 0 || lun->status != LUN_READY) { - - TRACE_WARNING("LUN_Read: Media not present\n\r"); - status = USBD_STATUS_ABORTED; - } - else { - - TRACE_INFO_WP("LUNRead(%u) ", blockAddress); - - // Compute read start address - medBlk = lun->baseAddress + (blockAddress * lun->blockSize); - medLen = length * lun->blockSize; - - // Start write operation - status = MED_Read(lun->media, - medBlk, - data, - medLen, - (MediaCallback) callback, - argument); - - // Check result code - if (status == MED_STATUS_SUCCESS) { - - status = USBD_STATUS_SUCCESS; - } - else { - - TRACE_WARNING("LUN_Read: Cannot read media\n\r"); - status = USBD_STATUS_ABORTED; - } - } - - return status; -} diff --git a/radio/bootloader/usb/device/massstorage/MSDLun.h b/radio/bootloader/usb/device/massstorage/MSDLun.h deleted file mode 100644 index 799775541..000000000 --- a/radio/bootloader/usb/device/massstorage/MSDLun.h +++ /dev/null @@ -1,161 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Logical Unit Number (LUN) used by the Mass Storage driver and the SCSI -/// protocol. Represents a logical hard-drive. -/// -/// !Usage -/// -# Initialize Memory related pins (see pio & board.h). -/// -# Initialize a Media instance for the LUN (see memories). -/// -# Initlalize the LUN with LUN_Init, and link to the initialized Media. -/// -# To read data from the LUN linked media, uses LUN_Read. -/// -# To write data to the LUN linked media, uses LUN_Write. -/// -# To unlink the media, uses LUN_Eject. -//------------------------------------------------------------------------------ - -#ifndef MSDLUN_H -#define MSDLUN_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "SBC.h" -#include -#include -#include - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -/// LUN RC: success -#define LUN_STATUS_SUCCESS 0x00 -/// LUN RC: error -#define LUN_STATUS_ERROR 0x02 - -/// Media of LUN is removed -#define LUN_NOT_PRESENT 0x00 -/// LUN is ejected by host -#define LUN_EJECTED 0x01 -/// Media of LUN is changed -#define LUN_CHANGED 0x10 -/// LUN Not Ready to Ready transition -#define LUN_TRANS_READY LUN_CHANGED -/// Media of LUN is ready -#define LUN_READY 0x11 - -//------------------------------------------------------------------------------ -// Structures -//------------------------------------------------------------------------------ - -/// LUN structure -typedef struct { - - /// Pointer to a SBCInquiryData instance. - SBCInquiryData *inquiryData; - /// Fifo for USB transfer, must be assigned. - MSDIOFifo ioFifo; - /// Pointer to Media instance for the LUN. - Media *media; - /// Pointer to a Monitor Function to analyze the flow of LUN. - /// \param flowDirection 1 - device to host (READ10) - /// 0 - host to device (WRITE10) - /// \param dataLength Length of data transferred in bytes. - /// \param fifoNullCount Times that FIFO is NULL to wait - /// \param fifoFullCount Times that FIFO is filled to wait - void (*dataMonitor)(unsigned char flowDirection, - unsigned int dataLength, - unsigned int fifoNullCount, - unsigned int fifoFullCount); - /// The start position of the media (blocks) allocated to the LUN. - unsigned int baseAddress; - /// The size of the media (blocks) allocated to the LUN. - unsigned int size; - /// Sector size of the media in number of media blocks - unsigned short blockSize; - /// The LUN can be readonly even the media is writable -#ifdef __cplusplus - unsigned char protectd; -#else - unsigned char protected; -#endif - - /// The LUN status (Ejected/Changed/) - unsigned char status; - - /// Data for the RequestSense command. - SBCRequestSenseData requestSenseData; - /// Data for the ReadCapacity command. - SBCReadCapacity10Data readCapacityData; - -} MSDLun; - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -extern void LUN_Init(MSDLun *lun, - Media *media, - unsigned char *ioBuffer, - unsigned int ioBufferSize, - unsigned int baseAddress, - unsigned int size, - unsigned short blockSize, -#ifdef __cplusplus - unsigned char protectd, -#else - unsigned char protected, -#endif - void (*dataMonitor)(unsigned char flowDirection, - unsigned int dataLength, - unsigned int fifoNullCount, - unsigned int fifoFullCount)); - -extern unsigned char LUN_Eject(MSDLun *lun); - -extern unsigned char LUN_Write(MSDLun *lun, - unsigned int blockAddress, - void *data, - unsigned int length, - TransferCallback callback, - void *argument); - -extern unsigned char LUN_Read(MSDLun *lun, - unsigned int blockAddress, - void *data, - unsigned int length, - TransferCallback callback, - void *argument); - -#endif //#ifndef MSDLUN_H - diff --git a/radio/bootloader/usb/device/massstorage/SBC.h b/radio/bootloader/usb/device/massstorage/SBC.h deleted file mode 100644 index 3c3f93c69..000000000 --- a/radio/bootloader/usb/device/massstorage/SBC.h +++ /dev/null @@ -1,653 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// SCSI definitions. -/// -/// !Usage -/// -/// -# After command block received, Access and decode the SCSI command block -/// with SBCCommand structure. -//------------------------------------------------------------------------------ - -#ifndef SBC_H -#define SBC_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Operation Codes" -/// This page lists operation codes of commands described in the SBC-3 -/// standard. -/// -/// \note That most commands are actually defined in other standards, -/// like SPC-4. Optional commands are not included here. -/// -/// \see sbc3r07.pdf - Section 5.1 - Table 12 -/// \see spc4r06.pdf -/// \see SBCCommand -/// -/// !Codes -/// - SBC_INQUIRY -/// - SBC_READ_10 -/// - SBC_READ_CAPACITY_10 -/// - SBC_REQUEST_SENSE -/// - SBC_TEST_UNIT_READY -/// - SBC_WRITE_10 -/// -/// !Optional Codes but required by Windows -/// - SBC_PREVENT_ALLOW_MEDIUM_REMOVAL -/// - SBC_MODE_SENSE_6 -/// - SBC_VERIFY_10 -/// - SBC_READ_FORMAT_CAPACITIES - -/// Request information regarding parameters of the target and Logical Unit. -#define SBC_INQUIRY 0x12 -/// Request the transfer data to the host. -#define SBC_READ_10 0x28 -/// Request capacities of the currently installed medium. -#define SBC_READ_CAPACITY_10 0x25 -/// Request that the device server transfer sense data. -#define SBC_REQUEST_SENSE 0x03 -/// Check if the LUN is ready -#define SBC_TEST_UNIT_READY 0x00 -/// Request that the device write the data transferred by the host. -#define SBC_WRITE_10 0x2A - -/// Request that the target enable or disable the removal of the medium in -/// the Logical Unit. -#define SBC_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E -/// Report parameters. -#define SBC_MODE_SENSE_6 0x1A -/// Request that the %device verify the data on the medium. -#define SBC_VERIFY_10 0x2F -/// Request a list of the possible capacities that can be formatted on medium -#define SBC_READ_FORMAT_CAPACITIES 0x23 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Periph. Qualifiers" -/// This page lists the peripheral qualifier values specified in the INQUIRY -/// data -/// \see spc4r06.pdf - Section 6.4.2 - Table 83 -/// \see SBCInquiryData -/// -/// !Qualifiers -/// - SBC_PERIPHERAL_DEVICE_CONNECTED -/// - SBC_PERIPHERAL_DEVICE_NOT_CONNECTED -/// - SBC_PERIPHERAL_DEVICE_NOT_SUPPORTED - -#define SBC_PERIPHERAL_DEVICE_CONNECTED 0x00 -#define SBC_PERIPHERAL_DEVICE_NOT_CONNECTED 0x01 -#define SBC_PERIPHERAL_DEVICE_NOT_SUPPORTED 0x03 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Periph. Types" -/// This page lists peripheral device types specified in the INQUIRY data -/// \see spc4r06.pdf - Section 6.4.2 - Table 84 -/// \see SBCInquiryData -/// -/// !Types -/// - SBC_DIRECT_ACCESS_BLOCK_DEVICE -/// - SBC_SEQUENTIAL_ACCESS_DEVICE -/// - SBC_PRINTER_DEVICE -/// - SBC_PROCESSOR_DEVICE -/// - SBC_WRITE_ONCE_DEVICE -/// - SBC_CD_DVD_DEVICE -/// - SBC_SCANNER_DEVICE -/// - SBC_OPTICAL_MEMORY_DEVICE -/// - SBC_MEDIA_CHANGER_DEVICE -/// - SBC_COMMUNICATION_DEVICE -/// - SBC_STORAGE_ARRAY_CONTROLLER_DEVICE -/// - SBC_ENCLOSURE_SERVICES_DEVICE -/// - SBC_SIMPLIFIED_DIRECT_ACCESS_DEVICE -/// - SBC_OPTICAL_CARD_READER_WRITER_DEVICE -/// - SBC_BRIDGE_CONTROLLER_COMMANDS -/// - SBC_OBJECT_BASED_STORAGE_DEVICE - -#define SBC_DIRECT_ACCESS_BLOCK_DEVICE 0x00 -#define SBC_SEQUENTIAL_ACCESS_DEVICE 0x01 -#define SBC_PRINTER_DEVICE 0x02 -#define SBC_PROCESSOR_DEVICE 0x03 -#define SBC_WRITE_ONCE_DEVICE 0x04 -#define SBC_CD_DVD_DEVICE 0x05 -#define SBC_SCANNER_DEVICE 0x06 -#define SBC_OPTICAL_MEMORY_DEVICE 0x07 -#define SBC_MEDIA_CHANGER_DEVICE 0x08 -#define SBC_COMMUNICATION_DEVICE 0x09 -#define SBC_STORAGE_ARRAY_CONTROLLER_DEVICE 0x0C -#define SBC_ENCLOSURE_SERVICES_DEVICE 0x0D -#define SBC_SIMPLIFIED_DIRECT_ACCESS_DEVICE 0x0E -#define SBC_OPTICAL_CARD_READER_WRITER_DEVICE 0x0F -#define SBC_BRIDGE_CONTROLLER_COMMANDS 0x10 -#define SBC_OBJECT_BASED_STORAGE_DEVICE 0x11 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \brief Version value for the SBC-3 specification -/// \see spc4r06.pdf - Section 6.4.2 - Table 85 -#define SBC_SPC_VERSION_4 0x06 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \brief Values for the TPGS field returned in INQUIRY data -/// \see spc4r06.pdf - Section 6.4.2 - Table 86 -#define SBC_TPGS_NONE 0x0 -#define SBC_TPGS_ASYMMETRIC 0x1 -#define SBC_TPGS_SYMMETRIC 0x2 -#define SBC_TPGS_BOTH 0x3 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \brief Version descriptor value for the SBC-3 specification -/// \see spc4r06.pdf - Section 6.4.2 - Table 87 -#define SBC_VERSION_DESCRIPTOR_SBC_3 0x04C0 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Sense Response Codes" -/// This page lists sense data response codes returned in REQUEST SENSE data -/// \see spc4r06.pdf - Section 4.5.1 - Table 12 -/// -/// !Codes -/// - SBC_SENSE_DATA_FIXED_CURRENT -/// - SBC_SENSE_DATA_FIXED_DEFERRED -/// - SBC_SENSE_DATA_DESCRIPTOR_CURRENT -/// - SBC_SENSE_DATA_DESCRIPTOR_DEFERRED - -#define SBC_SENSE_DATA_FIXED_CURRENT 0x70 -#define SBC_SENSE_DATA_FIXED_DEFERRED 0x71 -#define SBC_SENSE_DATA_DESCRIPTOR_CURRENT 0x72 -#define SBC_SENSE_DATA_DESCRIPTOR_DEFERRED 0x73 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Sense Keys" -/// This page lists sense key values returned in the REQUEST SENSE data -/// \see spc4r06.pdf - Section 4.5.6 - Table 27 -/// -/// !Keys -/// - SBC_SENSE_KEY_NO_SENSE -/// - SBC_SENSE_KEY_RECOVERED_ERROR -/// - SBC_SENSE_KEY_NOT_READY -/// - SBC_SENSE_KEY_MEDIUM_ERROR -/// - SBC_SENSE_KEY_HARDWARE_ERROR -/// - SBC_SENSE_KEY_ILLEGAL_REQUEST -/// - SBC_SENSE_KEY_UNIT_ATTENTION -/// - SBC_SENSE_KEY_DATA_PROTECT -/// - SBC_SENSE_KEY_BLANK_CHECK -/// - SBC_SENSE_KEY_VENDOR_SPECIFIC -/// - SBC_SENSE_KEY_COPY_ABORTED -/// - SBC_SENSE_KEY_ABORTED_COMMAND -/// - SBC_SENSE_KEY_VOLUME_OVERFLOW -/// - SBC_SENSE_KEY_MISCOMPARE - -/// No specific sense key. Successful command. -#define SBC_SENSE_KEY_NO_SENSE 0x00 -/// Command completed succesfully with some recovery action by the %device. -#define SBC_SENSE_KEY_RECOVERED_ERROR 0x01 -/// The device can not be accessed. -#define SBC_SENSE_KEY_NOT_READY 0x02 -/// Command terminated with a error condition that was probably caused by a -/// flaw in the medium or an error in the recorded data. -#define SBC_SENSE_KEY_MEDIUM_ERROR 0x03 -/// Hardware failure while performing the command or during a self test. -#define SBC_SENSE_KEY_HARDWARE_ERROR 0x04 -/// Illegal parameter found in the command or additional parameters. -#define SBC_SENSE_KEY_ILLEGAL_REQUEST 0x05 -/// Removable medium may have been changed or the %device has been reset. -#define SBC_SENSE_KEY_UNIT_ATTENTION 0x06 -/// Write on a block that is protected. -#define SBC_SENSE_KEY_DATA_PROTECT 0x07 -/// Indicates that a write-once device or a sequential-access device -/// encountered blank medium or format-defined end-of-data indication while -/// reading or a write-once device encountered a non-blank medium while writing. -#define SBC_SENSE_KEY_BLANK_CHECK 0x08 -/// Reporting vendor specific conditions. -#define SBC_SENSE_KEY_VENDOR_SPECIFIC 0x09 -/// EXTENDED COPY command was aborted. -#define SBC_SENSE_KEY_COPY_ABORTED 0x0A -/// Device aborted the command. -#define SBC_SENSE_KEY_ABORTED_COMMAND 0x0B -/// A buffered peripheral device is overflow. -#define SBC_SENSE_KEY_VOLUME_OVERFLOW 0x0D -/// The source data did not match the data read from the medium. -#define SBC_SENSE_KEY_MISCOMPARE 0x0E -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Sense Additionals" -/// This page lists additional sense code values returned in REQUEST SENSE data -/// \see spc4r06.pdf - Section 4.5.6 - Table 28 -/// -/// !Additional Codes -/// - SBC_ASC_LOGICAL_UNIT_NOT_READY -/// - SBC_ASC_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE -/// - SBC_ASC_INVALID_FIELD_IN_CDB -/// - SBC_ASC_WRITE_PROTECTED -/// - SBC_ASC_FORMAT_CORRUPTED -/// - SBC_ASC_INVALID_COMMAND_OPERATION_CODE -/// - SBC_ASC_TOO_MUCH_WRITE_DATA -/// - SBC_ASC_NOT_READY_TO_READY_CHANGE -/// - SBC_ASC_MEDIUM_NOT_PRESENT - -#define SBC_ASC_LOGICAL_UNIT_NOT_READY 0x04 -#define SBC_ASC_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE 0x21 -#define SBC_ASC_INVALID_FIELD_IN_CDB 0x24 -#define SBC_ASC_WRITE_PROTECTED 0x27 -#define SBC_ASC_FORMAT_CORRUPTED 0x31 -#define SBC_ASC_INVALID_COMMAND_OPERATION_CODE 0x20 -#define SBC_ASC_TOO_MUCH_WRITE_DATA 0x26 -#define SBC_ASC_NOT_READY_TO_READY_CHANGE 0x28 -#define SBC_ASC_MEDIUM_NOT_PRESENT 0x3A -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \brief MEDIUM TYPE field value for direct-access block devices -/// \see sbc3r06.pdf - Section 6.3.1 -#define SBC_MEDIUM_TYPE_DIRECT_ACCESS_BLOCK_DEVICE 0x00 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \brief MRIE field values -/// \see sbc3r06.pdf - Section 7.4.11 - Table 286 -#define SBC_MRIE_NO_REPORTING 0x00 -#define SBC_MRIE_ASYNCHRONOUS 0x01 -#define SBC_MRIE_GENERATE_UNIT_ATTENTION 0x02 -#define SBC_MRIE_COND_GENERATE_RECOVERED_ERROR 0x03 -#define SBC_MRIE_UNCOND_GENERATE_RECOVERED_ERROR 0x04 -#define SBC_MRIE_GENERATE_NO_SENSE 0x05 -#define SBC_MRIE_ON_REQUEST 0x06 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \brief Supported mode pages -/// \see sbc3r06.pdf - Section 6.3.1 - Table 115 -#define SBC_PAGE_READ_WRITE_ERROR_RECOVERY 0x01 -#define SBC_PAGE_INFORMATIONAL_EXCEPTIONS_CONTROL 0x1C -#define SBC_PAGE_RETURN_ALL 0x3F -#define SBC_PAGE_VENDOR_SPECIFIC 0x00 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Endian Macros" -/// This page lists the macros for endianness conversion. -/// -/// !Macros -/// - WORDB -/// - DWORDB -/// - STORE_DWORDB -/// - STORE_WORDB -/// \brief Converts a byte array to a word value using the big endian format -#define WORDB(bytes) ((unsigned short) ((bytes[0] << 8) | bytes[1])) - -/// \brief Converts a byte array to a dword value using the big endian format -#define DWORDB(bytes) ((unsigned int) ((bytes[0] << 24) | (bytes[1] << 16) \ - | (bytes[2] << 8) | bytes[3])) - -/// \brief Stores a dword value in a byte array, in big endian format -#define STORE_DWORDB(dword, bytes) \ - bytes[0] = (unsigned char) (((dword) >> 24) & 0xFF); \ - bytes[1] = (unsigned char) (((dword) >> 16) & 0xFF); \ - bytes[2] = (unsigned char) (((dword) >> 8) & 0xFF); \ - bytes[3] = (unsigned char) ((dword) & 0xFF); - -/// \brief Stores a word value in a byte array, in big endian format -#define STORE_WORDB(word, bytes) \ - bytes[0] = (unsigned char) (((word) >> 8) & 0xFF); \ - bytes[1] = (unsigned char) ((word) & 0xFF); -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Structures -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -/// \brief Structure for the INQUIRY command -/// \see spc4r06.pdf - Section 6.4.1 - Table 81 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x12 : SBC_INQUIRY - unsigned char isEVPD:1, //!< Type of requested data - bReserved1:7; //!< Reserved bits - unsigned char bPageCode; //!< Specifies the VPD to return - unsigned char pAllocationLength[2]; //!< Size of host buffer - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCInquiry; // GCC - -//------------------------------------------------------------------------------ -/// \brief Standard INQUIRY data format returned by the device -/// \see spc4r06.pdf - Section 6.4.2 - Table 82 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bPeripheralDeviceType:5, //!< Peripheral device type - bPeripheralQualifier :3; //!< Peripheral qualifier - unsigned char bReserved1:7, //!< Reserved bits - isRMB :1; //!< Is media removable ? - unsigned char bVersion; //!< SPC version used - unsigned char bResponseDataFormat:4, //!< Must be 0x2 - isHIGHSUP :1, //!< Hierarchical addressing used ? - isNORMACA :1, //!< ACA attribute supported ? - bObsolete1 :2; //!< Obsolete bits - unsigned char bAdditionalLength; //!< Length of remaining INQUIRY data - unsigned char isSCCS :1, //!< Embedded SCC ? - isACC :1, //!< Access control coordinator ? - bTPGS :2, //!< Target port support group - is3PC :1, //!< Third-party copy supported ? - bReserved2:2, //!< Reserved bits - isProtect :1; //!< Protection info supported ? - unsigned char bObsolete2:1, //!< Obsolete bit - isEncServ :1, //!< Embedded enclosure service comp? - isVS :1, //!< ??? - isMultiP :1, //!< Multi-port device ? - bObsolete3:3, //!< Obsolete bits - bUnused1 :1; //!< Unused feature - unsigned char bUnused2:6, //!< Unused features - isCmdQue:1, //!< Task management model supported ? - isVS2 :1; //!< ??? - unsigned char pVendorID[8]; //!< T10 vendor identification - unsigned char pProductID[16]; //!< Vendor-defined product ID - unsigned char pProductRevisionLevel[4];//!< Vendor-defined product revision - unsigned char pVendorSpecific[20]; //!< Vendor-specific data - unsigned char bUnused3; //!< Unused features - unsigned char bReserved3; //!< Reserved bits - unsigned short pVersionDescriptors[8]; //!< Standards the device complies to - unsigned char pReserved4[22]; //!< Reserved bytes - -} __attribute__ ((packed)) SBCInquiryData; // GCC - -//------------------------------------------------------------------------------ -/// \brief Data structure for the READ (10) command -/// \see sbc3r07.pdf - Section 5.7 - Table 34 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x28 : SBC_READ_10 - unsigned char bObsolete1:1, //!< Obsolete bit - isFUA_NV:1, //!< Cache control bit - bReserved1:1, //!< Reserved bit - isFUA:1, //!< Cache control bit - isDPO:1, //!< Cache control bit - bRdProtect:3; //!< Protection information to send - unsigned char pLogicalBlockAddress[4]; //!< Index of first block to read - unsigned char bGroupNumber:5, //!< Information grouping - bReserved2:3; //!< Reserved bits - unsigned char pTransferLength[2]; //!< Number of blocks to transmit - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCRead10; // GCC - -//------------------------------------------------------------------------------ -/// \brief Structure for the READ CAPACITY (10) command -/// \see sbc3r07.pdf - Section 5.11.1 - Table 40 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x25 : RBC_READ_CAPACITY - unsigned char bObsolete1:1, //!< Obsolete bit - bReserved1:7; //!< Reserved bits - unsigned char pLogicalBlockAddress[4]; //!< Block to evaluate if PMI is set - unsigned char pReserved2[2]; //!< Reserved bytes - unsigned char isPMI:1, //!< Partial medium indicator bit - bReserved3:7; //!< Reserved bits - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCReadCapacity10; - -//------------------------------------------------------------------------------ -/// \brief Data returned by the device after a READ CAPACITY (10) command -/// \see sbc3r07.pdf - Section 5.11.2 - Table 41 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char pLogicalBlockAddress[4]; //!< Address of last logical block - unsigned char pLogicalBlockLength[4]; //!< Length of each logical block - -} __attribute__ ((packed)) SBCReadCapacity10Data; - -//------------------------------------------------------------------------------ -/// \brief Structure for the REQUEST SENSE command -/// \see spc4r06.pdf - Section 6.26 - Table 170 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x03 : SBC_REQUEST_SENSE - unsigned char isDesc :1, //!< Type of information expected - bReserved1:7; //!< Reserved bits - unsigned char pReserved2[2]; //!< Reserved bytes - unsigned char bAllocationLength; //!< Size of host buffer - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCRequestSense; - -//------------------------------------------------------------------------------ -/// \brief Fixed format sense data returned after a REQUEST SENSE command has -/// been received with a DESC bit cleared. -/// \see spc4r06.pdf - Section 4.5.3 - Table 26 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bResponseCode:7, //!< Sense data format - isValid :1; //!< Information field is standard - unsigned char bObsolete1; //!< Obsolete byte - unsigned char bSenseKey :4, //!< Generic error information - bReserved1:1, //!< Reserved bit - isILI :1, //!< SSC - isEOM :1, //!< SSC - isFilemark:1; //!< SSC - unsigned char pInformation[4]; //!< Command-specific - unsigned char bAdditionalSenseLength; //!< sizeof(SBCRequestSense_data)-8 - unsigned char pCommandSpecificInformation[4]; //!< Command-specific - unsigned char bAdditionalSenseCode; //!< Additional error information - unsigned char bAdditionalSenseCodeQualifier; //!< Further error information - unsigned char bFieldReplaceableUnitCode; //!< Specific component code - unsigned char bSenseKeySpecific:7, //!< Additional exception info - isSKSV :1; //!< Is sense key specific valid? - unsigned char pSenseKeySpecific[2]; //!< Additional exception info - -} __attribute__ ((packed)) SBCRequestSenseData; - -//------------------------------------------------------------------------------ -/// \brief Data structure for the TEST UNIT READY command -/// \see spc4r06.pdf - Section 6.34 - Table 192 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x00 : SBC_TEST_UNIT_READY - unsigned char pReserved1[4]; //!< Reserved bits - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCTestUnitReady; // GCC - -//------------------------------------------------------------------------------ -/// \brief Structure for the WRITE (10) command -/// \see sbc3r07.pdf - Section 5.26 - Table 70 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x2A : SBC_WRITE_10 - unsigned char bObsolete1:1, //!< Obsolete bit - isFUA_NV:1, //!< Cache control bit - bReserved1:1, //!< Reserved bit - isFUA:1, //!< Cache control bit - isDPO:1, //!< Cache control bit - bWrProtect:3; //!< Protection information to send - unsigned char pLogicalBlockAddress[4]; //!< First block to write - unsigned char bGroupNumber:5, //!< Information grouping - bReserved2:3; //!< Reserved bits - unsigned char pTransferLength[2]; //!< Number of blocks to write - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCWrite10; - -//------------------------------------------------------------------------------ -/// \brief Structure for the PREVENT/ALLOW MEDIUM REMOVAL command -/// \see sbc3r07.pdf - Section 5.5 - Table 30 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x1E : SBC_PREVENT_ALLOW_MEDIUM_REMOVAL - unsigned char pReserved1[3]; //!< Reserved bytes - unsigned char bPrevent:2, //!< Accept/prohibit removal - bReserved2:6; //!< Reserved bits - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCMediumRemoval; // GCC - -//------------------------------------------------------------------------------ -/// \brief Structure for the MODE SENSE (6) command -/// \see spc4r06 - Section 6.9.1 - Table 98 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x1A : SBC_MODE_SENSE_6 - unsigned char bReserved1:3, //!< Reserved bits - isDBD:1, //!< Disable block descriptors bit - bReserved2:4; //!< Reserved bits - unsigned char bPageCode:6, //!< Mode page to return - bPC:2; //!< Type of parameter values to return - unsigned char bSubpageCode; //!< Mode subpage to return - unsigned char bAllocationLength; //!< Host buffer allocated size - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCModeSense6; // GCC - -//------------------------------------------------------------------------------ -/// \brief Header for the data returned after a MODE SENSE (6) command -/// \see spc4r06.pdf - Section 7.4.3 - Table 268 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bModeDataLength; //!< Length of mode data to follow - unsigned char bMediumType; //!< Type of medium (SBC_MEDIUM_TYPE_DIRECT_ACCESS_BLOCK_DEVICE) - unsigned char bReserved1:4, //!< Reserved bits - isDPOFUA:1, //!< DPO/FUA bits supported ? - bReserved2:2, //!< Reserved bits - isWP:1; //!< Is medium write-protected ? - unsigned char bBlockDescriptorLength; //!< Length of all block descriptors - -} __attribute__ ((packed)) SBCModeParameterHeader6; // GCC - -//------------------------------------------------------------------------------ -/// \brief Informational exceptions control mode page -/// \see spc4r06.pdf - Section 7.4.11 - Table 285 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bPageCode:6, //!< 0x1C : SBC_PAGE_INFORMATIONAL_EXCEPTIONS_CONTROL - isSPF:1, //!< Page or subpage data format - isPS:1; //!< Parameters saveable ? - unsigned char bPageLength; //!< Length of page data (0x0A) - unsigned char isLogErr:1, //!< Should informational exceptions be logged ? - isEBackErr:1, //!< Enable background error bit - isTest:1, //!< Create a device test failure ? - isDExcpt:1, //!< Disable exception control bit - isEWasc:1, //!< Report warnings ? - isEBF:1, //!< Enable background function bit - bReserved1:1, //!< Reserved bit - isPerf:1; //!< Delay acceptable when treating exceptions ? - unsigned char bMRIE:4, //!< Method of reporting informational exceptions - bReserved2:4; //!< Reserved bits - unsigned char pIntervalTimer[4]; //!< Error reporting period - unsigned char pReportCount[4]; //!< Maximum number of time a report can be issued - -} __attribute__ ((packed)) SBCInformationalExceptionsControl; // GCC - -//------------------------------------------------------------------------------ -/// \brief Read/write error recovery mode page -/// \see sbc3r07.pdf - Section 6.3.5 - Table 122 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bPageCode:6, //!< 0x01 : SBC_PAGE_READ_WRITE_ERROR_RECOVERY - isSPF:1, //!< Page or subpage data format - isPS:1; //!< Parameters saveable ? - unsigned char bPageLength; //!< Length of page data (0x0A) - unsigned char isDCR:1, //!< Disable correction bit - isDTE:1, //!< Data terminate on error bit - isPER:1, //!< Post error bit - isEER:1, //!< Enable early recovery bit - isRC:1, //!< Read continuous bit - isTB:1, //!< Transfer block bit - isARRE:1, //!< Automatic read reallocation enabled bit - isAWRE:1; //!< Automatic write reallocation enabled bit - unsigned char bReadRetryCount; //!< Number of retries when reading - unsigned char pObsolete1[3]; //!< Obsolete bytes - unsigned char bReserved1; //!< Reserved byte - unsigned char bWriteRetryCount; //!< Number of retries when writing - unsigned char bReserved2; //!< Reserved byte - unsigned char pRecoveryTimeLimit[2]; //!< Maximum time duration for error recovery - -} __attribute__ ((packed)) SBCReadWriteErrorRecovery; // GCC - -//------------------------------------------------------------------------------ -/// \brief Generic structure for holding information about SBC commands -/// \see SBCInquiry -/// \see SBCRead10 -/// \see SBCReadCapacity10 -/// \see SBCRequestSense -/// \see SBCTestUnitReady -/// \see SBCWrite10 -/// \see SBCMediumRemoval -/// \see SBCModeSense6 -//------------------------------------------------------------------------------ -typedef union { - - unsigned char bOperationCode; //!< Operation code of the command - SBCInquiry inquiry; //!< INQUIRY command - SBCRead10 read10; //!< READ (10) command - SBCReadCapacity10 readCapacity10; //!< READ CAPACITY (10) command - SBCRequestSense requestSense; //!< REQUEST SENSE command - SBCTestUnitReady testUnitReady; //!< TEST UNIT READY command - SBCWrite10 write10; //!< WRITE (10) command - SBCMediumRemoval mediumRemoval; //!< PREVENT/ALLOW MEDIUM REMOVAL command - SBCModeSense6 modeSense6; //!< MODE SENSE (6) command - -} SBCCommand; - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -#endif //#ifndef SBC_H - diff --git a/radio/bootloader/usb/device/massstorage/SBCMethods.c b/radio/bootloader/usb/device/massstorage/SBCMethods.c deleted file mode 100644 index 26c85eedf..000000000 --- a/radio/bootloader/usb/device/massstorage/SBCMethods.c +++ /dev/null @@ -1,1624 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "SBCMethods.h" -#include "MSDDStateMachine.h" -#include - -#include "MSDIOFifo.h" - -//------------------------------------------------------------------------------ -// Global variables -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Macros -//------------------------------------------------------------------------------ - -#ifdef MSDIO_READ10_CHUNK_SIZE -/// READ10 - Read data from specific LUN to FIFO -#define SBC_READ_CHUNK(pLun, lba, pFifo, pCb, pArg) \ - LUN_Read((pLun), (lba), \ - &(pFifo)->pBuffer[(pFifo)->inputNdx], \ - ((pFifo)->chunkSize/(pFifo)->blockSize), \ - (TransferCallback)(pCb), (void*)pArg) -/// READ10 - Transfer data from FIFO to USB -#define SBC_TX_CHUNK(pFifo, pCb, pArg) \ - MSDD_Write(&(pFifo)->pBuffer[(pFifo)->outputNdx], \ - (pFifo)->chunkSize, \ - (TransferCallback)(pCb), (void*)(pArg)) -#endif - -#ifdef MSDIO_WRITE10_CHUNK_SIZE -/// WRITE10 - Read data from USB to FIFO -#define SBC_RX_CHUNK(pFifo,pCb,pArg) \ - MSDD_Read(&(pFifo)->pBuffer[(pFifo)->inputNdx], \ - (pFifo)->chunkSize, \ - (TransferCallback)(pCb), (void*)(pArg)) -/// WRITE10 - Write data from FIFO to LUN -#define SBC_WRITE_CHUNK(pLun, lba, pFifo, pCb, pArg) \ - LUN_Write((pLun), (lba), \ - &(pFifo)->pBuffer[(pFifo)->outputNdx], \ - ((pFifo)->chunkSize/(pFifo)->blockSize), \ - (TransferCallback)(pCb), (void*)(pArg)) -#endif - - -//------------------------------------------------------------------------------ -//! \brief Header for the mode pages data -//! \see SBCModeParameterHeader6 -//------------------------------------------------------------------------------ -static const SBCModeParameterHeader6 modeParameterHeader6 = { - - sizeof(SBCModeParameterHeader6) - 1, //! Length is 0x03 - SBC_MEDIUM_TYPE_DIRECT_ACCESS_BLOCK_DEVICE, //! Direct-access block device - 0, //! Reserved bits - 0, //! DPO/FUA not supported - 0, //! Reserved bits - 0, //! not write-protected - 0 //! No block descriptor -}; - -//------------------------------------------------------------------------------ -// Internal functions -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -//! \brief Check if the LUN is ready. -//! \param lun Pointer to the LUN affected by the command -//! \return 1 if the LUN is ready to be written -//! \see MSDLun -//------------------------------------------------------------------------------ -static unsigned char SBCLunIsReady(MSDLun *lun) -{ - unsigned char lunIsReady = 0; - Media *media = lun->media; - - if (media == 0 || lun->status < LUN_CHANGED) { - TRACE_INFO("SBCLunIsReady: Not Present!\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_NOT_READY, - SBC_ASC_MEDIUM_NOT_PRESENT, - 0); - - } - else if (lun->status < LUN_READY) { - TRACE_INFO("SBCLunIsReady: Changing!\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_UNIT_ATTENTION, - SBC_ASC_NOT_READY_TO_READY_CHANGE, - 0); - lun->status = LUN_READY; - } - else { - - lunIsReady = 1; - } - - return lunIsReady; -} -//------------------------------------------------------------------------------ -//! \brief Check if the LUN can write. -//! \param lun Pointer to the LUN affected by the command -//! \return 1 if the LUN is ready to be written -//! \see MSDLun -//------------------------------------------------------------------------------ -static unsigned char SBCLunCanBeWritten(MSDLun *lun) -{ - unsigned char canBeWritten = 0; - - if (!SBCLunIsReady(lun)) { - - TRACE_WARNING("SBCLunCanBeWritten: Not Ready!\n\r"); - } - else if (lun->protected) { - - TRACE_WARNING("SBCLunCanBeWritten: Protected!\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_DATA_PROTECT, - SBC_ASC_WRITE_PROTECTED, - 0); - } - else { - - canBeWritten = 1; - } - - return canBeWritten; -} - -//------------------------------------------------------------------------------ -//! \brief Performs a WRITE (10) command on the specified LUN. -//! -//! The data to write is first received from the USB host and then -//! actually written on the media. -//! This function operates asynchronously and must be called multiple -//! times to complete. A result code of MSDDriver_STATUS_INCOMPLETE -//! indicates that at least another call of the method is necessary. -//! \param lun Pointer to the LUN affected by the command -//! \param commandState Current state of the command -//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) -//! \see MSDLun -//! \see MSDCommandState -//------------------------------------------------------------------------------ -static unsigned char SBC_Write10(MSDLun *lun, - MSDCommandState *commandState) -{ - unsigned char status; - unsigned char result = MSDD_STATUS_INCOMPLETE; - SBCRead10 *command = (SBCRead10 *) commandState->cbw.pCommand; - MSDTransfer *transfer = &(commandState->transfer); - MSDTransfer *disktransfer = &(commandState->disktransfer); - MSDIOFifo *fifo = &lun->ioFifo; - Media *media = lun->media; - - // Init command state - if (commandState->state == 0) { - - commandState->state = SBC_STATE_WRITE; - - // The command should not be proceeded if READONLY - if (!SBCLunCanBeWritten(lun)) { - - return MSDD_STATUS_RW; - } - else { - - - // Initialize FIFO - fifo->dataTotal = commandState->length; - fifo->blockSize = lun->blockSize * media->blockSize; - #ifdef MSDIO_WRITE10_CHUNK_SIZE - if ( fifo->dataTotal >= 64 * 1024 - && fifo->blockSize < MSDIO_WRITE10_CHUNK_SIZE) - fifo->chunkSize = MSDIO_WRITE10_CHUNK_SIZE; - else - fifo->chunkSize = fifo->blockSize; - #endif - fifo->fullCnt = 0; - fifo->nullCnt = 0; - - // Initialize FIFO output (Disk) - fifo->outputNdx = 0; - fifo->outputTotal = 0; - fifo->outputState = MSDIO_IDLE; - transfer->semaphore = 0; - - // Initialize FIFO input (USB) - fifo->inputNdx = 0; - fifo->inputTotal = 0; - fifo->inputState = MSDIO_START; - disktransfer->semaphore = 0; - } - - } - - if (commandState->length == 0) { - - // Perform the callback! - if (lun->dataMonitor) { - - lun->dataMonitor(0, fifo->dataTotal, fifo->nullCnt, fifo->fullCnt); - } - return MSDD_STATUS_SUCCESS; - } - - // USB receive task - switch(fifo->inputState) { - - //------------------ - case MSDIO_IDLE: - //------------------ - if (fifo->inputTotal < fifo->dataTotal && - fifo->inputTotal - fifo->outputTotal < fifo->bufferSize) { - - fifo->inputState = MSDIO_START; - } - break; - - //------------------ - case MSDIO_START: - //------------------ - // Should not start if there is any disk error - if (fifo->outputState == MSDIO_ERROR) { - - TRACE_INFO_WP("udErr "); - fifo->inputState = MSDIO_ERROR; - break; - } - - // Read one block of data sent by the host - if (media->mappedWR) { - - // Directly read to memory - status = MSDD_Read((void*) - ((media->baseAddress - + (lun->baseAddress - + DWORDB(command->pLogicalBlockAddress) - * lun->blockSize - ) - ) * media->blockSize - ), - fifo->dataTotal, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - } - else { - #ifdef MSDIO_WRITE10_CHUNK_SIZE - status = SBC_RX_CHUNK(fifo, MSDDriver_Callback, transfer); - #else - // Read block to buffer - status = MSDD_Read((void*)&fifo->pBuffer[fifo->inputNdx], - fifo->blockSize, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - #endif - } - - // Check operation result code - if (status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_Write10: Failed to start receiving\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_HARDWARE_ERROR, - 0, - 0); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("uRx "); - - // Prepare next device state - fifo->inputState = MSDIO_WAIT; - } - break; // MSDIO_START - - //------------------ - case MSDIO_WAIT: - //------------------ - TRACE_INFO_WP("uWait "); - - // Check semaphore - if (transfer->semaphore > 0) { - - transfer->semaphore--; - fifo->inputState = MSDIO_NEXT; - } - break; - - //------------------ - case MSDIO_NEXT: - //------------------ - // Check the result code of the read operation - if (transfer->status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_Write10: Failed to received\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_HARDWARE_ERROR, - 0, - 0); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("uNxt "); - - // Mapped read, all data done - if (media->mappedWR) { - - fifo->inputTotal = fifo->dataTotal; - fifo->inputState = MSDIO_IDLE; - } - else { - - // Update input index - #ifdef MSDIO_WRITE10_CHUNK_SIZE - MSDIOFifo_IncNdx(fifo->inputNdx, - fifo->chunkSize, - fifo->bufferSize); - fifo->inputTotal += fifo->chunkSize; - #else - MSDIOFifo_IncNdx(fifo->inputNdx, - fifo->blockSize, - fifo->bufferSize); - fifo->inputTotal += fifo->blockSize; - #endif - - // Start Next block - // - All Data done? - if (fifo->inputTotal >= fifo->dataTotal) { - - fifo->inputState = MSDIO_IDLE; - } - // - Buffer full? - else if (fifo->inputNdx == fifo->outputNdx) { - fifo->inputState = MSDIO_IDLE; - fifo->fullCnt ++; - - TRACE_DEBUG_WP("ufFull%d ", fifo->inputNdx); - } - // - More data to transfer? - else if (fifo->inputTotal < fifo->dataTotal) { - fifo->inputState = MSDIO_START; - - TRACE_INFO_WP("uStart "); - } - // never executed ! - //else { - // fifo->inputState = MSDIO_IDLE; - // TRACE_INFO_WP("uDone "); - //} - } - - } - break; // MSDIO_NEXT - - //------------------ - case MSDIO_ERROR: - //------------------ - - TRACE_WARNING_WP("uErr "); - commandState->length -= fifo->inputTotal; - return MSDD_STATUS_RW; - - } - - // Disk write task - switch(fifo->outputState) { - - //------------------ - case MSDIO_IDLE: - //------------------ - if (fifo->outputTotal < fifo->inputTotal) { - - fifo->outputState = MSDIO_START; - } - break; - - //------------------ - case MSDIO_START: - //------------------ - - // Write the block to the media - if (media->mappedWR) { - - MSDDriver_Callback(disktransfer, MED_STATUS_SUCCESS, 0, 0); - status = LUN_STATUS_SUCCESS; - } - else { - #ifdef MSDIO_WRITE10_CHUNK_SIZE - status = SBC_WRITE_CHUNK(lun, DWORDB(command->pLogicalBlockAddress), - fifo, MSDDriver_Callback, disktransfer); - #else - status = LUN_Write(lun, - DWORDB(command->pLogicalBlockAddress), - &fifo->pBuffer[fifo->outputNdx], - 1, - (TransferCallback) MSDDriver_Callback, - (void *) disktransfer); - #endif - } - - // Check operation result code - if (status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_Write10: Failed to start write - "); - - if (!SBCLunCanBeWritten(lun)) { - - TRACE_WARNING("?\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_NOT_READY, - 0, - 0); - } - - fifo->outputState = MSDIO_ERROR; - } - else { - - // Prepare next state - fifo->outputState = MSDIO_WAIT; - } - break; // MSDIO_START - - //------------------ - case MSDIO_WAIT: - //------------------ - TRACE_INFO_WP("dWait "); - - // Check semaphore value - if (disktransfer->semaphore > 0) { - - // Take semaphore and move to next state - disktransfer->semaphore--; - fifo->outputState = MSDIO_NEXT; - } - break; - - //------------------ - case MSDIO_NEXT: - //------------------ - // Check operation result code - if (transfer->status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_Write10: Failed to write\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_RECOVERED_ERROR, - SBC_ASC_TOO_MUCH_WRITE_DATA, - 0); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("dNxt "); - - // Update transfer length and block address - - // Mapped memory, done - if (media->mappedWR) { - - commandState->length = 0; - fifo->outputState = MSDIO_IDLE; - } - else { - - // Update output index - #ifdef MSDIO_WRITE10_CHUNK_SIZE - STORE_DWORDB(DWORDB(command->pLogicalBlockAddress) - + fifo->chunkSize/fifo->blockSize, - command->pLogicalBlockAddress); - MSDIOFifo_IncNdx(fifo->outputNdx, - fifo->chunkSize, - fifo->bufferSize); - fifo->outputTotal += fifo->chunkSize; - #else - STORE_DWORDB(DWORDB(command->pLogicalBlockAddress) + 1, - command->pLogicalBlockAddress); - MSDIOFifo_IncNdx(fifo->outputNdx, - fifo->blockSize, - fifo->bufferSize); - fifo->outputTotal += fifo->blockSize; - #endif - - // Start Next block - // - All data done? - if (fifo->outputTotal >= fifo->dataTotal) { - - fifo->outputState = MSDIO_IDLE; - commandState->length = 0; - TRACE_INFO_WP("dDone "); - } - // - Send next? - else if (fifo->outputTotal < fifo->inputTotal) { - - fifo->outputState = MSDIO_START; - TRACE_INFO_WP("dStart "); - } - // - Buffer Null? - else { - fifo->outputState = MSDIO_IDLE; - fifo->nullCnt ++; - - TRACE_DEBUG_WP("dfNull%d ", fifo->outputNdx); - } - } - } - break; // MSDIO_NEXT - - //------------------ - case MSDIO_ERROR: - //------------------ - break; - } - - return result; -} - -//------------------------------------------------------------------------------ -//! \brief Performs a READ (10) command on specified LUN. -//! -//! The data is first read from the media and then sent to the USB host. -//! This function operates asynchronously and must be called multiple -//! times to complete. A result code of MSDDriver_STATUS_INCOMPLETE -//! indicates that at least another call of the method is necessary. -//! \param lun Pointer to the LUN affected by the command -//! \param commandState Current state of the command -//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) -//! \see MSDLun -//! \see MSDCommandState -//------------------------------------------------------------------------------ -static unsigned char SBC_Read10(MSDLun *lun, - MSDCommandState *commandState) -{ - unsigned char status; - unsigned char result = MSDD_STATUS_INCOMPLETE; - SBCRead10 *command = (SBCRead10 *) commandState->cbw.pCommand; - MSDTransfer *transfer = &(commandState->transfer); - MSDTransfer *disktransfer = &(commandState->disktransfer); - MSDIOFifo *fifo = &lun->ioFifo; - Media *media = lun->media; - - // Init command state - if (commandState->state == 0) { - - commandState->state = SBC_STATE_READ; - - if (!SBCLunIsReady(lun)) { - - return MSDD_STATUS_RW; - } - else { - - // Initialize FIFO - fifo->dataTotal = commandState->length; - fifo->blockSize = lun->blockSize * media->blockSize; - #ifdef MSDIO_READ10_CHUNK_SIZE - if ( fifo->dataTotal >= 64*1024 - && fifo->blockSize < MSDIO_READ10_CHUNK_SIZE) - fifo->chunkSize = MSDIO_READ10_CHUNK_SIZE; - else - fifo->chunkSize = fifo->blockSize; - #endif - fifo->fullCnt = 0; - fifo->nullCnt = 0; - - #ifdef MSDIO_FIFO_OFFSET - // Enable offset if total size >= 2*bufferSize - if (fifo->dataTotal / fifo->bufferSize >= 2) - fifo->bufferOffset = MSDIO_FIFO_OFFSET; - else - fifo->bufferOffset = 0; - #endif - - // Initialize FIFO output (USB) - fifo->outputNdx = 0; - fifo->outputTotal = 0; - fifo->outputState = MSDIO_IDLE; - transfer->semaphore = 0; - - // Initialize FIFO input (Disk) - fifo->inputNdx = 0; - fifo->inputTotal = 0; - fifo->inputState = MSDIO_START; - disktransfer->semaphore = 0; - } - } - - // Check length - if (commandState->length == 0) { - - // Perform the callback! - if (lun->dataMonitor) { - - lun->dataMonitor(1, fifo->dataTotal, fifo->nullCnt, fifo->fullCnt); - } - return MSDD_STATUS_SUCCESS; - } - - // Disk reading task - switch(fifo->inputState) { - - //------------------ - case MSDIO_IDLE: - //------------------ - if (fifo->inputTotal < fifo->dataTotal && - fifo->inputTotal - fifo->outputTotal < fifo->bufferSize) { - - fifo->inputState = MSDIO_START; - } - break; - - //------------------ - case MSDIO_START: - //------------------ - // Read one block of data from the media - if (media->mappedRD) { - - // Directly write, no read needed - MSDDriver_Callback(disktransfer, MED_STATUS_SUCCESS, 0, 0); - status = LUN_STATUS_SUCCESS; - } - else { - #ifdef MSDIO_READ10_CHUNK_SIZE - status = SBC_READ_CHUNK(lun, DWORDB(command->pLogicalBlockAddress), - fifo, MSDDriver_Callback, disktransfer); - #else - status = LUN_Read(lun, - DWORDB(command->pLogicalBlockAddress), - &fifo->pBuffer[fifo->inputNdx], - 1, - (TransferCallback) MSDDriver_Callback, - (void *)disktransfer); - #endif - } - - // Check operation result code - if (status != LUN_STATUS_SUCCESS) { - - TRACE_WARNING("RBC_Read10: Failed to start reading\n\r"); - - if (SBCLunIsReady(lun)) { - - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_NOT_READY, - SBC_ASC_LOGICAL_UNIT_NOT_READY, - 0); - } - - fifo->inputState = MSDIO_ERROR; - } - else { - - TRACE_INFO_WP("dRd "); - - // Move to next command state - fifo->inputState = MSDIO_WAIT; - } - break; // MSDIO_START - - //------------------ - case MSDIO_WAIT: - //------------------ - // Check semaphore value - if (disktransfer->semaphore > 0) { - - TRACE_INFO_WP("dOk "); - - // Take semaphore and move to next state - disktransfer->semaphore--; - fifo->inputState = MSDIO_NEXT; - } - break; - - //------------------ - case MSDIO_NEXT: - //------------------ - // Check the operation result code - if (disktransfer->status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_Read10: Failed to read media\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_RECOVERED_ERROR, - SBC_ASC_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, - 0); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("dNxt "); - - if (media->mappedRD) { - - // All data is ready - fifo->inputState = MSDIO_IDLE; - fifo->inputTotal = fifo->dataTotal; - } - else { - - // Update block address - #ifdef MSDIO_READ10_CHUNK_SIZE - STORE_DWORDB(DWORDB(command->pLogicalBlockAddress) - + fifo->chunkSize/fifo->blockSize, - command->pLogicalBlockAddress); - - // Update input index - MSDIOFifo_IncNdx(fifo->inputNdx, - fifo->chunkSize, - fifo->bufferSize); - fifo->inputTotal += fifo->chunkSize; - #else - // Update block address - STORE_DWORDB(DWORDB(command->pLogicalBlockAddress) + 1, - command->pLogicalBlockAddress); - - // Update input index - MSDIOFifo_IncNdx(fifo->inputNdx, - fifo->blockSize, - fifo->bufferSize); - fifo->inputTotal += fifo->blockSize; - #endif - - // Start Next block - // - All Data done? - if (fifo->inputTotal >= fifo->dataTotal) { - - TRACE_INFO_WP("dDone "); - fifo->inputState = MSDIO_IDLE; - } - // - Buffer full? - else if (fifo->inputNdx == fifo->outputNdx) { - - TRACE_INFO_WP("dfFull%d ", (int)fifo->inputNdx); - fifo->inputState = MSDIO_IDLE; - fifo->fullCnt ++; - } - // - More data to transfer? - else if (fifo->inputTotal < fifo->dataTotal) { - - TRACE_DEBUG_WP("dStart "); - fifo->inputState = MSDIO_START; - } - } - - } - - break; - - //------------------ - case MSDIO_ERROR: - //------------------ - break; - } - - // USB sending task - switch(fifo->outputState) { - - //------------------ - case MSDIO_IDLE: - //------------------ - if (fifo->outputTotal < fifo->inputTotal) { - - #ifdef MSDIO_FIFO_OFFSET - // Offset buffer the input data - if (fifo->bufferOffset) { - if (fifo->inputTotal < fifo->bufferOffset) { - break; - } - fifo->bufferOffset = 0; - } - #endif - fifo->outputState = MSDIO_START; - } - break; - - //------------------ - case MSDIO_START: - //------------------ - // Should not start if there is any disk error - if (fifo->outputState == MSDIO_ERROR) { - - fifo->inputState = MSDIO_ERROR; - break; - } - - // Send the block to the host - if (media->mappedRD) { - - status = MSDD_Write((void*) - ((media->baseAddress - + (lun->baseAddress - + DWORDB(command->pLogicalBlockAddress) - * lun->blockSize - ) - ) * media->blockSize - ), - commandState->length, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - } - else { - #ifdef MSDIO_READ10_CHUNK_SIZE - status = SBC_TX_CHUNK(fifo, MSDDriver_Callback, transfer); - #else - status = MSDD_Write(&fifo->pBuffer[fifo->outputNdx], - fifo->blockSize, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - #endif - } - // Check operation result code - if (status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_Read10: Failed to start to send\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_HARDWARE_ERROR, - 0, - 0); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("uTx "); - - // Move to next command state - fifo->outputState = MSDIO_WAIT; - } - break; // MSDIO_START - - //------------------ - case MSDIO_WAIT: - //------------------ - // Check semaphore value - if (transfer->semaphore > 0) { - - TRACE_INFO_WP("uOk "); - - // Take semaphore and move to next state - transfer->semaphore--; - fifo->outputState = MSDIO_NEXT; - } - break; - - //------------------ - case MSDIO_NEXT: - //------------------ - // Check operation result code - if (transfer->status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_Read10: Failed to send data\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_HARDWARE_ERROR, - 0, - 0); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("uNxt "); - - if (media->mappedRD) { - - commandState->length = 0; - } - else { - - // Update output index - #ifdef MSDIO_READ10_CHUNK_SIZE - MSDIOFifo_IncNdx(fifo->outputNdx, - fifo->chunkSize, - fifo->bufferSize); - fifo->outputTotal += fifo->chunkSize; - #else - MSDIOFifo_IncNdx(fifo->outputNdx, - fifo->blockSize, - fifo->bufferSize); - fifo->outputTotal += fifo->blockSize; - #endif - - // Start Next block - // - All data done? - if (fifo->outputTotal >= fifo->dataTotal) { - - fifo->outputState = MSDIO_IDLE; - commandState->length = 0; - TRACE_INFO_WP("uDone "); - } - // - Buffer Null? - else if (fifo->inputNdx == fifo->outputNdx) { - - TRACE_INFO_WP("ufNull%d ", (int)fifo->outputNdx); - fifo->outputState = MSDIO_IDLE; - fifo->nullCnt ++; - } - // - Send next? - else if (fifo->outputTotal < fifo->inputTotal) { - - TRACE_DEBUG_WP("uStart "); - fifo->outputState = MSDIO_START; - } - } - - } - break; - - //------------------ - case MSDIO_ERROR: - //------------------ - break; - } - - return result; -} - -//------------------------------------------------------------------------------ -//! \brief Performs a READ CAPACITY (10) command. -//! -//! This function operates asynchronously and must be called multiple -//! times to complete. A result code of MSDD_STATUS_INCOMPLETE -//! indicates that at least another call of the method is necessary. -//! \param lun Pointer to the LUN affected by the command -//! \param commandState Current state of the command -//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) -//! \see MSDLun -//! \see MSDCommandState -//------------------------------------------------------------------------------ -static unsigned char SBC_ReadCapacity10(MSDLun *lun, - MSDCommandState *commandState) -{ - unsigned char result = MSDD_STATUS_INCOMPLETE; - unsigned char status; - MSDTransfer *transfer = &(commandState->transfer); - - if (!SBCLunIsReady(lun)) { - - TRACE_INFO("SBC_ReadCapacity10: Not Ready!\n\r"); - return MSDD_STATUS_RW; - } - - // Initialize command state if needed - if (commandState->state == 0) { - - commandState->state = SBC_STATE_WRITE; - } - - // Identify current command state - switch (commandState->state) { - //------------------- - case SBC_STATE_WRITE: - //------------------- - // Start the write operation - status = MSDD_Write(&(lun->readCapacityData), - commandState->length, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - - // Check operation result code - if (status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_ReadCapacity: Cannot start sending data\n\r"); - result = MSDD_STATUS_ERROR; - } - else { - - // Proceed to next command state - TRACE_INFO_WP("Sending "); - commandState->state = SBC_STATE_WAIT_WRITE; - } - break; - - //------------------------ - case SBC_STATE_WAIT_WRITE: - //------------------------ - // Check semaphore value - if (transfer->semaphore > 0) { - - // Take semaphore and terminate command - transfer->semaphore--; - - if (transfer->status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING("RBC_ReadCapacity: Cannot send data\n\r"); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("Sent "); - result = MSDD_STATUS_SUCCESS; - } - commandState->length -= transfer->transferred; - } - break; - } - - return result; -} - -//------------------------------------------------------------------------------ -//! \brief Handles an INQUIRY command. -//! -//! This function operates asynchronously and must be called multiple -//! times to complete. A result code of MSDDriver_STATUS_INCOMPLETE -//! indicates that at least another call of the method is necessary. -//! \param lun Pointer to the LUN affected by the command -//! \param commandState Current state of the command -//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) -//! \see MSDLun -//! \see MSDCommandState -//------------------------------------------------------------------------------ -static unsigned char SBC_Inquiry(MSDLun *lun, - MSDCommandState *commandState) -{ - unsigned char result = MSDD_STATUS_INCOMPLETE; - unsigned char status; - MSDTransfer *transfer = &(commandState->transfer); - - // Check if required length is 0 - if (commandState->length == 0) { - - // Nothing to do - result = MSDD_STATUS_SUCCESS; - } - // Initialize command state if needed - else if (commandState->state == 0) { - - commandState->state = SBC_STATE_WRITE; - - // Change additional length field of inquiry data - lun->inquiryData->bAdditionalLength - = (unsigned char) (commandState->length - 5); - } - - // Identify current command state - switch (commandState->state) { - //------------------- - case SBC_STATE_WRITE: - //------------------- - // Start write operation - status = MSDD_Write((void *) lun->inquiryData, - commandState->length, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - - // Check operation result code - if (status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "SPC_Inquiry: Cannot start sending data\n\r"); - result = MSDD_STATUS_ERROR; - } - else { - - // Proceed to next state - TRACE_INFO_WP("Sending "); - commandState->state = SBC_STATE_WAIT_WRITE; - } - break; - - //------------------------ - case SBC_STATE_WAIT_WRITE: - //------------------------ - // Check the semaphore value - if (transfer->semaphore > 0) { - - // Take semaphore and terminate command - transfer->semaphore--; - - if (transfer->status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "SPC_Inquiry: Data transfer failed\n\r"); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("Sent "); - result = MSDD_STATUS_SUCCESS; - } - - // Update length field - commandState->length -= transfer->transferred; - } - break; - } - - return result; -} - -//------------------------------------------------------------------------------ -//! \brief Performs a REQUEST SENSE command. -//! -//! This function operates asynchronously and must be called multiple -//! times to complete. A result code of MSDDriver_STATUS_INCOMPLETE -//! indicates that at least another call of the method is necessary. -//! \param lun Pointer to the LUN affected by the command -//! \param commandState Current state of the command -//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) -//! \see MSDLun -//! \see MSDCommandState -//------------------------------------------------------------------------------ -static unsigned char SBC_RequestSense(MSDLun *lun, - MSDCommandState *commandState) -{ - unsigned char result = MSDD_STATUS_INCOMPLETE; - unsigned char status; - MSDTransfer *transfer = &(commandState->transfer); - - // Check if requested length is zero - if (commandState->length == 0) { - - // Nothing to do - result = MSDD_STATUS_SUCCESS; - } - // Initialize command state if needed - else if (commandState->state == 0) { - - commandState->state = SBC_STATE_WRITE; - } - - // Identify current command state - switch (commandState->state) { - //------------------- - case SBC_STATE_WRITE: - //------------------- - // Start transfer - status = MSDD_Write(&(lun->requestSenseData), - commandState->length, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - - // Check result code - if (status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_RequestSense: Cannot start sending data\n\r"); - result = MSDD_STATUS_ERROR; - } - else { - - // Change state - commandState->state = SBC_STATE_WAIT_WRITE; - } - break; - - //------------------------ - case SBC_STATE_WAIT_WRITE: - //------------------------ - // Check the transfer semaphore - if (transfer->semaphore > 0) { - - // Take semaphore and finish command - transfer->semaphore--; - - if (transfer->status != USBD_STATUS_SUCCESS) { - - result = MSDD_STATUS_ERROR; - } - else { - - result = MSDD_STATUS_SUCCESS; - } - - // Update length - commandState->length -= transfer->transferred; - } - break; - } - - return result; -} - -//------------------------------------------------------------------------------ -//! \brief Performs a MODE SENSE (6) command. -//! -//! This function operates asynchronously and must be called multiple -//! times to complete. A result code of MSDDriver_STATUS_INCOMPLETE -//! indicates that at least another call of the method is necessary. -//! \param lun Pointer to the LUN affected by the command -//! \param commandState Current state of the command -//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) -//! \see MSDLun -//! \see MSDCommandState -//------------------------------------------------------------------------------ -static unsigned char SBC_ModeSense6(MSDLun *lun, MSDCommandState *commandState) -{ - unsigned char result = MSDD_STATUS_INCOMPLETE; - unsigned char status; - MSDTransfer *transfer = &(commandState->transfer); - - if (!SBCLunIsReady(lun)) { - - TRACE_INFO("SBC_ModeSense6: Not Ready!\n\r"); - return MSDD_STATUS_RW; - } - - // Check if mode page is supported - if (((SBCCommand *) commandState->cbw.pCommand)->modeSense6.bPageCode - != SBC_PAGE_RETURN_ALL) { - - return MSDD_STATUS_PARAMETER; - } - - // Initialize command state if needed - if (commandState->state == 0) { - - commandState->state = SBC_STATE_WRITE; - } - - // Check current command state - switch (commandState->state) { - //------------------- - case SBC_STATE_WRITE: - //------------------- - // Start transfer - status = MSDD_Write((void *) &modeParameterHeader6, - commandState->length, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - - // Check operation result code - if (status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "SPC_ModeSense6: Cannot start data transfer\n\r"); - result = MSDD_STATUS_ERROR; - } - else { - - // Proceed to next state - commandState->state = SBC_STATE_WAIT_WRITE; - } - break; - - //------------------------ - case SBC_STATE_WAIT_WRITE: - //------------------------ - TRACE_INFO_WP("Wait "); - - // Check semaphore value - if (transfer->semaphore > 0) { - - // Take semaphore and terminate command - transfer->semaphore--; - - if (transfer->status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "SPC_ModeSense6: Data transfer failed\n\r"); - result = MSDD_STATUS_ERROR; - } - else { - - result = MSDD_STATUS_SUCCESS; - } - - // Update length field - commandState->length -= transfer->transferred; - - } - break; - } - - return result; -} - -//------------------------------------------------------------------------------ -//! \brief Performs a TEST UNIT READY COMMAND command. -//! \param lun Pointer to the LUN affected by the command -//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) -//! \see MSDLun -//------------------------------------------------------------------------------ -static unsigned char SBC_TestUnitReady(MSDLun *lun) -{ - unsigned char result = MSDD_STATUS_RW; - unsigned char senseKey = SBC_SENSE_KEY_NO_SENSE, - addSenseCode = 0, - addSenseCodeQual = 0; - Media *media = lun->media; - - // Check current media state - if (lun->status < LUN_CHANGED) { - - TRACE_INFO_WP("Ejc "); - senseKey = SBC_SENSE_KEY_NOT_READY; - addSenseCode = SBC_ASC_MEDIUM_NOT_PRESENT; - } - else if (lun->status == LUN_CHANGED) { - - TRACE_INFO_WP("Chg "); - senseKey = SBC_SENSE_KEY_UNIT_ATTENTION; - addSenseCode = SBC_ASC_NOT_READY_TO_READY_CHANGE; - lun->status = LUN_READY; - } - else { - - switch(media->state) { - //------------------- - case MED_STATE_READY: - //------------------- - // Nothing to do - TRACE_INFO_WP("Rdy "); - result = MSDD_STATUS_SUCCESS; - break; - - //------------------ - case MED_STATE_BUSY: - //------------------ - TRACE_INFO_WP("Bsy "); - senseKey = SBC_SENSE_KEY_NOT_READY; - break; - - //------ - default: - //------ - TRACE_INFO_WP("? "); - senseKey = SBC_SENSE_KEY_NOT_READY; - addSenseCode = SBC_ASC_MEDIUM_NOT_PRESENT; - break; - } - } - SBC_UpdateSenseData(&(lun->requestSenseData), - senseKey, - addSenseCode, - addSenseCodeQual); - - return result; -} - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -//------------------------------------------------------------------------------ -//! \brief Updates the sense data of a LUN with the given key and codes -//! \param requestSenseData Pointer to the sense data to update -//! \param senseKey Sense key -//! \param additionalSenseCode Additional sense code -//! \param additionalSenseCodeQualifier Additional sense code qualifier -//------------------------------------------------------------------------------ -void SBC_UpdateSenseData(SBCRequestSenseData *requestSenseData, - unsigned char senseKey, - unsigned char additionalSenseCode, - unsigned char additionalSenseCodeQualifier) -{ - requestSenseData->bSenseKey = senseKey; - requestSenseData->bAdditionalSenseCode = additionalSenseCode; - requestSenseData->bAdditionalSenseCodeQualifier - = additionalSenseCodeQualifier; -} - -//------------------------------------------------------------------------------ -//! \brief Return information about the transfer length and direction expected -//! by the device for a particular command. -//! \param command Pointer to a buffer holding the command to evaluate -//! \param length Expected length of the data transfer -//! \param type Expected direction of data transfer -//! \param lun Pointer to the LUN affected by the command -//------------------------------------------------------------------------------ -unsigned char SBC_GetCommandInformation(void *command, - unsigned int *length, - unsigned char *type, - MSDLun *lun) -{ - SBCCommand *sbcCommand = (SBCCommand *) command; - unsigned char isCommandSupported = 1; - Media *media = lun->media; - - // Identify command - switch (sbcCommand->bOperationCode) { - //--------------- - case SBC_INQUIRY: - //--------------- - (*type) = MSDD_DEVICE_TO_HOST; - - // Allocation length is stored in big-endian format - (*length) = WORDB(sbcCommand->inquiry.pAllocationLength); - break; - - //-------------------- - case SBC_MODE_SENSE_6: - //-------------------- - (*type) = MSDD_DEVICE_TO_HOST; - if (sbcCommand->modeSense6.bAllocationLength > - sizeof(SBCModeParameterHeader6)) { - - *length = sizeof(SBCModeParameterHeader6); - } - else { - - *length = sbcCommand->modeSense6.bAllocationLength; - } - break; - - //------------------------------------ - case SBC_PREVENT_ALLOW_MEDIUM_REMOVAL: - case 0x1B: - //------------------------------------ - (*type) = MSDD_NO_TRANSFER; - break; - - //--------------------- - case SBC_REQUEST_SENSE: - //--------------------- - (*type) = MSDD_DEVICE_TO_HOST; - (*length) = sbcCommand->requestSense.bAllocationLength; - break; - - //----------------------- - case SBC_TEST_UNIT_READY: - //----------------------- - (*type) = MSDD_NO_TRANSFER; - break; - - //--------------------- - case SBC_READ_CAPACITY_10: - //--------------------- - (*type) = MSDD_DEVICE_TO_HOST; - (*length) = sizeof(SBCReadCapacity10Data); - break; - - //--------------- - case SBC_READ_10: - //--------------- - (*type) = MSDD_DEVICE_TO_HOST; - (*length) = WORDB(sbcCommand->read10.pTransferLength) - * lun->blockSize * media->blockSize; - break; - - //---------------- - case SBC_WRITE_10: - //---------------- - (*type) = MSDD_HOST_TO_DEVICE; - (*length) = WORDB(sbcCommand->write10.pTransferLength) - * lun->blockSize * media->blockSize; - break; - - //----------------- - case SBC_VERIFY_10: - //----------------- - (*type) = MSDD_NO_TRANSFER; - break; - #if 0 - //--------------------- - case SBC_READ_FORMAT_CAPACITIES: - //--------------------- - (*type) = MSDD_DEVICE_TO_HOST; - (*length) = 1; - break; - #endif - //------ - default: - //------ - isCommandSupported = 0; - } - - // If length is 0, no transfer is expected - if ((*length) == 0) { - - (*type) = MSDD_NO_TRANSFER; - } - - return isCommandSupported; -} - -//------------------------------------------------------------------------------ -//! \brief Processes a SBC command by dispatching it to a subfunction. -//! \param lun Pointer to the affected LUN -//! \param commandState Pointer to the current command state -//! \return Operation result code -//------------------------------------------------------------------------------ -unsigned char SBC_ProcessCommand(MSDLun *lun, - MSDCommandState *commandState) -{ - unsigned char result = MSDD_STATUS_INCOMPLETE; - SBCCommand *command = (SBCCommand *) commandState->cbw.pCommand; - Media *media = lun->media; - - // Identify command - switch (command->bOperationCode) { - //--------------- - case SBC_READ_10: - //--------------- - TRACE_DEBUG_WP("Read(10) "); - - // Perform the Read10 command - result = SBC_Read10(lun, commandState); - break; - - //---------------- - case SBC_WRITE_10: - //---------------- - TRACE_DEBUG_WP("Write(10) "); - - // Perform the Write10 command - result = SBC_Write10(lun, commandState); - break; - - //--------------------- - case SBC_READ_CAPACITY_10: - //--------------------- - TRACE_INFO_WP("RdCapacity(10) "); - - // Perform the ReadCapacity command - result = SBC_ReadCapacity10(lun, commandState); - break; - - //--------------------- - case SBC_VERIFY_10: - //--------------------- - TRACE_INFO_WP("Verify(10) "); - - // Flush media - MED_Flush(media); - result = MSDD_STATUS_SUCCESS; - break; - - //--------------- - case SBC_INQUIRY: - //--------------- - TRACE_INFO_WP("Inquiry "); - - // Process Inquiry command - result = SBC_Inquiry(lun, commandState); - break; - - //-------------------- - case SBC_MODE_SENSE_6: - //-------------------- - TRACE_INFO_WP("ModeSense(6) "); - - // Process ModeSense6 command - result = SBC_ModeSense6(lun, commandState); - break; - - //----------------------- - case SBC_TEST_UNIT_READY: - //----------------------- - TRACE_INFO_WP("TstUnitRdy "); - - // Process TestUnitReady command - //MED_Flush(media); - result = SBC_TestUnitReady(lun); - break; - - //--------------------- - case SBC_REQUEST_SENSE: - //--------------------- - TRACE_INFO_WP("ReqSense "); - - // Perform the RequestSense command - result = SBC_RequestSense(lun, commandState); - break; - - //------------------------------------ - case SBC_PREVENT_ALLOW_MEDIUM_REMOVAL: - case 0x1B: - //------------------------------------ - TRACE_INFO_WP("PrevAllowRem "); - - // Check parameter - result = command->mediumRemoval.bPrevent ? - MSDD_STATUS_PARAMETER : MSDD_STATUS_SUCCESS; - result = MSDD_STATUS_SUCCESS; - break; - - #if 0 - //------------------------------------ - case SBC_READ_FORMAT_CAPACITIES: - //------------------------------------ - TRACE_INFO_WP("RdFmtCap "); - result = MSDD_STATUS_RW; - break; - /* TODO BSS Added if (!SBCLunIsReady(lun)) { - - result = MSDD_STATUS_RW; - break; - } */ - #endif - //------ - default: - //------ - result = MSDD_STATUS_PARAMETER; - } - - return result; -} diff --git a/radio/bootloader/usb/device/massstorage/SBCMethods.h b/radio/bootloader/usb/device/massstorage/SBCMethods.h deleted file mode 100644 index 7ba794e67..000000000 --- a/radio/bootloader/usb/device/massstorage/SBCMethods.h +++ /dev/null @@ -1,111 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// SCSI commands implementation. -/// -/// !Usage -/// -/// -# After a CBW is received from host, use SBC_GetCommandInformation to check -/// if the command is supported, and get the command length and type -/// information before processing it. -/// -# Then SBC_ProcessCommand can be used to handle a valid command, to -/// perform the command operations. -/// -# SBC_UpdateSenseData is used to update the sense data that will be sent -/// to host. -//------------------------------------------------------------------------------ - -#ifndef SBCMETHODS_H -#define SBCMETHODS_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "SBC.h" -// #include -#include "MSDDStateMachine.h" - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Command States" -/// This page lists the possible states of a SBC command. -/// -/// !States -/// - SBC_STATE_READ -/// - SBC_STATE_WAIT_READ -/// - SBC_STATE_WRITE -/// - SBC_STATE_WAIT_WRITE -/// - SBC_STATE_NEXT_BLOCK - -/// Start of reading bulk data -#define SBC_STATE_READ 0x01 -/// Waiting for the bulk data reading complete -#define SBC_STATE_WAIT_READ 0x02 -/// Read error state -#define SBC_STATE_READ_ERROR 0x03 -/// Start next read block -#define SBC_STATE_NEXT_READ 0x04 -/// Start writing bulk data to host -#define SBC_STATE_WRITE 0x05 -/// Waiting for the bulk data sending complete -#define SBC_STATE_WAIT_WRITE 0x06 -/// Write error state -#define SBC_STATE_WRITE_ERROR 0x07 -/// Start next write block -#define SBC_STATE_NEXT_WRITE 0x08 -/// Start next command block -#define SBC_STATE_NEXT_BLOCK 0x09 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -void SBC_UpdateSenseData(SBCRequestSenseData *requestSenseData, - unsigned char senseKey, - unsigned char additionalSenseCode, - unsigned char additionalSenseCodeQualifier); - -unsigned char SBC_GetCommandInformation(void *command, - unsigned int *length, - unsigned char *type, - MSDLun *lun); - -unsigned char SBC_ProcessCommand(MSDLun *lun, - MSDCommandState *commandState); - -#endif //#ifndef SBCMETHODS_H - From 7853aebf3d659b38bd8fa0e6dc4a7aa21c4f09ba Mon Sep 17 00:00:00 2001 From: bsongis Date: Tue, 4 Mar 2014 12:03:34 +0100 Subject: [PATCH 017/285] 1 more file removed --- radio/bootloader/Makefile | 43 +-- radio/bootloader/startup_stm32f2xx.s | 512 --------------------------- 2 files changed, 1 insertion(+), 554 deletions(-) delete mode 100644 radio/bootloader/startup_stm32f2xx.s diff --git a/radio/bootloader/Makefile b/radio/bootloader/Makefile index 6c6944ed2..e0de909ff 100644 --- a/radio/bootloader/Makefile +++ b/radio/bootloader/Makefile @@ -144,47 +144,7 @@ CPPSRC = ../src/targets/taranis/aspi.cpp \ boot.cpp # List ASM source files here -ASRC = startup_stm32f2xx.s - -else - - -ifeq ($(PCB), X9D) -SRC = system_stm32f2xx.c \ - stm32f2xx_rcc.c \ - stm32f2xx_gpio.c \ - stm32f2xx_spi.c \ - misc.c \ - usb/usb_core.c \ - usb/usb_dcd.c \ - usb/usb_dcd_int.c \ - usb/usbd_core.c \ - usb/usbd_ioreq.c \ - usb/usbd_req.c \ - usb/usbd_msc_data.c \ - usb/usbd_msc_scsi.c \ - usb/usbd_msc_bot.c \ - usb/usbd_msc_core.c \ - usb/usbd_desc.c \ - usb/usb_bsp.c - -CPPSRC = lcdboot.cpp \ - ff.cpp \ - aspi.cpp \ - x9ddiskio.cpp \ - lcd_driver.cpp \ - i2c_ee.cpp \ - driversboot.cpp \ - logicioboot.cpp \ - ff_lfn.cpp \ - usbd_usr.cpp \ - usbd_storage_msd.cpp \ - power.cpp \ - boot.cpp - - -# List ASM source files here -ASRC = x9d/startup_stm32f2xx.s +ASRC = ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc_ride7/startup_stm32f2xx.s else @@ -217,7 +177,6 @@ CPPSRC = lcdboot.cpp \ # List ASM source files here ASRC = -endif endif # List all user directories here diff --git a/radio/bootloader/startup_stm32f2xx.s b/radio/bootloader/startup_stm32f2xx.s deleted file mode 100644 index 320550516..000000000 --- a/radio/bootloader/startup_stm32f2xx.s +++ /dev/null @@ -1,512 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f2xx.s - * @author MCD Application Team - * @version V1.1.3 - * @date 05-March-2012 - * @brief STM32F2xx Devices vector table for RIDE7 toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the system clock and the external SRAM mounted on - * STM322xG-EVAL board to be used as data memory (optional, - * to be enabled by user) - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word CAN1_TX_IRQHandler /* CAN1 TX */ - .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SCE_IRQHandler /* CAN1 SCE */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ - .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM4_IRQHandler /* TIM4 */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ - .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ - .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ - .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ - .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word FSMC_IRQHandler /* FSMC */ - .word SDIO_IRQHandler /* SDIO */ - .word TIM5_IRQHandler /* TIM5 */ - .word SPI3_IRQHandler /* SPI3 */ - .word UART4_IRQHandler /* UART4 */ - .word UART5_IRQHandler /* UART5 */ - .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ - .word TIM7_IRQHandler /* TIM7 */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word ETH_IRQHandler /* Ethernet */ - .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ - .word CAN2_TX_IRQHandler /* CAN2 TX */ - .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ - .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ - .word CAN2_SCE_IRQHandler /* CAN2 SCE */ - .word OTG_FS_IRQHandler /* USB OTG FS */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EV_IRQHandler /* I2C3 event */ - .word I2C3_ER_IRQHandler /* I2C3 error */ - .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ - .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ - .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ - .word OTG_HS_IRQHandler /* USB OTG HS */ - .word DCMI_IRQHandler /* DCMI */ - .word CRYP_IRQHandler /* CRYP crypto */ - .word HASH_RNG_IRQHandler /* Hash and Rng */ - - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM10_IRQHandler - .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM8_BRK_TIM12_IRQHandler - .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler - - .weak TIM8_UP_TIM13_IRQHandler - .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_TIM14_IRQHandler - .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak FSMC_IRQHandler - .thumb_set FSMC_IRQHandler,Default_Handler - - .weak SDIO_IRQHandler - .thumb_set SDIO_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak ETH_IRQHandler - .thumb_set ETH_IRQHandler,Default_Handler - - .weak ETH_WKUP_IRQHandler - .thumb_set ETH_WKUP_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler,Default_Handler - - .weak CAN2_SCE_IRQHandler - .thumb_set CAN2_SCE_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_OUT_IRQHandler - .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_IN_IRQHandler - .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler - - .weak OTG_HS_WKUP_IRQHandler - .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler - - .weak OTG_HS_IRQHandler - .thumb_set OTG_HS_IRQHandler,Default_Handler - - .weak DCMI_IRQHandler - .thumb_set DCMI_IRQHandler,Default_Handler - - .weak CRYP_IRQHandler - .thumb_set CRYP_IRQHandler,Default_Handler - - .weak HASH_RNG_IRQHandler - .thumb_set HASH_RNG_IRQHandler,Default_Handler - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ From ae54f4908a5028f89f1ee4f86921fc6f1056e48e Mon Sep 17 00:00:00 2001 From: bsongis Date: Tue, 4 Mar 2014 12:07:43 +0100 Subject: [PATCH 018/285] More Sky9x bootloader files removed --- radio/bootloader/MEDSdcard.c | 558 -- radio/bootloader/board_lowlevel.c | 273 - radio/bootloader/bootsamEeprom.cpp | 604 --- radio/bootloader/core_cm3.c | 880 --- radio/bootloader/crt.c | 147 - radio/bootloader/diskio.cpp | 1195 ----- radio/bootloader/include/AT91SAM3S4.h | 7102 ------------------------- radio/bootloader/sam3s4c_boot.ld | 144 - radio/bootloader/sam3s8c_boot.ld | 144 - radio/bootloader/vectors_sam3s.c | 198 - 10 files changed, 11245 deletions(-) delete mode 100644 radio/bootloader/MEDSdcard.c delete mode 100644 radio/bootloader/board_lowlevel.c delete mode 100644 radio/bootloader/bootsamEeprom.cpp delete mode 100644 radio/bootloader/core_cm3.c delete mode 100644 radio/bootloader/crt.c delete mode 100644 radio/bootloader/diskio.cpp delete mode 100644 radio/bootloader/include/AT91SAM3S4.h delete mode 100644 radio/bootloader/sam3s4c_boot.ld delete mode 100644 radio/bootloader/sam3s8c_boot.ld delete mode 100644 radio/bootloader/vectors_sam3s.c diff --git a/radio/bootloader/MEDSdcard.c b/radio/bootloader/MEDSdcard.c deleted file mode 100644 index e030b5571..000000000 --- a/radio/bootloader/MEDSdcard.c +++ /dev/null @@ -1,558 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include -#include "Media.h" -#include "debug.h" -#include "board.h" -#include "diskio.h" - -//------------------------------------------------------------------------------ -// Constants -//------------------------------------------------------------------------------ - -/// Number of SD Slots -#define NUM_SD_SLOTS 1 -#define SD_BLOCK_SIZE 512 - -//------------------------------------------------------------------------------ -/// Checks if the device is write protected. -/// \return 1 if protected. -//------------------------------------------------------------------------------ -#if 0 -static unsigned char CardIsProtected(unsigned char slot) -{ - if (slot == 0) { - #ifdef BOARD_SD_PIN_WP - PIO_Configure(&pinMciWriteProtect, 1); - return (PIO_Get(&pinMciWriteProtect) != 0); - #else - return 0; - #endif - } - - if (slot == 1) { - #ifdef BOARD_SD_MCI1_PIN_WP - PIO_Configure(&pinMciWriteProtect1, 1); - return (PIO_Get(&pinMciWriteProtect1) != 0); - #else - return 0; - #endif - } - - return 0; -} -#endif - -//------------------------------------------------------------------------------ -/// Configure the PIO for SD -//------------------------------------------------------------------------------ -#if 0 -static void ConfigurePIO(unsigned char mciID) -{ - #ifdef BOARD_SD_PINS - const Pin pinSd0[] = {BOARD_SD_PINS}; - #endif - - #ifdef BOARD_SD_MCI1_PINS - const Pin pinSd1[] = {BOARD_SD_MCI1_PINS}; - #endif - - if(mciID == 0) { - #ifdef BOARD_SD_PINS - PIO_Configure(pinSd0, PIO_LISTSIZE(pinSd0)); - #endif - } else { - #ifdef BOARD_SD_MCI1_PINS - PIO_Configure(pinSd1, PIO_LISTSIZE(pinSd1)); - #endif - } -} -#endif - -//------------------------------------------------------------------------------ -//! \brief Reads a specified amount of data from a SDCARD memory -//! \param media Pointer to a Media instance -//! \param address Address of the data to read -//! \param data Pointer to the buffer in which to store the retrieved -//! data -//! \param length Length of the buffer -//! \param callback Optional pointer to a callback function to invoke when -//! the operation is finished -//! \param argument Optional pointer to an argument for the callback -//! \return Operation result code -//------------------------------------------------------------------------------ -static unsigned char MEDSdcard_Read(Media *media, - unsigned int address, - void *data, - unsigned int length, - MediaCallback callback, - void *argument) -{ - TRACE_DEBUG("MEDSdcard_Read(address=%d length=%d)\n\r", address, length); - - // Check that the media is ready - if (media->state != MED_STATE_READY) { - - TRACE_INFO("Media busy\n\r"); - return MED_STATUS_BUSY; - } - - // Check that the data to read is not too big - if ((length + address) > media->size) { - - TRACE_WARNING("MEDSdcard_Read: Data too big: %d, %d\n\r", - (int)length, (int)address); - return MED_STATUS_ERROR; - } - - // Enter Busy state - media->state = MED_STATE_BUSY; - - disk_read (0, data, address, length); - - // Leave the Busy state - media->state = MED_STATE_READY; - - // Invoke callback - if (callback != 0) { - - callback(argument, MED_STATUS_SUCCESS, 0, 0); - } - - return MED_STATUS_SUCCESS; -} - -static unsigned char Eeprom_Read(Media *media, - unsigned int address, - void *data, - unsigned int length, - MediaCallback callback, - void *argument) -{ - if (media->state != MED_STATE_READY) { - - TRACE_INFO("Media busy\n\r"); - return MED_STATUS_BUSY; - } - // Check that the data to read is not too big - if ((length + address) > media->size) { - - TRACE_WARNING("Eeprom_Read: Data too big: %d, %d\n\r", - (int)length, (int)address); - return MED_STATUS_ERROR; - } - - // Enter Busy state - media->state = MED_STATE_BUSY; - - disk_read (1, data, address, length); - - // Leave the Busy state - media->state = MED_STATE_READY; - - // Invoke callback - if (callback != 0) { - - callback(argument, MED_STATUS_SUCCESS, 0, 0); - } - - return MED_STATUS_SUCCESS; - -} -//------------------------------------------------------------------------------ -//! \brief Writes data on a SDRAM media -//! \param media Pointer to a Media instance -//! \param address Address at which to write -//! \param data Pointer to the data to write -//! \param length Size of the data buffer -//! \param callback Optional pointer to a callback function to invoke when -//! the write operation terminates -//! \param argument Optional argument for the callback function -//! \return Operation result code -//! \see Media -//! \see MediaCallback -//------------------------------------------------------------------------------ -static unsigned char MEDSdcard_Write(Media *media, - unsigned int address, - void *data, - unsigned int length, - MediaCallback callback, - void *argument) -{ - - TRACE_DEBUG("MEDSdcard_Write(address=%d length=%d)\n\r", address, length); - - // Check that the media if ready - if (media->state != MED_STATE_READY) { - - TRACE_WARNING("MEDSdcard_Write: Media is busy\n\r"); - return MED_STATUS_BUSY; - } - - // Check that the data to write is not too big - if ((length + address) > media->size) { - - TRACE_WARNING("MEDSdcard_Write: Data too big\n\r"); - return MED_STATUS_ERROR; - } - - // Put the media in Busy state - media->state = MED_STATE_BUSY; - - disk_write(0, data, address, length); - - // Leave the Busy state - media->state = MED_STATE_READY; - - // Invoke the callback if it exists - if (callback != 0) { - - callback(argument, MED_STATUS_SUCCESS, 0, 0); - } - - return MED_STATUS_SUCCESS; -} - -static unsigned char Eeprom_Write(Media *media, - unsigned int address, - void *data, - unsigned int length, - MediaCallback callback, - void *argument) -{ - - TRACE_DEBUG("Eeprom_Write(address=%d length=%d)\n\r", address, length); - - // Check that the media if ready - if (media->state != MED_STATE_READY) { - - TRACE_WARNING("Eeprom_Write: Media is busy\n\r"); - return MED_STATUS_BUSY; - } - - // Check that the data to write is not too big - if ((length + address) > media->size) { - - TRACE_WARNING("Eeprom_Write: Data too big\n\r"); - return MED_STATUS_ERROR; - } - - // Put the media in Busy state - media->state = MED_STATE_BUSY; - - disk_write(1, data, address, length); - - // Leave the Busy state - media->state = MED_STATE_READY; - - // Invoke the callback if it exists - if (callback != 0) { - - callback(argument, MED_STATUS_SUCCESS, 0, 0); - } - - return MED_STATUS_SUCCESS; -} - -//------------------------------------------------------------------------------ -/// Initializes a Media instance and the associated physical interface -/// \param media Pointer to the Media instance to initialize -/// \return 1 if success. -//------------------------------------------------------------------------------ - -unsigned char MEDSdcard_Initialize(Media *media, unsigned char mciID) -{ - TRACE_INFO("MEDSdcard init\n\r"); - - // Initialize SDcard - //-------------------------------------------------------------------------- - - if ( !CardIsConnected( ) ) - { - return 0; - } - - // Configure SDcard pins - // ConfigurePIO(mciID); - -#if defined(MCI2_INTERFACE) - // DMAD_Initialize(BOARD_MCI_DMA_CHANNEL, DMAD_NO_DEFAULT_IT); -#endif - -#if 0 - // Initialize the MCI driver - if ( mciID == 0 ) - { - IRQ_ConfigureIT(BOARD_SD_MCI_ID, 1, MCI0_IrqHandler); - MCI_Init(mciDrv, BOARD_SD_MCI_BASE, BOARD_SD_MCI_ID, BOARD_SD_SLOT, BOARD_MCK ); - IRQ_EnableIT(BOARD_SD_MCI_ID); - } - else - { - #ifdef BOARD_SD_MCI1_ID - IRQ_ConfigureIT(BOARD_SD_MCI1_ID, 1, MCI0_IrqHandler); - MCI_Init(mciDrv, BOARD_SD_MCI1_BASE, BOARD_SD_MCI1_ID, BOARD_SD_MCI1_SLOT, BOARD_MCK ); - IRQ_EnableIT(BOARD_SD_MCI1_ID); - #else - TRACE_ERROR("SD/MMC card initialization failed (MCI1 not supported)\n\r"); - #endif - } -#if MCI_BUSY_CHECK_FIX && defined(BOARD_SD_DAT0) - MCI_SetBusyFix(mciDrv, &pinSdDAT0); -#endif - - // Initialize the SD card driver - if (SD_Init(sdDrv, (SdDriver *)mciDrv)) - { - TRACE_ERROR("SD/MMC card initialization failed\n\r"); - return 0; - } - else - { - //SD_DisplayRegisterCSD(&sdDrv); - TRACE_INFO("SD/MMC card initialization successful\n\r"); - TRACE_INFO("Card size: %d MB\n\r", (int)(MMC_GetTotalSizeKB(sdDrv)/1024)); - } - MCI_SetSpeed(mciDrv, sdDrv->transSpeed, sdDrv->transSpeed, BOARD_MCK); -#endif - - - media->write = MEDSdcard_Write; - media->read = MEDSdcard_Read; - media->lock = 0; - media->unlock = 0; - media->handler = 0; - media->flush = 0; - - media->blockSize = SD_BLOCK_SIZE; - media->baseAddress = 0; - - media->size = SD_GET_BLOCKNR(); - - media->mappedRD = 0; - media->mappedWR = 0; - media->protected = 0; // TODO BSS CardIsProtected(mciID); - media->removable = 1; - - media->state = MED_STATE_READY; - - media->transfer.data = 0; - media->transfer.address = 0; - media->transfer.length = 0; - media->transfer.callback = 0; - media->transfer.argument = 0; - - return 1; -} - -unsigned char EEPROM_Initialize(Media *media, unsigned char mciID) -{ - media->write = Eeprom_Write; - media->read = Eeprom_Read; - media->lock = 0; - media->unlock = 0; - media->handler = 0; - media->flush = 0; - - media->blockSize = 512 ; - media->baseAddress = 0; - -#ifdef REVX - media->size = 2051 ; -#else - media->size = 1539 ; -#endif - - media->mappedRD = 0; - media->mappedWR = 0; - media->protected = 0; // TODO BSS CardIsProtected(mciID); - media->removable = 1; - - media->state = MED_STATE_READY; - - media->transfer.data = 0; - media->transfer.address = 0; - media->transfer.length = 0; - media->transfer.callback = 0; - media->transfer.argument = 0; - - return 1; - -} - -#if 0 -//------------------------------------------------------------------------------ -/// Initializes a Media instance and the associated physical interface -/// \param media Pointer to the Media instance to initialize -/// \return 1 if success. -//------------------------------------------------------------------------------ -unsigned char MEDSdusb_Initialize(Media *media, unsigned char mciID) -{ - TRACE_INFO("MEDSdusb init\n\r"); - - // Initialize SDcard - //-------------------------------------------------------------------------- - - if (!CardIsConnected()) return 0; -#if 0 - // Configure SDcard pins - ConfigurePIO(mciID); - -#if defined(MCI2_INTERFACE) - DMAD_Initialize(BOARD_MCI_DMA_CHANNEL, DMAD_NO_DEFAULT_IT); -#endif - // Initialize the MCI driver - if ( mciID == 0 ) - { - IRQ_ConfigureIT(BOARD_SD_MCI_ID, 1, MCI0_IrqHandler); - MCI_Init(mciDrv, BOARD_SD_MCI_BASE, BOARD_SD_MCI_ID, BOARD_SD_SLOT, BOARD_MCK ); - IRQ_EnableIT(BOARD_SD_MCI_ID); - } - else - { -#ifdef BOARD_SD_MCI1_ID - IRQ_ConfigureIT(BOARD_SD_MCI1_ID, 1, MCI0_IrqHandler); - MCI_Init(mciDrv, BOARD_SD_MCI1_BASE, BOARD_SD_MCI1_ID, BOARD_SD_SLOT, BOARD_MCK ); - IRQ_EnableIT(BOARD_SD_MCI1_ID); -#else - TRACE_ERROR("SD/MMC card initialization failed (MCI1 not supported)\n\r"); -#endif - } -#if MCI_BUSY_CHECK_FIX && defined(BOARD_SD_DAT0) - MCI_SetBusyFix(mciDrv, &pinSdDAT0); -#endif - - // Initialize the SD card driver - if (SD_Init(sdDrv, (SdDriver *)mciDrv)) - { - TRACE_ERROR("SD/MMC card initialization failed\n\r"); - return 0; - } - else - { - TRACE_INFO("SD/MMC card initialization successful\n\r"); - TRACE_INFO("Card size: %d MB\n\r", (int)(MMC_GetTotalSizeKB(sdDrv)/1024)); - } - MCI_SetSpeed(mciDrv, sdDrv->transSpeed, sdDrv->transSpeed, BOARD_MCK); -#endif - // Initialize media fields - //-------------------------------------------------------------------------- - //media->interface = sdDrv; - media->write = MEDSdusb_Write; - media->read = MEDSdusb_Read; - media->lock = 0; - media->unlock = 0; - media->handler = 0; - media->flush = 0; - - media->blockSize = SD_BLOCK_SIZE; - media->baseAddress = 0; - media->size = 1024*1024; // TODO BSS SD_TOTAL_BLOCK(sdDrv); - - media->mappedRD = 0; - media->mappedWR = 0; - media->protectedd = false; // TODO BSS CardIsProtected(mciID); - media->removable = 1; - - media->state = MED_STATE_READY; - - media->transfer.data = 0; - media->transfer.address = 0; - media->transfer.length = 0; - media->transfer.callback = 0; - media->transfer.argument = 0; - - return 1; -} -#endif - -#if 0 -//------------------------------------------------------------------------------ -/// erase all the Sdcard -/// \param media Pointer to the Media instance to initialize -//------------------------------------------------------------------------------ -void MEDSdcard_EraseAll(Media *media) -{ - unsigned char buffer[SD_BLOCK_SIZE]; - unsigned int block; - unsigned int multiBlock = 1; // change buffer size for multiblocks - unsigned char error; - - TRACE_INFO("MEDSdcard Erase All ...\n\r"); - - // Clear the block buffer - memset(buffer, 0, media->blockSize * multiBlock); - - for (block=0; - block < (SD_TOTAL_BLOCK((SdCard*)media->interface)-multiBlock); - block += multiBlock) - { - // TODO BSS error = SD_WriteBlock((SdCard*)media->interface, block, multiBlock, buffer); - assert( !error ); /* "\n\r-F- Failed to write block (%d) #%u\n\r", error, block */ - } -} -#endif - -//------------------------------------------------------------------------------ -/// erase block -/// \param media Pointer to the Media instance to initialize -/// \param block to erase -//------------------------------------------------------------------------------ -#if 0 -void MEDSdcard_EraseBlock(Media *media, unsigned int block) -{ - unsigned char buffer[SD_BLOCK_SIZE]; - unsigned char error; - - // Clear the block buffer - memset(buffer, 0, media->blockSize); - - // TODO BSS error = SD_WriteBlock((SdCard*)media->interface, block, 1, buffer); - assert( !error ) ; /* "\n\r-F- Failed to write block (%d) #%u\n\r", error, block */ -} -#endif -//------------------------------------------------------------------------------ -/// Get driver pointer -//------------------------------------------------------------------------------ -#if 0 -SdCard* MEDSdcard_GetDriver( unsigned int slot ) -{ - if (slot >= NUM_SD_SLOTS) - { - return 0; - } - - return &sdDrv[slot]; -} -#endif diff --git a/radio/bootloader/board_lowlevel.c b/radio/bootloader/board_lowlevel.c deleted file mode 100644 index 8bb63be1f..000000000 --- a/radio/bootloader/board_lowlevel.c +++ /dev/null @@ -1,273 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * \par Purpose - * - * Provides the low-level initialization function that gets called on chip startup. - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "board.h" - -/*---------------------------------------------------------------------------- - * Local definitions - *----------------------------------------------------------------------------*/ -/** Define clock timeout */ -#define CLOCK_TIMEOUT 5000 -/** Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.*/ -#define PMC_PLLA_SET_BIT29 (0x1 << 29) -/** Specifies the number of Slow Clock cycles x8 before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.*/ -#define PMC_PLLA_COUNT (0xBF << 8) -/** The PLLA Clock frequency is the PLLA input frequency multiplied by 8*/ -#define PMC_PLLA_MULTIPIER (0x07 << 16) -/** PLLA Divider is bypassed.*/ -#define PMC_PLLA_DIV (0x01) - -void revert_osc( void ) ; - - -/*---------------------------------------------------------------------------- - * Local functions - * returns master_frequency - *----------------------------------------------------------------------------*/ - -// *** WARNING, this is called BEFORE .data and .bss have been initialised -// *** GLOBAL variables are NOT useable - -static uint32_t BOARD_ConfigurePmc(void) -{ -/* TODO: configurate PLL in new way */ -//#if 0 -// uint32_t timeout = 0; -// /** 1: Checking the Main Oscillator Frequency (Optional) and Initialize main oscillator */ -// /** 1.1 Initialize main oscillator */ -// // TODO: - -// /** 2. Setting PLL and Divider*/ -// /** 2.1 Initialize PLLA*/ -// PMC->CKGR_PLLAR = ( PMC_PLLA_SET_BIT29 | -// PMC_PLLA_MULTIPIER | -// PMC_PLLA_COUNT | -// PMC_PLLA_DIV -// ); -// timeout = 0; -// /** 2.2 Wait for the LOCKA bit to be set by polling the status register.*/ -// while (!(PMC->PMC_SR & PMC_SR_LOCKA) && (timeout++ < CLOCK_TIMEOUT)); -// /** 2.3 wait for the MCKRDY bit to be set by polling the status register*/ -// timeout = 0; -// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); - -// /** 3. Selection of Master Clock and Processor Clock*/ -// PMC->PMC_MCKR |= PMC_MCKR_PRES_CLK_2; - -// /** 3.1 wait for the MCKRDY bit to be set by polling the status register*/ -// timeout = 0; -// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); - -// /** 3.2 PLLA Clock is selected */ -// PMC->PMC_MCKR = PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK; - -// /** 3.3 wait for the MCKRDY bit to be set by polling the status register*/ -// timeout = 0; -// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); -//#endif - -#if 1 // old as sam3u -#define AT91C_CKGR_MUL_SHIFT 16 -//#define AT91C_CKGR_OUT_SHIFT 14 -#define AT91C_CKGR_PLLCOUNT_SHIFT 8 -#define AT91C_CKGR_DIV_SHIFT 0 - -// Settings at 72MHz/2 = 36MHz -#define BOARD_OSCOUNT (CKGR_MOR_MOSCXTST & (0x8 << 8)) -#define BOARD_PLLR ((1 << 29) | (0x5 << AT91C_CKGR_MUL_SHIFT) \ - | (0x1 << AT91C_CKGR_PLLCOUNT_SHIFT) | (0x2 << AT91C_CKGR_DIV_SHIFT)) -#define BOARD_MCKR (PMC_MCKR_CSS_PLLA_CLK) - -// Define clock timeout -#undef CLOCK_TIMEOUT -#define CLOCK_TIMEOUT 0xFFFFFFFF - - register uint32_t timeout = 0 ; - register Pmc *pmcptr ; - - pmcptr = PMC ; - - /* Enable NRST reset - ************************************/ - //AT91C_BASE_RSTC->RSTC_RMR |= AT91C_RSTC_URSTEN; - - /* Select external slow clock - ****************************/ - - -// if ((SUPC->SUPC_SR & SUPC_SR_OSCSEL) != SUPC_SR_OSCSEL_CRYST) { -// SUPC->SUPC_CR = SUPC_CR_XTALSEL_CRYSTAL_SEL | ((uint32_t)0xA5 << 24); -// timeout = 0; -// while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL_CRYST) ); -// } - - - /* Initialize main oscillator - ****************************/ - if(!(pmcptr->CKGR_MOR & CKGR_MOR_MOSCSEL)) - { - - pmcptr->CKGR_MOR = (0x37 << 16) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN; - timeout = 0; - while (!(pmcptr->PMC_SR & PMC_SR_MOSCXTS) && (++timeout < CLOCK_TIMEOUT)); - - } - - /* Switch to 3-20MHz Xtal oscillator */ - pmcptr->CKGR_MOR = (0x37 << 16) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL; - timeout = 0; - while (!(pmcptr->PMC_SR & PMC_SR_MOSCSELS) && (++timeout < CLOCK_TIMEOUT)); - - pmcptr->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS) | PMC_MCKR_CSS_MAIN_CLK; - timeout = 0; - while (!(pmcptr->PMC_SR & PMC_SR_MCKRDY) && (++timeout < CLOCK_TIMEOUT)); - - /* Initialize PLLA 72 MHz */ - pmcptr->CKGR_PLLAR = BOARD_PLLR; - timeout = 0; - while (!(pmcptr->PMC_SR & PMC_SR_LOCKA) && (++timeout < CLOCK_TIMEOUT)); - - - /* Initialize UTMI for USB usage, can be disabled if not using USB for the sake of saving power*/ - //AT91C_BASE_CKGR->CKGR_UCKR |= (AT91C_CKGR_UPLLCOUNT & (3 << 20)) | AT91C_CKGR_UPLLEN; - //timeout = 0; - //while (!(PMC->PMC_SR & AT91C_PMC_LOCKU) && (timeout++ < CLOCK_TIMEOUT)); - - /* Switch to fast clock - **********************/ -// PMC->PMC_MCKR = (BOARD_MCKR & ~PMC_MCKR_CSS) | PMC_MCKR_CSS_MAIN_CLK; -// timeout = 0; -// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); - - // Switch to PLLA as main clock 36MHz - PMC->PMC_MCKR = BOARD_MCKR; - timeout = 0; - while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); - -#endif - return 36000000L ; // Master_frequency -} - -#ifndef BOOT -void revert_osc() -{ - register uint32_t timeout = 0 ; - register Pmc *pmcptr ; - - pmcptr = PMC ; - - - // Switch back to the internal oscillator - pmcptr->CKGR_MOR = (0x37 << 16) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN ; - timeout = 0; - while (!(pmcptr->PMC_SR & PMC_SR_MOSCSELS) && (++timeout < CLOCK_TIMEOUT)); - - pmcptr->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS) | PMC_MCKR_CSS_SLOW_CLK; - timeout = 0; - while (!(pmcptr->PMC_SR & PMC_SR_MCKRDY) && (++timeout < CLOCK_TIMEOUT)); - - - pmcptr->CKGR_PLLAR = 1 << 29 ; // Stop PLLA - -} -#endif - -#ifdef BOOT - -extern void sam_bootx( void ) ; -extern void dispUSB( void ) ; -extern uint32_t initReadTrims( void ) ; -extern void run_application( void ) ; - -static void lowLevelUsbCheck( void ) -{ - PMC->PMC_PCER0 = (1<PIO_PER = PIO_PC25 ; // Enable bit C25 (USB-detect) - - uint32_t i ; - for ( i = 0 ; i < 50 ; i += 1 ) - { - __asm("nop") ; - } - - for ( i = 0 ; i < 10 ; i += 1 ) - { - if ( PIOC->PIO_PDSR & 0x02000000 ) - { - PMC->PMC_PCDR0 = (1<EEFC_FMR = (1 << 8) ; - - /** Configure PMC */ - return BOARD_ConfigurePmc(); -} - - diff --git a/radio/bootloader/bootsamEeprom.cpp b/radio/bootloader/bootsamEeprom.cpp deleted file mode 100644 index a3803793d..000000000 --- a/radio/bootloader/bootsamEeprom.cpp +++ /dev/null @@ -1,604 +0,0 @@ -/**************************************************************************** -* Copyright (c) 2014 by Michael Blandford. All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* 1. Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* 3. Neither the name of the author nor the names of its contributors may -* be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL -* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -* SUCH DAMAGE. -* -**************************************************************************** -* Other Authors: - * - Andre Bernet - * - Bertrand Songis - * - Bryan J. Rentoul (Gruvin) - * - Cameron Weeks - * - Erez Raviv - * - Jean-Pierre Parisy - * - Karl Szmutny - * - Michal Hlavinka - * - Pat Mackenzie - * - Philip Moss - * - Rob Thomson - * - Romolo Manfredini - * - Thomas Husterer -* -****************************************************************************/ - - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include -#include -#include -#include "AT91SAM3S4.h" - - -uint8_t Eblock_buffer[4096] ; -uint8_t Eblock_current[4096] ; // For erased checking -int32_t EblockAddress ; - -uint8_t Spi_tx_buf[24] ; -uint8_t Spi_rx_buf[24] ; -uint32_t Spi_init_done = 0 ; - -uint32_t EepromBlocked = 1 ; -extern uint8_t EE_timer ; - -// Test for EEPROM file -uint32_t isEepromStart( uint8_t *p ) -{ - uint32_t csum ; - uint32_t size = 7 ; - - csum = 0 ; - while( size ) - { - csum += *p++ ; - size -= 1 ; - } - if ( csum == *p ) - { - return 1 ; - } - return 0 ; -} - - -uint32_t eeprom_write_one( uint8_t byte, uint8_t count ) ; -uint32_t eeprom_read_status( void ) ; -void eeprom_write_enable( void ) ; -void eeprom_wait_busy( void ) ; -uint32_t spi_operation( register uint8_t *tx, register uint8_t *rx, register uint32_t count ) ; -void init_spi( void ) ; -uint32_t unprotect_eeprom( void ) ; -uint32_t spi_PDC_action( register uint8_t *command, register uint8_t *tx, register uint8_t *rx, register uint32_t comlen, register uint32_t count ) ; -void AT25D_Read( uint8_t *BufferAddr, uint32_t size, uint32_t memoryOffset) ; -void AT25D_Write( uint8_t *BufferAddr, uint32_t size, uint32_t memoryOffset ) ; -uint32_t AT25D_EraseBlock( uint32_t memoryOffset ) ; -void writeBlock( void ) ; - - -uint32_t eeprom_write_one( uint8_t byte, uint8_t count ) -{ - register Spi *spiptr ; - register uint32_t result ; - - spiptr = SPI ; - spiptr->SPI_CR = 1 ; // Enable - (void) spiptr->SPI_RDR ; // Dump any rx data - - spiptr->SPI_TDR = byte ; - - result = 0 ; - while( ( spiptr->SPI_SR & SPI_SR_RDRF ) == 0 ) - { - // wait for received - if ( ++result > 10000 ) - { - break ; - } - } - if ( count == 0 ) - { - spiptr->SPI_CR = 2 ; // Disable - return spiptr->SPI_RDR ; - } - (void) spiptr->SPI_RDR ; // Dump the rx data - spiptr->SPI_TDR = 0 ; - result = 0 ; - while( ( spiptr->SPI_SR & SPI_SR_RDRF ) == 0 ) - { - // wait for received - if ( ++result > 10000 ) - { - break ; - } - } - spiptr->SPI_CR = 2 ; // Disable - return spiptr->SPI_RDR ; -} - - -uint32_t eeprom_read_status() -{ - return eeprom_write_one( 5, 1 ) ; -} - - -void eeprom_write_enable() -{ - eeprom_write_one( 6, 0 ) ; -} - -void eeprom_wait_busy() -{ - register uint32_t x ; - register uint32_t y ; - - y = 0 ; - do - { - y += 1 ; - if ( y > 1000000 ) - { - break ; - } - x = eeprom_read_status() ; - } while ( x & 1 ) ; - -} - -uint32_t spi_operation( register uint8_t *tx, register uint8_t *rx, register uint32_t count ) -{ - register Spi *spiptr ; - register uint32_t result ; - -// PMC->PMC_PCER0 |= 0x00200000L ; // Enable peripheral clock to SPI - - result = 0 ; - spiptr = SPI ; - spiptr->SPI_CR = 1 ; // Enable - (void) spiptr->SPI_RDR ; // Dump any rx data - while( count ) - { - result = 0 ; - while( ( spiptr->SPI_SR & SPI_SR_TXEMPTY ) == 0 ) - { - // wait - if ( ++result > 10000 ) - { - result = 0xFFFF ; - break ; - } - } - if ( result > 10000 ) - { - break ; - } -// if ( count == 1 ) -// { -// spiptr->SPI_CR = SPI_CR_LASTXFER ; // LastXfer bit -// } - spiptr->SPI_TDR = *tx++ ; - result = 0 ; - while( ( spiptr->SPI_SR & SPI_SR_RDRF ) == 0 ) - { - // wait for received - if ( ++result > 10000 ) - { - result = 0x2FFFF ; - break ; - } - } - if ( result > 10000 ) - { - break ; - } - *rx++ = spiptr->SPI_RDR ; - count -= 1 ; - } - if ( result <= 10000 ) - { - result = 0 ; - } - spiptr->SPI_CR = 2 ; // Disable - -// Power save -// PMC->PMC_PCER0 &= ~0x00200000L ; // Disable peripheral clock to SPI - - return result ; -} - -uint32_t spi_PDC_action( register uint8_t *command, register uint8_t *tx, register uint8_t *rx, register uint32_t comlen, register uint32_t count ) -{ - register Spi *spiptr ; -// register uint32_t result ; - register uint32_t condition ; - static uint8_t discard_rx_command[4] ; - -// PMC->PMC_PCER0 |= 0x00200000L ; // Enable peripheral clock to SPI - -// Spi_complete = 0 ; - if ( comlen > 4 ) - { -// Spi_complete = 1 ; - return 0x4FFFF ; - } - condition = SPI_SR_TXEMPTY ; - spiptr = SPI ; - spiptr->SPI_CR = 1 ; // Enable - (void) spiptr->SPI_RDR ; // Dump any rx data - (void) spiptr->SPI_SR ; // Clear error flags - spiptr->SPI_RPR = (uint32_t)discard_rx_command ; - spiptr->SPI_RCR = comlen ; - if ( rx ) - { - spiptr->SPI_RNPR = (uint32_t)rx ; - spiptr->SPI_RNCR = count ; - condition = SPI_SR_RXBUFF ; - } - spiptr->SPI_TPR = (uint32_t)command ; - spiptr->SPI_TCR = comlen ; - if ( tx ) - { - spiptr->SPI_TNPR = (uint32_t)tx ; - } - else - { - spiptr->SPI_TNPR = (uint32_t)rx ; - } - spiptr->SPI_TNCR = count ; - - spiptr->SPI_PTCR = SPI_PTCR_RXTEN | SPI_PTCR_TXTEN ; // Start transfers - - // Wait for things to get started, avoids early interrupt - for ( count = 0 ; count < 1000 ; count += 1 ) - { - if ( ( spiptr->SPI_SR & SPI_SR_TXEMPTY ) == 0 ) - { - break ; - } - } - - count = 0 ; - while( ( spiptr->SPI_SR & condition ) == 0 ) - { - if ( ++count > 1000000 ) - { - break ; - } - } - - spiptr->SPI_CR = 2 ; // Disable - (void) spiptr->SPI_RDR ; // Dump any rx data - (void) spiptr->SPI_SR ; // Clear error flags - spiptr->SPI_PTCR = SPI_PTCR_RXTDIS | SPI_PTCR_TXTDIS ; // Stop tramsfers - - if ( count > 1000000 ) - { - return 1 ; - } - return 0 ; -} - - -uint32_t unprotect_eeprom() -{ - register uint8_t *p ; - - eeprom_write_enable() ; - - p = Spi_tx_buf ; - *p = 0x39 ; // Unprotect sector command - *(p+1) = 0 ; - *(p+2) = 0 ; - *(p+3) = 0 ; // 3 bytes address - - return spi_operation( p, Spi_rx_buf, 4 ) ; -} - - - - - - -void init_spi() -{ - register Pio *pioptr ; - register Spi *spiptr ; - register uint32_t timer ; - register uint8_t *p ; - uint8_t spi_buf[4] ; - - if ( !Spi_init_done) - { - PMC->PMC_PCER0 |= 0x00200000L ; // Enable peripheral clock to SPI - /* Configure PIO */ - pioptr = PIOA ; - pioptr->PIO_ABCDSR[0] &= ~0x00007800 ; // Peripheral A bits 14,13,12,11 - pioptr->PIO_ABCDSR[1] &= ~0x00007800 ; // Peripheral A - pioptr->PIO_PDR = 0x00007800 ; // Assign to peripheral - - spiptr = SPI ; - timer = ( 64000000 / 3000000 ) << 8 ; - spiptr->SPI_MR = 0x14000011 ; // 0001 0100 0000 0000 0000 0000 0001 0001 Master - spiptr->SPI_CSR[0] = 0x01180009 | timer ; // 0000 0001 0001 1000 xxxx xxxx 0000 1001 - // NVIC_EnableIRQ(SPI_IRQn) ; - - p = spi_buf ; - - // *p = 0x39 ; // Unprotect sector command - // *(p+1) = 0 ; - // *(p+2) = 0 ; - // *(p+3) = 0 ; // 3 bytes address - - // spi_operation( p, spi_buf, 4 ) ; - - eeprom_write_enable() ; - - *p = 1 ; // Write status register command - *(p+1) = 0 ; - spi_operation( p, spi_buf, 2 ) ; - Spi_init_done = 1 ; - } - -} - - -void AT25D_Read( uint8_t *BufferAddr, uint32_t size, uint32_t memoryOffset) -{ - register uint8_t *p ; - - p = Spi_tx_buf ; - *p = 3 ; // Read command - *(p+1) = memoryOffset >> 16 ; - *(p+2) = memoryOffset >> 8 ; - *(p+3) = memoryOffset ; // 3 bytes address - - spi_PDC_action( p, 0, BufferAddr, 4, size ) ; -} - - -uint32_t ee32_read_512( uint32_t sector, uint8_t *buffer ) -{ - AT25D_Read( buffer, 512, sector * 512 ) ; - return 1 ; -} - -void AT25D_Write( uint8_t *BufferAddr, uint32_t size, uint32_t memoryOffset ) -{ - register uint8_t *p ; - - eeprom_write_enable() ; - - p = Spi_tx_buf ; - *p = 2 ; // Write command - *(p+1) = memoryOffset >> 16 ; - *(p+2) = memoryOffset >> 8 ; - *(p+3) = memoryOffset ; // 3 bytes address - - spi_PDC_action( p, BufferAddr, 0, 4, size ) ; - - eeprom_wait_busy() ; - -} - -uint32_t eeprom_block_erased( register uint8_t *p) -{ - register uint32_t x ; - register uint32_t result ; - - result = 1 ; - - for ( x = 0 ; x < 4096 ; x += 1 ) - { - if ( *p++ != 0xFF ) - { - result = 0 ; - break ; - } - } - return result ; -} - -uint32_t eeprom_page_erased( register uint8_t *p) -{ - register uint32_t x ; - register uint32_t result ; - - result = 1 ; - - for ( x = 0 ; x < 256 ; x += 1 ) - { - if ( *p++ != 0xFF ) - { - result = 0 ; - break ; - } - } - return result ; -} - -void writeBlock() -{ - uint32_t x ; - uint32_t address ; - uint32_t i ; - uint8_t *s ; - - x = eeprom_block_erased( Eblock_current ) ; // EEPROM block blanked? - if ( x == 0 ) - { - AT25D_EraseBlock( EblockAddress ) ; - memset( Eblock_current, 0xFF, 4096 ) ; // Now erased - } - - s = Eblock_buffer ; - address = EblockAddress ; - for ( i = 0 ; i < 16 ; i += 1 ) // pages in block - { - x = eeprom_page_erased( s ) ; - if ( x == 0 ) // Not blank - { -//EeWriteCount += 1 ; - AT25D_Write( s, 256, address ) ; - } - s += 256 ; - address += 256 ; - } - EblockAddress = -1 ; - EE_timer = 0 ; -} - - -void readBlock( uint32_t block_address ) -{ - AT25D_Read( Eblock_buffer, 4096, block_address ) ; // read block to write to - memcpy( Eblock_current, Eblock_buffer, 4096 ) ; // Copy for erase checking - - EblockAddress = block_address ; -} - -uint32_t ee32_write( const uint8_t *buffer, uint32_t sector, uint32_t count ) -{ - // EEPROM write - uint32_t startMemoryOffset ; - uint32_t memoryOffset ; - uint32_t bytesToWrite ; - uint8_t *pBuffer ; - int32_t block_address ; - - if ( sector == 0 ) - { - if ( isEepromStart( (uint8_t *) buffer ) ) - { - EepromBlocked = 0 ; - } - else - { - EepromBlocked = 1 ; - } - } - - if ( EepromBlocked ) - { - return 1 ; - } - - startMemoryOffset = sector ; - startMemoryOffset *= 512 ; // Byte address into EEPROM - memoryOffset = startMemoryOffset; - - bytesToWrite = count * 512 ; - - unprotect_eeprom() ; - - pBuffer = (uint8_t *) buffer ; - - block_address = memoryOffset &0xFFFFF000 ; // 4k boundary - - if ( EblockAddress != -1 ) - { - // Ram copy is dirty - if ( EblockAddress != block_address ) - { - // flush buffer - writeBlock() ; - } - } - - // Now check for pre-read - if ( EblockAddress != block_address ) - { - readBlock( block_address ) ; - -// // Check to see if it is blank -// x = eeprom_block_erased( Eblock_buffer ) ; -// if ( x == 0 ) -// { -// AT25D_EraseBlock( block_address ) ; -// } - } - - while (bytesToWrite) - { - uint32_t bytes_to_copy ; - uint32_t i ; - uint8_t *s ; - uint8_t *dest ; - - if ( EblockAddress != block_address ) - { - readBlock( block_address ) ; - } - - dest = Eblock_buffer + (memoryOffset & 0x0FFF ) ; - s = pBuffer ; - bytes_to_copy = 4096 - ( memoryOffset - block_address ) ; - if ( bytes_to_copy > bytesToWrite ) - { - bytes_to_copy = bytesToWrite ; - } - for ( i = 0 ; i < bytes_to_copy ; i += 1 ) - { - *dest++ = *s++ ; - } - memoryOffset += bytes_to_copy ; - bytesToWrite -= bytes_to_copy ; - - if ( dest > &Eblock_buffer[4095] ) - { - // copied data past end - writeBlock() ; - } - else - { - EE_timer = 30 ; // Write dirty block in 0.3 secs - } - } - return 1 ; -} - -uint32_t AT25D_EraseBlock( uint32_t memoryOffset ) -{ - register uint8_t *p ; - register uint32_t x ; - -// EeEraseCount += 1 ; - - eeprom_write_enable() ; - p = Spi_tx_buf ; - *p = 0x20 ; // Block Erase command - *(p+1) = memoryOffset >> 16 ; - *(p+2) = memoryOffset >> 8 ; - *(p+3) = memoryOffset ; // 3 bytes address - x = spi_operation( p, Spi_rx_buf, 4 ) ; - - eeprom_wait_busy() ; - return x ; -} - - diff --git a/radio/bootloader/core_cm3.c b/radio/bootloader/core_cm3.c deleted file mode 100644 index 6f4106433..000000000 --- a/radio/bootloader/core_cm3.c +++ /dev/null @@ -1,880 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.c - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File - * @version V1.30 - * @date 30. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#include - -/* define compiler specific symbols */ -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - -uint32_t __get_PSP(void) ; -void __set_PSP(uint32_t topOfProcStack) ; -uint32_t __get_MSP(void) ; -void __set_MSP(uint32_t mainStackPointer) ; -uint32_t __REV16(uint16_t value) ; -int32_t __REVSH(int16_t value) ; -uint32_t __RBIT(uint32_t value) ; -uint8_t __LDREXB(uint8_t *addr) ; -uint16_t __LDREXH(uint16_t *addr) ; -uint32_t __LDREXW(uint32_t *addr) ; -uint32_t __STREXB(uint8_t value, uint8_t *addr) ; -uint32_t __STREXH(uint16_t value, uint16_t *addr) ; -uint32_t __STREXW(uint32_t value, uint32_t *addr) ; - -uint32_t __get_BASEPRI(void) ; -void __set_BASEPRI(uint32_t basePri) ; -uint32_t __get_PRIMASK(void) ; -void __set_PRIMASK(uint32_t priMask) ; -uint32_t __get_FAULTMASK(void) ; -void __set_FAULTMASK(uint32_t faultMask) ; -uint32_t __get_CONTROL(void) ; -void __set_CONTROL(uint32_t control) ; -uint32_t __REV(uint32_t value) ; - -void revert_osc( void ) ; -void sam_boot( void ) ; -void sam_bootx( void ) ; -void run_application( void ) ; - - -/* ################### Compiler specific Intrinsics ########################### */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -__ASM uint32_t __get_PSP(void) -{ - mrs r0, psp - bx lr -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -__ASM void __set_PSP(uint32_t topOfProcStack) -{ - msr psp, r0 - bx lr -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -__ASM uint32_t __get_MSP(void) -{ - mrs r0, msp - bx lr -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -__ASM void __set_MSP(uint32_t mainStackPointer) -{ - msr msp, r0 - bx lr -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -__ASM uint32_t __REV16(uint16_t value) -{ - rev16 r0, r0 - bx lr -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -__ASM int32_t __REVSH(int16_t value) -{ - revsh r0, r0 - bx lr -} - - -#if (__ARMCC_VERSION < 400000) - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -__ASM void __CLREX(void) -{ - clrex -} - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -__ASM uint32_t __get_BASEPRI(void) -{ - mrs r0, basepri - bx lr -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -__ASM void __set_BASEPRI(uint32_t basePri) -{ - msr basepri, r0 - bx lr -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -__ASM uint32_t __get_PRIMASK(void) -{ - mrs r0, primask - bx lr -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -__ASM void __set_PRIMASK(uint32_t priMask) -{ - msr primask, r0 - bx lr -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -__ASM uint32_t __get_FAULTMASK(void) -{ - mrs r0, faultmask - bx lr -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -__ASM void __set_FAULTMASK(uint32_t faultMask) -{ - msr faultmask, r0 - bx lr -} - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -__ASM uint32_t __get_CONTROL(void) -{ - mrs r0, control - bx lr -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -__ASM void __set_CONTROL(uint32_t control) -{ - msr control, r0 - bx lr -} - -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#pragma diag_suppress=Pe940 - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -uint32_t __get_PSP(void) -{ - __ASM("mrs r0, psp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM("msr psp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -uint32_t __get_MSP(void) -{ - __ASM("mrs r0, msp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM("msr msp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - __ASM("rev16 r0, r0"); - __ASM("bx lr"); -} - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -uint32_t __RBIT(uint32_t value) -{ - __ASM("rbit r0, r0"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit values) - */ -uint8_t __LDREXB(uint8_t *addr) -{ - __ASM("ldrexb r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -uint16_t __LDREXH(uint16_t *addr) -{ - __ASM("ldrexh r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -uint32_t __LDREXW(uint32_t *addr) -{ - __ASM("ldrex r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - __ASM("strexb r0, r0, [r1]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - __ASM("strexh r0, r0, [r1]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - __ASM("strex r0, r0, [r1]"); - __ASM("bx lr"); -} - -#pragma diag_default=Pe940 - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -#ifndef BOOT -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -/*extern uint32_t __get_PSP(void) __attribute__( ( naked ) ); */ -uint32_t __get_PSP(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, psp\n\t" - "MOV r0, %0 \n\t" - "BX lr \n\t" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -/*void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); */ -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n\t" - "BX lr \n\t" : : "r" (topOfProcStack) ); -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -/*uint32_t __get_MSP(void) __attribute__( ( naked ) ); */ -uint32_t __get_MSP(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, msp\n\t" - "MOV r0, %0 \n\t" - "BX lr \n\t" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -/*void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); */ -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n\t" - "BX lr \n\t" : : "r" (topOfMainStack) ); -} - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -uint32_t __get_BASEPRI(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -uint32_t __get_PRIMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -uint32_t __get_FAULTMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -uint32_t __get_CONTROL(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - -#endif - -/** - * @brief Reverse byte order in integer value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -uint32_t __REV(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#ifndef BOOT -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -int32_t __REVSH(int16_t value) -{ - uint32_t result=0; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -uint32_t __RBIT(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit value - */ -uint8_t __LDREXB(uint8_t *addr) -{ - uint8_t result=0; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -uint16_t __LDREXH(uint16_t *addr) -{ - uint16_t result=0; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -uint32_t __LDREXW(uint32_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} -#endif - -#ifdef BOOT -void run_application() -{ - __ASM(" mov.w r1, #4227072"); // 0x408000 - __ASM(" movw r0, #60680"); // 0xED08 - __ASM(" movt r0, #57344"); // 0xE000 - __ASM(" str r1, [r0, #0]"); // Set the VTOR - -// __ASM("mov.w r3, #0"); // 0x0000 -// __ASM("movt r3, #128"); // 0x0080 - __ASM("ldr r0, [r1, #0]"); // Stack pointer value - __ASM("msr msp, r0"); // Set it - __ASM("ldr r0, [r1, #4]"); // Reset address - __ASM("mov.w r1, #1"); - __ASM("orr r0, r1"); // Set lsbit - __ASM("bx r0"); // Execute application -} - -#endif - -#ifndef BOOT - -void sam_boot() -{ - revert_osc() ; - - __ASM(" mov.w r1, #8388608"); - __ASM(" movw r0, #60680"); - __ASM(" movt r0, #57344"); - __ASM(" str r1, [r0, #0]"); // Set the VTOR - - __ASM("mov.w r3, #0"); - __ASM("movt r3, #128"); - __ASM("ldr r0, [r3, #0]"); - __ASM("msr msp, r0"); - __ASM("ldr r0, [r3, #4]"); - __ASM("mov.w r3, #1"); - __ASM("orr r0, r3"); - __ASM("bx r0"); -} -#endif - -#ifdef BOOT - -void sam_bootx() -{ - __ASM(" mov.w r1, #8388608"); - __ASM(" movw r0, #60680"); - __ASM(" movt r0, #57344"); - __ASM(" str r1, [r0, #0]"); // Set the VTOR - - __ASM("mov.w r3, #0"); - __ASM("movt r3, #128"); - __ASM("ldr r0, [r3, #0]"); - __ASM("msr msp, r0"); - __ASM("ldr r0, [r3, #4]"); - __ASM("mov.w r3, #1"); - __ASM("orr r0, r3"); - __ASM("bx r0"); -} - -#endif - - -#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif diff --git a/radio/bootloader/crt.c b/radio/bootloader/crt.c deleted file mode 100644 index 158c5a27a..000000000 --- a/radio/bootloader/crt.c +++ /dev/null @@ -1,147 +0,0 @@ -/**************************************************************************** -* Copyright (c) 2011 by Michael Fischer. All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* 1. Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* 3. Neither the name of the author nor the names of its contributors may -* be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL -* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -* SUCH DAMAGE. -* -**************************************************************************** -* History: -* -* 09.04.2011 mifi First Version -* 29.04.2011 mifi Call SystemInit, and set the Vector Table Offset -* before copy of data and bss segment. -****************************************************************************/ -#define __CRT_C__ - -#include - -/*=========================================================================*/ -/* DEFINE: All extern Data */ -/*=========================================================================*/ -/* - * The next data are defined by the linker script. - */ -extern unsigned long _stext; -extern unsigned long _etext; -extern unsigned long _sdata; -extern unsigned long _edata; -extern unsigned long _sbss; -extern unsigned long _ebss; -extern unsigned long _estack; - -/* This is the main */ -extern int main (void); - -/*=========================================================================*/ -/* DEFINE: Prototypes */ -/*=========================================================================*/ -extern uint32_t SystemInit (void) ; // __attribute__((weak)); - -/*=========================================================================*/ -/* DEFINE: All code exported */ -/*=========================================================================*/ - -/***************************************************************************/ -/* SystemInit */ -/* */ -/* SystemInit is a function which is provided by the CMSIS interface. */ -/* If this function is not available, we need a function here to prevent */ -/* an error of the linker. Therefore this function is declared as weak. */ -/***************************************************************************/ -//uint32_t SystemInit (void) -//{ - -//} /* SystemInit */ - -extern uint32_t Master_frequency ; - -/***************************************************************************/ -/* ResetHandler */ -/* */ -/* This function is used for the C runtime initialisation, */ -/* for handling the .data and .bss segments. */ -/***************************************************************************/ -void ResetHandler (void) -{ - { - register uint32_t *pSrc; - register uint32_t *pDest; - register uint32_t m_freq ; - - /* - * Call the SystemInit code from CMSIS interface if available. - * SystemInit is a week function which can be override - * by an external function. - */ - m_freq = SystemInit(); - - /* - * Set the "Vector Table Offset Register". From the ARM - * documentation, we got the following information: - * - * Use the Vector Table Offset Register to determine: - * - if the vector table is in RAM or code memory - * - the vector table offset. - */ - *((uint32_t*)0xE000ED08) = (uint32_t)&_stext; - - /* - * Copy the initialized data of the ".data" segment - * from the flash to the are in the ram. - */ - pSrc = &_etext; - pDest = &_sdata; - while(pDest < &_edata) - { - *pDest++ = *pSrc++; - } - - /* - * Clear the ".bss" segment. - */ - pDest = &_sbss; - while(pDest < &_ebss) - { - *pDest++ = 0; - } - Master_frequency = m_freq ; - } - - /* - * And now the main function can be called. - * Scotty, energie... - */ - main(); - - /* - * In case there are problems with the - * "warp drive", stop here. - */ - while(1) {}; - -} /* ResetHandler */ - -/*** EOF ***/ diff --git a/radio/bootloader/diskio.cpp b/radio/bootloader/diskio.cpp deleted file mode 100644 index 2db16ad0b..000000000 --- a/radio/bootloader/diskio.cpp +++ /dev/null @@ -1,1195 +0,0 @@ -/* - * Authors (alphabetical order) - * - Bertrand Songis - * - Bryan J. Rentoul (Gruvin) - * - Cameron Weeks - * - Erez Raviv - * - Jean-Pierre Parisy - * - Karl Szmutny - * - Michael Blandford - * - Michal Hlavinka - * - Pat Mackenzie - * - Philip Moss - * - Rob Thomson - * - Romolo Manfredini - * - Thomas Husterer - * - * open9x is based on code named - * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, - * er9x by Erez Raviv: http://code.google.com/p/er9x/, - * and the original (and ongoing) project by - * Thomas Husterer, th9x: http://code.google.com/p/th9x/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/*-----------------------------------------------------------------------*/ -/* MMCv3/SDv1/SDv2 (in SPI mode) control module (C)ChaN, 2010 */ -/*-----------------------------------------------------------------------*/ -/* Only rcvr_spi(), xmit_spi(), disk_timerproc() and some macros */ -/* are platform dependent. */ -/*-----------------------------------------------------------------------*/ - -#include "radio.h" -//extern unsigned long Master_frequency ; -extern void delay2ms() ; -#ifdef BOOT -#define TRUE 1 -#endif - - -#ifndef BOOT -//#if !defined(SIMU) -//#include "CoOS.h" -//#endif -#endif - -#include "diskio.h" -#include "board.h" -#ifndef BOOT -#include "debug.h" -#endif -// States for initialising card -#define SD_ST_EMPTY 0 -#define SD_ST_INIT1 1 -#define SD_ST_INIT2 2 -#define SD_ST_IDLE 3 -#define SD_ST_READY 4 -#define SD_ST_IDENT 5 -#define SD_ST_STBY 6 -#define SD_ST_TRAN 7 -#define SD_ST_DATA 8 - -// Bits in status register of Sd card -#define STATUS_READY_FOR_DATA (1UL << 8) -#define STATUS_TRAN (4UL << 9) -#define STATUS_STATE (0xFUL << 9) - - - -uint32_t Card_ID[4] ; -uint32_t Card_SCR[2] ; -uint32_t Card_CSD[4] ; -uint32_t Card_state = SD_ST_EMPTY ; -uint32_t Sd_128_resp[4] ; -uint32_t Sd_rca ; -uint32_t Sd_status13 ; -uint32_t Cmd_A41_resp ; -uint32_t SpeedAllowed ; - -uint32_t Sd_retries ; - -/** - * Configure the MCI SDCBUS in the MCI_SDCR register. Only two modes available - * - * \param busWidth MCI bus width mode. 00: 1-bit, 10: 4-bit. - */ -uint32_t SD_SetBusWidth( uint32_t busWidth) -{ - uint32_t mciSdcr; - - if( (busWidth != HSMCI_SDCR_SDCBUS_1) && (busWidth != HSMCI_SDCR_SDCBUS_4) ) - { - return (uint32_t)-1; - } - - busWidth &= HSMCI_SDCR_SDCBUS_Msk ; - - mciSdcr = (HSMCI->HSMCI_SDCR & ~(uint32_t)(HSMCI_SDCR_SDCBUS_Msk)); - HSMCI->HSMCI_SDCR = mciSdcr | busWidth; - - return 0; -} - -#if 0 -/** - * Configure the MCI_CFG to enable the HS mode - * \param hsEnable 1 to enable, 0 to disable HS mode. - */ -void SD_EnableHsMode( uint8_t hsEnable) -{ - uint32_t cfgr; - - cfgr = HSMCI->HSMCI_CFG; - if (hsEnable) - { - cfgr |= HSMCI_CFG_HSMODE; - } - else - { - cfgr &= ~(uint32_t)HSMCI_CFG_HSMODE; - } - - HSMCI->HSMCI_CFG = cfgr; -} -#endif - -/** - * Configure the MCI CLKDIV in the MCI_MR register. The max. for MCI clock is - * MCK/2 and corresponds to CLKDIV = 0 - * \param mciSpeed MCI clock speed in Hz, 0 will not change current speed. - * \return The actual speed used, 0 for fail. - */ -uint32_t SD_SetSpeed( uint32_t mciSpeed ) -{ - uint32_t mciMr; - uint32_t clkdiv, divLimit; - - mciMr = HSMCI->HSMCI_MR & (~(uint32_t)HSMCI_MR_CLKDIV_Msk); - /* Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK) - * divided by (2*(CLKDIV+1)) - * mciSpeed = MCK / (2*(CLKDIV+1)) */ - if (mciSpeed > 0) - { - - divLimit = (Master_frequency / 2 / mciSpeed); - if ((Master_frequency / 2) % mciSpeed) divLimit ++; - - clkdiv = (Master_frequency / 2 / mciSpeed); - if (mciSpeed && clkdiv < divLimit) - clkdiv = divLimit; - if (clkdiv > 0) - clkdiv -= 1; - -// clkdiv = (Master_frequency / 2 / mciSpeed); -// /* Speed should not bigger than expired one */ -// if (mciSpeed < Master_frequency/2/clkdiv) -// { -// clkdiv++; -// } - -// if ( clkdiv > 0 ) -// { -// clkdiv -= 1; -// } - } - else - { - clkdiv = 0 ; - } - - /* Actual MCI speed */ - mciSpeed = Master_frequency / 2 / (clkdiv + 1); - /* Modify MR */ - HSMCI->HSMCI_MR = mciMr | clkdiv; - - return (mciSpeed); -} - -#if 0 -void SD_SetBlklen( uint32_t blklen ) -{ - uint32_t mciMr; - uint32_t clkdiv; - - mciMr = HSMCI->HSMCI_MR & (~(uint32_t)HSMCI_MR_BLKLEN); - /* Modify MR */ - HSMCI->HSMCI_MR = mciMr | blklen << 16 ; -} -#endif - -#if 0 -/** - * Reset MCI HW interface and disable it. - * \param keepSettings Keep old register settings, including - * _MR, _SDCR, _DTOR, _CSTOR, _DMA and _CFG. - */ -void SD_Reset( uint8_t keepSettings) -{ - Hsmci *pMciHw = HSMCI ; - - if (keepSettings) - { - uint32_t mr, sdcr, dtor, cstor; - uint32_t cfg; - mr = pMciHw->HSMCI_MR; - sdcr = pMciHw->HSMCI_SDCR; - dtor = pMciHw->HSMCI_DTOR; - cstor = pMciHw->HSMCI_CSTOR; - cfg = pMciHw->HSMCI_CFG; - pMciHw->HSMCI_CR = HSMCI_CR_SWRST ; // Reset - pMciHw->HSMCI_CR = HSMCI_CR_MCIDIS; // Disable - pMciHw->HSMCI_MR = mr; - pMciHw->HSMCI_SDCR = sdcr; - pMciHw->HSMCI_DTOR = dtor; - pMciHw->HSMCI_CSTOR = cstor; - pMciHw->HSMCI_CFG = cfg; - } - else - { - pMciHw->HSMCI_CR = HSMCI_CR_SWRST ; // Reset - pMciHw->HSMCI_CR = HSMCI_CR_MCIDIS; // Disable - } -} -#endif - - -uint32_t sdCommand(uint32_t cmd, uint32_t arg) -{ - uint32_t i; - Hsmci *phsmci = HSMCI; - - if (CardIsConnected()) - { - phsmci->HSMCI_ARGR = arg; - phsmci->HSMCI_CMDR = cmd; - - for (i = 0; i < 50000; i += 1) - { - if (phsmci->HSMCI_SR & HSMCI_SR_CMDRDY) - { - return 0; - } - } - return 1 ; // No response - } - else - { - return 1 ; // No Sdcard - } -} - - -#define SDMMC_APP_CMD (55| HSMCI_CMDR_SPCMD_STD \ - | HSMCI_CMDR_RSPTYP_48_BIT \ - | HSMCI_CMDR_TRCMD_NO_DATA \ - | HSMCI_CMDR_MAXLAT) - -uint32_t sd_cmd55() -{ - return sdCommand( SDMMC_APP_CMD, Sd_rca ) ; -} - -#define SDMMC_GO_IDLE_STATE (0 | HSMCI_CMDR_TRCMD_NO_DATA \ - | HSMCI_CMDR_SPCMD_STD ) - -// returns 0 = OK, non-zero = fail -uint32_t sd_cmd0() -{ - return sdCommand( SDMMC_GO_IDLE_STATE, 0 ) ; -} -#define SD_SEND_IF_COND (8 | HSMCI_CMDR_TRCMD_NO_DATA \ - | HSMCI_CMDR_SPCMD_STD \ - | HSMCI_CMDR_RSPTYP_48_BIT \ - | HSMCI_CMDR_OPDCMD /* BSS difference */ \ - | HSMCI_CMDR_MAXLAT ) - -#define SDMMC_SEND_STATUS_CMD (13 | HSMCI_CMDR_TRCMD_NO_DATA \ - | HSMCI_CMDR_SPCMD_STD \ - | HSMCI_CMDR_RSPTYP_48_BIT \ - | HSMCI_CMDR_MAXLAT ) - -// returns 0 = OK, non-zero = fail -uint32_t sd_cmd13(uint32_t *status) -{ - uint32_t result = sdCommand( SDMMC_SEND_STATUS_CMD, Sd_rca ) ; - if (result) - return result; - Sd_status13 = *status = HSMCI->HSMCI_RSPR[0]; - return 0 ; -} - -// returns 0 = OK, non-zero = fail -uint32_t sd_cmd8() -{ - return sdCommand( SD_SEND_IF_COND, 0X000001AA ) ; -} - -uint32_t sd_acmd41() -{ - uint32_t i; - Hsmci *phsmci = HSMCI; - - if (CardIsConnected()) { - sd_cmd55(); - phsmci->HSMCI_ARGR = 0x403F8000; - phsmci->HSMCI_CMDR = 0x00001069; - - for (i = 0; i < 30000; i += 1) { - if (phsmci->HSMCI_SR & HSMCI_SR_CMDRDY) { - break; - } - } - return Cmd_A41_resp = phsmci->HSMCI_RSPR[0] ; - } - else { - return 0; - } -} - -// Get Card ID -// returns 0 = OK, non-zero = fail -uint32_t sd_cmd2() -{ - uint32_t result = sdCommand( 0x00001082, 0 ) ; - if (result) - return result; - - Hsmci *phsmci = HSMCI ; - Card_ID[0] = phsmci->HSMCI_RSPR[0] ; - Card_ID[1] = phsmci->HSMCI_RSPR[1] ; - Card_ID[2] = phsmci->HSMCI_RSPR[2] ; - Card_ID[3] = phsmci->HSMCI_RSPR[3] ; - return 0 ; -} - -// Get new RCA -// returns 0 = OK, non-zero = fail -uint32_t sd_cmd3() -{ - uint32_t result = sdCommand( 0x00001043, 0 ) ; - if (result) - return result; - - Sd_rca = HSMCI->HSMCI_RSPR[0]; - return 0 ; -} - -// Get CSD -uint32_t sd_cmd9() -{ - uint32_t result = sdCommand( 0x00001089, Sd_rca ) ; - if (result) - return result; - - Hsmci *phsmci = HSMCI ; - - Card_CSD[0] = phsmci->HSMCI_RSPR[0] ; - Card_CSD[1] = phsmci->HSMCI_RSPR[1] ; - Card_CSD[2] = phsmci->HSMCI_RSPR[2] ; - Card_CSD[3] = phsmci->HSMCI_RSPR[3] ; - return 0 ; -} - -/** Cmd7 MCI, ac, R1/R1b */ -#define SDMMC_SELECT_CARD (7 | HSMCI_CMDR_TRCMD_NO_DATA \ - | HSMCI_CMDR_SPCMD_STD \ - | HSMCI_CMDR_RSPTYP_R1B \ - | HSMCI_CMDR_MAXLAT /* TODO not the same */ ) - -// Select Card -uint32_t sd_cmd7() -{ - return sdCommand( SDMMC_SELECT_CARD, Sd_rca ) ; -} - -#define SD_SEND_SCR (51 | HSMCI_CMDR_SPCMD_STD | HSMCI_CMDR_RSPTYP_48_BIT \ - | HSMCI_CMDR_TRCMD_START_DATA | HSMCI_CMDR_TRDIR_READ \ - | HSMCI_CMDR_TRTYP_SINGLE | HSMCI_CMDR_MAXLAT) - -#define SDMMC_SET_BLOCKLEN (16 | HSMCI_CMDR_TRCMD_NO_DATA \ - | HSMCI_CMDR_SPCMD_STD \ - | HSMCI_CMDR_RSPTYP_48_BIT \ - | HSMCI_CMDR_MAXLAT_64 ) - -#define SD_READ_SINGLE_BLOCK (17 | HSMCI_CMDR_SPCMD_STD | HSMCI_CMDR_RSPTYP_48_BIT \ - | HSMCI_CMDR_TRCMD_START_DATA | HSMCI_CMDR_TRDIR_READ \ - | HSMCI_CMDR_TRTYP_SINGLE | HSMCI_CMDR_MAXLAT) - -#define SD_WRITE_SINGLE_BLOCK (24 | HSMCI_CMDR_SPCMD_STD \ - | HSMCI_CMDR_RSPTYP_48_BIT \ - | HSMCI_CMDR_TRCMD_START_DATA \ - | HSMCI_CMDR_TRDIR_WRITE \ - | HSMCI_CMDR_TRTYP_SINGLE \ - | HSMCI_CMDR_MAXLAT) - -// Get SCR -uint32_t sd_acmd51( uint32_t *presult ) -{ - uint32_t i ; - uint32_t j = 0 ; - Hsmci *phsmci = HSMCI ; - - if ( CardIsConnected() ) - { - sd_cmd55() ; - // Block size = 64/ 8, nblocks = 1 - phsmci->HSMCI_BLKR = ( ( 64 / 8 ) << 16 ) | 1 ; - phsmci->HSMCI_ARGR = 0 ; - phsmci->HSMCI_CMDR = SD_SEND_SCR ; - - for ( i = 0 ; i < 50000 ; i += 1 ) - { - if ( phsmci->HSMCI_SR & HSMCI_SR_RXRDY ) - { - *presult++ = __REV(phsmci->HSMCI_RDR) ; - j += 0x10000000 ; - } - if ( ( phsmci->HSMCI_SR & ( HSMCI_SR_CMDRDY | HSMCI_SR_XFRDONE ) ) == ( HSMCI_SR_CMDRDY | HSMCI_SR_XFRDONE ) ) - { - break ; - } - - } - if ( i >= 50000 ) - { - *presult = phsmci->HSMCI_SR ; - } - return i | j ; //phsmci->HSMCI_RSPR[0] ; - } - else - { - return 0 ; - } -} - -#define SD_SET_BUS_WIDTH (6 | HSMCI_CMDR_SPCMD_STD | HSMCI_CMDR_RSPTYP_48_BIT \ - | HSMCI_CMDR_MAXLAT) - -// Set bus width to 4 bits, set speed to 9 MHz -uint32_t sd_acmd6() -{ - uint32_t i ; - Hsmci *phsmci = HSMCI ; - - if ( CardIsConnected() ) - { - sd_cmd55() ; - phsmci->HSMCI_ARGR = 2 ; // Bus width 4 bits - phsmci->HSMCI_CMDR = SD_SET_BUS_WIDTH ; - - for ( i = 0 ; i < 300000 ; i += 1 ) - { - if ( phsmci->HSMCI_SR & HSMCI_SR_CMDRDY ) - { - break ; - } - } - if ( i >= 300000 ) - { - return 0 ; - } - SD_SetBusWidth( HSMCI_SDCR_SDCBUS_4 ) ; - uint32_t j ; - j = SpeedAllowed ; - if ( j > 9000000 ) - { - j = 9000000 ; - } - - SD_SetSpeed( j ) ; - if (Cmd_A41_resp & 0x40000000 ) // OCR_SD_CCS) - sd_cmd16(); - return i ; //phsmci->HSMCI_RSPR[0] ; - } - else - { - return 0 ; - } -} - -const uint8_t SpeedTable[] = { 1, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80 } ; - -// This routine is called every 10 mS, and checks for card -// insertion and removal. -// When a card is inserted, it initialises it ready for read/write access. -void sd_poll_10mS() -{ - uint32_t i ; - - if ( !CardIsConnected() ) - { - Card_state = SD_ST_EMPTY ; - Sd_rca = 0 ; - - } - - switch ( Card_state ) - { - case SD_ST_EMPTY : - if ( CardIsConnected() ) { - Card_state = SD_ST_INIT1 ; - } - break ; - - case SD_ST_INIT1 : - i = sd_cmd0() ; // Keep a 10mS delay after this before sd_cmd8() - if ( i == 0 ) - { - Card_state = SD_ST_INIT2 ; - } - break ; - - case SD_ST_INIT2 : - i = sd_cmd8() ; - if ( i == 0 ) - { - Card_state = SD_ST_IDLE ; - } - break ; - - case SD_ST_IDLE : - i = sd_acmd41() ; - if ( i & 0x80000000 ) { - Card_state = SD_ST_READY ; - } - break ; - - case SD_ST_READY : - i = sd_cmd2() ; - if ( i == 0 ) - { - Card_state = SD_ST_IDENT ; - } - break ; - - case SD_ST_IDENT : - i = sd_cmd3() ; // Get new RCA - if ( i == 0 ) - { - Card_state = SD_ST_STBY ; - } - break ; - - case SD_ST_STBY : - i = sd_cmd9() ; - // Calc transmission speed - i = Card_CSD[0] & 0x0000007F ; - { - uint32_t j ; - j = i >> 3 ; - j = SpeedTable[j] ; - j *= 10000 ; - i &= 7 ; - if ( i-- ) - { - j *= 10 ; - } - if ( i-- ) - { - j *= 10 ; - } - if ( i ) - { - j *= 10 ; - } - SpeedAllowed = j ; - } - i = sd_cmd7() ; // Select Card - Card_state = SD_ST_TRAN ; - Sd_retries = 5 ; - break ; - - case SD_ST_TRAN : - i = sd_acmd51( Sd_128_resp ) ; - if ( i != 0 ) - { - if ( --Sd_retries > 0 ) - { - break ; - } - } - Card_SCR[0] = Sd_128_resp[0] ; - Card_SCR[1] = Sd_128_resp[1] ; - Card_state = SD_ST_DATA ; - i = sd_acmd6() ; // Set bus width to 4 bits, and speed to 9 MHz - // Should check the card can do this **** - break ; - } -} - -// Checks for card ready for read/write -// returns 1 for YES, 0 for NO -uint32_t sd_card_ready( void ) -{ - if ( CardIsConnected() ) - { - if ( Card_state == SD_ST_DATA ) - { - return 1 ; - } - } - return 0 ; -} - -uint32_t sd_cmd16() -{ -// @Mike: there is something wrong here, where could I have find infos??? -//#if 0 - Hsmci *phsmci = HSMCI; - - if (CardIsConnected()) - { - phsmci->HSMCI_BLKR = ( ( 512 ) << 16 ) | 1 ; - phsmci->HSMCI_ARGR = 512; - phsmci->HSMCI_CMDR = SDMMC_SET_BLOCKLEN; - - while(1) { - if (phsmci->HSMCI_SR & HSMCI_SR_CMDRDY) { - break; - } - } - return phsmci->HSMCI_RSPR[0]; - } - else - { - return 0; - } -//#else -// return 0; -//#endif -} - -uint32_t sd_read_block(uint32_t block_no, uint32_t *data) -{ - uint32_t result = 0; - Hsmci *phsmci = HSMCI; - uint32_t status = 0; - - if (sd_card_ready()) - { -// sd_cmd16(); - - // Wait for card to be ready for data transfers - do { - sd_cmd13(&status); - } while (((status & STATUS_READY_FOR_DATA) == 0) - || ((status & STATUS_STATE) != STATUS_TRAN) ); - - // Block size = 512, nblocks = 1 - phsmci->HSMCI_BLKR = ((512) << 16) | 1; - phsmci->HSMCI_MR = (phsmci->HSMCI_MR & (~(HSMCI_MR_BLKLEN_Msk|HSMCI_MR_FBYTE))) | (HSMCI_MR_PDCMODE|HSMCI_MR_WRPROOF|HSMCI_MR_RDPROOF) | (512 << 16); - phsmci->HSMCI_ARGR = Cmd_A41_resp & 0x40000000 ? block_no : block_no << 9; - phsmci->HSMCI_RPR = CONVERT_PTR(data); - phsmci->HSMCI_RCR = 512 / 4; - phsmci->HSMCI_PTCR = HSMCI_PTCR_RXTEN; - phsmci->HSMCI_CMDR = SD_READ_SINGLE_BLOCK; - - uint8_t retry = 100; - while (retry-- > 0) - { -#ifndef BOOT - CoTickDelay(1); // 2ms -#else - delay2ms() ; -#endif - if (phsmci->HSMCI_SR & HSMCI_SR_ENDRX) - { -// phsmci->HSMCI_PTCR = HSMCI_PTCR_RXTDIS; - result = 1; - break; - } - } - } - phsmci->HSMCI_PTCR = HSMCI_PTCR_RXTDIS; - phsmci->HSMCI_MR &= ~HSMCI_MR_PDCMODE; - return result; -} - -uint32_t sd_write_block( uint32_t block_no, uint32_t *data ) -{ - uint32_t result = 0; - Hsmci *phsmci = HSMCI; - uint32_t status = 0; - - if (sd_card_ready()) - { -// sd_cmd16(); - // Wait for card to be ready for data transfers - do { - sd_cmd13(&status); - } while (((status & STATUS_READY_FOR_DATA) == 0) - || ((status & STATUS_STATE) != STATUS_TRAN) ); - - // Block size = 512, nblocks = 1 - phsmci->HSMCI_BLKR = ((512) << 16) | 1; - phsmci->HSMCI_MR = (phsmci->HSMCI_MR & (~(HSMCI_MR_BLKLEN_Msk|HSMCI_MR_FBYTE))) | (HSMCI_MR_PDCMODE|HSMCI_MR_WRPROOF|HSMCI_MR_RDPROOF) | (512 << 16); - phsmci->HSMCI_ARGR = Cmd_A41_resp & 0x40000000 ? block_no : block_no << 9; - phsmci->HSMCI_TPR = CONVERT_PTR(data); - phsmci->HSMCI_TCR = 512 / 4; - phsmci->HSMCI_CMDR = SD_WRITE_SINGLE_BLOCK; - phsmci->HSMCI_PTCR = HSMCI_PTCR_TXTEN; - - uint8_t retry = 100; - while (retry-- > 0) { -#ifndef BOOT - CoTickDelay(1); // 2ms -#else - delay2ms() ; -#endif - if (phsmci->HSMCI_SR & HSMCI_SR_NOTBUSY) - { -// phsmci->HSMCI_PTCR = HSMCI_PTCR_TXTDIS; - result = 1; - break; - } - } - } - - phsmci->HSMCI_PTCR = HSMCI_PTCR_TXTDIS; - phsmci->HSMCI_MR &= ~HSMCI_MR_PDCMODE; - return result; -} - -/* - Notes on SD card: - -1) CMD8 fails and CMD58 fails: must be MMC, thus initialize using CMD1 -2) CMD8 fails and CMD58 passes: must be Ver1.x Standard Capacity SD Memory Card -3) CMD8 passes and CMD58 passes (CCS = 0): must be Ver2.00 or later Standard Capacity SD Memory Card -4) CMD8 passes and CMD58 passes (CCS = 1): must be Ver2.00 or later High Capacity SD Memory Card -5) CMD8 passes and CMD58 passes but indicates non compatible voltage range: unusable card - -On card present -1. Send CMD 55 (resp 48bit) - followed by ACMD41 (resp48bit) - until bit 31 of response is '1' - -2. Send CMD 2 (resp 136bit) - card ID - -3. Send CMD 3 (resp 48 bit) - new RCA returned - -4. Send CMD 9 (resp 136) - CSD - -5. Send CMD 7 (resp 48) - - -6. Send CMD 55 (resp 48bit) - followed by ACMD51 (resp48bit) - SCR stored as 2 32 bit values - -Now decide what the card can do! - -7. Set block length - -8. Set bus width - -9. Read block 0 - -*/ - - -#include "ff.h" -#include "diskio.h" - -/* FAT sub-type boundaries */ -/* Note that the FAT spec by Microsoft says 4085 but Windows works with 4087! */ -#define MIN_FAT16 4086 /* Minimum number of clusters for FAT16 */ -#define MIN_FAT32 65526 /* Minimum number of clusters for FAT32 */ - - -/* FatFs refers the members in the FAT structures as byte array instead of -/ structure member because there are incompatibility of the packing option -/ between compilers. */ - -#define BS_jmpBoot 0 -#define BS_OEMName 3 -#define BPB_BytsPerSec 11 -#define BPB_SecPerClus 13 -#define BPB_RsvdSecCnt 14 -#define BPB_NumFATs 16 -#define BPB_RootEntCnt 17 -#define BPB_TotSec16 19 -#define BPB_Media 21 -#define BPB_FATSz16 22 -#define BPB_SecPerTrk 24 -#define BPB_NumHeads 26 -#define BPB_HiddSec 28 -#define BPB_TotSec32 32 -#define BS_DrvNum 36 -#define BS_BootSig 38 -#define BS_VolID 39 -#define BS_VolLab 43 -#define BS_FilSysType 54 -#define BPB_FATSz32 36 -#define BPB_ExtFlags 40 -#define BPB_FSVer 42 -#define BPB_RootClus 44 -#define BPB_FSInfo 48 -#define BPB_BkBootSec 50 -#define BS_DrvNum32 64 -#define BS_BootSig32 66 -#define BS_VolID32 67 -#define BS_VolLab32 71 -#define BS_FilSysType32 82 -#define FSI_LeadSig 0 -#define FSI_StrucSig 484 -#define FSI_Free_Count 488 -#define FSI_Nxt_Free 492 -#define MBR_Table 446 -#define BS_55AA 510 - -#define DIR_Name 0 -#define DIR_Attr 11 -#define DIR_NTres 12 -#define DIR_CrtTime 14 -#define DIR_CrtDate 16 -#define DIR_FstClusHI 20 -#define DIR_WrtTime 22 -#define DIR_WrtDate 24 -#define DIR_FstClusLO 26 -#define DIR_FileSize 28 -#define LDIR_Ord 0 -#define LDIR_Attr 11 -#define LDIR_Type 12 -#define LDIR_Chksum 13 -#define LDIR_FstClusLO 26 - -#ifdef BOOT -#if !defined(SIMU) -#include "Fat12.cpp" -#endif -#endif - -/*-----------------------------------------------------------------------*/ -/* Initialize Disk Drive */ -/*-----------------------------------------------------------------------*/ - -DSTATUS disk_initialize ( - BYTE drv /* Physical drive nmuber (0) */ - ) -{ -#ifdef BOOT - if (drv==1) return RES_OK ; /* EEPROM */ -#endif - if (drv) return STA_NOINIT; /* Supports only single drive */ - if ( sd_card_ready() == 0 ) return RES_NOTRDY; - return RES_OK; - -#if 0 - BYTE n, cmd, ty, ocr[4]; - - - if (drv) return STA_NOINIT; /* Supports only single drive */ - - if (Stat & STA_NODISK) return Stat; /* No card in the socket */ - - power_on(); /* Force socket power on */ - FCLK_SLOW(); - for (n = 10; n; n--) rcvr_spi(); /* 80 dummy clocks */ - - ty = 0; - if (send_cmd(CMD0, 0) == 1) { /* Enter Idle state */ - Timer1 = 100; /* Initialization timeout of 1000 msec */ - if (send_cmd(CMD8, 0x1AA) == 1) { /* SDv2? */ - for (n = 0; n < 4; n++) ocr[n] = rcvr_spi(); /* Get trailing return value of R7 resp */ - if (ocr[2] == 0x01 && ocr[3] == 0xAA) { /* The card can work at vdd range of 2.7-3.6V */ - while (Timer1 && send_cmd(ACMD41, 1UL << 30)); /* Wait for leaving idle state (ACMD41 with HCS bit) */ - if (Timer1 && send_cmd(CMD58, 0) == 0) { /* Check CCS bit in the OCR */ - for (n = 0; n < 4; n++) ocr[n] = rcvr_spi(); - ty = (ocr[0] & 0x40) ? CT_SD2 | CT_BLOCK : CT_SD2; /* SDv2 */ - } - } - } else { /* SDv1 or MMCv3 */ - if (send_cmd(ACMD41, 0) <= 1) { - ty = CT_SD1; cmd = ACMD41; /* SDv1 */ - } else { - ty = CT_MMC; cmd = CMD1; /* MMCv3 */ - } - while (Timer1 && send_cmd(cmd, 0)); /* Wait for leaving idle state */ - if (!Timer1 || send_cmd(CMD16, 512) != 0) /* Set R/W block length to 512 */ - ty = 0; - } - } - CardType = ty; - deselect(); - - if (ty) { /* Initialization succeded */ - Stat &= ~STA_NOINIT; /* Clear STA_NOINIT */ - FCLK_FAST(); - } else { /* Initialization failed */ - power_off(); - } - - return Stat; -#endif -} - -/*-----------------------------------------------------------------------*/ -/* Get Disk Status */ -/*-----------------------------------------------------------------------*/ - -DSTATUS disk_status ( BYTE drv /* Physical drive number (0) */ ) -{ - - if (drv==1) return RES_OK ; /* EEPROM */ - if (drv) return STA_NOINIT; /* Supports only single drive */ - if ( sd_card_ready() == 0 ) return RES_NOTRDY; - return RES_OK; -} - -#if !defined(SIMU) - -/*-----------------------------------------------------------------------*/ -/* Read Sector(s) */ -/*-----------------------------------------------------------------------*/ - -DRESULT disk_read ( - BYTE drv, /* Physical drive nmuber (0) */ - BYTE *buff, /* Pointer to the data buffer to store read data */ - DWORD sector, /* Start sector number (LBA) */ - BYTE count /* Sector count (1..255) */ - ) -{ - uint32_t result ; - if ( !count) return RES_PARERR ; - -#ifdef BOOT - if (drv==1) /* EEPROM */ - { - - do - { - result = fat12Read( buff, sector ) ; - if (result) - { - sector += 1 ; - buff += 512 ; - count -= 1 ; - } - else - { - count = 1 ; // Flag error - break ; - } - } while ( count ) ; - } - else -#endif - { - if (drv ) return RES_PARERR; - - if ( sd_card_ready() == 0 ) return RES_NOTRDY; - - do { - result = sd_read_block( sector, ( uint32_t *)buff ) ; - if (result) { - sector += 1 ; - buff += 512 ; - count -= 1 ; - } - else { - count = 1 ; // Flag error - break ; - } - } while ( count ) ; - } - return count ? RES_ERROR : RES_OK; -} - - -/*-----------------------------------------------------------------------*/ -/* Write Sector(s) */ -/*-----------------------------------------------------------------------*/ - -DRESULT disk_write ( - BYTE drv, /* Physical drive nmuber (0) */ - const BYTE *buff, /* Pointer to the data to be written */ - DWORD sector, /* Start sector number (LBA) */ - BYTE count /* Sector count (1..255) */ - ) -{ - uint32_t result ; - - if ( !count) return RES_PARERR ; - -#ifdef BOOT - if (drv==1) /* EEPROM */ - { - count = fat12Write( buff, sector, count ) ; - } - else -#endif - { - if (drv ) return RES_PARERR; - - if ( sd_card_ready() == 0 ) return RES_NOTRDY; - - // TODO if (Stat & STA_PROTECT) return RES_WRPRT; - - do { - result = sd_write_block( sector, ( uint32_t *)buff ) ; - if (result) { - sector += 1 ; - buff += 512 ; - count -= 1 ; - } - else { - count = 1 ; // Flag error - break ; - } - } while ( count ) ; - } - return count ? RES_ERROR : RES_OK; -} - -#endif - -/*-----------------------------------------------------------------------*/ -/* Miscellaneous Functions */ -/*-----------------------------------------------------------------------*/ - -DRESULT disk_ioctl ( - BYTE drv, /* Physical drive nmuber (0) */ - BYTE ctrl, /* Control code */ - BYTE *buff /* Buffer to send/receive control data */ - ) -{ - DRESULT res; - BYTE *csd = (BYTE*)&Card_CSD[0]; - BYTE n; // csd[16], *ptr = buff; - WORD csize; - - res = RES_ERROR; -#ifdef BOOT - if (drv==1) - { - switch (ctrl) - { - case CTRL_SYNC : /* Make sure that no pending write process. Do not remove this or written sector might not left updated. */ - /* BSS if (select()) { - deselect(); */ - res = RES_OK; - // } - break ; - - case GET_SECTOR_COUNT : /* Get number of sectors on the disk (DWORD) */ -#ifdef REVX - *(DWORD*)buff = (DWORD)2051 ; -#else - *(DWORD*)buff = (DWORD)1539 ; -#endif - res = RES_OK; - break; - - case GET_SECTOR_SIZE : /* Get R/W sector size (WORD) */ - *(WORD*)buff = 512; - res = RES_OK; - break; - - } - return res ; - } -#endif - - if (drv) return RES_PARERR; - - res = RES_ERROR; - - if (ctrl == CTRL_POWER) { -#if 0 - switch (ptr[0]) { - case 0: /* Sub control code (POWER_OFF) */ - power_off(); /* Power off */ - res = RES_OK; - break; - case 1: /* Sub control code (POWER_GET) */ - ptr[1] = (BYTE)power_status(); - res = RES_OK; - break; - default : - res = RES_PARERR; - } -#endif - } - else { - switch (ctrl) { - case CTRL_SYNC : /* Make sure that no pending write process. Do not remove this or written sector might not left updated. */ - /* BSS if (select()) { - deselect(); */ - res = RES_OK; - // } - break; - - case GET_SECTOR_COUNT : /* Get number of sectors on the disk (DWORD) */ - // if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { - if ((csd[0] >> 6) == 1) { /* SDC ver 2.00 */ - csize = csd[9] + ((WORD)csd[8] << 8) + 1; - *(DWORD*)buff = (DWORD)csize << 10; - } else { /* SDC ver 1.XX or MMC*/ - n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + ((csd[9] & 3) << 1) + 2; - csize = (csd[8] >> 6) + ((WORD)csd[7] << 2) + ((WORD)(csd[6] & 3) << 10) + 1; - *(DWORD*)buff = (DWORD)csize << (n - 9); - } - res = RES_OK; - // } - break; - - case GET_SECTOR_SIZE : /* Get R/W sector size (WORD) */ - *(WORD*)buff = 512; - res = RES_OK; - break; - - case GET_BLOCK_SIZE : /* Get erase block size in unit of sector (DWORD) */ - // only used in f_mkfs -#if 0 - if (CardType & CT_SD2) { /* SDv2? */ - if (send_cmd(ACMD13, 0) == 0) { /* Read SD status */ - rcvr_spi(); - if (rcvr_datablock(csd, 16)) { /* Read partial block */ - for (n = 64 - 16; n; n--) rcvr_spi(); /* Purge trailing data */ - *(DWORD*)buff = 16UL << (csd[10] >> 4); - res = RES_OK; - } - } - } else { /* SDv1 or MMCv3 */ - if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { /* Read CSD */ - if (CardType & CT_SD1) { /* SDv1 */ - *(DWORD*)buff = (((csd[10] & 63) << 1) + ((WORD)(csd[11] & 128) >> 7) + 1) << ((csd[13] >> 6) - 1); - } else { /* MMCv3 */ - *(DWORD*)buff = ((WORD)((csd[10] & 124) >> 2) + 1) * (((csd[11] & 3) << 3) + ((csd[11] & 224) >> 5) + 1); - } - res = RES_OK; - } - } -#endif - break; - -#if 0 - case MMC_GET_TYPE : /* Get card type flags (1 byte) */ - *ptr = CardType; - res = RES_OK; - break; - - case MMC_GET_CSD : /* Receive CSD as a data block (16 bytes) */ - if (send_cmd(CMD9, 0) == 0 /* READ_CSD */ - && rcvr_datablock(ptr, 16)) - res = RES_OK; - break; - - case MMC_GET_CID : /* Receive CID as a data block (16 bytes) */ - if (send_cmd(CMD10, 0) == 0 /* READ_CID */ - && rcvr_datablock(ptr, 16)) - res = RES_OK; - break; - - case MMC_GET_OCR : /* Receive OCR as an R3 resp (4 bytes) */ - if (send_cmd(CMD58, 0) == 0) { /* READ_OCR */ - for (n = 4; n; n--) *ptr++ = rcvr_spi(); - res = RES_OK; - } - break; - - case MMC_GET_SDSTAT : /* Receive SD statsu as a data block (64 bytes) */ - if (send_cmd(ACMD13, 0) == 0) { /* SD_STATUS */ - rcvr_spi(); - if (rcvr_datablock(ptr, 64)) - res = RES_OK; - } - break; -#endif - default: - res = RES_PARERR; - } - - // BSS deselect(); - } - - return res; -} - - - - - - - - - - diff --git a/radio/bootloader/include/AT91SAM3S4.h b/radio/bootloader/include/AT91SAM3S4.h deleted file mode 100644 index 1e6914308..000000000 --- a/radio/bootloader/include/AT91SAM3S4.h +++ /dev/null @@ -1,7102 +0,0 @@ -/* ---------------------------------------------------------------------------- */ -/* Atmel Microcontroller Software Support */ -/* ---------------------------------------------------------------------------- */ -/* Copyright (c) 2009, Atmel Corporation */ -/* */ -/* All rights reserved. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following condition is met: */ -/* */ -/* - Redistributions of source code must retain the above copyright notice, */ -/* this list of conditions and the disclaimer below. */ -/* */ -/* Atmel's name may not be used to endorse or promote products derived from */ -/* this software without specific prior written permission. */ -/* */ -/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ -/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ -/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ -/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ -/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ -/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ -/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ -/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ -/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ -/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* ---------------------------------------------------------------------------- */ -/* */ -/* File Name : AT91SAM3S.h */ -/* Object : AT91SAM3S definitions */ -/* Generated by : AT91 SW Application Group */ -/* Generated on : 2009-10-26 */ - -#ifndef AT91SAM3S_H -#define AT91SAM3S_H - -/** \addtogroup AT91SAM3S_definitions AT91SAM3S definitions - This file defines all structures and symbols for AT91SAM3S: - - registers and bitfields - - peripheral base address - - peripheral ID - - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __ASSEMBLY__ -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *) value) -#define REG_ACCESS(type, address) (*(type*)address) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ***************************************************************************** */ -/* CMSIS DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_cmsis CMSIS Definitions */ - -/*@{*/ - -/** - * \brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#define __MPU_PRESENT 0 /**< AT91SAM3S does not provide a MPU present or not */ -#define __NVIC_PRIO_BITS 4 /**< AT91SAM3S uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ - -/**< Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************/ - NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ -/****** AT91SAM3S specific Interrupt Numbers *****************************************/ - - SUPC_IRQn = 0, /**< 0 AT91SAM3S Supply Controller (SUPC) */ - RSTC_IRQn = 1, /**< 1 AT91SAM3S Reset Controller (RSTC) */ - RTC_IRQn = 2, /**< 2 AT91SAM3S Real Time Clock (RTC) */ - RTT_IRQn = 3, /**< 3 AT91SAM3S Real Time Timer (RTT) */ - WDT_IRQn = 4, /**< 4 AT91SAM3S Watchdog Timer (WDT) */ - PMC_IRQn = 5, /**< 5 AT91SAM3S Power Management Controller (PMC) */ - EFC_IRQn = 6, /**< 6 AT91SAM3S Enhanced Flash Controller (EFC) */ - UART0_IRQn = 8, /**< 8 AT91SAM3S UART 0 (UART0) */ - UART1_IRQn = 9, /**< 9 AT91SAM3S UART 1 (UART1) */ - SMC_IRQn = 10, /**< 10 AT91SAM3S Static Memory Controller (SMC) */ - PIOA_IRQn = 11, /**< 11 AT91SAM3S Parallel I/O Controller A (PIOA) */ - PIOB_IRQn = 12, /**< 12 AT91SAM3S Parallel I/O Controller B (PIOB) */ - PIOC_IRQn = 13, /**< 13 AT91SAM3S Parallel I/O Controller C (PIOC) */ - USART0_IRQn = 14, /**< 14 AT91SAM3S USART 0 (USART0) */ - USART1_IRQn = 15, /**< 15 AT91SAM3S USART 1 (USART1) */ - HSMCI_IRQn = 18, /**< 18 AT91SAM3S Multimedia Card Interface (HSMCI) */ - TWI0_IRQn = 19, /**< 19 AT91SAM3S Two Wire Interface 0 (TWI0) */ - TWI1_IRQn = 20, /**< 20 AT91SAM3S Two Wire Interface 1 (TWI1) */ - SPI_IRQn = 21, /**< 21 AT91SAM3S Serial Peripheral Interface (SPI) */ - SSC_IRQn = 22, /**< 22 AT91SAM3S Synchronous Serial Controler (SSC) */ - TC0_IRQn = 23, /**< 23 AT91SAM3S Timer/Counter 0 (TC0) */ - TC1_IRQn = 24, /**< 24 AT91SAM3S Timer/Counter 1 (TC1) */ - TC2_IRQn = 25, /**< 25 AT91SAM3S Timer/Counter 2 (TC2) */ - TC3_IRQn = 26, /**< 26 AT91SAM3S Timer/Counter 3 (TC3) */ - TC4_IRQn = 27, /**< 27 AT91SAM3S Timer/Counter 4 (TC4) */ - TC5_IRQn = 28, /**< 28 AT91SAM3S Timer/Counter 5 (TC5) */ - ADC_IRQn = 29, /**< 29 AT91SAM3S Analog To Digital Converter (ADC) */ - DACC_IRQn = 30, /**< 30 AT91SAM3S Digital To Analog Converter (DACC) */ - PWM_IRQn = 31, /**< 31 AT91SAM3S Pulse Width Modulation (PWM) */ - CRCCU_IRQn = 32, /**< 32 AT91SAM3S CRC Calculation Unit (CRCCU) */ - ACC_IRQn = 33, /**< 33 AT91SAM3S Analog Comparator (ACC) */ - UDP_IRQn = 34 /**< 34 AT91SAM3S USB Device Port (UDP) */ -} IRQn_Type; -/*@}*/ - -/* ***************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_api Peripheral Software API */ -/*@{*/ -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_ACC Analog Comparator Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Acc hardware registers */ -typedef struct { - WoReg ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */ - RwReg ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */ - RwReg Reserved1[7]; - WoReg ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */ - WoReg ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */ - RoReg ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */ - RoReg ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */ - RwReg Reserved2[24]; - RwReg ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */ - RwReg Reserved3[19]; - RwReg ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protect Mode Register */ - RoReg ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protect Status Register */ -} Acc; -#endif /* __ASSEMBLY__ */ -/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */ -#define ACC_CR_SWRST (0x1 << 0) /**< \brief (ACC_CR) SoftWare ReSeT */ -/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */ -#define ACC_MR_SELPLUS (0x7 << 0) /**< \brief (ACC_MR) SELection for PLUS comparator input */ -#define ACC_MR_SELMINUS (0x7 << 4) /**< \brief (ACC_MR) SELection for MINUS comparator input */ -#define ACC_MR_ACEN (0x1 << 8) /**< \brief (ACC_MR) Analog Comparator ENable */ -#define ACC_MR_ACEN_EN (0x1 << 8) /**< \brief (ACC_MR) Analog Comparator ENable */ -#define ACC_MR_ACEN_DIS (0x0 << 8) /**< \brief (ACC_MR) Analog Comparator Disable */ -#define ACC_MR_EDGETYP (0x3 << 9) /**< \brief (ACC_MR) EDGE TYPe */ -#define ACC_MR_EDGETYP_RISING (0x0 << 9) /**< \brief (ACC_MR) EDGE TYPe ,RISING edge*/ -#define ACC_MR_EDGETYP_FALLING (0x1 << 9) /**< \brief (ACC_MR) EDGE TYPe,falling edge */ -#define ACC_MR_EDGETYP_ANY (0x2 << 9) /**< \brief (ACC_MR) EDGE TYPe,any edge */ -#define ACC_MR_INV (0x1 << 12) /**< \brief (ACC_MR) INVert comparator output */ -#define ACC_MR_INV_EN (0x1 << 12) /**< \brief (ACC_MR) INVert comparator output */ -#define ACC_MR_INV_DIS (0x0 << 12) /**< \brief (ACC_MR) DIRECTLY */ -#define ACC_MR_SELFS (0x1 << 13) /**< \brief (ACC_MR) SELection of Fault Source */ -#define ACC_MR_SELFS_CF (0x0 << 13) /**< \brief (ACC_MR) SELection of Fault Source */ -#define ACC_MR_SELFS_OUTPUT (0x1 << 13) /**< \brief (ACC_MR) SELection of Fault Source */ -#define ACC_MR_FE (0x1 << 14) /**< \brief (ACC_MR) Fault Enable */ -#define ACC_MR_FE_EN (0x1 << 14) /**< \brief (ACC_MR) Fault Enable */ -#define ACC_MR_FE_DIS (0x0 << 14) /**< \brief (ACC_MR) Fault Enable */ -/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */ -#define ACC_IER_CE (0x1 << 0) /**< \brief (ACC_IER) Comparison Edge */ -/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */ -#define ACC_IDR_CE (0x1 << 0) /**< \brief (ACC_IDR) Comparison Edge */ -/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */ -#define ACC_IMR_CE (0x1 << 0) /**< \brief (ACC_IMR) Comparison Edge */ -/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */ -#define ACC_ISR_CE (0x1 << 0) /**< \brief (ACC_ISR) Comparison Edge */ -#define ACC_ISR_SCO (0x1 << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */ -#define ACC_ISR_MASK (0x1 << 31) /**< \brief (ACC_ISR) */ -/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */ -#define ACC_ACR_ISEL (0x1 << 0) /**< \brief (ACC_ACR) Current SELection */ -#define ACC_ACR_HYST (0x3 << 1) /**< \brief (ACC_ACR) HYSTeresis selection */ -/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protect Mode Register -------- */ -#define ACC_WPMR_WPEN (0x1 << 0) /**< \brief (ACC_WPMR) Write Protect Enable */ -#define ACC_WPMR_WPKEY (0xffffff << 8) /**< \brief (ACC_WPMR) Write Protect KEY */ -/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protect Status Register -------- */ -#define ACC_WPSR_WPROTERR (0x1 << 0) /**< \brief (ACC_WPSR) Write PROTection ERRor */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Analog-to-digital Converter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_ADC Analog-to-digital Converter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Adc hardware registers */ -typedef struct { - WoReg ADC_CR; /**< \brief (Adc Offset: 0x00) Control Register */ - RwReg ADC_MR; /**< \brief (Adc Offset: 0x04) Mode Register */ - RwReg ADC_SEQR1; /**< \brief (Adc Offset: 0x08) Channel Sequence 1Register */ - RwReg ADC_SEQR2; /**< \brief (Adc Offset: 0x0C) Channel Sequence 2 Register */ - WoReg ADC_CHER; /**< \brief (Adc Offset: 0x10) Channel Enable Register */ - WoReg ADC_CHDR; /**< \brief (Adc Offset: 0x14) Channel Disable Register */ - RoReg ADC_CHSR; /**< \brief (Adc Offset: 0x18) Channel Status Register */ - RwReg Reserved1[1]; - RoReg ADC_LCDR; /**< \brief (Adc Offset: 0x20) Last Converted Data Register */ - WoReg ADC_IER; /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */ - WoReg ADC_IDR; /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */ - RoReg ADC_IMR; /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */ - RoReg ADC_ISR; /**< \brief (Adc Offset: 0x30) Interrupt Status Register */ - RwReg Reserved2[2]; - RoReg ADC_OVER; /**< \brief (Adc Offset: 0x3C) Overrun Status Register */ - RwReg ADC_EMR; /**< \brief (Adc Offset: 0x40) Extended Mode Register */ - RwReg ADC_CWR; /**< \brief (Adc Offset: 0x44) Compare Window Register */ - RwReg ADC_CGR; /**< \brief (Adc Offset: 0x48) Channel Gain Register */ - RwReg ADC_COR; /**< \brief (Adc Offset: 0x4C) Channel Offset Register */ - RoReg ADC_CDR0; /**< \brief (Adc Offset: 0x50) Channel Data Register 0 */ - RoReg ADC_CDR1; /**< \brief (Adc Offset: 0x54) Channel Data Register 1 */ - RoReg ADC_CDR2; /**< \brief (Adc Offset: 0x58) Channel Data Register 2 */ - RoReg ADC_CDR3; /**< \brief (Adc Offset: 0x5C) Channel Data Register 3 */ - RoReg ADC_CDR4; /**< \brief (Adc Offset: 0x60) Channel Data Register 4 */ - RoReg ADC_CDR5; /**< \brief (Adc Offset: 0x64) Channel Data Register 5 */ - RoReg ADC_CDR6; /**< \brief (Adc Offset: 0x68) Channel Data Register 6 */ - RoReg ADC_CDR7; /**< \brief (Adc Offset: 0x6C) Channel Data Register 7 */ - RoReg ADC_CDR8; /**< \brief (Adc Offset: 0x70) Channel Data Register 8 */ - RoReg ADC_CDR9; /**< \brief (Adc Offset: 0x74) Channel Data Register 9 */ - RoReg ADC_CDR10; /**< \brief (Adc Offset: 0x78) Channel Data Register 10 */ - RoReg ADC_CDR11; /**< \brief (Adc Offset: 0x7C) Channel Data Register 11 */ - RoReg ADC_CDR12; /**< \brief (Adc Offset: 0x80) Channel Data Register 12 */ - RoReg ADC_CDR13; /**< \brief (Adc Offset: 0x84) Channel Data Register 13 */ - RoReg ADC_CDR14; /**< \brief (Adc Offset: 0x88) Channel Data Register 14 */ - RoReg ADC_CDR15; /**< \brief (Adc Offset: 0x8C) Channel Data Register 15 */ - RwReg Reserved3[1]; - RwReg ADC_ACR; /**< \brief (Adc Offset: 0x94) Analog Control Register */ - RwReg Reserved4[19]; - RwReg ADC_WPMR; /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */ - RoReg ADC_WPSR; /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */ - RwReg Reserved5[5]; - RwReg ADC_RPR; /**< \brief (Adc Offset: 0x100) Receive Pointer Register */ - RwReg ADC_RCR; /**< \brief (Adc Offset: 0x104) Receive Counter Register */ - RwReg ADC_TPR; /**< \brief (Adc Offset: 0x108) Transmit Pointer Register */ - RwReg ADC_TCR; /**< \brief (Adc Offset: 0x10C) Transmit Counter Register */ - RwReg ADC_RNPR; /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */ - RwReg ADC_RNCR; /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */ - RwReg ADC_TNPR; /**< \brief (Adc Offset: 0x118) Transmit Next Pointer Register */ - RwReg ADC_TNCR; /**< \brief (Adc Offset: 0x11C) Transmit Next Counter Register */ - WoReg ADC_PTCR; /**< \brief (Adc Offset: 0x120) Transfer Control Register */ - RoReg ADC_PTSR; /**< \brief (Adc Offset: 0x124) Transfer Status Register */ -} Adc; -#endif /* __ASSEMBLY__ */ -/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */ -#define ADC_CR_SWRST (0x1 << 0) /**< \brief (ADC_CR) Software Reset */ -#define ADC_CR_START (0x1 << 1) /**< \brief (ADC_CR) Start Conversion */ -/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */ -#define ADC_MR_TRGEN (0x1 << 0) /**< \brief (ADC_MR) Trigger Enable */ -#define ADC_MR_TRGEN_DIS (0x0 << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software.*/ -#define ADC_MR_TRGEN_EN (0x1) /**< (ADC) Hardware trigger selected by TRGSEL field is enabled.*/ -#define ADC_MR_TRGSEL (0x7 << 1) /**< \brief (ADC_MR) Trigger Selection */ -#define ADC_MR_TRGSEL_EXT (0x0 << 1) /**< \brief (ADC_MR) Selected TRGSEL = External Trigger*/ -#define ADC_MR_TRGSEL_TIOA0 (0x1 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO0*/ -#define ADC_MR_TRGSEL_TIOA1 (0x2 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO1*/ -#define ADC_MR_TRGSEL_TIOA2 (0x3 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO2*/ -#define ADC_MR_TRGSEL_PWM0_TRIG (0x4 << 1) /**< \brief (ADC_MR) Selected TRGSEL = PWM trigger*/ -#define ADC_MR_TRGSEL_PWM1_TRIG (0x5 << 1) /**< \brief (ADC_MR) Selected TRGSEL = PWM Trigger*/ -#define ADC_MR_TRGSEL_RESERVED (0x6 << 1) /**< \brief (ADC_MR) Selected TRGSEL = Reserved*/ -#define ADC_MR_LOWRES (0x1 << 4) /**< \brief (ADC_MR) Resolution */ -#define ADC_MR_LOWRES_12_BIT (0x0 << 4) /**< \brief (ADC_MR) 12-bit resolution*/ -#define ADC_MR_LOWRES_10_BIT (0x1 << 4) /**< \brief (ADC_MR) 10-bit resolution*/ -#define ADC_MR_SLEEP (0x1 << 5) /**< \brief (ADC_MR) Sleep Mode */ -#define ADC_MR_SLEEP_NORMAL (0x0 << 5) /**< \brief (ADC12B) Normal Mode*/ -#define ADC_MR_FWUP (0x1 << 6) /**< \brief (ADC_MR) Fast Wake Up */ -#define ADC_MR_FREERUN (0x1 << 7) /**< \brief (ADC_MR) Free Run Mode */ -#define ADC_MR_PRESCAL (0xff << 8) /**< \brief (ADC_MR) Prescaler Rate Selection */ -#define ADC_MR_STARTUP (0xf << 16) /**< \brief (ADC_MR) Start Up Time */ -#define ADC_MR_SETTLING (0x3 << 20) /**< \brief (ADC_MR) Analog Settling Time */ -#define ADC_MR_ANACH (0x1 << 23) /**< \brief (ADC_MR) Analog Change */ -#define ADC_MR_TRACKTIM (0xf << 24) /**< \brief (ADC_MR) Tracking Time */ -#define ADC_MR_TRANSFER (0x3 << 28) /**< \brief (ADC_MR) */ -#define ADC_MR_USEQ (0x1 << 31) /**< \brief (ADC_MR) User Sequence Enable */ -/* -------- ADC_SEQ1R : (ADC Offset: 0x08) Channel Sequence 1Register -------- */ -#define ADC_SEQ1R_USCH1 (0x7 << 0) /**< \brief (ADC_SEQ1R) User Sequence Number 1 */ -#define ADC_SEQ1R_USCH2 (0x7 << 4) /**< \brief (ADC_SEQ1R) User Sequence Number 2 */ -#define ADC_SEQ1R_USCH3 (0x7 << 8) /**< \brief (ADC_SEQ1R) User Sequence Number 3 */ -#define ADC_SEQ1R_USCH4 (0x7 << 12) /**< \brief (ADC_SEQ1R) User Sequence Number 4 */ -#define ADC_SEQ1R_USCH5 (0x7 << 16) /**< \brief (ADC_SEQ1R) User Sequence Number 5 */ -#define ADC_SEQ1R_USCH6 (0x7 << 20) /**< \brief (ADC_SEQ1R) User Sequence Number 6 */ -#define ADC_SEQ1R_USCH7 (0x7 << 24) /**< \brief (ADC_SEQ1R) User Sequence Number 7 */ -#define ADC_SEQ1R_USCH8 (0x7 << 28) /**< \brief (ADC_SEQ1R) User Sequence Number 8 */ -/* -------- ADC_SEQ2R : (ADC Offset: 0x0C) Channel Sequence 2 Register -------- */ -#define ADC_SEQ2R_USCH9 (0x7 << 0) /**< \brief (ADC_SEQ2R) User Sequence Number 9 */ -#define ADC_SEQ2R_USCH10 (0x7 << 4) /**< \brief (ADC_SEQ2R) User Sequence Number 10 */ -#define ADC_SEQ2R_USCH11 (0x7 << 8) /**< \brief (ADC_SEQ2R) User Sequence Number 11 */ -#define ADC_SEQ2R_USCH12 (0x7 << 12) /**< \brief (ADC_SEQ2R) User Sequence Number 12 */ -#define ADC_SEQ2R_USCH13 (0x7 << 16) /**< \brief (ADC_SEQ2R) User Sequence Number 13 */ -#define ADC_SEQ2R_USCH14 (0x7 << 20) /**< \brief (ADC_SEQ2R) User Sequence Number 14 */ -#define ADC_SEQ2R_USCH15 (0x7 << 24) /**< \brief (ADC_SEQ2R) User Sequence Number 15 */ -#define ADC_SEQ2R_USCH16 (0x7 << 28) /**< \brief (ADC_SEQ2R) User Sequence Number 16 */ -/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */ -#define ADC_CHER_CH0 (0x1 << 0) /**< \brief (ADC_CHER) Channel 0 Enable */ -#define ADC_CHER_CH1 (0x1 << 1) /**< \brief (ADC_CHER) Channel 1 Enable */ -#define ADC_CHER_CH2 (0x1 << 2) /**< \brief (ADC_CHER) Channel 2 Enable */ -#define ADC_CHER_CH3 (0x1 << 3) /**< \brief (ADC_CHER) Channel 3 Enable */ -#define ADC_CHER_CH4 (0x1 << 4) /**< \brief (ADC_CHER) Channel 4 Enable */ -#define ADC_CHER_CH5 (0x1 << 5) /**< \brief (ADC_CHER) Channel 5 Enable */ -#define ADC_CHER_CH6 (0x1 << 6) /**< \brief (ADC_CHER) Channel 6 Enable */ -#define ADC_CHER_CH7 (0x1 << 7) /**< \brief (ADC_CHER) Channel 7 Enable */ -#define ADC_CHER_CH8 (0x1 << 8) /**< \brief (ADC_CHER) Channel 8 Enable */ -#define ADC_CHER_CH9 (0x1 << 9) /**< \brief (ADC_CHER) Channel 9 Enable */ -#define ADC_CHER_CH10 (0x1 << 10) /**< \brief (ADC_CHER) Channel 10 Enable */ -#define ADC_CHER_CH11 (0x1 << 11) /**< \brief (ADC_CHER) Channel 11 Enable */ -#define ADC_CHER_CH12 (0x1 << 12) /**< \brief (ADC_CHER) Channel 12 Enable */ -#define ADC_CHER_CH13 (0x1 << 13) /**< \brief (ADC_CHER) Channel 13 Enable */ -#define ADC_CHER_CH14 (0x1 << 14) /**< \brief (ADC_CHER) Channel 14 Enable */ -#define ADC_CHER_CH15 (0x1 << 15) /**< \brief (ADC_CHER) Channel 15 Enable */ -/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */ -#define ADC_CHDR_CH0 (0x1 << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */ -#define ADC_CHDR_CH1 (0x1 << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */ -#define ADC_CHDR_CH2 (0x1 << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */ -#define ADC_CHDR_CH3 (0x1 << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */ -#define ADC_CHDR_CH4 (0x1 << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */ -#define ADC_CHDR_CH5 (0x1 << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */ -#define ADC_CHDR_CH6 (0x1 << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */ -#define ADC_CHDR_CH7 (0x1 << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */ -#define ADC_CHDR_CH8 (0x1 << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */ -#define ADC_CHDR_CH9 (0x1 << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */ -#define ADC_CHDR_CH10 (0x1 << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */ -#define ADC_CHDR_CH11 (0x1 << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */ -#define ADC_CHDR_CH12 (0x1 << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */ -#define ADC_CHDR_CH13 (0x1 << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */ -#define ADC_CHDR_CH14 (0x1 << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */ -#define ADC_CHDR_CH15 (0x1 << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */ -/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */ -#define ADC_CHSR_CH0 (0x1 << 0) /**< \brief (ADC_CHSR) Channel 0 Status */ -#define ADC_CHSR_CH1 (0x1 << 1) /**< \brief (ADC_CHSR) Channel 1 Status */ -#define ADC_CHSR_CH2 (0x1 << 2) /**< \brief (ADC_CHSR) Channel 2 Status */ -#define ADC_CHSR_CH3 (0x1 << 3) /**< \brief (ADC_CHSR) Channel 3 Status */ -#define ADC_CHSR_CH4 (0x1 << 4) /**< \brief (ADC_CHSR) Channel 4 Status */ -#define ADC_CHSR_CH5 (0x1 << 5) /**< \brief (ADC_CHSR) Channel 5 Status */ -#define ADC_CHSR_CH6 (0x1 << 6) /**< \brief (ADC_CHSR) Channel 6 Status */ -#define ADC_CHSR_CH7 (0x1 << 7) /**< \brief (ADC_CHSR) Channel 7 Status */ -#define ADC_CHSR_CH8 (0x1 << 8) /**< \brief (ADC_CHSR) Channel 8 Status */ -#define ADC_CHSR_CH9 (0x1 << 9) /**< \brief (ADC_CHSR) Channel 9 Status */ -#define ADC_CHSR_CH10 (0x1 << 10) /**< \brief (ADC_CHSR) Channel 10 Status */ -#define ADC_CHSR_CH11 (0x1 << 11) /**< \brief (ADC_CHSR) Channel 11 Status */ -#define ADC_CHSR_CH12 (0x1 << 12) /**< \brief (ADC_CHSR) Channel 12 Status */ -#define ADC_CHSR_CH13 (0x1 << 13) /**< \brief (ADC_CHSR) Channel 13 Status */ -#define ADC_CHSR_CH14 (0x1 << 14) /**< \brief (ADC_CHSR) Channel 14 Status */ -#define ADC_CHSR_CH15 (0x1 << 15) /**< \brief (ADC_CHSR) Channel 15 Status */ -/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */ -#define ADC_LCDR_LDATA (0xfff << 0) /**< \brief (ADC_LCDR) Last Data Converted */ -#define ADC_LCDR_CHNB (0xf << 12) /**< \brief (ADC_LCDR) Channel Number */ -/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */ -#define ADC_IER_EOC0 (0x1 << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */ -#define ADC_IER_EOC1 (0x1 << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */ -#define ADC_IER_EOC2 (0x1 << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */ -#define ADC_IER_EOC3 (0x1 << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */ -#define ADC_IER_EOC4 (0x1 << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */ -#define ADC_IER_EOC5 (0x1 << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */ -#define ADC_IER_EOC6 (0x1 << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */ -#define ADC_IER_EOC7 (0x1 << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */ -#define ADC_IER_EOC8 (0x1 << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */ -#define ADC_IER_EOC9 (0x1 << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */ -#define ADC_IER_EOC10 (0x1 << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */ -#define ADC_IER_EOC11 (0x1 << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */ -#define ADC_IER_EOC12 (0x1 << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */ -#define ADC_IER_EOC13 (0x1 << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */ -#define ADC_IER_EOC14 (0x1 << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */ -#define ADC_IER_EOC15 (0x1 << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */ -#define ADC_IER_DRDY (0x1 << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */ -#define ADC_IER_GOVRE (0x1 << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */ -#define ADC_IER_COMPE (0x1 << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */ -#define ADC_IER_ENDRX (0x1 << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */ -#define ADC_IER_RXBUFF (0x1 << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */ -/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */ -#define ADC_IDR_EOC0 (0x1 << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */ -#define ADC_IDR_EOC1 (0x1 << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */ -#define ADC_IDR_EOC2 (0x1 << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */ -#define ADC_IDR_EOC3 (0x1 << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */ -#define ADC_IDR_EOC4 (0x1 << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */ -#define ADC_IDR_EOC5 (0x1 << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */ -#define ADC_IDR_EOC6 (0x1 << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */ -#define ADC_IDR_EOC7 (0x1 << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */ -#define ADC_IDR_EOC8 (0x1 << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */ -#define ADC_IDR_EOC9 (0x1 << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */ -#define ADC_IDR_EOC10 (0x1 << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */ -#define ADC_IDR_EOC11 (0x1 << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */ -#define ADC_IDR_EOC12 (0x1 << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */ -#define ADC_IDR_EOC13 (0x1 << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */ -#define ADC_IDR_EOC14 (0x1 << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */ -#define ADC_IDR_EOC15 (0x1 << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */ -#define ADC_IDR_DRDY (0x1 << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */ -#define ADC_IDR_GOVRE (0x1 << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */ -#define ADC_IDR_COMPE (0x1 << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */ -#define ADC_IDR_ENDRX (0x1 << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */ -#define ADC_IDR_RXBUFF (0x1 << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */ -/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */ -#define ADC_IMR_EOC0 (0x1 << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */ -#define ADC_IMR_EOC1 (0x1 << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */ -#define ADC_IMR_EOC2 (0x1 << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */ -#define ADC_IMR_EOC3 (0x1 << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */ -#define ADC_IMR_EOC4 (0x1 << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */ -#define ADC_IMR_EOC5 (0x1 << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */ -#define ADC_IMR_EOC6 (0x1 << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */ -#define ADC_IMR_EOC7 (0x1 << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */ -#define ADC_IMR_EOC8 (0x1 << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */ -#define ADC_IMR_EOC9 (0x1 << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */ -#define ADC_IMR_EOC10 (0x1 << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */ -#define ADC_IMR_EOC11 (0x1 << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */ -#define ADC_IMR_EOC12 (0x1 << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */ -#define ADC_IMR_EOC13 (0x1 << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */ -#define ADC_IMR_EOC14 (0x1 << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */ -#define ADC_IMR_EOC15 (0x1 << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */ -#define ADC_IMR_DRDY (0x1 << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */ -#define ADC_IMR_GOVRE (0x1 << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */ -#define ADC_IMR_COMPE (0x1 << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */ -#define ADC_IMR_ENDRX (0x1 << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */ -#define ADC_IMR_RXBUFF (0x1 << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */ -/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */ -#define ADC_ISR_EOC0 (0x1 << 0) /**< \brief (ADC_ISR) End of Conversion 0 */ -#define ADC_ISR_EOC1 (0x1 << 1) /**< \brief (ADC_ISR) End of Conversion 1 */ -#define ADC_ISR_EOC2 (0x1 << 2) /**< \brief (ADC_ISR) End of Conversion 2 */ -#define ADC_ISR_EOC3 (0x1 << 3) /**< \brief (ADC_ISR) End of Conversion 3 */ -#define ADC_ISR_EOC4 (0x1 << 4) /**< \brief (ADC_ISR) End of Conversion 4 */ -#define ADC_ISR_EOC5 (0x1 << 5) /**< \brief (ADC_ISR) End of Conversion 5 */ -#define ADC_ISR_EOC6 (0x1 << 6) /**< \brief (ADC_ISR) End of Conversion 6 */ -#define ADC_ISR_EOC7 (0x1 << 7) /**< \brief (ADC_ISR) End of Conversion 7 */ -#define ADC_ISR_EOC8 (0x1 << 8) /**< \brief (ADC_ISR) End of Conversion 8 */ -#define ADC_ISR_EOC9 (0x1 << 9) /**< \brief (ADC_ISR) End of Conversion 9 */ -#define ADC_ISR_EOC10 (0x1 << 10) /**< \brief (ADC_ISR) End of Conversion 10 */ -#define ADC_ISR_EOC11 (0x1 << 11) /**< \brief (ADC_ISR) End of Conversion 11 */ -#define ADC_ISR_EOC12 (0x1 << 12) /**< \brief (ADC_ISR) End of Conversion 12 */ -#define ADC_ISR_EOC13 (0x1 << 13) /**< \brief (ADC_ISR) End of Conversion 13 */ -#define ADC_ISR_EOC14 (0x1 << 14) /**< \brief (ADC_ISR) End of Conversion 14 */ -#define ADC_ISR_EOC15 (0x1 << 15) /**< \brief (ADC_ISR) End of Conversion 15 */ -#define ADC_ISR_DRDY (0x1 << 24) /**< \brief (ADC_ISR) Data Ready */ -#define ADC_ISR_GOVRE (0x1 << 25) /**< \brief (ADC_ISR) General Overrun Error */ -#define ADC_ISR_COMPE (0x1 << 26) /**< \brief (ADC_ISR) Comparison Error */ -#define ADC_ISR_ENDRX (0x1 << 27) /**< \brief (ADC_ISR) End of RX Buffer */ -#define ADC_ISR_RXBUFF (0x1 << 28) /**< \brief (ADC_ISR) RX Buffer Full */ -/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */ -#define ADC_OVER_OVRE0 (0x1 << 0) /**< \brief (ADC_OVER) Overrun Error 0 */ -#define ADC_OVER_OVRE1 (0x1 << 1) /**< \brief (ADC_OVER) Overrun Error 1 */ -#define ADC_OVER_OVRE2 (0x1 << 2) /**< \brief (ADC_OVER) Overrun Error 2 */ -#define ADC_OVER_OVRE3 (0x1 << 3) /**< \brief (ADC_OVER) Overrun Error 3 */ -#define ADC_OVER_OVRE4 (0x1 << 4) /**< \brief (ADC_OVER) Overrun Error 4 */ -#define ADC_OVER_OVRE5 (0x1 << 5) /**< \brief (ADC_OVER) Overrun Error 5 */ -#define ADC_OVER_OVRE6 (0x1 << 6) /**< \brief (ADC_OVER) Overrun Error 6 */ -#define ADC_OVER_OVRE7 (0x1 << 7) /**< \brief (ADC_OVER) Overrun Error 7 */ -#define ADC_OVER_OVRE8 (0x1 << 8) /**< \brief (ADC_OVER) Overrun Error 8 */ -#define ADC_OVER_OVRE9 (0x1 << 9) /**< \brief (ADC_OVER) Overrun Error 9 */ -#define ADC_OVER_OVRE10 (0x1 << 10) /**< \brief (ADC_OVER) Overrun Error 10 */ -#define ADC_OVER_OVRE11 (0x1 << 11) /**< \brief (ADC_OVER) Overrun Error 11 */ -#define ADC_OVER_OVRE12 (0x1 << 12) /**< \brief (ADC_OVER) Overrun Error 12 */ -#define ADC_OVER_OVRE13 (0x1 << 13) /**< \brief (ADC_OVER) Overrun Error 13 */ -#define ADC_OVER_OVRE14 (0x1 << 14) /**< \brief (ADC_OVER) Overrun Error 14 */ -#define ADC_OVER_OVRE15 (0x1 << 15) /**< \brief (ADC_OVER) Overrun Error 15 */ -/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */ -#define ADC_EMR_CMPMODE (0x3 << 0) /**< \brief (ADC_EMR) Comparison Mode */ -#define ADC_EMR_CMPMODE_LOW (0x0 << 0) /**< \brief (ADC_EMR) Comparison Mode,lower than low threshold */ -#define ADC_EMR_CMPMODE_HIGH (0x1 << 0) /**< \brief (ADC_EMR) Comparison Mode,higher than high threshold */ -#define ADC_EMR_CMPMODE_IN (0x2 << 0) /**< \brief (ADC_EMR) Comparison Mode, in the comparison window */ -#define ADC_EMR_CMPMODE_OUT (0x3 << 0) /**< \brief (ADC_EMR) Comparison Mode, out of the comparison window */ -#define ADC_EMR_CMPSEL (0xf << 4) /**< \brief (ADC_EMR) Comparison Selected Channel */ -#define ADC_EMR_CMPALL (0x1 << 9) /**< \brief (ADC_EMR) Compare All Channels */ -#define ADC_EMR_TAG (0x1 << 24) /**< \brief (ADC_EMR) TAG of ADC_LDCR register */ -/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */ -#define ADC_CWR_LOWTHRES (0xfff << 0) /**< \brief (ADC_CWR) Low Threshold */ -#define ADC_CWR_HIGHTHRES (0xfff << 16) /**< \brief (ADC_CWR) High Threshold */ -/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */ -#define ADC_CGR_GAIN0 (0x3 << 0) /**< \brief (ADC_CGR) Gain for channel 0 */ -#define ADC_CGR_GAIN1 (0x3 << 2) /**< \brief (ADC_CGR) Gain for channel 1 */ -#define ADC_CGR_GAIN2 (0x3 << 4) /**< \brief (ADC_CGR) Gain for channel 2 */ -#define ADC_CGR_GAIN3 (0x3 << 6) /**< \brief (ADC_CGR) Gain for channel 3 */ -#define ADC_CGR_GAIN4 (0x3 << 8) /**< \brief (ADC_CGR) Gain for channel 4 */ -#define ADC_CGR_GAIN5 (0x3 << 10) /**< \brief (ADC_CGR) Gain for channel 5 */ -#define ADC_CGR_GAIN6 (0x3 << 12) /**< \brief (ADC_CGR) Gain for channel 6 */ -#define ADC_CGR_GAIN7 (0x3 << 14) /**< \brief (ADC_CGR) Gain for channel 7 */ -#define ADC_CGR_GAIN8 (0x3 << 16) /**< \brief (ADC_CGR) Gain for channel 8 */ -#define ADC_CGR_GAIN9 (0x3 << 18) /**< \brief (ADC_CGR) Gain for channel 9 */ -#define ADC_CGR_GAIN10 (0x3 << 20) /**< \brief (ADC_CGR) Gain for channel 10 */ -#define ADC_CGR_GAIN11 (0x3 << 22) /**< \brief (ADC_CGR) Gain for channel 11 */ -#define ADC_CGR_GAIN12 (0x3 << 24) /**< \brief (ADC_CGR) Gain for channel 12 */ -#define ADC_CGR_GAIN13 (0x3 << 26) /**< \brief (ADC_CGR) Gain for channel 13 */ -#define ADC_CGR_GAIN14 (0x3 << 28) /**< \brief (ADC_CGR) Gain for channel 14 */ -#define ADC_CGR_GAIN15 (0x3 << 30) /**< \brief (ADC_CGR) Gain for channel 15 */ -/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */ -#define ADC_COR_OFF0 (0x1 << 0) /**< \brief (ADC_COR) Offset for channel 0 */ -#define ADC_COR_OFF1 (0x1 << 1) /**< \brief (ADC_COR) Offset for channel 1 */ -#define ADC_COR_OFF2 (0x1 << 2) /**< \brief (ADC_COR) Offset for channel 2 */ -#define ADC_COR_OFF3 (0x1 << 3) /**< \brief (ADC_COR) Offset for channel 3 */ -#define ADC_COR_OFF4 (0x1 << 4) /**< \brief (ADC_COR) Offset for channel 4 */ -#define ADC_COR_OFF5 (0x1 << 5) /**< \brief (ADC_COR) Offset for channel 5 */ -#define ADC_COR_OFF6 (0x1 << 6) /**< \brief (ADC_COR) Offset for channel 6 */ -#define ADC_COR_OFF7 (0x1 << 7) /**< \brief (ADC_COR) Offset for channel 7 */ -#define ADC_COR_OFF8 (0x1 << 8) /**< \brief (ADC_COR) Offset for channel 8 */ -#define ADC_COR_OFF9 (0x1 << 9) /**< \brief (ADC_COR) Offset for channel 9 */ -#define ADC_COR_OFF10 (0x1 << 10) /**< \brief (ADC_COR) Offset for channel 10 */ -#define ADC_COR_OFF11 (0x1 << 11) /**< \brief (ADC_COR) Offset for channel 11 */ -#define ADC_COR_OFF12 (0x1 << 12) /**< \brief (ADC_COR) Offset for channel 12 */ -#define ADC_COR_OFF13 (0x1 << 13) /**< \brief (ADC_COR) Offset for channel 13 */ -#define ADC_COR_OFF14 (0x1 << 14) /**< \brief (ADC_COR) Offset for channel 14 */ -#define ADC_COR_OFF15 (0x1 << 15) /**< \brief (ADC_COR) Offset for channel 15 */ -#define ADC_COR_DIFF0 (0x1 << 16) /**< \brief (ADC_COR) Differential inputs for channel 0 */ -#define ADC_COR_DIFF1 (0x1 << 17) /**< \brief (ADC_COR) Differential inputs for channel 1 */ -#define ADC_COR_DIFF2 (0x1 << 18) /**< \brief (ADC_COR) Differential inputs for channel 2 */ -#define ADC_COR_DIFF3 (0x1 << 19) /**< \brief (ADC_COR) Differential inputs for channel 3 */ -#define ADC_COR_DIFF4 (0x1 << 20) /**< \brief (ADC_COR) Differential inputs for channel 4 */ -#define ADC_COR_DIFF5 (0x1 << 21) /**< \brief (ADC_COR) Differential inputs for channel 5 */ -#define ADC_COR_DIFF6 (0x1 << 22) /**< \brief (ADC_COR) Differential inputs for channel 6 */ -#define ADC_COR_DIFF7 (0x1 << 23) /**< \brief (ADC_COR) Differential inputs for channel 7 */ -#define ADC_COR_DIFF8 (0x1 << 24) /**< \brief (ADC_COR) Differential inputs for channel 8 */ -#define ADC_COR_DIFF9 (0x1 << 25) /**< \brief (ADC_COR) Differential inputs for channel 9 */ -#define ADC_COR_DIFF10 (0x1 << 26) /**< \brief (ADC_COR) Differential inputs for channel 10 */ -#define ADC_COR_DIFF11 (0x1 << 27) /**< \brief (ADC_COR) Differential inputs for channel 11 */ -#define ADC_COR_DIFF12 (0x1 << 28) /**< \brief (ADC_COR) Differential inputs for channel 12 */ -#define ADC_COR_DIFF13 (0x1 << 29) /**< \brief (ADC_COR) Differential inputs for channel 13 */ -#define ADC_COR_DIFF14 (0x1 << 30) /**< \brief (ADC_COR) Differential inputs for channel 14 */ -#define ADC_COR_DIFF15 (0x1 << 31) /**< \brief (ADC_COR) Differential inputs for channel 15 */ -/* -------- ADC_CDR0 : (ADC Offset: 0x50) Channel Data Register 0 -------- */ -#define ADC_CDR0_DATA (0x3ff << 0) /**< \brief (ADC_CDR0) Converted Data */ -/* -------- ADC_CDR1 : (ADC Offset: 0x54) Channel Data Register 1 -------- */ -#define ADC_CDR1_DATA (0x3ff << 0) /**< \brief (ADC_CDR1) Converted Data */ -/* -------- ADC_CDR2 : (ADC Offset: 0x58) Channel Data Register 2 -------- */ -#define ADC_CDR2_DATA (0x3ff << 0) /**< \brief (ADC_CDR2) Converted Data */ -/* -------- ADC_CDR3 : (ADC Offset: 0x5C) Channel Data Register 3 -------- */ -#define ADC_CDR3_DATA (0x3ff << 0) /**< \brief (ADC_CDR3) Converted Data */ -/* -------- ADC_CDR4 : (ADC Offset: 0x60) Channel Data Register 4 -------- */ -#define ADC_CDR4_DATA (0x3ff << 0) /**< \brief (ADC_CDR4) Converted Data */ -/* -------- ADC_CDR5 : (ADC Offset: 0x64) Channel Data Register 5 -------- */ -#define ADC_CDR5_DATA (0x3ff << 0) /**< \brief (ADC_CDR5) Converted Data */ -/* -------- ADC_CDR6 : (ADC Offset: 0x68) Channel Data Register 6 -------- */ -#define ADC_CDR6_DATA (0x3ff << 0) /**< \brief (ADC_CDR6) Converted Data */ -/* -------- ADC_CDR15 : (ADC Offset: 0x6C) Channel Data Register 15 -------- */ -#define ADC_CDR15_DATA (0x3ff << 0) /**< \brief (ADC_CDR15) Converted Data */ -/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */ -#define ADC_ACR_TSON (0x1 << 4) /**< \brief (ADC_ACR) Temperature Sensor On */ -#define ADC_ACR_IBCTL (0x3 << 8) /**< \brief (ADC_ACR) ADC Bias Current Control */ -/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */ -#define ADC_WPMR_WPEN (0x1 << 0) /**< \brief (ADC_WPMR) Write Protect Enable */ -#define ADC_WPMR_WPKEY (0xffffff << 8) /**< \brief (ADC_WPMR) Write Protect KEY */ -/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */ -#define ADC_WPSR_WPVS (0x1 << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */ -#define ADC_WPSR_WPVSRC (0xffff << 8) /**< \brief (ADC_WPSR) Write Protect Violation Source */ -/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */ -#define ADC_RPR_RXPTR (0xffffffff << 0) /**< \brief (ADC_RPR) Receive Pointer Register */ -/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */ -#define ADC_RCR_RXCTR (0xffff << 0) /**< \brief (ADC_RCR) Receive Counter Register */ -/* -------- ADC_TPR : (ADC Offset: 0x108) Transmit Pointer Register -------- */ -#define ADC_TPR_TXPTR (0xffffffff << 0) /**< \brief (ADC_TPR) Transmit Counter Register */ -/* -------- ADC_TCR : (ADC Offset: 0x10C) Transmit Counter Register -------- */ -#define ADC_TCR_TXCTR (0xffff << 0) /**< \brief (ADC_TCR) Transmit Counter Register */ -/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */ -#define ADC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (ADC_RNPR) Receive Next Pointer */ -/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */ -#define ADC_RNCR_RXNCTR (0xffff << 0) /**< \brief (ADC_RNCR) Receive Next Counter */ -/* -------- ADC_TNPR : (ADC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define ADC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (ADC_TNPR) Transmit Next Pointer */ -/* -------- ADC_TNCR : (ADC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define ADC_TNCR_TXNCTR (0xffff << 0) /**< \brief (ADC_TNCR) Transmit Counter Next */ -/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */ -#define ADC_PTCR_RXTEN (0x1 << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */ -#define ADC_PTCR_RXTDIS (0x1 << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */ -#define ADC_PTCR_TXTEN (0x1 << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */ -#define ADC_PTCR_TXTDIS (0x1 << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */ -/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */ -#define ADC_PTSR_RXTEN (0x1 << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */ -#define ADC_PTSR_TXTEN (0x1 << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Chip Identifier */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_CHIPID Chip Identifier */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Chipid hardware registers */ -typedef struct { - RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */ - RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */ -} Chipid; -#endif /* __ASSEMBLY__ */ -/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */ -#define CHIPID_CIDR_VERSION (0x1f << 0) /**< \brief (CHIPID_CIDR) Version of the Device */ -#define CHIPID_CIDR_EPROC (0x7 << 5) /**< \brief (CHIPID_CIDR) Embedded Processor */ -#define CHIPID_CIDR_NVPSIZ (0xf << 8) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */ -#define CHIPID_CIDR_NVPSIZ2 (0xf << 12) /**< \brief (CHIPID_CIDR) */ -#define CHIPID_CIDR_SRAMSIZ (0xf << 16) /**< \brief (CHIPID_CIDR) Internal SRAM Size */ -#define CHIPID_CIDR_ARCH (0xff << 20) /**< \brief (CHIPID_CIDR) Architecture Identifier */ -#define CHIPID_CIDR_NVPTYP (0x7 << 28) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */ -#define CHIPID_CIDR_EXT (0x1 << 31) /**< \brief (CHIPID_CIDR) Extension Flag */ -/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */ -#define CHIPID_EXID_EXID (0xffffffff << 0) /**< \brief (CHIPID_EXID) Chip ID Extension */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Cyclic Redundancy Check Calculation Unit */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_CRCCU Cyclic Redundancy Check Calculation Unit */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Crccu hardware registers */ -typedef struct { - RwReg CRCCU_DSCR; /**< \brief (Crccu Offset: 0x00000000) CRCCU Descriptor Base Register */ - RwReg Reserved1[1]; - WoReg CRCCU_DMA_EN; /**< \brief (Crccu Offset: 0x00000008) CRCCU DMA Enable Register */ - WoReg CRCCU_DMA_DIS; /**< \brief (Crccu Offset: 0x0000000C) CRCCU DMA Disable Register */ - RoReg CRCCU_DMA_SR; /**< \brief (Crccu Offset: 0x00000010) CRCCU DMA Status Register */ - WoReg CRCCU_DMA_IER; /**< \brief (Crccu Offset: 0x00000014) CRCCU DMA Interrupt Enable Register */ - WoReg CRCCU_DMA_IDR; /**< \brief (Crccu Offset: 0x00000018) CRCCU DMA Interrupt Disable Register */ - RoReg CRCCU_DMA_IMR; /**< \brief (Crccu Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register */ - RoReg CRCCU_DMA_ISR; /**< \brief (Crccu Offset: 0x00000020) CRCCU DMA Interrupt Status Register */ - RwReg Reserved2[4]; - WoReg CRCCU_CR; /**< \brief (Crccu Offset: 0x00000034) CRCCU Control Register */ - RwReg CRCCU_MR; /**< \brief (Crccu Offset: 0x00000038) CRCCU Mode Register */ - RoReg CRCCU_SR; /**< \brief (Crccu Offset: 0x0000003C) CRCCU Status Register */ - WoReg CRCCU_IER; /**< \brief (Crccu Offset: 0x00000040) CRCCU Interrupt Enable Register */ - WoReg CRCCU_IDR; /**< \brief (Crccu Offset: 0x00000044) CRCCU Interrupt Disable Register */ - RoReg CRCCU_IMR; /**< \brief (Crccu Offset: 0x00000048) CRCCU Interrupt Mask Register */ - RoReg CRCCU_ISR; /**< \brief (Crccu Offset: 0x0000004C) CRCCU Interrupt Status Register */ -} Crccu; -#endif /* __ASSEMBLY__ */ -/* -------- CRCCU_DSCR : (CRCCU Offset: 0x00000000) CRCCU Descriptor Base Register -------- */ -#define CRCCU_DSCR_DSCR (0x7fffff << 9) /**< \brief (CRCCU_DSCR) Descriptor Base Address */ -/* -------- CRCCU_DMA_EN : (CRCCU Offset: 0x00000008) CRCCU DMA Enable Register -------- */ -#define CRCCU_DMA_EN_DMAEN (0x1 << 0) /**< \brief (CRCCU_DMA_EN) DMA Enable Register */ -/* -------- CRCCU_DMA_DIS : (CRCCU Offset: 0x0000000C) CRCCU DMA Disable Register -------- */ -#define CRCCU_DMA_DIS_DMADIS (0x1 << 0) /**< \brief (CRCCU_DMA_DIS) DMA Disable Register */ -/* -------- CRCCU_DMA_SR : (CRCCU Offset: 0x00000010) CRCCU DMA Status Register -------- */ -#define CRCCU_DMA_SR_DMASR (0x1 << 0) /**< \brief (CRCCU_DMA_SR) DMA Status Register */ -/* -------- CRCCU_DMA_IER : (CRCCU Offset: 0x00000014) CRCCU DMA Interrupt Enable Register -------- */ -#define CRCCU_DMA_IER_DMAIER (0x1 << 0) /**< \brief (CRCCU_DMA_IER) Interrupt Enable register */ -/* -------- CRCCU_DMA_IDR : (CRCCU Offset: 0x00000018) CRCCU DMA Interrupt Disable Register -------- */ -#define CRCCU_DMA_IDR_DMAIDR (0x1 << 0) /**< \brief (CRCCU_DMA_IDR) Interrupt Disable register */ -/* -------- CRCCU_DMA_IMR : (CRCCU Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register -------- */ -#define CRCCU_DMA_IMR_DMAIMR (0x1 << 0) /**< \brief (CRCCU_DMA_IMR) Interrupt Mask Register */ -/* -------- CRCCU_DMA_ISR : (CRCCU Offset: 0x00000020) CRCCU DMA Interrupt Status Register -------- */ -#define CRCCU_DMA_ISR_DMAISR (0x1 << 0) /**< \brief (CRCCU_DMA_ISR) Interrupt Status register */ -/* -------- CRCCU_CR : (CRCCU Offset: 0x00000034) CRCCU Control Register -------- */ -#define CRCCU_CR_RESET (0x1 << 0) /**< \brief (CRCCU_CR) CRC Computation Reset */ -/* -------- CRCCU_MR : (CRCCU Offset: 0x00000038) CRCCU Mode Register -------- */ -#define CRCCU_MR_ENABLE (0x1 << 0) /**< \brief (CRCCU_MR) CRC Enable */ -#define CRCCU_MR_COMPARE (0x1 << 1) /**< \brief (CRCCU_MR) CRC Compare */ -#define CRCCU_MR_PTYPE (0x3 << 2) /**< \brief (CRCCU_MR) Primitive Polynomial */ -#define CRCCU_MR_PTYPE_CCIT8023 (0x0 << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */ -#define CRCCU_MR_PTYPE_CASTAGNOLI (0x1 << 2) /**< \brief (CRCCU_MR) Polynom 0x1EDC6F41 */ -#define CRCCU_MR_PTYPE_CCIT16 (0x2 << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */ -#define CRCCU_MR_DIVIDER (0xf << 4) /**< \brief (CRCCU_MR) Request Divider */ -/* -------- CRCCU_SR : (CRCCU Offset: 0x0000003C) CRCCU Status Register -------- */ -#define CRCCU_SR_CRC (0xffffffff << 0) /**< \brief (CRCCU_SR) Cyclic Redundancy Check Value */ -/* -------- CRCCU_IER : (CRCCU Offset: 0x00000040) CRCCU Interrupt Enable Register -------- */ -#define CRCCU_IER_ERRIER (0x1 << 0) /**< \brief (CRCCU_IER) CRC Error Interrupt Enable */ -/* -------- CRCCU_IDR : (CRCCU Offset: 0x00000044) CRCCU Interrupt Disable Register -------- */ -#define CRCCU_IDR_ERRIDR (0x1 << 0) /**< \brief (CRCCU_IDR) CRC Error Interrupt Disable */ -/* -------- CRCCU_IMR : (CRCCU Offset: 0x00000048) CRCCU Interrupt Mask Register -------- */ -#define CRCCU_IMR_ERRIMR (0x1 << 0) /**< \brief (CRCCU_IMR) CRC Error Interrupt Mask */ -/* -------- CRCCU_ISR : (CRCCU Offset: 0x0000004C) CRCCU Interrupt Status Register -------- */ -#define CRCCU_ISR_ERRISR (0x1 << 0) /**< \brief (CRCCU_ISR) CRC Error Interrupt Status */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_DACC Digital-to-Analog Converter Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Dacc hardware registers */ -typedef struct { - WoReg DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */ - RwReg DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */ - RwReg Reserved1[2]; - WoReg DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */ - WoReg DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */ - RoReg DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */ - RwReg Reserved2[1]; - WoReg DACC_CDR; /**< \brief (Dacc Offset: 0x20) Conversion Data Register */ - WoReg DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */ - WoReg DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */ - RoReg DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */ - RoReg DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */ - RwReg Reserved3[24]; - RwReg DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */ - RwReg Reserved4[19]; - RwReg DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protect Mode register */ - RoReg DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protect Status register */ - RwReg Reserved5[5]; - RwReg DACC_RPR; /**< \brief (Dacc Offset: 0x100) Receive Pointer Register */ - RwReg DACC_RCR; /**< \brief (Dacc Offset: 0x104) Receive Counter Register */ - RwReg DACC_TPR; /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */ - RwReg DACC_TCR; /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */ - RwReg DACC_RNPR; /**< \brief (Dacc Offset: 0x110) Receive Next Pointer Register */ - RwReg DACC_RNCR; /**< \brief (Dacc Offset: 0x114) Receive Next Counter Register */ - RwReg DACC_TNPR; /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */ - RwReg DACC_TNCR; /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */ - WoReg DACC_PTCR; /**< \brief (Dacc Offset: 0x120) Transfer Control Register */ - RoReg DACC_PTSR; /**< \brief (Dacc Offset: 0x124) Transfer Status Register */ -} Dacc; -#endif /* __ASSEMBLY__ */ -/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */ -#define DACC_CR_SWRST (0x1 << 0) /**< \brief (DACC_CR) Software Reset */ -/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */ -#define DACC_MR_TRGEN (0x1 << 0) /**< \brief (DACC_MR) Trigger Enable */ -#define DACC_MR_TRGEN_DIS (0x0 << 0) // (DACC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. -#define DACC_MR_TRGEN_EN (0x1 << 0) // (DACC_MR) Hardware trigger selected by TRGSEL field is enabled. - -#define DACC_MR_TRGSEL (0x7 << 1) /**< \brief (DACC_MR) Trigger Selection */ -#define DACC_MR_TRGSEL_EXT_TRIG (0x0 << 1) // (DACC_MR) External trigger -#define DACC_MR_TRGSEL_TIOA_0 (0x1 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 0 -#define DACC_MR_TRGSEL_TIOA_1 (0x2 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 1 -#define DACC_MR_TRGSEL_TIOA_2 (0x3 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 2 -#define DACC_MR_TRGSEL_PWM_0 (0x4 << 1) // (DACC_MR) PWM Event Line 0 -#define DACC_MR_TRGSEL_PWM_1 (0x5 << 1) // (DACC_MR) PWM Event Line 1 -#define DACC_MR_WORD (0x1 << 4) /**< \brief (DACC_MR) Word Transfer */ -#define DACC_MR_WORD_HALF (0x0 << 4) /**< \brief (DACC_MR) Half-Word Transfer */ -#define DACC_MR_WORD_WORLD (0x1 << 4) /**< \brief (DACC_MR) Word Transfer */ -#define DACC_MR_SLEEP (0x1 << 5) /**< \brief (DACC_MR) Sleep Mode */ -#define DACC_MR_SLEEP_NORMAL (0x0 << 5) // (DACC_MR) Normal Mode -#define DACC_MR_SLEEP_SLEEP (0x1 << 5) // (DACC_MR) Sleep Modes -#define DACC_MR_FASTWKUP (0x1 << 6) /**< \brief (DACC_MR) Fast Wake up Mode */ -#define DACC_MR_REFRESH (0xff << 8) /**< \brief (DACC_MR) Refresh Period */ -#define DACC_MR_USER_SEL (0x3 << 16) /**< \brief (DACC_MR) User Channel Selection */ -#define DACC_MR_USER_SEL_0 (0x0 << 16) /**< \brief (DACC_MR) User Channel Selection */ -#define DACC_MR_USER_SEL_1 (0x1 << 16) /**< \brief (DACC_MR) User Channel Selection */ -#define DACC_MR_TAG (0x1 << 20) /**< \brief (DACC_MR) Tag Selection Mode */ -#define DACC_MR_MAXS (0x1 << 21) /**< \brief (DACC_MR) Max Speed Mode */ -#define DACC_MR_STARTUP (0x3f << 24) /**< \brief (DACC_MR) Startup Time Selection */ -/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */ -#define DACC_CHER_CH0 (0x1 << 0) /**< \brief (DACC_CHER) Channel 0 Enable */ -#define DACC_CHER_CH1 (0x1 << 1) /**< \brief (DACC_CHER) Channel 1 Enable */ -#define DACC_CHER_CH2 (0x1 << 2) /**< \brief (DACC_CHER) Channel 2 Enable */ -/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */ -#define DACC_CHDR_CH0 (0x1 << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */ -#define DACC_CHDR_CH1 (0x1 << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */ -#define DACC_CHDR_CH2 (0x1 << 2) /**< \brief (DACC_CHDR) Channel 2 Disable */ -/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */ -#define DACC_CHSR_CH0 (0x1 << 0) /**< \brief (DACC_CHSR) Channel 0 Status */ -#define DACC_CHSR_CH1 (0x1 << 1) /**< \brief (DACC_CHSR) Channel 1 Status */ -#define DACC_CHSR_CH2 (0x1 << 2) /**< \brief (DACC_CHSR) Channel 2 Status */ -/* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */ -#define DACC_CDR_DATA (0xffffffff << 0) /**< \brief (DACC_CDR) Data to Convert */ -/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */ -#define DACC_IER_TXRDY (0x1 << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */ -#define DACC_IER_EOC (0x1 << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */ -#define DACC_IER_ENDTX (0x1 << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */ -#define DACC_IER_TXBUFE (0x1 << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */ -/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */ -#define DACC_IDR_TXRDY (0x1 << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */ -#define DACC_IDR_EOC (0x1 << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */ -#define DACC_IDR_ENDTX (0x1 << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */ -#define DACC_IDR_TXBUFE (0x1 << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */ -/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */ -#define DACC_IMR_TXRDY (0x1 << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */ -#define DACC_IMR_EOC (0x1 << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */ -#define DACC_IMR_ENDTX (0x1 << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */ -#define DACC_IMR_TXBUFE (0x1 << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */ -/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */ -#define DACC_ISR_TXRDY (0x1 << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */ -#define DACC_ISR_EOC (0x1 << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */ -#define DACC_ISR_ENDTX (0x1 << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */ -#define DACC_ISR_TXBUFE (0x1 << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */ -/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */ -#define DACC_ACR_IBCTLCH0 (0x3 << 0) /**< \brief (DACC_ACR) Analog Output Current Control */ -#define DACC_ACR_IBCTLCH1 (0x3 << 2) /**< \brief (DACC_ACR) Analog Output Current Control */ -#define DACC_ACR_IBCTLDACCORE (0x3 << 8) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */ -/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */ -#define DACC_WPMR_WPEN (0x1 << 0) /**< \brief (DACC_WPMR) Write Protect Enable */ -#define DACC_WPMR_WPKEY (0xffffff << 8) /**< \brief (DACC_WPMR) Write Protect KEY */ -/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */ -#define DACC_WPSR_WPROTERR (0x1 << 0) /**< \brief (DACC_WPSR) Write protection error */ -#define DACC_WPSR_WPROTADDR (0xff << 8) /**< \brief (DACC_WPSR) Write protection error address */ -/* -------- DACC_RPR : (DACC Offset: 0x100) Receive Pointer Register -------- */ -#define DACC_RPR_RXPTR (0xffffffff << 0) /**< \brief (DACC_RPR) Receive Pointer Register */ -/* -------- DACC_RCR : (DACC Offset: 0x104) Receive Counter Register -------- */ -#define DACC_RCR_RXCTR (0xffff << 0) /**< \brief (DACC_RCR) Receive Counter Register */ -/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */ -#define DACC_TPR_TXPTR (0xffffffff << 0) /**< \brief (DACC_TPR) Transmit Counter Register */ -/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */ -#define DACC_TCR_TXCTR (0xffff << 0) /**< \brief (DACC_TCR) Transmit Counter Register */ -/* -------- DACC_RNPR : (DACC Offset: 0x110) Receive Next Pointer Register -------- */ -#define DACC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (DACC_RNPR) Receive Next Pointer */ -/* -------- DACC_RNCR : (DACC Offset: 0x114) Receive Next Counter Register -------- */ -#define DACC_RNCR_RXNCTR (0xffff << 0) /**< \brief (DACC_RNCR) Receive Next Counter */ -/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define DACC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (DACC_TNPR) Transmit Next Pointer */ -/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define DACC_TNCR_TXNCTR (0xffff << 0) /**< \brief (DACC_TNCR) Transmit Counter Next */ -/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */ -#define DACC_PTCR_RXTEN (0x1 << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */ -#define DACC_PTCR_RXTDIS (0x1 << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */ -#define DACC_PTCR_TXTEN (0x1 << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */ -#define DACC_PTCR_TXTDIS (0x1 << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */ -/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */ -#define DACC_PTSR_RXTEN (0x1 << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */ -#define DACC_PTSR_TXTEN (0x1 << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_EFC Embedded Flash Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Efc hardware registers */ -typedef struct { - RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */ - WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */ - RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */ - RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */ -} Efc; -#endif /* __ASSEMBLY__ */ -/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */ -#define EEFC_FMR_FRDY (0x1 << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */ -#define EEFC_FMR_FWS (0xf << 8) /**< \brief (EEFC_FMR) Flash Wait State */ -#define EEFC_FMR_FAM (0x1 << 24) /**< \brief (EEFC_FMR) Flash Access Mode */ -/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */ -#define EEFC_FCR_FCMD (0xff << 0) /**< \brief (EEFC_FCR) Flash Command */ -#define EEFC_FCR_FARG (0xffff << 8) /**< \brief (EEFC_FCR) Flash Command Argument */ -#define EEFC_FCR_FKEY (0xff << 24) /**< \brief (EEFC_FCR) Flash Writing Protection Key */ -/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */ -#define EEFC_FSR_FRDY (0x1 << 0) /**< \brief (EEFC_FSR) Flash Ready Status */ -#define EEFC_FSR_FCMDE (0x1 << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */ -#define EEFC_FSR_FLOCKE (0x1 << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */ -/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */ -#define EEFC_FRR_FVALUE (0xffffffff << 0) /**< \brief (EEFC_FRR) Flash Result Value */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR General Purpose Backup Register */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_GPBR General Purpose Backup Register */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Gpbr hardware registers */ -typedef struct { - RwReg SYS_GPBR0; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register 0 */ - RwReg SYS_GPBR1; /**< \brief (Gpbr Offset: 0x4) General Purpose Backup Register 1 */ - RwReg SYS_GPBR2; /**< \brief (Gpbr Offset: 0x8) General Purpose Backup Register 2 */ - RwReg SYS_GPBR3; /**< \brief (Gpbr Offset: 0xC) General Purpose Backup Register 3 */ -} Gpbr; -#endif /* __ASSEMBLY__ */ -/* -------- SYS_GPBR0 : (GPBR Offset: 0x0) General Purpose Backup Register 0 -------- */ -#define SYS_GPBR0_GPBR_VALUE0 (0xffffffff << 0) /**< \brief (SYS_GPBR0) Value of GPBR x */ -/* -------- SYS_GPBR1 : (GPBR Offset: 0x4) General Purpose Backup Register 1 -------- */ -#define SYS_GPBR1_GPBR_VALUE1 (0xffffffff << 0) /**< \brief (SYS_GPBR1) Value of GPBR x */ -/* -------- SYS_GPBR2 : (GPBR Offset: 0x8) General Purpose Backup Register 2 -------- */ -#define SYS_GPBR2_GPBR_VALUE2 (0xffffffff << 0) /**< \brief (SYS_GPBR2) Value of GPBR x */ -/* -------- SYS_GPBR3 : (GPBR Offset: 0xC) General Purpose Backup Register 3 -------- */ -#define SYS_GPBR3_GPBR_VALUE3 (0xffffffff << 0) /**< \brief (SYS_GPBR3) Value of GPBR x */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_HSMCI High Speed MultiMedia Card Interface */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Hsmci hardware registers */ -typedef struct { - WoReg HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */ - RwReg HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */ - RwReg HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */ - RwReg HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */ - RwReg HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */ - WoReg HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */ - RwReg HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */ - RwReg HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */ - RoReg HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */ - RoReg HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */ - WoReg HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */ - RwReg Reserved1[2]; - RoReg HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */ - WoReg HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */ - WoReg HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */ - RoReg HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */ - RwReg Reserved2[1]; - RwReg HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */ - RwReg Reserved3[35]; - RwReg HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */ - RoReg HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */ - RwReg Reserved4[5]; - RwReg HSMCI_RPR; /**< \brief (Hsmci Offset: 0x100) Receive Pointer Register */ - RwReg HSMCI_RCR; /**< \brief (Hsmci Offset: 0x104) Receive Counter Register */ - RwReg HSMCI_TPR; /**< \brief (Hsmci Offset: 0x108) Transmit Pointer Register */ - RwReg HSMCI_TCR; /**< \brief (Hsmci Offset: 0x10C) Transmit Counter Register */ - RwReg HSMCI_RNPR; /**< \brief (Hsmci Offset: 0x110) Receive Next Pointer Register */ - RwReg HSMCI_RNCR; /**< \brief (Hsmci Offset: 0x114) Receive Next Counter Register */ - RwReg HSMCI_TNPR; /**< \brief (Hsmci Offset: 0x118) Transmit Next Pointer Register */ - RwReg HSMCI_TNCR; /**< \brief (Hsmci Offset: 0x11C) Transmit Next Counter Register */ - WoReg HSMCI_PTCR; /**< \brief (Hsmci Offset: 0x120) Transfer Control Register */ - RoReg HSMCI_PTSR; /**< \brief (Hsmci Offset: 0x124) Transfer Status Register */ -} Hsmci; -#endif /* __ASSEMBLY__ */ -/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */ -#define HSMCI_CR_MCIEN (0x1 << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */ -#define HSMCI_CR_MCIDIS (0x1 << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */ -#define HSMCI_CR_PWSEN (0x1 << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */ -#define HSMCI_CR_PWSDIS (0x1 << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */ -#define HSMCI_CR_SWRST (0x1 << 7) /**< \brief (HSMCI_CR) Software Reset */ -/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */ -#define HSMCI_MR_CLKDIV_Pos 0 -#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */ -#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos))) -#define HSMCI_MR_PWSDIV_Pos 8 -#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */ -#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos))) -#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) */ -#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) */ -#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ -#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */ -#define HSMCI_MR_PDCMODE (0x1u << 15) /**< \brief (HSMCI_MR) PDC-oriented Mode */ -#define HSMCI_MR_BLKLEN_Pos 16 -#define HSMCI_MR_BLKLEN_Msk (0xffffu << HSMCI_MR_BLKLEN_Pos) /**< \brief (HSMCI_MR) Data Block Length */ -#define HSMCI_MR_BLKLEN(value) ((HSMCI_MR_BLKLEN_Msk & ((value) << HSMCI_MR_BLKLEN_Pos))) -/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ -#define HSMCI_DTOR_DTOCYC_Pos 0 -#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ -#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos))) -#define HSMCI_DTOR_DTOMUL_Pos 4 -#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */ -#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */ -#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */ -#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */ -#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */ -#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */ -#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */ -#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */ -#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */ -/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */ -#define HSMCI_SDCR_SDCSEL_Pos 0 -#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */ -#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */ -#define HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) /**< \brief (HSMCI_SDCR) - */ -#define HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) /**< \brief (HSMCI_SDCR) - */ -#define HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) /**< \brief (HSMCI_SDCR) - */ -#define HSMCI_SDCR_SDCBUS_Pos 6 -#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */ -#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */ -#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */ -#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */ -/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */ -#define HSMCI_ARGR_ARG (0xffffffff << 0) /**< \brief (HSMCI_ARGR) Command Argument */ -/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */ -#define HSMCI_CMDR_CMDNB_Pos 0 -#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */ -#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos))) -#define HSMCI_CMDR_RSPTYP_Pos 6 -#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */ -#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */ -#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */ -#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */ -#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */ -#define HSMCI_CMDR_SPCMD_Pos 8 -#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */ -#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */ -#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD:74 clock cycles for initialization sequence. */ -#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD:Wait for the end of the current data block transfer before sending the pending command. */ -#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command.The host cancels the ability for the device to return a command completion signal on the command line. */ -#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command:Corresponds to the Interrupt Mode (CMD40). */ -#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response:Corresponds to the Interrupt Mode (CMD40). */ -#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request.Start a boot operation mode, the host processor can read boot data from the MMC device directly. */ -#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation.This command allows the host processor to terminate the boot operation mode. */ -#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */ -#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */ -#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */ -#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */ -#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */ -#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */ -#define HSMCI_CMDR_TRCMD_Pos 16 -#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */ -#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */ -#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */ -#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */ -#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */ -#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */ -#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */ -#define HSMCI_CMDR_TRTYP_Pos 19 -#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */ -#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Single Block */ -#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Multiple Block */ -#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */ -#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */ -#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */ -#define HSMCI_CMDR_IOSPCMD_Pos 24 -#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */ -#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */ -#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */ -#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */ -#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */ -#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */ -#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */ -#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */ -/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */ -#define HSMCI_BLKR_BCNT_Pos 0 -#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */ -#define HSMCI_BLKR_BCNT_MULTIPLE (0x0u << 0) /**< \brief (HSMCI_BLKR) MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. */ -#define HSMCI_BLKR_BCNT_BYTE (0x4u << 0) /**< \brief (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. */ -#define HSMCI_BLKR_BCNT_BLOCK (0x5u << 0) /**< \brief (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. */ -#define HSMCI_BLKR_BLKLEN_Pos 16 -#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */ -#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos))) -/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */ -#define HSMCI_CSTOR_CSTOCYC_Pos 0 -#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */ -#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos))) -#define HSMCI_CSTOR_CSTOMUL_Pos 4 -#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */ -#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */ -#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */ -#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */ -#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */ -#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */ -#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */ -#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */ -#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */ -/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */ -#define HSMCI_RSPR_RSP (0xffffffff << 0) /**< \brief (HSMCI_RSPR[4]) Response */ -/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */ -#define HSMCI_RDR_DATA (0xffffffff << 0) /**< \brief (HSMCI_RDR) Data to Read */ -/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */ -#define HSMCI_TDR_DATA (0xffffffff << 0) /**< \brief (HSMCI_TDR) Data to Write */ -/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */ -#define HSMCI_SR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_SR) Command Ready */ -#define HSMCI_SR_RXRDY (0x1 << 1) /**< \brief (HSMCI_SR) Receiver Ready */ -#define HSMCI_SR_TXRDY (0x1 << 2) /**< \brief (HSMCI_SR) Transmit Ready */ -#define HSMCI_SR_BLKE (0x1 << 3) /**< \brief (HSMCI_SR) Data Block Ended */ -#define HSMCI_SR_DTIP (0x1 << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */ -#define HSMCI_SR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */ -#define HSMCI_SR_ENDRX (0x1 << 6) /**< \brief (HSMCI_SR) End of RX Buffer */ -#define HSMCI_SR_ENDTX (0x1 << 7) /**< \brief (HSMCI_SR) End of TX Buffer */ -#define HSMCI_SR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A */ -#define HSMCI_SR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */ -#define HSMCI_SR_CSRCV (0x1 << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */ -#define HSMCI_SR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_SR) RX Buffer Full */ -#define HSMCI_SR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_SR) TX Buffer Empty */ -#define HSMCI_SR_RINDE (0x1 << 16) /**< \brief (HSMCI_SR) Response Index Error */ -#define HSMCI_SR_RDIRE (0x1 << 17) /**< \brief (HSMCI_SR) Response Direction Error */ -#define HSMCI_SR_RCRCE (0x1 << 18) /**< \brief (HSMCI_SR) Response CRC Error */ -#define HSMCI_SR_RENDE (0x1 << 19) /**< \brief (HSMCI_SR) Response End Bit Error */ -#define HSMCI_SR_RTOE (0x1 << 20) /**< \brief (HSMCI_SR) Response Time-out Error */ -#define HSMCI_SR_DCRCE (0x1 << 21) /**< \brief (HSMCI_SR) Data CRC Error */ -#define HSMCI_SR_DTOE (0x1 << 22) /**< \brief (HSMCI_SR) Data Time-out Error */ -#define HSMCI_SR_CSTOE (0x1 << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */ -#define HSMCI_SR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_SR) FIFO empty flag */ -#define HSMCI_SR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_SR) Transfer Done flag */ -#define HSMCI_SR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */ -#define HSMCI_SR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */ -#define HSMCI_SR_OVRE (0x1 << 30) /**< \brief (HSMCI_SR) Overrun */ -#define HSMCI_SR_UNRE (0x1 << 31) /**< \brief (HSMCI_SR) Underrun */ -/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */ -#define HSMCI_IER_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */ -#define HSMCI_IER_RXRDY (0x1 << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */ -#define HSMCI_IER_TXRDY (0x1 << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */ -#define HSMCI_IER_BLKE (0x1 << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */ -#define HSMCI_IER_DTIP (0x1 << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */ -#define HSMCI_IER_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */ -#define HSMCI_IER_ENDRX (0x1 << 6) /**< \brief (HSMCI_IER) End of Receive Buffer Interrupt Enable */ -#define HSMCI_IER_ENDTX (0x1 << 7) /**< \brief (HSMCI_IER) End of Transmit Buffer Interrupt Enable */ -#define HSMCI_IER_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */ -#define HSMCI_IER_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */ -#define HSMCI_IER_CSRCV (0x1 << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */ -#define HSMCI_IER_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IER) Receive Buffer Full Interrupt Enable */ -#define HSMCI_IER_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IER) Transmit Buffer Empty Interrupt Enable */ -#define HSMCI_IER_RINDE (0x1 << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */ -#define HSMCI_IER_RDIRE (0x1 << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */ -#define HSMCI_IER_RCRCE (0x1 << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */ -#define HSMCI_IER_RENDE (0x1 << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */ -#define HSMCI_IER_RTOE (0x1 << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */ -#define HSMCI_IER_DCRCE (0x1 << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */ -#define HSMCI_IER_DTOE (0x1 << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */ -#define HSMCI_IER_CSTOE (0x1 << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */ -#define HSMCI_IER_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */ -#define HSMCI_IER_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */ -#define HSMCI_IER_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */ -#define HSMCI_IER_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */ -#define HSMCI_IER_OVRE (0x1 << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */ -#define HSMCI_IER_UNRE (0x1 << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */ -/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */ -#define HSMCI_IDR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */ -#define HSMCI_IDR_RXRDY (0x1 << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */ -#define HSMCI_IDR_TXRDY (0x1 << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */ -#define HSMCI_IDR_BLKE (0x1 << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */ -#define HSMCI_IDR_DTIP (0x1 << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */ -#define HSMCI_IDR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */ -#define HSMCI_IDR_ENDRX (0x1 << 6) /**< \brief (HSMCI_IDR) End of Receive Buffer Interrupt Disable */ -#define HSMCI_IDR_ENDTX (0x1 << 7) /**< \brief (HSMCI_IDR) End of Transmit Buffer Interrupt Disable */ -#define HSMCI_IDR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */ -#define HSMCI_IDR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */ -#define HSMCI_IDR_CSRCV (0x1 << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */ -#define HSMCI_IDR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IDR) Receive Buffer Full Interrupt Disable */ -#define HSMCI_IDR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IDR) Transmit Buffer Empty Interrupt Disable */ -#define HSMCI_IDR_RINDE (0x1 << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */ -#define HSMCI_IDR_RDIRE (0x1 << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */ -#define HSMCI_IDR_RCRCE (0x1 << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */ -#define HSMCI_IDR_RENDE (0x1 << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */ -#define HSMCI_IDR_RTOE (0x1 << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */ -#define HSMCI_IDR_DCRCE (0x1 << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */ -#define HSMCI_IDR_DTOE (0x1 << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */ -#define HSMCI_IDR_CSTOE (0x1 << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */ -#define HSMCI_IDR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */ -#define HSMCI_IDR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */ -#define HSMCI_IDR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */ -#define HSMCI_IDR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */ -#define HSMCI_IDR_OVRE (0x1 << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */ -#define HSMCI_IDR_UNRE (0x1 << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */ -/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */ -#define HSMCI_IMR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */ -#define HSMCI_IMR_RXRDY (0x1 << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */ -#define HSMCI_IMR_TXRDY (0x1 << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */ -#define HSMCI_IMR_BLKE (0x1 << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */ -#define HSMCI_IMR_DTIP (0x1 << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */ -#define HSMCI_IMR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */ -#define HSMCI_IMR_ENDRX (0x1 << 6) /**< \brief (HSMCI_IMR) End of Receive Buffer Interrupt Mask */ -#define HSMCI_IMR_ENDTX (0x1 << 7) /**< \brief (HSMCI_IMR) End of Transmit Buffer Interrupt Mask */ -#define HSMCI_IMR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */ -#define HSMCI_IMR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */ -#define HSMCI_IMR_CSRCV (0x1 << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */ -#define HSMCI_IMR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IMR) Receive Buffer Full Interrupt Mask */ -#define HSMCI_IMR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IMR) Transmit Buffer Empty Interrupt Mask */ -#define HSMCI_IMR_RINDE (0x1 << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */ -#define HSMCI_IMR_RDIRE (0x1 << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */ -#define HSMCI_IMR_RCRCE (0x1 << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */ -#define HSMCI_IMR_RENDE (0x1 << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */ -#define HSMCI_IMR_RTOE (0x1 << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */ -#define HSMCI_IMR_DCRCE (0x1 << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */ -#define HSMCI_IMR_DTOE (0x1 << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */ -#define HSMCI_IMR_CSTOE (0x1 << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */ -#define HSMCI_IMR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */ -#define HSMCI_IMR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */ -#define HSMCI_IMR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */ -#define HSMCI_IMR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */ -#define HSMCI_IMR_OVRE (0x1 << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */ -#define HSMCI_IMR_UNRE (0x1 << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */ -/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */ -#define HSMCI_CFG_FIFOMODE (0x1 << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */ -#define HSMCI_CFG_FERRCTRL (0x1 << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */ -#define HSMCI_CFG_HSMODE (0x1 << 8) /**< \brief (HSMCI_CFG) High Speed Mode */ -#define HSMCI_CFG_LSYNC (0x1 << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */ -/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */ -#define HSMCI_WPMR_WP_EN (0x1 << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */ -#define HSMCI_WPMR_WP_KEY (0xffffff << 8) /**< \brief (HSMCI_WPMR) Write Protection Key password */ -/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */ -#define HSMCI_WPSR_WP_VS (0xf << 0) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */ -#define HSMCI_WPSR_WP_VSRC (0xffff << 8) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */ -/* -------- HSMCI_RPR : (HSMCI Offset: 0x100) Receive Pointer Register -------- */ -#define HSMCI_RPR_RXPTR (0xffffffff << 0) /**< \brief (HSMCI_RPR) Receive Pointer Register */ -/* -------- HSMCI_RCR : (HSMCI Offset: 0x104) Receive Counter Register -------- */ -#define HSMCI_RCR_RXCTR (0xffff << 0) /**< \brief (HSMCI_RCR) Receive Counter Register */ -/* -------- HSMCI_TPR : (HSMCI Offset: 0x108) Transmit Pointer Register -------- */ -#define HSMCI_TPR_TXPTR (0xffffffff << 0) /**< \brief (HSMCI_TPR) Transmit Counter Register */ -/* -------- HSMCI_TCR : (HSMCI Offset: 0x10C) Transmit Counter Register -------- */ -#define HSMCI_TCR_TXCTR (0xffff << 0) /**< \brief (HSMCI_TCR) Transmit Counter Register */ -/* -------- HSMCI_RNPR : (HSMCI Offset: 0x110) Receive Next Pointer Register -------- */ -#define HSMCI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (HSMCI_RNPR) Receive Next Pointer */ -/* -------- HSMCI_RNCR : (HSMCI Offset: 0x114) Receive Next Counter Register -------- */ -#define HSMCI_RNCR_RXNCTR (0xffff << 0) /**< \brief (HSMCI_RNCR) Receive Next Counter */ -/* -------- HSMCI_TNPR : (HSMCI Offset: 0x118) Transmit Next Pointer Register -------- */ -#define HSMCI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (HSMCI_TNPR) Transmit Next Pointer */ -/* -------- HSMCI_TNCR : (HSMCI Offset: 0x11C) Transmit Next Counter Register -------- */ -#define HSMCI_TNCR_TXNCTR (0xffff << 0) /**< \brief (HSMCI_TNCR) Transmit Counter Next */ -/* -------- HSMCI_PTCR : (HSMCI Offset: 0x120) Transfer Control Register -------- */ -#define HSMCI_PTCR_RXTEN (0x1 << 0) /**< \brief (HSMCI_PTCR) Receiver Transfer Enable */ -#define HSMCI_PTCR_RXTDIS (0x1 << 1) /**< \brief (HSMCI_PTCR) Receiver Transfer Disable */ -#define HSMCI_PTCR_TXTEN (0x1 << 8) /**< \brief (HSMCI_PTCR) Transmitter Transfer Enable */ -#define HSMCI_PTCR_TXTDIS (0x1 << 9) /**< \brief (HSMCI_PTCR) Transmitter Transfer Disable */ -/* -------- HSMCI_PTSR : (HSMCI Offset: 0x124) Transfer Status Register -------- */ -#define HSMCI_PTSR_RXTEN (0x1 << 0) /**< \brief (HSMCI_PTSR) Receiver Transfer Enable */ -#define HSMCI_PTSR_TXTEN (0x1 << 8) /**< \brief (HSMCI_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_MATRIX AHB Bus Matrix */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Matrix hardware registers */ -typedef struct { - RwReg MATRIX_MCFG[4]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */ - RwReg Reserved1[12]; - RwReg MATRIX_SCFG[5]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */ - RwReg Reserved2[11]; - RwReg MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */ - RwReg Reserved3[1]; - RwReg MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */ - RwReg Reserved4[1]; - RwReg MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */ - RwReg Reserved5[1]; - RwReg MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */ - RwReg Reserved6[1]; - RwReg MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */ - RwReg Reserved7[28]; - RwReg CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System IO Configuration register */ - RwReg Reserved8[1]; - RwReg CCFG_SMCNFCS; /**< \brief (Matrix Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register */ - RwReg Reserved9[49]; - RwReg MATRIX_WPMR; /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */ - RoReg MATRIX_WPSR; /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */ -} Matrix; -#endif /* __ASSEMBLY__ */ -/* -------- MATRIX_MCFG[4] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */ -#define MATRIX_MCFG_ULBT (0x7 << 0) /**< \brief (MATRIX_MCFG[4]) Undefined Length Burst Type */ -/* -------- MATRIX_SCFG[5] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ -#define MATRIX_SCFG_SLOT_CYCLE (0xff << 0) /**< \brief (MATRIX_SCFG[5]) Maximum Number of Allowed Cycles for a Burst */ -#define MATRIX_SCFG_DEFMSTR_TYPE (0x3 << 16) /**< \brief (MATRIX_SCFG[5]) Default Master Type */ -#define MATRIX_SCFG_FIXED_DEFMSTR (0x7 << 18) /**< \brief (MATRIX_SCFG[5]) Fixed Default Master */ -#define MATRIX_SCFG_ARBT (0x3 << 24) /**< \brief (MATRIX_SCFG[5]) Arbitration Type */ -/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */ -#define MATRIX_PRAS0_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS0) Master 0 Priority */ -#define MATRIX_PRAS0_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS0) Master 1 Priority */ -#define MATRIX_PRAS0_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS0) Master 2 Priority */ -#define MATRIX_PRAS0_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS0) Master 3 Priority */ -#define MATRIX_PRAS0_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS0) Master 4 Priority */ -/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */ -#define MATRIX_PRAS1_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS1) Master 0 Priority */ -#define MATRIX_PRAS1_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS1) Master 1 Priority */ -#define MATRIX_PRAS1_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS1) Master 2 Priority */ -#define MATRIX_PRAS1_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS1) Master 3 Priority */ -#define MATRIX_PRAS1_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS1) Master 4 Priority */ -/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */ -#define MATRIX_PRAS2_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS2) Master 0 Priority */ -#define MATRIX_PRAS2_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS2) Master 1 Priority */ -#define MATRIX_PRAS2_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS2) Master 2 Priority */ -#define MATRIX_PRAS2_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS2) Master 3 Priority */ -#define MATRIX_PRAS2_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS2) Master 4 Priority */ -/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */ -#define MATRIX_PRAS3_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS3) Master 0 Priority */ -#define MATRIX_PRAS3_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS3) Master 1 Priority */ -#define MATRIX_PRAS3_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS3) Master 2 Priority */ -#define MATRIX_PRAS3_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS3) Master 3 Priority */ -#define MATRIX_PRAS3_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS3) Master 4 Priority */ -/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */ -#define MATRIX_PRAS4_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS4) Master 0 Priority */ -#define MATRIX_PRAS4_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS4) Master 1 Priority */ -#define MATRIX_PRAS4_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS4) Master 2 Priority */ -#define MATRIX_PRAS4_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS4) Master 3 Priority */ -#define MATRIX_PRAS4_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS4) Master 4 Priority */ -/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System IO Configuration register -------- */ -#define CCFG_SYSIO_SYSIO4 (0x1 << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */ -#define CCFG_SYSIO_SYSIO5 (0x1 << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */ -#define CCFG_SYSIO_SYSIO6 (0x1 << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */ -#define CCFG_SYSIO_SYSIO7 (0x1 << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */ -#define CCFG_SYSIO_SYSIO10 (0x1 << 10) /**< \brief (CCFG_SYSIO) PB10 or DDM Assignment */ -#define CCFG_SYSIO_SYSIO11 (0x1 << 11) /**< \brief (CCFG_SYSIO) PB11 or DDP Assignment */ -#define CCFG_SYSIO_SYSIO12 (0x1 << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */ -/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register -------- */ -#define CCFG_SMCNFCS_SMC_NFCS0 (0x1 << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */ -#define CCFG_SMCNFCS_SMC_NFCS1 (0x1 << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */ -#define CCFG_SMCNFCS_SMC_NFCS2 (0x1 << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */ -#define CCFG_SMCNFCS_SMC_NFCS3 (0x1 << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */ -/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */ -#define MATRIX_WPMR_WPEN (0x1 << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */ -#define MATRIX_WPMR_WPKEY (0xffffff << 8) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */ -/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */ -#define MATRIX_WPSR_WPVS (0x1 << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */ -#define MATRIX_WPSR_WPVSRC (0xffff << 8) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_PDC Peripheral DMA Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Pdc hardware registers */ -typedef struct { - RwReg Reserved1[64]; - RwReg PERIPH_RPR; /**< \brief (Pdc Offset: 0x100) Receive Pointer Register */ - RwReg PERIPH_RCR; /**< \brief (Pdc Offset: 0x104) Receive Counter Register */ - RwReg PERIPH_TPR; /**< \brief (Pdc Offset: 0x108) Transmit Pointer Register */ - RwReg PERIPH_TCR; /**< \brief (Pdc Offset: 0x10C) Transmit Counter Register */ - RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x110) Receive Next Pointer Register */ - RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x114) Receive Next Counter Register */ - RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x118) Transmit Next Pointer Register */ - RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x11C) Transmit Next Counter Register */ - WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x120) Transfer Control Register */ - RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x124) Transfer Status Register */ -} Pdc; -#endif /* __ASSEMBLY__ */ -/* -------- PERIPH_RPR : (PDC Offset: 0x100) Receive Pointer Register -------- */ -#define PERIPH_RPR_RXPTR (0xffffffff << 0) /**< \brief (PERIPH_RPR) Receive Pointer Register */ -/* -------- PERIPH_RCR : (PDC Offset: 0x104) Receive Counter Register -------- */ -#define PERIPH_RCR_RXCTR (0xffff << 0) /**< \brief (PERIPH_RCR) Receive Counter Register */ -/* -------- PERIPH_TPR : (PDC Offset: 0x108) Transmit Pointer Register -------- */ -#define PERIPH_TPR_TXPTR (0xffffffff << 0) /**< \brief (PERIPH_TPR) Transmit Counter Register */ -/* -------- PERIPH_TCR : (PDC Offset: 0x10C) Transmit Counter Register -------- */ -#define PERIPH_TCR_TXCTR (0xffff << 0) /**< \brief (PERIPH_TCR) Transmit Counter Register */ -/* -------- PERIPH_RNPR : (PDC Offset: 0x110) Receive Next Pointer Register -------- */ -#define PERIPH_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (PERIPH_RNPR) Receive Next Pointer */ -/* -------- PERIPH_RNCR : (PDC Offset: 0x114) Receive Next Counter Register -------- */ -#define PERIPH_RNCR_RXNCTR (0xffff << 0) /**< \brief (PERIPH_RNCR) Receive Next Counter */ -/* -------- PERIPH_TNPR : (PDC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define PERIPH_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */ -/* -------- PERIPH_TNCR : (PDC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define PERIPH_TNCR_TXNCTR (0xffff << 0) /**< \brief (PERIPH_TNCR) Transmit Counter Next */ -/* -------- PERIPH_PTCR : (PDC Offset: 0x120) Transfer Control Register -------- */ -#define PERIPH_PTCR_RXTEN (0x1 << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */ -#define PERIPH_PTCR_RXTDIS (0x1 << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */ -#define PERIPH_PTCR_TXTEN (0x1 << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */ -#define PERIPH_PTCR_TXTDIS (0x1 << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */ -/* -------- PERIPH_PTSR : (PDC Offset: 0x124) Transfer Status Register -------- */ -#define PERIPH_PTSR_RXTEN (0x1 << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */ -#define PERIPH_PTSR_TXTEN (0x1 << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Parallel Input/Output */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_PIO Parallel Input/Output */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Pio hardware registers */ -typedef struct { - WoReg PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */ - WoReg PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */ - RoReg PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */ - RwReg Reserved1[1]; - WoReg PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */ - WoReg PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */ - RoReg PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */ - RwReg Reserved2[1]; - WoReg PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ - WoReg PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ - RoReg PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */ - RwReg Reserved3[1]; - WoReg PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */ - WoReg PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */ - RwReg PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */ - RoReg PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */ - WoReg PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */ - WoReg PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */ - RoReg PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */ - RoReg PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */ - WoReg PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */ - WoReg PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */ - RoReg PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */ - RwReg Reserved4[1]; - WoReg PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */ - WoReg PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */ - RoReg PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */ - RwReg Reserved5[1]; - RwReg PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */ - RwReg Reserved6[2]; - WoReg PIO_SCIFSR; /**< \brief (Pio Offset: 0x0080) System Clock Glitch Input Filter Select Register */ - WoReg PIO_DIFSR; /**< \brief (Pio Offset: 0x0084) Debouncing Input Filter Select Register */ - RoReg PIO_IFDGSR; /**< \brief (Pio Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register */ - RwReg PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ - WoReg PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */ - WoReg PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */ - RoReg PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */ - RwReg Reserved7[1]; - WoReg PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */ - WoReg PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */ - RoReg PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */ - RwReg Reserved8[1]; - WoReg PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ - WoReg PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */ - RoReg PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ - RwReg Reserved9[1]; - WoReg PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */ - WoReg PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */ - RoReg PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */ - RwReg Reserved10[1]; - WoReg PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */ - WoReg PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */ - RoReg PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ - RwReg Reserved11[1]; - RoReg PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */ - RwReg PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */ - RoReg PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */ - RwReg Reserved12[5]; - RwReg PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */ - RwReg Reserved13[19]; - RwReg PIO_PCMR; /**< \brief (Pio Offset: 0x150) Parallel Capture Mode Register */ - WoReg PIO_PCIER; /**< \brief (Pio Offset: 0x154) Parallel Capture Interrupt Enable Register */ - WoReg PIO_PCIDR; /**< \brief (Pio Offset: 0x158) Parallel Capture Interrupt Disable Register */ - RoReg PIO_PCIMR; /**< \brief (Pio Offset: 0x15C) Parallel Capture Interrupt Mask Register */ - RoReg PIO_PCISR; /**< \brief (Pio Offset: 0x160) Parallel Capture Interrupt Status Register */ - RoReg PIO_PCRHR; /**< \brief (Pio Offset: 0x164) Parallel Capture Reception Holding Register */ - RwReg Reserved14[38]; -} Pio; -#endif /* __ASSEMBLY__ */ -/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ -#define PIO_PER_P0 (0x1 << 0) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P1 (0x1 << 1) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P2 (0x1 << 2) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P3 (0x1 << 3) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P4 (0x1 << 4) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P5 (0x1 << 5) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P6 (0x1 << 6) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P7 (0x1 << 7) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P8 (0x1 << 8) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P9 (0x1 << 9) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P10 (0x1 << 10) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P11 (0x1 << 11) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P12 (0x1 << 12) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P13 (0x1 << 13) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P14 (0x1 << 14) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P15 (0x1 << 15) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P16 (0x1 << 16) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P17 (0x1 << 17) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P18 (0x1 << 18) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P19 (0x1 << 19) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P20 (0x1 << 20) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P21 (0x1 << 21) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P22 (0x1 << 22) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P23 (0x1 << 23) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P24 (0x1 << 24) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P25 (0x1 << 25) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P26 (0x1 << 26) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P27 (0x1 << 27) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P28 (0x1 << 28) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P29 (0x1 << 29) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P30 (0x1 << 30) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P31 (0x1 << 31) /**< \brief (PIO_PER) PIO Enable */ -/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ -#define PIO_PDR_P0 (0x1 << 0) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P1 (0x1 << 1) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P2 (0x1 << 2) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P3 (0x1 << 3) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P4 (0x1 << 4) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P5 (0x1 << 5) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P6 (0x1 << 6) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P7 (0x1 << 7) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P8 (0x1 << 8) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P9 (0x1 << 9) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P10 (0x1 << 10) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P11 (0x1 << 11) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P12 (0x1 << 12) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P13 (0x1 << 13) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P14 (0x1 << 14) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P15 (0x1 << 15) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P16 (0x1 << 16) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P17 (0x1 << 17) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P18 (0x1 << 18) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P19 (0x1 << 19) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P20 (0x1 << 20) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P21 (0x1 << 21) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P22 (0x1 << 22) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P23 (0x1 << 23) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P24 (0x1 << 24) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P25 (0x1 << 25) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P26 (0x1 << 26) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P27 (0x1 << 27) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P28 (0x1 << 28) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P29 (0x1 << 29) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P30 (0x1 << 30) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P31 (0x1 << 31) /**< \brief (PIO_PDR) PIO Disable */ -/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ -#define PIO_PSR_P0 (0x1 << 0) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P1 (0x1 << 1) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P2 (0x1 << 2) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P3 (0x1 << 3) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P4 (0x1 << 4) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P5 (0x1 << 5) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P6 (0x1 << 6) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P7 (0x1 << 7) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P8 (0x1 << 8) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P9 (0x1 << 9) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P10 (0x1 << 10) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P11 (0x1 << 11) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P12 (0x1 << 12) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P13 (0x1 << 13) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P14 (0x1 << 14) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P15 (0x1 << 15) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P16 (0x1 << 16) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P17 (0x1 << 17) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P18 (0x1 << 18) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P19 (0x1 << 19) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P20 (0x1 << 20) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P21 (0x1 << 21) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P22 (0x1 << 22) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P23 (0x1 << 23) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P24 (0x1 << 24) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P25 (0x1 << 25) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P26 (0x1 << 26) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P27 (0x1 << 27) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P28 (0x1 << 28) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P29 (0x1 << 29) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P30 (0x1 << 30) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P31 (0x1 << 31) /**< \brief (PIO_PSR) PIO Status */ -/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ -#define PIO_OER_P0 (0x1 << 0) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P1 (0x1 << 1) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P2 (0x1 << 2) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P3 (0x1 << 3) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P4 (0x1 << 4) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P5 (0x1 << 5) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P6 (0x1 << 6) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P7 (0x1 << 7) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P8 (0x1 << 8) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P9 (0x1 << 9) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P10 (0x1 << 10) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P11 (0x1 << 11) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P12 (0x1 << 12) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P13 (0x1 << 13) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P14 (0x1 << 14) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P15 (0x1 << 15) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P16 (0x1 << 16) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P17 (0x1 << 17) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P18 (0x1 << 18) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P19 (0x1 << 19) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P20 (0x1 << 20) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P21 (0x1 << 21) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P22 (0x1 << 22) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P23 (0x1 << 23) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P24 (0x1 << 24) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P25 (0x1 << 25) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P26 (0x1 << 26) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P27 (0x1 << 27) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P28 (0x1 << 28) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P29 (0x1 << 29) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P30 (0x1 << 30) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P31 (0x1 << 31) /**< \brief (PIO_OER) Output Enable */ -/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ -#define PIO_ODR_P0 (0x1 << 0) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P1 (0x1 << 1) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P2 (0x1 << 2) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P3 (0x1 << 3) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P4 (0x1 << 4) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P5 (0x1 << 5) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P6 (0x1 << 6) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P7 (0x1 << 7) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P8 (0x1 << 8) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P9 (0x1 << 9) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P10 (0x1 << 10) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P11 (0x1 << 11) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P12 (0x1 << 12) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P13 (0x1 << 13) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P14 (0x1 << 14) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P15 (0x1 << 15) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P16 (0x1 << 16) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P17 (0x1 << 17) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P18 (0x1 << 18) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P19 (0x1 << 19) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P20 (0x1 << 20) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P21 (0x1 << 21) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P22 (0x1 << 22) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P23 (0x1 << 23) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P24 (0x1 << 24) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P25 (0x1 << 25) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P26 (0x1 << 26) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P27 (0x1 << 27) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P28 (0x1 << 28) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P29 (0x1 << 29) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P30 (0x1 << 30) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P31 (0x1 << 31) /**< \brief (PIO_ODR) Output Disable */ -/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ -#define PIO_OSR_P0 (0x1 << 0) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P1 (0x1 << 1) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P2 (0x1 << 2) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P3 (0x1 << 3) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P4 (0x1 << 4) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P5 (0x1 << 5) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P6 (0x1 << 6) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P7 (0x1 << 7) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P8 (0x1 << 8) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P9 (0x1 << 9) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P10 (0x1 << 10) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P11 (0x1 << 11) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P12 (0x1 << 12) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P13 (0x1 << 13) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P14 (0x1 << 14) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P15 (0x1 << 15) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P16 (0x1 << 16) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P17 (0x1 << 17) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P18 (0x1 << 18) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P19 (0x1 << 19) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P20 (0x1 << 20) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P21 (0x1 << 21) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P22 (0x1 << 22) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P23 (0x1 << 23) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P24 (0x1 << 24) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P25 (0x1 << 25) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P26 (0x1 << 26) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P27 (0x1 << 27) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P28 (0x1 << 28) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P29 (0x1 << 29) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P30 (0x1 << 30) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P31 (0x1 << 31) /**< \brief (PIO_OSR) Output Status */ -/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ -#define PIO_IFER_P0 (0x1 << 0) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P1 (0x1 << 1) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P2 (0x1 << 2) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P3 (0x1 << 3) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P4 (0x1 << 4) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P5 (0x1 << 5) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P6 (0x1 << 6) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P7 (0x1 << 7) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P8 (0x1 << 8) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P9 (0x1 << 9) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P10 (0x1 << 10) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P11 (0x1 << 11) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P12 (0x1 << 12) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P13 (0x1 << 13) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P14 (0x1 << 14) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P15 (0x1 << 15) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P16 (0x1 << 16) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P17 (0x1 << 17) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P18 (0x1 << 18) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P19 (0x1 << 19) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P20 (0x1 << 20) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P21 (0x1 << 21) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P22 (0x1 << 22) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P23 (0x1 << 23) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P24 (0x1 << 24) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P25 (0x1 << 25) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P26 (0x1 << 26) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P27 (0x1 << 27) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P28 (0x1 << 28) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P29 (0x1 << 29) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P30 (0x1 << 30) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P31 (0x1 << 31) /**< \brief (PIO_IFER) Input Filter Enable */ -/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ -#define PIO_IFDR_P0 (0x1 << 0) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P1 (0x1 << 1) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P2 (0x1 << 2) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P3 (0x1 << 3) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P4 (0x1 << 4) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P5 (0x1 << 5) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P6 (0x1 << 6) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P7 (0x1 << 7) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P8 (0x1 << 8) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P9 (0x1 << 9) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P10 (0x1 << 10) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P11 (0x1 << 11) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P12 (0x1 << 12) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P13 (0x1 << 13) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P14 (0x1 << 14) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P15 (0x1 << 15) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P16 (0x1 << 16) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P17 (0x1 << 17) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P18 (0x1 << 18) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P19 (0x1 << 19) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P20 (0x1 << 20) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P21 (0x1 << 21) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P22 (0x1 << 22) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P23 (0x1 << 23) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P24 (0x1 << 24) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P25 (0x1 << 25) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P26 (0x1 << 26) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P27 (0x1 << 27) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P28 (0x1 << 28) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P29 (0x1 << 29) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P30 (0x1 << 30) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P31 (0x1 << 31) /**< \brief (PIO_IFDR) Input Filter Disable */ -/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ -#define PIO_IFSR_P0 (0x1 << 0) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P1 (0x1 << 1) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P2 (0x1 << 2) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P3 (0x1 << 3) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P4 (0x1 << 4) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P5 (0x1 << 5) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P6 (0x1 << 6) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P7 (0x1 << 7) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P8 (0x1 << 8) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P9 (0x1 << 9) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P10 (0x1 << 10) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P11 (0x1 << 11) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P12 (0x1 << 12) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P13 (0x1 << 13) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P14 (0x1 << 14) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P15 (0x1 << 15) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P16 (0x1 << 16) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P17 (0x1 << 17) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P18 (0x1 << 18) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P19 (0x1 << 19) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P20 (0x1 << 20) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P21 (0x1 << 21) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P22 (0x1 << 22) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P23 (0x1 << 23) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P24 (0x1 << 24) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P25 (0x1 << 25) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P26 (0x1 << 26) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P27 (0x1 << 27) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P28 (0x1 << 28) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P29 (0x1 << 29) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P30 (0x1 << 30) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P31 (0x1 << 31) /**< \brief (PIO_IFSR) Input Filer Status */ -/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ -#define PIO_SODR_P0 (0x1 << 0) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P1 (0x1 << 1) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P2 (0x1 << 2) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P3 (0x1 << 3) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P4 (0x1 << 4) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P5 (0x1 << 5) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P6 (0x1 << 6) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P7 (0x1 << 7) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P8 (0x1 << 8) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P9 (0x1 << 9) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P10 (0x1 << 10) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P11 (0x1 << 11) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P12 (0x1 << 12) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P13 (0x1 << 13) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P14 (0x1 << 14) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P15 (0x1 << 15) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P16 (0x1 << 16) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P17 (0x1 << 17) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P18 (0x1 << 18) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P19 (0x1 << 19) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P20 (0x1 << 20) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P21 (0x1 << 21) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P22 (0x1 << 22) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P23 (0x1 << 23) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P24 (0x1 << 24) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P25 (0x1 << 25) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P26 (0x1 << 26) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P27 (0x1 << 27) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P28 (0x1 << 28) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P29 (0x1 << 29) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P30 (0x1 << 30) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P31 (0x1 << 31) /**< \brief (PIO_SODR) Set Output Data */ -/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ -#define PIO_CODR_P0 (0x1 << 0) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P1 (0x1 << 1) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P2 (0x1 << 2) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P3 (0x1 << 3) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P4 (0x1 << 4) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P5 (0x1 << 5) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P6 (0x1 << 6) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P7 (0x1 << 7) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P8 (0x1 << 8) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P9 (0x1 << 9) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P10 (0x1 << 10) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P11 (0x1 << 11) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P12 (0x1 << 12) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P13 (0x1 << 13) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P14 (0x1 << 14) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P15 (0x1 << 15) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P16 (0x1 << 16) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P17 (0x1 << 17) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P18 (0x1 << 18) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P19 (0x1 << 19) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P20 (0x1 << 20) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P21 (0x1 << 21) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P22 (0x1 << 22) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P23 (0x1 << 23) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P24 (0x1 << 24) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P25 (0x1 << 25) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P26 (0x1 << 26) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P27 (0x1 << 27) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P28 (0x1 << 28) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P29 (0x1 << 29) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P30 (0x1 << 30) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P31 (0x1 << 31) /**< \brief (PIO_CODR) Clear Output Data */ -/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ -#define PIO_ODSR_P0 (0x1 << 0) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P1 (0x1 << 1) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P2 (0x1 << 2) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P3 (0x1 << 3) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P4 (0x1 << 4) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P5 (0x1 << 5) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P6 (0x1 << 6) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P7 (0x1 << 7) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P8 (0x1 << 8) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P9 (0x1 << 9) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P10 (0x1 << 10) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P11 (0x1 << 11) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P12 (0x1 << 12) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P13 (0x1 << 13) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P14 (0x1 << 14) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P15 (0x1 << 15) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P16 (0x1 << 16) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P17 (0x1 << 17) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P18 (0x1 << 18) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P19 (0x1 << 19) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P20 (0x1 << 20) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P21 (0x1 << 21) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P22 (0x1 << 22) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P23 (0x1 << 23) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P24 (0x1 << 24) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P25 (0x1 << 25) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P26 (0x1 << 26) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P27 (0x1 << 27) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P28 (0x1 << 28) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P29 (0x1 << 29) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P30 (0x1 << 30) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P31 (0x1 << 31) /**< \brief (PIO_ODSR) Output Data Status */ -/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ -#define PIO_PDSR_P0 (0x1 << 0) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P1 (0x1 << 1) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P2 (0x1 << 2) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P3 (0x1 << 3) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P4 (0x1 << 4) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P5 (0x1 << 5) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P6 (0x1 << 6) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P7 (0x1 << 7) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P8 (0x1 << 8) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P9 (0x1 << 9) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P10 (0x1 << 10) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P11 (0x1 << 11) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P12 (0x1 << 12) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P13 (0x1 << 13) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P14 (0x1 << 14) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P15 (0x1 << 15) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P16 (0x1 << 16) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P17 (0x1 << 17) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P18 (0x1 << 18) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P19 (0x1 << 19) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P20 (0x1 << 20) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P21 (0x1 << 21) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P22 (0x1 << 22) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P23 (0x1 << 23) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P24 (0x1 << 24) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P25 (0x1 << 25) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P26 (0x1 << 26) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P27 (0x1 << 27) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P28 (0x1 << 28) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P29 (0x1 << 29) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P30 (0x1 << 30) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P31 (0x1 << 31) /**< \brief (PIO_PDSR) Output Data Status */ -/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ -#define PIO_IER_P0 (0x1 << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P1 (0x1 << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P2 (0x1 << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P3 (0x1 << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P4 (0x1 << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P5 (0x1 << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P6 (0x1 << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P7 (0x1 << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P8 (0x1 << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P9 (0x1 << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P10 (0x1 << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P11 (0x1 << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P12 (0x1 << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P13 (0x1 << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P14 (0x1 << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P15 (0x1 << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P16 (0x1 << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P17 (0x1 << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P18 (0x1 << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P19 (0x1 << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P20 (0x1 << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P21 (0x1 << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P22 (0x1 << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P23 (0x1 << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P24 (0x1 << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P25 (0x1 << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P26 (0x1 << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P27 (0x1 << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P28 (0x1 << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P29 (0x1 << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P30 (0x1 << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P31 (0x1 << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ -#define PIO_IDR_P0 (0x1 << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P1 (0x1 << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P2 (0x1 << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P3 (0x1 << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P4 (0x1 << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P5 (0x1 << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P6 (0x1 << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P7 (0x1 << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P8 (0x1 << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P9 (0x1 << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P10 (0x1 << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P11 (0x1 << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P12 (0x1 << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P13 (0x1 << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P14 (0x1 << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P15 (0x1 << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P16 (0x1 << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P17 (0x1 << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P18 (0x1 << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P19 (0x1 << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P20 (0x1 << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P21 (0x1 << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P22 (0x1 << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P23 (0x1 << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P24 (0x1 << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P25 (0x1 << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P26 (0x1 << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P27 (0x1 << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P28 (0x1 << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P29 (0x1 << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P30 (0x1 << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P31 (0x1 << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ -#define PIO_IMR_P0 (0x1 << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P1 (0x1 << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P2 (0x1 << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P3 (0x1 << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P4 (0x1 << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P5 (0x1 << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P6 (0x1 << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P7 (0x1 << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P8 (0x1 << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P9 (0x1 << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P10 (0x1 << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P11 (0x1 << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P12 (0x1 << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P13 (0x1 << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P14 (0x1 << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P15 (0x1 << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P16 (0x1 << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P17 (0x1 << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P18 (0x1 << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P19 (0x1 << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P20 (0x1 << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P21 (0x1 << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P22 (0x1 << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P23 (0x1 << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P24 (0x1 << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P25 (0x1 << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P26 (0x1 << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P27 (0x1 << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P28 (0x1 << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P29 (0x1 << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P30 (0x1 << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P31 (0x1 << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ -#define PIO_ISR_P0 (0x1 << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P1 (0x1 << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P2 (0x1 << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P3 (0x1 << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P4 (0x1 << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P5 (0x1 << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P6 (0x1 << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P7 (0x1 << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P8 (0x1 << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P9 (0x1 << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P10 (0x1 << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P11 (0x1 << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P12 (0x1 << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P13 (0x1 << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P14 (0x1 << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P15 (0x1 << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P16 (0x1 << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P17 (0x1 << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P18 (0x1 << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P19 (0x1 << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P20 (0x1 << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P21 (0x1 << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P22 (0x1 << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P23 (0x1 << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P24 (0x1 << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P25 (0x1 << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P26 (0x1 << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P27 (0x1 << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P28 (0x1 << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P29 (0x1 << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P30 (0x1 << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P31 (0x1 << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ -#define PIO_MDER_P0 (0x1 << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P1 (0x1 << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P2 (0x1 << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P3 (0x1 << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P4 (0x1 << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P5 (0x1 << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P6 (0x1 << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P7 (0x1 << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P8 (0x1 << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P9 (0x1 << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P10 (0x1 << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P11 (0x1 << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P12 (0x1 << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P13 (0x1 << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P14 (0x1 << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P15 (0x1 << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P16 (0x1 << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P17 (0x1 << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P18 (0x1 << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P19 (0x1 << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P20 (0x1 << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P21 (0x1 << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P22 (0x1 << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P23 (0x1 << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P24 (0x1 << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P25 (0x1 << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P26 (0x1 << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P27 (0x1 << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P28 (0x1 << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P29 (0x1 << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P30 (0x1 << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P31 (0x1 << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */ -/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ -#define PIO_MDDR_P0 (0x1 << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P1 (0x1 << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P2 (0x1 << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P3 (0x1 << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P4 (0x1 << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P5 (0x1 << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P6 (0x1 << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P7 (0x1 << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P8 (0x1 << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P9 (0x1 << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P10 (0x1 << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P11 (0x1 << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P12 (0x1 << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P13 (0x1 << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P14 (0x1 << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P15 (0x1 << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P16 (0x1 << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P17 (0x1 << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P18 (0x1 << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P19 (0x1 << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P20 (0x1 << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P21 (0x1 << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P22 (0x1 << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P23 (0x1 << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P24 (0x1 << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P25 (0x1 << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P26 (0x1 << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P27 (0x1 << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P28 (0x1 << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P29 (0x1 << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P30 (0x1 << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P31 (0x1 << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ -#define PIO_MDSR_P0 (0x1 << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P1 (0x1 << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P2 (0x1 << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P3 (0x1 << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P4 (0x1 << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P5 (0x1 << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P6 (0x1 << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P7 (0x1 << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P8 (0x1 << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P9 (0x1 << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P10 (0x1 << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P11 (0x1 << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P12 (0x1 << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P13 (0x1 << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P14 (0x1 << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P15 (0x1 << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P16 (0x1 << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P17 (0x1 << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P18 (0x1 << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P19 (0x1 << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P20 (0x1 << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P21 (0x1 << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P22 (0x1 << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P23 (0x1 << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P24 (0x1 << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P25 (0x1 << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P26 (0x1 << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P27 (0x1 << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P28 (0x1 << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P29 (0x1 << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P30 (0x1 << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P31 (0x1 << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */ -/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ -#define PIO_PUDR_P0 (0x1 << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P1 (0x1 << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P2 (0x1 << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P3 (0x1 << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P4 (0x1 << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P5 (0x1 << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P6 (0x1 << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P7 (0x1 << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P8 (0x1 << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P9 (0x1 << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P10 (0x1 << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P11 (0x1 << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P12 (0x1 << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P13 (0x1 << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P14 (0x1 << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P15 (0x1 << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P16 (0x1 << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P17 (0x1 << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P18 (0x1 << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P19 (0x1 << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P20 (0x1 << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P21 (0x1 << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P22 (0x1 << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P23 (0x1 << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P24 (0x1 << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P25 (0x1 << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P26 (0x1 << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P27 (0x1 << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P28 (0x1 << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P29 (0x1 << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P30 (0x1 << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P31 (0x1 << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */ -/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ -#define PIO_PUER_P0 (0x1 << 0) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P1 (0x1 << 1) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P2 (0x1 << 2) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P3 (0x1 << 3) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P4 (0x1 << 4) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P5 (0x1 << 5) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P6 (0x1 << 6) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P7 (0x1 << 7) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P8 (0x1 << 8) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P9 (0x1 << 9) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P10 (0x1 << 10) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P11 (0x1 << 11) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P12 (0x1 << 12) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P13 (0x1 << 13) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P14 (0x1 << 14) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P15 (0x1 << 15) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P16 (0x1 << 16) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P17 (0x1 << 17) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P18 (0x1 << 18) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P19 (0x1 << 19) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P20 (0x1 << 20) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P21 (0x1 << 21) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P22 (0x1 << 22) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P23 (0x1 << 23) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P24 (0x1 << 24) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P25 (0x1 << 25) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P26 (0x1 << 26) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P27 (0x1 << 27) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P28 (0x1 << 28) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P29 (0x1 << 29) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P30 (0x1 << 30) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P31 (0x1 << 31) /**< \brief (PIO_PUER) Pull Up Enable. */ -/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ -#define PIO_PUSR_P0 (0x1 << 0) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P1 (0x1 << 1) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P2 (0x1 << 2) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P3 (0x1 << 3) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P4 (0x1 << 4) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P5 (0x1 << 5) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P6 (0x1 << 6) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P7 (0x1 << 7) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P8 (0x1 << 8) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P9 (0x1 << 9) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P10 (0x1 << 10) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P11 (0x1 << 11) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P12 (0x1 << 12) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P13 (0x1 << 13) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P14 (0x1 << 14) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P15 (0x1 << 15) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P16 (0x1 << 16) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P17 (0x1 << 17) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P18 (0x1 << 18) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P19 (0x1 << 19) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P20 (0x1 << 20) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P21 (0x1 << 21) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P22 (0x1 << 22) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P23 (0x1 << 23) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P24 (0x1 << 24) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P25 (0x1 << 25) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P26 (0x1 << 26) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P27 (0x1 << 27) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P28 (0x1 << 28) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P29 (0x1 << 29) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P30 (0x1 << 30) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P31 (0x1 << 31) /**< \brief (PIO_PUSR) Pull Up Status. */ -/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */ -#define PIO_ABCDSR_P0 (0x1 << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P1 (0x1 << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P2 (0x1 << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P3 (0x1 << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P4 (0x1 << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P5 (0x1 << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P6 (0x1 << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P7 (0x1 << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P8 (0x1 << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P9 (0x1 << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P10 (0x1 << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P11 (0x1 << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P12 (0x1 << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P13 (0x1 << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P14 (0x1 << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P15 (0x1 << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P16 (0x1 << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P17 (0x1 << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P18 (0x1 << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P19 (0x1 << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P20 (0x1 << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P21 (0x1 << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P22 (0x1 << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P23 (0x1 << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P24 (0x1 << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P25 (0x1 << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P26 (0x1 << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P27 (0x1 << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P28 (0x1 << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P29 (0x1 << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P30 (0x1 << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P31 (0x1 << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -/* -------- PIO_SCIFSR : (PIO Offset: 0x0080) System Clock Glitch Input Filter Select Register -------- */ -#define PIO_SCIFSR_P0 (0x1 << 0) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P1 (0x1 << 1) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P2 (0x1 << 2) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P3 (0x1 << 3) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P4 (0x1 << 4) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P5 (0x1 << 5) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P6 (0x1 << 6) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P7 (0x1 << 7) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P8 (0x1 << 8) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P9 (0x1 << 9) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P10 (0x1 << 10) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P11 (0x1 << 11) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P12 (0x1 << 12) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P13 (0x1 << 13) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P14 (0x1 << 14) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P15 (0x1 << 15) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P16 (0x1 << 16) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P17 (0x1 << 17) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P18 (0x1 << 18) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P19 (0x1 << 19) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P20 (0x1 << 20) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P21 (0x1 << 21) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P22 (0x1 << 22) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P23 (0x1 << 23) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P24 (0x1 << 24) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P25 (0x1 << 25) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P26 (0x1 << 26) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P27 (0x1 << 27) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P28 (0x1 << 28) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P29 (0x1 << 29) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P30 (0x1 << 30) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P31 (0x1 << 31) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -/* -------- PIO_DIFSR : (PIO Offset: 0x0084) Debouncing Input Filter Select Register -------- */ -#define PIO_DIFSR_P0 (0x1 << 0) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P1 (0x1 << 1) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P2 (0x1 << 2) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P3 (0x1 << 3) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P4 (0x1 << 4) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P5 (0x1 << 5) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P6 (0x1 << 6) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P7 (0x1 << 7) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P8 (0x1 << 8) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P9 (0x1 << 9) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P10 (0x1 << 10) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P11 (0x1 << 11) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P12 (0x1 << 12) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P13 (0x1 << 13) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P14 (0x1 << 14) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P15 (0x1 << 15) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P16 (0x1 << 16) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P17 (0x1 << 17) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P18 (0x1 << 18) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P19 (0x1 << 19) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P20 (0x1 << 20) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P21 (0x1 << 21) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P22 (0x1 << 22) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P23 (0x1 << 23) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P24 (0x1 << 24) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P25 (0x1 << 25) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P26 (0x1 << 26) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P27 (0x1 << 27) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P28 (0x1 << 28) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P29 (0x1 << 29) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P30 (0x1 << 30) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P31 (0x1 << 31) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -/* -------- PIO_IFDGSR : (PIO Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register -------- */ -#define PIO_IFDGSR_P0 (0x1 << 0) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P1 (0x1 << 1) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P2 (0x1 << 2) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P3 (0x1 << 3) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P4 (0x1 << 4) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P5 (0x1 << 5) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P6 (0x1 << 6) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P7 (0x1 << 7) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P8 (0x1 << 8) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P9 (0x1 << 9) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P10 (0x1 << 10) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P11 (0x1 << 11) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P12 (0x1 << 12) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P13 (0x1 << 13) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P14 (0x1 << 14) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P15 (0x1 << 15) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P16 (0x1 << 16) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P17 (0x1 << 17) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P18 (0x1 << 18) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P19 (0x1 << 19) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P20 (0x1 << 20) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P21 (0x1 << 21) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P22 (0x1 << 22) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P23 (0x1 << 23) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P24 (0x1 << 24) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P25 (0x1 << 25) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P26 (0x1 << 26) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P27 (0x1 << 27) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P28 (0x1 << 28) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P29 (0x1 << 29) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P30 (0x1 << 30) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P31 (0x1 << 31) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ -#define PIO_SCDR_DIV0 (0x1 << 0) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV1 (0x1 << 1) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV2 (0x1 << 2) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV3 (0x1 << 3) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV4 (0x1 << 4) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV5 (0x1 << 5) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV6 (0x1 << 6) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV7 (0x1 << 7) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV8 (0x1 << 8) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV9 (0x1 << 9) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV10 (0x1 << 10) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV11 (0x1 << 11) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV12 (0x1 << 12) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV13 (0x1 << 13) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */ -#define PIO_PPDDR_P0 (0x1 << 0) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P1 (0x1 << 1) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P2 (0x1 << 2) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P3 (0x1 << 3) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P4 (0x1 << 4) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P5 (0x1 << 5) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P6 (0x1 << 6) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P7 (0x1 << 7) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P8 (0x1 << 8) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P9 (0x1 << 9) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P10 (0x1 << 10) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P11 (0x1 << 11) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P12 (0x1 << 12) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P13 (0x1 << 13) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P14 (0x1 << 14) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P15 (0x1 << 15) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P16 (0x1 << 16) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P17 (0x1 << 17) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P18 (0x1 << 18) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P19 (0x1 << 19) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P20 (0x1 << 20) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P21 (0x1 << 21) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P22 (0x1 << 22) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P23 (0x1 << 23) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P24 (0x1 << 24) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P25 (0x1 << 25) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P26 (0x1 << 26) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P27 (0x1 << 27) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P28 (0x1 << 28) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P29 (0x1 << 29) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P30 (0x1 << 30) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P31 (0x1 << 31) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */ -#define PIO_PPDER_P0 (0x1 << 0) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P1 (0x1 << 1) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P2 (0x1 << 2) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P3 (0x1 << 3) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P4 (0x1 << 4) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P5 (0x1 << 5) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P6 (0x1 << 6) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P7 (0x1 << 7) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P8 (0x1 << 8) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P9 (0x1 << 9) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P10 (0x1 << 10) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P11 (0x1 << 11) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P12 (0x1 << 12) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P13 (0x1 << 13) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P14 (0x1 << 14) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P15 (0x1 << 15) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P16 (0x1 << 16) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P17 (0x1 << 17) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P18 (0x1 << 18) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P19 (0x1 << 19) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P20 (0x1 << 20) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P21 (0x1 << 21) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P22 (0x1 << 22) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P23 (0x1 << 23) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P24 (0x1 << 24) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P25 (0x1 << 25) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P26 (0x1 << 26) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P27 (0x1 << 27) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P28 (0x1 << 28) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P29 (0x1 << 29) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P30 (0x1 << 30) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P31 (0x1 << 31) /**< \brief (PIO_PPDER) Pull Down Enable. */ -/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */ -#define PIO_PPDSR_P0 (0x1 << 0) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P1 (0x1 << 1) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P2 (0x1 << 2) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P3 (0x1 << 3) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P4 (0x1 << 4) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P5 (0x1 << 5) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P6 (0x1 << 6) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P7 (0x1 << 7) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P8 (0x1 << 8) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P9 (0x1 << 9) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P10 (0x1 << 10) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P11 (0x1 << 11) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P12 (0x1 << 12) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P13 (0x1 << 13) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P14 (0x1 << 14) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P15 (0x1 << 15) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P16 (0x1 << 16) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P17 (0x1 << 17) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P18 (0x1 << 18) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P19 (0x1 << 19) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P20 (0x1 << 20) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P21 (0x1 << 21) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P22 (0x1 << 22) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P23 (0x1 << 23) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P24 (0x1 << 24) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P25 (0x1 << 25) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P26 (0x1 << 26) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P27 (0x1 << 27) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P28 (0x1 << 28) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P29 (0x1 << 29) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P30 (0x1 << 30) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P31 (0x1 << 31) /**< \brief (PIO_PPDSR) Pull Down Status. */ -/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ -#define PIO_OWER_P0 (0x1 << 0) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P1 (0x1 << 1) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P2 (0x1 << 2) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P3 (0x1 << 3) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P4 (0x1 << 4) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P5 (0x1 << 5) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P6 (0x1 << 6) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P7 (0x1 << 7) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P8 (0x1 << 8) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P9 (0x1 << 9) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P10 (0x1 << 10) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P11 (0x1 << 11) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P12 (0x1 << 12) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P13 (0x1 << 13) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P14 (0x1 << 14) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P15 (0x1 << 15) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P16 (0x1 << 16) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P17 (0x1 << 17) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P18 (0x1 << 18) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P19 (0x1 << 19) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P20 (0x1 << 20) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P21 (0x1 << 21) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P22 (0x1 << 22) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P23 (0x1 << 23) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P24 (0x1 << 24) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P25 (0x1 << 25) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P26 (0x1 << 26) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P27 (0x1 << 27) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P28 (0x1 << 28) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P29 (0x1 << 29) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P30 (0x1 << 30) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P31 (0x1 << 31) /**< \brief (PIO_OWER) Output Write Enable. */ -/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ -#define PIO_OWDR_P0 (0x1 << 0) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P1 (0x1 << 1) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P2 (0x1 << 2) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P3 (0x1 << 3) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P4 (0x1 << 4) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P5 (0x1 << 5) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P6 (0x1 << 6) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P7 (0x1 << 7) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P8 (0x1 << 8) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P9 (0x1 << 9) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P10 (0x1 << 10) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P11 (0x1 << 11) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P12 (0x1 << 12) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P13 (0x1 << 13) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P14 (0x1 << 14) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P15 (0x1 << 15) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P16 (0x1 << 16) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P17 (0x1 << 17) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P18 (0x1 << 18) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P19 (0x1 << 19) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P20 (0x1 << 20) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P21 (0x1 << 21) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P22 (0x1 << 22) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P23 (0x1 << 23) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P24 (0x1 << 24) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P25 (0x1 << 25) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P26 (0x1 << 26) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P27 (0x1 << 27) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P28 (0x1 << 28) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P29 (0x1 << 29) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P30 (0x1 << 30) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P31 (0x1 << 31) /**< \brief (PIO_OWDR) Output Write Disable. */ -/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ -#define PIO_OWSR_P0 (0x1 << 0) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P1 (0x1 << 1) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P2 (0x1 << 2) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P3 (0x1 << 3) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P4 (0x1 << 4) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P5 (0x1 << 5) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P6 (0x1 << 6) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P7 (0x1 << 7) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P8 (0x1 << 8) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P9 (0x1 << 9) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P10 (0x1 << 10) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P11 (0x1 << 11) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P12 (0x1 << 12) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P13 (0x1 << 13) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P14 (0x1 << 14) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P15 (0x1 << 15) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P16 (0x1 << 16) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P17 (0x1 << 17) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P18 (0x1 << 18) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P19 (0x1 << 19) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P20 (0x1 << 20) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P21 (0x1 << 21) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P22 (0x1 << 22) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P23 (0x1 << 23) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P24 (0x1 << 24) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P25 (0x1 << 25) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P26 (0x1 << 26) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P27 (0x1 << 27) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P28 (0x1 << 28) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P29 (0x1 << 29) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P30 (0x1 << 30) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P31 (0x1 << 31) /**< \brief (PIO_OWSR) Output Write Status. */ -/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ -#define PIO_AIMER_P0 (0x1 << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P1 (0x1 << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P2 (0x1 << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P3 (0x1 << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P4 (0x1 << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P5 (0x1 << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P6 (0x1 << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P7 (0x1 << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P8 (0x1 << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P9 (0x1 << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P10 (0x1 << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P11 (0x1 << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P12 (0x1 << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P13 (0x1 << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P14 (0x1 << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P15 (0x1 << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P16 (0x1 << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P17 (0x1 << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P18 (0x1 << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P19 (0x1 << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P20 (0x1 << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P21 (0x1 << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P22 (0x1 << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P23 (0x1 << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P24 (0x1 << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P25 (0x1 << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P26 (0x1 << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P27 (0x1 << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P28 (0x1 << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P29 (0x1 << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P30 (0x1 << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P31 (0x1 << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */ -#define PIO_AIMDR_P0 (0x1 << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P1 (0x1 << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P2 (0x1 << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P3 (0x1 << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P4 (0x1 << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P5 (0x1 << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P6 (0x1 << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P7 (0x1 << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P8 (0x1 << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P9 (0x1 << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P10 (0x1 << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P11 (0x1 << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P12 (0x1 << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P13 (0x1 << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P14 (0x1 << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P15 (0x1 << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P16 (0x1 << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P17 (0x1 << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P18 (0x1 << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P19 (0x1 << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P20 (0x1 << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P21 (0x1 << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P22 (0x1 << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P23 (0x1 << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P24 (0x1 << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P25 (0x1 << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P26 (0x1 << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P27 (0x1 << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P28 (0x1 << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P29 (0x1 << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P30 (0x1 << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P31 (0x1 << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ -#define PIO_AIMMR_P0 (0x1 << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P1 (0x1 << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P2 (0x1 << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P3 (0x1 << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P4 (0x1 << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P5 (0x1 << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P6 (0x1 << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P7 (0x1 << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P8 (0x1 << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P9 (0x1 << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P10 (0x1 << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P11 (0x1 << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P12 (0x1 << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P13 (0x1 << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P14 (0x1 << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P15 (0x1 << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P16 (0x1 << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P17 (0x1 << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P18 (0x1 << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P19 (0x1 << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P20 (0x1 << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P21 (0x1 << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P22 (0x1 << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P23 (0x1 << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P24 (0x1 << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P25 (0x1 << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P26 (0x1 << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P27 (0x1 << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P28 (0x1 << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P29 (0x1 << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P30 (0x1 << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P31 (0x1 << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ -#define PIO_ESR_P0 (0x1 << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P1 (0x1 << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P2 (0x1 << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P3 (0x1 << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P4 (0x1 << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P5 (0x1 << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P6 (0x1 << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P7 (0x1 << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P8 (0x1 << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P9 (0x1 << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P10 (0x1 << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P11 (0x1 << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P12 (0x1 << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P13 (0x1 << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P14 (0x1 << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P15 (0x1 << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P16 (0x1 << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P17 (0x1 << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P18 (0x1 << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P19 (0x1 << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P20 (0x1 << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P21 (0x1 << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P22 (0x1 << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P23 (0x1 << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P24 (0x1 << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P25 (0x1 << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P26 (0x1 << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P27 (0x1 << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P28 (0x1 << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P29 (0x1 << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P30 (0x1 << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P31 (0x1 << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ -#define PIO_LSR_P0 (0x1 << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P1 (0x1 << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P2 (0x1 << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P3 (0x1 << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P4 (0x1 << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P5 (0x1 << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P6 (0x1 << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P7 (0x1 << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P8 (0x1 << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P9 (0x1 << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P10 (0x1 << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P11 (0x1 << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P12 (0x1 << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P13 (0x1 << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P14 (0x1 << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P15 (0x1 << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P16 (0x1 << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P17 (0x1 << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P18 (0x1 << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P19 (0x1 << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P20 (0x1 << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P21 (0x1 << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P22 (0x1 << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P23 (0x1 << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P24 (0x1 << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P25 (0x1 << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P26 (0x1 << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P27 (0x1 << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P28 (0x1 << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P29 (0x1 << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P30 (0x1 << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P31 (0x1 << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ -#define PIO_ELSR_P0 (0x1 << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P1 (0x1 << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P2 (0x1 << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P3 (0x1 << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P4 (0x1 << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P5 (0x1 << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P6 (0x1 << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P7 (0x1 << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P8 (0x1 << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P9 (0x1 << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P10 (0x1 << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P11 (0x1 << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P12 (0x1 << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P13 (0x1 << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P14 (0x1 << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P15 (0x1 << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P16 (0x1 << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P17 (0x1 << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P18 (0x1 << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P19 (0x1 << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P20 (0x1 << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P21 (0x1 << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P22 (0x1 << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P23 (0x1 << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P24 (0x1 << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P25 (0x1 << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P26 (0x1 << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P27 (0x1 << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P28 (0x1 << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P29 (0x1 << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P30 (0x1 << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P31 (0x1 << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */ -#define PIO_FELLSR_P0 (0x1 << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P1 (0x1 << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P2 (0x1 << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P3 (0x1 << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P4 (0x1 << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P5 (0x1 << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P6 (0x1 << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P7 (0x1 << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P8 (0x1 << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P9 (0x1 << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P10 (0x1 << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P11 (0x1 << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P12 (0x1 << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P13 (0x1 << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P14 (0x1 << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P15 (0x1 << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P16 (0x1 << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P17 (0x1 << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P18 (0x1 << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P19 (0x1 << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P20 (0x1 << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P21 (0x1 << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P22 (0x1 << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P23 (0x1 << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P24 (0x1 << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P25 (0x1 << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P26 (0x1 << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P27 (0x1 << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P28 (0x1 << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P29 (0x1 << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P30 (0x1 << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P31 (0x1 << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */ -#define PIO_REHLSR_P0 (0x1 << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P1 (0x1 << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P2 (0x1 << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P3 (0x1 << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P4 (0x1 << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P5 (0x1 << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P6 (0x1 << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P7 (0x1 << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P8 (0x1 << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P9 (0x1 << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P10 (0x1 << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P11 (0x1 << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P12 (0x1 << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P13 (0x1 << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P14 (0x1 << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P15 (0x1 << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P16 (0x1 << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P17 (0x1 << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P18 (0x1 << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P19 (0x1 << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P20 (0x1 << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P21 (0x1 << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P22 (0x1 << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P23 (0x1 << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P24 (0x1 << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P25 (0x1 << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P26 (0x1 << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P27 (0x1 << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P28 (0x1 << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P29 (0x1 << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P30 (0x1 << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P31 (0x1 << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ -#define PIO_FRLHSR_P0 (0x1 << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P1 (0x1 << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P2 (0x1 << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P3 (0x1 << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P4 (0x1 << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P5 (0x1 << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P6 (0x1 << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P7 (0x1 << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P8 (0x1 << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P9 (0x1 << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P10 (0x1 << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P11 (0x1 << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P12 (0x1 << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P13 (0x1 << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P14 (0x1 << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P15 (0x1 << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P16 (0x1 << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P17 (0x1 << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P18 (0x1 << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P19 (0x1 << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P20 (0x1 << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P21 (0x1 << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P22 (0x1 << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P23 (0x1 << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P24 (0x1 << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P25 (0x1 << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P26 (0x1 << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P27 (0x1 << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P28 (0x1 << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P29 (0x1 << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P30 (0x1 << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P31 (0x1 << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */ -#define PIO_LOCKSR_P0 (0x1 << 0) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P1 (0x1 << 1) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P2 (0x1 << 2) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P3 (0x1 << 3) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P4 (0x1 << 4) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P5 (0x1 << 5) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P6 (0x1 << 6) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P7 (0x1 << 7) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P8 (0x1 << 8) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P9 (0x1 << 9) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P10 (0x1 << 10) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P11 (0x1 << 11) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P12 (0x1 << 12) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P13 (0x1 << 13) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P14 (0x1 << 14) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P15 (0x1 << 15) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P16 (0x1 << 16) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P17 (0x1 << 17) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P18 (0x1 << 18) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P19 (0x1 << 19) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P20 (0x1 << 20) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P21 (0x1 << 21) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P22 (0x1 << 22) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P23 (0x1 << 23) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P24 (0x1 << 24) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P25 (0x1 << 25) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P26 (0x1 << 26) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P27 (0x1 << 27) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P28 (0x1 << 28) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P29 (0x1 << 29) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P30 (0x1 << 30) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P31 (0x1 << 31) /**< \brief (PIO_LOCKSR) Lock Status. */ -/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */ -#define PIO_WPMR_WPEN (0x1 << 0) /**< \brief (PIO_WPMR) Write Protect Enable */ -#define PIO_WPMR_WPKEY (0xffffff << 8) /**< \brief (PIO_WPMR) Write Protect KEY */ -/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */ -#define PIO_WPSR_WPVS (0x1 << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */ -#define PIO_WPSR_WPVSRC (0xffff << 8) /**< \brief (PIO_WPSR) Write Protect Violation Source */ -/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */ -#define PIO_SCHMITT_SCHMITT0 (0x1 << 0) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT1 (0x1 << 1) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT2 (0x1 << 2) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT3 (0x1 << 3) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT4 (0x1 << 4) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT5 (0x1 << 5) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT6 (0x1 << 6) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT7 (0x1 << 7) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT8 (0x1 << 8) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT9 (0x1 << 9) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT10 (0x1 << 10) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT11 (0x1 << 11) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT12 (0x1 << 12) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT13 (0x1 << 13) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT14 (0x1 << 14) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT15 (0x1 << 15) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT16 (0x1 << 16) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT17 (0x1 << 17) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT18 (0x1 << 18) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT19 (0x1 << 19) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT20 (0x1 << 20) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT21 (0x1 << 21) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT22 (0x1 << 22) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT23 (0x1 << 23) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT24 (0x1 << 24) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT25 (0x1 << 25) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT26 (0x1 << 26) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT27 (0x1 << 27) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT28 (0x1 << 28) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT29 (0x1 << 29) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT30 (0x1 << 30) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT31 (0x1 << 31) /**< \brief (PIO_SCHMITT) */ -/* -------- PIO_PCMR : (PIO Offset: 0x150) Parallel Capture Mode Register -------- */ -#define PIO_PCMR_PCEN (0x1 << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */ -#define PIO_PCMR_DSIZE (0x3 << 4) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */ -#define PIO_PCMR_ALWYS (0x1 << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */ -#define PIO_PCMR_HALFS (0x1 << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */ -#define PIO_PCMR_FRSTS (0x1 << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */ -/* -------- PIO_PCIER : (PIO Offset: 0x154) Parallel Capture Interrupt Enable Register -------- */ -#define PIO_PCIER_DRDY (0x1 << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */ -#define PIO_PCIER_OVRE (0x1 << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */ -#define PIO_PCIER_ENDRX (0x1 << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */ -#define PIO_PCIER_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */ -/* -------- PIO_PCIDR : (PIO Offset: 0x158) Parallel Capture Interrupt Disable Register -------- */ -#define PIO_PCIDR_DRDY (0x1 << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */ -#define PIO_PCIDR_OVRE (0x1 << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */ -#define PIO_PCIDR_ENDRX (0x1 << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */ -#define PIO_PCIDR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */ -/* -------- PIO_PCIMR : (PIO Offset: 0x15C) Parallel Capture Interrupt Mask Register -------- */ -#define PIO_PCIMR_DRDY (0x1 << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */ -#define PIO_PCIMR_OVRE (0x1 << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */ -#define PIO_PCIMR_ENDRX (0x1 << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */ -#define PIO_PCIMR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */ -/* -------- PIO_PCISR : (PIO Offset: 0x160) Parallel Capture Interrupt Status Register -------- */ -#define PIO_PCISR_DRDY (0x1 << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */ -#define PIO_PCISR_OVRE (0x1 << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error. */ -#define PIO_PCISR_ENDRX (0x1 << 2) /**< \brief (PIO_PCISR) End of Reception Transfer. */ -#define PIO_PCISR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCISR) Reception Buffer Full */ -/* -------- PIO_PCRHR : (PIO Offset: 0x164) Parallel Capture Reception Holding Register -------- */ -#define PIO_PCRHR_RDATA (0xffffffff << 0) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data. */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Power Management Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_PMC Power Management Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Pmc hardware registers */ -typedef struct { - WoReg PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */ - WoReg PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */ - RoReg PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */ - RwReg Reserved1[1]; - WoReg PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */ - WoReg PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */ - RoReg PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */ - RwReg Reserved2[1]; - RwReg CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */ - RoReg CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */ - RwReg CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */ - RwReg CKGR_PLLBR; /**< \brief (Pmc Offset: 0x002C) PLLB Register */ - RwReg PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */ - RwReg Reserved3[1]; - RwReg PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */ - RwReg Reserved4[1]; - RwReg PMC_PCK[3]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */ - RwReg Reserved5[5]; - WoReg PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */ - WoReg PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */ - RoReg PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */ - RoReg PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */ - RwReg PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */ - RwReg PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */ - WoReg PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */ - RwReg Reserved6[26]; - RwReg PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */ - RoReg PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */ - RwReg Reserved7[5]; - WoReg PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */ - WoReg PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */ - RoReg PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */ - RwReg Reserved8[1]; - RwReg PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */ -} Pmc; -#endif /* __ASSEMBLY__ */ -/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ -#define PMC_SCER_UDP (0x1 << 7) /**< \brief (PMC_SCER) USB Device Port Clock Enable */ -#define PMC_SCER_PCK0 (0x1 << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */ -#define PMC_SCER_PCK1 (0x1 << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */ -#define PMC_SCER_PCK2 (0x1 << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */ -/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */ -#define PMC_SCDR_UDP (0x1 << 7) /**< \brief (PMC_SCDR) USB Device Port Clock Disable */ -#define PMC_SCDR_PCK0 (0x1 << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */ -#define PMC_SCDR_PCK1 (0x1 << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */ -#define PMC_SCDR_PCK2 (0x1 << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */ -/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */ -#define PMC_SCSR_UDP (0x1 << 7) /**< \brief (PMC_SCSR) USB Device Port Clock Status */ -#define PMC_SCSR_PCK0 (0x1 << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */ -#define PMC_SCSR_PCK1 (0x1 << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */ -#define PMC_SCSR_PCK2 (0x1 << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */ -/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */ -#define PMC_PCER0_PID2 (0x1 << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */ -#define PMC_PCER0_PID3 (0x1 << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */ -#define PMC_PCER0_PID4 (0x1 << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */ -#define PMC_PCER0_PID5 (0x1 << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */ -#define PMC_PCER0_PID6 (0x1 << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */ -#define PMC_PCER0_PID7 (0x1 << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */ -#define PMC_PCER0_PID8 (0x1 << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */ -#define PMC_PCER0_PID9 (0x1 << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */ -#define PMC_PCER0_PID10 (0x1 << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */ -#define PMC_PCER0_PID11 (0x1 << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */ -#define PMC_PCER0_PID12 (0x1 << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */ -#define PMC_PCER0_PID13 (0x1 << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */ -#define PMC_PCER0_PID14 (0x1 << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */ -#define PMC_PCER0_PID15 (0x1 << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */ -#define PMC_PCER0_PID16 (0x1 << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */ -#define PMC_PCER0_PID17 (0x1 << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */ -#define PMC_PCER0_PID18 (0x1 << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */ -#define PMC_PCER0_PID19 (0x1 << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */ -#define PMC_PCER0_PID20 (0x1 << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */ -#define PMC_PCER0_PID21 (0x1 << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */ -#define PMC_PCER0_PID22 (0x1 << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */ -#define PMC_PCER0_PID23 (0x1 << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */ -#define PMC_PCER0_PID24 (0x1 << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */ -#define PMC_PCER0_PID25 (0x1 << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */ -#define PMC_PCER0_PID26 (0x1 << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */ -#define PMC_PCER0_PID27 (0x1 << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */ -#define PMC_PCER0_PID28 (0x1 << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */ -#define PMC_PCER0_PID29 (0x1 << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */ -#define PMC_PCER0_PID30 (0x1 << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */ -#define PMC_PCER0_PID31 (0x1 << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */ -/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */ -#define PMC_PCDR0_PID2 (0x1 << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */ -#define PMC_PCDR0_PID3 (0x1 << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */ -#define PMC_PCDR0_PID4 (0x1 << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */ -#define PMC_PCDR0_PID5 (0x1 << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */ -#define PMC_PCDR0_PID6 (0x1 << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */ -#define PMC_PCDR0_PID7 (0x1 << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */ -#define PMC_PCDR0_PID8 (0x1 << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */ -#define PMC_PCDR0_PID9 (0x1 << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */ -#define PMC_PCDR0_PID10 (0x1 << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */ -#define PMC_PCDR0_PID11 (0x1 << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */ -#define PMC_PCDR0_PID12 (0x1 << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */ -#define PMC_PCDR0_PID13 (0x1 << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */ -#define PMC_PCDR0_PID14 (0x1 << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */ -#define PMC_PCDR0_PID15 (0x1 << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */ -#define PMC_PCDR0_PID16 (0x1 << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */ -#define PMC_PCDR0_PID17 (0x1 << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */ -#define PMC_PCDR0_PID18 (0x1 << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */ -#define PMC_PCDR0_PID19 (0x1 << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */ -#define PMC_PCDR0_PID20 (0x1 << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */ -#define PMC_PCDR0_PID21 (0x1 << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */ -#define PMC_PCDR0_PID22 (0x1 << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */ -#define PMC_PCDR0_PID23 (0x1 << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */ -#define PMC_PCDR0_PID24 (0x1 << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */ -#define PMC_PCDR0_PID25 (0x1 << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */ -#define PMC_PCDR0_PID26 (0x1 << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */ -#define PMC_PCDR0_PID27 (0x1 << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */ -#define PMC_PCDR0_PID28 (0x1 << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */ -#define PMC_PCDR0_PID29 (0x1 << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */ -#define PMC_PCDR0_PID30 (0x1 << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */ -#define PMC_PCDR0_PID31 (0x1 << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */ -/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */ -#define PMC_PCSR0_PID2 (0x1 << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */ -#define PMC_PCSR0_PID3 (0x1 << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */ -#define PMC_PCSR0_PID4 (0x1 << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */ -#define PMC_PCSR0_PID5 (0x1 << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */ -#define PMC_PCSR0_PID6 (0x1 << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */ -#define PMC_PCSR0_PID7 (0x1 << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */ -#define PMC_PCSR0_PID8 (0x1 << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */ -#define PMC_PCSR0_PID9 (0x1 << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */ -#define PMC_PCSR0_PID10 (0x1 << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */ -#define PMC_PCSR0_PID11 (0x1 << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */ -#define PMC_PCSR0_PID12 (0x1 << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */ -#define PMC_PCSR0_PID13 (0x1 << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */ -#define PMC_PCSR0_PID14 (0x1 << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */ -#define PMC_PCSR0_PID15 (0x1 << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */ -#define PMC_PCSR0_PID16 (0x1 << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */ -#define PMC_PCSR0_PID17 (0x1 << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */ -#define PMC_PCSR0_PID18 (0x1 << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */ -#define PMC_PCSR0_PID19 (0x1 << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */ -#define PMC_PCSR0_PID20 (0x1 << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */ -#define PMC_PCSR0_PID21 (0x1 << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */ -#define PMC_PCSR0_PID22 (0x1 << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */ -#define PMC_PCSR0_PID23 (0x1 << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */ -#define PMC_PCSR0_PID24 (0x1 << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */ -#define PMC_PCSR0_PID25 (0x1 << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */ -#define PMC_PCSR0_PID26 (0x1 << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */ -#define PMC_PCSR0_PID27 (0x1 << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */ -#define PMC_PCSR0_PID28 (0x1 << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */ -#define PMC_PCSR0_PID29 (0x1 << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */ -#define PMC_PCSR0_PID30 (0x1 << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */ -#define PMC_PCSR0_PID31 (0x1 << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */ -/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */ -#define CKGR_MOR_MOSCXTEN (0x1 << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */ -#define CKGR_MOR_MOSCXTBY (0x1 << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */ -#define CKGR_MOR_WAITMODE (0x1 << 2) /**< \brief (CKGR_MOR) Wait Mode Command */ -#define CKGR_MOR_MOSCRCEN (0x1 << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */ -#define CKGR_MOR_MOSCRCF (0x7 << 4) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */ -#define CKGR_MOR_MOSCXTST (0xff << 8) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */ -#define CKGR_MOR_KEY (0xff << 16) /**< \brief (CKGR_MOR) Password */ -#define CKGR_MOR_MOSCSEL (0x1 << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */ -#define CKGR_MOR_CFDEN (0x1 << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */ -/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */ -#define CKGR_MCFR_MAINF (0xffff << 0) /**< \brief (CKGR_MCFR) Main Clock Frequency */ -#define CKGR_MCFR_MAINFRDY (0x1 << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */ -/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */ -#define CKGR_PLLAR_DIVA (0xff << 0) /**< \brief (CKGR_PLLAR) Divider */ -#define CKGR_PLLAR_PLLACOUNT (0x3f << 8) /**< \brief (CKGR_PLLAR) PLLA Counter */ -#define CKGR_PLLAR_MULA (0x7ff << 16) /**< \brief (CKGR_PLLAR) PLLA Multiplier */ -#define CKGR_PLLAR_STUCKTO1 (0x1 << 29) /**< \brief (CKGR_PLLAR) */ -/* -------- CKGR_PLLBR : (PMC Offset: 0x002C) PLLB Register -------- */ -#define CKGR_PLLBR_DIVB_Pos 0 -#define CKGR_PLLBR_DIVB_Msk (0xffu << CKGR_PLLBR_DIVB_Pos) /**< \brief (CKGR_PLLBR) Divider */ -#define CKGR_PLLBR_DIVB(value) ((CKGR_PLLBR_DIVB_Msk & ((value) << CKGR_PLLBR_DIVB_Pos))) -#define CKGR_PLLBR_PLLBCOUNT (0x3f << 8) /**< \brief (CKGR_PLLBR) PLLB Counter */ -#define CKGR_PLLBR_MULB_Pos 16 -#define CKGR_PLLBR_MULB_Msk (0x7ffu << CKGR_PLLBR_MULB_Pos) /**< \brief (CKGR_PLLBR) PLLB Multiplier */ -#define CKGR_PLLBR_MULB(value) ((CKGR_PLLBR_MULB_Msk & ((value) << CKGR_PLLBR_MULB_Pos))) -/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */ -#define PMC_MCKR_CSS (0x3 << 0) /**< \brief (PMC_MCKR) Master Clock Source Selection */ -#define PMC_MCKR_CSS_SLOW_CLK (0x0 << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */ -#define PMC_MCKR_CSS_MAIN_CLK (0x1 << 0) /**< \brief (PMC_MCKR) Main Clock is selected */ -#define PMC_MCKR_CSS_PLLA_CLK (0x2 << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ -#define PMC_MCKR_CSS_PLLB_CLK (0x3 << 0) /**< \brief (PMC_MCKR) PLLB Clock is selected */ -#define PMC_MCKR_PRES (0x7 << 4) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ -#define PMC_MCKR_PRES_CLK (0x0 << 4) /**< \brief (PMC_MCKR) Selected clock */ -#define PMC_MCKR_PRES_CLK_2 (0x1 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ -#define PMC_MCKR_PRES_CLK_4 (0x2 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ -#define PMC_MCKR_PRES_CLK_8 (0x3 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ -#define PMC_MCKR_PRES_CLK_16 (0x4 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */ -#define PMC_MCKR_PRES_CLK_32 (0x5 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */ -#define PMC_MCKR_PRES_CLK_64 (0x6 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */ -#define PMC_MCKR_PLLADIV2 (0x1 << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */ -#define PMC_MCKR_PLLBDIV2 (0x1 << 13) /**< \brief (PMC_MCKR) PLLB Divisor by 2 */ -/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */ -#define PMC_USB_USBS (0x1 << 0) /**< \brief (PMC_USB) USB Input Clock Selection */ -#define PMC_USB_USBDIV_Pos 8 -#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock. */ -#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)))/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */ -#define PMC_PCK_CSS (0x7 << 0) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */ -#define PMC_PCK_PRES (0x7 << 4) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */ -/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ -#define PMC_IER_MOSCXTS (0x1 << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */ -#define PMC_IER_LOCKA (0x1 << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ -#define PMC_IER_LOCKB (0x1 << 2) /**< \brief (PMC_IER) PLLB Lock Interrupt Enable */ -#define PMC_IER_MCKRDY (0x1 << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ -#define PMC_IER_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ -#define PMC_IER_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ -#define PMC_IER_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */ -#define PMC_IER_MOSCSELS (0x1 << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */ -#define PMC_IER_MOSCRCS (0x1 << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */ -#define PMC_IER_CFDEV (0x1 << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */ -/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */ -#define PMC_IDR_MOSCXTS (0x1 << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */ -#define PMC_IDR_LOCKA (0x1 << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */ -#define PMC_IDR_LOCKB (0x1 << 2) /**< \brief (PMC_IDR) PLLB Lock Interrupt Disable */ -#define PMC_IDR_MCKRDY (0x1 << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ -#define PMC_IDR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ -#define PMC_IDR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ -#define PMC_IDR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */ -#define PMC_IDR_MOSCSELS (0x1 << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */ -#define PMC_IDR_MOSCRCS (0x1 << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */ -#define PMC_IDR_CFDEV (0x1 << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */ -/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */ -#define PMC_SR_MOSCXTS (0x1 << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */ -#define PMC_SR_LOCKA (0x1 << 1) /**< \brief (PMC_SR) PLLA Lock Status */ -#define PMC_SR_LOCKB (0x1 << 2) /**< \brief (PMC_SR) PLLB Lock Status */ -#define PMC_SR_MCKRDY (0x1 << 3) /**< \brief (PMC_SR) Master Clock Status */ -#define PMC_SR_OSCSELS (0x1 << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */ -#define PMC_SR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_MOSCSELS (0x1 << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */ -#define PMC_SR_MOSCRCS (0x1 << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */ -#define PMC_SR_CFDEV (0x1 << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */ -#define PMC_SR_CFDS (0x1 << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */ -#define PMC_SR_FOS (0x1 << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */ -/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */ -#define PMC_IMR_MOSCXTS (0x1 << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */ -#define PMC_IMR_LOCKA (0x1 << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */ -#define PMC_IMR_LOCKB (0x1 << 2) /**< \brief (PMC_IMR) PLLB Lock Interrupt Mask */ -#define PMC_IMR_MCKRDY (0x1 << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ -#define PMC_IMR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ -#define PMC_IMR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ -#define PMC_IMR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */ -#define PMC_IMR_MOSCSELS (0x1 << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */ -#define PMC_IMR_MOSCRCS (0x1 << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */ -#define PMC_IMR_CFDEV (0x1 << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */ -/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */ -#define PMC_FSMR_FSTT0 (0x1 << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */ -#define PMC_FSMR_FSTT1 (0x1 << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */ -#define PMC_FSMR_FSTT2 (0x1 << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */ -#define PMC_FSMR_FSTT3 (0x1 << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */ -#define PMC_FSMR_FSTT4 (0x1 << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */ -#define PMC_FSMR_FSTT5 (0x1 << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */ -#define PMC_FSMR_FSTT6 (0x1 << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */ -#define PMC_FSMR_FSTT7 (0x1 << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */ -#define PMC_FSMR_FSTT8 (0x1 << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */ -#define PMC_FSMR_FSTT9 (0x1 << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */ -#define PMC_FSMR_FSTT10 (0x1 << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */ -#define PMC_FSMR_FSTT11 (0x1 << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */ -#define PMC_FSMR_FSTT12 (0x1 << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */ -#define PMC_FSMR_FSTT13 (0x1 << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */ -#define PMC_FSMR_FSTT14 (0x1 << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */ -#define PMC_FSMR_FSTT15 (0x1 << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */ -#define PMC_FSMR_RTTAL (0x1 << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */ -#define PMC_FSMR_RTCAL (0x1 << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */ -#define PMC_FSMR_USBAL (0x1 << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */ -#define PMC_FSMR_LPM (0x1 << 20) /**< \brief (PMC_FSMR) Low Power Mode */ -/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */ -#define PMC_FSPR_FSTP0 (0x1 << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP1 (0x1 << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP2 (0x1 << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP3 (0x1 << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP4 (0x1 << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP5 (0x1 << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP6 (0x1 << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP7 (0x1 << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP8 (0x1 << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP9 (0x1 << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP10 (0x1 << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP11 (0x1 << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP12 (0x1 << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP13 (0x1 << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP14 (0x1 << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP15 (0x1 << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */ -#define PMC_FOCR_FOCLR (0x1 << 0) /**< \brief (PMC_FOCR) Fault Output Clear */ -/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */ -#define PMC_WPMR_WPEN (0x1 << 0) /**< \brief (PMC_WPMR) Write Protect Enable */ -#define PMC_WPMR_WPKEY (0xffffff << 8) /**< \brief (PMC_WPMR) Write Protect KEY */ -/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */ -#define PMC_WPSR_WPVS (0x1 << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */ -#define PMC_WPSR_WPVSRC (0xffff << 8) /**< \brief (PMC_WPSR) Write Protect Violation Source */ -/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */ -#define PMC_PCER1_PID32 (0x1 << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */ -#define PMC_PCER1_PID33 (0x1 << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */ -#define PMC_PCER1_PID34 (0x1 << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */ -#define PMC_PCER1_PID35 (0x1 << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */ -#define PMC_PCER1_PID36 (0x1 << 4) /**< \brief (PMC_PCER1) Peripheral Clock 36 Enable */ -#define PMC_PCER1_PID37 (0x1 << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */ -#define PMC_PCER1_PID38 (0x1 << 6) /**< \brief (PMC_PCER1) Peripheral Clock 38 Enable */ -#define PMC_PCER1_PID39 (0x1 << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */ -#define PMC_PCER1_PID40 (0x1 << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */ -#define PMC_PCER1_PID41 (0x1 << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */ -#define PMC_PCER1_PID42 (0x1 << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */ -#define PMC_PCER1_PID43 (0x1 << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */ -#define PMC_PCER1_PID44 (0x1 << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */ -#define PMC_PCER1_PID45 (0x1 << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */ -#define PMC_PCER1_PID46 (0x1 << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */ -#define PMC_PCER1_PID47 (0x1 << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */ -#define PMC_PCER1_PID48 (0x1 << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */ -#define PMC_PCER1_PID49 (0x1 << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */ -#define PMC_PCER1_PID50 (0x1 << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */ -#define PMC_PCER1_PID51 (0x1 << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */ -#define PMC_PCER1_PID52 (0x1 << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */ -#define PMC_PCER1_PID53 (0x1 << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */ -#define PMC_PCER1_PID54 (0x1 << 22) /**< \brief (PMC_PCER1) Peripheral Clock 54 Enable */ -#define PMC_PCER1_PID55 (0x1 << 23) /**< \brief (PMC_PCER1) Peripheral Clock 55 Enable */ -#define PMC_PCER1_PID56 (0x1 << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */ -#define PMC_PCER1_PID57 (0x1 << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */ -#define PMC_PCER1_PID58 (0x1 << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */ -#define PMC_PCER1_PID59 (0x1 << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */ -#define PMC_PCER1_PID60 (0x1 << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */ -#define PMC_PCER1_PID61 (0x1 << 29) /**< \brief (PMC_PCER1) Peripheral Clock 61 Enable */ -#define PMC_PCER1_PID62 (0x1 << 30) /**< \brief (PMC_PCER1) Peripheral Clock 62 Enable */ -#define PMC_PCER1_PID63 (0x1 << 31) /**< \brief (PMC_PCER1) Peripheral Clock 63 Enable */ -/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */ -#define PMC_PCDR1_PID32 (0x1 << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */ -#define PMC_PCDR1_PID33 (0x1 << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */ -#define PMC_PCDR1_PID34 (0x1 << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */ -#define PMC_PCDR1_PID35 (0x1 << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */ -#define PMC_PCDR1_PID36 (0x1 << 4) /**< \brief (PMC_PCDR1) Peripheral Clock 36 Disable */ -#define PMC_PCDR1_PID37 (0x1 << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */ -#define PMC_PCDR1_PID38 (0x1 << 6) /**< \brief (PMC_PCDR1) Peripheral Clock 38 Disable */ -#define PMC_PCDR1_PID39 (0x1 << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */ -#define PMC_PCDR1_PID40 (0x1 << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */ -#define PMC_PCDR1_PID41 (0x1 << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */ -#define PMC_PCDR1_PID42 (0x1 << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */ -#define PMC_PCDR1_PID43 (0x1 << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */ -#define PMC_PCDR1_PID44 (0x1 << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */ -#define PMC_PCDR1_PID45 (0x1 << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */ -#define PMC_PCDR1_PID46 (0x1 << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */ -#define PMC_PCDR1_PID47 (0x1 << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */ -#define PMC_PCDR1_PID48 (0x1 << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */ -#define PMC_PCDR1_PID49 (0x1 << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */ -#define PMC_PCDR1_PID50 (0x1 << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */ -#define PMC_PCDR1_PID51 (0x1 << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */ -#define PMC_PCDR1_PID52 (0x1 << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */ -#define PMC_PCDR1_PID53 (0x1 << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */ -#define PMC_PCDR1_PID54 (0x1 << 22) /**< \brief (PMC_PCDR1) Peripheral Clock 54 Disable */ -#define PMC_PCDR1_PID55 (0x1 << 23) /**< \brief (PMC_PCDR1) Peripheral Clock 55 Disable */ -#define PMC_PCDR1_PID56 (0x1 << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */ -#define PMC_PCDR1_PID57 (0x1 << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */ -#define PMC_PCDR1_PID58 (0x1 << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */ -#define PMC_PCDR1_PID59 (0x1 << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */ -#define PMC_PCDR1_PID60 (0x1 << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */ -#define PMC_PCDR1_PID61 (0x1 << 29) /**< \brief (PMC_PCDR1) Peripheral Clock 61 Disable */ -#define PMC_PCDR1_PID62 (0x1 << 30) /**< \brief (PMC_PCDR1) Peripheral Clock 62 Disable */ -#define PMC_PCDR1_PID63 (0x1 << 31) /**< \brief (PMC_PCDR1) Peripheral Clock 63 Disable */ -/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */ -#define PMC_PCSR1_PID32 (0x1 << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */ -#define PMC_PCSR1_PID33 (0x1 << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */ -#define PMC_PCSR1_PID34 (0x1 << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */ -#define PMC_PCSR1_PID35 (0x1 << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */ -#define PMC_PCSR1_PID36 (0x1 << 4) /**< \brief (PMC_PCSR1) Peripheral Clock 36 Status */ -#define PMC_PCSR1_PID37 (0x1 << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */ -#define PMC_PCSR1_PID38 (0x1 << 6) /**< \brief (PMC_PCSR1) Peripheral Clock 38 Status */ -#define PMC_PCSR1_PID39 (0x1 << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */ -#define PMC_PCSR1_PID40 (0x1 << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */ -#define PMC_PCSR1_PID41 (0x1 << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */ -#define PMC_PCSR1_PID42 (0x1 << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */ -#define PMC_PCSR1_PID43 (0x1 << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */ -#define PMC_PCSR1_PID44 (0x1 << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */ -#define PMC_PCSR1_PID45 (0x1 << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */ -#define PMC_PCSR1_PID46 (0x1 << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */ -#define PMC_PCSR1_PID47 (0x1 << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */ -#define PMC_PCSR1_PID48 (0x1 << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */ -#define PMC_PCSR1_PID49 (0x1 << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */ -#define PMC_PCSR1_PID50 (0x1 << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */ -#define PMC_PCSR1_PID51 (0x1 << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */ -#define PMC_PCSR1_PID52 (0x1 << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */ -#define PMC_PCSR1_PID53 (0x1 << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */ -#define PMC_PCSR1_PID54 (0x1 << 22) /**< \brief (PMC_PCSR1) Peripheral Clock 54 Status */ -#define PMC_PCSR1_PID55 (0x1 << 23) /**< \brief (PMC_PCSR1) Peripheral Clock 55 Status */ -#define PMC_PCSR1_PID56 (0x1 << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */ -#define PMC_PCSR1_PID57 (0x1 << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */ -#define PMC_PCSR1_PID58 (0x1 << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */ -#define PMC_PCSR1_PID59 (0x1 << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */ -#define PMC_PCSR1_PID60 (0x1 << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */ -#define PMC_PCSR1_PID61 (0x1 << 29) /**< \brief (PMC_PCSR1) Peripheral Clock 61 Status */ -#define PMC_PCSR1_PID62 (0x1 << 30) /**< \brief (PMC_PCSR1) Peripheral Clock 62 Status */ -#define PMC_PCSR1_PID63 (0x1 << 31) /**< \brief (PMC_PCSR1) Peripheral Clock 63 Status */ -/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */ -#define PMC_OCR_CAL4 (0x7f << 0) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 Mhz */ -#define PMC_OCR_SEL4 (0x1 << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 Mhz */ -#define PMC_OCR_CAL8 (0x7f << 8) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 Mhz */ -#define PMC_OCR_SEL8 (0x1 << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 Mhz */ -#define PMC_OCR_CAL12 (0x7f << 16) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 Mhz */ -#define PMC_OCR_SEL12 (0x1 << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 Mhz */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_PWM Pulse Width Modulation Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief PwmCh_num hardware registers */ -typedef struct { - RwReg PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */ - RwReg PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */ - RwReg PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */ - RwReg PWM_CPDR; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */ - RwReg PWM_CPDRUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */ - RwReg PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */ - RwReg PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */ - RwReg PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */ -} PwmCh_num; -/** \brief Pwm hardware registers */ -typedef struct { - RwReg PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */ - WoReg PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */ - WoReg PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */ - RoReg PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */ - WoReg PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */ - WoReg PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */ - RoReg PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */ - RoReg PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */ - RwReg PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */ - RwReg Reserved1[1]; - RwReg PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */ - RwReg PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */ - WoReg PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */ - WoReg PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */ - WoReg PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */ - RoReg PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */ - RoReg PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */ - RwReg PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */ - RwReg PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */ - WoReg PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */ - WoReg PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */ - WoReg PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */ - WoReg PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */ - RwReg PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */ - RoReg PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */ - WoReg PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */ - RwReg PWM_FPV; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */ - RwReg PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */ - RwReg Reserved2[3]; - RwReg PWM_ELxMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */ - RwReg Reserved3[11]; - RwReg PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */ - RwReg Reserved4[12]; - WoReg PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */ - RoReg PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */ - RwReg Reserved5[5]; - RwReg PWM_RPR; /**< \brief (Pwm Offset: 0x100) Receive Pointer Register */ - RwReg PWM_RCR; /**< \brief (Pwm Offset: 0x104) Receive Counter Register */ - RwReg PWM_TPR; /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */ - RwReg PWM_TCR; /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */ - RwReg PWM_RNPR; /**< \brief (Pwm Offset: 0x110) Receive Next Pointer Register */ - RwReg PWM_RNCR; /**< \brief (Pwm Offset: 0x114) Receive Next Counter Register */ - RwReg PWM_TNPR; /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */ - RwReg PWM_TNCR; /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */ - WoReg PWM_PTCR; /**< \brief (Pwm Offset: 0x120) Transfer Control Register */ - RoReg PWM_PTSR; /**< \brief (Pwm Offset: 0x124) Transfer Status Register */ - RwReg Reserved6[2]; - RwReg PWM_CMP0V; /**< \brief (Pwm Offset: 0x130) PWM Comparison 0 Value Register */ - WoReg PWM_CMP0VUPD; /**< \brief (Pwm Offset: 0x134) PWM Comparison 0 Value Update Register */ - RwReg PWM_CMP0M; /**< \brief (Pwm Offset: 0x138) PWM Comparison 0 Mode Register */ - WoReg PWM_CMP0MUPD; /**< \brief (Pwm Offset: 0x13C) PWM Comparison 0 Mode Update Register */ - RwReg PWM_CMP1V; /**< \brief (Pwm Offset: 0x140) PWM Comparison 1 Value Register */ - WoReg PWM_CMP1VUPD; /**< \brief (Pwm Offset: 0x144) PWM Comparison 1 Value Update Register */ - RwReg PWM_CMP1M; /**< \brief (Pwm Offset: 0x148) PWM Comparison 1 Mode Register */ - WoReg PWM_CMP1MUPD; /**< \brief (Pwm Offset: 0x14C) PWM Comparison 1 Mode Update Register */ - RwReg PWM_CMP2V; /**< \brief (Pwm Offset: 0x150) PWM Comparison 2 Value Register */ - WoReg PWM_CMP2VUPD; /**< \brief (Pwm Offset: 0x154) PWM Comparison 2 Value Update Register */ - RwReg PWM_CMP2M; /**< \brief (Pwm Offset: 0x158) PWM Comparison 2 Mode Register */ - WoReg PWM_CMP2MUPD; /**< \brief (Pwm Offset: 0x15C) PWM Comparison 2 Mode Update Register */ - RwReg PWM_CMP3V; /**< \brief (Pwm Offset: 0x160) PWM Comparison 3 Value Register */ - WoReg PWM_CMP3VUPD; /**< \brief (Pwm Offset: 0x164) PWM Comparison 3 Value Update Register */ - RwReg PWM_CMP3M; /**< \brief (Pwm Offset: 0x168) PWM Comparison 3 Mode Register */ - WoReg PWM_CMP3MUPD; /**< \brief (Pwm Offset: 0x16C) PWM Comparison 3 Mode Update Register */ - RwReg PWM_CMP4V; /**< \brief (Pwm Offset: 0x170) PWM Comparison 4 Value Register */ - WoReg PWM_CMP4VUPD; /**< \brief (Pwm Offset: 0x174) PWM Comparison 4 Value Update Register */ - RwReg PWM_CMP4M; /**< \brief (Pwm Offset: 0x178) PWM Comparison 4 Mode Register */ - WoReg PWM_CMP4MUPD; /**< \brief (Pwm Offset: 0x17C) PWM Comparison 4 Mode Update Register */ - RwReg PWM_CMP5V; /**< \brief (Pwm Offset: 0x180) PWM Comparison 5 Value Register */ - WoReg PWM_CMP5VUPD; /**< \brief (Pwm Offset: 0x184) PWM Comparison 5 Value Update Register */ - RwReg PWM_CMP5M; /**< \brief (Pwm Offset: 0x188) PWM Comparison 5 Mode Register */ - WoReg PWM_CMP5MUPD; /**< \brief (Pwm Offset: 0x18C) PWM Comparison 5 Mode Update Register */ - RwReg PWM_CMP6V; /**< \brief (Pwm Offset: 0x190) PWM Comparison 6 Value Register */ - WoReg PWM_CMP6VUPD; /**< \brief (Pwm Offset: 0x194) PWM Comparison 6 Value Update Register */ - RwReg PWM_CMP6M; /**< \brief (Pwm Offset: 0x198) PWM Comparison 6 Mode Register */ - WoReg PWM_CMP6MUPD; /**< \brief (Pwm Offset: 0x19C) PWM Comparison 6 Mode Update Register */ - RwReg PWM_CMP7V; /**< \brief (Pwm Offset: 0x1A0) PWM Comparison 7 Value Register */ - WoReg PWM_CMP7VUPD; /**< \brief (Pwm Offset: 0x1A4) PWM Comparison 7 Value Update Register */ - RwReg PWM_CMP7M; /**< \brief (Pwm Offset: 0x1A8) PWM Comparison 7 Mode Register */ - WoReg PWM_CMP7MUPD; /**< \brief (Pwm Offset: 0x1AC) PWM Comparison 7 Mode Update Register */ - RwReg Reserved7[20]; - PwmCh_num PWM_CH_NUM[4]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */ -} Pwm; -#endif /* __ASSEMBLY__ */ -/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */ -#define PWM_CLK_DIVA (0xff << 0) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ -#define PWM_CLK_PREA (0xf << 8) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ -#define PWM_CLK_DIVB (0xff << 16) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ -#define PWM_CLK_PREB (0xf << 24) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ -/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */ -#define PWM_ENA_CHID0 (0x1 << 0) /**< \brief (PWM_ENA) Channel ID */ -#define PWM_ENA_CHID1 (0x1 << 1) /**< \brief (PWM_ENA) Channel ID */ -#define PWM_ENA_CHID2 (0x1 << 2) /**< \brief (PWM_ENA) Channel ID */ -#define PWM_ENA_CHID3 (0x1 << 3) /**< \brief (PWM_ENA) Channel ID */ -/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */ -#define PWM_DIS_CHID0 (0x1 << 0) /**< \brief (PWM_DIS) Channel ID */ -#define PWM_DIS_CHID1 (0x1 << 1) /**< \brief (PWM_DIS) Channel ID */ -#define PWM_DIS_CHID2 (0x1 << 2) /**< \brief (PWM_DIS) Channel ID */ -#define PWM_DIS_CHID3 (0x1 << 3) /**< \brief (PWM_DIS) Channel ID */ -/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */ -#define PWM_SR_CHID0 (0x1 << 0) /**< \brief (PWM_SR) Channel ID */ -#define PWM_SR_CHID1 (0x1 << 1) /**< \brief (PWM_SR) Channel ID */ -#define PWM_SR_CHID2 (0x1 << 2) /**< \brief (PWM_SR) Channel ID */ -#define PWM_SR_CHID3 (0x1 << 3) /**< \brief (PWM_SR) Channel ID */ -/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */ -#define PWM_IER1_CHID0 (0x1 << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */ -#define PWM_IER1_CHID1 (0x1 << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */ -#define PWM_IER1_CHID2 (0x1 << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */ -#define PWM_IER1_CHID3 (0x1 << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */ -#define PWM_IER1_FCHID0 (0x1 << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */ -#define PWM_IER1_FCHID1 (0x1 << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */ -#define PWM_IER1_FCHID2 (0x1 << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */ -#define PWM_IER1_FCHID3 (0x1 << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */ -/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */ -#define PWM_IDR1_CHID0 (0x1 << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */ -#define PWM_IDR1_CHID1 (0x1 << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */ -#define PWM_IDR1_CHID2 (0x1 << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */ -#define PWM_IDR1_CHID3 (0x1 << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */ -#define PWM_IDR1_FCHID0 (0x1 << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */ -#define PWM_IDR1_FCHID1 (0x1 << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */ -#define PWM_IDR1_FCHID2 (0x1 << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */ -#define PWM_IDR1_FCHID3 (0x1 << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */ -/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */ -#define PWM_IMR1_CHID0 (0x1 << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */ -#define PWM_IMR1_CHID1 (0x1 << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */ -#define PWM_IMR1_CHID2 (0x1 << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */ -#define PWM_IMR1_CHID3 (0x1 << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */ -#define PWM_IMR1_FCHID0 (0x1 << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */ -#define PWM_IMR1_FCHID1 (0x1 << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */ -#define PWM_IMR1_FCHID2 (0x1 << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */ -#define PWM_IMR1_FCHID3 (0x1 << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */ -/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */ -#define PWM_ISR1_CHID0 (0x1 << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */ -#define PWM_ISR1_CHID1 (0x1 << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */ -#define PWM_ISR1_CHID2 (0x1 << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */ -#define PWM_ISR1_CHID3 (0x1 << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */ -#define PWM_ISR1_FCHID0 (0x1 << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */ -#define PWM_ISR1_FCHID1 (0x1 << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */ -#define PWM_ISR1_FCHID2 (0x1 << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */ -#define PWM_ISR1_FCHID3 (0x1 << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */ -/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */ -#define PWM_SCM_SYNC0 (0x1 << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */ -#define PWM_SCM_SYNC1 (0x1 << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */ -#define PWM_SCM_SYNC2 (0x1 << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */ -#define PWM_SCM_SYNC3 (0x1 << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */ -#define PWM_SCM_UPDM (0x3 << 16) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */ -#define PWM_SCM_PTRM (0x1 << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */ -#define PWM_SCM_PTRCS (0x7 << 21) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */ -/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */ -#define PWM_SCUC_UPDULOCK (0x1 << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */ -/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */ -#define PWM_SCUP_UPR (0xf << 0) /**< \brief (PWM_SCUP) Update Period */ -#define PWM_SCUP_UPRCNT (0xf << 4) /**< \brief (PWM_SCUP) Update Period Counter */ -/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */ -#define PWM_SCUPUPD_UPRUPD (0xf << 0) /**< \brief (PWM_SCUPUPD) Update Period Update */ -/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */ -#define PWM_IER2_WRDY (0x1 << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */ -#define PWM_IER2_ENDTX (0x1 << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */ -#define PWM_IER2_TXBUFE (0x1 << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */ -#define PWM_IER2_UNRE (0x1 << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */ -#define PWM_IER2_CMPM0 (0x1 << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */ -#define PWM_IER2_CMPM1 (0x1 << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */ -#define PWM_IER2_CMPM2 (0x1 << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */ -#define PWM_IER2_CMPM3 (0x1 << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */ -#define PWM_IER2_CMPM4 (0x1 << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */ -#define PWM_IER2_CMPM5 (0x1 << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */ -#define PWM_IER2_CMPM6 (0x1 << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */ -#define PWM_IER2_CMPM7 (0x1 << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */ -#define PWM_IER2_CMPU0 (0x1 << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */ -#define PWM_IER2_CMPU1 (0x1 << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */ -#define PWM_IER2_CMPU2 (0x1 << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */ -#define PWM_IER2_CMPU3 (0x1 << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */ -#define PWM_IER2_CMPU4 (0x1 << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */ -#define PWM_IER2_CMPU5 (0x1 << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */ -#define PWM_IER2_CMPU6 (0x1 << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */ -#define PWM_IER2_CMPU7 (0x1 << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */ -/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */ -#define PWM_IDR2_WRDY (0x1 << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */ -#define PWM_IDR2_ENDTX (0x1 << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */ -#define PWM_IDR2_TXBUFE (0x1 << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */ -#define PWM_IDR2_UNRE (0x1 << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */ -#define PWM_IDR2_CMPM0 (0x1 << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */ -#define PWM_IDR2_CMPM1 (0x1 << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */ -#define PWM_IDR2_CMPM2 (0x1 << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */ -#define PWM_IDR2_CMPM3 (0x1 << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */ -#define PWM_IDR2_CMPM4 (0x1 << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */ -#define PWM_IDR2_CMPM5 (0x1 << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */ -#define PWM_IDR2_CMPM6 (0x1 << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */ -#define PWM_IDR2_CMPM7 (0x1 << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */ -#define PWM_IDR2_CMPU0 (0x1 << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */ -#define PWM_IDR2_CMPU1 (0x1 << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */ -#define PWM_IDR2_CMPU2 (0x1 << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */ -#define PWM_IDR2_CMPU3 (0x1 << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */ -#define PWM_IDR2_CMPU4 (0x1 << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */ -#define PWM_IDR2_CMPU5 (0x1 << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */ -#define PWM_IDR2_CMPU6 (0x1 << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */ -#define PWM_IDR2_CMPU7 (0x1 << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */ -/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */ -#define PWM_IMR2_WRDY (0x1 << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */ -#define PWM_IMR2_ENDTX (0x1 << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */ -#define PWM_IMR2_TXBUFE (0x1 << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */ -#define PWM_IMR2_UNRE (0x1 << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */ -#define PWM_IMR2_CMPM0 (0x1 << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */ -#define PWM_IMR2_CMPM1 (0x1 << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */ -#define PWM_IMR2_CMPM2 (0x1 << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */ -#define PWM_IMR2_CMPM3 (0x1 << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */ -#define PWM_IMR2_CMPM4 (0x1 << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */ -#define PWM_IMR2_CMPM5 (0x1 << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */ -#define PWM_IMR2_CMPM6 (0x1 << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */ -#define PWM_IMR2_CMPM7 (0x1 << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */ -#define PWM_IMR2_CMPU0 (0x1 << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */ -#define PWM_IMR2_CMPU1 (0x1 << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */ -#define PWM_IMR2_CMPU2 (0x1 << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */ -#define PWM_IMR2_CMPU3 (0x1 << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */ -#define PWM_IMR2_CMPU4 (0x1 << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */ -#define PWM_IMR2_CMPU5 (0x1 << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */ -#define PWM_IMR2_CMPU6 (0x1 << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */ -#define PWM_IMR2_CMPU7 (0x1 << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */ -/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */ -#define PWM_ISR2_WRDY (0x1 << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */ -#define PWM_ISR2_ENDTX (0x1 << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */ -#define PWM_ISR2_TXBUFE (0x1 << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */ -#define PWM_ISR2_UNRE (0x1 << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */ -#define PWM_ISR2_CMPM0 (0x1 << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */ -#define PWM_ISR2_CMPM1 (0x1 << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */ -#define PWM_ISR2_CMPM2 (0x1 << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */ -#define PWM_ISR2_CMPM3 (0x1 << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */ -#define PWM_ISR2_CMPM4 (0x1 << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */ -#define PWM_ISR2_CMPM5 (0x1 << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */ -#define PWM_ISR2_CMPM6 (0x1 << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */ -#define PWM_ISR2_CMPM7 (0x1 << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */ -#define PWM_ISR2_CMPU0 (0x1 << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */ -#define PWM_ISR2_CMPU1 (0x1 << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */ -#define PWM_ISR2_CMPU2 (0x1 << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */ -#define PWM_ISR2_CMPU3 (0x1 << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */ -#define PWM_ISR2_CMPU4 (0x1 << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */ -#define PWM_ISR2_CMPU5 (0x1 << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */ -#define PWM_ISR2_CMPU6 (0x1 << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */ -#define PWM_ISR2_CMPU7 (0x1 << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */ -/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */ -#define PWM_OOV_OOVH0 (0x1 << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */ -#define PWM_OOV_OOVH1 (0x1 << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */ -#define PWM_OOV_OOVH2 (0x1 << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */ -#define PWM_OOV_OOVH3 (0x1 << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */ -#define PWM_OOV_OOVL0 (0x1 << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */ -#define PWM_OOV_OOVL1 (0x1 << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */ -#define PWM_OOV_OOVL2 (0x1 << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */ -#define PWM_OOV_OOVL3 (0x1 << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */ -/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */ -#define PWM_OS_OSH0 (0x1 << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */ -#define PWM_OS_OSH1 (0x1 << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */ -#define PWM_OS_OSH2 (0x1 << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */ -#define PWM_OS_OSH3 (0x1 << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */ -#define PWM_OS_OSL0 (0x1 << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */ -#define PWM_OS_OSL1 (0x1 << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */ -#define PWM_OS_OSL2 (0x1 << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */ -#define PWM_OS_OSL3 (0x1 << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */ -/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */ -#define PWM_OSS_OSSH0 (0x1 << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */ -#define PWM_OSS_OSSH1 (0x1 << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */ -#define PWM_OSS_OSSH2 (0x1 << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */ -#define PWM_OSS_OSSH3 (0x1 << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */ -#define PWM_OSS_OSSL0 (0x1 << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */ -#define PWM_OSS_OSSL1 (0x1 << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */ -#define PWM_OSS_OSSL2 (0x1 << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */ -#define PWM_OSS_OSSL3 (0x1 << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */ -/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */ -#define PWM_OSC_OSCH0 (0x1 << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */ -#define PWM_OSC_OSCH1 (0x1 << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */ -#define PWM_OSC_OSCH2 (0x1 << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */ -#define PWM_OSC_OSCH3 (0x1 << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */ -#define PWM_OSC_OSCL0 (0x1 << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */ -#define PWM_OSC_OSCL1 (0x1 << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */ -#define PWM_OSC_OSCL2 (0x1 << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */ -#define PWM_OSC_OSCL3 (0x1 << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */ -/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */ -#define PWM_OSSUPD_OSSUPH0 (0x1 << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */ -#define PWM_OSSUPD_OSSUPH1 (0x1 << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */ -#define PWM_OSSUPD_OSSUPH2 (0x1 << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */ -#define PWM_OSSUPD_OSSUPH3 (0x1 << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */ -#define PWM_OSSUPD_OSSUPL0 (0x1 << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */ -#define PWM_OSSUPD_OSSUPL1 (0x1 << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */ -#define PWM_OSSUPD_OSSUPL2 (0x1 << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */ -#define PWM_OSSUPD_OSSUPL3 (0x1 << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */ -/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */ -#define PWM_OSCUPD_OSCUPH0 (0x1 << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */ -#define PWM_OSCUPD_OSCUPH1 (0x1 << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */ -#define PWM_OSCUPD_OSCUPH2 (0x1 << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */ -#define PWM_OSCUPD_OSCUPH3 (0x1 << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */ -#define PWM_OSCUPD_OSCUPL0 (0x1 << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */ -#define PWM_OSCUPD_OSCUPL1 (0x1 << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */ -#define PWM_OSCUPD_OSCUPL2 (0x1 << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */ -#define PWM_OSCUPD_OSCUPL3 (0x1 << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */ -/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */ -#define PWM_FMR_FPOL0 (0x1 << 0) /**< \brief (PWM_FMR) Fault 0 Polarity */ -#define PWM_FMR_FPOL1 (0x1 << 1) /**< \brief (PWM_FMR) Fault 1 Polarity */ -#define PWM_FMR_FPOL2 (0x1 << 2) /**< \brief (PWM_FMR) Fault 2 Polarity */ -#define PWM_FMR_FPOL3 (0x1 << 3) /**< \brief (PWM_FMR) Fault 3 Polarity */ -#define PWM_FMR_FMOD0 (0x1 << 8) /**< \brief (PWM_FMR) Fault 0 Activation Mode */ -#define PWM_FMR_FMOD1 (0x1 << 9) /**< \brief (PWM_FMR) Fault 1 Activation Mode */ -#define PWM_FMR_FMOD2 (0x1 << 10) /**< \brief (PWM_FMR) Fault 2 Activation Mode */ -#define PWM_FMR_FMOD3 (0x1 << 11) /**< \brief (PWM_FMR) Fault 3 Activation Mode */ -#define PWM_FMR_FFIL0 (0x1 << 16) /**< \brief (PWM_FMR) Fault 0 Filtering */ -#define PWM_FMR_FFIL1 (0x1 << 17) /**< \brief (PWM_FMR) Fault 1 Filtering */ -#define PWM_FMR_FFIL2 (0x1 << 18) /**< \brief (PWM_FMR) Fault 2 Filtering */ -#define PWM_FMR_FFIL3 (0x1 << 19) /**< \brief (PWM_FMR) Fault 3 Filtering */ -/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */ -#define PWM_FSR_FIV0 (0x1 << 0) /**< \brief (PWM_FSR) Fault Input 0 Value */ -#define PWM_FSR_FIV1 (0x1 << 1) /**< \brief (PWM_FSR) Fault Input 1 Value */ -#define PWM_FSR_FIV2 (0x1 << 2) /**< \brief (PWM_FSR) Fault Input 2 Value */ -#define PWM_FSR_FIV3 (0x1 << 3) /**< \brief (PWM_FSR) Fault Input 3 Value */ -#define PWM_FSR_FS0 (0x1 << 8) /**< \brief (PWM_FSR) Fault 0 Status */ -#define PWM_FSR_FS1 (0x1 << 9) /**< \brief (PWM_FSR) Fault 1 Status */ -#define PWM_FSR_FS2 (0x1 << 10) /**< \brief (PWM_FSR) Fault 2 Status */ -#define PWM_FSR_FS3 (0x1 << 11) /**< \brief (PWM_FSR) Fault 3 Status */ -/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */ -#define PWM_FCR_FCLR0 (0x1 << 0) /**< \brief (PWM_FCR) Fault 0 Clear */ -#define PWM_FCR_FCLR1 (0x1 << 1) /**< \brief (PWM_FCR) Fault 1 Clear */ -#define PWM_FCR_FCLR2 (0x1 << 2) /**< \brief (PWM_FCR) Fault 2 Clear */ -#define PWM_FCR_FCLR3 (0x1 << 3) /**< \brief (PWM_FCR) Fault 3 Clear */ -/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */ -#define PWM_FPV_FPVH0 (0x1 << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */ -#define PWM_FPV_FPVH1 (0x1 << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */ -#define PWM_FPV_FPVH2 (0x1 << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */ -#define PWM_FPV_FPVH3 (0x1 << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */ -#define PWM_FPV_FPVL0 (0x1 << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */ -#define PWM_FPV_FPVL1 (0x1 << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */ -#define PWM_FPV_FPVL2 (0x1 << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */ -#define PWM_FPV_FPVL3 (0x1 << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */ -/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */ -#define PWM_FPE_FPE0 (0xff << 0) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 0 for channel x */ -#define PWM_FPE_FPE1 (0xff << 8) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 1 for channel x */ -#define PWM_FPE_FPE2 (0xff << 16) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 2 for channel x */ -#define PWM_FPE_FPE3 (0xff << 24) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 3 for channel x */ -/* -------- PWM_ELxMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */ -#define PWM_ELxMR_CSEL0 (0x1 << 0) /**< \brief (PWM_ELxMR[2]) Comparison 0 Selection */ -#define PWM_ELxMR_CSEL1 (0x1 << 1) /**< \brief (PWM_ELxMR[2]) Comparison 1 Selection */ -#define PWM_ELxMR_CSEL2 (0x1 << 2) /**< \brief (PWM_ELxMR[2]) Comparison 2 Selection */ -#define PWM_ELxMR_CSEL3 (0x1 << 3) /**< \brief (PWM_ELxMR[2]) Comparison 3 Selection */ -#define PWM_ELxMR_CSEL4 (0x1 << 4) /**< \brief (PWM_ELxMR[2]) Comparison 4 Selection */ -#define PWM_ELxMR_CSEL5 (0x1 << 5) /**< \brief (PWM_ELxMR[2]) Comparison 5 Selection */ -#define PWM_ELxMR_CSEL6 (0x1 << 6) /**< \brief (PWM_ELxMR[2]) Comparison 6 Selection */ -#define PWM_ELxMR_CSEL7 (0x1 << 7) /**< \brief (PWM_ELxMR[2]) Comparison 7 Selection */ -/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */ -#define PWM_SMMR_GCEN0 (0x1 << 0) /**< \brief (PWM_SMMR) Gray Count ENable */ -#define PWM_SMMR_GCEN1 (0x1 << 1) /**< \brief (PWM_SMMR) Gray Count ENable */ -#define PWM_SMMR_DOWN0 (0x1 << 16) /**< \brief (PWM_SMMR) DOWN Count */ -#define PWM_SMMR_DOWN1 (0x1 << 17) /**< \brief (PWM_SMMR) DOWN Count */ -/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */ -#define PWM_WPCR_WPCMD (0x3 << 0) /**< \brief (PWM_WPCR) Write Protect Command */ -#define PWM_WPCR_WPRG0 (0x1 << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */ -#define PWM_WPCR_WPRG1 (0x1 << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */ -#define PWM_WPCR_WPRG2 (0x1 << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */ -#define PWM_WPCR_WPRG3 (0x1 << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */ -#define PWM_WPCR_WPRG4 (0x1 << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */ -#define PWM_WPCR_WPRG5 (0x1 << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */ -#define PWM_WPCR_WPKEY (0xffffff << 8) /**< \brief (PWM_WPCR) Write Protect Key */ -/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */ -#define PWM_WPSR_WPSWS0 (0x1 << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS1 (0x1 << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS2 (0x1 << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS3 (0x1 << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS4 (0x1 << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS5 (0x1 << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPVS (0x1 << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */ -#define PWM_WPSR_WPHWS0 (0x1 << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS1 (0x1 << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS2 (0x1 << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS3 (0x1 << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS4 (0x1 << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS5 (0x1 << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPVSRC (0xffff << 16) /**< \brief (PWM_WPSR) Write Protect Violation Source */ -/* -------- PWM_RPR : (PWM Offset: 0x100) Receive Pointer Register -------- */ -#define PWM_RPR_RXPTR (0xffffffff << 0) /**< \brief (PWM_RPR) Receive Pointer Register */ -/* -------- PWM_RCR : (PWM Offset: 0x104) Receive Counter Register -------- */ -#define PWM_RCR_RXCTR (0xffff << 0) /**< \brief (PWM_RCR) Receive Counter Register */ -/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */ -#define PWM_TPR_TXPTR (0xffffffff << 0) /**< \brief (PWM_TPR) Transmit Counter Register */ -/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */ -#define PWM_TCR_TXCTR (0xffff << 0) /**< \brief (PWM_TCR) Transmit Counter Register */ -/* -------- PWM_RNPR : (PWM Offset: 0x110) Receive Next Pointer Register -------- */ -#define PWM_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (PWM_RNPR) Receive Next Pointer */ -/* -------- PWM_RNCR : (PWM Offset: 0x114) Receive Next Counter Register -------- */ -#define PWM_RNCR_RXNCTR (0xffff << 0) /**< \brief (PWM_RNCR) Receive Next Counter */ -/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */ -#define PWM_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (PWM_TNPR) Transmit Next Pointer */ -/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */ -#define PWM_TNCR_TXNCTR (0xffff << 0) /**< \brief (PWM_TNCR) Transmit Counter Next */ -/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */ -#define PWM_PTCR_RXTEN (0x1 << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */ -#define PWM_PTCR_RXTDIS (0x1 << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */ -#define PWM_PTCR_TXTEN (0x1 << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */ -#define PWM_PTCR_TXTDIS (0x1 << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */ -/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */ -#define PWM_PTSR_RXTEN (0x1 << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */ -#define PWM_PTSR_TXTEN (0x1 << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */ -/* -------- PWM_CMP0V : (PWM Offset: 0x130) PWM Comparison 0 Value Register -------- */ -#define PWM_CMP0V_CV (0xffffff << 0) /**< \brief (PWM_CMP0V) Comparison x Value */ -#define PWM_CMP0V_CVM (0x1 << 24) /**< \brief (PWM_CMP0V) Comparison x Value Mode */ -/* -------- PWM_CMP0VUPD : (PWM Offset: 0x134) PWM Comparison 0 Value Update Register -------- */ -#define PWM_CMP0VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP0VUPD) Comparison x Value Update */ -#define PWM_CMP0VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP0VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP0M : (PWM Offset: 0x138) PWM Comparison 0 Mode Register -------- */ -#define PWM_CMP0M_CEN (0x1 << 0) /**< \brief (PWM_CMP0M) Comparison x Enable */ -#define PWM_CMP0M_CTR (0xf << 4) /**< \brief (PWM_CMP0M) Comparison x Trigger */ -#define PWM_CMP0M_CPR (0xf << 8) /**< \brief (PWM_CMP0M) Comparison x Period */ -#define PWM_CMP0M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP0M) Comparison x Period Counter */ -#define PWM_CMP0M_CUPR (0xf << 16) /**< \brief (PWM_CMP0M) Comparison x Update Period */ -#define PWM_CMP0M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP0M) Comparison x Update Period Counter */ -/* -------- PWM_CMP0MUPD : (PWM Offset: 0x13C) PWM Comparison 0 Mode Update Register -------- */ -#define PWM_CMP0MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP0MUPD) Comparison x Enable Update */ -#define PWM_CMP0MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP0MUPD) Comparison x Trigger Update */ -#define PWM_CMP0MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP0MUPD) Comparison x Period Update */ -#define PWM_CMP0MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP0MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP1V : (PWM Offset: 0x140) PWM Comparison 1 Value Register -------- */ -#define PWM_CMP1V_CV (0xffffff << 0) /**< \brief (PWM_CMP1V) Comparison x Value */ -#define PWM_CMP1V_CVM (0x1 << 24) /**< \brief (PWM_CMP1V) Comparison x Value Mode */ -/* -------- PWM_CMP1VUPD : (PWM Offset: 0x144) PWM Comparison 1 Value Update Register -------- */ -#define PWM_CMP1VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP1VUPD) Comparison x Value Update */ -#define PWM_CMP1VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP1VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP1M : (PWM Offset: 0x148) PWM Comparison 1 Mode Register -------- */ -#define PWM_CMP1M_CEN (0x1 << 0) /**< \brief (PWM_CMP1M) Comparison x Enable */ -#define PWM_CMP1M_CTR (0xf << 4) /**< \brief (PWM_CMP1M) Comparison x Trigger */ -#define PWM_CMP1M_CPR (0xf << 8) /**< \brief (PWM_CMP1M) Comparison x Period */ -#define PWM_CMP1M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP1M) Comparison x Period Counter */ -#define PWM_CMP1M_CUPR (0xf << 16) /**< \brief (PWM_CMP1M) Comparison x Update Period */ -#define PWM_CMP1M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP1M) Comparison x Update Period Counter */ -/* -------- PWM_CMP1MUPD : (PWM Offset: 0x14C) PWM Comparison 1 Mode Update Register -------- */ -#define PWM_CMP1MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP1MUPD) Comparison x Enable Update */ -#define PWM_CMP1MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP1MUPD) Comparison x Trigger Update */ -#define PWM_CMP1MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP1MUPD) Comparison x Period Update */ -#define PWM_CMP1MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP1MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP2V : (PWM Offset: 0x150) PWM Comparison 2 Value Register -------- */ -#define PWM_CMP2V_CV (0xffffff << 0) /**< \brief (PWM_CMP2V) Comparison x Value */ -#define PWM_CMP2V_CVM (0x1 << 24) /**< \brief (PWM_CMP2V) Comparison x Value Mode */ -/* -------- PWM_CMP2VUPD : (PWM Offset: 0x154) PWM Comparison 2 Value Update Register -------- */ -#define PWM_CMP2VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP2VUPD) Comparison x Value Update */ -#define PWM_CMP2VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP2VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP2M : (PWM Offset: 0x158) PWM Comparison 2 Mode Register -------- */ -#define PWM_CMP2M_CEN (0x1 << 0) /**< \brief (PWM_CMP2M) Comparison x Enable */ -#define PWM_CMP2M_CTR (0xf << 4) /**< \brief (PWM_CMP2M) Comparison x Trigger */ -#define PWM_CMP2M_CPR (0xf << 8) /**< \brief (PWM_CMP2M) Comparison x Period */ -#define PWM_CMP2M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP2M) Comparison x Period Counter */ -#define PWM_CMP2M_CUPR (0xf << 16) /**< \brief (PWM_CMP2M) Comparison x Update Period */ -#define PWM_CMP2M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP2M) Comparison x Update Period Counter */ -/* -------- PWM_CMP2MUPD : (PWM Offset: 0x15C) PWM Comparison 2 Mode Update Register -------- */ -#define PWM_CMP2MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP2MUPD) Comparison x Enable Update */ -#define PWM_CMP2MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP2MUPD) Comparison x Trigger Update */ -#define PWM_CMP2MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP2MUPD) Comparison x Period Update */ -#define PWM_CMP2MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP2MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP3V : (PWM Offset: 0x160) PWM Comparison 3 Value Register -------- */ -#define PWM_CMP3V_CV (0xffffff << 0) /**< \brief (PWM_CMP3V) Comparison x Value */ -#define PWM_CMP3V_CVM (0x1 << 24) /**< \brief (PWM_CMP3V) Comparison x Value Mode */ -/* -------- PWM_CMP3VUPD : (PWM Offset: 0x164) PWM Comparison 3 Value Update Register -------- */ -#define PWM_CMP3VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP3VUPD) Comparison x Value Update */ -#define PWM_CMP3VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP3VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP3M : (PWM Offset: 0x168) PWM Comparison 3 Mode Register -------- */ -#define PWM_CMP3M_CEN (0x1 << 0) /**< \brief (PWM_CMP3M) Comparison x Enable */ -#define PWM_CMP3M_CTR (0xf << 4) /**< \brief (PWM_CMP3M) Comparison x Trigger */ -#define PWM_CMP3M_CPR (0xf << 8) /**< \brief (PWM_CMP3M) Comparison x Period */ -#define PWM_CMP3M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP3M) Comparison x Period Counter */ -#define PWM_CMP3M_CUPR (0xf << 16) /**< \brief (PWM_CMP3M) Comparison x Update Period */ -#define PWM_CMP3M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP3M) Comparison x Update Period Counter */ -/* -------- PWM_CMP3MUPD : (PWM Offset: 0x16C) PWM Comparison 3 Mode Update Register -------- */ -#define PWM_CMP3MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP3MUPD) Comparison x Enable Update */ -#define PWM_CMP3MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP3MUPD) Comparison x Trigger Update */ -#define PWM_CMP3MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP3MUPD) Comparison x Period Update */ -#define PWM_CMP3MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP3MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP4V : (PWM Offset: 0x170) PWM Comparison 4 Value Register -------- */ -#define PWM_CMP4V_CV (0xffffff << 0) /**< \brief (PWM_CMP4V) Comparison x Value */ -#define PWM_CMP4V_CVM (0x1 << 24) /**< \brief (PWM_CMP4V) Comparison x Value Mode */ -/* -------- PWM_CMP4VUPD : (PWM Offset: 0x174) PWM Comparison 4 Value Update Register -------- */ -#define PWM_CMP4VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP4VUPD) Comparison x Value Update */ -#define PWM_CMP4VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP4VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP4M : (PWM Offset: 0x178) PWM Comparison 4 Mode Register -------- */ -#define PWM_CMP4M_CEN (0x1 << 0) /**< \brief (PWM_CMP4M) Comparison x Enable */ -#define PWM_CMP4M_CTR (0xf << 4) /**< \brief (PWM_CMP4M) Comparison x Trigger */ -#define PWM_CMP4M_CPR (0xf << 8) /**< \brief (PWM_CMP4M) Comparison x Period */ -#define PWM_CMP4M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP4M) Comparison x Period Counter */ -#define PWM_CMP4M_CUPR (0xf << 16) /**< \brief (PWM_CMP4M) Comparison x Update Period */ -#define PWM_CMP4M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP4M) Comparison x Update Period Counter */ -/* -------- PWM_CMP4MUPD : (PWM Offset: 0x17C) PWM Comparison 4 Mode Update Register -------- */ -#define PWM_CMP4MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP4MUPD) Comparison x Enable Update */ -#define PWM_CMP4MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP4MUPD) Comparison x Trigger Update */ -#define PWM_CMP4MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP4MUPD) Comparison x Period Update */ -#define PWM_CMP4MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP4MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP5V : (PWM Offset: 0x180) PWM Comparison 5 Value Register -------- */ -#define PWM_CMP5V_CV (0xffffff << 0) /**< \brief (PWM_CMP5V) Comparison x Value */ -#define PWM_CMP5V_CVM (0x1 << 24) /**< \brief (PWM_CMP5V) Comparison x Value Mode */ -/* -------- PWM_CMP5VUPD : (PWM Offset: 0x184) PWM Comparison 5 Value Update Register -------- */ -#define PWM_CMP5VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP5VUPD) Comparison x Value Update */ -#define PWM_CMP5VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP5VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP5M : (PWM Offset: 0x188) PWM Comparison 5 Mode Register -------- */ -#define PWM_CMP5M_CEN (0x1 << 0) /**< \brief (PWM_CMP5M) Comparison x Enable */ -#define PWM_CMP5M_CTR (0xf << 4) /**< \brief (PWM_CMP5M) Comparison x Trigger */ -#define PWM_CMP5M_CPR (0xf << 8) /**< \brief (PWM_CMP5M) Comparison x Period */ -#define PWM_CMP5M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP5M) Comparison x Period Counter */ -#define PWM_CMP5M_CUPR (0xf << 16) /**< \brief (PWM_CMP5M) Comparison x Update Period */ -#define PWM_CMP5M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP5M) Comparison x Update Period Counter */ -/* -------- PWM_CMP5MUPD : (PWM Offset: 0x18C) PWM Comparison 5 Mode Update Register -------- */ -#define PWM_CMP5MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP5MUPD) Comparison x Enable Update */ -#define PWM_CMP5MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP5MUPD) Comparison x Trigger Update */ -#define PWM_CMP5MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP5MUPD) Comparison x Period Update */ -#define PWM_CMP5MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP5MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP6V : (PWM Offset: 0x190) PWM Comparison 6 Value Register -------- */ -#define PWM_CMP6V_CV (0xffffff << 0) /**< \brief (PWM_CMP6V) Comparison x Value */ -#define PWM_CMP6V_CVM (0x1 << 24) /**< \brief (PWM_CMP6V) Comparison x Value Mode */ -/* -------- PWM_CMP6VUPD : (PWM Offset: 0x194) PWM Comparison 6 Value Update Register -------- */ -#define PWM_CMP6VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP6VUPD) Comparison x Value Update */ -#define PWM_CMP6VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP6VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP6M : (PWM Offset: 0x198) PWM Comparison 6 Mode Register -------- */ -#define PWM_CMP6M_CEN (0x1 << 0) /**< \brief (PWM_CMP6M) Comparison x Enable */ -#define PWM_CMP6M_CTR (0xf << 4) /**< \brief (PWM_CMP6M) Comparison x Trigger */ -#define PWM_CMP6M_CPR (0xf << 8) /**< \brief (PWM_CMP6M) Comparison x Period */ -#define PWM_CMP6M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP6M) Comparison x Period Counter */ -#define PWM_CMP6M_CUPR (0xf << 16) /**< \brief (PWM_CMP6M) Comparison x Update Period */ -#define PWM_CMP6M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP6M) Comparison x Update Period Counter */ -/* -------- PWM_CMP6MUPD : (PWM Offset: 0x19C) PWM Comparison 6 Mode Update Register -------- */ -#define PWM_CMP6MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP6MUPD) Comparison x Enable Update */ -#define PWM_CMP6MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP6MUPD) Comparison x Trigger Update */ -#define PWM_CMP6MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP6MUPD) Comparison x Period Update */ -#define PWM_CMP6MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP6MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP7V : (PWM Offset: 0x1A0) PWM Comparison 7 Value Register -------- */ -#define PWM_CMP7V_CV (0xffffff << 0) /**< \brief (PWM_CMP7V) Comparison x Value */ -#define PWM_CMP7V_CVM (0x1 << 24) /**< \brief (PWM_CMP7V) Comparison x Value Mode */ -/* -------- PWM_CMP7VUPD : (PWM Offset: 0x1A4) PWM Comparison 7 Value Update Register -------- */ -#define PWM_CMP7VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP7VUPD) Comparison x Value Update */ -#define PWM_CMP7VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP7VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP7M : (PWM Offset: 0x1A8) PWM Comparison 7 Mode Register -------- */ -#define PWM_CMP7M_CEN (0x1 << 0) /**< \brief (PWM_CMP7M) Comparison x Enable */ -#define PWM_CMP7M_CTR (0xf << 4) /**< \brief (PWM_CMP7M) Comparison x Trigger */ -#define PWM_CMP7M_CPR (0xf << 8) /**< \brief (PWM_CMP7M) Comparison x Period */ -#define PWM_CMP7M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP7M) Comparison x Period Counter */ -#define PWM_CMP7M_CUPR (0xf << 16) /**< \brief (PWM_CMP7M) Comparison x Update Period */ -#define PWM_CMP7M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP7M) Comparison x Update Period Counter */ -/* -------- PWM_CMP7MUPD : (PWM Offset: 0x1AC) PWM Comparison 7 Mode Update Register -------- */ -#define PWM_CMP7MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP7MUPD) Comparison x Enable Update */ -#define PWM_CMP7MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP7MUPD) Comparison x Trigger Update */ -#define PWM_CMP7MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP7MUPD) Comparison x Period Update */ -#define PWM_CMP7MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP7MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMR0 : (PWM Offset: 0x200) PWM Channel Mode Register (ch_num = 0) -------- */ -#define PWM_CMR0_CPRE (0xf << 0) /**< \brief (PWM_CMR0) Channel Pre-scaler */ -#define PWM_CMR0_CALG (0x1 << 8) /**< \brief (PWM_CMR0) Channel Alignment */ -#define PWM_CMR0_CPOL (0x1 << 9) /**< \brief (PWM_CMR0) Channel Polarity */ -#define PWM_CMR0_CES (0x1 << 10) /**< \brief (PWM_CMR0) Counter Event Selection */ -#define PWM_CMR0_DTE (0x1 << 16) /**< \brief (PWM_CMR0) Dead-Time Generator Enable */ -#define PWM_CMR0_DTHI (0x1 << 17) /**< \brief (PWM_CMR0) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR0_DTLI (0x1 << 18) /**< \brief (PWM_CMR0) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY0 : (PWM Offset: 0x204) PWM Channel Duty Cycle Register (ch_num = 0) -------- */ -#define PWM_CDTY0_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY0) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD0 : (PWM Offset: 0x208) PWM Channel Duty Cycle Update Register (ch_num = 0) -------- */ -#define PWM_CDTYUPD0_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD0) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD0 : (PWM Offset: 0x20C) PWM Channel Period Register (ch_num = 0) -------- */ -#define PWM_CPRD0_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD0) Channel Period */ -/* -------- PWM_CPRDUPD0 : (PWM Offset: 0x210) PWM Channel Period Update Register (ch_num = 0) -------- */ -#define PWM_CPRDUPD0_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD0) Channel Period Update */ -/* -------- PWM_CCNT0 : (PWM Offset: 0x214) PWM Channel Counter Register (ch_num = 0) -------- */ -#define PWM_CCNT0_CNT (0xffffff << 0) /**< \brief (PWM_CCNT0) Channel Counter Register */ -/* -------- PWM_DT0 : (PWM Offset: 0x218) PWM Channel Dead Time Register (ch_num = 0) -------- */ -#define PWM_DT0_DTH (0xffff << 0) /**< \brief (PWM_DT0) Dead-Time Value for PWMHx Output */ -#define PWM_DT0_DTL (0xffff << 16) /**< \brief (PWM_DT0) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD0 : (PWM Offset: 0x21C) PWM Channel Dead Time Update Register (ch_num = 0) -------- */ -#define PWM_DTUPD0_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD0) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD0_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD0) Dead-Time Value Update for PWMLx Output */ -/* -------- PWM_CMR1 : (PWM Offset: 0x220) PWM Channel Mode Register (ch_num = 1) -------- */ -#define PWM_CMR1_CPRE (0xf << 0) /**< \brief (PWM_CMR1) Channel Pre-scaler */ -#define PWM_CMR1_CALG (0x1 << 8) /**< \brief (PWM_CMR1) Channel Alignment */ -#define PWM_CMR1_CPOL (0x1 << 9) /**< \brief (PWM_CMR1) Channel Polarity */ -#define PWM_CMR1_CES (0x1 << 10) /**< \brief (PWM_CMR1) Counter Event Selection */ -#define PWM_CMR1_DTE (0x1 << 16) /**< \brief (PWM_CMR1) Dead-Time Generator Enable */ -#define PWM_CMR1_DTHI (0x1 << 17) /**< \brief (PWM_CMR1) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR1_DTLI (0x1 << 18) /**< \brief (PWM_CMR1) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY1 : (PWM Offset: 0x224) PWM Channel Duty Cycle Register (ch_num = 1) -------- */ -#define PWM_CDTY1_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY1) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD1 : (PWM Offset: 0x228) PWM Channel Duty Cycle Update Register (ch_num = 1) -------- */ -#define PWM_CDTYUPD1_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD1) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD1 : (PWM Offset: 0x22C) PWM Channel Period Register (ch_num = 1) -------- */ -#define PWM_CPRD1_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD1) Channel Period */ -/* -------- PWM_CPRDUPD1 : (PWM Offset: 0x230) PWM Channel Period Update Register (ch_num = 1) -------- */ -#define PWM_CPRDUPD1_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD1) Channel Period Update */ -/* -------- PWM_CCNT1 : (PWM Offset: 0x234) PWM Channel Counter Register (ch_num = 1) -------- */ -#define PWM_CCNT1_CNT (0xffffff << 0) /**< \brief (PWM_CCNT1) Channel Counter Register */ -/* -------- PWM_DT1 : (PWM Offset: 0x238) PWM Channel Dead Time Register (ch_num = 1) -------- */ -#define PWM_DT1_DTH (0xffff << 0) /**< \brief (PWM_DT1) Dead-Time Value for PWMHx Output */ -#define PWM_DT1_DTL (0xffff << 16) /**< \brief (PWM_DT1) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD1 : (PWM Offset: 0x23C) PWM Channel Dead Time Update Register (ch_num = 1) -------- */ -#define PWM_DTUPD1_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD1) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD1_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD1) Dead-Time Value Update for PWMLx Output */ -/* -------- PWM_CMR2 : (PWM Offset: 0x240) PWM Channel Mode Register (ch_num = 2) -------- */ -#define PWM_CMR2_CPRE (0xf << 0) /**< \brief (PWM_CMR2) Channel Pre-scaler */ -#define PWM_CMR2_CALG (0x1 << 8) /**< \brief (PWM_CMR2) Channel Alignment */ -#define PWM_CMR2_CPOL (0x1 << 9) /**< \brief (PWM_CMR2) Channel Polarity */ -#define PWM_CMR2_CES (0x1 << 10) /**< \brief (PWM_CMR2) Counter Event Selection */ -#define PWM_CMR2_DTE (0x1 << 16) /**< \brief (PWM_CMR2) Dead-Time Generator Enable */ -#define PWM_CMR2_DTHI (0x1 << 17) /**< \brief (PWM_CMR2) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR2_DTLI (0x1 << 18) /**< \brief (PWM_CMR2) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY2 : (PWM Offset: 0x244) PWM Channel Duty Cycle Register (ch_num = 2) -------- */ -#define PWM_CDTY2_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY2) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD2 : (PWM Offset: 0x248) PWM Channel Duty Cycle Update Register (ch_num = 2) -------- */ -#define PWM_CDTYUPD2_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD2) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD2 : (PWM Offset: 0x24C) PWM Channel Period Register (ch_num = 2) -------- */ -#define PWM_CPRD2_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD2) Channel Period */ -/* -------- PWM_CPRDUPD2 : (PWM Offset: 0x250) PWM Channel Period Update Register (ch_num = 2) -------- */ -#define PWM_CPRDUPD2_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD2) Channel Period Update */ -/* -------- PWM_CCNT2 : (PWM Offset: 0x254) PWM Channel Counter Register (ch_num = 2) -------- */ -#define PWM_CCNT2_CNT (0xffffff << 0) /**< \brief (PWM_CCNT2) Channel Counter Register */ -/* -------- PWM_DT2 : (PWM Offset: 0x258) PWM Channel Dead Time Register (ch_num = 2) -------- */ -#define PWM_DT2_DTH (0xffff << 0) /**< \brief (PWM_DT2) Dead-Time Value for PWMHx Output */ -#define PWM_DT2_DTL (0xffff << 16) /**< \brief (PWM_DT2) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD2 : (PWM Offset: 0x25C) PWM Channel Dead Time Update Register (ch_num = 2) -------- */ -#define PWM_DTUPD2_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD2) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD2_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD2) Dead-Time Value Update for PWMLx Output */ -/* -------- PWM_CMR3 : (PWM Offset: 0x260) PWM Channel Mode Register (ch_num = 3) -------- */ -#define PWM_CMR3_CPRE (0xf << 0) /**< \brief (PWM_CMR3) Channel Pre-scaler */ -#define PWM_CMR3_CALG (0x1 << 8) /**< \brief (PWM_CMR3) Channel Alignment */ -#define PWM_CMR3_CPOL (0x1 << 9) /**< \brief (PWM_CMR3) Channel Polarity */ -#define PWM_CMR3_CES (0x1 << 10) /**< \brief (PWM_CMR3) Counter Event Selection */ -#define PWM_CMR3_DTE (0x1 << 16) /**< \brief (PWM_CMR3) Dead-Time Generator Enable */ -#define PWM_CMR3_DTHI (0x1 << 17) /**< \brief (PWM_CMR3) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR3_DTLI (0x1 << 18) /**< \brief (PWM_CMR3) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY3 : (PWM Offset: 0x264) PWM Channel Duty Cycle Register (ch_num = 3) -------- */ -#define PWM_CDTY3_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY3) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD3 : (PWM Offset: 0x268) PWM Channel Duty Cycle Update Register (ch_num = 3) -------- */ -#define PWM_CDTYUPD3_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD3) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD3 : (PWM Offset: 0x26C) PWM Channel Period Register (ch_num = 3) -------- */ -#define PWM_CPRD3_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD3) Channel Period */ -/* -------- PWM_CPRDUPD3 : (PWM Offset: 0x270) PWM Channel Period Update Register (ch_num = 3) -------- */ -#define PWM_CPRDUPD3_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD3) Channel Period Update */ -/* -------- PWM_CCNT3 : (PWM Offset: 0x274) PWM Channel Counter Register (ch_num = 3) -------- */ -#define PWM_CCNT3_CNT (0xffffff << 0) /**< \brief (PWM_CCNT3) Channel Counter Register */ -/* -------- PWM_DT3 : (PWM Offset: 0x278) PWM Channel Dead Time Register (ch_num = 3) -------- */ -#define PWM_DT3_DTH (0xffff << 0) /**< \brief (PWM_DT3) Dead-Time Value for PWMHx Output */ -#define PWM_DT3_DTL (0xffff << 16) /**< \brief (PWM_DT3) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD3 : (PWM Offset: 0x27C) PWM Channel Dead Time Update Register (ch_num = 3) -------- */ -#define PWM_DTUPD3_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD3) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD3_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD3) Dead-Time Value Update for PWMLx Output */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Reset Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_RSTC Reset Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Rstc hardware registers */ -typedef struct { - WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */ - RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */ - RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */ -} Rstc; -#endif /* __ASSEMBLY__ */ -/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ -#define RSTC_CR_PROCRST (0x1 << 0) /**< \brief (RSTC_CR) Processor Reset */ -#define RSTC_CR_PERRST (0x1 << 2) /**< \brief (RSTC_CR) Peripheral Reset */ -#define RSTC_CR_EXTRST (0x1 << 3) /**< \brief (RSTC_CR) External Reset */ -#define RSTC_CR_KEY (0xff << 24) /**< \brief (RSTC_CR) Password */ -/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ -#define RSTC_SR_URSTS (0x1 << 0) /**< \brief (RSTC_SR) User Reset Status */ -#define RSTC_SR_RSTTYP (0x7 << 8) /**< \brief (RSTC_SR) Reset Type */ -#define RSTC_SR_NRSTL (0x1 << 16) /**< \brief (RSTC_SR) NRST Pin Level */ -#define RSTC_SR_SRCMP (0x1 << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ -/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ -#define RSTC_MR_URSTEN (0x1 << 0) /**< \brief (RSTC_MR) User Reset Enable */ -#define RSTC_MR_URSTIEN (0x1 << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */ -#define RSTC_MR_ERSTL (0xf << 8) /**< \brief (RSTC_MR) External Reset Length */ -#define RSTC_MR_KEY (0xff << 24) /**< \brief (RSTC_MR) Password */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Real-time Clock */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_RTC Real-time Clock */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Rtc hardware registers */ -typedef struct { - RwReg RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */ - RwReg RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */ - RwReg RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */ - RwReg RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */ - RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */ - RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */ - RoReg RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */ - WoReg RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */ - WoReg RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */ - WoReg RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */ - RoReg RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */ - RoReg RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */ -} Rtc; -#endif /* __ASSEMBLY__ */ -/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */ -#define RTC_CR_UPDTIM (0x1 << 0) /**< \brief (RTC_CR) Update Request Time Register */ -#define RTC_CR_UPDCAL (0x1 << 1) /**< \brief (RTC_CR) Update Request Calendar Register */ -#define RTC_CR_TIMEVSEL (0x3 << 8) /**< \brief (RTC_CR) Time Event Selection */ -#define RTC_CR_TIMEVSEL_MINUTE (0x0 << 8) /**< \brief (RTC_CR) Minute change. */ -#define RTC_CR_TIMEVSEL_HOUR (0x1 << 8) /**< \brief (RTC_CR) Hour change. */ -#define RTC_CR_TIMEVSEL_DAY24 (0x2 << 8) /**< \brief (RTC_CR) Every day at midnight. */ -#define RTC_CR_TIMEVSEL_DAY12 (0x3 << 8) /**< \brief (RTC_CR) Every day at noon. */ -#define RTC_CR_CALEVSEL (0x3 << 16) /**< \brief (RTC_CR) Calendar Event Selection */ -#define RTC_CR_CALEVSEL_WEEK (0x0 << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00). */ -#define RTC_CR_CALEVSEL_MONTH (0x1 << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00). */ -/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */ -#define RTC_MR_HRMOD (0x1 << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */ -/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */ -#define RTC_TIMR_SEC (0x7f << 0) /**< \brief (RTC_TIMR) Current Second */ -#define RTC_TIMR_MIN (0x7f << 8) /**< \brief (RTC_TIMR) Current Minute */ -#define RTC_TIMR_HOUR (0x3f << 16) /**< \brief (RTC_TIMR) Current Hour */ -#define RTC_TIMR_AMPM (0x1 << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */ -/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */ -#define RTC_CALR_CENT (0x7f << 0) /**< \brief (RTC_CALR) Current Century */ -#define RTC_CALR_YEAR (0xff << 8) /**< \brief (RTC_CALR) Current Year */ -#define RTC_CALR_MONTH (0x1f << 16) /**< \brief (RTC_CALR) Current Month */ -#define RTC_CALR_DAY (0x7 << 21) /**< \brief (RTC_CALR) Current Day in Current Week */ -#define RTC_CALR_DATE (0x3f << 24) /**< \brief (RTC_CALR) Current Day in Current Month */ -/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */ -#define RTC_TIMALR_SEC (0x7f << 0) /**< \brief (RTC_TIMALR) Second Alarm */ -#define RTC_TIMALR_SECEN (0x1 << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */ -#define RTC_TIMALR_MIN (0x7f << 8) /**< \brief (RTC_TIMALR) Minute Alarm */ -#define RTC_TIMALR_MINEN (0x1 << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */ -#define RTC_TIMALR_HOUR (0x3f << 16) /**< \brief (RTC_TIMALR) Hour Alarm */ -#define RTC_TIMALR_AMPM (0x1 << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */ -#define RTC_TIMALR_HOUREN (0x1 << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */ -/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */ -#define RTC_CALALR_MONTH (0x1f << 16) /**< \brief (RTC_CALALR) Month Alarm */ -#define RTC_CALALR_MTHEN (0x1 << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */ -#define RTC_CALALR_DATE (0x3f << 24) /**< \brief (RTC_CALALR) Date Alarm */ -#define RTC_CALALR_DATEEN (0x1 << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */ -/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */ -#define RTC_SR_ACKUPD (0x1 << 0) /**< \brief (RTC_SR) Acknowledge for Update */ -#define RTC_SR_ALARM (0x1 << 1) /**< \brief (RTC_SR) Alarm Flag */ -#define RTC_SR_SEC (0x1 << 2) /**< \brief (RTC_SR) Second Event */ -#define RTC_SR_TIMEV (0x1 << 3) /**< \brief (RTC_SR) Time Event */ -#define RTC_SR_CALEV (0x1 << 4) /**< \brief (RTC_SR) Calendar Event */ -/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */ -#define RTC_SCCR_ACKCLR (0x1 << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */ -#define RTC_SCCR_ALRCLR (0x1 << 1) /**< \brief (RTC_SCCR) Alarm Clear */ -#define RTC_SCCR_SECCLR (0x1 << 2) /**< \brief (RTC_SCCR) Second Clear */ -#define RTC_SCCR_TIMCLR (0x1 << 3) /**< \brief (RTC_SCCR) Time Clear */ -#define RTC_SCCR_CALCLR (0x1 << 4) /**< \brief (RTC_SCCR) Calendar Clear */ -/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */ -#define RTC_IER_ACKEN (0x1 << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */ -#define RTC_IER_ALREN (0x1 << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */ -#define RTC_IER_SECEN (0x1 << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */ -#define RTC_IER_TIMEN (0x1 << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */ -#define RTC_IER_CALEN (0x1 << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */ -/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */ -#define RTC_IDR_ACKDIS (0x1 << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */ -#define RTC_IDR_ALRDIS (0x1 << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */ -#define RTC_IDR_SECDIS (0x1 << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */ -#define RTC_IDR_TIMDIS (0x1 << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */ -#define RTC_IDR_CALDIS (0x1 << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */ -/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */ -#define RTC_IMR_ACK (0x1 << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */ -#define RTC_IMR_ALR (0x1 << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */ -#define RTC_IMR_SEC (0x1 << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */ -#define RTC_IMR_TIM (0x1 << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */ -#define RTC_IMR_CAL (0x1 << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */ -/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */ -#define RTC_VER_NVTIM (0x1 << 0) /**< \brief (RTC_VER) Non-valid Time */ -#define RTC_VER_NVCAL (0x1 << 1) /**< \brief (RTC_VER) Non-valid Calendar */ -#define RTC_VER_NVTIMALR (0x1 << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */ -#define RTC_VER_NVCALALR (0x1 << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Real-time Timer */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_RTT Real-time Timer */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Rtt hardware registers */ -typedef struct { - RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */ - RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */ - RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */ - RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */ -} Rtt; -#endif /* __ASSEMBLY__ */ -/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */ -#define RTT_MR_RTPRES (0xffff << 0) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */ -#define RTT_MR_ALMIEN (0x1 << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */ -#define RTT_MR_RTTINCIEN (0x1 << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */ -#define RTT_MR_RTTRST (0x1 << 18) /**< \brief (RTT_MR) Real-time Timer Restart */ -/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */ -#define RTT_AR_ALMV (0xffffffff << 0) /**< \brief (RTT_AR) Alarm Value */ -/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */ -#define RTT_VR_CRTV (0xffffffff << 0) /**< \brief (RTT_VR) Current Real-time Value */ -/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */ -#define RTT_SR_ALMS (0x1 << 0) /**< \brief (RTT_SR) Real-time Alarm Status */ -#define RTT_SR_RTTINC (0x1 << 1) /**< \brief (RTT_SR) Real-time Timer Increment */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Static Memory Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_SMC Static Memory Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief SmcCs_number hardware registers */ -typedef struct { - RwReg SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */ - RwReg SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */ - RwReg SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */ - RwReg SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC Mode Register */ -} SmcCs_number; -/** \brief Smc hardware registers */ -typedef struct { - SmcCs_number SMC_CS_NUMBER[5]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 4 */ - RwReg Reserved1[12]; - RwReg SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */ - WoReg SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */ - WoReg SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */ - RwReg Reserved2[22]; - RwReg SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protect Mode Register */ - RoReg SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protect Status Register */ -} Smc; -#endif /* __ASSEMBLY__ */ -/* -------- SMC_SETUP0 : (SMC Offset: 0x0) SMC Setup Register (CS_number = 0) -------- */ -#define SMC_SETUP0_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP0) NWE Setup Length */ -#define SMC_SETUP0_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP0) NCS Setup Length in WRITE Access */ -#define SMC_SETUP0_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP0) NRD Setup Length */ -#define SMC_SETUP0_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP0) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE0 : (SMC Offset: 0x4) SMC Pulse Register (CS_number = 0) -------- */ -#define SMC_PULSE0_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE0) NWE Pulse Length */ -#define SMC_PULSE0_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE0) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE0_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE0) NRD Pulse Length */ -#define SMC_PULSE0_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE0) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE0 : (SMC Offset: 0x8) SMC Cycle Register (CS_number = 0) -------- */ -#define SMC_CYCLE0_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE0) Total Write Cycle Length */ -#define SMC_CYCLE0_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE0) Total Read Cycle Length */ -/* -------- SMC_MODE0 : (SMC Offset: 0xC) SMC Mode Register (CS_number = 0) -------- */ -#define SMC_MODE0_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE0) */ -#define SMC_MODE0_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE0) */ -#define SMC_MODE0_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE0) NWAIT Mode */ -#define SMC_MODE0_DBW (0x3 << 12) /**< \brief (SMC_MODE0) Data Bus Width */ -#define SMC_MODE0_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE0) Data Float Time */ -#define SMC_MODE0_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE0) TDF Optimization */ -#define SMC_MODE0_PMEN (0x1 << 24) /**< \brief (SMC_MODE0) Page Mode Enabled */ -#define SMC_MODE0_PS (0x3 << 28) /**< \brief (SMC_MODE0) Page Size */ -/* -------- SMC_SETUP1 : (SMC Offset: 0x10) SMC Setup Register (CS_number = 1) -------- */ -#define SMC_SETUP1_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP1) NWE Setup Length */ -#define SMC_SETUP1_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP1) NCS Setup Length in WRITE Access */ -#define SMC_SETUP1_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP1) NRD Setup Length */ -#define SMC_SETUP1_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP1) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE1 : (SMC Offset: 0x14) SMC Pulse Register (CS_number = 1) -------- */ -#define SMC_PULSE1_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE1) NWE Pulse Length */ -#define SMC_PULSE1_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE1) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE1_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE1) NRD Pulse Length */ -#define SMC_PULSE1_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE1) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE1 : (SMC Offset: 0x18) SMC Cycle Register (CS_number = 1) -------- */ -#define SMC_CYCLE1_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE1) Total Write Cycle Length */ -#define SMC_CYCLE1_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE1) Total Read Cycle Length */ -/* -------- SMC_MODE1 : (SMC Offset: 0x1C) SMC Mode Register (CS_number = 1) -------- */ -#define SMC_MODE1_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE1) */ -#define SMC_MODE1_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE1) */ -#define SMC_MODE1_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE1) NWAIT Mode */ -#define SMC_MODE1_DBW (0x3 << 12) /**< \brief (SMC_MODE1) Data Bus Width */ -#define SMC_MODE1_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE1) Data Float Time */ -#define SMC_MODE1_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE1) TDF Optimization */ -#define SMC_MODE1_PMEN (0x1 << 24) /**< \brief (SMC_MODE1) Page Mode Enabled */ -#define SMC_MODE1_PS (0x3 << 28) /**< \brief (SMC_MODE1) Page Size */ -/* -------- SMC_SETUP2 : (SMC Offset: 0x20) SMC Setup Register (CS_number = 2) -------- */ -#define SMC_SETUP2_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP2) NWE Setup Length */ -#define SMC_SETUP2_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP2) NCS Setup Length in WRITE Access */ -#define SMC_SETUP2_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP2) NRD Setup Length */ -#define SMC_SETUP2_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP2) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE2 : (SMC Offset: 0x24) SMC Pulse Register (CS_number = 2) -------- */ -#define SMC_PULSE2_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE2) NWE Pulse Length */ -#define SMC_PULSE2_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE2) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE2_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE2) NRD Pulse Length */ -#define SMC_PULSE2_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE2) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE2 : (SMC Offset: 0x28) SMC Cycle Register (CS_number = 2) -------- */ -#define SMC_CYCLE2_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE2) Total Write Cycle Length */ -#define SMC_CYCLE2_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE2) Total Read Cycle Length */ -/* -------- SMC_MODE2 : (SMC Offset: 0x2C) SMC Mode Register (CS_number = 2) -------- */ -#define SMC_MODE2_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE2) */ -#define SMC_MODE2_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE2) */ -#define SMC_MODE2_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE2) NWAIT Mode */ -#define SMC_MODE2_DBW (0x3 << 12) /**< \brief (SMC_MODE2) Data Bus Width */ -#define SMC_MODE2_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE2) Data Float Time */ -#define SMC_MODE2_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE2) TDF Optimization */ -#define SMC_MODE2_PMEN (0x1 << 24) /**< \brief (SMC_MODE2) Page Mode Enabled */ -#define SMC_MODE2_PS (0x3 << 28) /**< \brief (SMC_MODE2) Page Size */ -/* -------- SMC_SETUP3 : (SMC Offset: 0x30) SMC Setup Register (CS_number = 3) -------- */ -#define SMC_SETUP3_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP3) NWE Setup Length */ -#define SMC_SETUP3_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP3) NCS Setup Length in WRITE Access */ -#define SMC_SETUP3_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP3) NRD Setup Length */ -#define SMC_SETUP3_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP3) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE3 : (SMC Offset: 0x34) SMC Pulse Register (CS_number = 3) -------- */ -#define SMC_PULSE3_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE3) NWE Pulse Length */ -#define SMC_PULSE3_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE3) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE3_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE3) NRD Pulse Length */ -#define SMC_PULSE3_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE3) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE3 : (SMC Offset: 0x38) SMC Cycle Register (CS_number = 3) -------- */ -#define SMC_CYCLE3_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE3) Total Write Cycle Length */ -#define SMC_CYCLE3_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE3) Total Read Cycle Length */ -/* -------- SMC_MODE3 : (SMC Offset: 0x3C) SMC Mode Register (CS_number = 3) -------- */ -#define SMC_MODE3_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE3) */ -#define SMC_MODE3_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE3) */ -#define SMC_MODE3_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE3) NWAIT Mode */ -#define SMC_MODE3_DBW (0x3 << 12) /**< \brief (SMC_MODE3) Data Bus Width */ -#define SMC_MODE3_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE3) Data Float Time */ -#define SMC_MODE3_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE3) TDF Optimization */ -#define SMC_MODE3_PMEN (0x1 << 24) /**< \brief (SMC_MODE3) Page Mode Enabled */ -#define SMC_MODE3_PS (0x3 << 28) /**< \brief (SMC_MODE3) Page Size */ -/* -------- SMC_SETUP4 : (SMC Offset: 0x40) SMC Setup Register (CS_number = 4) -------- */ -#define SMC_SETUP4_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP4) NWE Setup Length */ -#define SMC_SETUP4_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP4) NCS Setup Length in WRITE Access */ -#define SMC_SETUP4_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP4) NRD Setup Length */ -#define SMC_SETUP4_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP4) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE4 : (SMC Offset: 0x44) SMC Pulse Register (CS_number = 4) -------- */ -#define SMC_PULSE4_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE4) NWE Pulse Length */ -#define SMC_PULSE4_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE4) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE4_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE4) NRD Pulse Length */ -#define SMC_PULSE4_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE4) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE4 : (SMC Offset: 0x48) SMC Cycle Register (CS_number = 4) -------- */ -#define SMC_CYCLE4_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE4) Total Write Cycle Length */ -#define SMC_CYCLE4_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE4) Total Read Cycle Length */ -/* -------- SMC_MODE4 : (SMC Offset: 0x4C) SMC Mode Register (CS_number = 4) -------- */ -#define SMC_MODE4_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE4) */ -#define SMC_MODE4_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE4) */ -#define SMC_MODE4_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE4) NWAIT Mode */ -#define SMC_MODE4_DBW (0x3 << 12) /**< \brief (SMC_MODE4) Data Bus Width */ -#define SMC_MODE4_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE4) Data Float Time */ -#define SMC_MODE4_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE4) TDF Optimization */ -#define SMC_MODE4_PMEN (0x1 << 24) /**< \brief (SMC_MODE4) Page Mode Enabled */ -#define SMC_MODE4_PS (0x3 << 28) /**< \brief (SMC_MODE4) Page Size */ -/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */ -#define SMC_OCMS_SMSE (0x1 << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */ -#define SMC_OCMS_CS0SE (0x1 << 16) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -#define SMC_OCMS_CS1SE (0x1 << 17) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -#define SMC_OCMS_CS2SE (0x1 << 18) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -#define SMC_OCMS_CS3SE (0x1 << 19) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */ -#define SMC_KEY1_KEY1 (0xffffffff << 0) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */ -/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */ -#define SMC_KEY2_KEY2 (0xffffffff << 0) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */ -/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protect Mode Register -------- */ -#define SMC_WPMR_WPEN (0x1 << 0) /**< \brief (SMC_WPMR) Write Protect Enable */ -#define SMC_WPMR_WPKEY (0xffffff << 8) /**< \brief (SMC_WPMR) Write Protect KEY */ -/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protect Status Register -------- */ -#define SMC_WPSR_WPVS (0x1 << 0) /**< \brief (SMC_WPSR) Write Protect Enable */ -#define SMC_WPSR_WPVSRC (0xffff << 8) /**< \brief (SMC_WPSR) Write Protect Violation Source */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_SPI Serial Peripheral Interface */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Spi hardware registers */ -typedef struct { - WoReg SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */ - RwReg SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */ - RoReg SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */ - WoReg SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */ - RoReg SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */ - WoReg SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */ - WoReg SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */ - RoReg SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */ - RwReg Reserved1[4]; - RwReg SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */ - RwReg Reserved2[41]; - RwReg SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */ - RoReg SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */ - RwReg Reserved3[5]; - RwReg SPI_RPR; /**< \brief (Spi Offset: 0x100) Receive Pointer Register */ - RwReg SPI_RCR; /**< \brief (Spi Offset: 0x104) Receive Counter Register */ - RwReg SPI_TPR; /**< \brief (Spi Offset: 0x108) Transmit Pointer Register */ - RwReg SPI_TCR; /**< \brief (Spi Offset: 0x10C) Transmit Counter Register */ - RwReg SPI_RNPR; /**< \brief (Spi Offset: 0x110) Receive Next Pointer Register */ - RwReg SPI_RNCR; /**< \brief (Spi Offset: 0x114) Receive Next Counter Register */ - RwReg SPI_TNPR; /**< \brief (Spi Offset: 0x118) Transmit Next Pointer Register */ - RwReg SPI_TNCR; /**< \brief (Spi Offset: 0x11C) Transmit Next Counter Register */ - WoReg SPI_PTCR; /**< \brief (Spi Offset: 0x120) Transfer Control Register */ - RoReg SPI_PTSR; /**< \brief (Spi Offset: 0x124) Transfer Status Register */ -} Spi; -#endif /* __ASSEMBLY__ */ -/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */ -#define SPI_CR_SPIEN (0x1 << 0) /**< \brief (SPI_CR) SPI Enable */ -#define SPI_CR_SPIDIS (0x1 << 1) /**< \brief (SPI_CR) SPI Disable */ -#define SPI_CR_SWRST (0x1 << 7) /**< \brief (SPI_CR) SPI Software Reset */ -#define SPI_CR_LASTXFER (0x1 << 24) /**< \brief (SPI_CR) Last Transfer */ -/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */ -#define SPI_MR_MSTR (0x1 << 0) /**< \brief (SPI_MR) Master/Slave Mode */ -#define SPI_MR_PS (0x1 << 1) /**< \brief (SPI_MR) Peripheral Select */ -#define SPI_MR_PS_FIXED (0x0 << 1) /**< \brief (SPI_MR) Fixed Peripheral Select. */ -#define SPI_MR_PS_VARIABLE (0x1 << 1) /**< \brief (SPI_MR) Variable Peripheral Select. */ -#define SPI_MR_PCSDEC (0x1 << 2) /**< \brief (SPI_MR) Chip Select Decode */ -#define SPI_MR_MODFDIS (0x1 << 4) /**< \brief (SPI_MR) Mode Fault Detection */ -#define SPI_MR_WDRBT (0x1 << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */ -#define SPI_MR_LLB (0x1 << 7) /**< \brief (SPI_MR) Local Loopback Enable */ -#define SPI_MR_PCS (0xf << 16) /**< \brief (SPI_MR) Peripheral Chip Select */ -#define SPI_MR_DLYBCS (0xff << 24) /**< \brief (SPI_MR) Delay Between Chip Selects */ -/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */ -#define SPI_RDR_RD (0xffff << 0) /**< \brief (SPI_RDR) Receive Data */ -#define SPI_RDR_PCS (0xf << 16) /**< \brief (SPI_RDR) Peripheral Chip Select */ -/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */ -#define SPI_TDR_TD (0xffff << 0) /**< \brief (SPI_TDR) Transmit Data */ -#define SPI_TDR_PCS (0xf << 16) /**< \brief (SPI_TDR) Peripheral Chip Select */ -#define SPI_TDR_LASTXFER (0x1 << 24) /**< \brief (SPI_TDR) Last Transfer */ -/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ -#define SPI_SR_RDRF (0x1 << 0) /**< \brief (SPI_SR) Receive Data Register Full */ -#define SPI_SR_TDRE (0x1 << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */ -#define SPI_SR_MODF (0x1 << 2) /**< \brief (SPI_SR) Mode Fault Error */ -#define SPI_SR_OVRES (0x1 << 3) /**< \brief (SPI_SR) Overrun Error Status */ -#define SPI_SR_ENDRX (0x1 << 4) /**< \brief (SPI_SR) End of RX buffer */ -#define SPI_SR_ENDTX (0x1 << 5) /**< \brief (SPI_SR) End of TX buffer */ -#define SPI_SR_RXBUFF (0x1 << 6) /**< \brief (SPI_SR) RX Buffer Full */ -#define SPI_SR_TXBUFE (0x1 << 7) /**< \brief (SPI_SR) TX Buffer Empty */ -#define SPI_SR_NSSR (0x1 << 8) /**< \brief (SPI_SR) NSS Rising */ -#define SPI_SR_TXEMPTY (0x1 << 9) /**< \brief (SPI_SR) Transmission Registers Empty */ -#define SPI_SR_UNDES (0x1 << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */ -#define SPI_SR_SPIENS (0x1 << 16) /**< \brief (SPI_SR) SPI Enable Status */ -/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ -#define SPI_IER_RDRF (0x1 << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */ -#define SPI_IER_TDRE (0x1 << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */ -#define SPI_IER_MODF (0x1 << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */ -#define SPI_IER_OVRES (0x1 << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */ -#define SPI_IER_ENDRX (0x1 << 4) /**< \brief (SPI_IER) End of Receive Buffer Interrupt Enable */ -#define SPI_IER_ENDTX (0x1 << 5) /**< \brief (SPI_IER) End of Transmit Buffer Interrupt Enable */ -#define SPI_IER_RXBUFF (0x1 << 6) /**< \brief (SPI_IER) Receive Buffer Full Interrupt Enable */ -#define SPI_IER_TXBUFE (0x1 << 7) /**< \brief (SPI_IER) Transmit Buffer Empty Interrupt Enable */ -#define SPI_IER_NSSR (0x1 << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */ -#define SPI_IER_TXEMPTY (0x1 << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */ -#define SPI_IER_UNDES (0x1 << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */ -/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ -#define SPI_IDR_RDRF (0x1 << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */ -#define SPI_IDR_TDRE (0x1 << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */ -#define SPI_IDR_MODF (0x1 << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */ -#define SPI_IDR_OVRES (0x1 << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */ -#define SPI_IDR_ENDRX (0x1 << 4) /**< \brief (SPI_IDR) End of Receive Buffer Interrupt Disable */ -#define SPI_IDR_ENDTX (0x1 << 5) /**< \brief (SPI_IDR) End of Transmit Buffer Interrupt Disable */ -#define SPI_IDR_RXBUFF (0x1 << 6) /**< \brief (SPI_IDR) Receive Buffer Full Interrupt Disable */ -#define SPI_IDR_TXBUFE (0x1 << 7) /**< \brief (SPI_IDR) Transmit Buffer Empty Interrupt Disable */ -#define SPI_IDR_NSSR (0x1 << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */ -#define SPI_IDR_TXEMPTY (0x1 << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */ -#define SPI_IDR_UNDES (0x1 << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */ -/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */ -#define SPI_IMR_RDRF (0x1 << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */ -#define SPI_IMR_TDRE (0x1 << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */ -#define SPI_IMR_MODF (0x1 << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */ -#define SPI_IMR_OVRES (0x1 << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */ -#define SPI_IMR_ENDRX (0x1 << 4) /**< \brief (SPI_IMR) End of Receive Buffer Interrupt Mask */ -#define SPI_IMR_ENDTX (0x1 << 5) /**< \brief (SPI_IMR) End of Transmit Buffer Interrupt Mask */ -#define SPI_IMR_RXBUFF (0x1 << 6) /**< \brief (SPI_IMR) Receive Buffer Full Interrupt Mask */ -#define SPI_IMR_TXBUFE (0x1 << 7) /**< \brief (SPI_IMR) Transmit Buffer Empty Interrupt Mask */ -#define SPI_IMR_NSSR (0x1 << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */ -#define SPI_IMR_TXEMPTY (0x1 << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */ -#define SPI_IMR_UNDES (0x1 << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */ -/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */ -#define SPI_CSR_CPOL (0x1 << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */ -#define SPI_CSR_NCPHA (0x1 << 1) /**< \brief (SPI_CSR[4]) Clock Phase */ -#define SPI_CSR_CSNAAT (0x1 << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ -#define SPI_CSR_CSAAT (0x1 << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ -#define SPI_CSR_BITS (0xf << 4) /**< \brief (SPI_CSR[4]) Bits Per Transfer (See the (Note:) below the register table; Section 9.9 "SPI Chip Select Register" on page 35.) */ -#define SPI_CSR_BITS_8 (0x0 << 4) /**< \brief (SPI_CSR[4]) 8 */ -#define SPI_CSR_BITS_9 (0x1 << 4) /**< \brief (SPI_CSR[4]) 9 */ -#define SPI_CSR_BITS_10 (0x2 << 4) /**< \brief (SPI_CSR[4]) 10 */ -#define SPI_CSR_BITS_11 (0x3 << 4) /**< \brief (SPI_CSR[4]) 11 */ -#define SPI_CSR_BITS_12 (0x4 << 4) /**< \brief (SPI_CSR[4]) 12 */ -#define SPI_CSR_BITS_13 (0x5 << 4) /**< \brief (SPI_CSR[4]) 13 */ -#define SPI_CSR_BITS_14 (0x6 << 4) /**< \brief (SPI_CSR[4]) 14 */ -#define SPI_CSR_BITS_15 (0x7 << 4) /**< \brief (SPI_CSR[4]) 15 */ -#define SPI_CSR_BITS_16 (0x8 << 4) /**< \brief (SPI_CSR[4]) 16 */ -#define SPI_CSR_SCBR (0xff << 8) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */ -#define SPI_CSR_DLYBS (0xff << 16) /**< \brief (SPI_CSR[4]) Delay Before SPCK */ -#define SPI_CSR_DLYBCT (0xff << 24) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */ -/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */ -#define SPI_WPMR_SPIWPEN (0x1 << 0) /**< \brief (SPI_WPMR) SPI Write Protection Enable */ -#define SPI_WPMR_SPIWPKEY (0xffffff << 8) /**< \brief (SPI_WPMR) SPI Write Protection Key Password */ -/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */ -#define SPI_WPSR_SPIWPVS (0x7 << 0) /**< \brief (SPI_WPSR) SPI Write Protection Violation Status */ -#define SPI_WPSR_SPIWPVSRC (0xff << 8) /**< \brief (SPI_WPSR) SPI Write Protection Violation Source */ -/* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */ -#define SPI_RPR_RXPTR (0xffffffff << 0) /**< \brief (SPI_RPR) Receive Pointer Register */ -/* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */ -#define SPI_RCR_RXCTR (0xffff << 0) /**< \brief (SPI_RCR) Receive Counter Register */ -/* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */ -#define SPI_TPR_TXPTR (0xffffffff << 0) /**< \brief (SPI_TPR) Transmit Counter Register */ -/* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */ -#define SPI_TCR_TXCTR (0xffff << 0) /**< \brief (SPI_TCR) Transmit Counter Register */ -/* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */ -#define SPI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (SPI_RNPR) Receive Next Pointer */ -/* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */ -#define SPI_RNCR_RXNCTR (0xffff << 0) /**< \brief (SPI_RNCR) Receive Next Counter */ -/* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */ -#define SPI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (SPI_TNPR) Transmit Next Pointer */ -/* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */ -#define SPI_TNCR_TXNCTR (0xffff << 0) /**< \brief (SPI_TNCR) Transmit Counter Next */ -/* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */ -#define SPI_PTCR_RXTEN (0x1 << 0) /**< \brief (SPI_PTCR) Receiver Transfer Enable */ -#define SPI_PTCR_RXTDIS (0x1 << 1) /**< \brief (SPI_PTCR) Receiver Transfer Disable */ -#define SPI_PTCR_TXTEN (0x1 << 8) /**< \brief (SPI_PTCR) Transmitter Transfer Enable */ -#define SPI_PTCR_TXTDIS (0x1 << 9) /**< \brief (SPI_PTCR) Transmitter Transfer Disable */ -/* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */ -#define SPI_PTSR_RXTEN (0x1 << 0) /**< \brief (SPI_PTSR) Receiver Transfer Enable */ -#define SPI_PTSR_TXTEN (0x1 << 8) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_SSC Synchronous Serial Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Ssc hardware registers */ -typedef struct { - WoReg SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */ - RwReg SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */ - RwReg Reserved1[2]; - RwReg SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */ - RwReg SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */ - RwReg SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */ - RwReg SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */ - RoReg SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */ - WoReg SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */ - RwReg Reserved2[2]; - RoReg SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */ - RwReg SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */ - RwReg SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */ - RwReg SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */ - RoReg SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */ - WoReg SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */ - WoReg SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */ - RoReg SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */ - RwReg Reserved3[37]; - RwReg SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */ - RoReg SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */ - RwReg Reserved4[5]; - RwReg SSC_RPR; /**< \brief (Ssc Offset: 0x100) Receive Pointer Register */ - RwReg SSC_RCR; /**< \brief (Ssc Offset: 0x104) Receive Counter Register */ - RwReg SSC_TPR; /**< \brief (Ssc Offset: 0x108) Transmit Pointer Register */ - RwReg SSC_TCR; /**< \brief (Ssc Offset: 0x10C) Transmit Counter Register */ - RwReg SSC_RNPR; /**< \brief (Ssc Offset: 0x110) Receive Next Pointer Register */ - RwReg SSC_RNCR; /**< \brief (Ssc Offset: 0x114) Receive Next Counter Register */ - RwReg SSC_TNPR; /**< \brief (Ssc Offset: 0x118) Transmit Next Pointer Register */ - RwReg SSC_TNCR; /**< \brief (Ssc Offset: 0x11C) Transmit Next Counter Register */ - WoReg SSC_PTCR; /**< \brief (Ssc Offset: 0x120) Transfer Control Register */ - RoReg SSC_PTSR; /**< \brief (Ssc Offset: 0x124) Transfer Status Register */ -} Ssc; -#endif /* __ASSEMBLY__ */ -/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */ -#define SSC_CR_RXEN (0x1 << 0) /**< \brief (SSC_CR) Receive Enable */ -#define SSC_CR_RXDIS (0x1 << 1) /**< \brief (SSC_CR) Receive Disable */ -#define SSC_CR_TXEN (0x1 << 8) /**< \brief (SSC_CR) Transmit Enable */ -#define SSC_CR_TXDIS (0x1 << 9) /**< \brief (SSC_CR) Transmit Disable */ -#define SSC_CR_SWRST (0x1 << 15) /**< \brief (SSC_CR) Software Reset */ -/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */ -#define SSC_CMR_DIV (0xfff << 0) /**< \brief (SSC_CMR) Clock Divider */ -/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */ -#define SSC_RCMR_CKS (0x3 << 0) /**< \brief (SSC_RCMR) Receive Clock Selection */ -#define SSC_RCMR_CKS_DIV (0x0 << 0) /**< \brief (SSC_RCMR) Divided Clock */ -#define SSC_RCMR_CKS_TK (0x1 << 0) /**< \brief (SSC_RCMR) TK Clock signal */ -#define SSC_RCMR_CKS_RK (0x2 << 0) /**< \brief (SSC_RCMR) RK pin */ -#define SSC_RCMR_CKO (0x7 << 2) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */ -#define SSC_RCMR_CKI (0x1 << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */ -#define SSC_RCMR_CKG (0x3 << 6) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */ -#define SSC_RCMR_CKG_NONE (0x0 << 6) /**< \brief (SSC_RCMR) None, continuous clock */ -#define SSC_RCMR_CKG_LOW (0x1 << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */ -#define SSC_RCMR_CKG_HIGH (0x2 << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */ -#define SSC_RCMR_START (0xf << 8) /**< \brief (SSC_RCMR) Receive Start Selection */ -#define SSC_RCMR_STOP (0x1 << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */ -#define SSC_RCMR_STTDLY (0xff << 16) /**< \brief (SSC_RCMR) Receive Start Delay */ -#define SSC_RCMR_PERIOD (0xff << 24) /**< \brief (SSC_RCMR) Receive Period Divider Selection */ -/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */ -#define SSC_RFMR_DATLEN (0x1f << 0) /**< \brief (SSC_RFMR) Data Length */ -#define SSC_RFMR_LOOP (0x1 << 5) /**< \brief (SSC_RFMR) Loop Mode */ -#define SSC_RFMR_MSBF (0x1 << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */ -#define SSC_RFMR_DATNB (0xf << 8) /**< \brief (SSC_RFMR) Data Number per Frame */ -#define SSC_RFMR_FSLEN (0xf << 16) /**< \brief (SSC_RFMR) Receive Frame Sync Length */ -#define SSC_RFMR_FSOS (0x7 << 20) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */ -#define SSC_RFMR_FSEDGE (0x1 << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */ -#define SSC_RFMR_FSLEN_EXT (0xf << 28) /**< \brief (SSC_RFMR) FSLEN Field Extension */ -/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */ -#define SSC_TCMR_CKS (0x3 << 0) /**< \brief (SSC_TCMR) Transmit Clock Selection */ -#define SSC_TCMR_CKO (0x7 << 2) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */ -#define SSC_TCMR_CKI (0x1 << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */ -#define SSC_TCMR_CKG (0x3 << 6) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */ -#define SSC_TCMR_START (0xf << 8) /**< \brief (SSC_TCMR) Transmit Start Selection */ -#define SSC_TCMR_STTDLY (0xff << 16) /**< \brief (SSC_TCMR) Transmit Start Delay */ -#define SSC_TCMR_PERIOD (0xff << 24) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */ -/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */ -#define SSC_TFMR_DATLEN (0x1f << 0) /**< \brief (SSC_TFMR) Data Length */ -#define SSC_TFMR_DATDEF (0x1 << 5) /**< \brief (SSC_TFMR) Data Default Value */ -#define SSC_TFMR_MSBF (0x1 << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */ -#define SSC_TFMR_DATNB (0xf << 8) /**< \brief (SSC_TFMR) Data Number per frame */ -#define SSC_TFMR_FSLEN (0xf << 16) /**< \brief (SSC_TFMR) Transmit Frame Syn Length */ -#define SSC_TFMR_FSOS (0x7 << 20) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */ -#define SSC_TFMR_FSDEN (0x1 << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */ -#define SSC_TFMR_FSEDGE (0x1 << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */ -#define SSC_TFMR_FSLEN_EXT (0xf << 28) /**< \brief (SSC_TFMR) FSLEN Field Extension */ -/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */ -#define SSC_RHR_RDAT (0xffffffff << 0) /**< \brief (SSC_RHR) Receive Data */ -/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */ -#define SSC_THR_TDAT (0xffffffff << 0) /**< \brief (SSC_THR) Transmit Data */ -/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */ -#define SSC_RSHR_RSDAT (0xffff << 0) /**< \brief (SSC_RSHR) Receive Synchronization Data */ -/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */ -#define SSC_TSHR_TSDAT (0xffff << 0) /**< \brief (SSC_TSHR) Transmit Synchronization Data */ -/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */ -#define SSC_RC0R_CP0 (0xffff << 0) /**< \brief (SSC_RC0R) Receive Compare Data 0 */ -/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */ -#define SSC_RC1R_CP1 (0xffff << 0) /**< \brief (SSC_RC1R) Receive Compare Data 1 */ -/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */ -#define SSC_SR_TXRDY (0x1 << 0) /**< \brief (SSC_SR) Transmit Ready */ -#define SSC_SR_TXEMPTY (0x1 << 1) /**< \brief (SSC_SR) Transmit Empty */ -#define SSC_SR_ENDTX (0x1 << 2) /**< \brief (SSC_SR) End of Transmission */ -#define SSC_SR_TXBUFE (0x1 << 3) /**< \brief (SSC_SR) Transmit Buffer Empty */ -#define SSC_SR_RXRDY (0x1 << 4) /**< \brief (SSC_SR) Receive Ready */ -#define SSC_SR_OVRUN (0x1 << 5) /**< \brief (SSC_SR) Receive Overrun */ -#define SSC_SR_ENDRX (0x1 << 6) /**< \brief (SSC_SR) End of Reception */ -#define SSC_SR_RXBUFF (0x1 << 7) /**< \brief (SSC_SR) Receive Buffer Full */ -#define SSC_SR_CP0 (0x1 << 8) /**< \brief (SSC_SR) Compare 0 */ -#define SSC_SR_CP1 (0x1 << 9) /**< \brief (SSC_SR) Compare 1 */ -#define SSC_SR_TXSYN (0x1 << 10) /**< \brief (SSC_SR) Transmit Sync */ -#define SSC_SR_RXSYN (0x1 << 11) /**< \brief (SSC_SR) Receive Sync */ -#define SSC_SR_TXEN (0x1 << 16) /**< \brief (SSC_SR) Transmit Enable */ -#define SSC_SR_RXEN (0x1 << 17) /**< \brief (SSC_SR) Receive Enable */ -/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */ -#define SSC_IER_TXRDY (0x1 << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */ -#define SSC_IER_TXEMPTY (0x1 << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */ -#define SSC_IER_ENDTX (0x1 << 2) /**< \brief (SSC_IER) End of Transmission Interrupt Enable */ -#define SSC_IER_TXBUFE (0x1 << 3) /**< \brief (SSC_IER) Transmit Buffer Empty Interrupt Enable */ -#define SSC_IER_RXRDY (0x1 << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */ -#define SSC_IER_OVRUN (0x1 << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */ -#define SSC_IER_ENDRX (0x1 << 6) /**< \brief (SSC_IER) End of Reception Interrupt Enable */ -#define SSC_IER_RXBUFF (0x1 << 7) /**< \brief (SSC_IER) Receive Buffer Full Interrupt Enable */ -#define SSC_IER_CP0 (0x1 << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */ -#define SSC_IER_CP1 (0x1 << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */ -#define SSC_IER_TXSYN (0x1 << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */ -#define SSC_IER_RXSYN (0x1 << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */ -/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */ -#define SSC_IDR_TXRDY (0x1 << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */ -#define SSC_IDR_TXEMPTY (0x1 << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */ -#define SSC_IDR_ENDTX (0x1 << 2) /**< \brief (SSC_IDR) End of Transmission Interrupt Disable */ -#define SSC_IDR_TXBUFE (0x1 << 3) /**< \brief (SSC_IDR) Transmit Buffer Empty Interrupt Disable */ -#define SSC_IDR_RXRDY (0x1 << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */ -#define SSC_IDR_OVRUN (0x1 << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */ -#define SSC_IDR_ENDRX (0x1 << 6) /**< \brief (SSC_IDR) End of Reception Interrupt Disable */ -#define SSC_IDR_RXBUFF (0x1 << 7) /**< \brief (SSC_IDR) Receive Buffer Full Interrupt Disable */ -#define SSC_IDR_CP0 (0x1 << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */ -#define SSC_IDR_CP1 (0x1 << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */ -#define SSC_IDR_TXSYN (0x1 << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */ -#define SSC_IDR_RXSYN (0x1 << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */ -/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */ -#define SSC_IMR_TXRDY (0x1 << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */ -#define SSC_IMR_TXEMPTY (0x1 << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */ -#define SSC_IMR_ENDTX (0x1 << 2) /**< \brief (SSC_IMR) End of Transmission Interrupt Mask */ -#define SSC_IMR_TXBUFE (0x1 << 3) /**< \brief (SSC_IMR) Transmit Buffer Empty Interrupt Mask */ -#define SSC_IMR_RXRDY (0x1 << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */ -#define SSC_IMR_OVRUN (0x1 << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */ -#define SSC_IMR_ENDRX (0x1 << 6) /**< \brief (SSC_IMR) End of Reception Interrupt Mask */ -#define SSC_IMR_RXBUFF (0x1 << 7) /**< \brief (SSC_IMR) Receive Buffer Full Interrupt Mask */ -#define SSC_IMR_CP0 (0x1 << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */ -#define SSC_IMR_CP1 (0x1 << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */ -#define SSC_IMR_TXSYN (0x1 << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */ -#define SSC_IMR_RXSYN (0x1 << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */ -/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */ -#define SSC_WPMR_WPEN (0x1 << 0) /**< \brief (SSC_WPMR) Write Protect Enable */ -#define SSC_WPMR_WPKEY (0xffffff << 8) /**< \brief (SSC_WPMR) Write Protect KEY */ -/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */ -#define SSC_WPSR_WPVS (0x1 << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */ -#define SSC_WPSR_WPVSRC (0xffff << 8) /**< \brief (SSC_WPSR) Write Protect Violation Source */ -/* -------- SSC_RPR : (SSC Offset: 0x100) Receive Pointer Register -------- */ -#define SSC_RPR_RXPTR (0xffffffff << 0) /**< \brief (SSC_RPR) Receive Pointer Register */ -/* -------- SSC_RCR : (SSC Offset: 0x104) Receive Counter Register -------- */ -#define SSC_RCR_RXCTR (0xffff << 0) /**< \brief (SSC_RCR) Receive Counter Register */ -/* -------- SSC_TPR : (SSC Offset: 0x108) Transmit Pointer Register -------- */ -#define SSC_TPR_TXPTR (0xffffffff << 0) /**< \brief (SSC_TPR) Transmit Counter Register */ -/* -------- SSC_TCR : (SSC Offset: 0x10C) Transmit Counter Register -------- */ -#define SSC_TCR_TXCTR (0xffff << 0) /**< \brief (SSC_TCR) Transmit Counter Register */ -/* -------- SSC_RNPR : (SSC Offset: 0x110) Receive Next Pointer Register -------- */ -#define SSC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (SSC_RNPR) Receive Next Pointer */ -/* -------- SSC_RNCR : (SSC Offset: 0x114) Receive Next Counter Register -------- */ -#define SSC_RNCR_RXNCTR (0xffff << 0) /**< \brief (SSC_RNCR) Receive Next Counter */ -/* -------- SSC_TNPR : (SSC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define SSC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (SSC_TNPR) Transmit Next Pointer */ -/* -------- SSC_TNCR : (SSC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define SSC_TNCR_TXNCTR (0xffff << 0) /**< \brief (SSC_TNCR) Transmit Counter Next */ -/* -------- SSC_PTCR : (SSC Offset: 0x120) Transfer Control Register -------- */ -#define SSC_PTCR_RXTEN (0x1 << 0) /**< \brief (SSC_PTCR) Receiver Transfer Enable */ -#define SSC_PTCR_RXTDIS (0x1 << 1) /**< \brief (SSC_PTCR) Receiver Transfer Disable */ -#define SSC_PTCR_TXTEN (0x1 << 8) /**< \brief (SSC_PTCR) Transmitter Transfer Enable */ -#define SSC_PTCR_TXTDIS (0x1 << 9) /**< \brief (SSC_PTCR) Transmitter Transfer Disable */ -/* -------- SSC_PTSR : (SSC Offset: 0x124) Transfer Status Register -------- */ -#define SSC_PTSR_RXTEN (0x1 << 0) /**< \brief (SSC_PTSR) Receiver Transfer Enable */ -#define SSC_PTSR_TXTEN (0x1 << 8) /**< \brief (SSC_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Supply Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_SUPC Supply Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Supc hardware registers */ -typedef struct { - WoReg SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */ - RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */ - RwReg SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */ - RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */ - RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */ - RoReg SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */ -} Supc; -#endif /* __ASSEMBLY__ */ -/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */ -#define SUPC_CR_VROFF (0x1 << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */ -#define SUPC_CR_VROFF_NO_EFFECT (0x0 << 2) /**< \brief (SUPC_CR) no effect. */ -#define SUPC_CR_VROFF_STOP_VREG (0x1 << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */ -#define SUPC_CR_XTALSEL (0x1 << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */ -#define SUPC_CR_XTALSEL_NO_EFFECT (0x0 << 3) /**< \brief (SUPC_CR) no effect. */ -#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1 << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */ -#define SUPC_CR_KEY (0xff << 24) /**< \brief (SUPC_CR) Password */ -/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */ -#define SUPC_SMMR_SMTH (0xf << 0) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */ -#define SUPC_SMMR_SMTH_1_9V (0x0 << 0) /**< \brief (SUPC_SMMR) 1.9 V */ -#define SUPC_SMMR_SMTH_2_0V (0x1 << 0) /**< \brief (SUPC_SMMR) 2.0 V */ -#define SUPC_SMMR_SMTH_2_1V (0x2 << 0) /**< \brief (SUPC_SMMR) 2.1 V */ -#define SUPC_SMMR_SMTH_2_2V (0x3 << 0) /**< \brief (SUPC_SMMR) 2.2 V */ -#define SUPC_SMMR_SMTH_2_3V (0x4 << 0) /**< \brief (SUPC_SMMR) 2.3 V */ -#define SUPC_SMMR_SMTH_2_4V (0x5 << 0) /**< \brief (SUPC_SMMR) 2.4 V */ -#define SUPC_SMMR_SMTH_2_5V (0x6 << 0) /**< \brief (SUPC_SMMR) 2.5 V */ -#define SUPC_SMMR_SMTH_2_6V (0x7 << 0) /**< \brief (SUPC_SMMR) 2.6 V */ -#define SUPC_SMMR_SMTH_2_7V (0x8 << 0) /**< \brief (SUPC_SMMR) 2.7 V */ -#define SUPC_SMMR_SMTH_2_8V (0x9 << 0) /**< \brief (SUPC_SMMR) 2.8 V */ -#define SUPC_SMMR_SMTH_2_9V (0xA << 0) /**< \brief (SUPC_SMMR) 2.9 V */ -#define SUPC_SMMR_SMTH_3_0V (0xB << 0) /**< \brief (SUPC_SMMR) 3.0 V */ -#define SUPC_SMMR_SMTH_3_1V (0xC << 0) /**< \brief (SUPC_SMMR) 3.1 V */ -#define SUPC_SMMR_SMTH_3_2V (0xD << 0) /**< \brief (SUPC_SMMR) 3.2 V */ -#define SUPC_SMMR_SMTH_3_3V (0xE << 0) /**< \brief (SUPC_SMMR) 3.3 V */ -#define SUPC_SMMR_SMTH_3_4V (0xF << 0) /**< \brief (SUPC_SMMR) 3.4 V */ -#define SUPC_SMMR_SMSMPL (0x7 << 8) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */ -#define SUPC_SMMR_SMSMPL_SMD (0x0 << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */ -#define SUPC_SMMR_SMSMPL_CSM (0x1 << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */ -#define SUPC_SMMR_SMSMPL_32SLCK (0x2 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ -#define SUPC_SMMR_SMSMPL_256SLCK (0x3 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ -#define SUPC_SMMR_SMSMPL_2048SLCK (0x4 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ -#define SUPC_SMMR_SMRSTEN (0x1 << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */ -#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMRSTEN_ENABLE (0x1 << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMIEN (0x1 << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */ -#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0 << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMIEN_ENABLE (0x1 << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */ -/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */ -#define SUPC_MR_BODRSTEN (0x1 << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */ -#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */ -#define SUPC_MR_BODRSTEN_ENABLE (0x1 << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ -#define SUPC_MR_BODDIS (0x1 << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */ -#define SUPC_MR_BODDIS_ENABLE (0x0 << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */ -#define SUPC_MR_BODDIS_DISABLE (0x1 << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */ -#define SUPC_MR_ONREG (0x1 << 14) /**< \brief (SUPC_MR) Voltage Regulator enable */ -#define SUPC_MR_ONREG_ONREG_UNUSED (0x0 << 14) /**< \brief (SUPC_MR) Voltage Regulator is not used */ -#define SUPC_MR_ONREG_ONREG_USED (0x1 << 14) /**< \brief (SUPC_MR) Voltage Regulator is used */ -#define SUPC_MR_OSCBYPASS (0x1 << 20) /**< \brief (SUPC_MR) Oscillator Bypass */ -#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0 << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */ -#define SUPC_MR_OSCBYPASS_BYPASS (0x1 << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */ -#define SUPC_MR_KEY (0xff << 24) /**< \brief (SUPC_MR) Password Key */ -/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */ -#define SUPC_WUMR_SMEN (0x1 << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */ -#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0 << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */ -#define SUPC_WUMR_SMEN_ENABLE (0x1 << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */ -#define SUPC_WUMR_RTTEN (0x1 << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */ -#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0 << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */ -#define SUPC_WUMR_RTTEN_ENABLE (0x1 << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */ -#define SUPC_WUMR_RTCEN (0x1 << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */ -#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0 << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */ -#define SUPC_WUMR_RTCEN_ENABLE (0x1 << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */ -#define SUPC_WUMR_WKUPDBC (0x7 << 12) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer */ -#define SUPC_WUMR_WKUPDBC_1SCLK (0x0 << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ -#define SUPC_WUMR_WKUPDBC_3SCLK (0x1 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 3 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_32SCLK (0x2 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 32 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_512SCLK (0x3 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 512 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_4096SCLK (0x4 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 4,096 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_32768SCLK (0x5 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 32,768 SLCK periods */ -/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */ -#define SUPC_WUIR_WKUPEN0 (0x1 << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */ -#define SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0 << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN0_ENABLE (0x1 << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN1 (0x1 << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */ -#define SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0 << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN1_ENABLE (0x1 << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN2 (0x1 << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */ -#define SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0 << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN2_ENABLE (0x1 << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN3 (0x1 << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */ -#define SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0 << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN3_ENABLE (0x1 << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN4 (0x1 << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */ -#define SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0 << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN4_ENABLE (0x1 << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN5 (0x1 << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */ -#define SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0 << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN5_ENABLE (0x1 << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN6 (0x1 << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */ -#define SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0 << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN6_ENABLE (0x1 << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN7 (0x1 << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */ -#define SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0 << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN7_ENABLE (0x1 << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN8 (0x1 << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */ -#define SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0 << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN8_ENABLE (0x1 << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN9 (0x1 << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */ -#define SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0 << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN9_ENABLE (0x1 << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN10 (0x1 << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */ -#define SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0 << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN10_ENABLE (0x1 << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN11 (0x1 << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */ -#define SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0 << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN11_ENABLE (0x1 << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN12 (0x1 << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */ -#define SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN12_ENABLE (0x1 << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN13 (0x1 << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */ -#define SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0 << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN13_ENABLE (0x1 << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN14 (0x1 << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */ -#define SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0 << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN14_ENABLE (0x1 << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN15 (0x1 << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */ -#define SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0 << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN15_ENABLE (0x1 << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT0 (0x1 << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */ -#define SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0 << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1 << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT1 (0x1 << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */ -#define SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0 << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1 << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT2 (0x1 << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */ -#define SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0 << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1 << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT3 (0x1 << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */ -#define SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0 << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1 << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT4 (0x1 << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */ -#define SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0 << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1 << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT5 (0x1 << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */ -#define SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0 << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1 << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT6 (0x1 << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */ -#define SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0 << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1 << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT7 (0x1 << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */ -#define SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0 << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1 << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT8 (0x1 << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */ -#define SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0 << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1 << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT9 (0x1 << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */ -#define SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0 << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1 << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT10 (0x1 << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */ -#define SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0 << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1 << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT11 (0x1 << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */ -#define SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0 << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1 << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT12 (0x1 << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */ -#define SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0 << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1 << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT13 (0x1 << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */ -#define SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0 << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1 << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT14 (0x1 << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */ -#define SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0 << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1 << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT15 (0x1 << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */ -#define SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0 << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1 << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */ -#define SUPC_SR_WKUPS (0x1 << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */ -#define SUPC_SR_WKUPS_NO (0x0 << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_WKUPS_PRESENT (0x1 << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_SMWS (0x1 << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */ -#define SUPC_SR_SMWS_NO (0x0 << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_SMWS_PRESENT (0x1 << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_BODRSTS (0x1 << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */ -#define SUPC_SR_BODRSTS_NO (0x0 << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */ -#define SUPC_SR_BODRSTS_PRESENT (0x1 << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ -#define SUPC_SR_SMRSTS (0x1 << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */ -#define SUPC_SR_SMRSTS_NO (0x0 << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ -#define SUPC_SR_SMRSTS_PRESENT (0x1 << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ -#define SUPC_SR_SMS (0x1 << 5) /**< \brief (SUPC_SR) Supply Monitor Status */ -#define SUPC_SR_SMS_NO (0x0 << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */ -#define SUPC_SR_SMS_PRESENT (0x1 << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */ -#define SUPC_SR_SMOS (0x1 << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */ -#define SUPC_SR_SMOS_HIGH (0x0 << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO higher than its threshold at its last measurement. */ -#define SUPC_SR_SMOS_LOW (0x1 << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO lower than its threshold at its last measurement. */ -#define SUPC_SR_OSCSEL (0x1 << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */ -#define SUPC_SR_OSCSEL_RC (0x0 << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */ -#define SUPC_SR_OSCSEL_CRYST (0x1 << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */ -#define SUPC_SR_WKUPIS0 (0x1 << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */ -#define SUPC_SR_WKUPIS0_DIS (0x0 << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS0_EN (0x1 << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS1 (0x1 << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */ -#define SUPC_SR_WKUPIS1_DIS (0x0 << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS1_EN (0x1 << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS2 (0x1 << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */ -#define SUPC_SR_WKUPIS2_DIS (0x0 << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS2_EN (0x1 << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS3 (0x1 << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */ -#define SUPC_SR_WKUPIS3_DIS (0x0 << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS3_EN (0x1 << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS4 (0x1 << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */ -#define SUPC_SR_WKUPIS4_DIS (0x0 << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS4_EN (0x1 << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS5 (0x1 << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */ -#define SUPC_SR_WKUPIS5_DIS (0x0 << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS5_EN (0x1 << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS6 (0x1 << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */ -#define SUPC_SR_WKUPIS6_DIS (0x0 << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS6_EN (0x1 << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS7 (0x1 << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */ -#define SUPC_SR_WKUPIS7_DIS (0x0 << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS7_EN (0x1 << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS8 (0x1 << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */ -#define SUPC_SR_WKUPIS8_DIS (0x0 << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS8_EN (0x1 << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS9 (0x1 << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */ -#define SUPC_SR_WKUPIS9_DIS (0x0 << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS9_EN (0x1 << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS10 (0x1 << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */ -#define SUPC_SR_WKUPIS10_DIS (0x0 << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS10_EN (0x1 << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS11 (0x1 << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */ -#define SUPC_SR_WKUPIS11_DIS (0x0 << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS11_EN (0x1 << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS12 (0x1 << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */ -#define SUPC_SR_WKUPIS12_DIS (0x0 << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS12_EN (0x1 << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS13 (0x1 << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */ -#define SUPC_SR_WKUPIS13_DIS (0x0 << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS13_EN (0x1 << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS14 (0x1 << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */ -#define SUPC_SR_WKUPIS14_DIS (0x0 << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS14_EN (0x1 << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS15 (0x1 << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */ -#define SUPC_SR_WKUPIS15_DIS (0x0 << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS15_EN (0x1 << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Timer Counter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_TC Timer Counter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief TcChannel hardware registers */ -typedef struct { - RwReg TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ - RwReg TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ - RwReg Reserved1[2]; - RwReg TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ - RwReg TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ - RwReg TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ - RwReg TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ - RwReg TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ - RwReg TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ - RwReg TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ - RwReg TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ - RwReg Reserved2[4]; -} TcChannel; -/** \brief Tc hardware registers */ -typedef struct { - TcChannel TC_CHANNEL[3]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ - WoReg TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ - RwReg TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ - WoReg TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ - WoReg TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ - RoReg TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ - RoReg TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ - RwReg TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */ - RwReg Reserved1[2]; - RwReg TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */ - RwReg Reserved2[5]; - RoReg TC_VER; /**< \brief (Tc Offset: 0xFC) Version Register */ -} Tc; -#endif /* __ASSEMBLY__ */ -/* -------- TC_CCR0 : (TC Offset: 0x0) Channel Control Register (channel = 0) -------- */ -#define TC_CCR0_CLKEN (0x1 << 0) /**< \brief (TC_CCR0) Counter Clock Enable Command */ -#define TC_CCR0_CLKDIS (0x1 << 1) /**< \brief (TC_CCR0) Counter Clock Disable Command */ -#define TC_CCR0_SWTRG (0x1 << 2) /**< \brief (TC_CCR0) Software Trigger Command */ -/* -------- TC_CMR0 : (TC Offset: 0x4) Channel Mode Register (channel = 0) -------- */ -#define TC_CMR0_TCCLKS (0x7 << 0) /**< \brief (TC_CMR0) Clock Selection */ -#define TC_CM0_TCCLKS_TIMER_DIV1_CLOCK (0x0 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV1_CLOCK*/ -#define TC_CM0_TCCLKS_TIMER_DIV2_CLOCK (0x1 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV2_CLOCK*/ -#define TC_CM0_TCCLKS_TIMER_DIV3_CLOCK (0x2 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV3_CLOCK*/ -#define TC_CM0_TCCLKS_TIMER_DIV4_CLOCK (0x3 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV4_CLOCK*/ -#define TC_CM0_TCCLKS_TIMER_DIV5_CLOCK (0x4 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV5_CLOCK*/ -#define TC_CM0_TCCLKS_XC0 (0x5 << 0) /**< (TC_CMR0) Clock selected: XC0*/ -#define TC_CM0_TCCLKS_XC1 (0x6 << 0) /**< (TC_CMR0) Clock selected: XC1*/ -#define TC_CM0_TCCLKS_XC2 (0x7 << 0) /**< (TC_CMR0) Clock selected: XC2*/ -#define TC_CMR0_CLKI (0x1 << 3) /**< \brief (TC_CMR0) Clock Invert */ -#define TC_CMR0_BURST (0x3 << 4) /**< \brief (TC_CMR0) Burst Signal Selection */ -#define TC_CMR0_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR0) The clock is not gated by an external signal. */ -#define TC_CMR0_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR0) XC0 is ANDed with the selected clock. */ -#define TC_CMR0_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR0) XC1 is ANDed with the selected clock. */ -#define TC_CMR0_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR0) XC2 is ANDed with the selected clock. */ -#define TC_CMR0_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR0) Counter Clock Stopped with RB Loading */ -#define TC_CMR0_LDBDIS (0x1 << 7) /**< \brief (TC_CMR0) Counter Clock Disable with RB Loading */ -#define TC_CMR0_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR0) External Trigger Edge Selection */ -#define TC_CMR0_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR0) none */ -#define TC_CMR0_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR0) rising edge */ -#define TC_CMR0_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR0) falling edge */ -#define TC_CMR0_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR0) each edge */ -#define TC_CMR0_ABETRG (0x1 << 10) /**< \brief (TC_CMR0) TIOA or TIOB External Trigger Selection */ -#define TC_CMR0_CPCTRG (0x1 << 14) /**< \brief (TC_CMR0) RC Compare Trigger Enable */ -#define TC_CMR0_WAVE (0x1 << 15) /**< \brief (TC_CMR0) */ -#define TC_CMR0_LDRA (0x3 << 16) /**< \brief (TC_CMR0) RA Loading Selection */ -#define TC_CMR0_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR0) none */ -#define TC_CMR0_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR0) rising edge of TIOA */ -#define TC_CMR0_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR0) falling edge of TIOA */ -#define TC_CMR0_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR0) each edge of TIOA */ -#define TC_CMR0_LDRB (0x3 << 18) /**< \brief (TC_CMR0) RB Loading Selection */ -#define TC_CMR0_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR0) none */ -#define TC_CMR0_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR0) rising edge of TIOA */ -#define TC_CMR0_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR0) falling edge of TIOA */ -#define TC_CMR0_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR0) each edge of TIOA */ - -#define TC_CMR0_ACPA_NONE (0x0 << 16) // (TC) Effect: none -#define TC_CMR0_ACPA_SET (0x1 << 16) // (TC) Effect: set -#define TC_CMR0_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear -#define TC_CMR0_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle - -#define TC_CMR0_ACPC_NONE (0x0 << 18) // (TC) Effect: none -#define TC_CMR0_ACPC_SET (0x1 << 18) // (TC) Effect: set -#define TC_CMR0_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear -#define TC_CMR0_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle -/* -------- TC_CV0 : (TC Offset: 0x10) Counter Value (channel = 0) -------- */ -#define TC_CV0_CV (0xffff << 0) /**< \brief (TC_CV0) Counter Value */ -/* -------- TC_RA0 : (TC Offset: 0x14) Register A (channel = 0) -------- */ -#define TC_RA0_RA (0xffff << 0) /**< \brief (TC_RA0) Register A */ -/* -------- TC_RB0 : (TC Offset: 0x18) Register B (channel = 0) -------- */ -#define TC_RB0_RB (0xffff << 0) /**< \brief (TC_RB0) Register B */ -/* -------- TC_RC0 : (TC Offset: 0x1C) Register C (channel = 0) -------- */ -#define TC_RC0_RC (0xffff << 0) /**< \brief (TC_RC0) Register C */ -/* -------- TC_SR0 : (TC Offset: 0x20) Status Register (channel = 0) -------- */ -#define TC_SR0_COVFS (0x1 << 0) /**< \brief (TC_SR0) Counter Overflow Status */ -#define TC_SR0_LOVRS (0x1 << 1) /**< \brief (TC_SR0) Load Overrun Status */ -#define TC_SR0_CPAS (0x1 << 2) /**< \brief (TC_SR0) RA Compare Status */ -#define TC_SR0_CPBS (0x1 << 3) /**< \brief (TC_SR0) RB Compare Status */ -#define TC_SR0_CPCS (0x1 << 4) /**< \brief (TC_SR0) RC Compare Status */ -#define TC_SR0_LDRAS (0x1 << 5) /**< \brief (TC_SR0) RA Loading Status */ -#define TC_SR0_LDRBS (0x1 << 6) /**< \brief (TC_SR0) RB Loading Status */ -#define TC_SR0_ETRGS (0x1 << 7) /**< \brief (TC_SR0) External Trigger Status */ -#define TC_SR0_CLKSTA (0x1 << 16) /**< \brief (TC_SR0) Clock Enabling Status */ -#define TC_SR0_MTIOA (0x1 << 17) /**< \brief (TC_SR0) TIOA Mirror */ -#define TC_SR0_MTIOB (0x1 << 18) /**< \brief (TC_SR0) TIOB Mirror */ -/* -------- TC_IER0 : (TC Offset: 0x24) Interrupt Enable Register (channel = 0) -------- */ -#define TC_IER0_COVFS (0x1 << 0) /**< \brief (TC_IER0) Counter Overflow */ -#define TC_IER0_LOVRS (0x1 << 1) /**< \brief (TC_IER0) Load Overrun */ -#define TC_IER0_CPAS (0x1 << 2) /**< \brief (TC_IER0) RA Compare */ -#define TC_IER0_CPBS (0x1 << 3) /**< \brief (TC_IER0) RB Compare */ -#define TC_IER0_CPCS (0x1 << 4) /**< \brief (TC_IER0) RC Compare */ -#define TC_IER0_LDRAS (0x1 << 5) /**< \brief (TC_IER0) RA Loading */ -#define TC_IER0_LDRBS (0x1 << 6) /**< \brief (TC_IER0) RB Loading */ -#define TC_IER0_ETRGS (0x1 << 7) /**< \brief (TC_IER0) External Trigger */ -/* -------- TC_IDR0 : (TC Offset: 0x28) Interrupt Disable Register (channel = 0) -------- */ -#define TC_IDR0_COVFS (0x1 << 0) /**< \brief (TC_IDR0) Counter Overflow */ -#define TC_IDR0_LOVRS (0x1 << 1) /**< \brief (TC_IDR0) Load Overrun */ -#define TC_IDR0_CPAS (0x1 << 2) /**< \brief (TC_IDR0) RA Compare */ -#define TC_IDR0_CPBS (0x1 << 3) /**< \brief (TC_IDR0) RB Compare */ -#define TC_IDR0_CPCS (0x1 << 4) /**< \brief (TC_IDR0) RC Compare */ -#define TC_IDR0_LDRAS (0x1 << 5) /**< \brief (TC_IDR0) RA Loading */ -#define TC_IDR0_LDRBS (0x1 << 6) /**< \brief (TC_IDR0) RB Loading */ -#define TC_IDR0_ETRGS (0x1 << 7) /**< \brief (TC_IDR0) External Trigger */ -/* -------- TC_IMR0 : (TC Offset: 0x2C) Interrupt Mask Register (channel = 0) -------- */ -#define TC_IMR0_COVFS (0x1 << 0) /**< \brief (TC_IMR0) Counter Overflow */ -#define TC_IMR0_LOVRS (0x1 << 1) /**< \brief (TC_IMR0) Load Overrun */ -#define TC_IMR0_CPAS (0x1 << 2) /**< \brief (TC_IMR0) RA Compare */ -#define TC_IMR0_CPBS (0x1 << 3) /**< \brief (TC_IMR0) RB Compare */ -#define TC_IMR0_CPCS (0x1 << 4) /**< \brief (TC_IMR0) RC Compare */ -#define TC_IMR0_LDRAS (0x1 << 5) /**< \brief (TC_IMR0) RA Loading */ -#define TC_IMR0_LDRBS (0x1 << 6) /**< \brief (TC_IMR0) RB Loading */ -#define TC_IMR0_ETRGS (0x1 << 7) /**< \brief (TC_IMR0) External Trigger */ -/* -------- TC_CCR1 : (TC Offset: 0x40) Channel Control Register (channel = 1) -------- */ -#define TC_CCR1_CLKEN (0x1 << 0) /**< \brief (TC_CCR1) Counter Clock Enable Command */ -#define TC_CCR1_CLKDIS (0x1 << 1) /**< \brief (TC_CCR1) Counter Clock Disable Command */ -#define TC_CCR1_SWTRG (0x1 << 2) /**< \brief (TC_CCR1) Software Trigger Command */ -/* -------- TC_CMR1 : (TC Offset: 0x44) Channel Mode Register (channel = 1) -------- */ -#define TC_CMR1_TCCLKS (0x7 << 0) /**< \brief (TC_CMR1) Clock Selection */ -#define TC_CMR1_CLKI (0x1 << 3) /**< \brief (TC_CMR1) Clock Invert */ -#define TC_CMR1_BURST (0x3 << 4) /**< \brief (TC_CMR1) Burst Signal Selection */ -#define TC_CMR1_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR1) The clock is not gated by an external signal. */ -#define TC_CMR1_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR1) XC0 is ANDed with the selected clock. */ -#define TC_CMR1_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR1) XC1 is ANDed with the selected clock. */ -#define TC_CMR1_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR1) XC2 is ANDed with the selected clock. */ -#define TC_CMR1_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR1) Counter Clock Stopped with RB Loading */ -#define TC_CMR1_LDBDIS (0x1 << 7) /**< \brief (TC_CMR1) Counter Clock Disable with RB Loading */ -#define TC_CMR1_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR1) External Trigger Edge Selection */ -#define TC_CMR1_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR1) none */ -#define TC_CMR1_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR1) rising edge */ -#define TC_CMR1_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR1) falling edge */ -#define TC_CMR1_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR1) each edge */ -#define TC_CMR1_ABETRG (0x1 << 10) /**< \brief (TC_CMR1) TIOA or TIOB External Trigger Selection */ -#define TC_CMR1_CPCTRG (0x1 << 14) /**< \brief (TC_CMR1) RC Compare Trigger Enable */ -#define TC_CMR1_WAVE (0x1 << 15) /**< \brief (TC_CMR1) */ -#define TC_CMR1_LDRA (0x3 << 16) /**< \brief (TC_CMR1) RA Loading Selection */ -#define TC_CMR1_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR1) none */ -#define TC_CMR1_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR1) rising edge of TIOA */ -#define TC_CMR1_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR1) falling edge of TIOA */ -#define TC_CMR1_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR1) each edge of TIOA */ -#define TC_CMR1_LDRB (0x3 << 18) /**< \brief (TC_CMR1) RB Loading Selection */ -#define TC_CMR1_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR1) none */ -#define TC_CMR1_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR1) rising edge of TIOA */ -#define TC_CMR1_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR1) falling edge of TIOA */ -#define TC_CMR1_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR1) each edge of TIOA */ -/* -------- TC_CV1 : (TC Offset: 0x50) Counter Value (channel = 1) -------- */ -#define TC_CV1_CV (0xffff << 0) /**< \brief (TC_CV1) Counter Value */ -/* -------- TC_RA1 : (TC Offset: 0x54) Register A (channel = 1) -------- */ -#define TC_RA1_RA (0xffff << 0) /**< \brief (TC_RA1) Register A */ -/* -------- TC_RB1 : (TC Offset: 0x58) Register B (channel = 1) -------- */ -#define TC_RB1_RB (0xffff << 0) /**< \brief (TC_RB1) Register B */ -/* -------- TC_RC1 : (TC Offset: 0x5C) Register C (channel = 1) -------- */ -#define TC_RC1_RC (0xffff << 0) /**< \brief (TC_RC1) Register C */ -/* -------- TC_SR1 : (TC Offset: 0x60) Status Register (channel = 1) -------- */ -#define TC_SR1_COVFS (0x1 << 0) /**< \brief (TC_SR1) Counter Overflow Status */ -#define TC_SR1_LOVRS (0x1 << 1) /**< \brief (TC_SR1) Load Overrun Status */ -#define TC_SR1_CPAS (0x1 << 2) /**< \brief (TC_SR1) RA Compare Status */ -#define TC_SR1_CPBS (0x1 << 3) /**< \brief (TC_SR1) RB Compare Status */ -#define TC_SR1_CPCS (0x1 << 4) /**< \brief (TC_SR1) RC Compare Status */ -#define TC_SR1_LDRAS (0x1 << 5) /**< \brief (TC_SR1) RA Loading Status */ -#define TC_SR1_LDRBS (0x1 << 6) /**< \brief (TC_SR1) RB Loading Status */ -#define TC_SR1_ETRGS (0x1 << 7) /**< \brief (TC_SR1) External Trigger Status */ -#define TC_SR1_CLKSTA (0x1 << 16) /**< \brief (TC_SR1) Clock Enabling Status */ -#define TC_SR1_MTIOA (0x1 << 17) /**< \brief (TC_SR1) TIOA Mirror */ -#define TC_SR1_MTIOB (0x1 << 18) /**< \brief (TC_SR1) TIOB Mirror */ -/* -------- TC_IER1 : (TC Offset: 0x64) Interrupt Enable Register (channel = 1) -------- */ -#define TC_IER1_COVFS (0x1 << 0) /**< \brief (TC_IER1) Counter Overflow */ -#define TC_IER1_LOVRS (0x1 << 1) /**< \brief (TC_IER1) Load Overrun */ -#define TC_IER1_CPAS (0x1 << 2) /**< \brief (TC_IER1) RA Compare */ -#define TC_IER1_CPBS (0x1 << 3) /**< \brief (TC_IER1) RB Compare */ -#define TC_IER1_CPCS (0x1 << 4) /**< \brief (TC_IER1) RC Compare */ -#define TC_IER1_LDRAS (0x1 << 5) /**< \brief (TC_IER1) RA Loading */ -#define TC_IER1_LDRBS (0x1 << 6) /**< \brief (TC_IER1) RB Loading */ -#define TC_IER1_ETRGS (0x1 << 7) /**< \brief (TC_IER1) External Trigger */ -/* -------- TC_IDR1 : (TC Offset: 0x68) Interrupt Disable Register (channel = 1) -------- */ -#define TC_IDR1_COVFS (0x1 << 0) /**< \brief (TC_IDR1) Counter Overflow */ -#define TC_IDR1_LOVRS (0x1 << 1) /**< \brief (TC_IDR1) Load Overrun */ -#define TC_IDR1_CPAS (0x1 << 2) /**< \brief (TC_IDR1) RA Compare */ -#define TC_IDR1_CPBS (0x1 << 3) /**< \brief (TC_IDR1) RB Compare */ -#define TC_IDR1_CPCS (0x1 << 4) /**< \brief (TC_IDR1) RC Compare */ -#define TC_IDR1_LDRAS (0x1 << 5) /**< \brief (TC_IDR1) RA Loading */ -#define TC_IDR1_LDRBS (0x1 << 6) /**< \brief (TC_IDR1) RB Loading */ -#define TC_IDR1_ETRGS (0x1 << 7) /**< \brief (TC_IDR1) External Trigger */ -/* -------- TC_IMR1 : (TC Offset: 0x6C) Interrupt Mask Register (channel = 1) -------- */ -#define TC_IMR1_COVFS (0x1 << 0) /**< \brief (TC_IMR1) Counter Overflow */ -#define TC_IMR1_LOVRS (0x1 << 1) /**< \brief (TC_IMR1) Load Overrun */ -#define TC_IMR1_CPAS (0x1 << 2) /**< \brief (TC_IMR1) RA Compare */ -#define TC_IMR1_CPBS (0x1 << 3) /**< \brief (TC_IMR1) RB Compare */ -#define TC_IMR1_CPCS (0x1 << 4) /**< \brief (TC_IMR1) RC Compare */ -#define TC_IMR1_LDRAS (0x1 << 5) /**< \brief (TC_IMR1) RA Loading */ -#define TC_IMR1_LDRBS (0x1 << 6) /**< \brief (TC_IMR1) RB Loading */ -#define TC_IMR1_ETRGS (0x1 << 7) /**< \brief (TC_IMR1) External Trigger */ -/* -------- TC_CCR2 : (TC Offset: 0x80) Channel Control Register (channel = 2) -------- */ -#define TC_CCR2_CLKEN (0x1 << 0) /**< \brief (TC_CCR2) Counter Clock Enable Command */ -#define TC_CCR2_CLKDIS (0x1 << 1) /**< \brief (TC_CCR2) Counter Clock Disable Command */ -#define TC_CCR2_SWTRG (0x1 << 2) /**< \brief (TC_CCR2) Software Trigger Command */ -/* -------- TC_CMR2 : (TC Offset: 0x84) Channel Mode Register (channel = 2) -------- */ -#define TC_CMR2_TCCLKS (0x7 << 0) /**< \brief (TC_CMR2) Clock Selection */ -#define TC_CMR2_CLKI (0x1 << 3) /**< \brief (TC_CMR2) Clock Invert */ -#define TC_CMR2_BURST (0x3 << 4) /**< \brief (TC_CMR2) Burst Signal Selection */ -#define TC_CMR2_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR2) The clock is not gated by an external signal. */ -#define TC_CMR2_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR2) XC0 is ANDed with the selected clock. */ -#define TC_CMR2_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR2) XC1 is ANDed with the selected clock. */ -#define TC_CMR2_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR2) XC2 is ANDed with the selected clock. */ -#define TC_CMR2_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR2) Counter Clock Stopped with RB Loading */ -#define TC_CMR2_LDBDIS (0x1 << 7) /**< \brief (TC_CMR2) Counter Clock Disable with RB Loading */ -#define TC_CMR2_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR2) External Trigger Edge Selection */ -#define TC_CMR2_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR2) none */ -#define TC_CMR2_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR2) rising edge */ -#define TC_CMR2_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR2) falling edge */ -#define TC_CMR2_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR2) each edge */ -#define TC_CMR2_ABETRG (0x1 << 10) /**< \brief (TC_CMR2) TIOA or TIOB External Trigger Selection */ -#define TC_CMR2_CPCTRG (0x1 << 14) /**< \brief (TC_CMR2) RC Compare Trigger Enable */ -#define TC_CMR2_WAVE (0x1 << 15) /**< \brief (TC_CMR2) */ -#define TC_CMR2_LDRA (0x3 << 16) /**< \brief (TC_CMR2) RA Loading Selection */ -#define TC_CMR2_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR2) none */ -#define TC_CMR2_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR2) rising edge of TIOA */ -#define TC_CMR2_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR2) falling edge of TIOA */ -#define TC_CMR2_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR2) each edge of TIOA */ -#define TC_CMR2_LDRB (0x3 << 18) /**< \brief (TC_CMR2) RB Loading Selection */ -#define TC_CMR2_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR2) none */ -#define TC_CMR2_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR2) rising edge of TIOA */ -#define TC_CMR2_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR2) falling edge of TIOA */ -#define TC_CMR2_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR2) each edge of TIOA */ -/* -------- TC_CV2 : (TC Offset: 0x90) Counter Value (channel = 2) -------- */ -#define TC_CV2_CV (0xffff << 0) /**< \brief (TC_CV2) Counter Value */ -/* -------- TC_RA2 : (TC Offset: 0x94) Register A (channel = 2) -------- */ -#define TC_RA2_RA (0xffff << 0) /**< \brief (TC_RA2) Register A */ -/* -------- TC_RB2 : (TC Offset: 0x98) Register B (channel = 2) -------- */ -#define TC_RB2_RB (0xffff << 0) /**< \brief (TC_RB2) Register B */ -/* -------- TC_RC2 : (TC Offset: 0x9C) Register C (channel = 2) -------- */ -#define TC_RC2_RC (0xffff << 0) /**< \brief (TC_RC2) Register C */ -/* -------- TC_SR2 : (TC Offset: 0xA0) Status Register (channel = 2) -------- */ -#define TC_SR2_COVFS (0x1 << 0) /**< \brief (TC_SR2) Counter Overflow Status */ -#define TC_SR2_LOVRS (0x1 << 1) /**< \brief (TC_SR2) Load Overrun Status */ -#define TC_SR2_CPAS (0x1 << 2) /**< \brief (TC_SR2) RA Compare Status */ -#define TC_SR2_CPBS (0x1 << 3) /**< \brief (TC_SR2) RB Compare Status */ -#define TC_SR2_CPCS (0x1 << 4) /**< \brief (TC_SR2) RC Compare Status */ -#define TC_SR2_LDRAS (0x1 << 5) /**< \brief (TC_SR2) RA Loading Status */ -#define TC_SR2_LDRBS (0x1 << 6) /**< \brief (TC_SR2) RB Loading Status */ -#define TC_SR2_ETRGS (0x1 << 7) /**< \brief (TC_SR2) External Trigger Status */ -#define TC_SR2_CLKSTA (0x1 << 16) /**< \brief (TC_SR2) Clock Enabling Status */ -#define TC_SR2_MTIOA (0x1 << 17) /**< \brief (TC_SR2) TIOA Mirror */ -#define TC_SR2_MTIOB (0x1 << 18) /**< \brief (TC_SR2) TIOB Mirror */ -/* -------- TC_IER2 : (TC Offset: 0xA4) Interrupt Enable Register (channel = 2) -------- */ -#define TC_IER2_COVFS (0x1 << 0) /**< \brief (TC_IER2) Counter Overflow */ -#define TC_IER2_LOVRS (0x1 << 1) /**< \brief (TC_IER2) Load Overrun */ -#define TC_IER2_CPAS (0x1 << 2) /**< \brief (TC_IER2) RA Compare */ -#define TC_IER2_CPBS (0x1 << 3) /**< \brief (TC_IER2) RB Compare */ -#define TC_IER2_CPCS (0x1 << 4) /**< \brief (TC_IER2) RC Compare */ -#define TC_IER2_LDRAS (0x1 << 5) /**< \brief (TC_IER2) RA Loading */ -#define TC_IER2_LDRBS (0x1 << 6) /**< \brief (TC_IER2) RB Loading */ -#define TC_IER2_ETRGS (0x1 << 7) /**< \brief (TC_IER2) External Trigger */ -/* -------- TC_IDR2 : (TC Offset: 0xA8) Interrupt Disable Register (channel = 2) -------- */ -#define TC_IDR2_COVFS (0x1 << 0) /**< \brief (TC_IDR2) Counter Overflow */ -#define TC_IDR2_LOVRS (0x1 << 1) /**< \brief (TC_IDR2) Load Overrun */ -#define TC_IDR2_CPAS (0x1 << 2) /**< \brief (TC_IDR2) RA Compare */ -#define TC_IDR2_CPBS (0x1 << 3) /**< \brief (TC_IDR2) RB Compare */ -#define TC_IDR2_CPCS (0x1 << 4) /**< \brief (TC_IDR2) RC Compare */ -#define TC_IDR2_LDRAS (0x1 << 5) /**< \brief (TC_IDR2) RA Loading */ -#define TC_IDR2_LDRBS (0x1 << 6) /**< \brief (TC_IDR2) RB Loading */ -#define TC_IDR2_ETRGS (0x1 << 7) /**< \brief (TC_IDR2) External Trigger */ -/* -------- TC_IMR2 : (TC Offset: 0xAC) Interrupt Mask Register (channel = 2) -------- */ -#define TC_IMR2_COVFS (0x1 << 0) /**< \brief (TC_IMR2) Counter Overflow */ -#define TC_IMR2_LOVRS (0x1 << 1) /**< \brief (TC_IMR2) Load Overrun */ -#define TC_IMR2_CPAS (0x1 << 2) /**< \brief (TC_IMR2) RA Compare */ -#define TC_IMR2_CPBS (0x1 << 3) /**< \brief (TC_IMR2) RB Compare */ -#define TC_IMR2_CPCS (0x1 << 4) /**< \brief (TC_IMR2) RC Compare */ -#define TC_IMR2_LDRAS (0x1 << 5) /**< \brief (TC_IMR2) RA Loading */ -#define TC_IMR2_LDRBS (0x1 << 6) /**< \brief (TC_IMR2) RB Loading */ -#define TC_IMR2_ETRGS (0x1 << 7) /**< \brief (TC_IMR2) External Trigger */ -/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ -#define TC_BCR_SYNC (0x1 << 0) /**< \brief (TC_BCR) Synchro Command */ -/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ -#define TC_BMR_TC0XC0S (0x3 << 0) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ -#define TC_BMR_TC0XC0S_TCLK0 (0x0 << 0) /**< \brief (TC_BMR) TCLK0 */ -#define TC_BMR_TC0XC0S_NONE (0x1 << 0) /**< \brief (TC_BMR) none */ -#define TC_BMR_TC0XC0S_TIOA1 (0x2 << 0) /**< \brief (TC_BMR) TIOA1 */ -#define TC_BMR_TC0XC0S_TIOA2 (0x3 << 0) /**< \brief (TC_BMR) TIOA2 */ -#define TC_BMR_TC1XC1S (0x3 << 2) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ -#define TC_BMR_TC1XC1S_TCLK1 (0x0 << 2) /**< \brief (TC_BMR) TCLK1 */ -#define TC_BMR_TC1XC1S_NONE (0x1 << 2) /**< \brief (TC_BMR) none */ -#define TC_BMR_TC1XC1S_TIOA0 (0x2 << 2) /**< \brief (TC_BMR) TIOA0 */ -#define TC_BMR_TC1XC1S_TIOA2 (0x3 << 2) /**< \brief (TC_BMR) TIOA2 */ -#define TC_BMR_TC2XC2S (0x3 << 4) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ -#define TC_BMR_TC2XC2S_TCLK2 (0x0 << 4) /**< \brief (TC_BMR) TCLK2 */ -#define TC_BMR_TC2XC2S_NONE (0x1 << 4) /**< \brief (TC_BMR) none */ -#define TC_BMR_TC2XC2S_TIOA0 (0x2 << 4) /**< \brief (TC_BMR) TIOA0 */ -#define TC_BMR_TC2XC2S_TIOA1 (0x3 << 4) /**< \brief (TC_BMR) TIOA1 */ -#define TC_BMR_QDEN (0x1 << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */ -#define TC_BMR_POSEN (0x1 << 9) /**< \brief (TC_BMR) POSition ENabled */ -#define TC_BMR_SPEEDEN (0x1 << 10) /**< \brief (TC_BMR) SPEED ENabled */ -#define TC_BMR_QDTRANS (0x1 << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */ -#define TC_BMR_EDGPHA (0x1 << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */ -#define TC_BMR_INVA (0x1 << 13) /**< \brief (TC_BMR) INVerted phA */ -#define TC_BMR_INVB (0x1 << 14) /**< \brief (TC_BMR) INVerted phB */ -#define TC_BMR_INVIDX (0x1 << 15) /**< \brief (TC_BMR) INVerted InDeX */ -#define TC_BMR_SWAP (0x1 << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */ -#define TC_BMR_IDXPHB (0x1 << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */ -#define TC_BMR_FILTER (0x1 << 19) /**< \brief (TC_BMR) */ -#define TC_BMR_MAXFILT (0x3f << 20) /**< \brief (TC_BMR) MAXimum FILTer */ -/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ -#define TC_QIER_IDX (0x1 << 0) /**< \brief (TC_QIER) InDeX */ -#define TC_QIER_DIRCHG (0x1 << 1) /**< \brief (TC_QIER) DIRection CHanGe */ -#define TC_QIER_QERR (0x1 << 2) /**< \brief (TC_QIER) Quadrature ERRor */ -/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ -#define TC_QIDR_IDX (0x1 << 0) /**< \brief (TC_QIDR) InDeX */ -#define TC_QIDR_DIRCHG (0x1 << 1) /**< \brief (TC_QIDR) DIRection CHanGe */ -#define TC_QIDR_QERR (0x1 << 2) /**< \brief (TC_QIDR) Quadrature ERRor */ -/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ -#define TC_QIMR_IDX (0x1 << 0) /**< \brief (TC_QIMR) InDeX */ -#define TC_QIMR_DIRCHG (0x1 << 1) /**< \brief (TC_QIMR) DIRection CHanGe */ -#define TC_QIMR_QERR (0x1 << 2) /**< \brief (TC_QIMR) Quadrature ERRor */ -/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ -#define TC_QISR_IDX (0x1 << 0) /**< \brief (TC_QISR) InDeX */ -#define TC_QISR_DIRCHG (0x1 << 1) /**< \brief (TC_QISR) DIRection CHanGe */ -#define TC_QISR_QERR (0x1 << 2) /**< \brief (TC_QISR) Quadrature ERRor */ -#define TC_QISR_DIR (0x1 << 8) /**< \brief (TC_QISR) Direction */ -/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */ -#define TC_FMR_ENCF0 (0x1 << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */ -#define TC_FMR_ENCF1 (0x1 << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */ -/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */ -#define TC_WPMR_WPEN (0x1 << 0) /**< \brief (TC_WPMR) Write Protect Enable */ -#define TC_WPMR_WPKEY (0xffffff << 8) /**< \brief (TC_WPMR) Write Protect KEY */ -/* -------- TC_VER : (TC Offset: 0xFC) Version Register -------- */ -#define TC_VER_VERSION (0xfff << 0) /**< \brief (TC_VER) */ -#define TC_VER_MFN (0x7 << 16) /**< \brief (TC_VER) */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Two-wire Interface */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_TWI Two-wire Interface */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Twi hardware registers */ -typedef struct { - WoReg TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */ - RwReg TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */ - RwReg TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */ - RwReg TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */ - RwReg TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */ - RwReg Reserved1[3]; - RoReg TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */ - WoReg TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */ - WoReg TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */ - RoReg TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */ - RoReg TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */ - WoReg TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */ - RwReg Reserved2[50]; - RwReg TWI_RPR; /**< \brief (Twi Offset: 0x100) Receive Pointer Register */ - RwReg TWI_RCR; /**< \brief (Twi Offset: 0x104) Receive Counter Register */ - RwReg TWI_TPR; /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */ - RwReg TWI_TCR; /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */ - RwReg TWI_RNPR; /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */ - RwReg TWI_RNCR; /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */ - RwReg TWI_TNPR; /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */ - RwReg TWI_TNCR; /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */ - WoReg TWI_PTCR; /**< \brief (Twi Offset: 0x120) Transfer Control Register */ - RoReg TWI_PTSR; /**< \brief (Twi Offset: 0x124) Transfer Status Register */ -} Twi; -#endif /* __ASSEMBLY__ */ -/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */ -#define TWI_CR_START (0x1 << 0) /**< \brief (TWI_CR) Send a START Condition */ -#define TWI_CR_STOP (0x1 << 1) /**< \brief (TWI_CR) Send a STOP Condition */ -#define TWI_CR_MSEN (0x1 << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */ -#define TWI_CR_MSDIS (0x1 << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */ -#define TWI_CR_SVEN (0x1 << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */ -#define TWI_CR_SVDIS (0x1 << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */ -#define TWI_CR_QUICK (0x1 << 6) /**< \brief (TWI_CR) SMBUS Quick Command */ -#define TWI_CR_SWRST (0x1 << 7) /**< \brief (TWI_CR) Software Reset */ -/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */ -#define TWI_MMR_IADRSZ (0x3 << 8) /**< \brief (TWI_MMR) Internal Device Address Size */ -#define TWI_MMR_IADRSZ_NO (0x0 << 8) /**< \brief (TWI_MMR) No internal device address */ -#define TWI_MMR_IADRSZ_1_BYTE (0x1 << 8) /**< \brief (TWI_MMR) One-byte internal device address */ -#define TWI_MMR_IADRSZ_2_BYTE (0x2 << 8) /**< \brief (TWI_MMR) Two-byte internal device address */ -#define TWI_MMR_IADRSZ_3_BYTE (0x3 << 8) /**< \brief (TWI_MMR) Three-byte internal device address */ -#define TWI_MMR_MREAD (0x1 << 12) /**< \brief (TWI_MMR) Master Read Direction */ -#define TWI_MMR_DADR (0x7f << 16) /**< \brief (TWI_MMR) Device Address */ -/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */ -#define TWI_SMR_SADR (0x7f << 16) /**< \brief (TWI_SMR) Slave Address */ -/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */ -#define TWI_IADR_IADR (0xffffff << 0) /**< \brief (TWI_IADR) Internal Address */ -/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */ -#define TWI_CWGR_CLDIV (0xff << 0) /**< \brief (TWI_CWGR) Clock Low Divider */ -#define TWI_CWGR_CHDIV (0xff << 8) /**< \brief (TWI_CWGR) Clock High Divider */ -#define TWI_CWGR_CKDIV (0x7 << 16) /**< \brief (TWI_CWGR) Clock Divider */ -/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */ -#define TWI_SR_TXCOMP (0x1 << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */ -#define TWI_SR_RXRDY (0x1 << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */ -#define TWI_SR_TXRDY (0x1 << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */ -#define TWI_SR_SVREAD (0x1 << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */ -#define TWI_SR_SVACC (0x1 << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */ -#define TWI_SR_GACC (0x1 << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */ -#define TWI_SR_OVRE (0x1 << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */ -#define TWI_SR_NACK (0x1 << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */ -#define TWI_SR_ARBLST (0x1 << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */ -#define TWI_SR_SCLWS (0x1 << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */ -#define TWI_SR_EOSACC (0x1 << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */ -#define TWI_SR_ENDRX (0x1 << 12) /**< \brief (TWI_SR) End of RX buffer */ -#define TWI_SR_ENDTX (0x1 << 13) /**< \brief (TWI_SR) End of TX buffer */ -#define TWI_SR_RXBUFF (0x1 << 14) /**< \brief (TWI_SR) RX Buffer Full */ -#define TWI_SR_TXBUFE (0x1 << 15) /**< \brief (TWI_SR) TX Buffer Empty */ -/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */ -#define TWI_IER_TXCOMP (0x1 << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */ -#define TWI_IER_RXRDY (0x1 << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */ -#define TWI_IER_TXRDY (0x1 << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */ -#define TWI_IER_SVACC (0x1 << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */ -#define TWI_IER_GACC (0x1 << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */ -#define TWI_IER_OVRE (0x1 << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */ -#define TWI_IER_NACK (0x1 << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */ -#define TWI_IER_ARBLST (0x1 << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */ -#define TWI_IER_SCL_WS (0x1 << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */ -#define TWI_IER_EOSACC (0x1 << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */ -#define TWI_IER_ENDRX (0x1 << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */ -#define TWI_IER_ENDTX (0x1 << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */ -#define TWI_IER_RXBUFF (0x1 << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */ -#define TWI_IER_TXBUFE (0x1 << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */ -/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */ -#define TWI_IDR_TXCOMP (0x1 << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */ -#define TWI_IDR_RXRDY (0x1 << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */ -#define TWI_IDR_TXRDY (0x1 << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */ -#define TWI_IDR_SVACC (0x1 << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */ -#define TWI_IDR_GACC (0x1 << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */ -#define TWI_IDR_OVRE (0x1 << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */ -#define TWI_IDR_NACK (0x1 << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */ -#define TWI_IDR_ARBLST (0x1 << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */ -#define TWI_IDR_SCL_WS (0x1 << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */ -#define TWI_IDR_EOSACC (0x1 << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */ -#define TWI_IDR_ENDRX (0x1 << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */ -#define TWI_IDR_ENDTX (0x1 << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */ -#define TWI_IDR_RXBUFF (0x1 << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */ -#define TWI_IDR_TXBUFE (0x1 << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */ -/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */ -#define TWI_IMR_TXCOMP (0x1 << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */ -#define TWI_IMR_RXRDY (0x1 << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */ -#define TWI_IMR_TXRDY (0x1 << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */ -#define TWI_IMR_SVACC (0x1 << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */ -#define TWI_IMR_GACC (0x1 << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */ -#define TWI_IMR_OVRE (0x1 << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */ -#define TWI_IMR_NACK (0x1 << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */ -#define TWI_IMR_ARBLST (0x1 << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */ -#define TWI_IMR_SCL_WS (0x1 << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */ -#define TWI_IMR_EOSACC (0x1 << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */ -#define TWI_IMR_ENDRX (0x1 << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */ -#define TWI_IMR_ENDTX (0x1 << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */ -#define TWI_IMR_RXBUFF (0x1 << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */ -#define TWI_IMR_TXBUFE (0x1 << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */ -/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */ -#define TWI_RHR_RXDATA (0xff << 0) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */ -/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */ -#define TWI_THR_TXDATA (0xff << 0) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */ -/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */ -#define TWI_RPR_RXPTR (0xffffffff << 0) /**< \brief (TWI_RPR) Receive Pointer Register */ -/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */ -#define TWI_RCR_RXCTR (0xffff << 0) /**< \brief (TWI_RCR) Receive Counter Register */ -/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */ -#define TWI_TPR_TXPTR (0xffffffff << 0) /**< \brief (TWI_TPR) Transmit Counter Register */ -/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */ -#define TWI_TCR_TXCTR (0xffff << 0) /**< \brief (TWI_TCR) Transmit Counter Register */ -/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */ -#define TWI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (TWI_RNPR) Receive Next Pointer */ -/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */ -#define TWI_RNCR_RXNCTR (0xffff << 0) /**< \brief (TWI_RNCR) Receive Next Counter */ -/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */ -#define TWI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (TWI_TNPR) Transmit Next Pointer */ -/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */ -#define TWI_TNCR_TXNCTR (0xffff << 0) /**< \brief (TWI_TNCR) Transmit Counter Next */ -/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */ -#define TWI_PTCR_RXTEN (0x1 << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */ -#define TWI_PTCR_RXTDIS (0x1 << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */ -#define TWI_PTCR_TXTEN (0x1 << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */ -#define TWI_PTCR_TXTDIS (0x1 << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */ -/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */ -#define TWI_PTSR_RXTEN (0x1 << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */ -#define TWI_PTSR_TXTEN (0x1 << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_UART Universal Asynchronous Receiver Transmitter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Uart hardware registers */ -typedef struct { - WoReg UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ - RwReg UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ - WoReg UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ - WoReg UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ - RoReg UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ - RoReg UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ - RoReg UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ - WoReg UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ - RwReg UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ - RwReg Reserved1[55]; - RwReg UART_RPR; /**< \brief (Uart Offset: 0x100) Receive Pointer Register */ - RwReg UART_RCR; /**< \brief (Uart Offset: 0x104) Receive Counter Register */ - RwReg UART_TPR; /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */ - RwReg UART_TCR; /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */ - RwReg UART_RNPR; /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */ - RwReg UART_RNCR; /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */ - RwReg UART_TNPR; /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */ - RwReg UART_TNCR; /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */ - WoReg UART_PTCR; /**< \brief (Uart Offset: 0x120) Transfer Control Register */ - RoReg UART_PTSR; /**< \brief (Uart Offset: 0x124) Transfer Status Register */ -} Uart; -#endif /* __ASSEMBLY__ */ -/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ -#define UART_CR_RSTRX (0x1 << 2) /**< \brief (UART_CR) Reset Receiver */ -#define UART_CR_RSTTX (0x1 << 3) /**< \brief (UART_CR) Reset Transmitter */ -#define UART_CR_RXEN (0x1 << 4) /**< \brief (UART_CR) Receiver Enable */ -#define UART_CR_RXDIS (0x1 << 5) /**< \brief (UART_CR) Receiver Disable */ -#define UART_CR_TXEN (0x1 << 6) /**< \brief (UART_CR) Transmitter Enable */ -#define UART_CR_TXDIS (0x1 << 7) /**< \brief (UART_CR) Transmitter Disable */ -#define UART_CR_RSTSTA (0x1 << 8) /**< \brief (UART_CR) Reset Status Bits */ -/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ -#define UART_MR_PAR (0x7 << 9) /**< \brief (UART_MR) Parity Type */ -#define UART_MR_CHMODE (0x3 << 14) /**< \brief (UART_MR) Channel Mode */ -/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ -#define UART_IER_RXRDY (0x1 << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ -#define UART_IER_TXRDY (0x1 << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ -#define UART_IER_ENDRX (0x1 << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */ -#define UART_IER_ENDTX (0x1 << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */ -#define UART_IER_OVRE (0x1 << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ -#define UART_IER_FRAME (0x1 << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ -#define UART_IER_PARE (0x1 << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ -#define UART_IER_TXEMPTY (0x1 << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ -#define UART_IER_TXBUFE (0x1 << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */ -#define UART_IER_RXBUFF (0x1 << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */ -/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ -#define UART_IDR_RXRDY (0x1 << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ -#define UART_IDR_TXRDY (0x1 << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ -#define UART_IDR_ENDRX (0x1 << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */ -#define UART_IDR_ENDTX (0x1 << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */ -#define UART_IDR_OVRE (0x1 << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ -#define UART_IDR_FRAME (0x1 << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ -#define UART_IDR_PARE (0x1 << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ -#define UART_IDR_TXEMPTY (0x1 << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ -#define UART_IDR_TXBUFE (0x1 << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */ -#define UART_IDR_RXBUFF (0x1 << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */ -/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ -#define UART_IMR_RXRDY (0x1 << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ -#define UART_IMR_TXRDY (0x1 << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ -#define UART_IMR_ENDRX (0x1 << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */ -#define UART_IMR_ENDTX (0x1 << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */ -#define UART_IMR_OVRE (0x1 << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ -#define UART_IMR_FRAME (0x1 << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ -#define UART_IMR_PARE (0x1 << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ -#define UART_IMR_TXEMPTY (0x1 << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ -#define UART_IMR_TXBUFE (0x1 << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */ -#define UART_IMR_RXBUFF (0x1 << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */ -/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ -#define UART_SR_RXRDY (0x1 << 0) /**< \brief (UART_SR) Receiver Ready */ -#define UART_SR_TXRDY (0x1 << 1) /**< \brief (UART_SR) Transmitter Ready */ -#define UART_SR_ENDRX (0x1 << 3) /**< \brief (UART_SR) End of Receiver Transfer */ -#define UART_SR_ENDTX (0x1 << 4) /**< \brief (UART_SR) End of Transmitter Transfer */ -#define UART_SR_OVRE (0x1 << 5) /**< \brief (UART_SR) Overrun Error */ -#define UART_SR_FRAME (0x1 << 6) /**< \brief (UART_SR) Framing Error */ -#define UART_SR_PARE (0x1 << 7) /**< \brief (UART_SR) Parity Error */ -#define UART_SR_TXEMPTY (0x1 << 9) /**< \brief (UART_SR) Transmitter Empty */ -#define UART_SR_TXBUFE (0x1 << 11) /**< \brief (UART_SR) Transmission Buffer Empty */ -#define UART_SR_RXBUFF (0x1 << 12) /**< \brief (UART_SR) Receive Buffer Full */ -/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ -#define UART_RHR_RXCHR (0xff << 0) /**< \brief (UART_RHR) Received Character */ -/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ -#define UART_THR_TXCHR (0xff << 0) /**< \brief (UART_THR) Character to be Transmitted */ -/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ -#define UART_BRGR_CD (0xffff << 0) /**< \brief (UART_BRGR) Clock Divisor */ -/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */ -#define UART_RPR_RXPTR (0xffffffff << 0) /**< \brief (UART_RPR) Receive Pointer Register */ -/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */ -#define UART_RCR_RXCTR (0xffff << 0) /**< \brief (UART_RCR) Receive Counter Register */ -/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */ -#define UART_TPR_TXPTR (0xffffffff << 0) /**< \brief (UART_TPR) Transmit Counter Register */ -/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */ -#define UART_TCR_TXCTR (0xffff << 0) /**< \brief (UART_TCR) Transmit Counter Register */ -/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */ -#define UART_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (UART_RNPR) Receive Next Pointer */ -/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */ -#define UART_RNCR_RXNCTR (0xffff << 0) /**< \brief (UART_RNCR) Receive Next Counter */ -/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */ -#define UART_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (UART_TNPR) Transmit Next Pointer */ -/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */ -#define UART_TNCR_TXNCTR (0xffff << 0) /**< \brief (UART_TNCR) Transmit Counter Next */ -/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */ -#define UART_PTCR_RXTEN (0x1 << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */ -#define UART_PTCR_RXTDIS (0x1 << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */ -#define UART_PTCR_TXTEN (0x1 << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */ -#define UART_PTCR_TXTDIS (0x1 << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */ -/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */ -#define UART_PTSR_RXTEN (0x1 << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */ -#define UART_PTSR_TXTEN (0x1 << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR USB Device Port */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_UDP USB Device Port */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Udp hardware registers */ -typedef struct { - RoReg UDP_FRM_NUM; /**< \brief (Udp Offset: 0x000) Frame Number Register */ - RwReg UDP_GLB_STAT; /**< \brief (Udp Offset: 0x004) Global State Register */ - RwReg UDP_FADDR; /**< \brief (Udp Offset: 0x008) Function Address Register */ - RwReg Reserved1[1]; - WoReg UDP_IER; /**< \brief (Udp Offset: 0x010) Interrupt Enable Register */ - WoReg UDP_IDR; /**< \brief (Udp Offset: 0x014) Interrupt Disable Register */ - RoReg UDP_IMR; /**< \brief (Udp Offset: 0x018) Interrupt Mask Register */ - RoReg UDP_ISR; /**< \brief (Udp Offset: 0x01C) Interrupt Status Register */ - WoReg UDP_ICR; /**< \brief (Udp Offset: 0x020) Interrupt Clear Register */ - RwReg Reserved2[1]; - RwReg UDP_RST_EP; /**< \brief (Udp Offset: 0x028) Reset Endpoint Register */ - RwReg Reserved3[1]; - RwReg UDP_CSR[8]; /**< \brief (Udp Offset: 0x30) Endpoint Control and Status Register (ept_num = 0) */ - RwReg UDP_FDR[8]; /**< \brief (Udp Offset: 0x50) Endpoint FIFO Data Register (ept_num = 0) */ - RwReg Reserved4[1]; - RwReg UDP_TXVC; /**< \brief (Udp Offset: 0x074) Transceiver Control Register */ -} Udp; -#endif /* __ASSEMBLY__ */ -/* -------- UDP_FRM_NUM : (UDP Offset: 0x000) Frame Number Register -------- */ -#define UDP_FRM_NUM_FRM_NUM (0x7ff << 0) /**< \brief (UDP_FRM_NUM) Frame Number as Defined in the Packet Field Formats */ -#define UDP_FRM_NUM_FRM_ERR (0x1 << 16) /**< \brief (UDP_FRM_NUM) Frame Error */ -#define UDP_FRM_NUM_FRM_OK (0x1 << 17) /**< \brief (UDP_FRM_NUM) Frame OK */ -/* -------- UDP_GLB_STAT : (UDP Offset: 0x004) Global State Register -------- */ -#define UDP_GLB_STAT_FADDEN (0x1 << 0) /**< \brief (UDP_GLB_STAT) Function Address Enable */ -#define UDP_GLB_STAT_CONFG (0x1 << 1) /**< \brief (UDP_GLB_STAT) Configured */ -#define UDP_GLB_STAT_ESR (0x1 << 2) /**< \brief (UDP_GLB_STAT) Enable Send Resume */ -#define UDP_GLB_STAT_RSMINPR (0x1 << 3) /**< \brief (UDP_GLB_STAT) */ -#define UDP_GLB_STAT_RMWUPE (0x1 << 4) /**< \brief (UDP_GLB_STAT) Remote Wake Up Enable */ -/* -------- UDP_FADDR : (UDP Offset: 0x008) Function Address Register -------- */ -#define UDP_FADDR_FADD (0x7f << 0) /**< \brief (UDP_FADDR) Function Address Value */ -#define UDP_FADDR_FEN (0x1 << 8) /**< \brief (UDP_FADDR) Function Enable */ -/* -------- UDP_IER : (UDP Offset: 0x010) Interrupt Enable Register -------- */ -#define UDP_IER_EP0INT (0x1 << 0) /**< \brief (UDP_IER) Enable Endpoint 0 Interrupt */ -#define UDP_IER_EP1INT (0x1 << 1) /**< \brief (UDP_IER) Enable Endpoint 1 Interrupt */ -#define UDP_IER_EP2INT (0x1 << 2) /**< \brief (UDP_IER) Enable Endpoint 2Interrupt */ -#define UDP_IER_EP3INT (0x1 << 3) /**< \brief (UDP_IER) Enable Endpoint 3 Interrupt */ -#define UDP_IER_EP4INT (0x1 << 4) /**< \brief (UDP_IER) Enable Endpoint 4 Interrupt */ -#define UDP_IER_EP5INT (0x1 << 5) /**< \brief (UDP_IER) Enable Endpoint 5 Interrupt */ -#define UDP_IER_EP6INT (0x1 << 6) /**< \brief (UDP_IER) Enable Endpoint 6 Interrupt */ -#define UDP_IER_EP7INT (0x1 << 7) /**< \brief (UDP_IER) Enable Endpoint 7 Interrupt */ -#define UDP_IER_RXSUSP (0x1 << 8) /**< \brief (UDP_IER) Enable UDP Suspend Interrupt */ -#define UDP_IER_RXRSM (0x1 << 9) /**< \brief (UDP_IER) Enable UDP Resume Interrupt */ -#define UDP_IER_EXTRSM (0x1 << 10) /**< \brief (UDP_IER) */ -#define UDP_IER_SOFINT (0x1 << 11) /**< \brief (UDP_IER) Enable Start Of Frame Interrupt */ -#define UDP_IER_WAKEUP (0x1 << 13) /**< \brief (UDP_IER) Enable UDP bus Wakeup Interrupt */ -/* -------- UDP_IDR : (UDP Offset: 0x014) Interrupt Disable Register -------- */ -#define UDP_IDR_EP0INT (0x1 << 0) /**< \brief (UDP_IDR) Disable Endpoint 0 Interrupt */ -#define UDP_IDR_EP1INT (0x1 << 1) /**< \brief (UDP_IDR) Disable Endpoint 1 Interrupt */ -#define UDP_IDR_EP2INT (0x1 << 2) /**< \brief (UDP_IDR) Disable Endpoint 2 Interrupt */ -#define UDP_IDR_EP3INT (0x1 << 3) /**< \brief (UDP_IDR) Disable Endpoint 3 Interrupt */ -#define UDP_IDR_EP4INT (0x1 << 4) /**< \brief (UDP_IDR) Disable Endpoint 4 Interrupt */ -#define UDP_IDR_EP5INT (0x1 << 5) /**< \brief (UDP_IDR) Disable Endpoint 5 Interrupt */ -#define UDP_IDR_EP6INT (0x1 << 6) /**< \brief (UDP_IDR) Disable Endpoint 6 Interrupt */ -#define UDP_IDR_EP7INT (0x1 << 7) /**< \brief (UDP_IDR) Disable Endpoint 7 Interrupt */ -#define UDP_IDR_RXSUSP (0x1 << 8) /**< \brief (UDP_IDR) Disable UDP Suspend Interrupt */ -#define UDP_IDR_RXRSM (0x1 << 9) /**< \brief (UDP_IDR) Disable UDP Resume Interrupt */ -#define UDP_IDR_EXTRSM (0x1 << 10) /**< \brief (UDP_IDR) */ -#define UDP_IDR_SOFINT (0x1 << 11) /**< \brief (UDP_IDR) Disable Start Of Frame Interrupt */ -#define UDP_IDR_WAKEUP (0x1 << 13) /**< \brief (UDP_IDR) Disable USB Bus Interrupt */ -/* -------- UDP_IMR : (UDP Offset: 0x018) Interrupt Mask Register -------- */ -#define UDP_IMR_EP0INT (0x1 << 0) /**< \brief (UDP_IMR) Mask Endpoint 0 Interrupt */ -#define UDP_IMR_EP1INT (0x1 << 1) /**< \brief (UDP_IMR) Mask Endpoint 1 Interrupt */ -#define UDP_IMR_EP2INT (0x1 << 2) /**< \brief (UDP_IMR) Mask Endpoint 2 Interrupt */ -#define UDP_IMR_EP3INT (0x1 << 3) /**< \brief (UDP_IMR) Mask Endpoint 3 Interrupt */ -#define UDP_IMR_EP4INT (0x1 << 4) /**< \brief (UDP_IMR) Mask Endpoint 4 Interrupt */ -#define UDP_IMR_EP5INT (0x1 << 5) /**< \brief (UDP_IMR) Mask Endpoint 5 Interrupt */ -#define UDP_IMR_EP6INT (0x1 << 6) /**< \brief (UDP_IMR) Mask Endpoint 6 Interrupt */ -#define UDP_IMR_EP7INT (0x1 << 7) /**< \brief (UDP_IMR) Mask Endpoint 7 Interrupt */ -#define UDP_IMR_RXSUSP (0x1 << 8) /**< \brief (UDP_IMR) Mask UDP Suspend Interrupt */ -#define UDP_IMR_RXRSM (0x1 << 9) /**< \brief (UDP_IMR) Mask UDP Resume Interrupt. */ -#define UDP_IMR_EXTRSM (0x1 << 10) /**< \brief (UDP_IMR) */ -#define UDP_IMR_SOFINT (0x1 << 11) /**< \brief (UDP_IMR) Mask Start Of Frame Interrupt */ -#define UDP_IMR_BIT12 (0x1 << 12) /**< \brief (UDP_IMR) UDP_IMR Bit 12 */ -#define UDP_IMR_WAKEUP (0x1 << 13) /**< \brief (UDP_IMR) USB Bus WAKEUP Interrupt */ -/* -------- UDP_ISR : (UDP Offset: 0x01C) Interrupt Status Register -------- */ -#define UDP_ISR_EP0INT (0x1 << 0) /**< \brief (UDP_ISR) Endpoint 0 Interrupt Status */ -#define UDP_ISR_EP1INT (0x1 << 1) /**< \brief (UDP_ISR) Endpoint 1 Interrupt Status */ -#define UDP_ISR_EP2INT (0x1 << 2) /**< \brief (UDP_ISR) Endpoint 2 Interrupt Status */ -#define UDP_ISR_EP3INT (0x1 << 3) /**< \brief (UDP_ISR) Endpoint 3 Interrupt Status */ -#define UDP_ISR_EP4INT (0x1 << 4) /**< \brief (UDP_ISR) Endpoint 4 Interrupt Status */ -#define UDP_ISR_EP5INT (0x1 << 5) /**< \brief (UDP_ISR) Endpoint 5 Interrupt Status */ -#define UDP_ISR_EP6INT (0x1 << 6) /**< \brief (UDP_ISR) Endpoint 6 Interrupt Status */ -#define UDP_ISR_EP7INT (0x1 << 7) /**< \brief (UDP_ISR) Endpoint 7Interrupt Status */ -#define UDP_ISR_RXSUSP (0x1 << 8) /**< \brief (UDP_ISR) UDP Suspend Interrupt Status */ -#define UDP_ISR_RXRSM (0x1 << 9) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */ -#define UDP_ISR_EXTRSM (0x1 << 10) /**< \brief (UDP_ISR) */ -#define UDP_ISR_SOFINT (0x1 << 11) /**< \brief (UDP_ISR) Start of Frame Interrupt Status */ -#define UDP_ISR_ENDBUSRES (0x1 << 12) /**< \brief (UDP_ISR) End of BUS Reset Interrupt Status */ -#define UDP_ISR_WAKEUP (0x1 << 13) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */ -/* -------- UDP_ICR : (UDP Offset: 0x020) Interrupt Clear Register -------- */ -#define UDP_ICR_RXSUSP (0x1 << 8) /**< \brief (UDP_ICR) Clear UDP Suspend Interrupt */ -#define UDP_ICR_RXRSM (0x1 << 9) /**< \brief (UDP_ICR) Clear UDP Resume Interrupt */ -#define UDP_ICR_EXTRSM (0x1 << 10) /**< \brief (UDP_ICR) */ -#define UDP_ICR_SOFINT (0x1 << 11) /**< \brief (UDP_ICR) Clear Start Of Frame Interrupt */ -#define UDP_ICR_ENDBUSRES (0x1 << 12) /**< \brief (UDP_ICR) Clear End of Bus Reset Interrupt */ -#define UDP_ICR_WAKEUP (0x1 << 13) /**< \brief (UDP_ICR) Clear Wakeup Interrupt */ -/* -------- UDP_RST_EP : (UDP Offset: 0x028) Reset Endpoint Register -------- */ -#define UDP_RST_EP_EP0 (0x1 << 0) /**< \brief (UDP_RST_EP) Reset Endpoint 0 */ -#define UDP_RST_EP_EP1 (0x1 << 1) /**< \brief (UDP_RST_EP) Reset Endpoint 1 */ -#define UDP_RST_EP_EP2 (0x1 << 2) /**< \brief (UDP_RST_EP) Reset Endpoint 2 */ -#define UDP_RST_EP_EP3 (0x1 << 3) /**< \brief (UDP_RST_EP) Reset Endpoint 3 */ -#define UDP_RST_EP_EP4 (0x1 << 4) /**< \brief (UDP_RST_EP) Reset Endpoint 4 */ -#define UDP_RST_EP_EP5 (0x1 << 5) /**< \brief (UDP_RST_EP) Reset Endpoint 5 */ -#define UDP_RST_EP_EP6 (0x1 << 6) /**< \brief (UDP_RST_EP) Reset Endpoint 6 */ -#define UDP_RST_EP_EP7 (0x1 << 7) /**< \brief (UDP_RST_EP) Reset Endpoint 7 */ -/* -------- UDP_CSR[8] : (UDP Offset: 0x2C) Endpoint Control and Status Register (ept_num = 0) -------- */ -#define UDP_CSR_TXCOMP (0x1 << 0) /**< \brief (UDP_CSR[8]) Generates an IN Packet with Data Previously Written in the DPR */ -#define UDP_CSR_RX_DATA_BK0 (0x1 << 1) /**< \brief (UDP_CSR[8]) Receive Data Bank 0 */ -#define UDP_CSR_RXSETUP (0x1 << 2) /**< \brief (UDP_CSR[8]) Received Setup */ -#define UDP_CSR_STALLSENTISOERROR (0x1 << 3) /**< \brief (UDP_CSR[8]) */ -#define UDP_CSR_TXPKTRDY (0x1 << 4) /**< \brief (UDP_CSR[8]) Transmit Packet Ready */ -#define UDP_CSR_FORCESTALL (0x1 << 5) /**< \brief (UDP_CSR[8]) Force Stall (used by Control, Bulk and Isochronous Endpoints) */ -#define UDP_CSR_RX_DATA_BK1 (0x1 << 6) /**< \brief (UDP_CSR[8]) Receive Data Bank 1 (only used by endpoints with ping-pong attributes) */ -#define UDP_CSR_DIR (0x1 << 7) /**< \brief (UDP_CSR[8]) Transfer Direction (only available for control endpoints) */ -#define UDP_CSR_EPTYPE (0x7 << 8) /**< \brief (UDP_CSR[8]) Endpoint Type */ -#define UDP_CSR_EPTYPE_CTRL (0x0 << 8) /**< \brief (UDP_CSR[8]) Control */ -#define UDP_CSR_EPTYPE_ISO_OUT (0x1 << 8) /**< \brief (UDP_CSR[8]) Isochronous OUT */ -#define UDP_CSR_EPTYPE_BULK_OUT (0x2 << 8) /**< \brief (UDP_CSR[8]) Bulk OUT */ -#define UDP_CSR_EPTYPE_INT_OUT (0x3 << 8) /**< \brief (UDP_CSR[8]) Interrupt OUT */ -#define UDP_CSR_EPTYPE_ISO_IN (0x5 << 8) /**< \brief (UDP_CSR[8]) Isochronous IN */ -#define UDP_CSR_EPTYPE_BULK_IN (0x6 << 8) /**< \brief (UDP_CSR[8]) Bulk IN */ -#define UDP_CSR_EPTYPE_INT_IN (0x7 << 8) /**< \brief (UDP_CSR[8]) Interrupt IN */ -#define UDP_CSR_DTGLE (0x1 << 11) /**< \brief (UDP_CSR[8]) Data Toggle */ -#define UDP_CSR_EPEDS (0x1 << 15) /**< \brief (UDP_CSR[8]) Endpoint Enable Disable */ -#define UDP_CSR_RXBYTECNT (0x7ff << 16) /**< \brief (UDP_CSR[8]) Number of Bytes Available in the FIFO */ -/* -------- UDP_FDR[8] : (UDP Offset: 0x4C) Endpoint FIFO Data Register (ept_num = 0) -------- */ -#define UDP_FDR_FIFO_DATA (0xff << 0) /**< \brief (UDP_FDR[8]) FIFO Data Value */ -/* -------- UDP_TXVC : (UDP Offset: 0x074) Transceiver Control Register -------- */ -#define UDP_TXVC_TXVDIS (0x1 << 8) /**< \brief (UDP_TXVC) Transceiver Disable */ -#define UDP_TXVC_PUON (0x1 << 9) /**< \brief (UDP_TXVC) Pullup On */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_USART Universal Synchronous Asynchronous Receiver Transmitter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Usart hardware registers */ -typedef struct { - WoReg US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */ - RwReg US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */ - WoReg US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */ - WoReg US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */ - RoReg US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */ - RoReg US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */ - RoReg US_RHR; /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */ - WoReg US_THR; /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */ - RwReg US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */ - RwReg US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */ - RwReg US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */ - RwReg Reserved1[5]; - RwReg US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */ - RoReg US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */ - RwReg Reserved2[1]; - RwReg US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */ - RwReg US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */ - RwReg Reserved3[36]; - RwReg US_WPMR; /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */ - RoReg US_WPSR; /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */ - RwReg Reserved4[4]; - RoReg US_VERSION; /**< \brief (Usart Offset: 0xFC) Version Register */ - RwReg US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */ - RwReg US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */ - RwReg US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */ - RwReg US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */ - RwReg US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */ - RwReg US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */ - RwReg US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */ - RwReg US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */ - WoReg US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */ - RoReg US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */ -} Usart; -#endif /* __ASSEMBLY__ */ -/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */ -#define US_CR_RSTRX (0x1 << 2) /**< \brief (US_CR) Reset Receiver */ -#define US_CR_RSTTX (0x1 << 3) /**< \brief (US_CR) Reset Transmitter */ -#define US_CR_RXEN (0x1 << 4) /**< \brief (US_CR) Receiver Enable */ -#define US_CR_RXDIS (0x1 << 5) /**< \brief (US_CR) Receiver Disable */ -#define US_CR_TXEN (0x1 << 6) /**< \brief (US_CR) Transmitter Enable */ -#define US_CR_TXDIS (0x1 << 7) /**< \brief (US_CR) Transmitter Disable */ -#define US_CR_RSTSTA (0x1 << 8) /**< \brief (US_CR) Reset Status Bits */ -#define US_CR_STTBRK (0x1 << 9) /**< \brief (US_CR) Start Break */ -#define US_CR_STPBRK (0x1 << 10) /**< \brief (US_CR) Stop Break */ -#define US_CR_STTTO (0x1 << 11) /**< \brief (US_CR) Start Time-out */ -#define US_CR_SENDA (0x1 << 12) /**< \brief (US_CR) Send Address */ -#define US_CR_RSTIT (0x1 << 13) /**< \brief (US_CR) Reset Iterations */ -#define US_CR_RSTNACK (0x1 << 14) /**< \brief (US_CR) Reset Non Acknowledge */ -#define US_CR_RETTO (0x1 << 15) /**< \brief (US_CR) Rearm Time-out */ -#define US_CR_DTREN (0x1 << 16) /**< \brief (US_CR) Data Terminal Ready Enable */ -#define US_CR_DTRDIS (0x1 << 17) /**< \brief (US_CR) Data Terminal Ready Disable */ -#define US_CR_RTSEN__FCS (0x1 << 18) /**< \brief (US_CR) Request to Send Enable/Force SPI Chip Select */ -#define US_CR_RTSDIS__RCS (0x1 << 19) /**< \brief (US_CR) Request to Send Disable/Release SPI Chip Select */ -/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */ -#define US_MR_USART_MODE (0xf << 0) /**< \brief (US_MR) */ -#define US_MR_USART_MODE_NORMAL (0x0) /**< (USART) Normal*/ -#define US_MR_USART_MODE_RS485 (0x1) /**< (USART) RS485*/ -#define US_MR_USART_MODE_HWHSH (0x2) /**< (USART) Hardware Handshaking*/ -#define US_MR_USART_MODE_ISO7816_0 (0x4) /**< (USART) ISO7816 protocol: T = 0*/ -#define US_MR_USART_MODE_ISO7816_1 (0x6) /**< (USART) ISO7816 protocol: T = 1*/ -#define US_MR_USART_MODE_IRDA (0x8) /**< (USART) IrDA*/ -#define US_MR_USART_MODE_SPIM (0xE) /**< (USART) SPI Master*/ -#define US_MR_USART_MODE_SPIS (0xF) /**< (USART) SPI Slave*/ -#define US_MR_USCLKS (0x3 << 4) /**< \brief (US_MR) Clock Selection */ -#define US_MR_USCLKS_CLOCK (0x0 << 4) /**< (USART) MCK*/ -#define US_MR_USCLKS_FDIV1 (0x1 << 4) /**< (USART) MCK/DIV(DIV=8)*/ -#define US_MR_USCLKS_SLOW (0x2 << 4) /**< (USART) Reserved*/ -#define US_MR_USCLKS_EXT (0x3 << 4) /**< (USART) SCK*/ -#define US_MR_CHRL (0x3 << 6) /**< \brief (US_MR) Character Length. */ -#define US_MR_CHRL_5_BITS (0x0 << 6) /**< (USART) Character Length: 5 bits*/ -#define US_MR_CHRL_6_BITS (0x1 << 6) /**< (USART) Character Length: 6 bits*/ -#define US_MR_CHRL_7_BITS (0x2 << 6) /**< (USART) Character Length: 7 bits*/ -#define US_MR_CHRL_8_BITS (0x3 << 6) /**< (USART) Character Length: 8 bits*/ -#define US_MR_SYNC__CPHA (0x1 << 8) /**< \brief (US_MR) Synchronous Mode Select or SPI Clock Phase */ -#define US_MR_PAR (0x7 << 9) /**< \brief (US_MR) Parity Type */ -#define US_MR_PAR_EVEN (0x0 << 9) /**< (USART) Even Parity*/ -#define US_MR_PAR_ODD (0x1 << 9) /**< (USART) Odd Parity*/ -#define US_MR_PAR_SPACE (0x2 << 9) /**< (USART) Parity forced to 0 (Space)*/ -#define US_MR_PAR_MARK (0x3 << 9) /**< (USART) Parity forced to 1 (Mark)*/ -#define US_MR_PAR_NONE (0x4 << 9) /**< (USART) No Parity*/ -#define US_MR_PAR_MULTI_DROP (0x6 << 9) /**< (USART) Multi-drop mode*/ -#define US_MR_NBSTOP (0x3 << 12) /**< \brief (US_MR) Number of Stop Bits */ -#define US_MR_NBSTOP_1_BIT (0x0 << 12) /**< (USART) 1 stop bit*/ -#define US_MR_NBSTOP_15_BIT (0x1 << 12) /**< (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits*/ -#define US_MR_NBSTOP_2_BIT (0x2 << 12) /**< (USART) 2 stop bits*/ -#define US_MR_CHMODE (0x3 << 14) /**< \brief (US_MR) Channel Mode */ -#define US_MR_CHMODE_NORMAL (0x0 << 14) /**< (USART) Normal Mode: The USART channel operates as an RX/TX USART.*/ -#define US_MR_CHMODE_AUTO (0x1 << 14) /**< (USART) Automatic Echo: Receiver Data Input is connected to the TXD pin.*/ -#define US_MR_CHMODE_LOCAL (0x2 << 14) /**< (USART) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.*/ -#define US_MR_CHMODE_REMOTE (0x3 << 14) /**< (USART) Remote Loopback: RXD pin is internally connected to TXD pin.*/ -#define US_MR_MSBF__CPOL (0x1 << 16) /**< \brief (US_MR) Bit Order or SPI Clock Polarity */ -#define US_MR_MODE9 (0x1 << 17) /**< \brief (US_MR) 9-bit Character Length */ -#define US_MR_CLKO (0x1 << 18) /**< \brief (US_MR) Clock Output Select */ -#define US_MR_OVER (0x1 << 19) /**< \brief (US_MR) Oversampling Mode */ -#define US_MR_INACK (0x1 << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */ -#define US_MR_DSNACK (0x1 << 21) /**< \brief (US_MR) Disable Successive NACK */ -#define US_MR_VAR_SYNC (0x1 << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */ -#define US_MR_INVDATA (0x1 << 23) /**< \brief (US_MR) INverted Data */ -#define US_MR_MAX_ITERATION (0x7 << 24) /**< \brief (US_MR) */ -#define US_MR_FILTER (0x1 << 28) /**< \brief (US_MR) Infrared Receive Line Filter */ -#define US_MR_MAN (0x1 << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */ -#define US_MR_MODSYNC_ (0x1 << 30) /**< \brief (US_MR) */ -#define US_MR_ONEBIT (0x1 << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */ -/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */ -#define US_IER_RXRDY (0x1 << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */ -#define US_IER_TXRDY (0x1 << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */ -#define US_IER_RXBRK (0x1 << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */ -#define US_IER_ENDRX (0x1 << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */ -#define US_IER_ENDTX (0x1 << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */ -#define US_IER_OVRE (0x1 << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */ -#define US_IER_FRAME (0x1 << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */ -#define US_IER_PARE (0x1 << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */ -#define US_IER_TIMEOUT (0x1 << 8) /**< \brief (US_IER) Time-out Interrupt Enable */ -#define US_IER_TXEMPTY (0x1 << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */ -#define US_IER_ITER__UNRE (0x1 << 10) /**< \brief (US_IER) Iteration or SPI Underrun Error Interrupt Enable */ -#define US_IER_TXBUFE (0x1 << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */ -#define US_IER_RXBUFF (0x1 << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */ -#define US_IER_NACK (0x1 << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */ -#define US_IER_RIIC (0x1 << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */ -#define US_IER_DSRIC (0x1 << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */ -#define US_IER_DCDIC (0x1 << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */ -#define US_IER_CTSIC (0x1 << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */ -#define US_IER_MANE (0x1 << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */ -/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */ -#define US_IDR_RXRDY (0x1 << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */ -#define US_IDR_TXRDY (0x1 << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */ -#define US_IDR_RXBRK (0x1 << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */ -#define US_IDR_ENDRX (0x1 << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */ -#define US_IDR_ENDTX (0x1 << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */ -#define US_IDR_OVRE (0x1 << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */ -#define US_IDR_FRAME (0x1 << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */ -#define US_IDR_PARE (0x1 << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */ -#define US_IDR_TIMEOUT (0x1 << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */ -#define US_IDR_TXEMPTY (0x1 << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */ -#define US_IDR_ITER__UNRE (0x1 << 10) /**< \brief (US_IDR) Iteration or SPI Underrun Error Interrupt Enable */ -#define US_IDR_TXBUFE (0x1 << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */ -#define US_IDR_RXBUFF (0x1 << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */ -#define US_IDR_NACK (0x1 << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */ -#define US_IDR_RIIC (0x1 << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */ -#define US_IDR_DSRIC (0x1 << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */ -#define US_IDR_DCDIC (0x1 << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */ -#define US_IDR_CTSIC (0x1 << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */ -#define US_IDR_MANE (0x1 << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */ -/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */ -#define US_IMR_RXRDY (0x1 << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */ -#define US_IMR_TXRDY (0x1 << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */ -#define US_IMR_RXBRK (0x1 << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */ -#define US_IMR_ENDRX (0x1 << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */ -#define US_IMR_ENDTX (0x1 << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */ -#define US_IMR_OVRE (0x1 << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */ -#define US_IMR_FRAME (0x1 << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */ -#define US_IMR_PARE (0x1 << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */ -#define US_IMR_TIMEOUT (0x1 << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */ -#define US_IMR_TXEMPTY (0x1 << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */ -#define US_IMR_ITER__UNRE (0x1 << 10) /**< \brief (US_IMR) Iteration or SPI Underrun Error Interrupt Enable */ -#define US_IMR_TXBUFE (0x1 << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */ -#define US_IMR_RXBUFF (0x1 << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */ -#define US_IMR_NACK (0x1 << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */ -#define US_IMR_RIIC (0x1 << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */ -#define US_IMR_DSRIC (0x1 << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */ -#define US_IMR_DCDIC (0x1 << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */ -#define US_IMR_CTSIC (0x1 << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */ -#define US_IMR_MANE (0x1 << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */ -/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */ -#define US_CSR_RXRDY (0x1 << 0) /**< \brief (US_CSR) Receiver Ready */ -#define US_CSR_TXRDY (0x1 << 1) /**< \brief (US_CSR) Transmitter Ready */ -#define US_CSR_RXBRK (0x1 << 2) /**< \brief (US_CSR) Break Received/End of Break */ -#define US_CSR_ENDRX (0x1 << 3) /**< \brief (US_CSR) End of Receiver Transfer */ -#define US_CSR_ENDTX (0x1 << 4) /**< \brief (US_CSR) End of Transmitter Transfer */ -#define US_CSR_OVRE (0x1 << 5) /**< \brief (US_CSR) Overrun Error */ -#define US_CSR_FRAME (0x1 << 6) /**< \brief (US_CSR) Framing Error */ -#define US_CSR_PARE (0x1 << 7) /**< \brief (US_CSR) Parity Error */ -#define US_CSR_TIMEOUT (0x1 << 8) /**< \brief (US_CSR) Receiver Time-out */ -#define US_CSR_TXEMPTY (0x1 << 9) /**< \brief (US_CSR) Transmitter Empty */ -#define US_CSR_ITER__UNRE (0x1 << 10) /**< \brief (US_CSR) Max number of Repetitions Reached or SPI Underrun Error */ -#define US_CSR_TXBUFE (0x1 << 11) /**< \brief (US_CSR) Transmission Buffer Empty */ -#define US_CSR_RXBUFF (0x1 << 12) /**< \brief (US_CSR) Reception Buffer Full */ -#define US_CSR_NACK (0x1 << 13) /**< \brief (US_CSR) */ -#define US_CSR_RIIC (0x1 << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */ -#define US_CSR_DSRIC (0x1 << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */ -#define US_CSR_DCDIC (0x1 << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */ -#define US_CSR_CTSIC (0x1 << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */ -#define US_CSR_RI (0x1 << 20) /**< \brief (US_CSR) Image of RI Input */ -#define US_CSR_DSR (0x1 << 21) /**< \brief (US_CSR) Image of DSR Input */ -#define US_CSR_DCD (0x1 << 22) /**< \brief (US_CSR) Image of DCD Input */ -#define US_CSR_CTS (0x1 << 23) /**< \brief (US_CSR) Image of CTS Input */ -#define US_CSR_MANERR (0x1 << 24) /**< \brief (US_CSR) Manchester Error */ -/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */ -#define US_RHR_RXCHR (0x1ff << 0) /**< \brief (US_RHR) Received Character */ -#define US_RHR_RXSYNH (0x1 << 15) /**< \brief (US_RHR) Received Sync */ -/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */ -#define US_THR_TXCHR (0x1ff << 0) /**< \brief (US_THR) Character to be Transmitted */ -#define US_THR_TXSYNH (0x1 << 15) /**< \brief (US_THR) Sync Field to be transmitted */ -/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */ -#define US_BRGR_CD (0xffff << 0) /**< \brief (US_BRGR) Clock Divider */ -#define US_BRGR_FP (0x7 << 16) /**< \brief (US_BRGR) Fractional Part */ -/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */ -#define US_RTOR_TO (0xffff << 0) /**< \brief (US_RTOR) Time-out Value */ -/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */ -#define US_TTGR_TG (0xff << 0) /**< \brief (US_TTGR) Timeguard Value */ -/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */ -#define US_FIDI_FI_DI_RATIO (0x7ff << 0) /**< \brief (US_FIDI) FI Over DI Ratio Value */ -/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */ -#define US_NER_NB_ERRORS (0xff << 0) /**< \brief (US_NER) Number of Errors */ -/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */ -#define US_IF_IRDA_FILTER (0xff << 0) /**< \brief (US_IF) IrDA Filter */ -/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */ -#define US_MAN_TX_PL (0xf << 0) /**< \brief (US_MAN) Transmitter Preamble Length */ -#define US_MAN_TX_PP (0x3 << 8) /**< \brief (US_MAN) Transmitter Preamble Pattern */ -#define US_MAN_TX_MPOL (0x1 << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */ -#define US_MAN_RX_PL (0xf << 16) /**< \brief (US_MAN) Receiver Preamble Length */ -#define US_MAN_RX_PP (0x3 << 24) /**< \brief (US_MAN) Receiver Preamble Pattern detected */ -#define US_MAN_RX_MPOL (0x1 << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */ -#define US_MAN_STUCKTO1 (0x1 << 29) /**< \brief (US_MAN) */ -#define US_MAN_DRIFT (0x1 << 30) /**< \brief (US_MAN) Drift compensation */ -/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */ -#define US_WPMR_WPEN (0x1 << 0) /**< \brief (US_WPMR) Write Protect Enable */ -#define US_WPMR_WPKEY (0xffffff << 8) /**< \brief (US_WPMR) Write Protect KEY */ -/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */ -#define US_WPSR_WPVS (0x1 << 0) /**< \brief (US_WPSR) Write Protect Violation Status */ -#define US_WPSR_WPVSRC (0xffff << 8) /**< \brief (US_WPSR) Write Protect Violation Source */ -/* -------- US_VERSION : (USART Offset: 0xFC) Version Register -------- */ -#define US_VERSION_VERSION (0xfff << 0) /**< \brief (US_VERSION) */ -#define US_VERSION_MFN (0x7 << 16) /**< \brief (US_VERSION) */ -/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */ -#define US_RPR_RXPTR (0xffffffff << 0) /**< \brief (US_RPR) Receive Pointer Register */ -/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */ -#define US_RCR_RXCTR (0xffff << 0) /**< \brief (US_RCR) Receive Counter Register */ -/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */ -#define US_TPR_TXPTR (0xffffffff << 0) /**< \brief (US_TPR) Transmit Counter Register */ -/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */ -#define US_TCR_TXCTR (0xffff << 0) /**< \brief (US_TCR) Transmit Counter Register */ -/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */ -#define US_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (US_RNPR) Receive Next Pointer */ -/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */ -#define US_RNCR_RXNCTR (0xffff << 0) /**< \brief (US_RNCR) Receive Next Counter */ -/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */ -#define US_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (US_TNPR) Transmit Next Pointer */ -/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */ -#define US_TNCR_TXNCTR (0xffff << 0) /**< \brief (US_TNCR) Transmit Counter Next */ -/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */ -#define US_PTCR_RXTEN (0x1 << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */ -#define US_PTCR_RXTDIS (0x1 << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */ -#define US_PTCR_TXTEN (0x1 << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */ -#define US_PTCR_TXTDIS (0x1 << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */ -/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */ -#define US_PTSR_RXTEN (0x1 << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */ -#define US_PTSR_TXTEN (0x1 << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Watchdog Timer */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_WDT Watchdog Timer */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Wdt hardware registers */ -typedef struct { - WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ - RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ - RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ -} Wdt; -#endif /* __ASSEMBLY__ */ -/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ -#define WDT_CR_WDRSTT (0x1 << 0) /**< \brief (WDT_CR) Watchdog Restart */ -#define WDT_CR_KEY (0xff << 24) /**< \brief (WDT_CR) Password */ -/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ -#define WDT_MR_WDV (0xfff << 0) /**< \brief (WDT_MR) Watchdog Counter Value */ -#define WDT_MR_WDFIEN (0x1 << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ -#define WDT_MR_WDRSTEN (0x1 << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ -#define WDT_MR_WDRPROC (0x1 << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */ -#define WDT_MR_WDDIS (0x1 << 15) /**< \brief (WDT_MR) Watchdog Disable */ -#define WDT_MR_WDD (0xfff << 16) /**< \brief (WDT_MR) Watchdog Delta Value */ -#define WDT_MR_WDDBGHLT (0x1 << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ -#define WDT_MR_WDIDLEHLT (0x1 << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ -/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ -#define WDT_SR_WDUNF (0x1 << 0) /**< \brief (WDT_SR) Watchdog Underflow */ -#define WDT_SR_WDERR (0x1 << 1) /**< \brief (WDT_SR) Watchdog Error */ - -/*@}*/ - -/*@}*/ - -/* ***************************************************************************** */ -/* REGISTER ACCESS DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_reg Registers Access Definitions */ -/*@{*/ - -/* ========== Register definition for HSMCI peripheral ========== */ -#define REG_HSMCI_CR REG_ACCESS(WoReg, 0x40000000U) /**< \brief (HSMCI) Control Register */ -#define REG_HSMCI_MR REG_ACCESS(RwReg, 0x40000004U) /**< \brief (HSMCI) Mode Register */ -#define REG_HSMCI_DTOR REG_ACCESS(RwReg, 0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ -#define REG_HSMCI_SDCR REG_ACCESS(RwReg, 0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ -#define REG_HSMCI_ARGR REG_ACCESS(RwReg, 0x40000010U) /**< \brief (HSMCI) Argument Register */ -#define REG_HSMCI_CMDR REG_ACCESS(WoReg, 0x40000014U) /**< \brief (HSMCI) Command Register */ -#define REG_HSMCI_BLKR REG_ACCESS(RwReg, 0x40000018U) /**< \brief (HSMCI) Block Register */ -#define REG_HSMCI_CSTOR REG_ACCESS(RwReg, 0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ -#define REG_HSMCI_RSPR REG_ACCESS(RoReg, 0x40000020U) /**< \brief (HSMCI) Response Register */ -#define REG_HSMCI_RDR REG_ACCESS(RoReg, 0x40000030U) /**< \brief (HSMCI) Receive Data Register */ -#define REG_HSMCI_TDR REG_ACCESS(WoReg, 0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ -#define REG_HSMCI_SR REG_ACCESS(RoReg, 0x40000040U) /**< \brief (HSMCI) Status Register */ -#define REG_HSMCI_IER REG_ACCESS(WoReg, 0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ -#define REG_HSMCI_IDR REG_ACCESS(WoReg, 0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ -#define REG_HSMCI_IMR REG_ACCESS(RoReg, 0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ -#define REG_HSMCI_CFG REG_ACCESS(RwReg, 0x40000054U) /**< \brief (HSMCI) Configuration Register */ -#define REG_HSMCI_WPMR REG_ACCESS(RwReg, 0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ -#define REG_HSMCI_WPSR REG_ACCESS(RoReg, 0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ -#define REG_HSMCI_RPR REG_ACCESS(RwReg, 0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */ -#define REG_HSMCI_RCR REG_ACCESS(RwReg, 0x40000104U) /**< \brief (HSMCI) Receive Counter Register */ -#define REG_HSMCI_TPR REG_ACCESS(RwReg, 0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */ -#define REG_HSMCI_TCR REG_ACCESS(RwReg, 0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */ -#define REG_HSMCI_RNPR REG_ACCESS(RwReg, 0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */ -#define REG_HSMCI_RNCR REG_ACCESS(RwReg, 0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */ -#define REG_HSMCI_TNPR REG_ACCESS(RwReg, 0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */ -#define REG_HSMCI_TNCR REG_ACCESS(RwReg, 0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */ -#define REG_HSMCI_PTCR REG_ACCESS(WoReg, 0x40000120U) /**< \brief (HSMCI) Transfer Control Register */ -#define REG_HSMCI_PTSR REG_ACCESS(RoReg, 0x40000124U) /**< \brief (HSMCI) Transfer Status Register */ -/* ========== Register definition for SSC peripheral ========== */ -#define REG_SSC_CR REG_ACCESS(WoReg, 0x40004000U) /**< \brief (SSC) Control Register */ -#define REG_SSC_CMR REG_ACCESS(RwReg, 0x40004004U) /**< \brief (SSC) Clock Mode Register */ -#define REG_SSC_RCMR REG_ACCESS(RwReg, 0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ -#define REG_SSC_RFMR REG_ACCESS(RwReg, 0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ -#define REG_SSC_TCMR REG_ACCESS(RwReg, 0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ -#define REG_SSC_TFMR REG_ACCESS(RwReg, 0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ -#define REG_SSC_RHR REG_ACCESS(RoReg, 0x40004020U) /**< \brief (SSC) Receive Holding Register */ -#define REG_SSC_THR REG_ACCESS(WoReg, 0x40004024U) /**< \brief (SSC) Transmit Holding Register */ -#define REG_SSC_RSHR REG_ACCESS(RoReg, 0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ -#define REG_SSC_TSHR REG_ACCESS(RwReg, 0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ -#define REG_SSC_RC0R REG_ACCESS(RwReg, 0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ -#define REG_SSC_RC1R REG_ACCESS(RwReg, 0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ -#define REG_SSC_SR REG_ACCESS(RoReg, 0x40004040U) /**< \brief (SSC) Status Register */ -#define REG_SSC_IER REG_ACCESS(WoReg, 0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ -#define REG_SSC_IDR REG_ACCESS(WoReg, 0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ -#define REG_SSC_IMR REG_ACCESS(RoReg, 0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ -#define REG_SSC_WPMR REG_ACCESS(RwReg, 0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */ -#define REG_SSC_WPSR REG_ACCESS(RoReg, 0x400040E8U) /**< \brief (SSC) Write Protect Status Register */ -#define REG_SSC_RPR REG_ACCESS(RwReg, 0x40004100U) /**< \brief (SSC) Receive Pointer Register */ -#define REG_SSC_RCR REG_ACCESS(RwReg, 0x40004104U) /**< \brief (SSC) Receive Counter Register */ -#define REG_SSC_TPR REG_ACCESS(RwReg, 0x40004108U) /**< \brief (SSC) Transmit Pointer Register */ -#define REG_SSC_TCR REG_ACCESS(RwReg, 0x4000410CU) /**< \brief (SSC) Transmit Counter Register */ -#define REG_SSC_RNPR REG_ACCESS(RwReg, 0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */ -#define REG_SSC_RNCR REG_ACCESS(RwReg, 0x40004114U) /**< \brief (SSC) Receive Next Counter Register */ -#define REG_SSC_TNPR REG_ACCESS(RwReg, 0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */ -#define REG_SSC_TNCR REG_ACCESS(RwReg, 0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */ -#define REG_SSC_PTCR REG_ACCESS(WoReg, 0x40004120U) /**< \brief (SSC) Transfer Control Register */ -#define REG_SSC_PTSR REG_ACCESS(RoReg, 0x40004124U) /**< \brief (SSC) Transfer Status Register */ -/* ========== Register definition for SPI peripheral ========== */ -#define REG_SPI_CR REG_ACCESS(WoReg, 0x40008000U) /**< \brief (SPI) Control Register */ -#define REG_SPI_MR REG_ACCESS(RwReg, 0x40008004U) /**< \brief (SPI) Mode Register */ -#define REG_SPI_RDR REG_ACCESS(RoReg, 0x40008008U) /**< \brief (SPI) Receive Data Register */ -#define REG_SPI_TDR REG_ACCESS(WoReg, 0x4000800CU) /**< \brief (SPI) Transmit Data Register */ -#define REG_SPI_SR REG_ACCESS(RoReg, 0x40008010U) /**< \brief (SPI) Status Register */ -#define REG_SPI_IER REG_ACCESS(WoReg, 0x40008014U) /**< \brief (SPI) Interrupt Enable Register */ -#define REG_SPI_IDR REG_ACCESS(WoReg, 0x40008018U) /**< \brief (SPI) Interrupt Disable Register */ -#define REG_SPI_IMR REG_ACCESS(RoReg, 0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */ -#define REG_SPI_CSR REG_ACCESS(RwReg, 0x40008030U) /**< \brief (SPI) Chip Select Register */ -#define REG_SPI_WPMR REG_ACCESS(RwReg, 0x400080E4U) /**< \brief (SPI) Write Protection Control Register */ -#define REG_SPI_WPSR REG_ACCESS(RoReg, 0x400080E8U) /**< \brief (SPI) Write Protection Status Register */ -#define REG_SPI_RPR REG_ACCESS(RwReg, 0x40008100U) /**< \brief (SPI) Receive Pointer Register */ -#define REG_SPI_RCR REG_ACCESS(RwReg, 0x40008104U) /**< \brief (SPI) Receive Counter Register */ -#define REG_SPI_TPR REG_ACCESS(RwReg, 0x40008108U) /**< \brief (SPI) Transmit Pointer Register */ -#define REG_SPI_TCR REG_ACCESS(RwReg, 0x4000810CU) /**< \brief (SPI) Transmit Counter Register */ -#define REG_SPI_RNPR REG_ACCESS(RwReg, 0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */ -#define REG_SPI_RNCR REG_ACCESS(RwReg, 0x40008114U) /**< \brief (SPI) Receive Next Counter Register */ -#define REG_SPI_TNPR REG_ACCESS(RwReg, 0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */ -#define REG_SPI_TNCR REG_ACCESS(RwReg, 0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */ -#define REG_SPI_PTCR REG_ACCESS(WoReg, 0x40008120U) /**< \brief (SPI) Transfer Control Register */ -#define REG_SPI_PTSR REG_ACCESS(RoReg, 0x40008124U) /**< \brief (SPI) Transfer Status Register */ -/* ========== Register definition for TC0 peripheral ========== */ -#define REG_TC0_CCR0 REG_ACCESS(WoReg, 0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ -#define REG_TC0_CMR0 REG_ACCESS(RwReg, 0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ -#define REG_TC0_CV0 REG_ACCESS(RoReg, 0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */ -#define REG_TC0_RA0 REG_ACCESS(RwReg, 0x40010014U) /**< \brief (TC0) Register A (channel = 0) */ -#define REG_TC0_RB0 REG_ACCESS(RwReg, 0x40010018U) /**< \brief (TC0) Register B (channel = 0) */ -#define REG_TC0_RC0 REG_ACCESS(RwReg, 0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */ -#define REG_TC0_SR0 REG_ACCESS(RoReg, 0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */ -#define REG_TC0_IER0 REG_ACCESS(WoReg, 0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ -#define REG_TC0_IDR0 REG_ACCESS(WoReg, 0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ -#define REG_TC0_IMR0 REG_ACCESS(RoReg, 0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ -#define REG_TC0_CCR1 REG_ACCESS(WoReg, 0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ -#define REG_TC0_CMR1 REG_ACCESS(RwReg, 0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ -#define REG_TC0_CV1 REG_ACCESS(RoReg, 0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */ -#define REG_TC0_RA1 REG_ACCESS(RwReg, 0x40010054U) /**< \brief (TC0) Register A (channel = 1) */ -#define REG_TC0_RB1 REG_ACCESS(RwReg, 0x40010058U) /**< \brief (TC0) Register B (channel = 1) */ -#define REG_TC0_RC1 REG_ACCESS(RwReg, 0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */ -#define REG_TC0_SR1 REG_ACCESS(RoReg, 0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */ -#define REG_TC0_IER1 REG_ACCESS(WoReg, 0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ -#define REG_TC0_IDR1 REG_ACCESS(WoReg, 0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ -#define REG_TC0_IMR1 REG_ACCESS(RoReg, 0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ -#define REG_TC0_CCR2 REG_ACCESS(WoReg, 0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ -#define REG_TC0_CMR2 REG_ACCESS(RwReg, 0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ -#define REG_TC0_CV2 REG_ACCESS(RoReg, 0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */ -#define REG_TC0_RA2 REG_ACCESS(RwReg, 0x40010094U) /**< \brief (TC0) Register A (channel = 2) */ -#define REG_TC0_RB2 REG_ACCESS(RwReg, 0x40010098U) /**< \brief (TC0) Register B (channel = 2) */ -#define REG_TC0_RC2 REG_ACCESS(RwReg, 0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */ -#define REG_TC0_SR2 REG_ACCESS(RoReg, 0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */ -#define REG_TC0_IER2 REG_ACCESS(WoReg, 0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ -#define REG_TC0_IDR2 REG_ACCESS(WoReg, 0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ -#define REG_TC0_IMR2 REG_ACCESS(RoReg, 0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ -#define REG_TC0_BCR REG_ACCESS(WoReg, 0x400100C0U) /**< \brief (TC0) Block Control Register */ -#define REG_TC0_BMR REG_ACCESS(RwReg, 0x400100C4U) /**< \brief (TC0) Block Mode Register */ -#define REG_TC0_QIER REG_ACCESS(WoReg, 0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ -#define REG_TC0_QIDR REG_ACCESS(WoReg, 0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ -#define REG_TC0_QIMR REG_ACCESS(RoReg, 0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ -#define REG_TC0_QISR REG_ACCESS(RoReg, 0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ -#define REG_TC0_FMR REG_ACCESS(RwReg, 0x400100D8U) /**< \brief (TC0) Fault Mode Register */ -#define REG_TC0_WPMR REG_ACCESS(RwReg, 0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */ -#define REG_TC0_VER REG_ACCESS(RoReg, 0x400100FCU) /**< \brief (TC0) Version Register */ -/* ========== Register definition for TC1 peripheral ========== */ -#define REG_TC1_CCR0 REG_ACCESS(WoReg, 0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ -#define REG_TC1_CMR0 REG_ACCESS(RwReg, 0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ -#define REG_TC1_CV0 REG_ACCESS(RoReg, 0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */ -#define REG_TC1_RA0 REG_ACCESS(RwReg, 0x40014014U) /**< \brief (TC1) Register A (channel = 0) */ -#define REG_TC1_RB0 REG_ACCESS(RwReg, 0x40014018U) /**< \brief (TC1) Register B (channel = 0) */ -#define REG_TC1_RC0 REG_ACCESS(RwReg, 0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */ -#define REG_TC1_SR0 REG_ACCESS(RoReg, 0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */ -#define REG_TC1_IER0 REG_ACCESS(WoReg, 0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ -#define REG_TC1_IDR0 REG_ACCESS(WoReg, 0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ -#define REG_TC1_IMR0 REG_ACCESS(RoReg, 0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ -#define REG_TC1_CCR1 REG_ACCESS(WoReg, 0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ -#define REG_TC1_CMR1 REG_ACCESS(RwReg, 0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ -#define REG_TC1_CV1 REG_ACCESS(RoReg, 0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */ -#define REG_TC1_RA1 REG_ACCESS(RwReg, 0x40014054U) /**< \brief (TC1) Register A (channel = 1) */ -#define REG_TC1_RB1 REG_ACCESS(RwReg, 0x40014058U) /**< \brief (TC1) Register B (channel = 1) */ -#define REG_TC1_RC1 REG_ACCESS(RwReg, 0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */ -#define REG_TC1_SR1 REG_ACCESS(RoReg, 0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */ -#define REG_TC1_IER1 REG_ACCESS(WoReg, 0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ -#define REG_TC1_IDR1 REG_ACCESS(WoReg, 0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ -#define REG_TC1_IMR1 REG_ACCESS(RoReg, 0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ -#define REG_TC1_CCR2 REG_ACCESS(WoReg, 0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ -#define REG_TC1_CMR2 REG_ACCESS(RwReg, 0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ -#define REG_TC1_CV2 REG_ACCESS(RoReg, 0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */ -#define REG_TC1_RA2 REG_ACCESS(RwReg, 0x40014094U) /**< \brief (TC1) Register A (channel = 2) */ -#define REG_TC1_RB2 REG_ACCESS(RwReg, 0x40014098U) /**< \brief (TC1) Register B (channel = 2) */ -#define REG_TC1_RC2 REG_ACCESS(RwReg, 0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */ -#define REG_TC1_SR2 REG_ACCESS(RoReg, 0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */ -#define REG_TC1_IER2 REG_ACCESS(WoReg, 0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ -#define REG_TC1_IDR2 REG_ACCESS(WoReg, 0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ -#define REG_TC1_IMR2 REG_ACCESS(RoReg, 0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ -#define REG_TC1_BCR REG_ACCESS(WoReg, 0x400140C0U) /**< \brief (TC1) Block Control Register */ -#define REG_TC1_BMR REG_ACCESS(RwReg, 0x400140C4U) /**< \brief (TC1) Block Mode Register */ -#define REG_TC1_QIER REG_ACCESS(WoReg, 0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ -#define REG_TC1_QIDR REG_ACCESS(WoReg, 0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ -#define REG_TC1_QIMR REG_ACCESS(RoReg, 0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ -#define REG_TC1_QISR REG_ACCESS(RoReg, 0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ -#define REG_TC1_FMR REG_ACCESS(RwReg, 0x400140D8U) /**< \brief (TC1) Fault Mode Register */ -#define REG_TC1_WPMR REG_ACCESS(RwReg, 0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */ -#define REG_TC1_VER REG_ACCESS(RoReg, 0x400140FCU) /**< \brief (TC1) Version Register */ -/* ========== Register definition for TWI0 peripheral ========== */ -#define REG_TWI0_CR REG_ACCESS(WoReg, 0x40018000U) /**< \brief (TWI0) Control Register */ -#define REG_TWI0_MMR REG_ACCESS(RwReg, 0x40018004U) /**< \brief (TWI0) Master Mode Register */ -#define REG_TWI0_SMR REG_ACCESS(RwReg, 0x40018008U) /**< \brief (TWI0) Slave Mode Register */ -#define REG_TWI0_IADR REG_ACCESS(RwReg, 0x4001800CU) /**< \brief (TWI0) Internal Address Register */ -#define REG_TWI0_CWGR REG_ACCESS(RwReg, 0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */ -#define REG_TWI0_SR REG_ACCESS(RoReg, 0x40018020U) /**< \brief (TWI0) Status Register */ -#define REG_TWI0_IER REG_ACCESS(WoReg, 0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */ -#define REG_TWI0_IDR REG_ACCESS(WoReg, 0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */ -#define REG_TWI0_IMR REG_ACCESS(RoReg, 0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */ -#define REG_TWI0_RHR REG_ACCESS(RoReg, 0x40018030U) /**< \brief (TWI0) Receive Holding Register */ -#define REG_TWI0_THR REG_ACCESS(WoReg, 0x40018034U) /**< \brief (TWI0) Transmit Holding Register */ -#define REG_TWI0_RPR REG_ACCESS(RwReg, 0x40018100U) /**< \brief (TWI0) Receive Pointer Register */ -#define REG_TWI0_RCR REG_ACCESS(RwReg, 0x40018104U) /**< \brief (TWI0) Receive Counter Register */ -#define REG_TWI0_TPR REG_ACCESS(RwReg, 0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */ -#define REG_TWI0_TCR REG_ACCESS(RwReg, 0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */ -#define REG_TWI0_RNPR REG_ACCESS(RwReg, 0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */ -#define REG_TWI0_RNCR REG_ACCESS(RwReg, 0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */ -#define REG_TWI0_TNPR REG_ACCESS(RwReg, 0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */ -#define REG_TWI0_TNCR REG_ACCESS(RwReg, 0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */ -#define REG_TWI0_PTCR REG_ACCESS(WoReg, 0x40018120U) /**< \brief (TWI0) Transfer Control Register */ -#define REG_TWI0_PTSR REG_ACCESS(RoReg, 0x40018124U) /**< \brief (TWI0) Transfer Status Register */ -/* ========== Register definition for TWI1 peripheral ========== */ -#define REG_TWI1_CR REG_ACCESS(WoReg, 0x4001C000U) /**< \brief (TWI1) Control Register */ -#define REG_TWI1_MMR REG_ACCESS(RwReg, 0x4001C004U) /**< \brief (TWI1) Master Mode Register */ -#define REG_TWI1_SMR REG_ACCESS(RwReg, 0x4001C008U) /**< \brief (TWI1) Slave Mode Register */ -#define REG_TWI1_IADR REG_ACCESS(RwReg, 0x4001C00CU) /**< \brief (TWI1) Internal Address Register */ -#define REG_TWI1_CWGR REG_ACCESS(RwReg, 0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */ -#define REG_TWI1_SR REG_ACCESS(RoReg, 0x4001C020U) /**< \brief (TWI1) Status Register */ -#define REG_TWI1_IER REG_ACCESS(WoReg, 0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */ -#define REG_TWI1_IDR REG_ACCESS(WoReg, 0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */ -#define REG_TWI1_IMR REG_ACCESS(RoReg, 0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */ -#define REG_TWI1_RHR REG_ACCESS(RoReg, 0x4001C030U) /**< \brief (TWI1) Receive Holding Register */ -#define REG_TWI1_THR REG_ACCESS(WoReg, 0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */ -#define REG_TWI1_RPR REG_ACCESS(RwReg, 0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */ -#define REG_TWI1_RCR REG_ACCESS(RwReg, 0x4001C104U) /**< \brief (TWI1) Receive Counter Register */ -#define REG_TWI1_TPR REG_ACCESS(RwReg, 0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */ -#define REG_TWI1_TCR REG_ACCESS(RwReg, 0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */ -#define REG_TWI1_RNPR REG_ACCESS(RwReg, 0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */ -#define REG_TWI1_RNCR REG_ACCESS(RwReg, 0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */ -#define REG_TWI1_TNPR REG_ACCESS(RwReg, 0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */ -#define REG_TWI1_TNCR REG_ACCESS(RwReg, 0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */ -#define REG_TWI1_PTCR REG_ACCESS(WoReg, 0x4001C120U) /**< \brief (TWI1) Transfer Control Register */ -#define REG_TWI1_PTSR REG_ACCESS(RoReg, 0x4001C124U) /**< \brief (TWI1) Transfer Status Register */ -/* ========== Register definition for PWM peripheral ========== */ -#define REG_PWM_CLK REG_ACCESS(RwReg, 0x40020000U) /**< \brief (PWM) PWM Clock Register */ -#define REG_PWM_ENA REG_ACCESS(WoReg, 0x40020004U) /**< \brief (PWM) PWM Enable Register */ -#define REG_PWM_DIS REG_ACCESS(WoReg, 0x40020008U) /**< \brief (PWM) PWM Disable Register */ -#define REG_PWM_SR REG_ACCESS(RoReg, 0x4002000CU) /**< \brief (PWM) PWM Status Register */ -#define REG_PWM_IER1 REG_ACCESS(WoReg, 0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ -#define REG_PWM_IDR1 REG_ACCESS(WoReg, 0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ -#define REG_PWM_IMR1 REG_ACCESS(RoReg, 0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ -#define REG_PWM_ISR1 REG_ACCESS(RoReg, 0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ -#define REG_PWM_SCM REG_ACCESS(RwReg, 0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ -#define REG_PWM_SCUC REG_ACCESS(RwReg, 0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ -#define REG_PWM_SCUP REG_ACCESS(RwReg, 0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ -#define REG_PWM_SCUPUPD REG_ACCESS(WoReg, 0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ -#define REG_PWM_IER2 REG_ACCESS(WoReg, 0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ -#define REG_PWM_IDR2 REG_ACCESS(WoReg, 0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ -#define REG_PWM_IMR2 REG_ACCESS(RoReg, 0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ -#define REG_PWM_ISR2 REG_ACCESS(RoReg, 0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ -#define REG_PWM_OOV REG_ACCESS(RwReg, 0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */ -#define REG_PWM_OS REG_ACCESS(RwReg, 0x40020048U) /**< \brief (PWM) PWM Output Selection Register */ -#define REG_PWM_OSS REG_ACCESS(WoReg, 0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */ -#define REG_PWM_OSC REG_ACCESS(WoReg, 0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */ -#define REG_PWM_OSSUPD REG_ACCESS(WoReg, 0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ -#define REG_PWM_OSCUPD REG_ACCESS(WoReg, 0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ -#define REG_PWM_FMR REG_ACCESS(RwReg, 0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */ -#define REG_PWM_FSR REG_ACCESS(RoReg, 0x40020060U) /**< \brief (PWM) PWM Fault Status Register */ -#define REG_PWM_FCR REG_ACCESS(WoReg, 0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */ -#define REG_PWM_FPV REG_ACCESS(RwReg, 0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */ -#define REG_PWM_FPE REG_ACCESS(RwReg, 0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */ -#define REG_PWM_ELxMR REG_ACCESS(RwReg, 0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ -#define REG_PWM_SMMR REG_ACCESS(RwReg, 0x400200B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */ -#define REG_PWM_WPCR REG_ACCESS(WoReg, 0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */ -#define REG_PWM_WPSR REG_ACCESS(RoReg, 0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */ -#define REG_PWM_RPR REG_ACCESS(RwReg, 0x40020100U) /**< \brief (PWM) Receive Pointer Register */ -#define REG_PWM_RCR REG_ACCESS(RwReg, 0x40020104U) /**< \brief (PWM) Receive Counter Register */ -#define REG_PWM_TPR REG_ACCESS(RwReg, 0x40020108U) /**< \brief (PWM) Transmit Pointer Register */ -#define REG_PWM_TCR REG_ACCESS(RwReg, 0x4002010CU) /**< \brief (PWM) Transmit Counter Register */ -#define REG_PWM_RNPR REG_ACCESS(RwReg, 0x40020110U) /**< \brief (PWM) Receive Next Pointer Register */ -#define REG_PWM_RNCR REG_ACCESS(RwReg, 0x40020114U) /**< \brief (PWM) Receive Next Counter Register */ -#define REG_PWM_TNPR REG_ACCESS(RwReg, 0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */ -#define REG_PWM_TNCR REG_ACCESS(RwReg, 0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */ -#define REG_PWM_PTCR REG_ACCESS(WoReg, 0x40020120U) /**< \brief (PWM) Transfer Control Register */ -#define REG_PWM_PTSR REG_ACCESS(RoReg, 0x40020124U) /**< \brief (PWM) Transfer Status Register */ -#define REG_PWM_CMP0V REG_ACCESS(RwReg, 0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ -#define REG_PWM_CMP0VUPD REG_ACCESS(WoReg, 0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ -#define REG_PWM_CMP0M REG_ACCESS(RwReg, 0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ -#define REG_PWM_CMP0MUPD REG_ACCESS(WoReg, 0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ -#define REG_PWM_CMP1V REG_ACCESS(RwReg, 0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ -#define REG_PWM_CMP1VUPD REG_ACCESS(WoReg, 0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ -#define REG_PWM_CMP1M REG_ACCESS(RwReg, 0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ -#define REG_PWM_CMP1MUPD REG_ACCESS(WoReg, 0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ -#define REG_PWM_CMP2V REG_ACCESS(RwReg, 0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ -#define REG_PWM_CMP2VUPD REG_ACCESS(WoReg, 0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ -#define REG_PWM_CMP2M REG_ACCESS(RwReg, 0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ -#define REG_PWM_CMP2MUPD REG_ACCESS(WoReg, 0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ -#define REG_PWM_CMP3V REG_ACCESS(RwReg, 0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ -#define REG_PWM_CMP3VUPD REG_ACCESS(WoReg, 0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ -#define REG_PWM_CMP3M REG_ACCESS(RwReg, 0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ -#define REG_PWM_CMP3MUPD REG_ACCESS(WoReg, 0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ -#define REG_PWM_CMP4V REG_ACCESS(RwReg, 0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ -#define REG_PWM_CMP4VUPD REG_ACCESS(WoReg, 0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ -#define REG_PWM_CMP4M REG_ACCESS(RwReg, 0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ -#define REG_PWM_CMP4MUPD REG_ACCESS(WoReg, 0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ -#define REG_PWM_CMP5V REG_ACCESS(RwReg, 0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ -#define REG_PWM_CMP5VUPD REG_ACCESS(WoReg, 0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ -#define REG_PWM_CMP5M REG_ACCESS(RwReg, 0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ -#define REG_PWM_CMP5MUPD REG_ACCESS(WoReg, 0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ -#define REG_PWM_CMP6V REG_ACCESS(RwReg, 0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ -#define REG_PWM_CMP6VUPD REG_ACCESS(WoReg, 0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ -#define REG_PWM_CMP6M REG_ACCESS(RwReg, 0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ -#define REG_PWM_CMP6MUPD REG_ACCESS(WoReg, 0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ -#define REG_PWM_CMP7V REG_ACCESS(RwReg, 0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ -#define REG_PWM_CMP7VUPD REG_ACCESS(WoReg, 0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ -#define REG_PWM_CMP7M REG_ACCESS(RwReg, 0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ -#define REG_PWM_CMP7MUPD REG_ACCESS(WoReg, 0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ -#define REG_PWM_CMR0 REG_ACCESS(RwReg, 0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ -#define REG_PWM_CDTY0 REG_ACCESS(RwReg, 0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ -#define REG_PWM_CDTYUPD0 REG_ACCESS(WoReg, 0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ -#define REG_PWM_CPRD0 REG_ACCESS(RwReg, 0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ -#define REG_PWM_CPRDUPD0 REG_ACCESS(WoReg, 0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ -#define REG_PWM_CCNT0 REG_ACCESS(RoReg, 0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ -#define REG_PWM_DT0 REG_ACCESS(RwReg, 0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ -#define REG_PWM_DTUPD0 REG_ACCESS(WoReg, 0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ -#define REG_PWM_CMR1 REG_ACCESS(RwReg, 0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ -#define REG_PWM_CDTY1 REG_ACCESS(RwReg, 0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ -#define REG_PWM_CDTYUPD1 REG_ACCESS(WoReg, 0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ -#define REG_PWM_CPRD1 REG_ACCESS(RwReg, 0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ -#define REG_PWM_CPRDUPD1 REG_ACCESS(WoReg, 0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ -#define REG_PWM_CCNT1 REG_ACCESS(RoReg, 0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ -#define REG_PWM_DT1 REG_ACCESS(RwReg, 0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ -#define REG_PWM_DTUPD1 REG_ACCESS(WoReg, 0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ -#define REG_PWM_CMR2 REG_ACCESS(RwReg, 0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ -#define REG_PWM_CDTY2 REG_ACCESS(RwReg, 0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ -#define REG_PWM_CDTYUPD2 REG_ACCESS(WoReg, 0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ -#define REG_PWM_CPRD2 REG_ACCESS(RwReg, 0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ -#define REG_PWM_CPRDUPD2 REG_ACCESS(WoReg, 0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ -#define REG_PWM_CCNT2 REG_ACCESS(RoReg, 0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ -#define REG_PWM_DT2 REG_ACCESS(RwReg, 0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ -#define REG_PWM_DTUPD2 REG_ACCESS(WoReg, 0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ -#define REG_PWM_CMR3 REG_ACCESS(RwReg, 0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ -#define REG_PWM_CDTY3 REG_ACCESS(RwReg, 0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ -#define REG_PWM_CDTYUPD3 REG_ACCESS(WoReg, 0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ -#define REG_PWM_CPRD3 REG_ACCESS(RwReg, 0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ -#define REG_PWM_CPRDUPD3 REG_ACCESS(WoReg, 0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ -#define REG_PWM_CCNT3 REG_ACCESS(RoReg, 0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ -#define REG_PWM_DT3 REG_ACCESS(RwReg, 0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ -#define REG_PWM_DTUPD3 REG_ACCESS(WoReg, 0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ -/* ========== Register definition for USART0 peripheral ========== */ -#define REG_USART0_CR REG_ACCESS(WoReg, 0x40024000U) /**< \brief (USART0) Control Register */ -#define REG_USART0_MR REG_ACCESS(RwReg, 0x40024004U) /**< \brief (USART0) Mode Register */ -#define REG_USART0_IER REG_ACCESS(WoReg, 0x40024008U) /**< \brief (USART0) Interrupt Enable Register */ -#define REG_USART0_IDR REG_ACCESS(WoReg, 0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */ -#define REG_USART0_IMR REG_ACCESS(RoReg, 0x40024010U) /**< \brief (USART0) Interrupt Mask Register */ -#define REG_USART0_CSR REG_ACCESS(RoReg, 0x40024014U) /**< \brief (USART0) Channel Status Register */ -#define REG_USART0_RHR REG_ACCESS(RoReg, 0x40024018U) /**< \brief (USART0) Receiver Holding Register */ -#define REG_USART0_THR REG_ACCESS(WoReg, 0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */ -#define REG_USART0_BRGR REG_ACCESS(RwReg, 0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */ -#define REG_USART0_RTOR REG_ACCESS(RwReg, 0x40024024U) /**< \brief (USART0) Receiver Time-out Register */ -#define REG_USART0_TTGR REG_ACCESS(RwReg, 0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */ -#define REG_USART0_FIDI REG_ACCESS(RwReg, 0x40024040U) /**< \brief (USART0) FI DI Ratio Register */ -#define REG_USART0_NER REG_ACCESS(RoReg, 0x40024044U) /**< \brief (USART0) Number of Errors Register */ -#define REG_USART0_IF REG_ACCESS(RwReg, 0x4002404CU) /**< \brief (USART0) IrDA Filter Register */ -#define REG_USART0_MAN REG_ACCESS(RwReg, 0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */ -#define REG_USART0_WPMR REG_ACCESS(RwReg, 0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */ -#define REG_USART0_WPSR REG_ACCESS(RoReg, 0x400240E8U) /**< \brief (USART0) Write Protect Status Register */ -#define REG_USART0_VERSION REG_ACCESS(RoReg, 0x400240FCU) /**< \brief (USART0) Version Register */ -#define REG_USART0_RPR REG_ACCESS(RwReg, 0x40024100U) /**< \brief (USART0) Receive Pointer Register */ -#define REG_USART0_RCR REG_ACCESS(RwReg, 0x40024104U) /**< \brief (USART0) Receive Counter Register */ -#define REG_USART0_TPR REG_ACCESS(RwReg, 0x40024108U) /**< \brief (USART0) Transmit Pointer Register */ -#define REG_USART0_TCR REG_ACCESS(RwReg, 0x4002410CU) /**< \brief (USART0) Transmit Counter Register */ -#define REG_USART0_RNPR REG_ACCESS(RwReg, 0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */ -#define REG_USART0_RNCR REG_ACCESS(RwReg, 0x40024114U) /**< \brief (USART0) Receive Next Counter Register */ -#define REG_USART0_TNPR REG_ACCESS(RwReg, 0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */ -#define REG_USART0_TNCR REG_ACCESS(RwReg, 0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */ -#define REG_USART0_PTCR REG_ACCESS(WoReg, 0x40024120U) /**< \brief (USART0) Transfer Control Register */ -#define REG_USART0_PTSR REG_ACCESS(RoReg, 0x40024124U) /**< \brief (USART0) Transfer Status Register */ -/* ========== Register definition for USART1 peripheral ========== */ -#define REG_USART1_CR REG_ACCESS(WoReg, 0x40028000U) /**< \brief (USART1) Control Register */ -#define REG_USART1_MR REG_ACCESS(RwReg, 0x40028004U) /**< \brief (USART1) Mode Register */ -#define REG_USART1_IER REG_ACCESS(WoReg, 0x40028008U) /**< \brief (USART1) Interrupt Enable Register */ -#define REG_USART1_IDR REG_ACCESS(WoReg, 0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */ -#define REG_USART1_IMR REG_ACCESS(RoReg, 0x40028010U) /**< \brief (USART1) Interrupt Mask Register */ -#define REG_USART1_CSR REG_ACCESS(RoReg, 0x40028014U) /**< \brief (USART1) Channel Status Register */ -#define REG_USART1_RHR REG_ACCESS(RoReg, 0x40028018U) /**< \brief (USART1) Receiver Holding Register */ -#define REG_USART1_THR REG_ACCESS(WoReg, 0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */ -#define REG_USART1_BRGR REG_ACCESS(RwReg, 0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */ -#define REG_USART1_RTOR REG_ACCESS(RwReg, 0x40028024U) /**< \brief (USART1) Receiver Time-out Register */ -#define REG_USART1_TTGR REG_ACCESS(RwReg, 0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */ -#define REG_USART1_FIDI REG_ACCESS(RwReg, 0x40028040U) /**< \brief (USART1) FI DI Ratio Register */ -#define REG_USART1_NER REG_ACCESS(RoReg, 0x40028044U) /**< \brief (USART1) Number of Errors Register */ -#define REG_USART1_IF REG_ACCESS(RwReg, 0x4002804CU) /**< \brief (USART1) IrDA Filter Register */ -#define REG_USART1_MAN REG_ACCESS(RwReg, 0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ -#define REG_USART1_WPMR REG_ACCESS(RwReg, 0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */ -#define REG_USART1_WPSR REG_ACCESS(RoReg, 0x400280E8U) /**< \brief (USART1) Write Protect Status Register */ -#define REG_USART1_VERSION REG_ACCESS(RoReg, 0x400280FCU) /**< \brief (USART1) Version Register */ -#define REG_USART1_RPR REG_ACCESS(RwReg, 0x40028100U) /**< \brief (USART1) Receive Pointer Register */ -#define REG_USART1_RCR REG_ACCESS(RwReg, 0x40028104U) /**< \brief (USART1) Receive Counter Register */ -#define REG_USART1_TPR REG_ACCESS(RwReg, 0x40028108U) /**< \brief (USART1) Transmit Pointer Register */ -#define REG_USART1_TCR REG_ACCESS(RwReg, 0x4002810CU) /**< \brief (USART1) Transmit Counter Register */ -#define REG_USART1_RNPR REG_ACCESS(RwReg, 0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */ -#define REG_USART1_RNCR REG_ACCESS(RwReg, 0x40028114U) /**< \brief (USART1) Receive Next Counter Register */ -#define REG_USART1_TNPR REG_ACCESS(RwReg, 0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */ -#define REG_USART1_TNCR REG_ACCESS(RwReg, 0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */ -#define REG_USART1_PTCR REG_ACCESS(WoReg, 0x40028120U) /**< \brief (USART1) Transfer Control Register */ -#define REG_USART1_PTSR REG_ACCESS(RoReg, 0x40028124U) /**< \brief (USART1) Transfer Status Register */ -/* ========== Register definition for UDP peripheral ========== */ -#define REG_UDP_FRM_NUM REG_ACCESS(RoReg, 0x40034000U) /**< \brief (UDP) Frame Number Register */ -#define REG_UDP_GLB_STAT REG_ACCESS(RwReg, 0x40034004U) /**< \brief (UDP) Global State Register */ -#define REG_UDP_FADDR REG_ACCESS(RwReg, 0x40034008U) /**< \brief (UDP) Function Address Register */ -#define REG_UDP_IER REG_ACCESS(WoReg, 0x40034010U) /**< \brief (UDP) Interrupt Enable Register */ -#define REG_UDP_IDR REG_ACCESS(WoReg, 0x40034014U) /**< \brief (UDP) Interrupt Disable Register */ -#define REG_UDP_IMR REG_ACCESS(RoReg, 0x40034018U) /**< \brief (UDP) Interrupt Mask Register */ -#define REG_UDP_ISR REG_ACCESS(RoReg, 0x4003401CU) /**< \brief (UDP) Interrupt Status Register */ -#define REG_UDP_ICR REG_ACCESS(WoReg, 0x40034020U) /**< \brief (UDP) Interrupt Clear Register */ -#define REG_UDP_RST_EP REG_ACCESS(RwReg, 0x40034028U) /**< \brief (UDP) Reset Endpoint Register */ -#define REG_UDP_CSR REG_ACCESS(RwReg, 0x4003402CU) /**< \brief (UDP) Endpoint Control and Status Register (ept_num = 0) */ -#define REG_UDP_FDR REG_ACCESS(RwReg, 0x4003404CU) /**< \brief (UDP) Endpoint FIFO Data Register (ept_num = 0) */ -#define REG_UDP_TXVC REG_ACCESS(RwReg, 0x40034074U) /**< \brief (UDP) Transceiver Control Register */ -/* ========== Register definition for ADC peripheral ========== */ -#define REG_ADC_CR REG_ACCESS(WoReg, 0x40038000U) /**< \brief (ADC) Control Register */ -#define REG_ADC_MR REG_ACCESS(RwReg, 0x40038004U) /**< \brief (ADC) Mode Register */ -#define REG_ADC_SEQ1R REG_ACCESS(RwReg, 0x40038008U) /**< \brief (ADC) Channel Sequence 1Register */ -#define REG_ADC_SEQ2R REG_ACCESS(RwReg, 0x4003800CU) /**< \brief (ADC) Channel Sequence 2 Register */ -#define REG_ADC_CHER REG_ACCESS(WoReg, 0x40038010U) /**< \brief (ADC) Channel Enable Register */ -#define REG_ADC_CHDR REG_ACCESS(WoReg, 0x40038014U) /**< \brief (ADC) Channel Disable Register */ -#define REG_ADC_CHSR REG_ACCESS(RoReg, 0x40038018U) /**< \brief (ADC) Channel Status Register */ -#define REG_ADC_LCDR REG_ACCESS(RoReg, 0x40038020U) /**< \brief (ADC) Last Converted Data Register */ -#define REG_ADC_IER REG_ACCESS(WoReg, 0x40038024U) /**< \brief (ADC) Interrupt Enable Register */ -#define REG_ADC_IDR REG_ACCESS(WoReg, 0x40038028U) /**< \brief (ADC) Interrupt Disable Register */ -#define REG_ADC_IMR REG_ACCESS(RoReg, 0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */ -#define REG_ADC_ISR REG_ACCESS(RoReg, 0x40038030U) /**< \brief (ADC) Interrupt Status Register */ -#define REG_ADC_OVER REG_ACCESS(RoReg, 0x4003803CU) /**< \brief (ADC) Overrun Status Register */ -#define REG_ADC_EMR REG_ACCESS(RwReg, 0x40038040U) /**< \brief (ADC) Extended Mode Register */ -#define REG_ADC_CWR REG_ACCESS(RwReg, 0x40038044U) /**< \brief (ADC) Compare Window Register */ -#define REG_ADC_CGR REG_ACCESS(RwReg, 0x40038048U) /**< \brief (ADC) Channel Gain Register */ -#define REG_ADC_COR REG_ACCESS(RwReg, 0x4003804CU) /**< \brief (ADC) Channel Offset Register */ -#define REG_ADC_CDR0 REG_ACCESS(RoReg, 0x40038050U) /**< \brief (ADC) Channel Data Register 0 */ -#define REG_ADC_CDR1 REG_ACCESS(RoReg, 0x40038054U) /**< \brief (ADC) Channel Data Register 1 */ -#define REG_ADC_CDR2 REG_ACCESS(RoReg, 0x40038058U) /**< \brief (ADC) Channel Data Register 2 */ -#define REG_ADC_CDR3 REG_ACCESS(RoReg, 0x4003805CU) /**< \brief (ADC) Channel Data Register 3 */ -#define REG_ADC_CDR4 REG_ACCESS(RoReg, 0x40038060U) /**< \brief (ADC) Channel Data Register 4 */ -#define REG_ADC_CDR5 REG_ACCESS(RoReg, 0x40038064U) /**< \brief (ADC) Channel Data Register 5 */ -#define REG_ADC_CDR6 REG_ACCESS(RoReg, 0x40038068U) /**< \brief (ADC) Channel Data Register 6 */ -#define REG_ADC_CDR15 REG_ACCESS(RoReg, 0x4003806CU) /**< \brief (ADC) Channel Data Register 15 */ -#define REG_ADC_ACR REG_ACCESS(RwReg, 0x40038094U) /**< \brief (ADC) Analog Control Register */ -#define REG_ADC_WPMR REG_ACCESS(RwReg, 0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */ -#define REG_ADC_WPSR REG_ACCESS(RoReg, 0x400380E8U) /**< \brief (ADC) Write Protect Status Register */ -#define REG_ADC_RPR REG_ACCESS(RwReg, 0x40038100U) /**< \brief (ADC) Receive Pointer Register */ -#define REG_ADC_RCR REG_ACCESS(RwReg, 0x40038104U) /**< \brief (ADC) Receive Counter Register */ -#define REG_ADC_TPR REG_ACCESS(RwReg, 0x40038108U) /**< \brief (ADC) Transmit Pointer Register */ -#define REG_ADC_TCR REG_ACCESS(RwReg, 0x4003810CU) /**< \brief (ADC) Transmit Counter Register */ -#define REG_ADC_RNPR REG_ACCESS(RwReg, 0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */ -#define REG_ADC_RNCR REG_ACCESS(RwReg, 0x40038114U) /**< \brief (ADC) Receive Next Counter Register */ -#define REG_ADC_TNPR REG_ACCESS(RwReg, 0x40038118U) /**< \brief (ADC) Transmit Next Pointer Register */ -#define REG_ADC_TNCR REG_ACCESS(RwReg, 0x4003811CU) /**< \brief (ADC) Transmit Next Counter Register */ -#define REG_ADC_PTCR REG_ACCESS(WoReg, 0x40038120U) /**< \brief (ADC) Transfer Control Register */ -#define REG_ADC_PTSR REG_ACCESS(RoReg, 0x40038124U) /**< \brief (ADC) Transfer Status Register */ -/* ========== Register definition for DACC peripheral ========== */ -#define REG_DACC_CR REG_ACCESS(WoReg, 0x4003C000U) /**< \brief (DACC) Control Register */ -#define REG_DACC_MR REG_ACCESS(RwReg, 0x4003C004U) /**< \brief (DACC) Mode Register */ -#define REG_DACC_CHER REG_ACCESS(WoReg, 0x4003C010U) /**< \brief (DACC) Channel Enable Register */ -#define REG_DACC_CHDR REG_ACCESS(WoReg, 0x4003C014U) /**< \brief (DACC) Channel Disable Register */ -#define REG_DACC_CHSR REG_ACCESS(RoReg, 0x4003C018U) /**< \brief (DACC) Channel Status Register */ -#define REG_DACC_CDR REG_ACCESS(WoReg, 0x4003C020U) /**< \brief (DACC) Conversion Data Register */ -#define REG_DACC_IER REG_ACCESS(WoReg, 0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */ -#define REG_DACC_IDR REG_ACCESS(WoReg, 0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */ -#define REG_DACC_IMR REG_ACCESS(RoReg, 0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */ -#define REG_DACC_ISR REG_ACCESS(RoReg, 0x4003C030U) /**< \brief (DACC) Interrupt Status Register */ -#define REG_DACC_ACR REG_ACCESS(RwReg, 0x4003C094U) /**< \brief (DACC) Analog Current Register */ -#define REG_DACC_WPMR REG_ACCESS(RwReg, 0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */ -#define REG_DACC_WPSR REG_ACCESS(RoReg, 0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */ -#define REG_DACC_RPR REG_ACCESS(RwReg, 0x4003C100U) /**< \brief (DACC) Receive Pointer Register */ -#define REG_DACC_RCR REG_ACCESS(RwReg, 0x4003C104U) /**< \brief (DACC) Receive Counter Register */ -#define REG_DACC_TPR REG_ACCESS(RwReg, 0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */ -#define REG_DACC_TCR REG_ACCESS(RwReg, 0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */ -#define REG_DACC_RNPR REG_ACCESS(RwReg, 0x4003C110U) /**< \brief (DACC) Receive Next Pointer Register */ -#define REG_DACC_RNCR REG_ACCESS(RwReg, 0x4003C114U) /**< \brief (DACC) Receive Next Counter Register */ -#define REG_DACC_TNPR REG_ACCESS(RwReg, 0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */ -#define REG_DACC_TNCR REG_ACCESS(RwReg, 0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */ -#define REG_DACC_PTCR REG_ACCESS(WoReg, 0x4003C120U) /**< \brief (DACC) Transfer Control Register */ -#define REG_DACC_PTSR REG_ACCESS(RoReg, 0x4003C124U) /**< \brief (DACC) Transfer Status Register */ -/* ========== Register definition for ACC peripheral ========== */ -#define REG_ACC_CR REG_ACCESS(WoReg, 0x40040000U) /**< \brief (ACC) Control Register */ -#define REG_ACC_MR REG_ACCESS(RwReg, 0x40040004U) /**< \brief (ACC) Mode Register */ -#define REG_ACC_IER REG_ACCESS(WoReg, 0x40040024U) /**< \brief (ACC) Interrupt Enable Register */ -#define REG_ACC_IDR REG_ACCESS(WoReg, 0x40040028U) /**< \brief (ACC) Interrupt Disable Register */ -#define REG_ACC_IMR REG_ACCESS(RoReg, 0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */ -#define REG_ACC_ISR REG_ACCESS(RoReg, 0x40040030U) /**< \brief (ACC) Interrupt Status Register */ -#define REG_ACC_ACR REG_ACCESS(RwReg, 0x40040094U) /**< \brief (ACC) Analog Control Register */ -#define REG_ACC_WPMR REG_ACCESS(RwReg, 0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */ -#define REG_ACC_WPSR REG_ACCESS(RoReg, 0x400400E8U) /**< \brief (ACC) Write Protect Status Register */ -/* ========== Register definition for CRCCU peripheral ========== */ -#define REG_CRCCU_DSCR REG_ACCESS(RwReg, 0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */ -#define REG_CRCCU_DMA_EN REG_ACCESS(WoReg, 0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */ -#define REG_CRCCU_DMA_DIS REG_ACCESS(WoReg, 0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */ -#define REG_CRCCU_DMA_SR REG_ACCESS(RoReg, 0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */ -#define REG_CRCCU_DMA_IER REG_ACCESS(WoReg, 0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */ -#define REG_CRCCU_DMA_IDR REG_ACCESS(WoReg, 0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */ -#define REG_CRCCU_DMA_IMR REG_ACCESS(RoReg, 0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */ -#define REG_CRCCU_DMA_ISR REG_ACCESS(RoReg, 0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */ -#define REG_CRCCU_CR REG_ACCESS(WoReg, 0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */ -#define REG_CRCCU_MR REG_ACCESS(RwReg, 0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */ -#define REG_CRCCU_SR REG_ACCESS(RoReg, 0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */ -#define REG_CRCCU_IER REG_ACCESS(WoReg, 0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */ -#define REG_CRCCU_IDR REG_ACCESS(WoReg, 0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */ -#define REG_CRCCU_IMR REG_ACCESS(RoReg, 0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */ -#define REG_CRCCU_ISR REG_ACCESS(RoReg, 0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */ -/* ========== Register definition for SMC peripheral ========== */ -#define REG_SMC_SETUP0 REG_ACCESS(RwReg, 0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ -#define REG_SMC_PULSE0 REG_ACCESS(RwReg, 0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ -#define REG_SMC_CYCLE0 REG_ACCESS(RwReg, 0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ -#define REG_SMC_MODE0 REG_ACCESS(RwReg, 0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ -#define REG_SMC_SETUP1 REG_ACCESS(RwReg, 0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ -#define REG_SMC_PULSE1 REG_ACCESS(RwReg, 0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ -#define REG_SMC_CYCLE1 REG_ACCESS(RwReg, 0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ -#define REG_SMC_MODE1 REG_ACCESS(RwReg, 0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ -#define REG_SMC_SETUP2 REG_ACCESS(RwReg, 0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ -#define REG_SMC_PULSE2 REG_ACCESS(RwReg, 0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ -#define REG_SMC_CYCLE2 REG_ACCESS(RwReg, 0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ -#define REG_SMC_MODE2 REG_ACCESS(RwReg, 0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ -#define REG_SMC_SETUP3 REG_ACCESS(RwReg, 0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ -#define REG_SMC_PULSE3 REG_ACCESS(RwReg, 0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ -#define REG_SMC_CYCLE3 REG_ACCESS(RwReg, 0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ -#define REG_SMC_MODE3 REG_ACCESS(RwReg, 0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ -#define REG_SMC_SETUP4 REG_ACCESS(RwReg, 0x400E0040U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */ -#define REG_SMC_PULSE4 REG_ACCESS(RwReg, 0x400E0044U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */ -#define REG_SMC_CYCLE4 REG_ACCESS(RwReg, 0x400E0048U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */ -#define REG_SMC_MODE4 REG_ACCESS(RwReg, 0x400E004CU) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */ -#define REG_SMC_OCMS REG_ACCESS(RwReg, 0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */ -#define REG_SMC_KEY1 REG_ACCESS(WoReg, 0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */ -#define REG_SMC_KEY2 REG_ACCESS(WoReg, 0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */ -#define REG_SMC_WPMR REG_ACCESS(RwReg, 0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */ -#define REG_SMC_WPSR REG_ACCESS(RoReg, 0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */ -/* ========== Register definition for MATRIX peripheral ========== */ -#define REG_MATRIX_MCFG REG_ACCESS(RwReg, 0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */ -#define REG_MATRIX_SCFG REG_ACCESS(RwReg, 0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */ -#define REG_MATRIX_PRAS0 REG_ACCESS(RwReg, 0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ -#define REG_MATRIX_PRAS1 REG_ACCESS(RwReg, 0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ -#define REG_MATRIX_PRAS2 REG_ACCESS(RwReg, 0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ -#define REG_MATRIX_PRAS3 REG_ACCESS(RwReg, 0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ -#define REG_MATRIX_PRAS4 REG_ACCESS(RwReg, 0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ -#define REG_MATRIX_SYSIO REG_ACCESS(RwReg, 0x400E0314U) /**< \brief (MATRIX) System IO Configuration register */ -#define REG_MATRIX_SMCNFCS REG_ACCESS(RwReg, 0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */ -#define REG_MATRIX_WPMR REG_ACCESS(RwReg, 0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */ -#define REG_MATRIX_WPSR REG_ACCESS(RoReg, 0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */ -/* ========== Register definition for PMC peripheral ========== */ -#define REG_PMC_SCER REG_ACCESS(WoReg, 0x400E0400U) /**< \brief (PMC) System Clock Enable Register */ -#define REG_PMC_SCDR REG_ACCESS(WoReg, 0x400E0404U) /**< \brief (PMC) System Clock Disable Register */ -#define REG_PMC_SCSR REG_ACCESS(RoReg, 0x400E0408U) /**< \brief (PMC) System Clock Status Register */ -#define REG_PMC_PCER0 REG_ACCESS(WoReg, 0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ -#define REG_PMC_PCDR0 REG_ACCESS(WoReg, 0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ -#define REG_PMC_PCSR0 REG_ACCESS(RoReg, 0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ -#define REG_PMC_MOR REG_ACCESS(RwReg, 0x400E0420U) /**< \brief (PMC) Main Oscillator Register */ -#define REG_PMC_MCFR REG_ACCESS(RoReg, 0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */ -#define REG_PMC_PLLAR REG_ACCESS(RwReg, 0x400E0428U) /**< \brief (PMC) PLLA Register */ -#define REG_PMC_PLLBR REG_ACCESS(RwReg, 0x400E042CU) /**< \brief (PMC) PLLB Register */ -#define REG_PMC_MCKR REG_ACCESS(RwReg, 0x400E0430U) /**< \brief (PMC) Master Clock Register */ -#define REG_PMC_USB REG_ACCESS(RwReg, 0x400E0438U) /**< \brief (PMC) USB Clock Register */ -#define REG_PMC_PCK REG_ACCESS(RwReg, 0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */ -#define REG_PMC_IER REG_ACCESS(WoReg, 0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */ -#define REG_PMC_IDR REG_ACCESS(WoReg, 0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */ -#define REG_PMC_SR REG_ACCESS(RoReg, 0x400E0468U) /**< \brief (PMC) Status Register */ -#define REG_PMC_IMR REG_ACCESS(RoReg, 0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */ -#define REG_PMC_FSMR REG_ACCESS(RwReg, 0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */ -#define REG_PMC_FSPR REG_ACCESS(RwReg, 0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */ -#define REG_PMC_FOCR REG_ACCESS(WoReg, 0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */ -#define REG_PMC_WPMR REG_ACCESS(RwReg, 0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */ -#define REG_PMC_WPSR REG_ACCESS(RoReg, 0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */ -#define REG_PMC_PCER1 REG_ACCESS(WoReg, 0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ -#define REG_PMC_PCDR1 REG_ACCESS(WoReg, 0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ -#define REG_PMC_PCSR1 REG_ACCESS(RoReg, 0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ -#define REG_PMC_OCR REG_ACCESS(RwReg, 0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */ -/* ========== Register definition for UART0 peripheral ========== */ -#define REG_UART0_CR REG_ACCESS(WoReg, 0x400E0600U) /**< \brief (UART0) Control Register */ -#define REG_UART0_MR REG_ACCESS(RwReg, 0x400E0604U) /**< \brief (UART0) Mode Register */ -#define REG_UART0_IER REG_ACCESS(WoReg, 0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */ -#define REG_UART0_IDR REG_ACCESS(WoReg, 0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */ -#define REG_UART0_IMR REG_ACCESS(RoReg, 0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */ -#define REG_UART0_SR REG_ACCESS(RoReg, 0x400E0614U) /**< \brief (UART0) Status Register */ -#define REG_UART0_RHR REG_ACCESS(RoReg, 0x400E0618U) /**< \brief (UART0) Receive Holding Register */ -#define REG_UART0_THR REG_ACCESS(WoReg, 0x400E061CU) /**< \brief (UART0) Transmit Holding Register */ -#define REG_UART0_BRGR REG_ACCESS(RwReg, 0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */ -#define REG_UART0_RPR REG_ACCESS(RwReg, 0x400E0700U) /**< \brief (UART0) Receive Pointer Register */ -#define REG_UART0_RCR REG_ACCESS(RwReg, 0x400E0704U) /**< \brief (UART0) Receive Counter Register */ -#define REG_UART0_TPR REG_ACCESS(RwReg, 0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */ -#define REG_UART0_TCR REG_ACCESS(RwReg, 0x400E070CU) /**< \brief (UART0) Transmit Counter Register */ -#define REG_UART0_RNPR REG_ACCESS(RwReg, 0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */ -#define REG_UART0_RNCR REG_ACCESS(RwReg, 0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */ -#define REG_UART0_TNPR REG_ACCESS(RwReg, 0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */ -#define REG_UART0_TNCR REG_ACCESS(RwReg, 0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */ -#define REG_UART0_PTCR REG_ACCESS(WoReg, 0x400E0720U) /**< \brief (UART0) Transfer Control Register */ -#define REG_UART0_PTSR REG_ACCESS(RoReg, 0x400E0724U) /**< \brief (UART0) Transfer Status Register */ -/* ========== Register definition for CHIPID peripheral ========== */ -#define REG_CHIPID_CIDR REG_ACCESS(RoReg, 0x400E0740U) /**< \brief (CHIPID) Chip ID Register */ -#define REG_CHIPID_EXID REG_ACCESS(RoReg, 0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */ -/* ========== Register definition for UART1 peripheral ========== */ -#define REG_UART1_CR REG_ACCESS(WoReg, 0x400E0800U) /**< \brief (UART1) Control Register */ -#define REG_UART1_MR REG_ACCESS(RwReg, 0x400E0804U) /**< \brief (UART1) Mode Register */ -#define REG_UART1_IER REG_ACCESS(WoReg, 0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */ -#define REG_UART1_IDR REG_ACCESS(WoReg, 0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */ -#define REG_UART1_IMR REG_ACCESS(RoReg, 0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */ -#define REG_UART1_SR REG_ACCESS(RoReg, 0x400E0814U) /**< \brief (UART1) Status Register */ -#define REG_UART1_RHR REG_ACCESS(RoReg, 0x400E0818U) /**< \brief (UART1) Receive Holding Register */ -#define REG_UART1_THR REG_ACCESS(WoReg, 0x400E081CU) /**< \brief (UART1) Transmit Holding Register */ -#define REG_UART1_BRGR REG_ACCESS(RwReg, 0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */ -#define REG_UART1_RPR REG_ACCESS(RwReg, 0x400E0900U) /**< \brief (UART1) Receive Pointer Register */ -#define REG_UART1_RCR REG_ACCESS(RwReg, 0x400E0904U) /**< \brief (UART1) Receive Counter Register */ -#define REG_UART1_TPR REG_ACCESS(RwReg, 0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */ -#define REG_UART1_TCR REG_ACCESS(RwReg, 0x400E090CU) /**< \brief (UART1) Transmit Counter Register */ -#define REG_UART1_RNPR REG_ACCESS(RwReg, 0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */ -#define REG_UART1_RNCR REG_ACCESS(RwReg, 0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */ -#define REG_UART1_TNPR REG_ACCESS(RwReg, 0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */ -#define REG_UART1_TNCR REG_ACCESS(RwReg, 0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */ -#define REG_UART1_PTCR REG_ACCESS(WoReg, 0x400E0920U) /**< \brief (UART1) Transfer Control Register */ -#define REG_UART1_PTSR REG_ACCESS(RoReg, 0x400E0924U) /**< \brief (UART1) Transfer Status Register */ -/* ========== Register definition for EFC peripheral ========== */ -#define REG_EFC_FMR REG_ACCESS(RwReg, 0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */ -#define REG_EFC_FCR REG_ACCESS(WoReg, 0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */ -#define REG_EFC_FSR REG_ACCESS(RoReg, 0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */ -#define REG_EFC_FRR REG_ACCESS(RoReg, 0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */ -/* ========== Register definition for PIOA peripheral ========== */ -#define REG_PIOA_PER REG_ACCESS(WoReg, 0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ -#define REG_PIOA_PDR REG_ACCESS(WoReg, 0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ -#define REG_PIOA_PSR REG_ACCESS(RoReg, 0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ -#define REG_PIOA_OER REG_ACCESS(WoReg, 0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ -#define REG_PIOA_ODR REG_ACCESS(WoReg, 0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ -#define REG_PIOA_OSR REG_ACCESS(RoReg, 0x400E0E18U) /**< \brief (PIOA) Output Status Register */ -#define REG_PIOA_IFER REG_ACCESS(WoReg, 0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ -#define REG_PIOA_IFDR REG_ACCESS(WoReg, 0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ -#define REG_PIOA_IFSR REG_ACCESS(RoReg, 0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ -#define REG_PIOA_SODR REG_ACCESS(WoReg, 0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ -#define REG_PIOA_CODR REG_ACCESS(WoReg, 0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ -#define REG_PIOA_ODSR REG_ACCESS(RwReg, 0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ -#define REG_PIOA_PDSR REG_ACCESS(RoReg, 0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ -#define REG_PIOA_IER REG_ACCESS(WoReg, 0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ -#define REG_PIOA_IDR REG_ACCESS(WoReg, 0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ -#define REG_PIOA_IMR REG_ACCESS(RoReg, 0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ -#define REG_PIOA_ISR REG_ACCESS(RoReg, 0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ -#define REG_PIOA_MDER REG_ACCESS(WoReg, 0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ -#define REG_PIOA_MDDR REG_ACCESS(WoReg, 0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ -#define REG_PIOA_MDSR REG_ACCESS(RoReg, 0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ -#define REG_PIOA_PUDR REG_ACCESS(WoReg, 0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ -#define REG_PIOA_PUER REG_ACCESS(WoReg, 0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ -#define REG_PIOA_PUSR REG_ACCESS(RoReg, 0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ -#define REG_PIOA_ABCDSR REG_ACCESS(RwReg, 0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ -#define REG_PIOA_SCIFSR REG_ACCESS(WoReg, 0x400E0E80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */ -#define REG_PIOA_DIFSR REG_ACCESS(WoReg, 0x400E0E84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */ -#define REG_PIOA_IFDGSR REG_ACCESS(RoReg, 0x400E0E88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */ -#define REG_PIOA_SCDR REG_ACCESS(RwReg, 0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ -#define REG_PIOA_PPDDR REG_ACCESS(WoReg, 0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ -#define REG_PIOA_PPDER REG_ACCESS(WoReg, 0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ -#define REG_PIOA_PPDSR REG_ACCESS(RoReg, 0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ -#define REG_PIOA_OWER REG_ACCESS(WoReg, 0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ -#define REG_PIOA_OWDR REG_ACCESS(WoReg, 0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ -#define REG_PIOA_OWSR REG_ACCESS(RoReg, 0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ -#define REG_PIOA_AIMER REG_ACCESS(WoReg, 0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ -#define REG_PIOA_AIMDR REG_ACCESS(WoReg, 0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */ -#define REG_PIOA_AIMMR REG_ACCESS(RoReg, 0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ -#define REG_PIOA_ESR REG_ACCESS(WoReg, 0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ -#define REG_PIOA_LSR REG_ACCESS(WoReg, 0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ -#define REG_PIOA_ELSR REG_ACCESS(RoReg, 0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ -#define REG_PIOA_FELLSR REG_ACCESS(WoReg, 0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */ -#define REG_PIOA_REHLSR REG_ACCESS(WoReg, 0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */ -#define REG_PIOA_FRLHSR REG_ACCESS(RoReg, 0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ -#define REG_PIOA_LOCKSR REG_ACCESS(RoReg, 0x400E0EE0U) /**< \brief (PIOA) Lock Status */ -#define REG_PIOA_WPMR REG_ACCESS(RwReg, 0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */ -#define REG_PIOA_WPSR REG_ACCESS(RoReg, 0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */ -#define REG_PIOA_SCHMITT REG_ACCESS(RwReg, 0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ -#define REG_PIOA_PCMR REG_ACCESS(RwReg, 0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */ -#define REG_PIOA_PCIER REG_ACCESS(WoReg, 0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */ -#define REG_PIOA_PCIDR REG_ACCESS(WoReg, 0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */ -#define REG_PIOA_PCIMR REG_ACCESS(RoReg, 0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */ -#define REG_PIOA_PCISR REG_ACCESS(RoReg, 0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */ -#define REG_PIOA_PCRHR REG_ACCESS(RoReg, 0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */ -/* ========== Register definition for PIOB peripheral ========== */ -#define REG_PIOB_PER REG_ACCESS(WoReg, 0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ -#define REG_PIOB_PDR REG_ACCESS(WoReg, 0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ -#define REG_PIOB_PSR REG_ACCESS(RoReg, 0x400E1008U) /**< \brief (PIOB) PIO Status Register */ -#define REG_PIOB_OER REG_ACCESS(WoReg, 0x400E1010U) /**< \brief (PIOB) Output Enable Register */ -#define REG_PIOB_ODR REG_ACCESS(WoReg, 0x400E1014U) /**< \brief (PIOB) Output Disable Register */ -#define REG_PIOB_OSR REG_ACCESS(RoReg, 0x400E1018U) /**< \brief (PIOB) Output Status Register */ -#define REG_PIOB_IFER REG_ACCESS(WoReg, 0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ -#define REG_PIOB_IFDR REG_ACCESS(WoReg, 0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ -#define REG_PIOB_IFSR REG_ACCESS(RoReg, 0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ -#define REG_PIOB_SODR REG_ACCESS(WoReg, 0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ -#define REG_PIOB_CODR REG_ACCESS(WoReg, 0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ -#define REG_PIOB_ODSR REG_ACCESS(RwReg, 0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ -#define REG_PIOB_PDSR REG_ACCESS(RoReg, 0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ -#define REG_PIOB_IER REG_ACCESS(WoReg, 0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ -#define REG_PIOB_IDR REG_ACCESS(WoReg, 0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ -#define REG_PIOB_IMR REG_ACCESS(RoReg, 0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ -#define REG_PIOB_ISR REG_ACCESS(RoReg, 0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ -#define REG_PIOB_MDER REG_ACCESS(WoReg, 0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ -#define REG_PIOB_MDDR REG_ACCESS(WoReg, 0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ -#define REG_PIOB_MDSR REG_ACCESS(RoReg, 0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ -#define REG_PIOB_PUDR REG_ACCESS(WoReg, 0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ -#define REG_PIOB_PUER REG_ACCESS(WoReg, 0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ -#define REG_PIOB_PUSR REG_ACCESS(RoReg, 0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ -#define REG_PIOB_ABCDSR REG_ACCESS(RwReg, 0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */ -#define REG_PIOB_SCIFSR REG_ACCESS(WoReg, 0x400E1080U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */ -#define REG_PIOB_DIFSR REG_ACCESS(WoReg, 0x400E1084U) /**< \brief (PIOB) Debouncing Input Filter Select Register */ -#define REG_PIOB_IFDGSR REG_ACCESS(RoReg, 0x400E1088U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */ -#define REG_PIOB_SCDR REG_ACCESS(RwReg, 0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ -#define REG_PIOB_PPDDR REG_ACCESS(WoReg, 0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */ -#define REG_PIOB_PPDER REG_ACCESS(WoReg, 0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */ -#define REG_PIOB_PPDSR REG_ACCESS(RoReg, 0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */ -#define REG_PIOB_OWER REG_ACCESS(WoReg, 0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ -#define REG_PIOB_OWDR REG_ACCESS(WoReg, 0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ -#define REG_PIOB_OWSR REG_ACCESS(RoReg, 0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ -#define REG_PIOB_AIMER REG_ACCESS(WoReg, 0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ -#define REG_PIOB_AIMDR REG_ACCESS(WoReg, 0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */ -#define REG_PIOB_AIMMR REG_ACCESS(RoReg, 0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ -#define REG_PIOB_ESR REG_ACCESS(WoReg, 0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ -#define REG_PIOB_LSR REG_ACCESS(WoReg, 0x400E10C4U) /**< \brief (PIOB) Level Select Register */ -#define REG_PIOB_ELSR REG_ACCESS(RoReg, 0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ -#define REG_PIOB_FELLSR REG_ACCESS(WoReg, 0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */ -#define REG_PIOB_REHLSR REG_ACCESS(WoReg, 0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */ -#define REG_PIOB_FRLHSR REG_ACCESS(RoReg, 0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ -#define REG_PIOB_LOCKSR REG_ACCESS(RoReg, 0x400E10E0U) /**< \brief (PIOB) Lock Status */ -#define REG_PIOB_WPMR REG_ACCESS(RwReg, 0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */ -#define REG_PIOB_WPSR REG_ACCESS(RoReg, 0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */ -#define REG_PIOB_SCHMITT REG_ACCESS(RwReg, 0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */ -#define REG_PIOB_PCMR REG_ACCESS(RwReg, 0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */ -#define REG_PIOB_PCIER REG_ACCESS(WoReg, 0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */ -#define REG_PIOB_PCIDR REG_ACCESS(WoReg, 0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */ -#define REG_PIOB_PCIMR REG_ACCESS(RoReg, 0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */ -#define REG_PIOB_PCISR REG_ACCESS(RoReg, 0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */ -#define REG_PIOB_PCRHR REG_ACCESS(RoReg, 0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */ -/* ========== Register definition for PIOC peripheral ========== */ -#define REG_PIOC_PER REG_ACCESS(WoReg, 0x400E1200U) /**< \brief (PIOC) PIO Enable Register */ -#define REG_PIOC_PDR REG_ACCESS(WoReg, 0x400E1204U) /**< \brief (PIOC) PIO Disable Register */ -#define REG_PIOC_PSR REG_ACCESS(RoReg, 0x400E1208U) /**< \brief (PIOC) PIO Status Register */ -#define REG_PIOC_OER REG_ACCESS(WoReg, 0x400E1210U) /**< \brief (PIOC) Output Enable Register */ -#define REG_PIOC_ODR REG_ACCESS(WoReg, 0x400E1214U) /**< \brief (PIOC) Output Disable Register */ -#define REG_PIOC_OSR REG_ACCESS(RoReg, 0x400E1218U) /**< \brief (PIOC) Output Status Register */ -#define REG_PIOC_IFER REG_ACCESS(WoReg, 0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ -#define REG_PIOC_IFDR REG_ACCESS(WoReg, 0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ -#define REG_PIOC_IFSR REG_ACCESS(RoReg, 0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */ -#define REG_PIOC_SODR REG_ACCESS(WoReg, 0x400E1230U) /**< \brief (PIOC) Set Output Data Register */ -#define REG_PIOC_CODR REG_ACCESS(WoReg, 0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */ -#define REG_PIOC_ODSR REG_ACCESS(RwReg, 0x400E1238U) /**< \brief (PIOC) Output Data Status Register */ -#define REG_PIOC_PDSR REG_ACCESS(RoReg, 0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */ -#define REG_PIOC_IER REG_ACCESS(WoReg, 0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */ -#define REG_PIOC_IDR REG_ACCESS(WoReg, 0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */ -#define REG_PIOC_IMR REG_ACCESS(RoReg, 0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */ -#define REG_PIOC_ISR REG_ACCESS(RoReg, 0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */ -#define REG_PIOC_MDER REG_ACCESS(WoReg, 0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */ -#define REG_PIOC_MDDR REG_ACCESS(WoReg, 0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */ -#define REG_PIOC_MDSR REG_ACCESS(RoReg, 0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */ -#define REG_PIOC_PUDR REG_ACCESS(WoReg, 0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */ -#define REG_PIOC_PUER REG_ACCESS(WoReg, 0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */ -#define REG_PIOC_PUSR REG_ACCESS(RoReg, 0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */ -#define REG_PIOC_ABCDSR REG_ACCESS(RwReg, 0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */ -#define REG_PIOC_SCIFSR REG_ACCESS(WoReg, 0x400E1280U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */ -#define REG_PIOC_DIFSR REG_ACCESS(WoReg, 0x400E1284U) /**< \brief (PIOC) Debouncing Input Filter Select Register */ -#define REG_PIOC_IFDGSR REG_ACCESS(RoReg, 0x400E1288U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */ -#define REG_PIOC_SCDR REG_ACCESS(RwReg, 0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ -#define REG_PIOC_PPDDR REG_ACCESS(WoReg, 0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */ -#define REG_PIOC_PPDER REG_ACCESS(WoReg, 0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */ -#define REG_PIOC_PPDSR REG_ACCESS(RoReg, 0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */ -#define REG_PIOC_OWER REG_ACCESS(WoReg, 0x400E12A0U) /**< \brief (PIOC) Output Write Enable */ -#define REG_PIOC_OWDR REG_ACCESS(WoReg, 0x400E12A4U) /**< \brief (PIOC) Output Write Disable */ -#define REG_PIOC_OWSR REG_ACCESS(RoReg, 0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */ -#define REG_PIOC_AIMER REG_ACCESS(WoReg, 0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ -#define REG_PIOC_AIMDR REG_ACCESS(WoReg, 0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */ -#define REG_PIOC_AIMMR REG_ACCESS(RoReg, 0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ -#define REG_PIOC_ESR REG_ACCESS(WoReg, 0x400E12C0U) /**< \brief (PIOC) Edge Select Register */ -#define REG_PIOC_LSR REG_ACCESS(WoReg, 0x400E12C4U) /**< \brief (PIOC) Level Select Register */ -#define REG_PIOC_ELSR REG_ACCESS(RoReg, 0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */ -#define REG_PIOC_FELLSR REG_ACCESS(WoReg, 0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */ -#define REG_PIOC_REHLSR REG_ACCESS(WoReg, 0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */ -#define REG_PIOC_FRLHSR REG_ACCESS(RoReg, 0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ -#define REG_PIOC_LOCKSR REG_ACCESS(RoReg, 0x400E12E0U) /**< \brief (PIOC) Lock Status */ -#define REG_PIOC_WPMR REG_ACCESS(RwReg, 0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */ -#define REG_PIOC_WPSR REG_ACCESS(RoReg, 0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */ -#define REG_PIOC_SCHMITT REG_ACCESS(RwReg, 0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */ -#define REG_PIOC_PCMR REG_ACCESS(RwReg, 0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */ -#define REG_PIOC_PCIER REG_ACCESS(WoReg, 0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */ -#define REG_PIOC_PCIDR REG_ACCESS(WoReg, 0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */ -#define REG_PIOC_PCIMR REG_ACCESS(RoReg, 0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */ -#define REG_PIOC_PCISR REG_ACCESS(RoReg, 0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */ -#define REG_PIOC_PCRHR REG_ACCESS(RoReg, 0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */ -/* ========== Register definition for RSTC peripheral ========== */ -#define REG_RSTC_CR REG_ACCESS(WoReg, 0x400E1400U) /**< \brief (RSTC) Control Register */ -#define REG_RSTC_SR REG_ACCESS(RoReg, 0x400E1404U) /**< \brief (RSTC) Status Register */ -#define REG_RSTC_MR REG_ACCESS(RwReg, 0x400E1408U) /**< \brief (RSTC) Mode Register */ -/* ========== Register definition for SUPC peripheral ========== */ -#define REG_SUPC_CR REG_ACCESS(WoReg, 0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */ -#define REG_SUPC_SMMR REG_ACCESS(RwReg, 0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ -#define REG_SUPC_MR REG_ACCESS(RwReg, 0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */ -#define REG_SUPC_WUMR REG_ACCESS(RwReg, 0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */ -#define REG_SUPC_WUIR REG_ACCESS(RwReg, 0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */ -#define REG_SUPC_SR REG_ACCESS(RoReg, 0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */ -/* ========== Register definition for RTT peripheral ========== */ -#define REG_RTT_MR REG_ACCESS(RwReg, 0x400E1430U) /**< \brief (RTT) Mode Register */ -#define REG_RTT_AR REG_ACCESS(RwReg, 0x400E1434U) /**< \brief (RTT) Alarm Register */ -#define REG_RTT_VR REG_ACCESS(RoReg, 0x400E1438U) /**< \brief (RTT) Value Register */ -#define REG_RTT_SR REG_ACCESS(RoReg, 0x400E143CU) /**< \brief (RTT) Status Register */ -/* ========== Register definition for WDT peripheral ========== */ -#define REG_WDT_CR REG_ACCESS(WoReg, 0x400E1450U) /**< \brief (WDT) Control Register */ -#define REG_WDT_MR REG_ACCESS(RwReg, 0x400E1454U) /**< \brief (WDT) Mode Register */ -#define REG_WDT_SR REG_ACCESS(RoReg, 0x400E1458U) /**< \brief (WDT) Status Register */ -/* ========== Register definition for RTC peripheral ========== */ -#define REG_RTC_CR REG_ACCESS(RwReg, 0x400E1460U) /**< \brief (RTC) Control Register */ -#define REG_RTC_MR REG_ACCESS(RwReg, 0x400E1464U) /**< \brief (RTC) Mode Register */ -#define REG_RTC_TIMR REG_ACCESS(RwReg, 0x400E1468U) /**< \brief (RTC) Time Register */ -#define REG_RTC_CALR REG_ACCESS(RwReg, 0x400E146CU) /**< \brief (RTC) Calendar Register */ -#define REG_RTC_TIMALR REG_ACCESS(RwReg, 0x400E1470U) /**< \brief (RTC) Time Alarm Register */ -#define REG_RTC_CALALR REG_ACCESS(RwReg, 0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */ -#define REG_RTC_SR REG_ACCESS(RoReg, 0x400E1478U) /**< \brief (RTC) Status Register */ -#define REG_RTC_SCCR REG_ACCESS(WoReg, 0x400E147CU) /**< \brief (RTC) Status Clear Command Register */ -#define REG_RTC_IER REG_ACCESS(WoReg, 0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */ -#define REG_RTC_IDR REG_ACCESS(WoReg, 0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */ -#define REG_RTC_IMR REG_ACCESS(RoReg, 0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */ -#define REG_RTC_VER REG_ACCESS(RoReg, 0x400E148CU) /**< \brief (RTC) Valid Entry Register */ -/* ========== Register definition for GPBR peripheral ========== */ -#define REG_GPBR_GPBR0 REG_ACCESS(RwReg, 0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register 0 */ -#define REG_GPBR_GPBR1 REG_ACCESS(RwReg, 0x400E1494U) /**< \brief (GPBR) General Purpose Backup Register 1 */ -#define REG_GPBR_GPBR2 REG_ACCESS(RwReg, 0x400E1498U) /**< \brief (GPBR) General Purpose Backup Register 2 */ -#define REG_GPBR_GPBR3 REG_ACCESS(RwReg, 0x400E149CU) /**< \brief (GPBR) General Purpose Backup Register 3 */ -/*@}*/ - -/* ***************************************************************************** */ -/* PERIPHERAL ID DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_id Peripheral Ids Definitions */ -/*@{*/ - -#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ -#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ -#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ -#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ -#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ -#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ -#define ID_EFC ( 6) /**< \brief Enhanced Flash Controller (EFC) */ -#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */ -#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */ -#define ID_SMC (10) /**< \brief Static Memory Controller (SMC) */ -#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ -#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ -#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */ -#define ID_USART0 (14) /**< \brief USART 0 (USART0) */ -#define ID_USART1 (15) /**< \brief USART 1 (USART1) */ -#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ -#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */ -#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */ -#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */ -#define ID_SSC (22) /**< \brief Synchronous Serial Controler (SSC) */ -#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ -#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ -#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ -#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ -#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ -#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ -#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ -#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ -#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */ -#define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */ -#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ -#define ID_UDP (34) /**< \brief USB Device Port (UDP) */ -/*@}*/ - -/* ***************************************************************************** */ -/* BASE ADDRESS DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_base Peripheral Base Address Definitions */ -/*@{*/ - -#define HSMCI CAST(Hsmci , 0x40000000U) /**< \brief (HSMCI ) Base Address */ -#define PDC_HSMCI CAST(Pdc , 0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ -#define SSC CAST(Ssc , 0x40004000U) /**< \brief (SSC ) Base Address */ -#define PDC_SSC CAST(Pdc , 0x40004100U) /**< \brief (PDC_SSC ) Base Address */ -#define SPI CAST(Spi , 0x40008000U) /**< \brief (SPI ) Base Address */ -#define PDC_SPI CAST(Pdc , 0x40008100U) /**< \brief (PDC_SPI ) Base Address */ -#define TC0 CAST(Tc , 0x40010000U) /**< \brief (TC0 ) Base Address */ -#define TC1 CAST(Tc , 0x40014000U) /**< \brief (TC1 ) Base Address */ -#define TWI0 CAST(Twi , 0x40018000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 CAST(Pdc , 0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 CAST(Twi , 0x4001C000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 CAST(Pdc , 0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define PWM CAST(Pwm , 0x40020000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM CAST(Pdc , 0x40020100U) /**< \brief (PDC_PWM ) Base Address */ -#define USART0 CAST(Usart , 0x40024000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 CAST(Pdc , 0x40024100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 CAST(Usart , 0x40028000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 CAST(Pdc , 0x40028100U) /**< \brief (PDC_USART1) Base Address */ -#define UDP CAST(Udp , 0x40034000U) /**< \brief (UDP ) Base Address */ -#define ADC CAST(Adc , 0x40038000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC CAST(Pdc , 0x40038100U) /**< \brief (PDC_ADC ) Base Address */ -#define DACC CAST(Dacc , 0x4003C000U) /**< \brief (DACC ) Base Address */ -#define PDC_DACC CAST(Pdc , 0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ -#define ACC CAST(Acc , 0x40040000U) /**< \brief (ACC ) Base Address */ -#define CRCCU CAST(Crccu , 0x40044000U) /**< \brief (CRCCU ) Base Address */ -#define SMC CAST(Smc , 0x400E0000U) /**< \brief (SMC ) Base Address */ -#define MATRIX CAST(Matrix , 0x400E0200U) /**< \brief (MATRIX ) Base Address */ -#define PMC CAST(Pmc , 0x400E0400U) /**< \brief (PMC ) Base Address */ -#define UART0 CAST(Uart , 0x400E0600U) /**< \brief (UART0 ) Base Address */ -#define PDC_UART0 CAST(Pdc , 0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ -#define CHIPID CAST(Chipid , 0x400E0740U) /**< \brief (CHIPID ) Base Address */ -#define UART1 CAST(Uart , 0x400E0800U) /**< \brief (UART1 ) Base Address */ -#define PDC_UART1 CAST(Pdc , 0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ -#define EFC CAST(Efc , 0x400E0A00U) /**< \brief (EFC ) Base Address */ -#define PIOA CAST(Pio , 0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB CAST(Pio , 0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define PIOC CAST(Pio , 0x400E1200U) /**< \brief (PIOC ) Base Address */ -#define RSTC CAST(Rstc , 0x400E1400U) /**< \brief (RSTC ) Base Address */ -#define SUPC CAST(Supc , 0x400E1410U) /**< \brief (SUPC ) Base Address */ -#define RTT CAST(Rtt , 0x400E1430U) /**< \brief (RTT ) Base Address */ -#define WDT CAST(Wdt , 0x400E1450U) /**< \brief (WDT ) Base Address */ -#define RTC CAST(Rtc , 0x400E1460U) /**< \brief (RTC ) Base Address */ -#define GPBR CAST(Gpbr , 0x400E1490U) /**< \brief (GPBR ) Base Address */ - -// indices for three pio structures -#define iPIOA 0 -#define iPIOB 1 -#define iPIOC 2 -/*@}*/ - -/* ***************************************************************************** */ -/* PIO DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_pio Peripheral Pio Definitions */ -/*@{*/ - -#define PIO_PA0 (1 << 0) /**< \brief Pin Controlled by PA0 */ -#define PIO_PA1 (1 << 1) /**< \brief Pin Controlled by PA1 */ -#define PIO_PA2 (1 << 2) /**< \brief Pin Controlled by PA2 */ -#define PIO_PA3 (1 << 3) /**< \brief Pin Controlled by PA3 */ -#define PIO_PA4 (1 << 4) /**< \brief Pin Controlled by PA4 */ -#define PIO_PA5 (1 << 5) /**< \brief Pin Controlled by PA5 */ -#define PIO_PA6 (1 << 6) /**< \brief Pin Controlled by PA6 */ -#define PIO_PA7 (1 << 7) /**< \brief Pin Controlled by PA7 */ -#define PIO_PA8 (1 << 8) /**< \brief Pin Controlled by PA8 */ -#define PIO_PA9 (1 << 9) /**< \brief Pin Controlled by PA9 */ -#define PIO_PA10 (1 << 10) /**< \brief Pin Controlled by PA10 */ -#define PIO_PA11 (1 << 11) /**< \brief Pin Controlled by PA11 */ -#define PIO_PA12 (1 << 12) /**< \brief Pin Controlled by PA12 */ -#define PIO_PA13 (1 << 13) /**< \brief Pin Controlled by PA13 */ -#define PIO_PA14 (1 << 14) /**< \brief Pin Controlled by PA14 */ -#define PIO_PA15 (1 << 15) /**< \brief Pin Controlled by PA15 */ -#define PIO_PA16 (1 << 16) /**< \brief Pin Controlled by PA16 */ -#define PIO_PA17 (1 << 17) /**< \brief Pin Controlled by PA17 */ -#define PIO_PA18 (1 << 18) /**< \brief Pin Controlled by PA18 */ -#define PIO_PA19 (1 << 19) /**< \brief Pin Controlled by PA19 */ -#define PIO_PA20 (1 << 20) /**< \brief Pin Controlled by PA20 */ -#define PIO_PA21 (1 << 21) /**< \brief Pin Controlled by PA21 */ -#define PIO_PA22 (1 << 22) /**< \brief Pin Controlled by PA22 */ -#define PIO_PA23 (1 << 23) /**< \brief Pin Controlled by PA23 */ -#define PIO_PA24 (1 << 24) /**< \brief Pin Controlled by PA24 */ -#define PIO_PA25 (1 << 25) /**< \brief Pin Controlled by PA25 */ -#define PIO_PA26 (1 << 26) /**< \brief Pin Controlled by PA26 */ -#define PIO_PA27 (1 << 27) /**< \brief Pin Controlled by PA27 */ -#define PIO_PA28 (1 << 28) /**< \brief Pin Controlled by PA28 */ -#define PIO_PA29 (1 << 29) /**< \brief Pin Controlled by PA29 */ -#define PIO_PA30 (1 << 30) /**< \brief Pin Controlled by PA30 */ -#define PIO_PA31 (1 << 31) /**< \brief Pin Controlled by PA31 */ -#define PIO_PB0 (1 << 0) /**< \brief Pin Controlled by PB0 */ -#define PIO_PB1 (1 << 1) /**< \brief Pin Controlled by PB1 */ -#define PIO_PB2 (1 << 2) /**< \brief Pin Controlled by PB2 */ -#define PIO_PB3 (1 << 3) /**< \brief Pin Controlled by PB3 */ -#define PIO_PB4 (1 << 4) /**< \brief Pin Controlled by PB4 */ -#define PIO_PB5 (1 << 5) /**< \brief Pin Controlled by PB5 */ -#define PIO_PB6 (1 << 6) /**< \brief Pin Controlled by PB6 */ -#define PIO_PB7 (1 << 7) /**< \brief Pin Controlled by PB7 */ -#define PIO_PB8 (1 << 8) /**< \brief Pin Controlled by PB8 */ -#define PIO_PB9 (1 << 9) /**< \brief Pin Controlled by PB9 */ -#define PIO_PB10 (1 << 10) /**< \brief Pin Controlled by PB10 */ -#define PIO_PB11 (1 << 11) /**< \brief Pin Controlled by PB11 */ -#define PIO_PB12 (1 << 12) /**< \brief Pin Controlled by PB12 */ -#define PIO_PB13 (1 << 13) /**< \brief Pin Controlled by PB13 */ -#define PIO_PB14 (1 << 14) /**< \brief Pin Controlled by PB14 */ -#define PIO_PC0 (1 << 0) /**< \brief Pin Controlled by PC0 */ -#define PIO_PC1 (1 << 1) /**< \brief Pin Controlled by PC1 */ -#define PIO_PC2 (1 << 2) /**< \brief Pin Controlled by PC2 */ -#define PIO_PC3 (1 << 3) /**< \brief Pin Controlled by PC3 */ -#define PIO_PC4 (1 << 4) /**< \brief Pin Controlled by PC4 */ -#define PIO_PC5 (1 << 5) /**< \brief Pin Controlled by PC5 */ -#define PIO_PC6 (1 << 6) /**< \brief Pin Controlled by PC6 */ -#define PIO_PC7 (1 << 7) /**< \brief Pin Controlled by PC7 */ -#define PIO_PC8 (1 << 8) /**< \brief Pin Controlled by PC8 */ -#define PIO_PC9 (1 << 9) /**< \brief Pin Controlled by PC9 */ -#define PIO_PC10 (1 << 10) /**< \brief Pin Controlled by PC10 */ -#define PIO_PC11 (1 << 11) /**< \brief Pin Controlled by PC11 */ -#define PIO_PC12 (1 << 12) /**< \brief Pin Controlled by PC12 */ -#define PIO_PC13 (1 << 13) /**< \brief Pin Controlled by PC13 */ -#define PIO_PC14 (1 << 14) /**< \brief Pin Controlled by PC14 */ -#define PIO_PC15 (1 << 15) /**< \brief Pin Controlled by PC15 */ -#define PIO_PC16 (1 << 16) /**< \brief Pin Controlled by PC16 */ -#define PIO_PC17 (1 << 17) /**< \brief Pin Controlled by PC17 */ -#define PIO_PC18 (1 << 18) /**< \brief Pin Controlled by PC18 */ -#define PIO_PC19 (1 << 19) /**< \brief Pin Controlled by PC19 */ -#define PIO_PC20 (1 << 20) /**< \brief Pin Controlled by PC20 */ -#define PIO_PC21 (1 << 21) /**< \brief Pin Controlled by PC21 */ -#define PIO_PC22 (1 << 22) /**< \brief Pin Controlled by PC22 */ -#define PIO_PC23 (1 << 23) /**< \brief Pin Controlled by PC23 */ -#define PIO_PC24 (1 << 24) /**< \brief Pin Controlled by PC24 */ -#define PIO_PC25 (1 << 25) /**< \brief Pin Controlled by PC25 */ -#define PIO_PC26 (1 << 26) /**< \brief Pin Controlled by PC26 */ -#define PIO_PC27 (1 << 27) /**< \brief Pin Controlled by PC27 */ -#define PIO_PC28 (1 << 28) /**< \brief Pin Controlled by PC28 */ -#define PIO_PC29 (1 << 29) /**< \brief Pin Controlled by PC29 */ -#define PIO_PC30 (1 << 30) /**< \brief Pin Controlled by PC30 */ -#define PIO_PC31 (1 << 31) /**< \brief Pin Controlled by PC31 */ -/* ========== Pio definition for HSMCI peripheral ========== */ -#define PIO_PA28C_MCCDA (1 << 28) /**< \brief Hsmci signal: MCCDA */ -#define PIO_PA29C_MCCK (1 << 29) /**< \brief Hsmci signal: MCCK */ -#define PIO_PA30C_MCDA0 (1 << 30) /**< \brief Hsmci signal: MCDA0 */ -#define PIO_PA31C_MCDA1 (1 << 31) /**< \brief Hsmci signal: MCDA1 */ -#define PIO_PA26C_MCDA2 (1 << 26) /**< \brief Hsmci signal: MCDA2 */ -#define PIO_PA27C_MCDA3 (1 << 27) /**< \brief Hsmci signal: MCDA3 */ -/* ========== Pio definition for SSC peripheral ========== */ -#define PIO_PA18A_RD (1 << 18) /**< \brief Ssc signal: RD */ -#define PIO_PA20A_RF (1 << 20) /**< \brief Ssc signal: RF */ -#define PIO_PA19A_RK (1 << 19) /**< \brief Ssc signal: RK */ -#define PIO_PA17A_TD (1 << 17) /**< \brief Ssc signal: TD */ -#define PIO_PA15A_TF (1 << 15) /**< \brief Ssc signal: TF */ -#define PIO_PA16A_TK (1 << 16) /**< \brief Ssc signal: TK */ -/* ========== Pio definition for SPI peripheral ========== */ -#define PIO_PA12A_MISO (1 << 12) /**< \brief Spi signal: MISO */ -#define PIO_PA13A_MOSI (1 << 13) /**< \brief Spi signal: MOSI */ -#define PIO_PA11A_NPCS0 (1 << 11) /**< \brief Spi signal: NPCS0 */ -#define PIO_PA31A_NPCS1 (1 << 31) /**< \brief Spi signal: NPCS1 */ -#define PIO_PA9B_NPCS1 (1 << 9) /**< \brief Spi signal: NPCS1 */ -#define PIO_PB14A_NPCS1 (1 << 14) /**< \brief Spi signal: NPCS1 */ -#define PIO_PC4B_NPCS1 (1 << 4) /**< \brief Spi signal: NPCS1 */ -#define PIO_PA10B_NPCS2 (1 << 10) /**< \brief Spi signal: NPCS2 */ -#define PIO_PA30B_NPCS2 (1 << 30) /**< \brief Spi signal: NPCS2 */ -#define PIO_PB2B_NPCS2 (1 << 2) /**< \brief Spi signal: NPCS2 */ -#define PIO_PA22B_NPCS3 (1 << 22) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA3B_NPCS3 (1 << 3) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA5B_NPCS3 (1 << 5) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA14A_SPCK (1 << 14) /**< \brief Spi signal: SPCK */ -/* ========== Pio definition for TC0 peripheral ========== */ -#define PIO_PA4B_TCLK0 (1 << 4) /**< \brief Tc0 signal: TCLK0 */ -#define PIO_PA28B_TCLK1 (1 << 28) /**< \brief Tc0 signal: TCLK1 */ -#define PIO_PA29B_TCLK2 (1 << 29) /**< \brief Tc0 signal: TCLK2 */ -#define PIO_PA0B_TIOA0 (1 << 0) /**< \brief Tc0 signal: TIOA0 */ -#define PIO_PA15B_TIOA1 (1 << 15) /**< \brief Tc0 signal: TIOA1 */ -#define PIO_PA26B_TIOA2 (1 << 26) /**< \brief Tc0 signal: TIOA2 */ -#define PIO_PA1B_TIOB0 (1 << 1) /**< \brief Tc0 signal: TIOB0 */ -#define PIO_PA16B_TIOB1 (1 << 16) /**< \brief Tc0 signal: TIOB1 */ -#define PIO_PA27B_TIOB2 (1 << 27) /**< \brief Tc0 signal: TIOB2 */ -/* ========== Pio definition for TC1 peripheral ========== */ -#define PIO_PC25B_TCLK3 (1 << 25) /**< \brief Tc1 signal: TCLK3 */ -#define PIO_PC28B_TCLK4 (1 << 28) /**< \brief Tc1 signal: TCLK4 */ -#define PIO_PC31B_TCLK5 (1 << 31) /**< \brief Tc1 signal: TCLK5 */ -#define PIO_PC23B_TIOA3 (1 << 23) /**< \brief Tc1 signal: TIOA3 */ -#define PIO_PC26B_TIOA4 (1 << 26) /**< \brief Tc1 signal: TIOA4 */ -#define PIO_PC29B_TIOA5 (1 << 29) /**< \brief Tc1 signal: TIOA5 */ -#define PIO_PC24B_TIOB3 (1 << 24) /**< \brief Tc1 signal: TIOB3 */ -#define PIO_PC27B_TIOB4 (1 << 27) /**< \brief Tc1 signal: TIOB4 */ -#define PIO_PC30B_TIOB5 (1 << 30) /**< \brief Tc1 signal: TIOB5 */ -/* ========== Pio definition for TWI0 peripheral ========== */ -#define PIO_PA4A_TWCK0 (1 << 4) /**< \brief Twi0 signal: TWCK0 */ -#define PIO_PA3A_TWD0 (1 << 3) /**< \brief Twi0 signal: TWD0 */ -/* ========== Pio definition for TWI1 peripheral ========== */ -#define PIO_PB5A_TWCK1 (1 << 5) /**< \brief Twi1 signal: TWCK1 */ -#define PIO_PB4A_TWD1 (1 << 4) /**< \brief Twi1 signal: TWD1 */ -/* ========== Pio definition for PWM peripheral ========== */ -#define PIO_PA9C_PWMFI0 (1 << 9) /**< \brief Pwm signal: PWMFI0 */ -#define PIO_PA0A_PWMH0 (1 << 0) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA11B_PWMH0 (1 << 11) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA23B_PWMH0 (1 << 23) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PB0A_PWMH0 (1 << 0) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PC18B_PWMH0 (1 << 18) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA1A_PWMH1 (1 << 1) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA12B_PWMH1 (1 << 12) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA24B_PWMH1 (1 << 24) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PB1A_PWMH1 (1 << 1) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PC19B_PWMH1 (1 << 19) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA13B_PWMH2 (1 << 13) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA2A_PWMH2 (1 << 2) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA25B_PWMH2 (1 << 25) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PB4B_PWMH2 (1 << 4) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PC20B_PWMH2 (1 << 20) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA14B_PWMH3 (1 << 14) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA17C_PWMH3 (1 << 17) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA7B_PWMH3 (1 << 7) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PB14B_PWMH3 (1 << 14) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PC21B_PWMH3 (1 << 21) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA19B_PWML0 (1 << 19) /**< \brief Pwm signal: PWML0 */ -#define PIO_PB5B_PWML0 (1 << 5) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC0B_PWML0 (1 << 0) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC13B_PWML0 (1 << 13) /**< \brief Pwm signal: PWML0 */ -#define PIO_PA20B_PWML1 (1 << 20) /**< \brief Pwm signal: PWML1 */ -#define PIO_PB12A_PWML1 (1 << 12) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC1B_PWML1 (1 << 1) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC15B_PWML1 (1 << 15) /**< \brief Pwm signal: PWML1 */ -#define PIO_PA16C_PWML2 (1 << 16) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA30A_PWML2 (1 << 30) /**< \brief Pwm signal: PWML2 */ -#define PIO_PB13A_PWML2 (1 << 13) /**< \brief Pwm signal: PWML2 */ -#define PIO_PC2B_PWML2 (1 << 2) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA15C_PWML3 (1 << 15) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC22B_PWML3 (1 << 22) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC3B_PWML3 (1 << 3) /**< \brief Pwm signal: PWML3 */ -/* ========== Pio definition for USART0 peripheral ========== */ -#define PIO_PA8A_CTS0 (1 << 8) /**< \brief Usart0 signal: CTS0 */ -#define PIO_PA7A_RTS0 (1 << 7) /**< \brief Usart0 signal: RTS0 */ -#define PIO_PA5A_RXD0 (1 << 5) /**< \brief Usart0 signal: RXD0 */ -#define PIO_PA2B_SCK0 (1 << 2) /**< \brief Usart0 signal: SCK0 */ -#define PIO_PA6A_TXD0 (1 << 6) /**< \brief Usart0 signal: TXD0 */ -/* ========== Pio definition for USART1 peripheral ========== */ -#define PIO_PA25A_CTS1 (1 << 25) /**< \brief Usart1 signal: CTS1 */ -#define PIO_PA26A_DCD1 (1 << 26) /**< \brief Usart1 signal: DCD1 */ -#define PIO_PA28A_DSR1 (1 << 28) /**< \brief Usart1 signal: DSR1 */ -#define PIO_PA27A_DTR1 (1 << 27) /**< \brief Usart1 signal: DTR1 */ -#define PIO_PA29A_RI1 (1 << 29) /**< \brief Usart1 signal: RI1 */ -#define PIO_PA24A_RTS1 (1 << 24) /**< \brief Usart1 signal: RTS1 */ -#define PIO_PA21A_RXD1 (1 << 21) /**< \brief Usart1 signal: RXD1 */ -#define PIO_PA23A_SCK1 (1 << 23) /**< \brief Usart1 signal: SCK1 */ -#define PIO_PA22A_TXD1 (1 << 22) /**< \brief Usart1 signal: TXD1 */ -/* ========== Pio definition for ADC peripheral ========== */ -#define PIO_PA17X1_AD0 (1 << 17) /**< \brief Adc signal: AD0 */ -#define PIO_PA18X1_AD1 (1 << 18) /**< \brief Adc signal: AD1 */ -#define PIO_PC13X1_AD10 (1 << 13) /**< \brief Adc signal: AD10 */ -#define PIO_PC15X1_AD11 (1 << 15) /**< \brief Adc signal: AD11 */ -#define PIO_PC12X1_AD12 (1 << 12) /**< \brief Adc signal: AD12 */ -#define PIO_PC29X1_AD13 (1 << 29) /**< \brief Adc signal: AD13 */ -#define PIO_PC30X1_AD14 (1 << 30) /**< \brief Adc signal: AD14 */ -#define PIO_PA19X1_AD2 (1 << 19) /**< \brief Adc signal: AD2 */ -#define PIO_PA20X1_AD3 (1 << 20) /**< \brief Adc signal: AD3 */ -#define PIO_PB0X1_AD4 (1 << 0) /**< \brief Adc signal: AD4 */ -#define PIO_PB1X1_AD5 (1 << 1) /**< \brief Adc signal: AD5 */ -#define PIO_PB2X1_AD6 (1 << 2) /**< \brief Adc signal: AD6 */ -#define PIO_PB3X1_AD7 (1 << 3) /**< \brief Adc signal: AD7 */ -#define PIO_PA21X1_AD8 (1 << 21) /**< \brief Adc signal: AD8 */ -#define PIO_PA22X1_AD9 (1 << 22) /**< \brief Adc signal: AD9 */ -#define PIO_PA8B_ADTRG (1 << 8) /**< \brief Adc signal: ADTRG */ -/* ========== Pio definition for DACC peripheral ========== */ -#define PIO_PB13X1_DAC0 (1 << 13) /**< \brief Dacc signal: DAC0 */ -#define PIO_PB14X1_DAC1 (1 << 14) /**< \brief Dacc signal: DAC1 */ -#define PIO_PA2C_DATRG (1 << 2) /**< \brief Dacc signal: DATRG */ -/* ========== Pio definition for PMC peripheral ========== */ -#define PIO_PA6B_PCK0 (1 << 6) /**< \brief Pmc signal: PCK0 */ -#define PIO_PB13B_PCK0 (1 << 13) /**< \brief Pmc signal: PCK0 */ -#define PIO_PA17B_PCK1 (1 << 17) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA21B_PCK1 (1 << 21) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA18B_PCK2 (1 << 18) /**< \brief Pmc signal: PCK2 */ -#define PIO_PA31B_PCK2 (1 << 31) /**< \brief Pmc signal: PCK2 */ -#define PIO_PB3B_PCK2 (1 << 3) /**< \brief Pmc signal: PCK2 */ -/* ========== Pio definition for UART0 peripheral ========== */ -#define PIO_PA9A_URXD0 (1 << 9) /**< \brief Uart0 signal: URXD0 */ -#define PIO_PA10A_UTXD0 (1 << 10) /**< \brief Uart0 signal: UTXD0 */ -/* ========== Pio definition for UART1 peripheral ========== */ -#define PIO_PB2A_URXD1 (1 << 2) /**< \brief Uart1 signal: URXD1 */ -#define PIO_PB3A_UTXD1 (1 << 3) /**< \brief Uart1 signal: UTXD1 */ -/* ========== Pio definition for PIOA peripheral ========== */ -#define PIO_PA24X1_PIODC0 (1 << 24) /**< \brief Pioa signal: PIODC0 */ -#define PIO_PA25X1_PIODC1 (1 << 25) /**< \brief Pioa signal: PIODC1 */ -#define PIO_PA26X1_PIODC2 (1 << 26) /**< \brief Pioa signal: PIODC2 */ -#define PIO_PA27X1_PIODC3 (1 << 27) /**< \brief Pioa signal: PIODC3 */ -#define PIO_PA28X1_PIODC4 (1 << 28) /**< \brief Pioa signal: PIODC4 */ -#define PIO_PA29X1_PIODC5 (1 << 29) /**< \brief Pioa signal: PIODC5 */ -#define PIO_PA30X1_PIODC6 (1 << 30) /**< \brief Pioa signal: PIODC6 */ -#define PIO_PA31X1_PIODC7 (1 << 31) /**< \brief Pioa signal: PIODC7 */ -#define PIO_PA23X1_PIODCCLK (1 << 23) /**< \brief Pioa signal: PIODCCLK */ -#define PIO_PA15X1_PIODCEN1 (1 << 15) /**< \brief Pioa signal: PIODCEN1 */ -#define PIO_PA16X1_PIODCEN2 (1 << 16) /**< \brief Pioa signal: PIODCEN2 */ -/*@}*/ - -/* ***************************************************************************** */ -/* MEMORY MAPPING DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ - -#define AT91C_IRAM (0x20000000) /**< Internal RAM base address */ -#define AT91C_IFLASH (0x00400000) /**< Internal Flash base address */ -#define AT91C_IROM (0x00800000) /**< Internal ROM base address */ -#define AT91C_IRAM (0x20000000) /**< Internal RAM base address */ -#define AT91C_EBI_CS0 (0x60000000) /**< EBI Chip Select 0 base address */ -#define AT91C_EBI_CS1 (0x61000000) /**< EBI Chip Select 1 base address */ -#define AT91C_EBI_CS2 (0x62000000) /**< EBI Chip Select 2 base address */ -#define AT91C_EBI_CS3 (0x63000000) /**< EBI Chip Select 3 base address */ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* AT91SAM3S_H */ diff --git a/radio/bootloader/sam3s4c_boot.ld b/radio/bootloader/sam3s4c_boot.ld deleted file mode 100644 index ffda73521..000000000 --- a/radio/bootloader/sam3s4c_boot.ld +++ /dev/null @@ -1,144 +0,0 @@ -/**************************************************************************** -* Copyright (c) 2011 by Michael Fischer. All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* 1. Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* 3. Neither the name of the author nor the names of its contributors may -* be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL -* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -* SUCH DAMAGE. -* -***************************************************************************** -* History: -* -* 22.05.2011 mifi First Version -****************************************************************************/ - - -/* - * In this linker script there is no heap available. - * The stack start at the end of the ram segment. - */ - - -/* - * Take a look in the "The GNU linker" manual, here you get - * the following information about the "MEMORY": - * - * "The MEMORY command describes the location and size of - * blocks of memory in the target." - */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00400000, LENGTH = 256K - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 48K -} - - -/* - * And the "SECTION" is used for: - * - * "The SECTIONS command tells the linker how to map input - * sections into output sections, and how to place the output - * sections in memory. - */ -SECTIONS -{ - - /* - * The ".text" section is used for the code, and - * read only (.rodata) data. Even the vectors (.vectors) - * MUST be saved at the start of this section. - */ - .text : - { - _stext = .; /* Provide the name for the start of this section */ - - CREATE_OBJECT_SYMBOLS - KEEP(*(.vectors)) - - *(.text) - *(.text.*) - - . = ALIGN(4); /* Align the start of the exidx part */ - *(.ARM.exidx) - *(.ARM.exidx.*) - - . = ALIGN(4); /* Align the start of the rodata part */ - *(.rodata) - *(.rodata.*) - - . = ALIGN(4); /* Align the end of the section */ - } > FLASH - _etext = .; /* Provide the name for the end of this section */ - - - /* - * The ".data" section is used for initialized data - * and for functions (.fastrun) which should be copied - * from flash to ram. This functions will later be - * executed from ram instead of flash. - */ - .data : AT (_etext) - { - . = ALIGN(4); /* Align the start of the section */ - _sdata = .; /* Provide the name for the start of this section */ - - *(.data) - *(.data.*) - - . = ALIGN(4); /* Align the start of the fastrun part */ - *(.fastrun) - *(.fastrun.*) - - . = ALIGN(4); /* Align the end of the section */ - } > RAM - _edata = .; /* Provide the name for the end of this section */ - - - /* - * The ".bss" section is used for uninitialized data. - * This section will be cleared by the startup code. - */ - .bss : - { - . = ALIGN(4); /* Align the start of the section */ - _sbss = .; /* Provide the name for the start of this section */ - - *(.bss) - *(.bss.*) - - . = ALIGN(4); /* Align the end of the section */ - } > RAM = 0 - _ebss = .; /* Provide the name for the end of this section */ - - - /* - * The ".stack" section is our stack. - * Here this section starts at the end of the ram segment. - */ - _estack = ORIGIN(RAM) + LENGTH(RAM); - -} - -/*** EOF **/ - diff --git a/radio/bootloader/sam3s8c_boot.ld b/radio/bootloader/sam3s8c_boot.ld deleted file mode 100644 index 1a8584c77..000000000 --- a/radio/bootloader/sam3s8c_boot.ld +++ /dev/null @@ -1,144 +0,0 @@ -/**************************************************************************** -* Copyright (c) 2011 by Michael Fischer. All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* 1. Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* 3. Neither the name of the author nor the names of its contributors may -* be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL -* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -* SUCH DAMAGE. -* -***************************************************************************** -* History: -* -* 22.05.2011 mifi First Version -****************************************************************************/ - - -/* - * In this linker script there is no heap available. - * The stack start at the end of the ram segment. - */ - - -/* - * Take a look in the "The GNU linker" manual, here you get - * the following information about the "MEMORY": - * - * "The MEMORY command describes the location and size of - * blocks of memory in the target." - */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00400000, LENGTH = 512K - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 48K -} - - -/* - * And the "SECTION" is used for: - * - * "The SECTIONS command tells the linker how to map input - * sections into output sections, and how to place the output - * sections in memory. - */ -SECTIONS -{ - - /* - * The ".text" section is used for the code, and - * read only (.rodata) data. Even the vectors (.vectors) - * MUST be saved at the start of this section. - */ - .text : - { - _stext = .; /* Provide the name for the start of this section */ - - CREATE_OBJECT_SYMBOLS - KEEP(*(.vectors)) - - *(.text) - *(.text.*) - - . = ALIGN(4); /* Align the start of the exidx part */ - *(.ARM.exidx) - *(.ARM.exidx.*) - - . = ALIGN(4); /* Align the start of the rodata part */ - *(.rodata) - *(.rodata.*) - - . = ALIGN(4); /* Align the end of the section */ - } > FLASH - _etext = .; /* Provide the name for the end of this section */ - - - /* - * The ".data" section is used for initialized data - * and for functions (.fastrun) which should be copied - * from flash to ram. This functions will later be - * executed from ram instead of flash. - */ - .data : AT (_etext) - { - . = ALIGN(4); /* Align the start of the section */ - _sdata = .; /* Provide the name for the start of this section */ - - *(.data) - *(.data.*) - - . = ALIGN(4); /* Align the start of the fastrun part */ - *(.fastrun) - *(.fastrun.*) - - . = ALIGN(4); /* Align the end of the section */ - } > RAM - _edata = .; /* Provide the name for the end of this section */ - - - /* - * The ".bss" section is used for uninitialized data. - * This section will be cleared by the startup code. - */ - .bss : - { - . = ALIGN(4); /* Align the start of the section */ - _sbss = .; /* Provide the name for the start of this section */ - - *(.bss) - *(.bss.*) - - . = ALIGN(4); /* Align the end of the section */ - } > RAM = 0 - _ebss = .; /* Provide the name for the end of this section */ - - - /* - * The ".stack" section is our stack. - * Here this section starts at the end of the ram segment. - */ - _estack = ORIGIN(RAM) + LENGTH(RAM); - -} - -/*** EOF **/ - diff --git a/radio/bootloader/vectors_sam3s.c b/radio/bootloader/vectors_sam3s.c deleted file mode 100644 index 11f014cea..000000000 --- a/radio/bootloader/vectors_sam3s.c +++ /dev/null @@ -1,198 +0,0 @@ -/**************************************************************************** -* Copyright (c) 2011 by Michael Fischer. All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* 1. Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* 3. Neither the name of the author nor the names of its contributors may -* be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL -* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -* SUCH DAMAGE. -* -**************************************************************************** -* History: -* -* 22.05.2011 mifi First Version for the SAM3S4C -****************************************************************************/ -#define __VECTORS_SAM3S_C__ - -/*=========================================================================*/ -/* DEFINE: All extern Data */ -/*=========================================================================*/ -extern unsigned long _estack; - -/*=========================================================================*/ -/* DEFINE: Prototypes */ -/*=========================================================================*/ -void ResetHandler(void); - -void NMI_Handler (void) __attribute__((weak)); -void HardFault_Handler (void) __attribute__((weak)); -void MemManage_Handler (void) __attribute__((weak)); -void BusFault_Handler (void) __attribute__((weak)); -void UsageFault_Handler (void) __attribute__((weak)); -void SVC_Handler (void) __attribute__((weak)); -void DebugMon_Handler (void) __attribute__((weak)); -void PendSV_Handler (void) __attribute__((weak)); -void SysTick_Handler (void) __attribute__((weak)); - -void SUPC_IRQHandler (void) __attribute__((weak)); -void RSTC_IRQHandler (void) __attribute__((weak)); -void RTC_IRQHandler (void) __attribute__((weak)); -void RTT_IRQHandler (void) __attribute__((weak)); -void WDT_IRQHandler (void) __attribute__((weak)); -void PMC_IRQHandler (void) __attribute__((weak)); -void EEFC_IRQHandler (void) __attribute__((weak)); -void UART0_IRQHandler (void) __attribute__((weak)); -void UART1_IRQHandler (void) __attribute__((weak)); -void SMC_IRQHandler (void) __attribute__((weak)); -void PIOA_IRQHandler (void) __attribute__((weak)); -void PIOB_IRQHandler (void) __attribute__((weak)); -void PIOC_IRQHandler (void) __attribute__((weak)); -void USART0_IRQHandler (void) __attribute__((weak)); -void USART1_IRQHandler (void) __attribute__((weak)); -void MCI_IRQHandler (void) __attribute__((weak)); -void TWI0_IRQHandler (void) __attribute__((weak)); -void TWI1_IRQHandler (void) __attribute__((weak)); -void SPI_IRQHandler (void) __attribute__((weak)); -void SSC_IRQHandler (void) __attribute__((weak)); -void TC0_IRQHandler (void) __attribute__((weak)); -void TC1_IRQHandler (void) __attribute__((weak)); -void TC2_IRQHandler (void) __attribute__((weak)); -void TC3_IRQHandler (void) __attribute__((weak)); -void TC4_IRQHandler (void) __attribute__((weak)); -void TC5_IRQHandler (void) __attribute__((weak)); -void ADC_IRQHandler (void) __attribute__((weak)); -void DAC_IRQHandler (void) __attribute__((weak)); -void PWM_IRQHandler (void) __attribute__((weak)); -void CRCCU_IRQHandler (void) __attribute__((weak)); -void ACC_IRQHandler (void) __attribute__((weak)); -void USBD_IRQHandler (void) __attribute__((weak)); - -/*=========================================================================*/ -/* DEFINE: All code exported */ -/*=========================================================================*/ -/* - * This is our vector table. - */ -__attribute__ ((section(".vectors"), used)) -void (* const gVectors[])(void) = -{ - (void (*)(void))((unsigned long)&_estack), - ResetHandler, - NMI_Handler, - HardFault_Handler, - MemManage_Handler, - BusFault_Handler, - UsageFault_Handler, - 0, 0, 0, 0, - SVC_Handler, - DebugMon_Handler, - 0, - PendSV_Handler, - SysTick_Handler, - - SUPC_IRQHandler, /* 0 SUPPLY CONTROLLER */ - RSTC_IRQHandler, /* 1 RESET CONTROLLER */ - RTC_IRQHandler, /* 2 REAL TIME CLOCK */ - RTT_IRQHandler, /* 3 REAL TIME TIMER */ - WDT_IRQHandler, /* 4 WATCHDOG TIMER */ - PMC_IRQHandler, /* 5 PMC */ - EEFC_IRQHandler, /* 6 EEFC */ - 0, /* 7 Reserved */ - UART0_IRQHandler, /* 8 UART0 */ - UART1_IRQHandler, /* 9 UART1 */ - SMC_IRQHandler, /* 10 SMC */ - PIOA_IRQHandler, /* 11 Parallel IO Controller A */ - PIOB_IRQHandler, /* 12 Parallel IO Controller B */ - PIOC_IRQHandler, /* 13 Parallel IO Controller C */ - USART0_IRQHandler, /* 14 USART 0 */ - USART1_IRQHandler, /* 15 USART 1 */ - 0, /* 16 Reserved */ - 0, /* 17 Reserved */ - MCI_IRQHandler, /* 18 MCI */ - TWI0_IRQHandler, /* 19 TWI 0 */ - TWI1_IRQHandler, /* 20 TWI 1 */ - SPI_IRQHandler, /* 21 SPI */ - SSC_IRQHandler, /* 22 SSC */ - TC0_IRQHandler, /* 23 Timer Counter 0 */ - TC1_IRQHandler, /* 24 Timer Counter 1 */ - TC2_IRQHandler, /* 25 Timer Counter 2 */ - TC3_IRQHandler, /* 26 Timer Counter 3 */ - TC4_IRQHandler, /* 27 Timer Counter 4 */ - TC5_IRQHandler, /* 28 Timer Counter 5 */ - ADC_IRQHandler, /* 29 ADC controller */ - DAC_IRQHandler, /* 30 DAC controller */ - PWM_IRQHandler, /* 31 PWM */ - CRCCU_IRQHandler, /* 32 CRC Calculation Unit */ - ACC_IRQHandler, /* 33 Analog Comparator */ - USBD_IRQHandler, /* 34 USB Device Port */ - 0 /* 35 not used */ -}; /* gVectors */ - -/* - * And here are the weak interrupt handlers. - */ -void NMI_Handler (void) { while(1); } -void HardFault_Handler (void) { while(1); } -void MemManage_Handler (void) { while(1); } -void BusFault_Handler (void) { while(1); } -void UsageFault_Handler (void) { while(1); } -void SVC_Handler (void) { while(1); } -void DebugMon_Handler (void) { while(1); } -void PendSV_Handler (void) { while(1); } -void SysTick_Handler (void) { while(1); } - -void SUPC_IRQHandler (void) { while(1); } -void RSTC_IRQHandler (void) { while(1); } -void RTC_IRQHandler (void) { while(1); } -void RTT_IRQHandler (void) { while(1); } -void WDT_IRQHandler (void) { while(1); } -void PMC_IRQHandler (void) { while(1); } -void EEFC_IRQHandler (void) { while(1); } -void UART0_IRQHandler (void) { while(1); } -void UART1_IRQHandler (void) { while(1); } -void SMC_IRQHandler (void) { while(1); } -void PIOA_IRQHandler (void) { while(1); } -void PIOB_IRQHandler (void) { while(1); } -void PIOC_IRQHandler (void) { while(1); } -void USART0_IRQHandler (void) { while(1); } -void USART1_IRQHandler (void) { while(1); } -void MCI_IRQHandler (void) { while(1); } -void TWI0_IRQHandler (void) { while(1); } -void TWI1_IRQHandler (void) { while(1); } -void SPI_IRQHandler (void) { while(1); } -void SSC_IRQHandler (void) { while(1); } -void TC0_IRQHandler (void) { while(1); } -void TC1_IRQHandler (void) { while(1); } -void TC2_IRQHandler (void) { while(1); } -void TC3_IRQHandler (void) { while(1); } -void TC4_IRQHandler (void) { while(1); } -void TC5_IRQHandler (void) { while(1); } -void ADC_IRQHandler (void) { while(1); } -void DAC_IRQHandler (void) { while(1); } -void PWM_IRQHandler (void) { while(1); } -void CRCCU_IRQHandler (void) { while(1); } -void ACC_IRQHandler (void) { while(1); } -void USBD_IRQHandler (void) { while(1); } -// void USBD_IRQHandler (void) { while(1); } - -/*** EOF ***/ From b7e079a0d94b07b35560abe4e03f366e8994b1f2 Mon Sep 17 00:00:00 2001 From: bsongis Date: Tue, 4 Mar 2014 15:33:26 +0100 Subject: [PATCH 019/285] 2 files removed --- radio/bootloader/Makefile | 7 +-- radio/bootloader/boot.cpp | 2 +- radio/bootloader/include/aspi.h | 37 ------------- radio/bootloader/include/i2c_ee.h | 52 ------------------- radio/bootloader/lcd_driver.cpp | 4 +- radio/bootloader/usbd_storage_msd.cpp | 2 +- radio/src/Makefile | 4 +- .../src/targets/taranis/{aspi.cpp => aspi.c} | 3 +- radio/src/targets/taranis/aspi.h | 8 +++ radio/src/targets/taranis/board_taranis.h | 47 +++++++++++------ .../targets/taranis/{delays.cpp => delays.c} | 2 +- radio/src/targets/taranis/i2c.c | 19 +++---- radio/src/targets/taranis/i2c.h | 10 +++- .../src/targets/taranis/usbd_storage_msd.cpp | 2 +- 14 files changed, 70 insertions(+), 129 deletions(-) delete mode 100644 radio/bootloader/include/aspi.h delete mode 100644 radio/bootloader/include/i2c_ee.h rename radio/src/targets/taranis/{aspi.cpp => aspi.c} (88%) rename radio/src/targets/taranis/{delays.cpp => delays.c} (94%) diff --git a/radio/bootloader/Makefile b/radio/bootloader/Makefile index e0de909ff..adebf731c 100644 --- a/radio/bootloader/Makefile +++ b/radio/bootloader/Makefile @@ -112,6 +112,8 @@ UADEFS = ifeq ($(PCB), TARANIS) SRC = system_stm32f2xx.c \ + ../src/targets/taranis/i2c.c \ + ../src/targets/taranis/delays.c \ ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rcc.c \ ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_gpio.c \ ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_spi.c \ @@ -128,17 +130,16 @@ SRC = system_stm32f2xx.c \ ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_bot.c \ ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_core.c \ ../src/targets/taranis/usbd_desc.c \ + ../src/targets/taranis/aspi.c \ ../src/targets/taranis/usb_bsp.c -CPPSRC = ../src/targets/taranis/aspi.cpp \ - lcd_driver.cpp \ +CPPSRC = lcd_driver.cpp \ driversboot.cpp \ logicioboot.cpp \ ff.cpp \ x9ddiskio.cpp \ ../src/targets/taranis/usbd_usr.cpp \ usbd_storage_msd.cpp \ - i2c_ee.cpp \ lcdboot.cpp \ power.cpp \ boot.cpp diff --git a/radio/bootloader/boot.cpp b/radio/bootloader/boot.cpp index 26d320632..9305a9064 100644 --- a/radio/bootloader/boot.cpp +++ b/radio/bootloader/boot.cpp @@ -61,7 +61,7 @@ #ifdef PCBTARANIS #include "stm32f2xx.h" #include "stm32f2xx_flash.h" -#include "i2c_ee.h" +#include "../src/targets/taranis/i2c.h" #include "hal.h" #include "timers.h" diff --git a/radio/bootloader/include/aspi.h b/radio/bootloader/include/aspi.h deleted file mode 100644 index 36c354311..000000000 --- a/radio/bootloader/include/aspi.h +++ /dev/null @@ -1,37 +0,0 @@ -/** - ****************************************************************************** - * @file Project/spi/spi.h - * @author X9D Application Team - * @Hardware version V0.2 - * @date 11-July-2012 - * @brief spi.c' Header file. - * * - ****************************************************************************** -*/ -#ifndef _ASPI_H_ -#define _ASPI_H_ - -#include "stm32f2xx.h" - -#define LCD_NCS_HIGH() (GPIO_LCD->BSRRL = PIN_LCD_NCS) -#define LCD_NCS_LOW() (GPIO_LCD->BSRRH = PIN_LCD_NCS) - -#define LCD_A0_HIGH() (GPIO_LCD->BSRRL = PIN_LCD_A0) -#define LCD_A0_LOW() (GPIO_LCD->BSRRH = PIN_LCD_A0) - -#define LCD_RST_HIGH() (GPIO_LCD->BSRRL = PIN_LCD_RST) -#define LCD_RST_LOW() (GPIO_LCD->BSRRH = PIN_LCD_RST) - -#define LCD_CLK_HIGH() (GPIO_LCD->BSRRL = PIN_LCD_CLK) -#define LCD_CLK_LOW() (GPIO_LCD->BSRRH = PIN_LCD_CLK) - -#define LCD_MOSI_HIGH() (GPIO_LCD->BSRRL = PIN_LCD_MOSI) -#define LCD_MOSI_LOW() (GPIO_LCD->BSRRH = PIN_LCD_MOSI) - - -void AspiCmd(u8 Command_Byte); -void AspiData(u8 Para_data); -//u16 spiRegAccess(u8 addrByte, u8 writeValue); - -#endif - diff --git a/radio/bootloader/include/i2c_ee.h b/radio/bootloader/include/i2c_ee.h deleted file mode 100644 index 8e2f45d08..000000000 --- a/radio/bootloader/include/i2c_ee.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - ****************************************************************************** - * @file Project/ee_drivers/i2c_ee.h - * @author X9D Application Team - * @version V 0.2 - * @date 12-JLY-2012 - * @brief Header for i2c_ee.c module - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion ------------------------------------ */ -#ifndef __I2C_EE_H -#define __I2C_EE_H - -#define EE_CMD_WRITE (0) -#define EE_CMD_READ (1) -//#define I2C_delay() //do { delayUsec(5); } while(0) - -#define SCL_H do{I2C_EE_GPIO->BSRRL = I2C_EE_SCL;}while(0) -#define SCL_L do{I2C_EE_GPIO->BSRRH = I2C_EE_SCL;}while(0) -#define SDA_H do{I2C_EE_GPIO->BSRRL = I2C_EE_SDA;}while(0) -#define SDA_L do{I2C_EE_GPIO->BSRRH = I2C_EE_SDA;}while(0) -#define SCL_read (I2C_EE_GPIO->IDR & I2C_EE_SCL) -#define SDA_read (I2C_EE_GPIO->IDR & I2C_EE_SDA) -#define WP_H do{I2C_EE_WP_GPIO->BSRRL = I2C_EE_WP;}while(0) -#define WP_L do{I2C_EE_WP_GPIO->BSRRH = I2C_EE_WP;}while(0) - - -/* Exported functions ------------------------------------------------------- */ -void I2C_EE_Init(void); -void I2C_EE_ByteWrite(uint8_t* pBuffer, uint16_t WriteAddr); -void I2C_EE_PageWrite(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t NumByteToWrite); -void I2C_EE_BufferWrite(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite); -void I2C_EE_BufferRead(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t NumByteToRead); -void I2C_EE_WaitEepromStandbyState(void); -void I2C_set_volume( uint8_t volume ) ; -uint8_t I2C_read_volume( void ) ; - -#endif /* __I2C_EE_H */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ - diff --git a/radio/bootloader/lcd_driver.cpp b/radio/bootloader/lcd_driver.cpp index 839c9a5cc..dd36230db 100644 --- a/radio/bootloader/lcd_driver.cpp +++ b/radio/bootloader/lcd_driver.cpp @@ -15,7 +15,7 @@ #include "stm32f2xx_gpio.h" #include "stm32f2xx_rcc.h" #include "hal.h" -#include "aspi.h" +#include "../src/targets/taranis/aspi.h" #include "timers.h" #include "lcd.h" @@ -268,7 +268,7 @@ static void LCD_Init() AspiCmd(0xF7); //ending row address of RAM program window. AspiCmd(0x9F); - AspiCmd(0xAF); //dc2=1,IC into exit SLEEP MODE, dc3=1 gray=ON ҽ ,dc4=1 Green Enhanc mode disabled ɫǿģʽ + AspiCmd(0xAF); //dc2=1,IC into exit SLEEP MODE, dc3=1 gray=ON ���ҽ� ,dc4=1 Green Enhanc mode disabled ��ɫ��ǿģʽ�� } diff --git a/radio/bootloader/usbd_storage_msd.cpp b/radio/bootloader/usbd_storage_msd.cpp index b26490086..0f150a750 100644 --- a/radio/bootloader/usbd_storage_msd.cpp +++ b/radio/bootloader/usbd_storage_msd.cpp @@ -32,7 +32,7 @@ #include //#include #include "drivers.h" -#include "i2c_ee.h" +#include "../src/targets/taranis/i2c.h" #include "diskio.h" //#include "board_taranis.h" diff --git a/radio/src/Makefile b/radio/src/Makefile index eb132116e..b583e8868 100644 --- a/radio/src/Makefile +++ b/radio/src/Makefile @@ -636,12 +636,12 @@ ifeq ($(PCB), TARANIS) EXTRAINCDIRS += targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/inc targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Core/inc EXTRAINCDIRS += targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/inc targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/hid/inc BOARDSRC = targets/taranis/board_taranis.cpp - EXTRABOARDSRC += targets/taranis/lcd_driver.cpp targets/taranis/aspi.cpp targets/taranis/i2c.c + EXTRABOARDSRC += targets/taranis/lcd_driver.cpp targets/taranis/aspi.c targets/taranis/i2c.c targets/taranis/delays.c SRC += CoOS/kernel/core.c CoOS/kernel/hook.c CoOS/kernel/task.c CoOS/kernel/event.c CoOS/kernel/time.c CoOS/kernel/timer.c CoOS/kernel/flag.c CoOS/kernel/mutex.c CoOS/kernel/serviceReq.c CoOS/portable/GCC/port.c CoOS/portable/arch.c EEPROMSRC = eeprom_common.cpp eeprom_rlc.cpp eeprom_conversions.cpp PULSESSRC = protocols/pulses_arm.cpp protocols/ppm_arm.cpp protocols/pxx_arm.cpp CPPSRC += audio_arm.cpp - CPPSRC += targets/taranis/pwr_driver.cpp targets/taranis/pulses_driver.cpp targets/taranis/keys_driver.cpp targets/taranis/adc_driver.cpp targets/taranis/trainer_driver.cpp targets/taranis/audio_driver.cpp targets/taranis/delays.cpp targets/taranis/uart3_driver.cpp targets/taranis/sport_driver.cpp + CPPSRC += targets/taranis/pwr_driver.cpp targets/taranis/pulses_driver.cpp targets/taranis/keys_driver.cpp targets/taranis/adc_driver.cpp targets/taranis/trainer_driver.cpp targets/taranis/audio_driver.cpp targets/taranis/uart3_driver.cpp targets/taranis/sport_driver.cpp CPPSRC += bmp.cpp gui/view_channels.cpp gui/view_about.cpp gui/view_text.cpp SRC += targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c SRC += targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/misc.c diff --git a/radio/src/targets/taranis/aspi.cpp b/radio/src/targets/taranis/aspi.c similarity index 88% rename from radio/src/targets/taranis/aspi.cpp rename to radio/src/targets/taranis/aspi.c index 5aa1487a6..f75cb4a02 100644 --- a/radio/src/targets/taranis/aspi.cpp +++ b/radio/src/targets/taranis/aspi.c @@ -10,8 +10,7 @@ ****************************************************************************** */ -#include "../../opentx.h" -#include "./STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_gpio.h" +#include "board_taranis.h" /** **********send command to lcd************** diff --git a/radio/src/targets/taranis/aspi.h b/radio/src/targets/taranis/aspi.h index cd42e7eb6..a3f4f829f 100644 --- a/radio/src/targets/taranis/aspi.h +++ b/radio/src/targets/taranis/aspi.h @@ -11,6 +11,10 @@ #ifndef _ASPI_H_ #define _ASPI_H_ +#ifdef __cplusplus +extern "C" { +#endif + #include "./STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" #define __no_operation __NOP @@ -33,5 +37,9 @@ void AspiCmd(u8 Command_Byte); void AspiData(u8 Para_data); +#ifdef __cplusplus +} +#endif + #endif diff --git a/radio/src/targets/taranis/board_taranis.h b/radio/src/targets/taranis/board_taranis.h index 4bbd2fde0..64e437b12 100644 --- a/radio/src/targets/taranis/board_taranis.h +++ b/radio/src/targets/taranis/board_taranis.h @@ -45,17 +45,28 @@ #include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dma.h" #include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_usart.h" #include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" + +#ifdef __cplusplus extern "C" { +#endif + #include "STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_core.h" #include "STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_usr.h" #include "usbd_desc.h" #include "usb_conf.h" #include "usbd_conf.h" -} + #include "hal.h" #include "aspi.h" #include "i2c.h" + +#ifdef __cplusplus +} +#endif + +#if !defined(BOOT) #include "audio_driver.h" +#endif #define PERI1_FREQUENCY 30000000 #define PERI2_FREQUENCY 60000000 @@ -97,11 +108,11 @@ void delay_01us(uint16_t nb); #define SD_GET_SIZE_MB() (0) #define SD_GET_BLOCKNR() (0) #define SD_GET_SPEED() (0) - void sdInit(); - void sdDone(); - void sdPoll10ms(); + void sdInit(void); + void sdDone(void); + void sdPoll10ms(void); #define sdMountPoll() - uint32_t sdMounted(); + uint32_t sdMounted(void); #define SD_CARD_PRESENT() (~SD_PRESENT_GPIO->IDR & SD_PRESENT_GPIO_Pin) #endif @@ -116,15 +127,15 @@ void init_dsm2( uint32_t module_index ); void disable_dsm2( uint32_t module_index ); // Trainer driver -void init_trainer_ppm(); -void stop_trainer_ppm(); -void init_trainer_capture(); -void stop_trainer_capture(); +void init_trainer_ppm(void); +void stop_trainer_ppm(void); +void init_trainer_capture(void); +void stop_trainer_capture(void); // Keys driver -void keysInit(); -uint32_t readKeys(); -uint32_t readTrims(); +void keysInit(void); +uint32_t readKeys(void); +uint32_t readTrims(void); #define TRIMS_PRESSED() (readTrims()) #define KEYS_PRESSED() (~readKeys()) #define DBLKEYS_PRESSED_RGT_LFT(i) ((in & ((2<CCR1 = 0 #define IS_BACKLIGHT_ON() (TIM10->CCR1 != 0) +#if !defined(BOOT) // USB driver #define BOOTLOADER_REQUEST() (0) #define usbBootloader() void usbInit(void); void usbStart(void); bool usbPlugged(void); +#endif // EEPROM driver #if !defined(SIMU) diff --git a/radio/src/targets/taranis/delays.cpp b/radio/src/targets/taranis/delays.c similarity index 94% rename from radio/src/targets/taranis/delays.cpp rename to radio/src/targets/taranis/delays.c index 256f431ed..756db1ed7 100644 --- a/radio/src/targets/taranis/delays.cpp +++ b/radio/src/targets/taranis/delays.c @@ -34,7 +34,7 @@ * */ -#include "../../opentx.h" +#include "board_taranis.h" void delaysInit(void) { diff --git a/radio/src/targets/taranis/i2c.c b/radio/src/targets/taranis/i2c.c index df9b616c4..91bd70cbe 100644 --- a/radio/src/targets/taranis/i2c.c +++ b/radio/src/targets/taranis/i2c.c @@ -10,7 +10,7 @@ ****************************************************************************** */ -#include "../opentx.h" +#include "board_taranis.h" #define I2C_delay() delay_01us(100); @@ -44,7 +44,7 @@ static void I2C_GPIO_Configuration(void) SCL_H; } -short I2C_START() +short I2C_START(void) { SDA_H; I2C_delay(); @@ -59,7 +59,7 @@ short I2C_START() return 1; } -void I2C_STOP() +void I2C_STOP(void) { SCL_L; I2C_delay(); @@ -71,7 +71,7 @@ void I2C_STOP() I2C_delay(); } -void I2C_ACK() +void I2C_ACK(void) { SCL_L; I2C_delay(); @@ -82,7 +82,8 @@ void I2C_ACK() SCL_L; I2C_delay(); } -void I2C_NO_ACK() + +void I2C_NO_ACK(void) { SCL_L; I2C_delay(); @@ -94,7 +95,7 @@ void I2C_NO_ACK() I2C_delay(); } -short I2C_WAIT_ACK() +short I2C_WAIT_ACK(void) { short i=50; SCL_L; @@ -103,7 +104,7 @@ short I2C_WAIT_ACK() I2C_delay(); SCL_H; I2C_delay(); - while(i) { + while (i) { if(SDA_read) { I2C_delay(); i--; @@ -138,7 +139,7 @@ void I2C_SEND_DATA(char SendByte) I2C_delay(); } -char I2C_READ() +char I2C_READ(void) { short i=8; char ReceiveByte=0; @@ -158,7 +159,7 @@ char I2C_READ() return ReceiveByte; } -void I2C_EE_Init() +void I2C_EE_Init(void) { /* GPIO Periph clock enable */ RCC_AHB1PeriphClockCmd(I2C_EE_GPIO_CLK, ENABLE); diff --git a/radio/src/targets/taranis/i2c.h b/radio/src/targets/taranis/i2c.h index b872dbc7f..75f75e7e2 100644 --- a/radio/src/targets/taranis/i2c.h +++ b/radio/src/targets/taranis/i2c.h @@ -33,6 +33,10 @@ #define WP_H do{I2C_EE_WP_GPIO->BSRRL = I2C_EE_WP;}while(0) #define WP_L do{I2C_EE_WP_GPIO->BSRRH = I2C_EE_WP;}while(0) +#ifdef __cplusplus +extern "C" { +#endif + /* Exported functions ------------------------------------------------------- */ void I2C_EE_Init(void); void I2C_EE_ByteWrite(uint8_t* pBuffer, uint16_t WriteAddr); @@ -42,7 +46,11 @@ void I2C_EE_BufferRead(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t NumByteToRe void I2C_EE_WaitEepromStandbyState(void); void I2C_set_volume(register uint8_t volume); -uint8_t I2C_read_volume(); +uint8_t I2C_read_volume(void); + +#ifdef __cplusplus +} +#endif #endif /* __I2C_EE_H */ diff --git a/radio/src/targets/taranis/usbd_storage_msd.cpp b/radio/src/targets/taranis/usbd_storage_msd.cpp index a11301c1e..e9c4dff58 100644 --- a/radio/src/targets/taranis/usbd_storage_msd.cpp +++ b/radio/src/targets/taranis/usbd_storage_msd.cpp @@ -35,7 +35,7 @@ extern "C" { #include "usbd_msc_mem.h" #include "usb_conf.h" -void eeprom_read_block (void *pointer_ram, uint16_t pointer_eeprom, size_t size); +// void eeprom_read_block (void *pointer_ram, uint16_t pointer_eeprom, size_t size); #define STORAGE_LUN_NBR 2 #define BLOCKSIZE 512 From 74872b13229f35ab277692e55280299cbe34de43 Mon Sep 17 00:00:00 2001 From: bsongis Date: Tue, 4 Mar 2014 15:58:01 +0100 Subject: [PATCH 020/285] 18 more files removed --- radio/bootloader/Makefile | 4 + radio/bootloader/include/usb_bsp.h | 102 -- radio/bootloader/include/usb_conf.h | 175 --- radio/bootloader/include/usb_core.h | 417 ------ radio/bootloader/include/usb_dcd.h | 163 --- radio/bootloader/include/usb_dcd_int.h | 127 -- radio/bootloader/include/usb_defines.h | 249 ---- radio/bootloader/include/usb_regs.h | 1188 ----------------- radio/bootloader/include/usbd_conf.h | 54 - radio/bootloader/include/usbd_core.h | 120 -- radio/bootloader/include/usbd_def.h | 156 --- radio/bootloader/include/usbd_ioreq.h | 121 -- radio/bootloader/include/usbd_msc_bot.h | 153 --- radio/bootloader/include/usbd_msc_core.h | 77 -- radio/bootloader/include/usbd_msc_data.h | 104 -- radio/bootloader/include/usbd_msc_mem.h | 112 -- radio/bootloader/include/usbd_msc_scsi.h | 195 --- radio/bootloader/include/usbd_req.h | 108 -- radio/bootloader/include/usbd_usr.h | 141 -- .../src/targets/taranis/usbd_storage_msd.cpp | 2 - 20 files changed, 4 insertions(+), 3764 deletions(-) delete mode 100644 radio/bootloader/include/usb_bsp.h delete mode 100644 radio/bootloader/include/usb_conf.h delete mode 100644 radio/bootloader/include/usb_core.h delete mode 100644 radio/bootloader/include/usb_dcd.h delete mode 100644 radio/bootloader/include/usb_dcd_int.h delete mode 100644 radio/bootloader/include/usb_defines.h delete mode 100644 radio/bootloader/include/usb_regs.h delete mode 100644 radio/bootloader/include/usbd_conf.h delete mode 100644 radio/bootloader/include/usbd_core.h delete mode 100644 radio/bootloader/include/usbd_def.h delete mode 100644 radio/bootloader/include/usbd_ioreq.h delete mode 100644 radio/bootloader/include/usbd_msc_bot.h delete mode 100644 radio/bootloader/include/usbd_msc_core.h delete mode 100644 radio/bootloader/include/usbd_msc_data.h delete mode 100644 radio/bootloader/include/usbd_msc_mem.h delete mode 100644 radio/bootloader/include/usbd_msc_scsi.h delete mode 100644 radio/bootloader/include/usbd_req.h delete mode 100644 radio/bootloader/include/usbd_usr.h diff --git a/radio/bootloader/Makefile b/radio/bootloader/Makefile index adebf731c..50e327181 100644 --- a/radio/bootloader/Makefile +++ b/radio/bootloader/Makefile @@ -101,6 +101,10 @@ else EXTRAINCDIRS += include EXTRAINCDIRS += ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc EXTRAINCDIRS += ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include + EXTRAINCDIRS += ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/inc + EXTRAINCDIRS += ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Core/inc + EXTRAINCDIRS += ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/inc + EXTRAINCDIRS += ../src/targets/taranis endif endif diff --git a/radio/bootloader/include/usb_bsp.h b/radio/bootloader/include/usb_bsp.h deleted file mode 100644 index 4a60bcff6..000000000 --- a/radio/bootloader/include/usb_bsp.h +++ /dev/null @@ -1,102 +0,0 @@ -/** - ****************************************************************************** - * @file usb_bsp.h - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief Specific api's relative to the used hardware platform - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_BSP__H__ -#define __USB_BSP__H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_core.h" - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_BSP - * @brief This file is the - * @{ - */ - - -/** @defgroup USB_BSP_Exported_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_BSP_Exported_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_BSP_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_BSP_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_BSP_Exported_FunctionsPrototype - * @{ - */ -void BSP_Init(void); - -void USB_OTG_BSP_Init (USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_BSP_uDelay (const uint32_t usec); -void USB_OTG_BSP_mDelay (const uint32_t msec); -void USB_OTG_BSP_EnableInterrupt (USB_OTG_CORE_HANDLE *pdev); -#ifdef USE_HOST_MODE -void USB_OTG_BSP_ConfigVBUS(USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_BSP_DriveVBUS(USB_OTG_CORE_HANDLE *pdev,uint8_t state); -#endif -/** - * @} - */ - -#endif //__USB_BSP__H__ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/radio/bootloader/include/usb_conf.h b/radio/bootloader/include/usb_conf.h deleted file mode 100644 index 5e6d787a6..000000000 --- a/radio/bootloader/include/usb_conf.h +++ /dev/null @@ -1,175 +0,0 @@ -/** - ****************************************************************************** - * @file usb_conf.h - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief General low level driver configuration - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_CONF__H__ -#define __USB_CONF__H__ - -#include "stm32f2xx.h" - -#define HID_IN_EP 0x81 -#define HID_OUT_EP 0x01 - -#define HID_IN_PACKET 4 -#define HID_OUT_PACKET 4 - -/* USB Core and PHY interface configuration. - Tip: To avoid modifying these defines each time you need to change the USB - configuration, you can declare the needed define in your toolchain - compiler preprocessor. - */ -/****************** USB OTG FS PHY CONFIGURATION ******************************* -* The USB OTG FS Core supports one on-chip Full Speed PHY. -* -* The USE_EMBEDDED_PHY symbol is defined in the project compiler preprocessor -* when FS core is used. -*******************************************************************************/ -#ifndef USE_USB_OTG_FS - #define USE_USB_OTG_FS -#endif /* USE_USB_OTG_FS */ - -#ifdef USE_USB_OTG_FS - #define USB_OTG_FS_CORE -#endif - -/******************************************************************************* -* FIFO Size Configuration in Device mode -* -* (i) Receive data FIFO size = RAM for setup packets + -* OUT endpoint control information + -* data OUT packets + miscellaneous -* Space = ONE 32-bits words -* --> RAM for setup packets = 10 spaces -* (n is the nbr of CTRL EPs the device core supports) -* --> OUT EP CTRL info = 1 space -* (one space for status information written to the FIFO along with each -* received packet) -* --> data OUT packets = (Largest Packet Size / 4) + 1 spaces -* (MINIMUM to receive packets) -* --> OR data OUT packets = at least 2*(Largest Packet Size / 4) + 1 spaces -* (if high-bandwidth EP is enabled or multiple isochronous EPs) -* --> miscellaneous = 1 space per OUT EP -* (one space for transfer complete status information also pushed to the -* FIFO with each endpoint's last packet) -* -* (ii)MINIMUM RAM space required for each IN EP Tx FIFO = MAX packet size for -* that particular IN EP. More space allocated in the IN EP Tx FIFO results -* in a better performance on the USB and can hide latencies on the AHB. -* -* (iii) TXn min size = 16 words. (n : Transmit FIFO index) -* (iv) When a TxFIFO is not used, the Configuration should be as follows: -* case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) -* --> Txm can use the space allocated for Txn. -* case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) -* --> Txn should be configured with the minimum space of 16 words -* (v) The FIFO is used optimally when used TxFIFOs are allocated in the top -* of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. -* (vi) In HS case12 FIFO locations should be reserved for internal DMA registers -* so total FIFO size should be 1012 Only instead of 1024 -*******************************************************************************/ - -/****************** USB OTG FS CONFIGURATION **********************************/ -#ifdef USB_OTG_FS_CORE - #define RX_FIFO_FS_SIZE 128 - #define TX0_FIFO_FS_SIZE 64 - #define TX1_FIFO_FS_SIZE 128 - #define TX2_FIFO_FS_SIZE 0 - #define TX3_FIFO_FS_SIZE 0 - -// #define USB_OTG_FS_LOW_PWR_MGMT_SUPPORT -// #define USB_OTG_FS_SOF_OUTPUT_ENABLED -#endif - -/****************** USB OTG MISC CONFIGURATION ********************************/ -#define VBUS_SENSING_ENABLED - -/****************** USB OTG MODE CONFIGURATION ********************************/ -//#define USE_HOST_MODE -#define USE_DEVICE_MODE -//#define USE_OTG_MODE - -#ifndef USB_OTG_FS_CORE - #ifndef USB_OTG_HS_CORE - #error "USB_OTG_HS_CORE or USB_OTG_FS_CORE should be defined" - #endif -#endif - -#ifndef USE_DEVICE_MODE - #ifndef USE_HOST_MODE - #error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" - #endif -#endif - -#ifndef USE_USB_OTG_HS - #ifndef USE_USB_OTG_FS - #error "USE_USB_OTG_HS or USE_USB_OTG_FS should be defined" - #endif -#else //USE_USB_OTG_HS - #ifndef USE_ULPI_PHY - #ifndef USE_EMBEDDED_PHY - #error "USE_ULPI_PHY or USE_EMBEDDED_PHY should be defined" - #endif - #endif -#endif - -/****************** C Compilers dependant keywords ****************************/ -/* In HS mode and when the DMA is used, all variables and data structures dealing - with the DMA during the transaction process should be 4-bytes aligned */ -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined (__GNUC__) /* GNU Compiler */ - #define __ALIGN_END __attribute__ ((aligned (4))) - #define __ALIGN_BEGIN - #else - #define __ALIGN_END - #if defined (__CC_ARM) /* ARM Compiler */ - #define __ALIGN_BEGIN __align(4) - #elif defined (__ICCARM__) /* IAR Compiler */ - #define __ALIGN_BEGIN - #elif defined (__TASKING__) /* TASKING Compiler */ - #define __ALIGN_BEGIN __align(4) - #endif /* __CC_ARM */ - #endif /* __GNUC__ */ -#else - #define __ALIGN_BEGIN - #define __ALIGN_END -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ - -/* __packed keyword used to decrease the data type alignment to 1-byte */ -#if defined (__CC_ARM) /* ARM Compiler */ - #define __packed __packed -#elif defined (__ICCARM__) /* IAR Compiler */ - #define __packed __packed -#elif defined ( __GNUC__ ) /* GNU Compiler */ - #define __packed __attribute__ ((__packed__)) -#elif defined (__TASKING__) /* TASKING Compiler */ - #define __packed __unaligned -#endif /* __CC_ARM */ - -#endif //__USB_CONF__H__ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/radio/bootloader/include/usb_core.h b/radio/bootloader/include/usb_core.h deleted file mode 100644 index 55e0fca82..000000000 --- a/radio/bootloader/include/usb_core.h +++ /dev/null @@ -1,417 +0,0 @@ -/** - ****************************************************************************** - * @file usb_core.h - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief Header of the Core Layer - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_CORE_H__ -#define __USB_CORE_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" -#include "usb_regs.h" -#include "usb_defines.h" - - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_CORE - * @brief usb otg driver core layer - * @{ - */ - - -/** @defgroup USB_CORE_Exported_Defines - * @{ - */ - -#define USB_OTG_EP0_IDLE 0 -#define USB_OTG_EP0_SETUP 1 -#define USB_OTG_EP0_DATA_IN 2 -#define USB_OTG_EP0_DATA_OUT 3 -#define USB_OTG_EP0_STATUS_IN 4 -#define USB_OTG_EP0_STATUS_OUT 5 -#define USB_OTG_EP0_STALL 6 - -#define USB_OTG_EP_TX_DIS 0x0000 -#define USB_OTG_EP_TX_STALL 0x0010 -#define USB_OTG_EP_TX_NAK 0x0020 -#define USB_OTG_EP_TX_VALID 0x0030 - -#define USB_OTG_EP_RX_DIS 0x0000 -#define USB_OTG_EP_RX_STALL 0x1000 -#define USB_OTG_EP_RX_NAK 0x2000 -#define USB_OTG_EP_RX_VALID 0x3000 -/** - * @} - */ -#define MAX_DATA_LENGTH 0x200 - -/** @defgroup USB_CORE_Exported_Types - * @{ - */ - - -typedef enum { - USB_OTG_OK = 0, - USB_OTG_FAIL -}USB_OTG_STS; - -typedef enum { - HC_IDLE = 0, - HC_XFRC, - HC_HALTED, - HC_NAK, - HC_NYET, - HC_STALL, - HC_XACTERR, - HC_BBLERR, - HC_DATATGLERR, -}HC_STATUS; - -typedef enum { - URB_IDLE = 0, - URB_DONE, - URB_NOTREADY, - URB_ERROR, - URB_STALL -}URB_STATE; - -typedef enum { - CTRL_START = 0, - CTRL_XFRC, - CTRL_HALTED, - CTRL_NAK, - CTRL_STALL, - CTRL_XACTERR, - CTRL_BBLERR, - CTRL_DATATGLERR, - CTRL_FAIL -}CTRL_STATUS; - - -typedef struct USB_OTG_hc -{ - uint8_t dev_addr ; - uint8_t ep_num; - uint8_t ep_is_in; - uint8_t speed; - uint8_t do_ping; - uint8_t ep_type; - uint16_t max_packet; - uint8_t data_pid; - uint8_t *xfer_buff; - uint32_t xfer_len; - uint32_t xfer_count; - uint8_t toggle_in; - uint8_t toggle_out; - uint32_t dma_addr; -} -USB_OTG_HC , *PUSB_OTG_HC; - -typedef struct USB_OTG_ep -{ - uint8_t num; - uint8_t is_in; - uint8_t is_stall; - uint8_t type; - uint8_t data_pid_start; - uint8_t even_odd_frame; - uint16_t tx_fifo_num; - uint32_t maxpacket; - /* transaction level variables*/ - uint8_t *xfer_buff; - uint32_t dma_addr; - uint32_t xfer_len; - uint32_t xfer_count; - /* Transfer level variables*/ - uint32_t rem_data_len; - uint32_t total_data_len; - uint32_t ctl_data_len; - -} - -USB_OTG_EP , *PUSB_OTG_EP; - - - -typedef struct USB_OTG_core_cfg -{ - uint8_t host_channels; - uint8_t dev_endpoints; - uint8_t speed; - uint8_t dma_enable; - uint16_t mps; - uint16_t TotalFifoSize; - uint8_t phy_itface; - uint8_t Sof_output; - uint8_t low_power; - uint8_t coreID; - -} -USB_OTG_CORE_CFGS, *PUSB_OTG_CORE_CFGS; - - - -typedef struct usb_setup_req { - - uint8_t bmRequest; - uint8_t bRequest; - uint16_t wValue; - uint16_t wIndex; - uint16_t wLength; -} USB_SETUP_REQ; - -typedef struct _Device_TypeDef -{ - uint8_t *(*GetDeviceDescriptor)( uint8_t speed , uint16_t *length); - uint8_t *(*GetLangIDStrDescriptor)( uint8_t speed , uint16_t *length); - uint8_t *(*GetManufacturerStrDescriptor)( uint8_t speed , uint16_t *length); - uint8_t *(*GetProductStrDescriptor)( uint8_t speed , uint16_t *length); - uint8_t *(*GetSerialStrDescriptor)( uint8_t speed , uint16_t *length); - uint8_t *(*GetConfigurationStrDescriptor)( uint8_t speed , uint16_t *length); - uint8_t *(*GetInterfaceStrDescriptor)( uint8_t speed , uint16_t *length); -} USBD_DEVICE, *pUSBD_DEVICE; - -//typedef struct USB_OTG_hPort -//{ -// void (*Disconnect) (void *phost); -// void (*Connect) (void *phost); -// uint8_t ConnStatus; -// uint8_t DisconnStatus; -// uint8_t ConnHandled; -// uint8_t DisconnHandled; -//} USB_OTG_hPort_TypeDef; - -typedef struct _Device_cb -{ - uint8_t (*Init) (void *pdev , uint8_t cfgidx); - uint8_t (*DeInit) (void *pdev , uint8_t cfgidx); - /* Control Endpoints*/ - uint8_t (*Setup) (void *pdev , USB_SETUP_REQ *req); - uint8_t (*EP0_TxSent) (void *pdev ); - uint8_t (*EP0_RxReady) (void *pdev ); - /* Class Specific Endpoints*/ - uint8_t (*DataIn) (void *pdev , uint8_t epnum); - uint8_t (*DataOut) (void *pdev , uint8_t epnum); - uint8_t (*SOF) (void *pdev); - uint8_t (*IsoINIncomplete) (void *pdev); - uint8_t (*IsoOUTIncomplete) (void *pdev); - - uint8_t *(*GetConfigDescriptor)( uint8_t speed , uint16_t *length); -#ifdef USB_OTG_HS_CORE - uint8_t *(*GetOtherConfigDescriptor)( uint8_t speed , uint16_t *length); -#endif - -#ifdef USB_SUPPORT_USER_STRING_DESC - uint8_t *(*GetUsrStrDescriptor)( uint8_t speed ,uint8_t index, uint16_t *length); -#endif - -} USBD_Class_cb_TypeDef; - - - -typedef struct _USBD_USR_PROP -{ - void (*Init)(void); - void (*DeviceReset)(uint8_t speed); - void (*DeviceConfigured)(void); - void (*DeviceSuspended)(void); - void (*DeviceResumed)(void); - - void (*DeviceConnected)(void); - void (*DeviceDisconnected)(void); - -} -USBD_Usr_cb_TypeDef; - -typedef struct _DCD -{ - uint8_t device_config; - uint8_t device_state; - uint8_t device_status; - uint8_t device_old_status; - uint8_t device_address; - uint8_t connection_status; - uint8_t test_mode; - uint32_t DevRemoteWakeup; - USB_OTG_EP in_ep [USB_OTG_MAX_TX_FIFOS]; - USB_OTG_EP out_ep [USB_OTG_MAX_TX_FIFOS]; - uint8_t setup_packet [8*3]; - USBD_Class_cb_TypeDef *class_cb; - USBD_Usr_cb_TypeDef *usr_cb; - USBD_DEVICE *usr_device; - uint8_t *pConfig_descriptor; - } -DCD_DEV , *DCD_PDEV; - - -typedef struct _HCD -{ - uint8_t Rx_Buffer [MAX_DATA_LENGTH]; - __IO uint32_t ConnSts; - __IO uint32_t ErrCnt[USB_OTG_MAX_TX_FIFOS]; - __IO uint32_t XferCnt[USB_OTG_MAX_TX_FIFOS]; - __IO HC_STATUS HC_Status[USB_OTG_MAX_TX_FIFOS]; - __IO URB_STATE URB_State[USB_OTG_MAX_TX_FIFOS]; - USB_OTG_HC hc [USB_OTG_MAX_TX_FIFOS]; - uint16_t channel [USB_OTG_MAX_TX_FIFOS]; -// USB_OTG_hPort_TypeDef *port_cb; -} -HCD_DEV , *USB_OTG_USBH_PDEV; - - -typedef struct _OTG -{ - uint8_t OTG_State; - uint8_t OTG_PrevState; - uint8_t OTG_Mode; -} -OTG_DEV , *USB_OTG_USBO_PDEV; - -typedef struct USB_OTG_handle -{ - USB_OTG_CORE_CFGS cfg; - USB_OTG_CORE_REGS regs; -#ifdef USE_DEVICE_MODE - DCD_DEV dev; -#endif -#ifdef USE_HOST_MODE - HCD_DEV host; -#endif -#ifdef USE_OTG_MODE - OTG_DEV otg; -#endif -} -USB_OTG_CORE_HANDLE , *PUSB_OTG_CORE_HANDLE; - -/** - * @} - */ - - -/** @defgroup USB_CORE_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USB_CORE_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_CORE_Exported_FunctionsPrototype - * @{ - */ - - -USB_OTG_STS USB_OTG_CoreInit (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_SelectCore (USB_OTG_CORE_HANDLE *pdev, - USB_OTG_CORE_ID_TypeDef coreID); -USB_OTG_STS USB_OTG_EnableGlobalInt (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_DisableGlobalInt(USB_OTG_CORE_HANDLE *pdev); -void* USB_OTG_ReadPacket (USB_OTG_CORE_HANDLE *pdev , - uint8_t *dest, - uint16_t len); -USB_OTG_STS USB_OTG_WritePacket (USB_OTG_CORE_HANDLE *pdev , - uint8_t *src, - uint8_t ch_ep_num, - uint16_t len); -USB_OTG_STS USB_OTG_FlushTxFifo (USB_OTG_CORE_HANDLE *pdev , uint32_t num); -USB_OTG_STS USB_OTG_FlushRxFifo (USB_OTG_CORE_HANDLE *pdev); - -uint32_t USB_OTG_ReadCoreItr (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_ReadOtgItr (USB_OTG_CORE_HANDLE *pdev); -uint8_t USB_OTG_IsHostMode (USB_OTG_CORE_HANDLE *pdev); -uint8_t USB_OTG_IsDeviceMode (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_GetMode (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_PhyInit (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_SetCurrentMode (USB_OTG_CORE_HANDLE *pdev, - uint8_t mode); - -/*********************** HOST APIs ********************************************/ -#ifdef USE_HOST_MODE -USB_OTG_STS USB_OTG_CoreInitHost (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_EnableHostInt (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_HC_Init (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num); -USB_OTG_STS USB_OTG_HC_Halt (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num); -USB_OTG_STS USB_OTG_HC_StartXfer (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num); -USB_OTG_STS USB_OTG_HC_DoPing (USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num); -uint32_t USB_OTG_ReadHostAllChannels_intr (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_ResetPort (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_ReadHPRT0 (USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_DriveVbus (USB_OTG_CORE_HANDLE *pdev, uint8_t state); -void USB_OTG_InitFSLSPClkSel (USB_OTG_CORE_HANDLE *pdev ,uint8_t freq); -uint8_t USB_OTG_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev) ; -void USB_OTG_StopHost (USB_OTG_CORE_HANDLE *pdev); -#endif -/********************* DEVICE APIs ********************************************/ -#ifdef USE_DEVICE_MODE -USB_OTG_STS USB_OTG_CoreInitDev (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_EnableDevInt (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_ReadDevAllInEPItr (USB_OTG_CORE_HANDLE *pdev); -enum USB_OTG_SPEED USB_OTG_GetDeviceSpeed (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_EP0Activate (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_EPActivate (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); -USB_OTG_STS USB_OTG_EPDeactivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); -USB_OTG_STS USB_OTG_EPStartXfer (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); -USB_OTG_STS USB_OTG_EP0StartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); -USB_OTG_STS USB_OTG_EPSetStall (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); -USB_OTG_STS USB_OTG_EPClearStall (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); -uint32_t USB_OTG_ReadDevAllOutEp_itr (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_ReadDevOutEP_itr (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); -uint32_t USB_OTG_ReadDevAllInEPItr (USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_InitDevSpeed (USB_OTG_CORE_HANDLE *pdev , uint8_t speed); -uint8_t USBH_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_EP0_OutStart(USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_ActiveRemoteWakeup(USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_UngateClock(USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_StopDevice(USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep , uint32_t Status); -uint32_t USB_OTG_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,USB_OTG_EP *ep); -#endif -/** - * @} - */ - -#endif /* __USB_CORE_H__ */ - - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/radio/bootloader/include/usb_dcd.h b/radio/bootloader/include/usb_dcd.h deleted file mode 100644 index 17e7f18ed..000000000 --- a/radio/bootloader/include/usb_dcd.h +++ /dev/null @@ -1,163 +0,0 @@ -/** - ****************************************************************************** - * @file usb_dcd.h - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief Peripheral Driver Header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __DCD_H__ -#define __DCD_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_core.h" - -/** @addtogroup USB_OTG_DRIVER -* @{ -*/ - -/** @defgroup USB_DCD -* @brief This file is the -* @{ -*/ - - -/** @defgroup USB_DCD_Exported_Defines -* @{ -*/ -#define USB_OTG_EP_CONTROL 0 -#define USB_OTG_EP_ISOC 1 -#define USB_OTG_EP_BULK 2 -#define USB_OTG_EP_INT 3 -#define USB_OTG_EP_MASK 3 - -/* Device Status */ -#define USB_OTG_DEFAULT 1 -#define USB_OTG_ADDRESSED 2 -#define USB_OTG_CONFIGURED 3 -#define USB_OTG_SUSPENDED 4 - -/** -* @} -*/ - - -/** @defgroup USB_DCD_Exported_Types -* @{ -*/ -/******************************************************************************** -Data structure type -********************************************************************************/ -typedef struct -{ - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bEndpointAddress; - uint8_t bmAttributes; - uint16_t wMaxPacketSize; - uint8_t bInterval; -} -EP_DESCRIPTOR , *PEP_DESCRIPTOR; - -/** -* @} -*/ - - -/** @defgroup USB_DCD_Exported_Macros -* @{ -*/ -/** -* @} -*/ - -/** @defgroup USB_DCD_Exported_Variables -* @{ -*/ -/** -* @} -*/ - -/** @defgroup USB_DCD_Exported_FunctionsPrototype -* @{ -*/ -/******************************************************************************** -EXPORTED FUNCTION FROM THE USB-OTG LAYER -********************************************************************************/ -void DCD_Init(USB_OTG_CORE_HANDLE *pdev , - USB_OTG_CORE_ID_TypeDef coreID); - -void DCD_DevConnect (USB_OTG_CORE_HANDLE *pdev); -void DCD_DevDisconnect (USB_OTG_CORE_HANDLE *pdev); -void DCD_EP_SetAddress (USB_OTG_CORE_HANDLE *pdev, - uint8_t address); -uint32_t DCD_EP_Open(USB_OTG_CORE_HANDLE *pdev , - uint8_t ep_addr, - uint16_t ep_mps, - uint8_t ep_type); - -uint32_t DCD_EP_Close (USB_OTG_CORE_HANDLE *pdev, - uint8_t ep_addr); - - -uint32_t DCD_EP_PrepareRx ( USB_OTG_CORE_HANDLE *pdev, - uint8_t ep_addr, - uint8_t *pbuf, - uint16_t buf_len); - -uint32_t DCD_EP_Tx (USB_OTG_CORE_HANDLE *pdev, - uint8_t ep_addr, - uint8_t *pbuf, - uint32_t buf_len); -uint32_t DCD_EP_Stall (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum); -uint32_t DCD_EP_ClrStall (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum); -uint32_t DCD_EP_Flush (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum); -uint32_t DCD_Handle_ISR(USB_OTG_CORE_HANDLE *pdev); - -uint32_t DCD_GetEPStatus(USB_OTG_CORE_HANDLE *pdev , - uint8_t epnum); - -void DCD_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , - uint8_t epnum , - uint32_t Status); - -/** -* @} -*/ - - -#endif //__DCD_H__ - - -/** -* @} -*/ - -/** -* @} -*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/radio/bootloader/include/usb_dcd_int.h b/radio/bootloader/include/usb_dcd_int.h deleted file mode 100644 index 69e525a26..000000000 --- a/radio/bootloader/include/usb_dcd_int.h +++ /dev/null @@ -1,127 +0,0 @@ -/** - ****************************************************************************** - * @file usb_dcd_int.h - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief Peripheral Device Interface Layer - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef USB_DCD_INT_H__ -#define USB_DCD_INT_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_dcd.h" - - - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_DCD_INT - * @brief This file is the - * @{ - */ - - -/** @defgroup USB_DCD_INT_Exported_Defines - * @{ - */ - -typedef struct _USBD_DCD_INT -{ - uint8_t (* DataOutStage) (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); - uint8_t (* DataInStage) (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); - uint8_t (* SetupStage) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* SOF) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* Reset) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* Suspend) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* Resume) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* IsoINIncomplete) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* IsoOUTIncomplete) (USB_OTG_CORE_HANDLE *pdev); - - uint8_t (* DevConnected) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* DevDisconnected) (USB_OTG_CORE_HANDLE *pdev); - -}USBD_DCD_INT_cb_TypeDef; - -extern USBD_DCD_INT_cb_TypeDef *USBD_DCD_INT_fops; -/** - * @} - */ - - -/** @defgroup USB_DCD_INT_Exported_Types - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_DCD_INT_Exported_Macros - * @{ - */ - -#define CLEAR_IN_EP_INTR(epnum,intr) \ - diepint.d32=0; \ - diepint.b.intr = 1; \ - USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[epnum]->DIEPINT,diepint.d32); - -#define CLEAR_OUT_EP_INTR(epnum,intr) \ - doepint.d32=0; \ - doepint.b.intr = 1; \ - USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[epnum]->DOEPINT,doepint.d32); - -/** - * @} - */ - -/** @defgroup USB_DCD_INT_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_DCD_INT_Exported_FunctionsPrototype - * @{ - */ - -uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev); - -/** - * @} - */ - - -#endif // USB_DCD_INT_H__ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/radio/bootloader/include/usb_defines.h b/radio/bootloader/include/usb_defines.h deleted file mode 100644 index 93c1bb010..000000000 --- a/radio/bootloader/include/usb_defines.h +++ /dev/null @@ -1,249 +0,0 @@ -/** - ****************************************************************************** - * @file usb_defines.h - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief Header of the Core Layer - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_DEF_H__ -#define __USB_DEF_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_DEFINES - * @brief This file is the - * @{ - */ - - -/** @defgroup USB_DEFINES_Exported_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup _CORE_DEFINES_ - * @{ - */ - -#define USB_OTG_SPEED_PARAM_HIGH 0 -#define USB_OTG_SPEED_PARAM_HIGH_IN_FULL 1 -#define USB_OTG_SPEED_PARAM_FULL 3 - -#define USB_OTG_SPEED_HIGH 0 -#define USB_OTG_SPEED_FULL 1 - -#define USB_OTG_ULPI_PHY 1 -#define USB_OTG_EMBEDDED_PHY 2 - -/** - * @} - */ - - -/** @defgroup _GLOBAL_DEFINES_ - * @{ - */ -#define GAHBCFG_TXFEMPTYLVL_EMPTY 1 -#define GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 -#define GAHBCFG_GLBINT_ENABLE 1 -#define GAHBCFG_INT_DMA_BURST_SINGLE 0 -#define GAHBCFG_INT_DMA_BURST_INCR 1 -#define GAHBCFG_INT_DMA_BURST_INCR4 3 -#define GAHBCFG_INT_DMA_BURST_INCR8 5 -#define GAHBCFG_INT_DMA_BURST_INCR16 7 -#define GAHBCFG_DMAENABLE 1 -#define GAHBCFG_TXFEMPTYLVL_EMPTY 1 -#define GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 -#define GRXSTS_PKTSTS_IN 2 -#define GRXSTS_PKTSTS_IN_XFER_COMP 3 -#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5 -#define GRXSTS_PKTSTS_CH_HALTED 7 -/** - * @} - */ - - -/** @defgroup _OnTheGo_DEFINES_ - * @{ - */ -#define MODE_HNP_SRP_CAPABLE 0 -#define MODE_SRP_ONLY_CAPABLE 1 -#define MODE_NO_HNP_SRP_CAPABLE 2 -#define MODE_SRP_CAPABLE_DEVICE 3 -#define MODE_NO_SRP_CAPABLE_DEVICE 4 -#define MODE_SRP_CAPABLE_HOST 5 -#define MODE_NO_SRP_CAPABLE_HOST 6 -#define A_HOST 1 -#define A_SUSPEND 2 -#define A_PERIPHERAL 3 -#define B_PERIPHERAL 4 -#define B_HOST 5 -#define DEVICE_MODE 0 -#define HOST_MODE 1 -#define OTG_MODE 2 -/** - * @} - */ - - -/** @defgroup __DEVICE_DEFINES_ - * @{ - */ -#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 -#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 -#define DSTS_ENUMSPD_LS_PHY_6MHZ 2 -#define DSTS_ENUMSPD_FS_PHY_48MHZ 3 - -#define DCFG_FRAME_INTERVAL_80 0 -#define DCFG_FRAME_INTERVAL_85 1 -#define DCFG_FRAME_INTERVAL_90 2 -#define DCFG_FRAME_INTERVAL_95 3 - -#define DEP0CTL_MPS_64 0 -#define DEP0CTL_MPS_32 1 -#define DEP0CTL_MPS_16 2 -#define DEP0CTL_MPS_8 3 - -#define EP_SPEED_LOW 0 -#define EP_SPEED_FULL 1 -#define EP_SPEED_HIGH 2 - -#define EP_TYPE_CTRL 0 -#define EP_TYPE_ISOC 1 -#define EP_TYPE_BULK 2 -#define EP_TYPE_INTR 3 -#define EP_TYPE_MSK 3 - -#define STS_GOUT_NAK 1 -#define STS_DATA_UPDT 2 -#define STS_XFER_COMP 3 -#define STS_SETUP_COMP 4 -#define STS_SETUP_UPDT 6 -/** - * @} - */ - - -/** @defgroup __HOST_DEFINES_ - * @{ - */ -#define HC_PID_DATA0 0 -#define HC_PID_DATA2 1 -#define HC_PID_DATA1 2 -#define HC_PID_SETUP 3 - -#define HPRT0_PRTSPD_HIGH_SPEED 0 -#define HPRT0_PRTSPD_FULL_SPEED 1 -#define HPRT0_PRTSPD_LOW_SPEED 2 - -#define HCFG_30_60_MHZ 0 -#define HCFG_48_MHZ 1 -#define HCFG_6_MHZ 2 - -#define HCCHAR_CTRL 0 -#define HCCHAR_ISOC 1 -#define HCCHAR_BULK 2 -#define HCCHAR_INTR 3 - -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) - -/** - * @} - */ - - -/** @defgroup USB_DEFINES_Exported_Types - * @{ - */ - -typedef enum -{ - USB_OTG_HS_CORE_ID = 0, - USB_OTG_FS_CORE_ID = 1 -}USB_OTG_CORE_ID_TypeDef; -/** - * @} - */ - - -/** @defgroup USB_DEFINES_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_DEFINES_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_DEFINES_Exported_FunctionsPrototype - * @{ - */ -/** - * @} - */ - - -/** @defgroup Internal_Macro's - * @{ - */ -#define USB_OTG_READ_REG32(reg) (*(__IO uint32_t *)reg) -#define USB_OTG_WRITE_REG32(reg,value) (*(__IO uint32_t *)reg = value) -#define USB_OTG_MODIFY_REG32(reg,clear_mask,set_mask) \ - USB_OTG_WRITE_REG32(reg, (((USB_OTG_READ_REG32(reg)) & ~clear_mask) | set_mask ) ) - -/******************************************************************************** - ENUMERATION TYPE -********************************************************************************/ -enum USB_OTG_SPEED { - USB_SPEED_UNKNOWN = 0, - USB_SPEED_LOW, - USB_SPEED_FULL, - USB_SPEED_HIGH -}; - -#endif //__USB_DEFINES__H__ - - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/radio/bootloader/include/usb_regs.h b/radio/bootloader/include/usb_regs.h deleted file mode 100644 index 7befb51d2..000000000 --- a/radio/bootloader/include/usb_regs.h +++ /dev/null @@ -1,1188 +0,0 @@ -/** - ****************************************************************************** - * @file usb_regs.h - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief hardware registers - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_OTG_REGS_H__ -#define __USB_OTG_REGS_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" - - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_REGS - * @brief This file is the - * @{ - */ - - -/** @defgroup USB_REGS_Exported_Defines - * @{ - */ - -#define USB_OTG_HS_BASE_ADDR 0x40040000 -#define USB_OTG_FS_BASE_ADDR 0x50000000 - -#define USB_OTG_CORE_GLOBAL_REGS_OFFSET 0x000 -#define USB_OTG_DEV_GLOBAL_REG_OFFSET 0x800 -#define USB_OTG_DEV_IN_EP_REG_OFFSET 0x900 -#define USB_OTG_EP_REG_OFFSET 0x20 -#define USB_OTG_DEV_OUT_EP_REG_OFFSET 0xB00 -#define USB_OTG_HOST_GLOBAL_REG_OFFSET 0x400 -#define USB_OTG_HOST_PORT_REGS_OFFSET 0x440 -#define USB_OTG_HOST_CHAN_REGS_OFFSET 0x500 -#define USB_OTG_CHAN_REGS_OFFSET 0x20 -#define USB_OTG_PCGCCTL_OFFSET 0xE00 -#define USB_OTG_DATA_FIFO_OFFSET 0x1000 -#define USB_OTG_DATA_FIFO_SIZE 0x1000 - - -#define USB_OTG_MAX_TX_FIFOS 15 - -#define USB_OTG_HS_MAX_PACKET_SIZE 512 -#define USB_OTG_FS_MAX_PACKET_SIZE 64 -#define USB_OTG_MAX_EP0_SIZE 64 -/** - * @} - */ - -/** @defgroup USB_REGS_Exported_Types - * @{ - */ - -/** @defgroup __USB_OTG_Core_register - * @{ - */ -typedef struct _USB_OTG_GREGS //000h -{ - __IO uint32_t GOTGCTL; /* USB_OTG Control and Status Register 000h*/ - __IO uint32_t GOTGINT; /* USB_OTG Interrupt Register 004h*/ - __IO uint32_t GAHBCFG; /* Core AHB Configuration Register 008h*/ - __IO uint32_t GUSBCFG; /* Core USB Configuration Register 00Ch*/ - __IO uint32_t GRSTCTL; /* Core Reset Register 010h*/ - __IO uint32_t GINTSTS; /* Core Interrupt Register 014h*/ - __IO uint32_t GINTMSK; /* Core Interrupt Mask Register 018h*/ - __IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch*/ - __IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h*/ - __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/ - __IO uint32_t DIEPTXF0_HNPTXFSIZ; /* EP0 / Non Periodic Tx FIFO Size Register 028h*/ - __IO uint32_t HNPTXSTS; /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/ - uint32_t Reserved30[2]; /* Reserved 030h*/ - __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/ - __IO uint32_t CID; /* User ID Register 03Ch*/ - uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/ - __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/ - __IO uint32_t DIEPTXF[USB_OTG_MAX_TX_FIFOS];/* dev Periodic Transmit FIFO */ -} -USB_OTG_GREGS; -/** - * @} - */ - - -/** @defgroup __device_Registers - * @{ - */ -typedef struct _USB_OTG_DREGS // 800h -{ - __IO uint32_t DCFG; /* dev Configuration Register 800h*/ - __IO uint32_t DCTL; /* dev Control Register 804h*/ - __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/ - uint32_t Reserved0C; /* Reserved 80Ch*/ - __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/ - __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/ - __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/ - __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/ - uint32_t Reserved20; /* Reserved 820h*/ - uint32_t Reserved9; /* Reserved 824h*/ - __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/ - __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/ - __IO uint32_t DTHRCTL; /* dev thr 830h*/ - __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ - __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/ - __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/ - uint32_t Reserved40; /* dedicated EP mask 840h*/ - __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ - uint32_t Reserved44[15]; /* Reserved 844-87Ch*/ - __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ -} -USB_OTG_DREGS; -/** - * @} - */ - - -/** @defgroup __IN_Endpoint-Specific_Register - * @{ - */ -typedef struct _USB_OTG_INEPREGS -{ - __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ - uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/ - __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ - uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/ - __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ - __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/ - __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ - uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ -} -USB_OTG_INEPREGS; -/** - * @} - */ - - -/** @defgroup __OUT_Endpoint-Specific_Registers - * @{ - */ -typedef struct _USB_OTG_OUTEPREGS -{ - __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ - uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ - __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ - uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ - __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ - __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ - uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ -} -USB_OTG_OUTEPREGS; -/** - * @} - */ - - -/** @defgroup __Host_Mode_Register_Structures - * @{ - */ -typedef struct _USB_OTG_HREGS -{ - __IO uint32_t HCFG; /* Host Configuration Register 400h*/ - __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ - __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ - uint32_t Reserved40C; /* Reserved 40Ch*/ - __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ - __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ - __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ -} -USB_OTG_HREGS; -/** - * @} - */ - - -/** @defgroup __Host_Channel_Specific_Registers - * @{ - */ -typedef struct _USB_OTG_HC_REGS -{ - __IO uint32_t HCCHAR; - __IO uint32_t HCSPLT; - __IO uint32_t HCINT; - __IO uint32_t HCINTMSK; - __IO uint32_t HCTSIZ; - __IO uint32_t HCDMA; - uint32_t Reserved[2]; -} -USB_OTG_HC_REGS; -/** - * @} - */ - - -/** @defgroup __otg_Core_registers - * @{ - */ -typedef struct USB_OTG_core_regs //000h -{ - USB_OTG_GREGS *GREGS; - USB_OTG_DREGS *DREGS; - USB_OTG_HREGS *HREGS; - USB_OTG_INEPREGS *INEP_REGS[USB_OTG_MAX_TX_FIFOS]; - USB_OTG_OUTEPREGS *OUTEP_REGS[USB_OTG_MAX_TX_FIFOS]; - USB_OTG_HC_REGS *HC_REGS[USB_OTG_MAX_TX_FIFOS]; - __IO uint32_t *HPRT0; - __IO uint32_t *DFIFO[USB_OTG_MAX_TX_FIFOS]; - __IO uint32_t *PCGCCTL; -} -USB_OTG_CORE_REGS , *PUSB_OTG_CORE_REGS; -typedef union _USB_OTG_GOTGCTL_TypeDef -{ - uint32_t d32; - struct - { -uint32_t sesreqscs : - 1; -uint32_t sesreq : - 1; -uint32_t Reserved2_7 : - 6; -uint32_t hstnegscs : - 1; -uint32_t hnpreq : - 1; -uint32_t hstsethnpen : - 1; -uint32_t devhnpen : - 1; -uint32_t Reserved12_15 : - 4; -uint32_t conidsts : - 1; -uint32_t dbct : - 1; -uint32_t asesvld : - 1; -uint32_t bsesvld : - 1; -uint32_t Reserved20_31 : - 12; - } - b; -} USB_OTG_GOTGCTL_TypeDef ; - -typedef union _USB_OTG_GOTGINT_TypeDef -{ - uint32_t d32; - struct - { -uint32_t Reserved0_1 : - 2; -uint32_t sesenddet : - 1; -uint32_t Reserved3_7 : - 5; -uint32_t sesreqsucstschng : - 1; -uint32_t hstnegsucstschng : - 1; -uint32_t reserver10_16 : - 7; -uint32_t hstnegdet : - 1; -uint32_t adevtoutchng : - 1; -uint32_t debdone : - 1; -uint32_t Reserved31_20 : - 12; - } - b; -} USB_OTG_GOTGINT_TypeDef ; -typedef union _USB_OTG_GAHBCFG_TypeDef -{ - uint32_t d32; - struct - { -uint32_t glblintrmsk : - 1; -uint32_t hburstlen : - 4; -uint32_t dmaenable : - 1; -uint32_t Reserved : - 1; -uint32_t nptxfemplvl_txfemplvl : - 1; -uint32_t ptxfemplvl : - 1; -uint32_t Reserved9_31 : - 23; - } - b; -} USB_OTG_GAHBCFG_TypeDef ; -typedef union _USB_OTG_GUSBCFG_TypeDef -{ - uint32_t d32; - struct - { -uint32_t toutcal : - 3; -uint32_t Reserved3_5 : - 3; -uint32_t physel : - 1; -uint32_t Reserved7 : - 1; -uint32_t srpcap : - 1; -uint32_t hnpcap : - 1; -uint32_t usbtrdtim : - 4; -uint32_t Reserved14 : - 1; -uint32_t phylpwrclksel : - 1; -uint32_t Reserved16 : - 1; -uint32_t ulpi_fsls : - 1; -uint32_t ulpi_auto_res : - 1; -uint32_t ulpi_clk_sus_m : - 1; -uint32_t ulpi_ext_vbus_drv : - 1; -uint32_t ulpi_int_vbus_ind : - 1; -uint32_t term_sel_dl_pulse : - 1; -uint32_t ulpi_ind_cpl : - 1; -uint32_t ulpi_passthrough : - 1; -uint32_t ulpi_protect_disable : - 1; -uint32_t Reserved26_28 : - 3; -uint32_t force_host : - 1; -uint32_t force_dev : - 1; -uint32_t corrupt_tx : - 1; - } - b; -} USB_OTG_GUSBCFG_TypeDef ; -typedef union _USB_OTG_GRSTCTL_TypeDef -{ - uint32_t d32; - struct - { -uint32_t csftrst : - 1; -uint32_t hsftrst : - 1; -uint32_t hstfrm : - 1; -uint32_t Reserved3 : - 1; -uint32_t rxfflsh : - 1; -uint32_t txfflsh : - 1; -uint32_t txfnum : - 5; -uint32_t Reserved11_29 : - 19; -uint32_t dmareq : - 1; -uint32_t ahbidle : - 1; - } - b; -} USB_OTG_GRSTCTL_TypeDef ; -typedef union _USB_OTG_GINTMSK_TypeDef -{ - uint32_t d32; - struct - { -uint32_t Reserved0 : - 1; -uint32_t modemismatch : - 1; -uint32_t otgintr : - 1; -uint32_t sofintr : - 1; -uint32_t rxstsqlvl : - 1; -uint32_t nptxfempty : - 1; -uint32_t ginnakeff : - 1; -uint32_t goutnakeff : - 1; -uint32_t Reserved8_9 : - 2; -uint32_t erlysuspend : - 1; -uint32_t usbsuspend : - 1; -uint32_t usbreset : - 1; -uint32_t enumdone : - 1; -uint32_t isooutdrop : - 1; -uint32_t eopframe : - 1; -uint32_t Reserved16 : - 1; -uint32_t epmismatch : - 1; -uint32_t inepintr : - 1; -uint32_t outepintr : - 1; -uint32_t incomplisoin : - 1; -uint32_t incomplisoout : - 1; -uint32_t Reserved22_23 : - 2; -uint32_t portintr : - 1; -uint32_t hcintr : - 1; -uint32_t ptxfempty : - 1; -uint32_t Reserved27 : - 1; -uint32_t conidstschng : - 1; -uint32_t disconnect : - 1; -uint32_t sessreqintr : - 1; -uint32_t wkupintr : - 1; - } - b; -} USB_OTG_GINTMSK_TypeDef ; -typedef union _USB_OTG_GINTSTS_TypeDef -{ - uint32_t d32; - struct - { -uint32_t curmode : - 1; -uint32_t modemismatch : - 1; -uint32_t otgintr : - 1; -uint32_t sofintr : - 1; -uint32_t rxstsqlvl : - 1; -uint32_t nptxfempty : - 1; -uint32_t ginnakeff : - 1; -uint32_t goutnakeff : - 1; -uint32_t Reserved8_9 : - 2; -uint32_t erlysuspend : - 1; -uint32_t usbsuspend : - 1; -uint32_t usbreset : - 1; -uint32_t enumdone : - 1; -uint32_t isooutdrop : - 1; -uint32_t eopframe : - 1; -uint32_t Reserved16_17 : - 2; -uint32_t inepint: - 1; -uint32_t outepintr : - 1; -uint32_t incomplisoin : - 1; -uint32_t incomplisoout : - 1; -uint32_t Reserved22_23 : - 2; -uint32_t portintr : - 1; -uint32_t hcintr : - 1; -uint32_t ptxfempty : - 1; -uint32_t Reserved27 : - 1; -uint32_t conidstschng : - 1; -uint32_t disconnect : - 1; -uint32_t sessreqintr : - 1; -uint32_t wkupintr : - 1; - } - b; -} USB_OTG_GINTSTS_TypeDef ; -typedef union _USB_OTG_DRXSTS_TypeDef -{ - uint32_t d32; - struct - { -uint32_t epnum : - 4; -uint32_t bcnt : - 11; -uint32_t dpid : - 2; -uint32_t pktsts : - 4; -uint32_t fn : - 4; -uint32_t Reserved : - 7; - } - b; -} USB_OTG_DRXSTS_TypeDef ; -typedef union _USB_OTG_GRXSTS_TypeDef -{ - uint32_t d32; - struct - { -uint32_t chnum : - 4; -uint32_t bcnt : - 11; -uint32_t dpid : - 2; -uint32_t pktsts : - 4; -uint32_t Reserved : - 11; - } - b; -} USB_OTG_GRXFSTS_TypeDef ; -typedef union _USB_OTG_FSIZ_TypeDef -{ - uint32_t d32; - struct - { -uint32_t startaddr : - 16; -uint32_t depth : - 16; - } - b; -} USB_OTG_FSIZ_TypeDef ; -typedef union _USB_OTG_HNPTXSTS_TypeDef -{ - uint32_t d32; - struct - { - uint32_t nptxfspcavail : - 16; - uint32_t nptxqspcavail : - 8; - struct - { - uint32_t terminate : - 1; - uint32_t token : - 2; - uint32_t chnum : - 4; - } nptxqtop; - uint32_t Reserved : - 1; - } - b; -} USB_OTG_HNPTXSTS_TypeDef ; -typedef union _USB_OTG_DTXFSTSn_TypeDef -{ - uint32_t d32; - struct - { -uint32_t txfspcavail : - 16; -uint32_t Reserved : - 16; - } - b; -} USB_OTG_DTXFSTSn_TypeDef ; - -typedef union _USB_OTG_GCCFG_TypeDef -{ - uint32_t d32; - struct - { -uint32_t Reserved_in : - 16; -uint32_t pwdn : - 1; -uint32_t Reserved_17 : - 1; -uint32_t vbussensingA : - 1; -uint32_t vbussensingB : - 1; -uint32_t sofouten : - 1; -uint32_t disablevbussensing : - 1; -uint32_t Reserved_out : - 10; - } - b; -} USB_OTG_GCCFG_TypeDef ; - -typedef union _USB_OTG_DCFG_TypeDef -{ - uint32_t d32; - struct - { -uint32_t devspd : - 2; -uint32_t nzstsouthshk : - 1; -uint32_t Reserved3 : - 1; -uint32_t devaddr : - 7; -uint32_t perfrint : - 2; -uint32_t Reserved12_31 : - 19; - } - b; -} USB_OTG_DCFG_TypeDef ; -typedef union _USB_OTG_DCTL_TypeDef -{ - uint32_t d32; - struct - { -uint32_t rmtwkupsig : - 1; -uint32_t sftdiscon : - 1; -uint32_t gnpinnaksts : - 1; -uint32_t goutnaksts : - 1; -uint32_t tstctl : - 3; -uint32_t sgnpinnak : - 1; -uint32_t cgnpinnak : - 1; -uint32_t sgoutnak : - 1; -uint32_t cgoutnak : - 1; -uint32_t poprg_done : - 1; -uint32_t Reserved : - 20; - } - b; -} USB_OTG_DCTL_TypeDef ; -typedef union _USB_OTG_DSTS_TypeDef -{ - uint32_t d32; - struct - { -uint32_t suspsts : - 1; -uint32_t enumspd : - 2; -uint32_t errticerr : - 1; -uint32_t Reserved4_7: - 4; -uint32_t soffn : - 14; -uint32_t Reserved22_31 : - 10; - } - b; -} USB_OTG_DSTS_TypeDef ; -typedef union _USB_OTG_DIEPINTn_TypeDef -{ - uint32_t d32; - struct - { -uint32_t xfercompl : - 1; -uint32_t epdisabled : - 1; -uint32_t Reserved2 : - 1; -uint32_t timeout : - 1; -uint32_t intktxfemp : - 1; -uint32_t Reserved5 : - 1; -uint32_t inepnakeff : - 1; -uint32_t emptyintr : - 1; -uint32_t txfifoundrn : - 1; -uint32_t Reserved14_31 : - 23; - } - b; -} USB_OTG_DIEPINTn_TypeDef ; -typedef union _USB_OTG_DIEPINTn_TypeDef USB_OTG_DIEPMSK_TypeDef ; -typedef union _USB_OTG_DOEPINTn_TypeDef -{ - uint32_t d32; - struct - { -uint32_t xfercompl : - 1; -uint32_t epdisabled : - 1; -uint32_t Reserved2 : - 1; -uint32_t setup : - 1; -uint32_t Reserved04_31 : - 28; - } - b; -} USB_OTG_DOEPINTn_TypeDef ; -typedef union _USB_OTG_DOEPINTn_TypeDef USB_OTG_DOEPMSK_TypeDef ; - -typedef union _USB_OTG_DAINT_TypeDef -{ - uint32_t d32; - struct - { -uint32_t in : - 16; -uint32_t out : - 16; - } - ep; -} USB_OTG_DAINT_TypeDef ; - -typedef union _USB_OTG_DTHRCTL_TypeDef -{ - uint32_t d32; - struct - { -uint32_t non_iso_thr_en : - 1; -uint32_t iso_thr_en : - 1; -uint32_t tx_thr_len : - 9; -uint32_t Reserved11_15 : - 5; -uint32_t rx_thr_en : - 1; -uint32_t rx_thr_len : - 9; -uint32_t Reserved26 : - 1; -uint32_t arp_en : - 1; -uint32_t Reserved28_31 : - 4; - } - b; -} USB_OTG_DTHRCTL_TypeDef ; -typedef union _USB_OTG_DEPCTL_TypeDef -{ - uint32_t d32; - struct - { -uint32_t mps : - 11; -uint32_t reserved : - 4; -uint32_t usbactep : - 1; -uint32_t dpid : - 1; -uint32_t naksts : - 1; -uint32_t eptype : - 2; -uint32_t snp : - 1; -uint32_t stall : - 1; -uint32_t txfnum : - 4; -uint32_t cnak : - 1; -uint32_t snak : - 1; -uint32_t setd0pid : - 1; -uint32_t setd1pid : - 1; -uint32_t epdis : - 1; -uint32_t epena : - 1; - } - b; -} USB_OTG_DEPCTL_TypeDef ; -typedef union _USB_OTG_DEPXFRSIZ_TypeDef -{ - uint32_t d32; - struct - { -uint32_t xfersize : - 19; -uint32_t pktcnt : - 10; -uint32_t mc : - 2; -uint32_t Reserved : - 1; - } - b; -} USB_OTG_DEPXFRSIZ_TypeDef ; -typedef union _USB_OTG_DEP0XFRSIZ_TypeDef -{ - uint32_t d32; - struct - { -uint32_t xfersize : - 7; -uint32_t Reserved7_18 : - 12; -uint32_t pktcnt : - 2; -uint32_t Reserved20_28 : - 9; -uint32_t supcnt : - 2; - uint32_t Reserved31; - } - b; -} USB_OTG_DEP0XFRSIZ_TypeDef ; -typedef union _USB_OTG_HCFG_TypeDef -{ - uint32_t d32; - struct - { -uint32_t fslspclksel : - 2; -uint32_t fslssupp : - 1; - } - b; -} USB_OTG_HCFG_TypeDef ; -typedef union _USB_OTG_HFRMINTRVL_TypeDef -{ - uint32_t d32; - struct - { -uint32_t frint : - 16; -uint32_t Reserved : - 16; - } - b; -} USB_OTG_HFRMINTRVL_TypeDef ; - -typedef union _USB_OTG_HFNUM_TypeDef -{ - uint32_t d32; - struct - { -uint32_t frnum : - 16; -uint32_t frrem : - 16; - } - b; -} USB_OTG_HFNUM_TypeDef ; -typedef union _USB_OTG_HPTXSTS_TypeDef -{ - uint32_t d32; - struct - { -uint32_t ptxfspcavail : - 16; -uint32_t ptxqspcavail : - 8; - struct - { - uint32_t terminate : - 1; - uint32_t token : - 2; - uint32_t chnum : - 4; - uint32_t odd_even : - 1; - } ptxqtop; - } - b; -} USB_OTG_HPTXSTS_TypeDef ; -typedef union _USB_OTG_HPRT0_TypeDef -{ - uint32_t d32; - struct - { -uint32_t prtconnsts : - 1; -uint32_t prtconndet : - 1; -uint32_t prtena : - 1; -uint32_t prtenchng : - 1; -uint32_t prtovrcurract : - 1; -uint32_t prtovrcurrchng : - 1; -uint32_t prtres : - 1; -uint32_t prtsusp : - 1; -uint32_t prtrst : - 1; -uint32_t Reserved9 : - 1; -uint32_t prtlnsts : - 2; -uint32_t prtpwr : - 1; -uint32_t prttstctl : - 4; -uint32_t prtspd : - 2; -uint32_t Reserved19_31 : - 13; - } - b; -} USB_OTG_HPRT0_TypeDef ; -typedef union _USB_OTG_HAINT_TypeDef -{ - uint32_t d32; - struct - { -uint32_t chint : - 16; -uint32_t Reserved : - 16; - } - b; -} USB_OTG_HAINT_TypeDef ; -typedef union _USB_OTG_HAINTMSK_TypeDef -{ - uint32_t d32; - struct - { -uint32_t chint : - 16; -uint32_t Reserved : - 16; - } - b; -} USB_OTG_HAINTMSK_TypeDef ; -typedef union _USB_OTG_HCCHAR_TypeDef -{ - uint32_t d32; - struct - { -uint32_t mps : - 11; -uint32_t epnum : - 4; -uint32_t epdir : - 1; -uint32_t Reserved : - 1; -uint32_t lspddev : - 1; -uint32_t eptype : - 2; -uint32_t multicnt : - 2; -uint32_t devaddr : - 7; -uint32_t oddfrm : - 1; -uint32_t chdis : - 1; -uint32_t chen : - 1; - } - b; -} USB_OTG_HCCHAR_TypeDef ; -typedef union _USB_OTG_HCSPLT_TypeDef -{ - uint32_t d32; - struct - { -uint32_t prtaddr : - 7; -uint32_t hubaddr : - 7; -uint32_t xactpos : - 2; -uint32_t compsplt : - 1; -uint32_t Reserved : - 14; -uint32_t spltena : - 1; - } - b; -} USB_OTG_HCSPLT_TypeDef ; -typedef union _USB_OTG_HCINTn_TypeDef -{ - uint32_t d32; - struct - { -uint32_t xfercompl : - 1; -uint32_t chhltd : - 1; -uint32_t ahberr : - 1; -uint32_t stall : - 1; -uint32_t nak : - 1; -uint32_t ack : - 1; -uint32_t nyet : - 1; -uint32_t xacterr : - 1; -uint32_t bblerr : - 1; -uint32_t frmovrun : - 1; -uint32_t datatglerr : - 1; -uint32_t Reserved : - 21; - } - b; -} USB_OTG_HCINTn_TypeDef ; -typedef union _USB_OTG_HCTSIZn_TypeDef -{ - uint32_t d32; - struct - { -uint32_t xfersize : - 19; -uint32_t pktcnt : - 10; -uint32_t pid : - 2; -uint32_t dopng : - 1; - } - b; -} USB_OTG_HCTSIZn_TypeDef ; -typedef union _USB_OTG_HCINTMSK_TypeDef -{ - uint32_t d32; - struct - { -uint32_t xfercompl : - 1; -uint32_t chhltd : - 1; -uint32_t ahberr : - 1; -uint32_t stall : - 1; -uint32_t nak : - 1; -uint32_t ack : - 1; -uint32_t nyet : - 1; -uint32_t xacterr : - 1; -uint32_t bblerr : - 1; -uint32_t frmovrun : - 1; -uint32_t datatglerr : - 1; -uint32_t Reserved : - 21; - } - b; -} USB_OTG_HCINTMSK_TypeDef ; - -typedef union _USB_OTG_PCGCCTL_TypeDef -{ - uint32_t d32; - struct - { -uint32_t stoppclk : - 1; -uint32_t gatehclk : - 1; -uint32_t Reserved2_3 : - 2; -uint32_t phy_susp : - 1; -uint32_t Reserved5_31 : - 27; - } - b; -} USB_OTG_PCGCCTL_TypeDef ; - -/** - * @} - */ - - -/** @defgroup USB_REGS_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_REGS_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_REGS_Exported_FunctionsPrototype - * @{ - */ -/** - * @} - */ - - -#endif //__USB_OTG_REGS_H__ - - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/radio/bootloader/include/usbd_conf.h b/radio/bootloader/include/usbd_conf.h deleted file mode 100644 index 34e07e811..000000000 --- a/radio/bootloader/include/usbd_conf.h +++ /dev/null @@ -1,54 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_conf.h - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief USB Device configuration file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_CONF__H__ -#define __USBD_CONF__H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" - -#define USBD_CFG_MAX_NUM 1 -#define USBD_ITF_MAX_NUM 1 -#define USB_MAX_STR_DESC_SIZ 64 - -#define USBD_SELF_POWERED - -/* Class Layer Parameter */ - -#define MSC_IN_EP 0x81 -#define MSC_OUT_EP 0x01 -#define MSC_MAX_PACKET 64 - -#define MSC_MEDIA_PACKET 4096 - - -#endif //__USBD_CONF__H__ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/radio/bootloader/include/usbd_core.h b/radio/bootloader/include/usbd_core.h deleted file mode 100644 index 1ba845c5a..000000000 --- a/radio/bootloader/include/usbd_core.h +++ /dev/null @@ -1,120 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_core.h - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief Header file for usbd_core.c - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_CORE_H -#define __USBD_CORE_H - -/* Includes ------------------------------------------------------------------*/ -#include "usb_dcd.h" -#include "usbd_def.h" -#include "usbd_conf.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_CORE - * @brief This file is the Header file for usbd_core.c file - * @{ - */ - - -/** @defgroup USBD_CORE_Exported_Defines - * @{ - */ - -typedef enum { - USBD_OK = 0, - USBD_BUSY, - USBD_FAIL, -}USBD_Status; -/** - * @} - */ - - -/** @defgroup USBD_CORE_Exported_TypesDefinitions - * @{ - */ - - -/** - * @} - */ - - - -/** @defgroup USBD_CORE_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_FunctionsPrototype - * @{ - */ -void USBD_Init(USB_OTG_CORE_HANDLE *pdev, - USB_OTG_CORE_ID_TypeDef coreID, - USBD_DEVICE *pDevice, - USBD_Class_cb_TypeDef *class_cb, - USBD_Usr_cb_TypeDef *usr_cb); - -USBD_Status USBD_DeInit(USB_OTG_CORE_HANDLE *pdev); - -USBD_Status USBD_ClrCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx); - -USBD_Status USBD_SetCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx); - -/** - * @} - */ - -#endif /* __USBD_CORE_H */ - -/** - * @} - */ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - - diff --git a/radio/bootloader/include/usbd_def.h b/radio/bootloader/include/usbd_def.h deleted file mode 100644 index 2aa132543..000000000 --- a/radio/bootloader/include/usbd_def.h +++ /dev/null @@ -1,156 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_def.h - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief general defines for the usb device library - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#ifndef __USBD_DEF_H -#define __USBD_DEF_H - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_conf.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USB_DEF - * @brief general defines for the usb device library file - * @{ - */ - -/** @defgroup USB_DEF_Exported_Defines - * @{ - */ - -#ifndef NULL -#define NULL 0 -#endif - -#define USB_LEN_DEV_QUALIFIER_DESC 0x0A -#define USB_LEN_DEV_DESC 0x12 -#define USB_LEN_CFG_DESC 0x09 -#define USB_LEN_IF_DESC 0x09 -#define USB_LEN_EP_DESC 0x07 -#define USB_LEN_OTG_DESC 0x03 - -#define USBD_IDX_LANGID_STR 0x00 -#define USBD_IDX_MFC_STR 0x01 -#define USBD_IDX_PRODUCT_STR 0x02 -#define USBD_IDX_SERIAL_STR 0x03 -#define USBD_IDX_CONFIG_STR 0x04 -#define USBD_IDX_INTERFACE_STR 0x05 - -#define USB_REQ_TYPE_STANDARD 0x00 -#define USB_REQ_TYPE_CLASS 0x20 -#define USB_REQ_TYPE_VENDOR 0x40 -#define USB_REQ_TYPE_MASK 0x60 - -#define USB_REQ_RECIPIENT_DEVICE 0x00 -#define USB_REQ_RECIPIENT_INTERFACE 0x01 -#define USB_REQ_RECIPIENT_ENDPOINT 0x02 -#define USB_REQ_RECIPIENT_MASK 0x03 - -#define USB_REQ_GET_STATUS 0x00 -#define USB_REQ_CLEAR_FEATURE 0x01 -#define USB_REQ_SET_FEATURE 0x03 -#define USB_REQ_SET_ADDRESS 0x05 -#define USB_REQ_GET_DESCRIPTOR 0x06 -#define USB_REQ_SET_DESCRIPTOR 0x07 -#define USB_REQ_GET_CONFIGURATION 0x08 -#define USB_REQ_SET_CONFIGURATION 0x09 -#define USB_REQ_GET_INTERFACE 0x0A -#define USB_REQ_SET_INTERFACE 0x0B -#define USB_REQ_SYNCH_FRAME 0x0C - -#define USB_DESC_TYPE_DEVICE 1 -#define USB_DESC_TYPE_CONFIGURATION 2 -#define USB_DESC_TYPE_STRING 3 -#define USB_DESC_TYPE_INTERFACE 4 -#define USB_DESC_TYPE_ENDPOINT 5 -#define USB_DESC_TYPE_DEVICE_QUALIFIER 6 -#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 7 - - -#define USB_CONFIG_REMOTE_WAKEUP 2 -#define USB_CONFIG_SELF_POWERED 1 - -#define USB_FEATURE_EP_HALT 0 -#define USB_FEATURE_REMOTE_WAKEUP 1 -#define USB_FEATURE_TEST_MODE 2 - -/** - * @} - */ - - -/** @defgroup USBD_DEF_Exported_TypesDefinitions - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USBD_DEF_Exported_Macros - * @{ - */ -#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ - (((uint16_t)(*(((uint8_t *)(addr)) + 1))) << 8)) - -#define LOBYTE(x) ((uint8_t)(x & 0x00FF)) -#define HIBYTE(x) ((uint8_t)((x & 0xFF00) >>8)) -/** - * @} - */ - -/** @defgroup USBD_DEF_Exported_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_DEF_Exported_FunctionsPrototype - * @{ - */ - -/** - * @} - */ - -#endif /* __USBD_DEF_H */ - -/** - * @} - */ - -/** -* @} -*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/include/usbd_ioreq.h b/radio/bootloader/include/usbd_ioreq.h deleted file mode 100644 index b385b31ca..000000000 --- a/radio/bootloader/include/usbd_ioreq.h +++ /dev/null @@ -1,121 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_ioreq.h - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief header file for the usbd_ioreq.c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#ifndef __USBD_IOREQ_H_ -#define __USBD_IOREQ_H_ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_def.h" -#include "usbd_core.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_IOREQ - * @brief header file for the usbd_ioreq.c file - * @{ - */ - -/** @defgroup USBD_IOREQ_Exported_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Exported_Types - * @{ - */ - - -/** - * @} - */ - - - -/** @defgroup USBD_IOREQ_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_IOREQ_Exported_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_IOREQ_Exported_FunctionsPrototype - * @{ - */ - -USBD_Status USBD_CtlSendData (USB_OTG_CORE_HANDLE *pdev, - uint8_t *buf, - uint16_t len); - -USBD_Status USBD_CtlContinueSendData (USB_OTG_CORE_HANDLE *pdev, - uint8_t *pbuf, - uint16_t len); - -USBD_Status USBD_CtlPrepareRx (USB_OTG_CORE_HANDLE *pdev, - uint8_t *pbuf, - uint16_t len); - -USBD_Status USBD_CtlContinueRx (USB_OTG_CORE_HANDLE *pdev, - uint8_t *pbuf, - uint16_t len); - -USBD_Status USBD_CtlSendStatus (USB_OTG_CORE_HANDLE *pdev); - -USBD_Status USBD_CtlReceiveStatus (USB_OTG_CORE_HANDLE *pdev); - -uint16_t USBD_GetRxCount (USB_OTG_CORE_HANDLE *pdev , - uint8_t epnum); - -/** - * @} - */ - -#endif /* __USBD_IOREQ_H_ */ - -/** - * @} - */ - -/** -* @} -*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/include/usbd_msc_bot.h b/radio/bootloader/include/usbd_msc_bot.h deleted file mode 100644 index fe85b5170..000000000 --- a/radio/bootloader/include/usbd_msc_bot.h +++ /dev/null @@ -1,153 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_msc_bot.h - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief header for the usbd_msc_bot.c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#include "usbd_core.h" - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_MSC_BOT_H -#define __USBD_MSC_BOT_H - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup MSC_BOT - * @brief This file is the Header file for usbd_bot.c - * @{ - */ - - -/** @defgroup USBD_CORE_Exported_Defines - * @{ - */ -#define BOT_IDLE 0 /* Idle state */ -#define BOT_DATA_OUT 1 /* Data Out state */ -#define BOT_DATA_IN 2 /* Data In state */ -#define BOT_LAST_DATA_IN 3 /* Last Data In Last */ -#define BOT_SEND_DATA 4 /* Send Immediate data */ - -#define BOT_CBW_SIGNATURE 0x43425355 -#define BOT_CSW_SIGNATURE 0x53425355 -#define BOT_CBW_LENGTH 31 -#define BOT_CSW_LENGTH 13 - -/* CSW Status Definitions */ -#define CSW_CMD_PASSED 0x00 -#define CSW_CMD_FAILED 0x01 -#define CSW_PHASE_ERROR 0x02 - -/* BOT Status */ -#define BOT_STATE_NORMAL 0 -#define BOT_STATE_RECOVERY 1 -#define BOT_STATE_ERROR 2 - - -#define DIR_IN 0 -#define DIR_OUT 1 -#define BOTH_DIR 2 - -/** - * @} - */ - -/** @defgroup MSC_CORE_Private_TypesDefinitions - * @{ - */ - -typedef struct _MSC_BOT_CBW -{ - uint32_t dSignature; - uint32_t dTag; - uint32_t dDataLength; - uint8_t bmFlags; - uint8_t bLUN; - uint8_t bCBLength; - uint8_t CB[16]; -} -MSC_BOT_CBW_TypeDef; - - -typedef struct _MSC_BOT_CSW -{ - uint32_t dSignature; - uint32_t dTag; - uint32_t dDataResidue; - uint8_t bStatus; -} -MSC_BOT_CSW_TypeDef; - -/** - * @} - */ - - -/** @defgroup USBD_CORE_Exported_Types - * @{ - */ - -extern uint8_t MSC_BOT_Data[]; -extern uint16_t MSC_BOT_DataLen; -extern uint8_t MSC_BOT_State; -extern uint8_t MSC_BOT_BurstMode; -extern MSC_BOT_CBW_TypeDef MSC_BOT_cbw; -extern MSC_BOT_CSW_TypeDef MSC_BOT_csw; -/** - * @} - */ -/** @defgroup USBD_CORE_Exported_FunctionsPrototypes - * @{ - */ -void MSC_BOT_Init (USB_OTG_CORE_HANDLE *pdev); -void MSC_BOT_Reset (USB_OTG_CORE_HANDLE *pdev); -void MSC_BOT_DeInit (USB_OTG_CORE_HANDLE *pdev); -void MSC_BOT_DataIn (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum); - -void MSC_BOT_DataOut (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum); - -void MSC_BOT_SendCSW (USB_OTG_CORE_HANDLE *pdev, - uint8_t CSW_Status); - -void MSC_BOT_CplClrFeature (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum); -/** - * @} - */ - -#endif /* __USBD_MSC_BOT_H */ -/** - * @} - */ - -/** -* @} -*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/radio/bootloader/include/usbd_msc_core.h b/radio/bootloader/include/usbd_msc_core.h deleted file mode 100644 index 5662465cc..000000000 --- a/radio/bootloader/include/usbd_msc_core.h +++ /dev/null @@ -1,77 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_msc_core.h - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief header for the usbd_msc_core.c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef _USB_MSC_CORE_H_ -#define _USB_MSC_CORE_H_ - -#include "usbd_ioreq.h" - -/** @addtogroup USBD_MSC_BOT - * @{ - */ - -/** @defgroup USBD_MSC - * @brief This file is the Header file for USBD_msc.c - * @{ - */ - - -/** @defgroup USBD_BOT_Exported_Defines - * @{ - */ - - -#define BOT_GET_MAX_LUN 0xFE -#define BOT_RESET 0xFF -#define USB_MSC_CONFIG_DESC_SIZ 32 - -#define MSC_EPIN_SIZE MSC_MAX_PACKET -#define MSC_EPOUT_SIZE MSC_MAX_PACKET - -/** - * @} - */ - -/** @defgroup USB_CORE_Exported_Types - * @{ - */ - -extern USBD_Class_cb_TypeDef USBD_MSC_cb; -/** - * @} - */ - -/** - * @} - */ -#endif // _USB_MSC_CORE_H_ -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/include/usbd_msc_data.h b/radio/bootloader/include/usbd_msc_data.h deleted file mode 100644 index 3fb21185a..000000000 --- a/radio/bootloader/include/usbd_msc_data.h +++ /dev/null @@ -1,104 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_msc_data.h - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief header for the usbd_msc_data.c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#ifndef _USBD_MSC_DATA_H_ -#define _USBD_MSC_DATA_H_ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_conf.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USB_INFO - * @brief general defines for the usb device library file - * @{ - */ - -/** @defgroup USB_INFO_Exported_Defines - * @{ - */ -#define MODE_SENSE6_LEN 8 -#define MODE_SENSE10_LEN 8 -#define LENGTH_INQUIRY_PAGE00 7 -#define LENGTH_FORMAT_CAPACITIES 20 - -/** - * @} - */ - - -/** @defgroup USBD_INFO_Exported_TypesDefinitions - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USBD_INFO_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_INFO_Exported_Variables - * @{ - */ -extern const uint8_t MSC_Page00_Inquiry_Data[]; -extern const uint8_t MSC_Mode_Sense6_data[]; -extern const uint8_t MSC_Mode_Sense10_data[] ; - -/** - * @} - */ - -/** @defgroup USBD_INFO_Exported_FunctionsPrototype - * @{ - */ - -/** - * @} - */ - -#endif /* _USBD_MSC_DATA_H_ */ - -/** - * @} - */ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/include/usbd_msc_mem.h b/radio/bootloader/include/usbd_msc_mem.h deleted file mode 100644 index 6b1378f7c..000000000 --- a/radio/bootloader/include/usbd_msc_mem.h +++ /dev/null @@ -1,112 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_msc_mem.h - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief header for the STORAGE DISK file file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#ifndef __USBD_MEM_H -#define __USBD_MEM_H -/* Includes ------------------------------------------------------------------*/ -#include "usbd_def.h" - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_MEM - * @brief header file for the storage disk file - * @{ - */ - -/** @defgroup USBD_MEM_Exported_Defines - * @{ - */ -#define USBD_STD_INQUIRY_LENGTH 36 -/** - * @} - */ - - -/** @defgroup USBD_MEM_Exported_TypesDefinitions - * @{ - */ - -typedef struct _USBD_STORAGE -{ - int8_t (* Init) (uint8_t lun); - int8_t (* GetCapacity) (uint8_t lun, uint32_t *block_num, uint32_t *block_size); - int8_t (* IsReady) (uint8_t lun); - int8_t (* IsWriteProtected) (uint8_t lun); - int8_t (* Read) (uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len); - int8_t (* Write)(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len); - int8_t (* GetMaxLun)(void); - int8_t *pInquiry; - -}USBD_STORAGE_cb_TypeDef; -/** - * @} - */ - - - -/** @defgroup USBD_MEM_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_MEM_Exported_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_MEM_Exported_FunctionsPrototype - * @{ - */ -extern USBD_STORAGE_cb_TypeDef *USBD_STORAGE_fops; -/** - * @} - */ - -#endif /* __USBD_MEM_H */ -/** - * @} - */ - -/** - * @} - */ - -/** -* @} -*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/include/usbd_msc_scsi.h b/radio/bootloader/include/usbd_msc_scsi.h deleted file mode 100644 index 71b8250d3..000000000 --- a/radio/bootloader/include/usbd_msc_scsi.h +++ /dev/null @@ -1,195 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_msc_scsi.h - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief header for the usbd_msc_scsi.c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_MSC_SCSI_H -#define __USBD_MSC_SCSI_H - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_def.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_SCSI - * @brief header file for the storage disk file - * @{ - */ - -/** @defgroup USBD_SCSI_Exported_Defines - * @{ - */ - -#define SENSE_LIST_DEEPTH 4 - -/* SCSI Commands */ -#define SCSI_FORMAT_UNIT 0x04 -#define SCSI_INQUIRY 0x12 -#define SCSI_MODE_SELECT6 0x15 -#define SCSI_MODE_SELECT10 0x55 -#define SCSI_MODE_SENSE6 0x1A -#define SCSI_MODE_SENSE10 0x5A -#define SCSI_ALLOW_MEDIUM_REMOVAL 0x1E -#define SCSI_READ6 0x08 -#define SCSI_READ10 0x28 -#define SCSI_READ12 0xA8 -#define SCSI_READ16 0x88 - -#define SCSI_READ_CAPACITY10 0x25 -#define SCSI_READ_CAPACITY16 0x9E - -#define SCSI_REQUEST_SENSE 0x03 -#define SCSI_START_STOP_UNIT 0x1B -#define SCSI_TEST_UNIT_READY 0x00 -#define SCSI_WRITE6 0x0A -#define SCSI_WRITE10 0x2A -#define SCSI_WRITE12 0xAA -#define SCSI_WRITE16 0x8A - -#define SCSI_VERIFY10 0x2F -#define SCSI_VERIFY12 0xAF -#define SCSI_VERIFY16 0x8F - -#define SCSI_SEND_DIAGNOSTIC 0x1D -#define SCSI_READ_FORMAT_CAPACITIES 0x23 - -#define NO_SENSE 0 -#define RECOVERED_ERROR 1 -#define NOT_READY 2 -#define MEDIUM_ERROR 3 -#define HARDWARE_ERROR 4 -#define ILLEGAL_REQUEST 5 -#define UNIT_ATTENTION 6 -#define DATA_PROTECT 7 -#define BLANK_CHECK 8 -#define VENDOR_SPECIFIC 9 -#define COPY_ABORTED 10 -#define ABORTED_COMMAND 11 -#define VOLUME_OVERFLOW 13 -#define MISCOMPARE 14 - - -#define INVALID_CDB 0x20 -#define INVALID_FIELED_IN_COMMAND 0x24 -#define PARAMETER_LIST_LENGTH_ERROR 0x1A -#define INVALID_FIELD_IN_PARAMETER_LIST 0x26 -#define ADDRESS_OUT_OF_RANGE 0x21 -#define MEDIUM_NOT_PRESENT 0x3A -#define MEDIUM_HAVE_CHANGED 0x28 -#define WRITE_PROTECTED 0x27 -#define UNRECOVERED_READ_ERROR 0x11 -#define WRITE_FAULT 0x03 - -#define READ_FORMAT_CAPACITY_DATA_LEN 0x0C -#define READ_CAPACITY10_DATA_LEN 0x08 -#define MODE_SENSE10_DATA_LEN 0x08 -#define MODE_SENSE6_DATA_LEN 0x04 -#define REQUEST_SENSE_DATA_LEN 0x12 -#define STANDARD_INQUIRY_DATA_LEN 0x24 -#define BLKVFY 0x04 - -extern uint8_t Page00_Inquiry_Data[]; -extern uint8_t Standard_Inquiry_Data[]; -extern uint8_t Standard_Inquiry_Data2[]; -extern uint8_t Mode_Sense6_data[]; -extern uint8_t Mode_Sense10_data[]; -extern uint8_t Scsi_Sense_Data[]; -extern uint8_t ReadCapacity10_Data[]; -extern uint8_t ReadFormatCapacity_Data []; -/** - * @} - */ - - -/** @defgroup USBD_SCSI_Exported_TypesDefinitions - * @{ - */ - -typedef struct _SENSE_ITEM { - char Skey; - union { - struct _ASCs { - char ASC; - char ASCQ; - }b; - unsigned int ASC; - char *pData; - } w; -} SCSI_Sense_TypeDef; -/** - * @} - */ - -/** @defgroup USBD_SCSI_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_SCSI_Exported_Variables - * @{ - */ -extern SCSI_Sense_TypeDef SCSI_Sense [SENSE_LIST_DEEPTH]; -extern uint8_t SCSI_Sense_Head; -extern uint8_t SCSI_Sense_Tail; - -/** - * @} - */ -/** @defgroup USBD_SCSI_Exported_FunctionsPrototype - * @{ - */ -int8_t SCSI_ProcessCmd(USB_OTG_CORE_HANDLE *pdev, - uint8_t lun, - uint8_t *cmd); - -void SCSI_SenseCode(uint8_t lun, - uint8_t sKey, - uint8_t ASC); - -/** - * @} - */ - -#endif /* __USBD_MSC_SCSI_H */ -/** - * @} - */ - -/** - * @} - */ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/radio/bootloader/include/usbd_req.h b/radio/bootloader/include/usbd_req.h deleted file mode 100644 index e16593739..000000000 --- a/radio/bootloader/include/usbd_req.h +++ /dev/null @@ -1,108 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_req.h - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief header file for the usbd_req.c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#ifndef __USB_REQUEST_H_ -#define __USB_REQUEST_H_ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_def.h" -#include "usbd_core.h" -#include "usbd_conf.h" - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_REQ - * @brief header file for the usbd_ioreq.c file - * @{ - */ - -/** @defgroup USBD_REQ_Exported_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_REQ_Exported_Types - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USBD_REQ_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBD_REQ_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USBD_REQ_Exported_FunctionsPrototype - * @{ - */ - -USBD_Status USBD_StdDevReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req); -USBD_Status USBD_StdItfReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req); -USBD_Status USBD_StdEPReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req); -void USBD_ParseSetupRequest( USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -void USBD_CtlError( USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len); -/** - * @} - */ - -#endif /* __USB_REQUEST_H_ */ - -/** - * @} - */ - -/** -* @} -*/ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/include/usbd_usr.h b/radio/bootloader/include/usbd_usr.h deleted file mode 100644 index 428cf68e6..000000000 --- a/radio/bootloader/include/usbd_usr.h +++ /dev/null @@ -1,141 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_usr.h - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief Header file for usbd_usr.c - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_USR_H__ -#define __USBD_USR_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_core.h" - - -/** @addtogroup USBD_USER - * @{ - */ - -/** @addtogroup USBD_MSC_DEMO_USER_CALLBACKS - * @{ - */ - -/** @defgroup USBD_USR - * @brief This file is the Header file for usbd_usr.c - * @{ - */ - - -/** @defgroup USBD_USR_Exported_Types - * @{ - */ - -extern USBD_Usr_cb_TypeDef USR_cb; -extern USBD_Usr_cb_TypeDef USR_FS_cb; -extern USBD_Usr_cb_TypeDef USR_HS_cb; - - - -/** - * @} - */ - - - -/** @defgroup USBD_USR_Exported_Defines - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_USR_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBD_USR_Exported_Variables - * @{ - */ - -void USBD_USR_Init(void); -void USBD_USR_DeviceReset (uint8_t speed); -void USBD_USR_DeviceConfigured (void); -void USBD_USR_DeviceSuspended(void); -void USBD_USR_DeviceResumed(void); - -void USBD_USR_DeviceConnected(void); -void USBD_USR_DeviceDisconnected(void); - -void USBD_USR_FS_Init(void); -void USBD_USR_FS_DeviceReset (uint8_t speed); -void USBD_USR_FS_DeviceConfigured (void); -void USBD_USR_FS_DeviceSuspended(void); -void USBD_USR_FS_DeviceResumed(void); - -void USBD_USR_FS_DeviceConnected(void); -void USBD_USR_FS_DeviceDisconnected(void); - -void USBD_USR_HS_Init(void); -void USBD_USR_HS_DeviceReset (uint8_t speed); -void USBD_USR_HS_DeviceConfigured (void); -void USBD_USR_HS_DeviceSuspended(void); -void USBD_USR_HS_DeviceResumed(void); - -void USBD_USR_HS_DeviceConnected(void); -void USBD_USR_HS_DeviceDisconnected(void); - -/** - * @} - */ - -/** @defgroup USBD_USR_Exported_FunctionsPrototype - * @{ - */ -/** - * @} - */ - -#endif /*__USBD_USR_H__*/ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - - - diff --git a/radio/src/targets/taranis/usbd_storage_msd.cpp b/radio/src/targets/taranis/usbd_storage_msd.cpp index e9c4dff58..65d382b96 100644 --- a/radio/src/targets/taranis/usbd_storage_msd.cpp +++ b/radio/src/targets/taranis/usbd_storage_msd.cpp @@ -35,8 +35,6 @@ extern "C" { #include "usbd_msc_mem.h" #include "usb_conf.h" -// void eeprom_read_block (void *pointer_ram, uint16_t pointer_eeprom, size_t size); - #define STORAGE_LUN_NBR 2 #define BLOCKSIZE 512 From 0b83d9e0d7f29fe0eca397906c8a34fd8d665d94 Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Tue, 4 Mar 2014 16:42:26 +0100 Subject: [PATCH 021/285] Update DONATIONS.txt --- DONATIONS.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/DONATIONS.txt b/DONATIONS.txt index 9d0ad46c1..7c003ccfd 100644 --- a/DONATIONS.txt +++ b/DONATIONS.txt @@ -332,3 +332,5 @@ Steve Coley Sean Cull Roberto Orsello David Finger +FrSky - www.frsky-rc.com +Jean-marie Oddo From bb767ca8637086a833015655ecef0d6a2ccbb806 Mon Sep 17 00:00:00 2001 From: Kjell Kernen Date: Tue, 4 Mar 2014 17:03:54 +0100 Subject: [PATCH 022/285] Slowing down the close of the download dialog with 2 seconds to avoid unpeasant flashing dialogs. --- companion/src/downloaddialog.cpp | 12 ++++++++++++ companion/src/downloaddialog.h | 1 + 2 files changed, 13 insertions(+) diff --git a/companion/src/downloaddialog.cpp b/companion/src/downloaddialog.cpp index 794dbbcd1..aa7ea6ef3 100644 --- a/companion/src/downloaddialog.cpp +++ b/companion/src/downloaddialog.cpp @@ -2,6 +2,7 @@ #include "ui_downloaddialog.h" #include #include +#include #include "helpers.h" downloadDialog::downloadDialog(QWidget *parent, QString src, QString tgt) : @@ -87,3 +88,14 @@ void downloadDialog::fileError() file = 0; reject(); } + +void downloadDialog::closeEvent( QCloseEvent * event) +{ + // Delay closing 2 seconds to avoid unpleasant flashing download dialogs + QTime closeTime= QTime::currentTime().addSecs(2); + while( QTime::currentTime() < closeTime ) + QCoreApplication::processEvents(QEventLoop::AllEvents, 100); + + event->accept(); +} + diff --git a/companion/src/downloaddialog.h b/companion/src/downloaddialog.h index 596002250..9730e3134 100644 --- a/companion/src/downloaddialog.h +++ b/companion/src/downloaddialog.h @@ -27,6 +27,7 @@ private slots: void updateDataReadProgress(qint64 bytesRead, qint64 totalBytes); private: + void closeEvent( QCloseEvent * event); Ui::downloadDialog *ui; QNetworkAccessManager qnam; From 51fe47ed8af74fe55922344dea83bd4326816994 Mon Sep 17 00:00:00 2001 From: bsongis Date: Tue, 4 Mar 2014 17:14:35 +0100 Subject: [PATCH 023/285] 3 files removed --- radio/bootloader/Makefile | 2 +- radio/bootloader/boot.cpp | 4 +- radio/bootloader/include/diskio.h | 6 +- radio/bootloader/include/hal.h | 254 ---------------------- radio/bootloader/massstorage.cpp | 233 -------------------- radio/bootloader/sdcard_driver.cpp | 71 ------ radio/bootloader/usbd_storage_msd.cpp | 9 +- radio/src/targets/taranis/board_taranis.h | 11 +- radio/src/targets/taranis/diskio.cpp | 22 +- radio/src/targets/taranis/hal.h | 4 +- 10 files changed, 35 insertions(+), 581 deletions(-) delete mode 100644 radio/bootloader/include/hal.h delete mode 100644 radio/bootloader/massstorage.cpp delete mode 100644 radio/bootloader/sdcard_driver.cpp diff --git a/radio/bootloader/Makefile b/radio/bootloader/Makefile index 50e327181..886d06bb2 100644 --- a/radio/bootloader/Makefile +++ b/radio/bootloader/Makefile @@ -141,7 +141,7 @@ CPPSRC = lcd_driver.cpp \ driversboot.cpp \ logicioboot.cpp \ ff.cpp \ - x9ddiskio.cpp \ + ../src/targets/taranis/diskio.cpp \ ../src/targets/taranis/usbd_usr.cpp \ usbd_storage_msd.cpp \ lcdboot.cpp \ diff --git a/radio/bootloader/boot.cpp b/radio/bootloader/boot.cpp index 9305a9064..1c3dd2673 100644 --- a/radio/bootloader/boot.cpp +++ b/radio/bootloader/boot.cpp @@ -819,7 +819,7 @@ extern uint8_t OptrexDisplay ; #ifdef PCBTARANIS // SD card detect pin - configure_pins( GPIO_Pin_CP, PIN_PORTD | PIN_INPUT | PIN_PULLUP ) ; + configure_pins( SD_PRESENT_GPIO_Pin, PIN_PORTD | PIN_INPUT | PIN_PULLUP ) ; disk_initialize( 0 ) ; sdInit() ; unlockFlash() ; @@ -859,7 +859,7 @@ extern uint8_t OptrexDisplay ; lcd_puts_Pleft( 0, "\006Boot Loader" ) ; #endif - if ( sd_card_ready() ) + if ( sdMounted() ) { #ifdef PCBSKY lcd_puts_Pleft( 0, "\014Ready" ) ; diff --git a/radio/bootloader/include/diskio.h b/radio/bootloader/include/diskio.h index b05e8073c..e091b709c 100644 --- a/radio/bootloader/include/diskio.h +++ b/radio/bootloader/include/diskio.h @@ -76,12 +76,11 @@ typedef enum { /*---------------------------------------*/ /* Prototypes for disk control functions */ -DSTATUS disk_initialize (BYTE); -DSTATUS disk_status (BYTE); - #ifdef __cplusplus extern "C" { #endif +DSTATUS disk_initialize (BYTE); +DSTATUS disk_status (BYTE); DRESULT disk_read (BYTE, BYTE*, DWORD, BYTE); DRESULT disk_write (BYTE, const BYTE*, DWORD, BYTE); DRESULT disk_ioctl (BYTE, BYTE, BYTE*); @@ -164,6 +163,7 @@ extern void sd_poll_10mS( void ) ; #ifdef PCBTARANIS extern void sdPoll10ms( void ) ; extern void sdInit( void ) ; +uint32_t sdMounted(void); #endif extern uint32_t sd_card_ready( void ) ; extern uint32_t sd_read_block( uint32_t block_no, uint32_t *data ) ; diff --git a/radio/bootloader/include/hal.h b/radio/bootloader/include/hal.h deleted file mode 100644 index 8bad5aa6e..000000000 --- a/radio/bootloader/include/hal.h +++ /dev/null @@ -1,254 +0,0 @@ -#ifndef _HAL_ -#define _HAL_ - -/* - * GPIOS - */ - -#define RCC_AHB1Periph_GPIOBUTTON (RCC_AHB1Periph_GPIOA|RCC_AHB1Periph_GPIOB|RCC_AHB1Periph_GPIOC|RCC_AHB1Periph_GPIOD|RCC_AHB1Periph_GPIOE) - -// Keys -#define PIN_BUTTON_PLUS GPIO_Pin_10 //SW3 PE.10 -#define PIN_BUTTON_MINUS GPIO_Pin_11 //SW2 PE.11 -#define PIN_BUTTON_ENTER GPIO_Pin_12 //SW1 PE.12 -#define PIN_BUTTON_MENU GPIO_Pin_7 //SW4 PD.07 -#define PIN_BUTTON_EXIT GPIO_Pin_2 //SW5 PD.02 -#define PIN_BUTTON_PAGE GPIO_Pin_3 //SW6 PD.03 - -// Trims -#define PIN_TRIM1_UP GPIO_Pin_3 //PC.03 -#define PIN_TRIM1_DN GPIO_Pin_2 //PC.02 -#define PIN_TRIM2_UP GPIO_Pin_1 //PC.01 -#define PIN_TRIM2_DN GPIO_Pin_13 //PC.13 -#define PIN_TRIM3_UP GPIO_Pin_4 //PE.04 -#define PIN_TRIM3_DN GPIO_Pin_3 //PE.03 -#define PIN_TRIM4_UP GPIO_Pin_6 //PE.06 -#define PIN_TRIM4_DN GPIO_Pin_5 //PE.05 - -// Switches -#if defined(REV3) -#define PIN_SW_A_L GPIO_Pin_14 //PE.14 -#define PIN_SW_B_H GPIO_Pin_3 //PB.03 -#define PIN_SW_B_L GPIO_Pin_4 //PB.04 -#define PIN_SW_C_H GPIO_Pin_5 //PB.05 -#define PIN_SW_C_L GPIO_Pin_6 //PB.06 -#define PIN_SW_D_H GPIO_Pin_7 //PB.07 -#define PIN_SW_D_L GPIO_Pin_2 //PE.02 -#define PIN_SW_E_H GPIO_Pin_0 //PB.00 -#define PIN_SW_E_L GPIO_Pin_5 //PA.05 -#define PIN_SW_F_H GPIO_Pin_7 //PE.07 -#define PIN_SW_F_L GPIO_Pin_1 //PB.01 -#define PIN_SW_G_H GPIO_Pin_9 //PE.09 -#define PIN_SW_G_L GPIO_Pin_8 //PE.08 -#define PIN_SW_H_L GPIO_Pin_13 //PE.13 -#else -#define PIN_SW_A_L GPIO_Pin_0 //PE.00 -#define PIN_SW_A_H GPIO_Pin_5 //PB.05 -#define PIN_SW_B_L GPIO_Pin_2 //PE.02 -#define PIN_SW_B_H GPIO_Pin_1 //PE.01 -#define PIN_SW_C_L GPIO_Pin_5 //PA.05 -#define PIN_SW_C_H GPIO_Pin_15 //PE.15 -#define PIN_SW_D_L GPIO_Pin_1 //PB.01 -#define PIN_SW_D_H GPIO_Pin_7 //PE.07 -#define PIN_SW_E_L GPIO_Pin_4 //PB.04 -#define PIN_SW_E_H GPIO_Pin_3 //PB.03 -#define PIN_SW_F GPIO_Pin_14 //PE.14 -#define PIN_SW_G_L GPIO_Pin_8 //PE.08 -#define PIN_SW_G_H GPIO_Pin_9 //PE.09 -#define PIN_SW_H GPIO_Pin_13 //PE.13 -#endif -// ADC -#define PIN_STK_J1 GPIO_Pin_0 //PA.00 -#define PIN_STK_J2 GPIO_Pin_1 //PA.01 -#define PIN_STK_J3 GPIO_Pin_2 //PA.02 -#define PIN_STK_J4 GPIO_Pin_3 //PA.03 -#define PIN_SLD_J1 GPIO_Pin_4 //PC.04 -#define PIN_SLD_J2 GPIO_Pin_5 //PC.05 -#define PIN_FLP_J1 GPIO_Pin_6 //PA.06 -#define PIN_FLP_J2 GPIO_Pin_0 //PB.00 -#define PIN_MVOLT GPIO_Pin_0 //PC.00 -#define RCC_AHB1Periph_GPIOADC RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOC - -// DAC -#define PIN_AUDIO_DAC GPIO_Pin_4 //PA.04 - -// Power_OFF Delay and LED -#define PIN_PWR_LED GPIO_Pin_6 //PC.06 -#define PIN_PWR_STATUS GPIO_Pin_1 //PD.01 -#define PIN_MCU_PWR GPIO_Pin_0 //PD.00 -#define RCC_AHB1Periph_GPIOPWR RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD -#define GPIOPWRLED GPIOC -#define GPIOPWR GPIOD -#define PIN_INT_RF_PWR GPIO_Pin_15 -#define PIN_EXT_RF_PWR GPIO_Pin_8 - - -// Smart-Port -#define PIN_SPORT_ON GPIO_Pin_4 //PD.04 -#define PIN_SPORT_TX GPIO_Pin_5 //PD.05 -#define PIN_SPORT_RX GPIO_Pin_6 //PD.06 - -// Trainer Port -#define GPIO_TR_INOUT GPIOC -#define PIN_TR_PPM_IN GPIO_Pin_8 //PC.08 -#define PIN_TR_PPM_OUT GPIO_Pin_9 //PC.09 -#define GPIOTRNDET GPIOA -#define PIN_TRNDET GPIO_Pin_8 - - - -// Cppm -#define RCC_AHB1Periph_GPIOCPPM RCC_AHB1Periph_GPIOA -#define RCC_AHB1Periph_GPIO_INTPPM RCC_AHB1Periph_GPIOA -#define PORT_INTPPM PIN_PORTA -#define GPIO_INTPPM GPIOA -#define PIN_INTPPM_OUT GPIO_Pin_10 //PA.10 -#define PIN_CPPM_OUT GPIO_Pin_8 //PA.08 -#define GPIOCPPM GPIOA -#define GPIO_PinSource_CPPM GPIO_PinSource8 -#define PIN_EXTPPM_OUT GPIO_Pin_7 //PA.07 -#define PORT_EXTPPM PIN_PORTA -#define GPIO_PinSource_EXTPPM GPIO_PinSource7 - -// Heart Beat -#define PIN_HEART_BEAT GPIO_Pin_7 //PC.07 - -// Update UART----RS232 ---UART3 -#define PIN_UPDATE_UART_TX GPIO_Pin_10 //PB.10 -#define PIN_UPDATE_UART_RX GPIO_Pin_11 //PB.11 - -// USB_OTG -#define PIN_FS_VBUS GPIO_Pin_9 //PA.09 -#define PIN_FS_ID GPIO_Pin_10 //PA.10 -#define PIN_FS_DM GPIO_Pin_11 //PA.11 -#define PIN_FS_DP GPIO_Pin_12 //PA.12 - -// BackLight PB8 -#define RCC_AHB1Periph_GPIOBL RCC_AHB1Periph_GPIOB -#define GPIO_Pin_BL GPIO_Pin_8 //PB.08 -#define GPIOBL GPIOB -#define GPIO_PinSource_BL GPIO_PinSource8 - -// LCD GPIOD 10-14 -#define RCC_AHB1Periph_LCD RCC_AHB1Periph_GPIOD -#define GPIO_LCD GPIOD -#define PIN_LCD_MOSI GPIO_Pin_10 //PD.10 -#define PIN_LCD_CLK GPIO_Pin_11 //PD.11 -#define PIN_LCD_NCS GPIO_Pin_14 //PD.14 -#define PIN_LCD_A0 GPIO_Pin_13 //PD.13 -#define PIN_LCD_RST GPIO_Pin_12 //pd12 test //RESET occurs when powered up,but should delay before initialize - -// Audio----I2S3 -//#define CODEC_I2S_ADDRESS 0x4000380C -#define CODEC_I2S SPI3 -#define CODEC_I2S_CLK RCC_APB1Periph_SPI3 -#define CODEC_I2S_GPIO_AF GPIO_AF_SPI3 -#define CODEC_I2S_IRQ SPI3_IRQn -#define CODEC_I2S_GPIO_CLOCK (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOC )//| RCC_AHB1Periph_GPIOE) -#define CODEC_I2S_WS_PIN GPIO_Pin_15 //PA.15 -#define CODEC_I2S_SCK_PIN GPIO_Pin_10 //PC.10 -#define CODEC_I2S_SD_PIN GPIO_Pin_12 //PC.12 -#define CODEC_I2S_MCK_PIN GPIO_Pin_6 //DISABLED -#define CODEC_I2S_WS_PINSRC GPIO_PinSource15 -#define CODEC_I2S_SCK_PINSRC GPIO_PinSource10 -#define CODEC_I2S_SD_PINSRC GPIO_PinSource12 -#define CODEC_I2S_MCK_PINSRC GPIO_PinSource6 -#define CODEC_I2S_GPIO GPIOC -#define CODEC_I2S_MCK_GPIO GPIOC -#define CODEC_I2S_WS_GPIO GPIOA -#define CODEC_I2S_MUTE GPIO_Pin_11 //PC.11 -//#define CODEC_I2S_FLT GPIO_Pin_ //IIR/FIR -//#define CODEC_I2S_MODE GPIO_Pin_ //Connect to GND=I2S_STANDARD - -// Eeprom 5137 -#define I2C_EE_GPIO GPIOB -#define I2C_EE_WP_GPIO GPIOB -#define I2C_EE_GPIO_CLK RCC_AHB1Periph_GPIOB -#define I2C_EE_SCL GPIO_Pin_6 //PB6 -#define I2C_EE_SDA GPIO_Pin_7 //PB7 -#define I2C_EE_WP GPIO_Pin_9 //PB9 - -// SD---spi2 -#define SPI_SD SPI2 -#define GPIO_AF_SD GPIO_AF_SPI2 -#define RCC_AHB1Periph_GPIO_CS RCC_AHB1Periph_GPIOB -#define GPIO_SPI_SD GPIOB -#define GPIO_Pin_SPI_SD_CS GPIO_Pin_12 //PB.12 -#define GPIO_Pin_SPI_SD_SCK GPIO_Pin_13 //PB.13 -#define GPIO_Pin_SPI_SD_MISO GPIO_Pin_14 //PB.14 -#define GPIO_Pin_SPI_SD_MOSI GPIO_Pin_15 //PB.15 -#define GPIO_PinSource_CS GPIO_PinSource12 -#define GPIO_PinSource_SCK GPIO_PinSource13 -#define GPIO_PinSource_MISO GPIO_PinSource14 -#define GPIO_PinSource_MOSI GPIO_PinSource15 -#define RCC_APBPeriphClockCmd_SPI_SD RCC_APB1PeriphClockCmd -#define RCC_APBPeriph_SPI_SD RCC_APB1Periph_SPI2 -#define RCC_AHBxPeriph_GPIO_WP RCC_AHB1Periph_GPIOD -#define RCC_AHBxPeriph_GPIO_CP RCC_AHB1Periph_GPIOD -#define GPIO_Mode_WP GPIO_Mode_OUT//lock? -#define GPIO_Mode_CP GPIO_Mode_IN // -#define GPIO_Pin_WP GPIO_Pin_8 //PD.08 -#define GPIO_Pin_CP GPIO_Pin_9 //PD.09 -#define GPIO_CTL_SD GPIOD - -// Audio----I2S3-----SPI3 -#define CODEC_MCLK_DISABLED -#define CODEC_USE_INT -//#define CODEC_USE_DMA -#define AudioFreq I2S_AudioFreq_44k - - -// EEPROM and CAT5137 -//#define EE_M24C08 /* Support the device: M24C08. */ -//#define EE_M24C64_32 /* Support the devices: M24C32 and M24C64 */ -#define I2C_Speed 200000 -#define I2C_FLASH_PAGESIZE 64 -#define I2C_EEPROM_ADDRESS 0xA2 -#define I2C_CAT5137_ADDRESS 0x5C //0101110 - -//#if defined (EE_M24C08) -// #define I2C_FLASH_PAGESIZE (16) -//#elif defined (EE_M24C64_32) -// #define I2C_FLASH_PAGESIZE (32) -//#endif - -//#ifdef EE_M24C64_32 -// #define EEPROM_HW_ADDRESS 0xA0 /* E0 = E1 = E2 = 0 */ -//#elif defined (EE_M24C08) -////#define EEPROM_Block0_ADDRESS 0xA0 /* 000*/ -//#define EEPROM_Block1_ADDRESS 0xA2 /* E3 E2 E1= 001 */ -////#define EEPROM_Block2_ADDRESS 0xA4 /* 010 */ -////#define EEPROM_Block3_ADDRESS 0xA6 /* 011 */ -//#endif - -//#define USE_CAT5137 /*Support the Volume Control*/ - -//#ifdef USE_CAT5137 -//#define I2C_CAT5137_ADDRESS 0x5C//0101110 -//#endif - -// SD card----SPI2 -// demo uses a command line option to define this (see Makefile): -// #define STM32_SD_USE_DMA -#ifdef STM32_SD_USE_DMA -// #warning "Information only: using DMA" -#pragma message "*** Using DMA ***" -#endif - -/* set to 1 to provide a disk_ioctrl function even if not needed by the FatFs */ -#define STM32_SD_DISK_IOCTRL_FORCE (0) - -#define CARD_SUPPLY_SWITCHABLE (0) //0power on not depend any IO -#define SOCKET_WP_CONNECTED (0) -#define SOCKET_CP_CONNECTED (0) - -#define SPI_BaudRatePrescaler_SPI_SD SPI_BaudRatePrescaler_4 // - for SPI1 and full-speed APB2: 60MHz/4 =15MHZ < 20MHZ - -// Selectable -// DMA -#define DMA_Channel_SPI_SD_RX DMA1_Channel2 -#define DMA_Channel_SPI_SD_TX DMA1_Channel3 -#define DMA_FLAG_SPI_SD_TC_RX DMA1_FLAG_TC2 -#define DMA_FLAG_SPI_SD_TC_TX DMA1_FLAG_TC3 - -#endif diff --git a/radio/bootloader/massstorage.cpp b/radio/bootloader/massstorage.cpp deleted file mode 100644 index 92d80ddf3..000000000 --- a/radio/bootloader/massstorage.cpp +++ /dev/null @@ -1,233 +0,0 @@ -/* - * Authors (alphabetical order) - * - Bertrand Songis - * - Bryan J. Rentoul (Gruvin) - * - Cameron Weeks - * - Erez Raviv - * - Jean-Pierre Parisy - * - Karl Szmutny - * - Michael Blandford - * - Michal Hlavinka - * - Pat Mackenzie - * - Philip Moss - * - Rob Thomson - * - Romolo Manfredini - * - Thomas Husterer - * - * open9x is based on code named - * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, - * er9x by Erez Raviv: http://code.google.com/p/er9x/, - * and the original (and ongoing) project by - * Thomas Husterer, th9x: http://code.google.com/p/th9x/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include "radio.h" -#include "board.h" -//#include "debug.h" -//#include "Audio.h" - -//#ifndef SIMU -//#include "CoOS.h" -//#endif - -#ifndef SIMU - -extern "C" { -#include "MSDDriver.h" -extern unsigned char MEDSdcard_Initialize(Media *media, unsigned char mciID); -} - -/** Size of one block in bytes. */ -#define BLOCK_SIZE 512 - -/** Size of the MSD IO buffer in bytes (6K, more the better). */ -#define MSD_BUFFER_SIZE (12*BLOCK_SIZE) - -/** LUN read/write buffer. */ -unsigned char msdBuffer[MSD_BUFFER_SIZE]; - -unsigned int msdReadTotal=0, msdWriteTotal=0; - -static void ConfigureUsbClock(void) -{ - /* Enable PLLB for USB */ - PMC->CKGR_PLLBR = CKGR_PLLBR_DIVB(1) - | CKGR_PLLBR_MULB(7) - | CKGR_PLLBR_PLLBCOUNT; - while((PMC->PMC_SR & PMC_SR_LOCKB) == 0); // TODO && (timeout++ < CLOCK_TIMEOUT)); - /* USB Clock uses PLLB */ - PMC->PMC_USB = PMC_USB_USBDIV(1) /* /2 */ - | PMC_USB_USBS; /* PLLB */ -} - -/** Maximum number of LUNs which can be defined. */ -#define MAX_LUNS 2 - -/** Media index for different disks */ -#define DRV_SDMMC 0 /** SD card */ -#define DRV_EEPROM 1 /** EEPROM */ - -Media medias[MAX_LUNS]; - - -/*---------------------------------------------------------------------------- - * Local variables - *----------------------------------------------------------------------------*/ - -#ifdef HID - -uint8_t hid_iBuffer[64] ; -uint8_t hid_oBuffer[64] ; - -static void hid_transfer() -{ - uint32_t dwCnt=0 ; - uint32_t dwLen ; - - dwLen = HIDDTransferDriver_Read( hid_iBuffer, 64 ) ; - if ( dwLen ) - { -// printf( "Data In(%u):", (unsigned int)dwLen ) ; -// _ShowBuffer( iBuffer, dwLen ) ; - -// bmLEDs = iBuffer[0] ; -// update = 1 ; - } - - dwLen = HIDDTransferDriver_ReadReport( iBuffer, 64 ) ; - if ( dwLen ) - { -// printf( "Report In(%u):", (unsigned int)dwLen ) ; -// _ShowBuffer( iBuffer, dwLen ) ; - -// bmLEDs = iBuffer[0] ; -// update = 1 ; - } - - oBuffer[0] = 0x80 ; - if ( PIO_Get( &pinsButtons[PUSHBUTTON_BP1]) == 0 ) - { - oBuffer[0] |= 0x01 ; - } - if ( PIO_Get( &pinsButtons[PUSHBUTTON_BP2] ) == 0 ) - { - oBuffer[0] |= 0x02 ; - } - - sprintf( (char*)&oBuffer[5], ":%04x:%05u!", (unsigned int)dwCnt, (unsigned int)dwCnt ) ; - oBuffer[1] = (uint8_t)(dwCnt) ; - oBuffer[2] = (uint8_t)(dwCnt >> 8) ; - oBuffer[3] = (uint8_t)(dwCnt >> 16) ; - oBuffer[4] = (uint8_t)(dwCnt >> 24) ; - if ( USBD_STATUS_SUCCESS == HIDDTransferDriver_Write( oBuffer, 64, 0, 0 ) ) - { - dwCnt ++ ; - } -} - -#endif - - - - -/** Device LUNs. */ -MSDLun luns[MAX_LUNS]; - -static void MSDCallbacks_Data( unsigned char flowDirection, unsigned int dataLength, - unsigned int fifoNullCount, unsigned int fifoFullCount ) -{ -#if 0 - if (flowDirection) - msdReadTotal += dataLength; - else - msdWriteTotal += dataLength; -#endif -} - -extern "C" unsigned char EEPROM_Initialize(Media *media, unsigned char mciID) ; -extern uint32_t sd_card_ready( void ) ; - -void usbMassStorage() -{ - static bool initialized = false ; - static bool active = false ; - - if ( PIOC->PIO_PDSR & 0x02000000 ) - { - // TRACE_DEBUG("usbMassStorage\n\r"); - - if (!initialized) - { - ConfigureUsbClock(); - /* Initialize LUN */ - MEDSdcard_Initialize(&(medias[DRV_SDMMC]), 0); - EEPROM_Initialize(&(medias[DRV_EEPROM]), 0); - LUN_Init(&(luns[DRV_SDMMC]), sd_card_ready() ? &(medias[DRV_SDMMC]) : 0 , - msdBuffer, MSD_BUFFER_SIZE, - 0, 0, 0, 0, - MSDCallbacks_Data); - - LUN_Init(&(luns[DRV_EEPROM]), &(medias[DRV_EEPROM]), - msdBuffer, MSD_BUFFER_SIZE, - 0, 0, 0, 0, - MSDCallbacks_Data); - - /* BOT driver initialization */ - MSDDriver_Initialize( luns, 2 ) ; - // VBus_Configure(); - USBD_Connect(); - initialized = true; - } - - if ( active == false ) - { -#ifndef BOOT - CoSchedLock() ; - if ( Voice.VoiceLock == 0 ) - { - Voice.VoiceLock = 1 ; -#endif - active = true ; -#ifndef BOOT - } - CoSchedUnlock() ; -#endif - } - if ( active ) - { - /* Mass storage state machine */ - for (uint8_t i=0; i<50; i++) - { -#ifdef HID - hid_transfer() ; -#endif - MSDDriver_StateMachine() ; - } - } - } - else - { - if ( active ) - { - active = false ; -#ifndef BOOT - Voice.VoiceLock = 0 ; -#endif - } - - msdReadTotal = 0; - msdWriteTotal = 0; - } -} - -#endif diff --git a/radio/bootloader/sdcard_driver.cpp b/radio/bootloader/sdcard_driver.cpp deleted file mode 100644 index c437a7f8b..000000000 --- a/radio/bootloader/sdcard_driver.cpp +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Authors (alphabetical order) - * - Bertrand Songis - * - Bryan J. Rentoul (Gruvin) - * - Cameron Weeks - * - Erez Raviv - * - Jean-Pierre Parisy - * - Karl Szmutny - * - Michael Blandford - * - Michal Hlavinka - * - Pat Mackenzie - * - Philip Moss - * - Rob Thomson - * - Romolo Manfredini - * - Thomas Husterer - * - * open9x is based on code named - * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, - * er9x by Erez Raviv: http://code.google.com/p/er9x/, - * and the original (and ongoing) project by - * Thomas Husterer, th9x: http://code.google.com/p/th9x/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include "diskio.h" -#include "radio.h" -#include "drivers.h" -#include "logicio.h" - -// SD Card routines - -#define MCI_INITIAL_SPEED 400000 - -void init_SDcard() -{ -#ifndef SIMU - configure_pins( 0xFC000000, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_C | PIN_PORTA | PIN_NO_PULLUP ) ; - configure_pins( PIO_PB7, PIN_INPUT | PIN_PORTB | PIN_NO_PULLUP | PIN_NO_PULLDOWN ) ; - - unsigned short clkDiv; - Hsmci *pMciHw = HSMCI ; - - /* Enable the MCI peripheral */ - PMC->PMC_PCER0 |= 1 << ID_HSMCI ; // Enable peripheral clock to HSMCI - pMciHw->HSMCI_CR = HSMCI_CR_SWRST; /* Reset the MCI */ - pMciHw->HSMCI_CR = HSMCI_CR_MCIDIS | HSMCI_CR_PWSDIS; /* Disable the MCI */ - pMciHw->HSMCI_IDR = 0xFFFFFFFF; /* Disable all the interrupts */ - pMciHw->HSMCI_DTOR = HSMCI_DTOR_DTOCYC_Msk | HSMCI_DTOR_DTOMUL_Msk ; /* Set the Data Timeout Register */ - pMciHw->HSMCI_CSTOR = HSMCI_CSTOR_CSTOCYC_Msk | HSMCI_CSTOR_CSTOMUL_Msk ; /* CSTOR ? */ - /* Set the Mode Register: 400KHz for MCK = 48MHz (CLKDIV = 58) */ - clkDiv = (Master_frequency / (MCI_INITIAL_SPEED * 2)) - 1; - pMciHw->HSMCI_MR = clkDiv | (7 << 8) ; - - /* Set the SDCard Register 1-bit, slot A */ - pMciHw->HSMCI_SDCR = HSMCI_SDCR_SDCSEL_SLOTA | HSMCI_SDCR_SDCBUS_1 ; - /* Enable the MCI and the Power Saving */ - pMciHw->HSMCI_CR = HSMCI_CR_MCIEN | HSMCI_CR_PWSEN ; - /* Configure MCI */ - pMciHw->HSMCI_CFG = HSMCI_CFG_FIFOMODE | ((1 << 4) & HSMCI_CFG_FERRCTRL); -#endif -} diff --git a/radio/bootloader/usbd_storage_msd.cpp b/radio/bootloader/usbd_storage_msd.cpp index 0f150a750..4aa3804d3 100644 --- a/radio/bootloader/usbd_storage_msd.cpp +++ b/radio/bootloader/usbd_storage_msd.cpp @@ -33,10 +33,13 @@ //#include #include "drivers.h" #include "../src/targets/taranis/i2c.h" - #include "diskio.h" //#include "board_taranis.h" +#include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_gpio.h" +#include "hal.h" +#define SD_CARD_PRESENT() (~SD_PRESENT_GPIO->IDR & SD_PRESENT_GPIO_Pin) + void I2C_EE_BufferWrite(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite) ; void eeprom_read_block (void *pointer_ram, uint16_t pointer_eeprom, size_t size); @@ -156,7 +159,7 @@ int8_t STORAGE_GetCapacity (uint8_t lun, uint32_t *block_num, uint32_t *block_si *block_num = EESIZE/BLOCKSIZE + 3 + 1024 ; } else { - if (socket_is_empty()) + if (!SD_CARD_PRESENT()) return -1; *block_size = BLOCKSIZE; @@ -186,7 +189,7 @@ int8_t STORAGE_IsReady (uint8_t lun) return 0; } else { - return !socket_is_empty() ? 0 : -1; + return SD_CARD_PRESENT() ? 0 : -1; } } diff --git a/radio/src/targets/taranis/board_taranis.h b/radio/src/targets/taranis/board_taranis.h index 64e437b12..f561e979d 100644 --- a/radio/src/targets/taranis/board_taranis.h +++ b/radio/src/targets/taranis/board_taranis.h @@ -37,6 +37,10 @@ #ifndef board_taranis_h #define board_taranis_h +#ifdef __cplusplus +extern "C" { +#endif + #include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rcc.h" #include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_gpio.h" #include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_spi.h" @@ -45,11 +49,6 @@ #include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dma.h" #include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_usart.h" #include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" - -#ifdef __cplusplus -extern "C" { -#endif - #include "STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_core.h" #include "STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_usr.h" #include "usbd_desc.h" @@ -86,7 +85,7 @@ extern uint16_t sessionTimer; #define SLAVE_MODE() (g_model.trainerMode == 1) #define TRAINER_CONNECTED() (GPIO_ReadInputDataBit(GPIOTRNDET, PIN_TRNDET) == Bit_RESET) -void delaysInit(); +void delaysInit(void); #define DEBUG_BAUDRATE 115200 #define SPORT_BAUDRATE 57600 diff --git a/radio/src/targets/taranis/diskio.cpp b/radio/src/targets/taranis/diskio.cpp index d9586804f..9d7a24b11 100644 --- a/radio/src/targets/taranis/diskio.cpp +++ b/radio/src/targets/taranis/diskio.cpp @@ -35,9 +35,10 @@ */ #include -#include "../FatFs/diskio.h" -#include "../FatFs/ff.h" -#include "../CoOS/kernel/CoOS.h" +#include "board_taranis.h" +#include "../../FatFs/diskio.h" +#include "../../FatFs/ff.h" +#include "../../CoOS/kernel/CoOS.h" #include "hal.h" /* Definitions for MMC/SDC command */ @@ -93,6 +94,7 @@ uint32_t transSpeed; */ /*-----------------------------------------------------------------------*/ /* Lock / unlock functions */ /*-----------------------------------------------------------------------*/ +#if !defined(BOOT) int ff_cre_syncobj (BYTE vol, _SYNC_t *mutex) { *mutex = CoCreateMutex(); @@ -114,6 +116,7 @@ int ff_del_syncobj (_SYNC_t mutex) { return 1; } +#endif static const DWORD socket_state_mask_cp = (1 << 0); static const DWORD socket_state_mask_wp = (1 << 1); @@ -124,7 +127,6 @@ DSTATUS Stat = STA_NOINIT; /* Disk status */ static volatile DWORD Timer1, Timer2; /* 100Hz decrement timers */ -static BYTE CardType; /* Card type flags */ enum speed_setting { INTERFACE_SLOW, INTERFACE_FAST }; @@ -655,7 +657,6 @@ DSTATUS disk_initialize ( /*-----------------------------------------------------------------------*/ /* Get Disk Status */ /*-----------------------------------------------------------------------*/ - DSTATUS disk_status ( BYTE drv /* Physical drive number (0) */ ) @@ -665,7 +666,6 @@ DSTATUS disk_status ( } - /*-----------------------------------------------------------------------*/ /* Read Sector(s) */ /*-----------------------------------------------------------------------*/ @@ -966,7 +966,14 @@ FATFS g_FATFS_Obj; FIL g_telemetryFile = {0}; #endif -void sdInit() +#if defined(BOOT) +void sdInit(void) +{ + f_mount(0, &g_FATFS_Obj); +} +#else +// TODO shouldn't be there! +void sdInit(void) { if (f_mount(0, &g_FATFS_Obj) == FR_OK) { referenceSystemAudioFiles(); @@ -989,6 +996,7 @@ void sdDone() f_mount(0, 0); // unmount SD } } +#endif uint32_t sdMounted() { diff --git a/radio/src/targets/taranis/hal.h b/radio/src/targets/taranis/hal.h index f559ae171..592feb2c7 100644 --- a/radio/src/targets/taranis/hal.h +++ b/radio/src/targets/taranis/hal.h @@ -307,7 +307,9 @@ #define STM32_SD_DISK_IOCTRL_FORCE 0 //DMA -#define STM32_SD_USE_DMA //Enable the DMA for SD +#if !defined(BOOT) +#define STM32_SD_USE_DMA //Enable the DMA for SD +#endif #ifdef STM32_SD_USE_DMA #define DMA_Channel_SPI_SD_RX DMA1_Stream3 From dc3ea6b5554ad4631387c22b6124807ac58017eb Mon Sep 17 00:00:00 2001 From: bsongis Date: Tue, 4 Mar 2014 17:56:52 +0100 Subject: [PATCH 024/285] one more file removed --- radio/bootloader/i2c_ee.cpp | 416 ------------------------------------ 1 file changed, 416 deletions(-) delete mode 100644 radio/bootloader/i2c_ee.cpp diff --git a/radio/bootloader/i2c_ee.cpp b/radio/bootloader/i2c_ee.cpp deleted file mode 100644 index def61280a..000000000 --- a/radio/bootloader/i2c_ee.cpp +++ /dev/null @@ -1,416 +0,0 @@ -/** - ****************************************************************************** - * @file Project/ee_drivers/i2c_ee.c - * @author X9D Application Team - * @version V 0.2 - * @date 12-JULY-2012 - * @brief This file provides a set of functions needed to manage the - * communication between I2C peripheral and I2C M24CXX EEPROM. - CAT5137 added,share the I2C. - ****************************************************************************** -*/ - - -#include "radio.h" -#include "stm32f2xx.h" -#include "logicio.h" -#include "stm32f2xx_rcc.h" -#include "hal.h" -#include "i2c_ee.h" -#include "timers.h" - - -#define I2C_delay() hw_delay( 100 ) - -/** - * @brief Configure the used I/O ports pin - * @param None - * @retval None - */ -static void I2C_GPIO_Configuration(void) -{ - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN ; // Enable portB clock - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOEEN ; // Enable portE clock - -// GPIO_InitTypeDef GPIO_InitStructure; - - GPIOB->BSRRH =I2C_EE_WP; //PB9 - configure_pins( I2C_EE_WP, PIN_OUTPUT | PIN_OS50 | PIN_PORTB | PIN_PUSHPULL | PIN_NO_PULL ) ; - -// GPIO_InitStructure.GPIO_Pin = I2C_EE_WP; -// GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; -// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; -// GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; -// GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; -// GPIO_Init(I2C_EE_WP_GPIO, &GPIO_InitStructure); - - /* Configure I2C_EE pins: SCL and SDA */ - configure_pins( I2C_EE_SCL | I2C_EE_SDA, PIN_OUTPUT | PIN_OS50 | PIN_PORTB | PIN_ODRAIN | PIN_PULLUP ) ; -// GPIO_InitStructure.GPIO_Pin = I2C_EE_SCL | I2C_EE_SDA;//PE0,PE1 -// GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; -// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; -// GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; -// GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; -// GPIO_Init(I2C_EE_GPIO, &GPIO_InitStructure); - - //Set Idle levels - SDA_H; - SCL_H; - WP_L ; -} - -short I2C_START() -{ - SDA_H; - I2C_delay(); - SCL_H; - I2C_delay(); - // if (!SDA_read) return 0; - SDA_L; - I2C_delay(); - // if (SDA_read) return 0; - SCL_L; - I2C_delay(); - return 1; -} - -void I2C_STOP() -{ - SCL_L; - I2C_delay(); - SDA_L; - I2C_delay(); - SCL_H; - I2C_delay(); - SDA_H; - I2C_delay(); -} - -void I2C_ACK() -{ - SCL_L; - I2C_delay(); - SDA_L; - I2C_delay(); - SCL_H; - I2C_delay(); - SCL_L; - I2C_delay(); -} -void I2C_NO_ACK() -{ - SCL_L; - I2C_delay(); - SDA_H; - I2C_delay(); - SCL_H; - I2C_delay(); - SCL_L; - I2C_delay(); -} - -short I2C_WAIT_ACK() -{ - short i=50; - SCL_L; - I2C_delay(); - SDA_H; - I2C_delay(); - SCL_H; - I2C_delay(); - while(i) { - if(SDA_read) { - I2C_delay(); - i--; - } - else { - i=2; - break; - } - } - SCL_L; - I2C_delay(); - - return i; -} - -void I2C_SEND_DATA(char SendByte) -{ - short i=8; - while (i--) { - SCL_L; -// I2C_delay(); - if (SendByte & 0x80) - SDA_H; - else - SDA_L; - SendByte <<= 1; - I2C_delay(); - SCL_H; - I2C_delay(); - } - SCL_L; - I2C_delay(); -} - -char I2C_READ() -{ - short i=8; - char ReceiveByte=0; - - SDA_H; - while (i--) { - ReceiveByte <<= 1; - SCL_L; - I2C_delay(); - SCL_H; - I2C_delay(); - if (SDA_read) { - ReceiveByte|=0x01; - } - } - SCL_L; - return ReceiveByte; -} - -void I2C_EE_Init() -{ - /* GPIO Periph clock enable */ - RCC_AHB1PeriphClockCmd(I2C_EE_GPIO_CLK, ENABLE); - - /* GPIO configuration */ - I2C_GPIO_Configuration(); -} - -void I2C_set_volume( register uint8_t volume ) -{ - I2C_START(); - I2C_SEND_DATA(I2C_CAT5137_ADDRESS|EE_CMD_WRITE); - I2C_WAIT_ACK(); - I2C_SEND_DATA(0); - I2C_WAIT_ACK(); - I2C_SEND_DATA(volume); - I2C_WAIT_ACK(); - I2C_STOP(); -} - -uint8_t I2C_read_volume() -{ - uint8_t volume ; - I2C_START(); - I2C_SEND_DATA(I2C_CAT5137_ADDRESS|EE_CMD_WRITE); - I2C_WAIT_ACK(); - I2C_SEND_DATA(0); - I2C_WAIT_ACK(); - I2C_START(); - I2C_SEND_DATA(I2C_CAT5137_ADDRESS|EE_CMD_READ); - I2C_WAIT_ACK(); - volume = I2C_READ(); - I2C_NO_ACK(); - I2C_STOP(); - return volume ; -} - -/** - * @brief Writes one byte to the I2C EEPROM. - * @param pBuffer : pointer to the buffer containing the data to be - * written to the EEPROM. - * @param WriteAddr : EEPROM's internal address to write to. - * @retval None - */ -void I2C_EE_ByteWrite(uint8_t* pBuffer, uint16_t WriteAddr) -{ - I2C_START(); - I2C_SEND_DATA(I2C_EEPROM_ADDRESS|EE_CMD_WRITE); - I2C_WAIT_ACK(); -#ifdef EE_M24C08 - I2C_SEND_DATA(WriteAddr); - I2C_WAIT_ACK(); -#else - I2C_SEND_DATA((uint8_t)((WriteAddr&0xFF00)>>8) ); - I2C_WAIT_ACK(); - I2C_SEND_DATA((uint8_t)(WriteAddr&0xFF)); - I2C_WAIT_ACK(); -#endif - I2C_SEND_DATA(*pBuffer); - I2C_WAIT_ACK(); - I2C_STOP(); -} - -/** - * @brief Reads a block of data from the EEPROM. - * @param pBuffer : pointer to the buffer that receives the data read - * from the EEPROM. - * @param ReadAddr : EEPROM's internal address to read from. - * @param NumByteToRead : number of bytes to read from the EEPROM. - * @retval None - */ -void I2C_EE_BufferRead(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t NumByteToRead) -{ - I2C_START(); - I2C_SEND_DATA(I2C_EEPROM_ADDRESS|EE_CMD_WRITE); - I2C_WAIT_ACK(); -#ifdef EE_M24C08 - I2C_SEND_DATA(ReadAddr); - I2C_WAIT_ACK(); -#else - I2C_SEND_DATA((uint8_t)((ReadAddr & 0xFF00) >> 8)); - I2C_WAIT_ACK(); - I2C_SEND_DATA((uint8_t)(ReadAddr & 0x00FF)); - I2C_WAIT_ACK(); -#endif - - I2C_START(); - I2C_SEND_DATA(I2C_EEPROM_ADDRESS|EE_CMD_READ); - I2C_WAIT_ACK(); - while (NumByteToRead) { - if (NumByteToRead == 1) { - *pBuffer =I2C_READ(); - I2C_NO_ACK(); - I2C_STOP(); - } - else { - *pBuffer =I2C_READ(); - I2C_ACK(); - pBuffer++; - } - NumByteToRead--; - } -} - -/** - * @brief Writes buffer of data to the I2C EEPROM. - * @param pBuffer : pointer to the buffer containing the data to be - * written to the EEPROM. - * @param WriteAddr : EEPROM's internal address to write to. - * @param NumByteToWrite : number of bytes to write to the EEPROM. - * @retval None - */ -void I2C_EE_BufferWrite(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite) -{ - uint8_t NumOfPage = 0, NumOfSingle = 0, count = 0; - uint16_t Addr = 0; - - Addr = WriteAddr % I2C_FLASH_PAGESIZE; - count = I2C_FLASH_PAGESIZE - Addr; - NumOfPage = NumByteToWrite / I2C_FLASH_PAGESIZE; - NumOfSingle = NumByteToWrite % I2C_FLASH_PAGESIZE; - - /* If WriteAddr is I2C_FLASH_PAGESIZE aligned */ - if (Addr == 0) { - /* If NumByteToWrite < I2C_FLASH_PAGESIZE */ - if (NumOfPage == 0) { - I2C_EE_PageWrite(pBuffer, WriteAddr, NumOfSingle); - - I2C_EE_WaitEepromStandbyState(); - } - /* If NumByteToWrite > I2C_FLASH_PAGESIZE */ - else { - while (NumOfPage--) { - I2C_EE_PageWrite(pBuffer, WriteAddr, I2C_FLASH_PAGESIZE); - I2C_EE_WaitEepromStandbyState(); - WriteAddr += I2C_FLASH_PAGESIZE; - pBuffer += I2C_FLASH_PAGESIZE; - } - - if (NumOfSingle != 0) { - I2C_EE_PageWrite(pBuffer, WriteAddr, NumOfSingle); - I2C_EE_WaitEepromStandbyState(); - } - } - } - /* If WriteAddr is not I2C_FLASH_PAGESIZE aligned */ - else { - /* If NumByteToWrite < I2C_FLASH_PAGESIZE */ - if (NumOfPage== 0) { - /* If the number of data to be written is more than the remaining space - in the current page: */ - if (NumByteToWrite > count) { - /* Write the data conained in same page */ - I2C_EE_PageWrite(pBuffer, WriteAddr, count); - I2C_EE_WaitEepromStandbyState(); - - /* Write the remaining data in the following page */ - I2C_EE_PageWrite((uint8_t*)(pBuffer + count), (WriteAddr + count), (NumByteToWrite - count)); - I2C_EE_WaitEepromStandbyState(); - } - else { - I2C_EE_PageWrite(pBuffer, WriteAddr, NumOfSingle); - I2C_EE_WaitEepromStandbyState(); - } - } - /* If NumByteToWrite > I2C_FLASH_PAGESIZE */ - else { - NumByteToWrite -= count; - NumOfPage = NumByteToWrite / I2C_FLASH_PAGESIZE; - NumOfSingle = NumByteToWrite % I2C_FLASH_PAGESIZE; - - if (count != 0) { - I2C_EE_PageWrite(pBuffer, WriteAddr, count); - I2C_EE_WaitEepromStandbyState(); - WriteAddr += count; - pBuffer += count; - } - - while (NumOfPage--) { - I2C_EE_PageWrite(pBuffer, WriteAddr, I2C_FLASH_PAGESIZE); - I2C_EE_WaitEepromStandbyState(); - WriteAddr += I2C_FLASH_PAGESIZE; - pBuffer += I2C_FLASH_PAGESIZE; - } - if (NumOfSingle != 0) { - I2C_EE_PageWrite(pBuffer, WriteAddr, NumOfSingle); - I2C_EE_WaitEepromStandbyState(); - } - } - } -} - -/** - * @brief Writes more than one byte to the EEPROM with a single WRITE cycle. - * @note The number of byte can't exceed the EEPROM page size. - * @param pBuffer : pointer to the buffer containing the data to be - * written to the EEPROM. - * @param WriteAddr : EEPROM's internal address to write to. - * @param NumByteToWrite : number of bytes to write to the EEPROM. - * @retval None - */ -void I2C_EE_PageWrite(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t NumByteToWrite) -{ - I2C_START(); - I2C_SEND_DATA(I2C_EEPROM_ADDRESS|EE_CMD_WRITE); - I2C_WAIT_ACK(); - -#ifdef EE_M24C08 - I2C_SEND_DATA(WriteAddr); - I2C_WAIT_ACK(); -#else - I2C_SEND_DATA((uint8_t)((WriteAddr & 0xFF00) >> 8)); - I2C_WAIT_ACK(); - I2C_SEND_DATA((uint8_t)(WriteAddr & 0x00FF)); - I2C_WAIT_ACK(); -#endif /* EE_M24C08 */ - - /* While there is data to be written */ - while (NumByteToWrite--) { - I2C_SEND_DATA(*pBuffer); - I2C_WAIT_ACK(); - pBuffer++; - } - I2C_STOP(); -} - -/** - * @brief Wait for EEPROM Standby state - * @param None - * @retval None - */ -void I2C_EE_WaitEepromStandbyState(void) -{ - do { - I2C_START(); - I2C_SEND_DATA(I2C_EEPROM_ADDRESS|EE_CMD_WRITE); - } while (0 == I2C_WAIT_ACK()); - - I2C_STOP(); -} From 9cdd1752502c496e94a51f9f5860065c109cfad2 Mon Sep 17 00:00:00 2001 From: bsongis Date: Tue, 4 Mar 2014 17:58:57 +0100 Subject: [PATCH 025/285] 4 more files removed --- radio/bootloader/include/MSD.h | 233 ---------- radio/bootloader/include/MSDDriver.h | 75 --- radio/bootloader/include/MSDLun.h | 161 ------- radio/bootloader/include/SBC.h | 653 --------------------------- 4 files changed, 1122 deletions(-) delete mode 100644 radio/bootloader/include/MSD.h delete mode 100644 radio/bootloader/include/MSDDriver.h delete mode 100644 radio/bootloader/include/MSDLun.h delete mode 100644 radio/bootloader/include/SBC.h diff --git a/radio/bootloader/include/MSD.h b/radio/bootloader/include/MSD.h deleted file mode 100644 index 23a934d35..000000000 --- a/radio/bootloader/include/MSD.h +++ /dev/null @@ -1,233 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Mass Storage class definitions. -/// -/// See -/// - -/// USB Mass Storage Class Spec. Overview -/// - -/// USB Mass Storage Class Bulk-Only Transport -/// -/// !Usage -/// -/// -# Uses "MSD Requests" to check incoming requests from USB Host. -/// -# Uses "MSD Subclass Codes" and "MSD Protocol Codes" to fill %device -/// interface descriptors for a MSD %device. -/// -# Handle the incoming Bulk data with "MSD CBW Definitions" and MSCbw -/// structure. -/// -# Prepare the outgoing Bulk data with "MSD CSW Definitions" and MSCsw -/// structure. -//------------------------------------------------------------------------------ - -#ifndef MSD_H -#define MSD_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Requests" -/// This page lists MSD-specific requests ( Actually for Bulk-only protocol ). -/// -/// !Requests -/// - MSD_BULK_ONLY_RESET -/// - MSD_GET_MAX_LUN - -/// Reset the mass storage %device and its associated interface. -#define MSD_BULK_ONLY_RESET 0xFF -/// Return the maximum LUN number supported by the %device. -#define MSD_GET_MAX_LUN 0xFE -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Subclass Codes" -/// This page lists the Subclass Codes for bInterfaceSubClass field. -/// (Table 2.1, USB Mass Storage Class Spec. Overview) -/// -/// !SubClasses -/// - MSD_SUBCLASS_RBC -/// - MSD_SUBCLASS_SFF_MCC -/// - MSD_SUBCLASS_QIC -/// - MSD_SUBCLASS_UFI -/// - MSD_SUBCLASS_SFF -/// - MSD_SUBCLASS_SCSI - -/// Reduced Block Commands (RBC) T10 -#define MSD_SUBCLASS_RBC 0x01 -/// C/DVD devices -#define MSD_SUBCLASS_SFF_MCC 0x02 -/// Tape device -#define MSD_SUBCLASS_QIC 0x03 -/// Floppy disk drive (FDD) device -#define MSD_SUBCLASS_UFI 0x04 -/// Floppy disk drive (FDD) device -#define MSD_SUBCLASS_SFF 0x05 -/// SCSI transparent command set -#define MSD_SUBCLASS_SCSI 0x06 -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -/// \page "MSD Protocol Codes" -/// This page lists the Transport Protocol codes for MSD. -/// (Table 3.1, USB Mass Storage Class Spec. Overview) -/// -/// !Protocols -/// - MSD_PROTOCOL_CBI_COMPLETION -/// - MSD_PROTOCOL_CBI -/// - MSD_PROTOCOL_BULK_ONLY - -/// Control/Bulk/Interrupt (CBI) Transport (with command complete interrupt) -#define MSD_PROTOCOL_CBI_COMPLETION 0x00 -/// Control/Bulk/Interrupt (CBI) Transport (no command complete interrupt) -#define MSD_PROTOCOL_CBI 0x01 -/// Bulk-Only Transport -#define MSD_PROTOCOL_BULK_ONLY 0x50 -//------------------------------------------------------------------------------ - -/// Test unit control: -#define CTRL_NOT_READY 0x00 -#define CTRL_GOOD 0x01 -#define CTRL_BUSY 0x02 - -//------------------------------------------------------------------------------ -/// \page "MSD CBW Definitions" -/// This page lists the Command Block Wrapper (CBW) definitions. -/// -/// !Constants -/// - MSD_CBW_SIZE -/// - MSD_CBW_SIGNATURE -/// -/// !Fields -/// - MSD_CBW_DEVICE_TO_HOST - -/// Command Block Wrapper Size -#define MSD_CBW_SIZE 31 -/// 'USBC' 0x43425355 -#define MSD_CBW_SIGNATURE 0x43425355 - -/// CBW bmCBWFlags field -#define MSD_CBW_DEVICE_TO_HOST (1 << 7) -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD CSW Definitions" -/// This page lists the Command Status Wrapper (CSW) definitions. -/// -/// !Constants -/// - MSD_CSW_SIZE -/// - MSD_CSW_SIGNATURE -/// -/// !Command Block Status Values -/// (Table 5.3 , USB Mass Storage Class Bulk-Only Transport) -/// - MSD_CSW_COMMAND_PASSED -/// - MSD_CSW_COMMAND_FAILED -/// - MSD_CSW_PHASE_ERROR - -/// Command Status Wrapper Size -#define MSD_CSW_SIZE 13 -/// 'USBS' 0x53425355 -#define MSD_CSW_SIGNATURE 0x53425355 - -/// Command Passed (good status) -#define MSD_CSW_COMMAND_PASSED 0 -/// Command Failed -#define MSD_CSW_COMMAND_FAILED 1 -/// Phase Error -#define MSD_CSW_PHASE_ERROR 2 -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// Structures -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Command Block Wrapper (CBW), -/// See Table 5.1, USB Mass Storage Class Bulk-Only Transport. -/// -/// The CBW shall start on a packet boundary and shall end as a -/// short packet with exactly 31 (1Fh) bytes transferred. -//------------------------------------------------------------------------------ -typedef struct { - - /// 'USBC' 0x43425355 (little endian) - unsigned int dCBWSignature; - /// Must be the same as dCSWTag - unsigned int dCBWTag; - /// Number of bytes transfer - unsigned int dCBWDataTransferLength; - /// Indicates the directin of the transfer: - /// 0x80=IN=device-to-host, - /// 0x00=OUT=host-to-device - unsigned char bmCBWFlags; - /// bits 0->3: bCBWLUN - unsigned char bCBWLUN :4, - bReserved1:4; /// reserved - /// bits 0->4: bCBWCBLength - unsigned char bCBWCBLength:5, - bReserved2 :3; /// reserved - /// Command block - unsigned char pCommand[16]; - -} MSCbw; - -//------------------------------------------------------------------------------ -/// Command Status Wrapper (CSW), -/// See Table 5.2, USB Mass Storage Class Bulk-Only Transport. -//------------------------------------------------------------------------------ -typedef struct -{ - /// 'USBS' 0x53425355 (little endian) - unsigned int dCSWSignature; - /// Must be the same as dCBWTag - unsigned int dCSWTag; - /// For Data-Out the device shall report in the dCSWDataResidue the - /// difference between the amount of data expected as stated in the - /// dCBWDataTransferLength, and the actual amount of data processed by - /// the device. For Data-In the device shall report in the dCSWDataResidue - /// the difference between the amount of data expected as stated in the - /// dCBWDataTransferLength and the actual amount of relevant data sent by - /// the device. The dCSWDataResidue shall not exceed the value sent in the - /// dCBWDataTransferLength. - unsigned int dCSWDataResidue; - /// Indicates the success or failure of the command. - unsigned char bCSWStatus; - -} MSCsw; - -#endif //#ifndef MSD_H - diff --git a/radio/bootloader/include/MSDDriver.h b/radio/bootloader/include/MSDDriver.h deleted file mode 100644 index 30e6b087c..000000000 --- a/radio/bootloader/include/MSDDriver.h +++ /dev/null @@ -1,75 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Mass storage %device driver implementation. -/// -/// !Usage -/// -/// -# Enable and setup USB related pins (see pio & board.h). -/// -# Configure the memory interfaces used for Mass Storage LUNs -/// (see memories, MSDLun.h). -/// -# Configure the USB MSD %driver using MSDDriver_Initialize. -/// -# Invoke MSDDriver_StateMachine in main loop to handle all Mass Storage -/// operations. -//------------------------------------------------------------------------------ - -#ifndef MSDDRIVER_H -#define MSDDRIVER_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "MSD.h" -#include "MSDLun.h" -// #include - -//------------------------------------------------------------------------------ -// Global functions -//------------------------------------------------------------------------------ - -extern void MSDDriver_Initialize(MSDLun *luns, unsigned char numLuns); - -extern void MSDDriver_RequestHandler(const USBGenericRequest *request); - -extern void MSDDriver_StateMachine(void); - -extern void MSDDriver_RemoteWakeUp(void); - -extern void MSDDriver_DataCallback(unsigned char isRead, - unsigned int dataLength, - unsigned int nullCnt, - unsigned int fullCnt); - -#endif // #ifndef MSDDRIVER_H - diff --git a/radio/bootloader/include/MSDLun.h b/radio/bootloader/include/MSDLun.h deleted file mode 100644 index 799775541..000000000 --- a/radio/bootloader/include/MSDLun.h +++ /dev/null @@ -1,161 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Logical Unit Number (LUN) used by the Mass Storage driver and the SCSI -/// protocol. Represents a logical hard-drive. -/// -/// !Usage -/// -# Initialize Memory related pins (see pio & board.h). -/// -# Initialize a Media instance for the LUN (see memories). -/// -# Initlalize the LUN with LUN_Init, and link to the initialized Media. -/// -# To read data from the LUN linked media, uses LUN_Read. -/// -# To write data to the LUN linked media, uses LUN_Write. -/// -# To unlink the media, uses LUN_Eject. -//------------------------------------------------------------------------------ - -#ifndef MSDLUN_H -#define MSDLUN_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "SBC.h" -#include -#include -#include - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -/// LUN RC: success -#define LUN_STATUS_SUCCESS 0x00 -/// LUN RC: error -#define LUN_STATUS_ERROR 0x02 - -/// Media of LUN is removed -#define LUN_NOT_PRESENT 0x00 -/// LUN is ejected by host -#define LUN_EJECTED 0x01 -/// Media of LUN is changed -#define LUN_CHANGED 0x10 -/// LUN Not Ready to Ready transition -#define LUN_TRANS_READY LUN_CHANGED -/// Media of LUN is ready -#define LUN_READY 0x11 - -//------------------------------------------------------------------------------ -// Structures -//------------------------------------------------------------------------------ - -/// LUN structure -typedef struct { - - /// Pointer to a SBCInquiryData instance. - SBCInquiryData *inquiryData; - /// Fifo for USB transfer, must be assigned. - MSDIOFifo ioFifo; - /// Pointer to Media instance for the LUN. - Media *media; - /// Pointer to a Monitor Function to analyze the flow of LUN. - /// \param flowDirection 1 - device to host (READ10) - /// 0 - host to device (WRITE10) - /// \param dataLength Length of data transferred in bytes. - /// \param fifoNullCount Times that FIFO is NULL to wait - /// \param fifoFullCount Times that FIFO is filled to wait - void (*dataMonitor)(unsigned char flowDirection, - unsigned int dataLength, - unsigned int fifoNullCount, - unsigned int fifoFullCount); - /// The start position of the media (blocks) allocated to the LUN. - unsigned int baseAddress; - /// The size of the media (blocks) allocated to the LUN. - unsigned int size; - /// Sector size of the media in number of media blocks - unsigned short blockSize; - /// The LUN can be readonly even the media is writable -#ifdef __cplusplus - unsigned char protectd; -#else - unsigned char protected; -#endif - - /// The LUN status (Ejected/Changed/) - unsigned char status; - - /// Data for the RequestSense command. - SBCRequestSenseData requestSenseData; - /// Data for the ReadCapacity command. - SBCReadCapacity10Data readCapacityData; - -} MSDLun; - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -extern void LUN_Init(MSDLun *lun, - Media *media, - unsigned char *ioBuffer, - unsigned int ioBufferSize, - unsigned int baseAddress, - unsigned int size, - unsigned short blockSize, -#ifdef __cplusplus - unsigned char protectd, -#else - unsigned char protected, -#endif - void (*dataMonitor)(unsigned char flowDirection, - unsigned int dataLength, - unsigned int fifoNullCount, - unsigned int fifoFullCount)); - -extern unsigned char LUN_Eject(MSDLun *lun); - -extern unsigned char LUN_Write(MSDLun *lun, - unsigned int blockAddress, - void *data, - unsigned int length, - TransferCallback callback, - void *argument); - -extern unsigned char LUN_Read(MSDLun *lun, - unsigned int blockAddress, - void *data, - unsigned int length, - TransferCallback callback, - void *argument); - -#endif //#ifndef MSDLUN_H - diff --git a/radio/bootloader/include/SBC.h b/radio/bootloader/include/SBC.h deleted file mode 100644 index 3c3f93c69..000000000 --- a/radio/bootloader/include/SBC.h +++ /dev/null @@ -1,653 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// SCSI definitions. -/// -/// !Usage -/// -/// -# After command block received, Access and decode the SCSI command block -/// with SBCCommand structure. -//------------------------------------------------------------------------------ - -#ifndef SBC_H -#define SBC_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Operation Codes" -/// This page lists operation codes of commands described in the SBC-3 -/// standard. -/// -/// \note That most commands are actually defined in other standards, -/// like SPC-4. Optional commands are not included here. -/// -/// \see sbc3r07.pdf - Section 5.1 - Table 12 -/// \see spc4r06.pdf -/// \see SBCCommand -/// -/// !Codes -/// - SBC_INQUIRY -/// - SBC_READ_10 -/// - SBC_READ_CAPACITY_10 -/// - SBC_REQUEST_SENSE -/// - SBC_TEST_UNIT_READY -/// - SBC_WRITE_10 -/// -/// !Optional Codes but required by Windows -/// - SBC_PREVENT_ALLOW_MEDIUM_REMOVAL -/// - SBC_MODE_SENSE_6 -/// - SBC_VERIFY_10 -/// - SBC_READ_FORMAT_CAPACITIES - -/// Request information regarding parameters of the target and Logical Unit. -#define SBC_INQUIRY 0x12 -/// Request the transfer data to the host. -#define SBC_READ_10 0x28 -/// Request capacities of the currently installed medium. -#define SBC_READ_CAPACITY_10 0x25 -/// Request that the device server transfer sense data. -#define SBC_REQUEST_SENSE 0x03 -/// Check if the LUN is ready -#define SBC_TEST_UNIT_READY 0x00 -/// Request that the device write the data transferred by the host. -#define SBC_WRITE_10 0x2A - -/// Request that the target enable or disable the removal of the medium in -/// the Logical Unit. -#define SBC_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E -/// Report parameters. -#define SBC_MODE_SENSE_6 0x1A -/// Request that the %device verify the data on the medium. -#define SBC_VERIFY_10 0x2F -/// Request a list of the possible capacities that can be formatted on medium -#define SBC_READ_FORMAT_CAPACITIES 0x23 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Periph. Qualifiers" -/// This page lists the peripheral qualifier values specified in the INQUIRY -/// data -/// \see spc4r06.pdf - Section 6.4.2 - Table 83 -/// \see SBCInquiryData -/// -/// !Qualifiers -/// - SBC_PERIPHERAL_DEVICE_CONNECTED -/// - SBC_PERIPHERAL_DEVICE_NOT_CONNECTED -/// - SBC_PERIPHERAL_DEVICE_NOT_SUPPORTED - -#define SBC_PERIPHERAL_DEVICE_CONNECTED 0x00 -#define SBC_PERIPHERAL_DEVICE_NOT_CONNECTED 0x01 -#define SBC_PERIPHERAL_DEVICE_NOT_SUPPORTED 0x03 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Periph. Types" -/// This page lists peripheral device types specified in the INQUIRY data -/// \see spc4r06.pdf - Section 6.4.2 - Table 84 -/// \see SBCInquiryData -/// -/// !Types -/// - SBC_DIRECT_ACCESS_BLOCK_DEVICE -/// - SBC_SEQUENTIAL_ACCESS_DEVICE -/// - SBC_PRINTER_DEVICE -/// - SBC_PROCESSOR_DEVICE -/// - SBC_WRITE_ONCE_DEVICE -/// - SBC_CD_DVD_DEVICE -/// - SBC_SCANNER_DEVICE -/// - SBC_OPTICAL_MEMORY_DEVICE -/// - SBC_MEDIA_CHANGER_DEVICE -/// - SBC_COMMUNICATION_DEVICE -/// - SBC_STORAGE_ARRAY_CONTROLLER_DEVICE -/// - SBC_ENCLOSURE_SERVICES_DEVICE -/// - SBC_SIMPLIFIED_DIRECT_ACCESS_DEVICE -/// - SBC_OPTICAL_CARD_READER_WRITER_DEVICE -/// - SBC_BRIDGE_CONTROLLER_COMMANDS -/// - SBC_OBJECT_BASED_STORAGE_DEVICE - -#define SBC_DIRECT_ACCESS_BLOCK_DEVICE 0x00 -#define SBC_SEQUENTIAL_ACCESS_DEVICE 0x01 -#define SBC_PRINTER_DEVICE 0x02 -#define SBC_PROCESSOR_DEVICE 0x03 -#define SBC_WRITE_ONCE_DEVICE 0x04 -#define SBC_CD_DVD_DEVICE 0x05 -#define SBC_SCANNER_DEVICE 0x06 -#define SBC_OPTICAL_MEMORY_DEVICE 0x07 -#define SBC_MEDIA_CHANGER_DEVICE 0x08 -#define SBC_COMMUNICATION_DEVICE 0x09 -#define SBC_STORAGE_ARRAY_CONTROLLER_DEVICE 0x0C -#define SBC_ENCLOSURE_SERVICES_DEVICE 0x0D -#define SBC_SIMPLIFIED_DIRECT_ACCESS_DEVICE 0x0E -#define SBC_OPTICAL_CARD_READER_WRITER_DEVICE 0x0F -#define SBC_BRIDGE_CONTROLLER_COMMANDS 0x10 -#define SBC_OBJECT_BASED_STORAGE_DEVICE 0x11 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \brief Version value for the SBC-3 specification -/// \see spc4r06.pdf - Section 6.4.2 - Table 85 -#define SBC_SPC_VERSION_4 0x06 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \brief Values for the TPGS field returned in INQUIRY data -/// \see spc4r06.pdf - Section 6.4.2 - Table 86 -#define SBC_TPGS_NONE 0x0 -#define SBC_TPGS_ASYMMETRIC 0x1 -#define SBC_TPGS_SYMMETRIC 0x2 -#define SBC_TPGS_BOTH 0x3 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \brief Version descriptor value for the SBC-3 specification -/// \see spc4r06.pdf - Section 6.4.2 - Table 87 -#define SBC_VERSION_DESCRIPTOR_SBC_3 0x04C0 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Sense Response Codes" -/// This page lists sense data response codes returned in REQUEST SENSE data -/// \see spc4r06.pdf - Section 4.5.1 - Table 12 -/// -/// !Codes -/// - SBC_SENSE_DATA_FIXED_CURRENT -/// - SBC_SENSE_DATA_FIXED_DEFERRED -/// - SBC_SENSE_DATA_DESCRIPTOR_CURRENT -/// - SBC_SENSE_DATA_DESCRIPTOR_DEFERRED - -#define SBC_SENSE_DATA_FIXED_CURRENT 0x70 -#define SBC_SENSE_DATA_FIXED_DEFERRED 0x71 -#define SBC_SENSE_DATA_DESCRIPTOR_CURRENT 0x72 -#define SBC_SENSE_DATA_DESCRIPTOR_DEFERRED 0x73 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Sense Keys" -/// This page lists sense key values returned in the REQUEST SENSE data -/// \see spc4r06.pdf - Section 4.5.6 - Table 27 -/// -/// !Keys -/// - SBC_SENSE_KEY_NO_SENSE -/// - SBC_SENSE_KEY_RECOVERED_ERROR -/// - SBC_SENSE_KEY_NOT_READY -/// - SBC_SENSE_KEY_MEDIUM_ERROR -/// - SBC_SENSE_KEY_HARDWARE_ERROR -/// - SBC_SENSE_KEY_ILLEGAL_REQUEST -/// - SBC_SENSE_KEY_UNIT_ATTENTION -/// - SBC_SENSE_KEY_DATA_PROTECT -/// - SBC_SENSE_KEY_BLANK_CHECK -/// - SBC_SENSE_KEY_VENDOR_SPECIFIC -/// - SBC_SENSE_KEY_COPY_ABORTED -/// - SBC_SENSE_KEY_ABORTED_COMMAND -/// - SBC_SENSE_KEY_VOLUME_OVERFLOW -/// - SBC_SENSE_KEY_MISCOMPARE - -/// No specific sense key. Successful command. -#define SBC_SENSE_KEY_NO_SENSE 0x00 -/// Command completed succesfully with some recovery action by the %device. -#define SBC_SENSE_KEY_RECOVERED_ERROR 0x01 -/// The device can not be accessed. -#define SBC_SENSE_KEY_NOT_READY 0x02 -/// Command terminated with a error condition that was probably caused by a -/// flaw in the medium or an error in the recorded data. -#define SBC_SENSE_KEY_MEDIUM_ERROR 0x03 -/// Hardware failure while performing the command or during a self test. -#define SBC_SENSE_KEY_HARDWARE_ERROR 0x04 -/// Illegal parameter found in the command or additional parameters. -#define SBC_SENSE_KEY_ILLEGAL_REQUEST 0x05 -/// Removable medium may have been changed or the %device has been reset. -#define SBC_SENSE_KEY_UNIT_ATTENTION 0x06 -/// Write on a block that is protected. -#define SBC_SENSE_KEY_DATA_PROTECT 0x07 -/// Indicates that a write-once device or a sequential-access device -/// encountered blank medium or format-defined end-of-data indication while -/// reading or a write-once device encountered a non-blank medium while writing. -#define SBC_SENSE_KEY_BLANK_CHECK 0x08 -/// Reporting vendor specific conditions. -#define SBC_SENSE_KEY_VENDOR_SPECIFIC 0x09 -/// EXTENDED COPY command was aborted. -#define SBC_SENSE_KEY_COPY_ABORTED 0x0A -/// Device aborted the command. -#define SBC_SENSE_KEY_ABORTED_COMMAND 0x0B -/// A buffered peripheral device is overflow. -#define SBC_SENSE_KEY_VOLUME_OVERFLOW 0x0D -/// The source data did not match the data read from the medium. -#define SBC_SENSE_KEY_MISCOMPARE 0x0E -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Sense Additionals" -/// This page lists additional sense code values returned in REQUEST SENSE data -/// \see spc4r06.pdf - Section 4.5.6 - Table 28 -/// -/// !Additional Codes -/// - SBC_ASC_LOGICAL_UNIT_NOT_READY -/// - SBC_ASC_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE -/// - SBC_ASC_INVALID_FIELD_IN_CDB -/// - SBC_ASC_WRITE_PROTECTED -/// - SBC_ASC_FORMAT_CORRUPTED -/// - SBC_ASC_INVALID_COMMAND_OPERATION_CODE -/// - SBC_ASC_TOO_MUCH_WRITE_DATA -/// - SBC_ASC_NOT_READY_TO_READY_CHANGE -/// - SBC_ASC_MEDIUM_NOT_PRESENT - -#define SBC_ASC_LOGICAL_UNIT_NOT_READY 0x04 -#define SBC_ASC_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE 0x21 -#define SBC_ASC_INVALID_FIELD_IN_CDB 0x24 -#define SBC_ASC_WRITE_PROTECTED 0x27 -#define SBC_ASC_FORMAT_CORRUPTED 0x31 -#define SBC_ASC_INVALID_COMMAND_OPERATION_CODE 0x20 -#define SBC_ASC_TOO_MUCH_WRITE_DATA 0x26 -#define SBC_ASC_NOT_READY_TO_READY_CHANGE 0x28 -#define SBC_ASC_MEDIUM_NOT_PRESENT 0x3A -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \brief MEDIUM TYPE field value for direct-access block devices -/// \see sbc3r06.pdf - Section 6.3.1 -#define SBC_MEDIUM_TYPE_DIRECT_ACCESS_BLOCK_DEVICE 0x00 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \brief MRIE field values -/// \see sbc3r06.pdf - Section 7.4.11 - Table 286 -#define SBC_MRIE_NO_REPORTING 0x00 -#define SBC_MRIE_ASYNCHRONOUS 0x01 -#define SBC_MRIE_GENERATE_UNIT_ATTENTION 0x02 -#define SBC_MRIE_COND_GENERATE_RECOVERED_ERROR 0x03 -#define SBC_MRIE_UNCOND_GENERATE_RECOVERED_ERROR 0x04 -#define SBC_MRIE_GENERATE_NO_SENSE 0x05 -#define SBC_MRIE_ON_REQUEST 0x06 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \brief Supported mode pages -/// \see sbc3r06.pdf - Section 6.3.1 - Table 115 -#define SBC_PAGE_READ_WRITE_ERROR_RECOVERY 0x01 -#define SBC_PAGE_INFORMATIONAL_EXCEPTIONS_CONTROL 0x1C -#define SBC_PAGE_RETURN_ALL 0x3F -#define SBC_PAGE_VENDOR_SPECIFIC 0x00 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Endian Macros" -/// This page lists the macros for endianness conversion. -/// -/// !Macros -/// - WORDB -/// - DWORDB -/// - STORE_DWORDB -/// - STORE_WORDB -/// \brief Converts a byte array to a word value using the big endian format -#define WORDB(bytes) ((unsigned short) ((bytes[0] << 8) | bytes[1])) - -/// \brief Converts a byte array to a dword value using the big endian format -#define DWORDB(bytes) ((unsigned int) ((bytes[0] << 24) | (bytes[1] << 16) \ - | (bytes[2] << 8) | bytes[3])) - -/// \brief Stores a dword value in a byte array, in big endian format -#define STORE_DWORDB(dword, bytes) \ - bytes[0] = (unsigned char) (((dword) >> 24) & 0xFF); \ - bytes[1] = (unsigned char) (((dword) >> 16) & 0xFF); \ - bytes[2] = (unsigned char) (((dword) >> 8) & 0xFF); \ - bytes[3] = (unsigned char) ((dword) & 0xFF); - -/// \brief Stores a word value in a byte array, in big endian format -#define STORE_WORDB(word, bytes) \ - bytes[0] = (unsigned char) (((word) >> 8) & 0xFF); \ - bytes[1] = (unsigned char) ((word) & 0xFF); -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Structures -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -/// \brief Structure for the INQUIRY command -/// \see spc4r06.pdf - Section 6.4.1 - Table 81 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x12 : SBC_INQUIRY - unsigned char isEVPD:1, //!< Type of requested data - bReserved1:7; //!< Reserved bits - unsigned char bPageCode; //!< Specifies the VPD to return - unsigned char pAllocationLength[2]; //!< Size of host buffer - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCInquiry; // GCC - -//------------------------------------------------------------------------------ -/// \brief Standard INQUIRY data format returned by the device -/// \see spc4r06.pdf - Section 6.4.2 - Table 82 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bPeripheralDeviceType:5, //!< Peripheral device type - bPeripheralQualifier :3; //!< Peripheral qualifier - unsigned char bReserved1:7, //!< Reserved bits - isRMB :1; //!< Is media removable ? - unsigned char bVersion; //!< SPC version used - unsigned char bResponseDataFormat:4, //!< Must be 0x2 - isHIGHSUP :1, //!< Hierarchical addressing used ? - isNORMACA :1, //!< ACA attribute supported ? - bObsolete1 :2; //!< Obsolete bits - unsigned char bAdditionalLength; //!< Length of remaining INQUIRY data - unsigned char isSCCS :1, //!< Embedded SCC ? - isACC :1, //!< Access control coordinator ? - bTPGS :2, //!< Target port support group - is3PC :1, //!< Third-party copy supported ? - bReserved2:2, //!< Reserved bits - isProtect :1; //!< Protection info supported ? - unsigned char bObsolete2:1, //!< Obsolete bit - isEncServ :1, //!< Embedded enclosure service comp? - isVS :1, //!< ??? - isMultiP :1, //!< Multi-port device ? - bObsolete3:3, //!< Obsolete bits - bUnused1 :1; //!< Unused feature - unsigned char bUnused2:6, //!< Unused features - isCmdQue:1, //!< Task management model supported ? - isVS2 :1; //!< ??? - unsigned char pVendorID[8]; //!< T10 vendor identification - unsigned char pProductID[16]; //!< Vendor-defined product ID - unsigned char pProductRevisionLevel[4];//!< Vendor-defined product revision - unsigned char pVendorSpecific[20]; //!< Vendor-specific data - unsigned char bUnused3; //!< Unused features - unsigned char bReserved3; //!< Reserved bits - unsigned short pVersionDescriptors[8]; //!< Standards the device complies to - unsigned char pReserved4[22]; //!< Reserved bytes - -} __attribute__ ((packed)) SBCInquiryData; // GCC - -//------------------------------------------------------------------------------ -/// \brief Data structure for the READ (10) command -/// \see sbc3r07.pdf - Section 5.7 - Table 34 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x28 : SBC_READ_10 - unsigned char bObsolete1:1, //!< Obsolete bit - isFUA_NV:1, //!< Cache control bit - bReserved1:1, //!< Reserved bit - isFUA:1, //!< Cache control bit - isDPO:1, //!< Cache control bit - bRdProtect:3; //!< Protection information to send - unsigned char pLogicalBlockAddress[4]; //!< Index of first block to read - unsigned char bGroupNumber:5, //!< Information grouping - bReserved2:3; //!< Reserved bits - unsigned char pTransferLength[2]; //!< Number of blocks to transmit - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCRead10; // GCC - -//------------------------------------------------------------------------------ -/// \brief Structure for the READ CAPACITY (10) command -/// \see sbc3r07.pdf - Section 5.11.1 - Table 40 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x25 : RBC_READ_CAPACITY - unsigned char bObsolete1:1, //!< Obsolete bit - bReserved1:7; //!< Reserved bits - unsigned char pLogicalBlockAddress[4]; //!< Block to evaluate if PMI is set - unsigned char pReserved2[2]; //!< Reserved bytes - unsigned char isPMI:1, //!< Partial medium indicator bit - bReserved3:7; //!< Reserved bits - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCReadCapacity10; - -//------------------------------------------------------------------------------ -/// \brief Data returned by the device after a READ CAPACITY (10) command -/// \see sbc3r07.pdf - Section 5.11.2 - Table 41 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char pLogicalBlockAddress[4]; //!< Address of last logical block - unsigned char pLogicalBlockLength[4]; //!< Length of each logical block - -} __attribute__ ((packed)) SBCReadCapacity10Data; - -//------------------------------------------------------------------------------ -/// \brief Structure for the REQUEST SENSE command -/// \see spc4r06.pdf - Section 6.26 - Table 170 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x03 : SBC_REQUEST_SENSE - unsigned char isDesc :1, //!< Type of information expected - bReserved1:7; //!< Reserved bits - unsigned char pReserved2[2]; //!< Reserved bytes - unsigned char bAllocationLength; //!< Size of host buffer - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCRequestSense; - -//------------------------------------------------------------------------------ -/// \brief Fixed format sense data returned after a REQUEST SENSE command has -/// been received with a DESC bit cleared. -/// \see spc4r06.pdf - Section 4.5.3 - Table 26 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bResponseCode:7, //!< Sense data format - isValid :1; //!< Information field is standard - unsigned char bObsolete1; //!< Obsolete byte - unsigned char bSenseKey :4, //!< Generic error information - bReserved1:1, //!< Reserved bit - isILI :1, //!< SSC - isEOM :1, //!< SSC - isFilemark:1; //!< SSC - unsigned char pInformation[4]; //!< Command-specific - unsigned char bAdditionalSenseLength; //!< sizeof(SBCRequestSense_data)-8 - unsigned char pCommandSpecificInformation[4]; //!< Command-specific - unsigned char bAdditionalSenseCode; //!< Additional error information - unsigned char bAdditionalSenseCodeQualifier; //!< Further error information - unsigned char bFieldReplaceableUnitCode; //!< Specific component code - unsigned char bSenseKeySpecific:7, //!< Additional exception info - isSKSV :1; //!< Is sense key specific valid? - unsigned char pSenseKeySpecific[2]; //!< Additional exception info - -} __attribute__ ((packed)) SBCRequestSenseData; - -//------------------------------------------------------------------------------ -/// \brief Data structure for the TEST UNIT READY command -/// \see spc4r06.pdf - Section 6.34 - Table 192 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x00 : SBC_TEST_UNIT_READY - unsigned char pReserved1[4]; //!< Reserved bits - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCTestUnitReady; // GCC - -//------------------------------------------------------------------------------ -/// \brief Structure for the WRITE (10) command -/// \see sbc3r07.pdf - Section 5.26 - Table 70 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x2A : SBC_WRITE_10 - unsigned char bObsolete1:1, //!< Obsolete bit - isFUA_NV:1, //!< Cache control bit - bReserved1:1, //!< Reserved bit - isFUA:1, //!< Cache control bit - isDPO:1, //!< Cache control bit - bWrProtect:3; //!< Protection information to send - unsigned char pLogicalBlockAddress[4]; //!< First block to write - unsigned char bGroupNumber:5, //!< Information grouping - bReserved2:3; //!< Reserved bits - unsigned char pTransferLength[2]; //!< Number of blocks to write - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCWrite10; - -//------------------------------------------------------------------------------ -/// \brief Structure for the PREVENT/ALLOW MEDIUM REMOVAL command -/// \see sbc3r07.pdf - Section 5.5 - Table 30 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x1E : SBC_PREVENT_ALLOW_MEDIUM_REMOVAL - unsigned char pReserved1[3]; //!< Reserved bytes - unsigned char bPrevent:2, //!< Accept/prohibit removal - bReserved2:6; //!< Reserved bits - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCMediumRemoval; // GCC - -//------------------------------------------------------------------------------ -/// \brief Structure for the MODE SENSE (6) command -/// \see spc4r06 - Section 6.9.1 - Table 98 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x1A : SBC_MODE_SENSE_6 - unsigned char bReserved1:3, //!< Reserved bits - isDBD:1, //!< Disable block descriptors bit - bReserved2:4; //!< Reserved bits - unsigned char bPageCode:6, //!< Mode page to return - bPC:2; //!< Type of parameter values to return - unsigned char bSubpageCode; //!< Mode subpage to return - unsigned char bAllocationLength; //!< Host buffer allocated size - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCModeSense6; // GCC - -//------------------------------------------------------------------------------ -/// \brief Header for the data returned after a MODE SENSE (6) command -/// \see spc4r06.pdf - Section 7.4.3 - Table 268 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bModeDataLength; //!< Length of mode data to follow - unsigned char bMediumType; //!< Type of medium (SBC_MEDIUM_TYPE_DIRECT_ACCESS_BLOCK_DEVICE) - unsigned char bReserved1:4, //!< Reserved bits - isDPOFUA:1, //!< DPO/FUA bits supported ? - bReserved2:2, //!< Reserved bits - isWP:1; //!< Is medium write-protected ? - unsigned char bBlockDescriptorLength; //!< Length of all block descriptors - -} __attribute__ ((packed)) SBCModeParameterHeader6; // GCC - -//------------------------------------------------------------------------------ -/// \brief Informational exceptions control mode page -/// \see spc4r06.pdf - Section 7.4.11 - Table 285 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bPageCode:6, //!< 0x1C : SBC_PAGE_INFORMATIONAL_EXCEPTIONS_CONTROL - isSPF:1, //!< Page or subpage data format - isPS:1; //!< Parameters saveable ? - unsigned char bPageLength; //!< Length of page data (0x0A) - unsigned char isLogErr:1, //!< Should informational exceptions be logged ? - isEBackErr:1, //!< Enable background error bit - isTest:1, //!< Create a device test failure ? - isDExcpt:1, //!< Disable exception control bit - isEWasc:1, //!< Report warnings ? - isEBF:1, //!< Enable background function bit - bReserved1:1, //!< Reserved bit - isPerf:1; //!< Delay acceptable when treating exceptions ? - unsigned char bMRIE:4, //!< Method of reporting informational exceptions - bReserved2:4; //!< Reserved bits - unsigned char pIntervalTimer[4]; //!< Error reporting period - unsigned char pReportCount[4]; //!< Maximum number of time a report can be issued - -} __attribute__ ((packed)) SBCInformationalExceptionsControl; // GCC - -//------------------------------------------------------------------------------ -/// \brief Read/write error recovery mode page -/// \see sbc3r07.pdf - Section 6.3.5 - Table 122 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bPageCode:6, //!< 0x01 : SBC_PAGE_READ_WRITE_ERROR_RECOVERY - isSPF:1, //!< Page or subpage data format - isPS:1; //!< Parameters saveable ? - unsigned char bPageLength; //!< Length of page data (0x0A) - unsigned char isDCR:1, //!< Disable correction bit - isDTE:1, //!< Data terminate on error bit - isPER:1, //!< Post error bit - isEER:1, //!< Enable early recovery bit - isRC:1, //!< Read continuous bit - isTB:1, //!< Transfer block bit - isARRE:1, //!< Automatic read reallocation enabled bit - isAWRE:1; //!< Automatic write reallocation enabled bit - unsigned char bReadRetryCount; //!< Number of retries when reading - unsigned char pObsolete1[3]; //!< Obsolete bytes - unsigned char bReserved1; //!< Reserved byte - unsigned char bWriteRetryCount; //!< Number of retries when writing - unsigned char bReserved2; //!< Reserved byte - unsigned char pRecoveryTimeLimit[2]; //!< Maximum time duration for error recovery - -} __attribute__ ((packed)) SBCReadWriteErrorRecovery; // GCC - -//------------------------------------------------------------------------------ -/// \brief Generic structure for holding information about SBC commands -/// \see SBCInquiry -/// \see SBCRead10 -/// \see SBCReadCapacity10 -/// \see SBCRequestSense -/// \see SBCTestUnitReady -/// \see SBCWrite10 -/// \see SBCMediumRemoval -/// \see SBCModeSense6 -//------------------------------------------------------------------------------ -typedef union { - - unsigned char bOperationCode; //!< Operation code of the command - SBCInquiry inquiry; //!< INQUIRY command - SBCRead10 read10; //!< READ (10) command - SBCReadCapacity10 readCapacity10; //!< READ CAPACITY (10) command - SBCRequestSense requestSense; //!< REQUEST SENSE command - SBCTestUnitReady testUnitReady; //!< TEST UNIT READY command - SBCWrite10 write10; //!< WRITE (10) command - SBCMediumRemoval mediumRemoval; //!< PREVENT/ALLOW MEDIUM REMOVAL command - SBCModeSense6 modeSense6; //!< MODE SENSE (6) command - -} SBCCommand; - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -#endif //#ifndef SBC_H - From e45410c257beb956b09ec45ca0b87eebff48d0d6 Mon Sep 17 00:00:00 2001 From: Kjell Kernen Date: Tue, 4 Mar 2014 18:05:51 +0100 Subject: [PATCH 026/285] Check for updates dialog now always on top. The check for downloads dialogs were started asynchonously. This was the reason for the dialog ending up under other windows and behaving strangely since other windows will steal focus as soon as the dialog lets go of it. --- companion/src/mainwindow.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/companion/src/mainwindow.cpp b/companion/src/mainwindow.cpp index 0f8d36389..d419ed99f 100644 --- a/companion/src/mainwindow.cpp +++ b/companion/src/mainwindow.cpp @@ -222,7 +222,7 @@ void MainWindow::checkForUpdates(bool ignoreSettings, QString & fwId) if(ignoreSettings) { downloadDialog_forWait = new downloadDialog(this, tr("Checking for updates")); - downloadDialog_forWait->show(); + downloadDialog_forWait->exec(); } else { downloadDialog_forWait = NULL; // TODO needed? } @@ -272,7 +272,7 @@ void MainWindow::checkForUpdateFinished(QNetworkReply * reply) downloadDialog * dd = new downloadDialog(this, QString(OPENTX_COMPANION_DOWNLOADS C9X_INSTALLER).arg(version), fileName); installer_fileName = fileName; connect(dd, SIGNAL(accepted()), this, SLOT(updateDownloaded())); - dd->show(); + dd->exec(); } } #else From 3788f5f56299a4fc2e4e703647df268b3141490b Mon Sep 17 00:00:00 2001 From: bsongis Date: Tue, 4 Mar 2014 18:31:12 +0100 Subject: [PATCH 027/285] 5 more files removed --- radio/bootloader/Makefile | 6 +- radio/bootloader/boot.cpp | 64 +-- radio/bootloader/include/Media.h | 288 ------------- radio/bootloader/include/eeprom_rlc.h | 48 --- radio/bootloader/include/myeeprom.h | 527 ----------------------- radio/bootloader/include/timers.h | 45 -- radio/bootloader/lcd_driver.cpp | 314 -------------- radio/bootloader/usbd_storage_msd.cpp | 2 +- radio/src/eeprom_rlc.h | 13 +- radio/src/lcd.cpp | 14 +- radio/src/lcd.h | 14 +- radio/src/opentx.h | 4 +- radio/src/targets/taranis/lcd_driver.cpp | 6 +- 13 files changed, 77 insertions(+), 1268 deletions(-) delete mode 100644 radio/bootloader/include/Media.h delete mode 100644 radio/bootloader/include/eeprom_rlc.h delete mode 100644 radio/bootloader/include/myeeprom.h delete mode 100644 radio/bootloader/include/timers.h delete mode 100644 radio/bootloader/lcd_driver.cpp diff --git a/radio/bootloader/Makefile b/radio/bootloader/Makefile index 886d06bb2..9f406db8b 100644 --- a/radio/bootloader/Makefile +++ b/radio/bootloader/Makefile @@ -105,6 +105,7 @@ else EXTRAINCDIRS += ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Core/inc EXTRAINCDIRS += ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/inc EXTRAINCDIRS += ../src/targets/taranis + EXTRAINCDIRS += ../src/fonts/std endif endif @@ -137,14 +138,15 @@ SRC = system_stm32f2xx.c \ ../src/targets/taranis/aspi.c \ ../src/targets/taranis/usb_bsp.c -CPPSRC = lcd_driver.cpp \ +CPPSRC = ../src/targets/taranis/lcd_driver.cpp \ driversboot.cpp \ logicioboot.cpp \ ff.cpp \ ../src/targets/taranis/diskio.cpp \ ../src/targets/taranis/usbd_usr.cpp \ usbd_storage_msd.cpp \ - lcdboot.cpp \ + ../src/lcd.cpp \ + ../src/translations.cpp \ power.cpp \ boot.cpp diff --git a/radio/bootloader/boot.cpp b/radio/bootloader/boot.cpp index 1c3dd2673..b8a186455 100644 --- a/radio/bootloader/boot.cpp +++ b/radio/bootloader/boot.cpp @@ -63,7 +63,7 @@ #include "stm32f2xx_flash.h" #include "../src/targets/taranis/i2c.h" #include "hal.h" -#include "timers.h" +// #include "timers.h" extern "C" { #include "usb_dcd_int.h" @@ -75,8 +75,11 @@ extern "C" { #endif +#include "board_taranis.h" +#include "../src/lcd.h" + #include "radio.h" -#include "lcd.h" +// #include "lcd.h" #include "ff.h" #include "diskio.h" #include "drivers.h" @@ -405,7 +408,7 @@ void init10msTimer() // Timer14 RCC->APB1ENR |= RCC_APB1ENR_TIM14EN ; // Enable clock TIM14->ARR = 9999 ; // 10mS - TIM14->PSC = (Peri1_frequency*Timer_mult1) / 1000000 - 1 ; // 1uS from 12MHz + TIM14->PSC = (PERI1_FREQUENCY * TIMER_MULT_APB1) / 1000000 - 1 ; // 1uS from 12MHz TIM14->CCER = 0 ; TIM14->CCMR1 = 0 ; TIM14->EGR = 0 ; @@ -425,7 +428,7 @@ void init_hw_timer() // Timer13 RCC->APB1ENR |= RCC_APB1ENR_TIM13EN ; // Enable clock TIM13->ARR = 65535 ; - TIM13->PSC = (Peri1_frequency*Timer_mult1) / 10000000 - 1 ; // 0.1uS from 12MHz + TIM13->PSC = (PERI1_FREQUENCY * TIMER_MULT_APB1) / 10000000 - 1 ; // 0.1uS from 12MHz TIM13->CCER = 0 ; TIM13->CCMR1 = 0 ; TIM13->EGR = 0 ; @@ -669,7 +672,7 @@ uint8_t flashFile( uint32_t index ) FRESULT fr ; lcd_clear() ; - lcd_puts_Pleft( 0, "\005Flash File" ) ; + lcd_putsLeft( 0, "\005Flash File" ) ; if ( Valid == 0 ) { // Validate file here @@ -685,11 +688,11 @@ uint8_t flashFile( uint32_t index ) } if ( Valid == 2 ) { - lcd_puts_Pleft( 3*FH,"NOT A VALID FIRMWARE") ; + lcd_putsLeft( 3*FH,"NOT A VALID FIRMWARE") ; #ifdef PCBTARANIS - lcd_puts_Pleft( 6*FH,"\015[EXIT]") ; + lcd_putsLeft( 6*FH,"\015[EXIT]") ; #else - lcd_puts_Pleft( 6*FH,"\007[EXIT]") ; + lcd_putsLeft( 6*FH,"\007[EXIT]") ; #endif uint8_t event = getEvent() ; if ( event == EVT_KEY_FIRST(BOOT_KEY_EXIT) ) @@ -698,14 +701,14 @@ uint8_t flashFile( uint32_t index ) } return 4 ; // } - lcd_putsn_P( 0, 2*FH, Filenames[index], DISPLAY_CHAR_WIDTH ) ; + lcd_putsnAtt( 0, 2*FH, Filenames[index], DISPLAY_CHAR_WIDTH, 0 ) ; #ifdef PCBTARANIS - lcd_puts_Pleft( 6*FH,"\010[ENTER]\021[EXIT]") ; - lcd_puts_Pleft( 5*FH,"\010YES\021NO") ; + lcd_putsLeft( 6*FH,"\010[ENTER]\021[EXIT]") ; + lcd_putsLeft( 5*FH,"\010YES\021NO") ; #else - lcd_puts_Pleft( 6*FH,"\003[MENU]\013[EXIT]") ; - lcd_puts_Pleft( 5*FH,"\003YES\013NO") ; + lcd_putsLeft( 6*FH,"\003[MENU]\013[EXIT]") ; + lcd_putsLeft( 5*FH,"\003YES\013NO") ; #endif uint8_t event = getEvent() ; @@ -770,19 +773,19 @@ int main() start_timer0() ; #endif - lcd_init() ; + lcdInit() ; #ifdef PCBSKY extern uint8_t OptrexDisplay ; OptrexDisplay = 1 ; #endif lcd_clear() ; #ifdef PCBTARANIS - lcd_puts_Pleft( 0, "\006Boot Loader" ) ; + lcd_putsLeft( 0, "\006Boot Loader" ) ; #endif - refreshDisplay() ; + lcdRefresh() ; #ifdef PCBSKY OptrexDisplay = 0 ; - refreshDisplay() ; + lcdRefresh() ; #endif #ifdef PCBTARANIS @@ -853,19 +856,19 @@ extern uint8_t OptrexDisplay ; Tenms = 0 ; lcd_clear() ; #ifdef PCBSKY - lcd_puts_Pleft( 0, "Boot Loader" ) ; + lcd_putsLeft( 0, "Boot Loader" ) ; #endif #ifdef PCBTARANIS - lcd_puts_Pleft( 0, "\006Boot Loader" ) ; + lcd_putsLeft( 0, "\006Boot Loader" ) ; #endif if ( sdMounted() ) { #ifdef PCBSKY - lcd_puts_Pleft( 0, "\014Ready" ) ; + lcd_putsLeft( 0, "\014Ready" ) ; #endif #ifdef PCBTARANIS - lcd_puts_Pleft( 0, "\022Ready" ) ; + lcd_putsLeft( 0, "\022Ready" ) ; #endif if ( usbPlugged() ) @@ -876,10 +879,10 @@ extern uint8_t OptrexDisplay ; if ( state == ST_USB ) { #ifdef PCBSKY - lcd_puts_Pleft( 3*FH, "\010BUSY" ) ; + lcd_putsLeft( 3*FH, "\010BUSY" ) ; #endif #ifdef PCBTARANIS - lcd_puts_Pleft( 3*FH, "\016BUSY" ) ; + lcd_putsLeft( 3*FH, "\016BUSY" ) ; #endif if ( usbPlugged() == 0 ) { @@ -921,10 +924,10 @@ extern uint8_t OptrexDisplay ; if ( state == ST_DIR_CHECK ) { #ifdef PCBSKY - lcd_puts_Pleft( 16, "\005No Firmware" ) ; + lcd_putsLeft( 16, "\005No Firmware" ) ; #endif #ifdef PCBTARANIS - lcd_puts_Pleft( 16, "\013No Firmware" ) ; + lcd_putsLeft( 16, "\013No Firmware" ) ; #endif } if ( state == ST_OPEN_DIR ) @@ -970,7 +973,7 @@ extern uint8_t OptrexDisplay ; { x = 0 ; } - lcd_putsn_P( 0, 16+FH*i, &Filenames[i][x], DISPLAY_CHAR_WIDTH ) ; + lcd_putsnAtt( 0, 16+FH*i, &Filenames[i][x], DISPLAY_CHAR_WIDTH, 0 ) ; } { uint8_t event = getEvent() ; @@ -1030,7 +1033,8 @@ extern uint8_t OptrexDisplay ; state = ST_REBOOT ; } } - lcd_char_inverse( 0, 2*FH+FH*vpos, DISPLAY_CHAR_WIDTH*FW, 0 ) ; + lcd_invert_line(2*FH+FH*vpos); + // lcd_char_inverse( 0, 2*FH+FH*vpos, DISPLAY_CHAR_WIDTH*FW, 0 ) ; } if ( state == ST_FLASH_CHECK ) { @@ -1061,7 +1065,7 @@ extern uint8_t OptrexDisplay ; { // Commit to flashing uint32_t blockOffset = 0 ; - lcd_puts_Pleft( 3*FH, "Flashing" ) ; + lcd_putsLeft( 3*FH, "Flashing" ) ; while ( BlockCount ) { program( (uint32_t *)firmwareAddress, &Block_buffer[blockOffset] ) ; // size is 256 bytes @@ -1098,7 +1102,7 @@ extern uint8_t OptrexDisplay ; if ( state == ST_FLASH_DONE ) { uint8_t event = getEvent() ; - lcd_puts_Pleft( 3*FH, "Flashing Complete" ) ; + lcd_putsLeft( 3*FH, "Flashing Complete" ) ; if ( event == EVT_KEY_FIRST(BOOT_KEY_EXIT) ) { state = ST_FILE_LIST ; @@ -1111,7 +1115,7 @@ extern uint8_t OptrexDisplay ; { TenCount = 2 ; #endif - refreshDisplay() ; + lcdRefresh() ; #ifdef PCBTARANIS } #endif diff --git a/radio/bootloader/include/Media.h b/radio/bootloader/include/Media.h deleted file mode 100644 index ef0a22586..000000000 --- a/radio/bootloader/include/Media.h +++ /dev/null @@ -1,288 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Generic Media type, which provides transparent access to all types of -/// memories. -/// -/// \note The physical or HW related media operations (physical device -/// connection & protection detecting, PIO configurations and interface -/// driver initialization) are excluded. -/// -/// !Usage -/// -# Do PIO initialization for peripheral interfaces. -/// -# Initialize peripheral interface driver & device driver. -/// -# Initialize specific media interface and link to this initialized driver. -/// -//------------------------------------------------------------------------------ - -#ifndef MEDIA_H -#define MEDIA_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//! \brief Operation result code returned by media methods -#define MED_STATUS_SUCCESS 0x00 -#define MED_STATUS_ERROR 0x01 -#define MED_STATUS_BUSY 0x02 -#define MED_STATUS_PROTECTED 0x04 - -//! \brief Media statuses -#define MED_STATE_READY 0x00 /// Media is ready for access -#define MED_STATE_BUSY 0x01 /// Media is busy - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ -typedef struct _Media Media; - -typedef void (*MediaCallback)(void *argument, - unsigned char status, - unsigned int transferred, - unsigned int remaining); - -typedef unsigned char (*Media_write)(Media *media, - unsigned int address, - void *data, - unsigned int length, - MediaCallback callback, - void *argument); - -typedef unsigned char (*Media_read)(Media *media, - unsigned int address, - void *data, - unsigned int length, - MediaCallback callback, - void *argument); - -typedef unsigned char (*Media_cancelIo)(Media *media); - -typedef unsigned char (*Media_lock)(Media *media, - unsigned int start, - unsigned int end, - unsigned int *pActualStart, - unsigned int *pActualEnd); - -typedef unsigned char (*Media_unlock)(Media *media, - unsigned int start, - unsigned int end, - unsigned int *pActualStart, - unsigned int *pActualEnd); - -typedef unsigned char (*Media_ioctl)(Media *media, - unsigned char ctrl, - void *buff); - -typedef unsigned char (*Media_flush)(Media *media); - -typedef void (*Media_handler)(Media *media); - -//! \brief Media transfer -//! \see TransferCallback -typedef struct { - - void *data; //!< Pointer to the data buffer - unsigned int address; //!< Address where to read/write the data - unsigned int length; //!< Size of the data to read/write - MediaCallback callback; //!< Callback to invoke when the transfer done - void *argument; //!< Callback argument - -} MEDTransfer; - -//! \brief Media object -//! \see MEDTransfer -struct _Media { - - Media_write write; //!< Write method - Media_read read; //!< Read method - Media_cancelIo cancelIo; //!< Cancel pending IO method - Media_lock lock; //!< lock method if possible - Media_unlock unlock; //!< unlock method if possible - Media_flush flush; //!< Flush method - Media_handler handler; //!< Interrupt handler - unsigned int blockSize; //!< Block size in bytes (1, 512, 1K, 2K ...) - unsigned int baseAddress; //!< Base address of media in number of blocks - unsigned int size; //!< Size of media in number of blocks - MEDTransfer transfer; //!< Current transfer operation - void *interface; //!< Pointer to the physical interface used - unsigned char bReserved:4, - mappedRD:1, //!< Mapped to memory space to read - mappedWR:1, //!< Mapped to memory space to write -#ifdef __cplusplus - protectd:1, //!< Protected media? -#else - protected:1, //!< Protected media? -#endif - removable:1; //!< Removable/Fixed media? - unsigned char state; //!< Status of media - unsigned short reserved; -}; - -/// Available medias. -extern Media medias[]; - -/// Number of medias which are effectively used. -/// Defined by Media, shared usage by USB MSD & FS ... -extern unsigned int numMedias; - -//------------------------------------------------------------------------------ -// Inline Functions -//------------------------------------------------------------------------------ -//------------------------------------------------------------------------------ -//! \brief Writes data on a media -//! \param media Pointer to a Media instance -//! \param address Address at which to write -//! \param data Pointer to the data to write -//! \param length Size of the data buffer -//! \param callback Optional pointer to a callback function to invoke when -//! the write operation terminates -//! \param argument Optional argument for the callback function -//! \return Operation result code -//! \see TransferCallback -//------------------------------------------------------------------------------ -static inline unsigned char MED_Write(Media *media, - unsigned int address, - void *data, - unsigned int length, - MediaCallback callback, - void *argument) -{ - return media->write(media, address, data, length, callback, argument); -} - -//------------------------------------------------------------------------------ -//! \brief Reads a specified amount of data from a media -//! \param media Pointer to a Media instance -//! \param address Address of the data to read -//! \param data Pointer to the buffer in which to store the retrieved -//! data -//! \param length Length of the buffer -//! \param callback Optional pointer to a callback function to invoke when -//! the operation is finished -//! \param argument Optional pointer to an argument for the callback -//! \return Operation result code -//! \see TransferCallback -//------------------------------------------------------------------------------ -static inline unsigned char MED_Read(Media *media, - unsigned int address, - void *data, - unsigned int length, - MediaCallback callback, - void *argument) -{ - return media->read(media, address, data, length, callback, argument); -} - -//------------------------------------------------------------------------------ -//! \brief Locks all the regions in the given address range. -//! \param media Pointer to a Media instance -/// \param start Start address of lock range. -/// \param end End address of lock range. -/// \param pActualStart Start address of the actual lock range (optional). -/// \param pActualEnd End address of the actual lock range (optional). -/// \return 0 if successful; otherwise returns an error code. -//------------------------------------------------------------------------------ -static inline unsigned char MED_Lock(Media *media, - unsigned int start, - unsigned int end, - unsigned int *pActualStart, - unsigned int *pActualEnd) -{ - if( media->lock ) { - return media->lock(media, start, end, pActualStart, pActualEnd); - } - else { - return MED_STATUS_SUCCESS; - } -} - -//------------------------------------------------------------------------------ -//! \brief Unlocks all the regions in the given address range -//! \param media Pointer to a Media instance -/// \param start Start address of unlock range. -/// \param end End address of unlock range. -/// \param pActualStart Start address of the actual unlock range (optional). -/// \param pActualEnd End address of the actual unlock range (optional). -/// \return 0 if successful; otherwise returns an error code. -//------------------------------------------------------------------------------ -static inline unsigned char MED_Unlock(Media *media, - unsigned int start, - unsigned int end, - unsigned int *pActualStart, - unsigned int *pActualEnd) -{ - if( media->unlock ) { - return media->unlock(media, start, end, pActualStart, pActualEnd); - } - else { - return MED_STATUS_SUCCESS; - } -} - -//------------------------------------------------------------------------------ -//! \brief -//! \param media Pointer to the Media instance to use -//------------------------------------------------------------------------------ -static inline unsigned char MED_Flush(Media *media) -{ - if (media->flush) { - - return media->flush(media); - } - else { - - return MED_STATUS_SUCCESS; - } -} - -//------------------------------------------------------------------------------ -//! \brief Invokes the interrupt handler of the specified media -//! \param media Pointer to the Media instance to use -//------------------------------------------------------------------------------ -static inline void MED_Handler(Media *media) -{ - if (media->handler) { - - media->handler(media); - } -} - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern void MED_HandleAll(Media *medias, unsigned char numMedias); - -#endif // _MEDIA_H - diff --git a/radio/bootloader/include/eeprom_rlc.h b/radio/bootloader/include/eeprom_rlc.h deleted file mode 100644 index d758b7fc5..000000000 --- a/radio/bootloader/include/eeprom_rlc.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Authors (alphabetical order) - * - Andre Bernet - * - Andreas Weitl - * - Bertrand Songis - * - Bryan J. Rentoul (Gruvin) - * - Cameron Weeks - * - Erez Raviv - * - Gabriel Birkus - * - Jean-Pierre Parisy - * - Karl Szmutny - * - Michael Blandford - * - Michal Hlavinka - * - Pat Mackenzie - * - Philip Moss - * - Rob Thomson - * - Romolo Manfredini - * - Thomas Husterer - * - * opentx is based on code named - * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, - * er9x by Erez Raviv: http://code.google.com/p/er9x/, - * and the original (and ongoing) project by - * Thomas Husterer, th9x: http://code.google.com/p/th9x/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef eeprom_rlc_h -#define eeprom_rlc_h - -#include - -#if !defined(EESIZE) - #define EESIZE (32*1024) -#endif - -//uint32_t ee32_check_finished( void ) ; - -#endif diff --git a/radio/bootloader/include/myeeprom.h b/radio/bootloader/include/myeeprom.h deleted file mode 100644 index 269c29d99..000000000 --- a/radio/bootloader/include/myeeprom.h +++ /dev/null @@ -1,527 +0,0 @@ -/* - * Author - Erez Raviv - * - * Based on th9x -> http://code.google.com/p/th9x/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#ifndef eeprom_h -#define eeprom_h - -#include - - -//eeprom data -//#define EE_VERSION 2 -#define MAX_MODELS 32 -#define MAX_MIXERS 32 -#define MAX_SKYMIXERS 48 -#define MAX_CURVE5 8 -#define MAX_CURVE9 8 -#define MDVERS_r9 1 -#define MDVERS_r14 2 -#define MDVERS_r22 3 -#define MDVERS_r77 4 -#define MDVERS_r85 5 -#define MDVERS_r261 6 -#define MDVERS_r352 7 -#define MDVERS_r365 8 -#define MDVERS_r668 9 -#define MDVERS_e119 10 -#define MDVERS 11 - -#define MDSKYVERS 2 - -#define NUM_VOICE 8 - -//OBSOLETE - USE ONLY MDVERS NOW -//#define GENERAL_MYVER_r261 3 -//#define GENERAL_MYVER_r365 4 -//#define GENERAL_MYVER 5 - - -// eeprom ver <9 => mdvers == 1 -// eeprom ver >9 => mdvers ==2 - -#define WARN_THR_BIT 0x01 -#define WARN_BEP_BIT 0x80 -#define WARN_SW_BIT 0x02 -#define WARN_MEM_BIT 0x04 -#define WARN_BVAL_BIT 0x38 - -#define WARN_THR (!(g_eeGeneral.warnOpts & WARN_THR_BIT)) -#define WARN_BEP (!(g_eeGeneral.warnOpts & WARN_BEP_BIT)) -#define WARN_SW (!(g_eeGeneral.warnOpts & WARN_SW_BIT)) -#define WARN_MEM (!(g_eeGeneral.warnOpts & WARN_MEM_BIT)) -#define BEEP_VAL ( (g_eeGeneral.warnOpts & WARN_BVAL_BIT) >>3 ) - -// Bits in stickGain -#define STICK_LV_GAIN 0x40 -#define STICK_LH_GAIN 0x10 -#define STICK_RV_GAIN 0x04 -#define STICK_RH_GAIN 0x01 - -#define GENERAL_OWNER_NAME_LEN 10 -#define MODEL_NAME_LEN 10 - -#define MAX_GVARS 7 - -#define MAX_PHASES 6 - -#ifndef PACK -#define PACK( __Declaration__ ) __Declaration__ __attribute__((__packed__)) -#endif - -PACK(typedef struct t_TrainerMix { - uint8_t srcChn:3; //0-7 = ch1-8 - int8_t swtch:5; - int8_t studWeight:6; - uint8_t mode:2; //off,add-mode,subst-mode -}) TrainerMix; // - -PACK(typedef struct t_TrainerData { - int16_t calib[4]; - TrainerMix mix[4]; -}) TrainerData; - -PACK(typedef struct t_EEGeneral { - uint8_t myVers; - int16_t calibMid[7]; - int16_t calibSpanNeg[7]; - int16_t calibSpanPos[7]; - uint16_t chkSum; - uint8_t currModel; //0..15 - uint8_t contrast; - uint8_t vBatWarn; - int8_t vBatCalib; - int8_t lightSw; - TrainerData trainer; - uint8_t view; - uint8_t disableThrottleWarning:1; - uint8_t disableSwitchWarning:1; - uint8_t disableMemoryWarning:1; - uint8_t beeperVal:3; - uint8_t reserveWarning:1; - uint8_t disableAlarmWarning:1; - uint8_t stickMode; - int8_t inactivityTimer; - uint8_t throttleReversed:1; - uint8_t minuteBeep:1; - uint8_t preBeep:1; - uint8_t flashBeep:1; - uint8_t disableSplashScreen:1; - uint8_t disablePotScroll:1; - uint8_t stickScroll:1 ; - uint8_t frskyinternalalarm:1; - uint8_t filterInput; - uint8_t lightAutoOff; - uint8_t templateSetup; //RETA order according to chout_ar array - int8_t PPM_Multiplier; - uint8_t FRSkyYellow:4; - uint8_t FRSkyOrange:4; - uint8_t FRSkyRed:4; //mike please check these are correct - uint8_t hideNameOnSplash:1; - uint8_t optrexDisplay:1; - uint8_t unexpectedShutdown:1; - uint8_t spare:1; - uint8_t speakerPitch; - uint8_t hapticStrength; - uint8_t speakerMode; - uint8_t lightOnStickMove; - char ownerName[GENERAL_OWNER_NAME_LEN]; - uint8_t switchWarningStates; - uint8_t volume ; - uint8_t bright ; // backlight - uint8_t stickGain; - uint8_t mAh_alarm ; - uint16_t mAh_used ; - uint16_t run_time ; - int8_t current_calib ; - uint8_t bt_baudrate ; - uint8_t rotaryDivisor ; - uint8_t crosstrim:1; - uint8_t spare9:7; - int8_t rtcCal ; - int16_t x9dcalibMid ; // X9D - int16_t x9dcalibSpanNeg ; // X9D - int16_t x9dcalibSpanPos ; // X9D - uint8_t stickReverse ; - uint8_t language ; -}) EEGeneral; - - - - - -//eeprom modelspec -//expo[3][2][2] //[Norm/Dr][expo/weight][R/L] - -PACK(typedef struct t_ExpoData { - int8_t expo[3][2][2]; - int8_t drSw1; - int8_t drSw2; -}) ExpoData; - - -PACK(typedef struct t_LimitData { - int8_t min; - int8_t max; - bool revert; - int16_t offset; -}) LimitData; - -#define MLTPX_ADD 0 -#define MLTPX_MUL 1 -#define MLTPX_REP 2 - -PACK(typedef struct t_MixData { - uint8_t destCh; // 1..NUM_CHNOUT - uint8_t srcRaw; // - int8_t weight; - int8_t swtch; - uint8_t curve; //0=symmetrisch 1=no neg 2=no pos - uint8_t delayUp:4; - uint8_t delayDown:4; - uint8_t speedUp:4; // Servogeschwindigkeit aus Tabelle (10ms Cycle) - uint8_t speedDown:4; // 0 nichts - uint8_t carryTrim:1; - uint8_t mltpx:3; // multiplex method 0=+ 1=* 2=replace - uint8_t mixWarn:2; // mixer warning - uint8_t enableFmTrim:1; - uint8_t mixres:1; - int8_t sOffset; - int8_t res; -}) MixData; - - -PACK(typedef struct t_CSwData { // Custom Switches data - int8_t v1; //input - int8_t v2; //offset - uint8_t func:4; - uint8_t andsw:4; -}) CSwData; - -PACK(typedef struct t_SafetySwData { // Custom Switches data - union opt - { - struct ss - { - int8_t swtch:6; - uint8_t mode:2; - int8_t val; - } ss ; - struct vs - { - uint8_t vswtch:5 ; - uint8_t vmode:3 ; // ON, OFF, BOTH, 15Secs, 30Secs, 60Secs, Varibl - uint8_t vval; - } vs ; - } opt ; -}) SafetySwData; - -PACK(typedef struct t_FrSkyChannelData { - uint8_t ratio; // 0.0 means not used, 0.1V steps EG. 6.6 Volts = 66. 25.1V = 251, etc. - uint8_t alarms_value[2]; // 0.1V steps EG. 6.6 Volts = 66. 25.1V = 251, etc. - uint8_t alarms_level:4; - uint8_t alarms_greater:2; // 0=LT(<), 1=GT(>) - uint8_t type:2; // 0=volts, 1=raw, 2=volts*2, 3=Amps -}) FrSkyChannelData; - -PACK(typedef struct t_FrSkyData { - FrSkyChannelData channels[2]; -}) FrSkyData; - -PACK(typedef struct t_FrSkyalarms -{ - uint8_t frskyAlarmType ; - uint8_t frskyAlarmLimit ; - uint8_t frskyAlarmSound ; -}) FrSkyAlData; - -PACK(typedef struct t_FrSkyAlarmData { - FrSkyAlData alarmData[8] ; -}) FrSkyAlarmData; - -PACK(typedef struct t_TimerMode -{ - uint8_t tmrModeA:7 ; // timer trigger source -> off, abs, stk, stk%, cx% - uint8_t tmrDir:1 ; // Timer direction - int8_t tmrModeB ; // timer trigger source -> !sw, none, sw, m_sw - uint16_t tmrVal ; -}) TimerMode ; - -//PACK(typedef struct t_swVoice { -// uint8_t swtch:5 ; -// uint8_t mode:3 ; // ON, OFF, BOTH, 15Secs, 30Secs, 60Secs -// uint8_t val ; -//}) old_voiceSwData ; - - -PACK(typedef struct t_ModelData { - char name[MODEL_NAME_LEN]; // 10 must be first for eeLoadModelName - uint8_t modelVoice ; // Index to model name voice (261+value) - uint8_t RxNum ; // was timer trigger source, now RxNum for model match - uint8_t sparex:1; // was tmrDir, now use tmrVal>0 => count down - uint8_t traineron:1; // 0 disable trainer, 1 allow trainer - uint8_t spare22:1 ; // Start timer2 using throttle - uint8_t FrSkyUsrProto:1 ; // Protocol in FrSky User Data, 0=FrSky Hub, 1=WS HowHigh - uint8_t FrSkyGpsAlt:1 ; // Use Gps Altitude as main altitude reading - uint8_t FrSkyImperial:1 ; // Convert FrSky values to imperial units - uint8_t FrSkyAltAlarm:2; - uint8_t version ; - uint8_t spare_u8 ; // Was timerval - uint8_t protocol; - int8_t ppmNCH; - uint8_t thrTrim:1; // Enable Throttle Trim - uint8_t numBlades:2; // RPM scaling - uint8_t spare10:1; - uint8_t thrExpo:1; // Enable Throttle Expo - uint8_t spare11:3; - int8_t trimInc; // Trim Increments - int8_t ppmDelay; - int8_t trimSw; - uint8_t beepANACenter; // 1<<0->A1.. 1<<6->A7 - uint8_t pulsePol:1; - uint8_t extendedLimits:1; - uint8_t swashInvertELE:1; - uint8_t swashInvertAIL:1; - uint8_t swashInvertCOL:1; - uint8_t swashType:3; - uint8_t swashCollectiveSource; - uint8_t swashRingValue; - int8_t ppmFrameLength; //0=22.5 (10msec-30msec) 0.5msec increments - MixData mixData[MAX_MIXERS]; - LimitData limitData[NUM_CHNOUT]; - ExpoData expoData[4]; - int8_t trim[4]; - int8_t curves5[MAX_CURVE5][5]; - int8_t curves9[MAX_CURVE9][9]; - CSwData customSw[NUM_CSW]; -// uint8_t rxnum; - uint8_t frSkyVoltThreshold ; - uint8_t bt_telemetry; - uint8_t numVoice; // 0-16, rest are Safety switches - SafetySwData safetySw[NUM_CHNOUT]; - FrSkyData frsky; - TimerMode timer[2] ; - FrSkyAlarmData frskyAlarms ; -// Add 6 bytes for custom telemetry screen - uint8_t customDisplayIndex[6] ; -}) ModelData; - -#define TOTAL_EEPROM_USAGE (sizeof(ModelData)*MAX_MODELS + sizeof(EEGeneral)) - - -extern EEGeneral g_eeGeneral; -extern ModelData g_oldmodel; - -PACK(typedef struct t_PhaseData { - int16_t trim[4]; // -500..500 => trim value, 501 => use trim of phase 0, 502, 503, 504 => use trim of phases 1|2|3|4 instead - int8_t swtch; // swtch of phase[0] is not used - char name[6]; - uint8_t fadeIn:4; - uint8_t fadeOut:4; - uint16_t spare ; // Future expansion -}) PhaseData; - -PACK(typedef struct te_MixData { - uint8_t destCh; // 1..NUM_CHNOUT - uint8_t srcRaw; // - int8_t weight; - int8_t swtch; - int8_t curve; //0=symmetrisch 1=no neg 2=no pos - uint8_t delayUp; - uint8_t delayDown; - uint8_t speedUp; // Servogeschwindigkeit aus Tabelle (10ms Cycle) - uint8_t speedDown; // 0 nichts - uint8_t carryTrim:1; - uint8_t mltpx:2; // multiplex method 0=+ 1=* 2=replace - uint8_t lateOffset:1; // Add offset later - uint8_t mixWarn:2; // mixer warning - uint8_t enableFmTrim:1; - uint8_t differential:1 ; - int8_t sOffset; - uint8_t res[4]; -}) SKYMixData; - -PACK(typedef struct te_CSwData { // Custom Switches data - int8_t v1; //input - int8_t v2; //offset - uint8_t func; - int8_t andsw; - uint8_t res ; -}) SKYCSwData; - -PACK(typedef struct te_SafetySwData { // Safety Switches data - union opt - { - struct ss - { - int8_t swtch ; - uint8_t mode ; - int8_t val ; - uint8_t res ; - } ss ; - struct vs - { - uint8_t vswtch ; - uint8_t vmode ; // ON, OFF, BOTH, 15Secs, 30Secs, 60Secs, Varibl - uint8_t vval; - uint8_t vres ; - } vs ; - } opt ; -}) SKYSafetySwData; - -PACK(typedef struct te_FrSkyChannelData { - uint8_t ratio ; // 0.0 means not used, 0.1V steps EG. 6.6 Volts = 66. 25.1V = 251, etc. - uint8_t offset ; // - uint8_t gain ; // - uint8_t alarms_value[2] ; // 0.1V steps EG. 6.6 Volts = 66. 25.1V = 251, etc. - uint8_t alarms_level ; - uint8_t alarms_greater ; // 0=LT(<), 1=GT(>) - uint8_t type ; // 0=volts, 1=raw, 2=volts*2, 3=Amps -}) SKYFrSkyChannelData; - -PACK(typedef struct te_FrSkyData { - SKYFrSkyChannelData channels[2]; -}) SKYFrSkyData; - -PACK(typedef struct te_swVoice { - uint8_t swtch ; - uint8_t mode ; // ON, OFF, BOTH, 15Secs, 30Secs, 60Secs - uint8_t val ; - uint8_t vres ; -}) voiceSwData ; - -PACK(typedef struct t_FunctionData { // Function data - int8_t swtch ; //input - uint8_t func ; - uint8_t param[6] ; - uint8_t spare1 ; - uint8_t spare2 ; -}) FunctionData; - -PACK(typedef struct t_Vario -{ - uint8_t varioSource ; - int8_t swtch ; - uint8_t sinkTones:1 ; - uint8_t spare:1 ; - uint8_t param:6 ; -}) VarioData ; - -PACK(typedef struct t_gvar { - int8_t gvar ; - uint8_t gvsource ; -// int8_t gvswitch ; -}) GvarData ; - -PACK(typedef struct te_ModelData { - char name[MODEL_NAME_LEN]; // 10 must be first for eeLoadModelName - uint8_t modelVoice ; // Index to model name voice (261+value) - uint8_t RxNum ; // was timer trigger source, now RxNum for model match - uint8_t telemetryRxInvert:1 ; // was tmrDir, now use tmrVal>0 => count down - uint8_t traineron:1; // 0 disable trainer, 1 allow trainer - uint8_t spare15:1 ; - uint8_t FrSkyUsrProto:1 ; // Protocol in FrSky User Data, 0=FrSky Hub, 1=WS HowHigh - uint8_t FrSkyGpsAlt:1 ; // Use Gps Altitude as main altitude reading - uint8_t FrSkyImperial:1 ; // Convert FrSky values to imperial units - uint8_t FrSkyAltAlarm:2; - uint8_t modelVersion ; - uint8_t protocol:4 ; - uint8_t country:2 ; - uint8_t sub_protocol:2 ; - int8_t ppmNCH; - uint8_t thrTrim:1; // Enable Throttle Trim - uint8_t xnumBlades:2; // RPM scaling, now elsewhere as uint8_t - uint8_t extendedTrims:1; // Only applies to phases - uint8_t thrExpo:1; // Enable Throttle Expo - uint8_t frskyComPort:1; - uint8_t spare11:2; - int8_t trimInc; // Trim Increments - int8_t ppmDelay; - int8_t trimSw; - uint8_t beepANACenter; // 1<<0->A1.. 1<<6->A7 - uint8_t pulsePol:1; - uint8_t extendedLimits:1; - uint8_t swashInvertELE:1; - uint8_t swashInvertAIL:1; - uint8_t swashInvertCOL:1; - uint8_t swashType:3; - uint8_t swashCollectiveSource; - uint8_t swashRingValue; - int8_t ppmFrameLength; //0=22.5 (10msec-30msec) 0.5msec increments - SKYMixData mixData[MAX_SKYMIXERS]; - LimitData limitData[NUM_SKYCHNOUT]; - ExpoData expoData[4]; - int8_t trim[4]; - int8_t curves5[MAX_CURVE5][5]; - int8_t curves9[MAX_CURVE9][9]; - int8_t curvexy[18]; - SKYCSwData customSw[NUM_SKYCSW]; -// uint8_t rxnum; - uint8_t frSkyVoltThreshold ; - uint8_t bt_telemetry; - uint8_t numVoice; // 0-16, rest are Safety switches - SKYSafetySwData safetySw[NUM_SKYCHNOUT]; - voiceSwData voiceSwitches[NUM_VOICE] ; - SKYFrSkyData frsky; - TimerMode timer[2] ; - FrSkyAlarmData frskyAlarms ; -// Add 6 bytes for custom telemetry screen - uint8_t customDisplayIndex[6] ; - FunctionData functionData[NUM_FSW]; - PhaseData phaseData[MAX_PHASES] ; - GvarData gvars[MAX_GVARS] ; - uint8_t numBlades ; // RPM scaling - uint8_t startChannel ; // for main output 0 = ch1 - uint8_t startPPM2channel ; // for PPM2 output 0 follow - int8_t ppm2NCH ; - uint8_t sub_trim_limit ; - uint8_t FASoffset ; // 0.0 to 1.5 - VarioData varioData ; - uint8_t anaVolume ; // analog volume control - int8_t pxxFailsafe[16] ; - int8_t logSwitch ; - uint8_t logRate ; - // X9D ext module - uint8_t xprotocol:4 ; - uint8_t xcountry:2 ; - uint8_t xsub_protocol:2 ; - int8_t xppmNCH ; - int8_t xppmDelay ; - uint8_t xpulsePol ; - int8_t xppmFrameLength; //0=22.5 (10msec-30msec) 0.5msec increments - uint8_t xstartChannel ; // for output 0 = ch1 - uint8_t pxxRxNum ; - int8_t dsmMode ; - uint8_t xPxxRxNum ; // For external module - uint16_t modelswitchWarningStates ; // Enough bits for Taranis - int8_t enRssiOrange:2 ; - int8_t rssiOrange:6 ; - uint8_t enRssiRed:2 ; - int8_t rssiRed:6 ; -// uint8_t spare24:6 ; -// uint8_t curentSource ; -// uint8_t altSource ; -}) SKYModelData; - - -extern SKYModelData g_model; - - - - -#endif -/*eof*/ - - - diff --git a/radio/bootloader/include/timers.h b/radio/bootloader/include/timers.h deleted file mode 100644 index d617d0df4..000000000 --- a/radio/bootloader/include/timers.h +++ /dev/null @@ -1,45 +0,0 @@ -/**************************************************************************** -* Copyright (c) 2012 by Michael Blandford. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License version 2 as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* -****************************************************************************/ - - - - -void init5msTimer( void ) ; -void stop5msTimer( void ) ; - -#ifdef PCBSKY -extern void start_timer0( void ) ; -extern void stop_timer0( void ) ; -extern void init_pwm( void ) ; -#endif - -#ifdef PCBTARANIS -extern uint32_t Peri1_frequency ; -extern uint32_t Peri2_frequency ; -extern uint32_t Timer_mult1 ; -extern uint32_t Timer_mult2 ; -extern void init_hw_timer( void ) ; -extern void hw_delay( uint16_t time ) ; -extern void init_main_ppm( void ) ; -extern void disable_main_ppm( void ) ; -extern void init_trainer_ppm( void ) ; -extern void init_trainer_capture( void ) ; -extern void setupPulsesPXX(uint8_t module) ; -extern void setupPulses( unsigned int port ) ; -extern void setupPulsesPpm( void ) ; - -#endif - - diff --git a/radio/bootloader/lcd_driver.cpp b/radio/bootloader/lcd_driver.cpp deleted file mode 100644 index dd36230db..000000000 --- a/radio/bootloader/lcd_driver.cpp +++ /dev/null @@ -1,314 +0,0 @@ -/** - ****************************************************************************** - * @file Project/lcd/lcd.c - * @author X9D Application Team - * @Hardware version V0.2 - * @date 11-July-2012 - * @brief This file provides LCD Init and botom drivers. - * * - ****************************************************************************** -*/ - -#include "radio.h" - -#include "stm32f2xx.h" -#include "stm32f2xx_gpio.h" -#include "stm32f2xx_rcc.h" -#include "hal.h" -#include "../src/targets/taranis/aspi.h" - -#include "timers.h" -#include "lcd.h" -#include "logicio.h" - -#define WriteData(x) AspiData(x) -#define WriteCommand(x) AspiCmd(x) -#define CONTRAST_OFS 5 - -#define __no_operation __NOP - - -extern uint8_t DisplayBuf[] ; - -void Set_Address(uint8_t x, uint8_t y) -{ - WriteCommand(x&0x0F); //Set Column Address LSB CA[3:0] - WriteCommand((x>>4)|0x10); //Set Column Address MSB CA[7:4] - - WriteCommand((y&0x0F)|0x60); //Set Row Address LSB RA [3:0] - WriteCommand(((y>>4)&0x0F)|0x70); //Set Row Address MSB RA [7:4] -} - -void refreshDisplay() -{ - for (uint32_t y=0; y>3)*DISPLAY_W]; - uint8_t mask = (1 << (y%8)); - GPIO_TypeDef *gpiod = GPIOD ; - Set_Address(0, y); - AspiCmd(0xAF); - - gpiod->BSRRL = PIN_LCD_CLK ; // Clock high - gpiod->BSRRL = PIN_LCD_A0 ; // A0 high - gpiod->BSRRH = PIN_LCD_NCS ; // CS low - - for (uint32_t x=0; xBSRRL = PIN_LCD_MOSI ; - } - else - { - gpiod->BSRRH = PIN_LCD_MOSI ; - } - gpiod->BSRRH = PIN_LCD_CLK ; // Clock low - - if(data&0x40) - { - gpiod->BSRRL = PIN_LCD_MOSI | PIN_LCD_CLK ; - } - else - { - *(uint32_t *)&gpiod->BSRRL = (PIN_LCD_MOSI<<16) | PIN_LCD_CLK ; - } - __no_operation() ; - gpiod->BSRRH = PIN_LCD_CLK ; // Clock low - - if(data&0x20) - { - gpiod->BSRRL = PIN_LCD_MOSI | PIN_LCD_CLK ; - } - else - { - *(uint32_t *)&gpiod->BSRRL = (PIN_LCD_MOSI<<16) | PIN_LCD_CLK ; - } - __no_operation() ; - gpiod->BSRRH = PIN_LCD_CLK ; // Clock low - - if(data&0x10) - { - gpiod->BSRRL = PIN_LCD_MOSI | PIN_LCD_CLK ; - } - else - { - *(uint32_t *)&gpiod->BSRRL = (PIN_LCD_MOSI<<16) | PIN_LCD_CLK ; - } - __no_operation() ; - gpiod->BSRRH = PIN_LCD_CLK ; // Clock low - - if(data&0x08) - { - gpiod->BSRRL = PIN_LCD_MOSI | PIN_LCD_CLK ; - } - else - { - *(uint32_t *)&gpiod->BSRRL = (PIN_LCD_MOSI<<16) | PIN_LCD_CLK ; - } - __no_operation() ; - gpiod->BSRRH = PIN_LCD_CLK ; // Clock low - - if(data&0x04) - { - gpiod->BSRRL = PIN_LCD_MOSI | PIN_LCD_CLK ; - } - else - { - *(uint32_t *)&gpiod->BSRRL = (PIN_LCD_MOSI<<16) | PIN_LCD_CLK ; - } - __no_operation() ; - gpiod->BSRRH = PIN_LCD_CLK ; // Clock low - - if(data&0x02) - { - gpiod->BSRRL = PIN_LCD_MOSI | PIN_LCD_CLK ; - } - else - { - *(uint32_t *)&gpiod->BSRRL = (PIN_LCD_MOSI<<16) | PIN_LCD_CLK ; - } - __no_operation() ; - gpiod->BSRRH = PIN_LCD_CLK ; // Clock low - - if(data&0x01) - { - gpiod->BSRRL = PIN_LCD_MOSI | PIN_LCD_CLK ; - } - else - { - *(uint32_t *)&gpiod->BSRRL = (PIN_LCD_MOSI<<16) | PIN_LCD_CLK ; - } - __no_operation() ; - gpiod->BSRRH = PIN_LCD_CLK ; // Clock low - __no_operation() ; - gpiod->BSRRL = PIN_LCD_CLK ; // Clock high - - } - gpiod->BSRRL = PIN_LCD_NCS ; - gpiod->BSRRL = PIN_LCD_A0 ; - WriteData(0); - } -} - -uint16_t BacklightBrightness ; - -void backlight_on() -{ - TIM10->CCR1 = 100 - BacklightBrightness ; -} - -void backlight_off() -{ - TIM10->CCR1 = 0 ; -} - -void backlight_set( uint16_t brightness ) -{ - BacklightBrightness = brightness ; - TIM10->CCR1 = 100 - BacklightBrightness ; -} - - -/**Init the Backlight GPIO */ -static void LCD_BL_Config() -{ - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOBL, ENABLE); - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin =GPIO_Pin_BL; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(GPIOBL, &GPIO_InitStructure); - - GPIO_PinAFConfig(GPIOBL, GPIO_PinSource_BL ,GPIO_AF_TIM10); - - RCC->APB2ENR |= RCC_APB2ENR_TIM10EN ; // Enable clock - TIM10->ARR = 100 ; - TIM10->PSC = (Peri2_frequency*Timer_mult2) / 10000 - 1 ; // 100uS from 30MHz - TIM10->CCMR1 = 0x60 ; // PWM - TIM10->CCER = 1 ; - - BacklightBrightness = 80 ; - TIM10->CCR1 = BacklightBrightness ; - TIM10->EGR = 0 ; - TIM10->CR1 = 1 ; -} - -/** Init the anolog spi gpio -*/ -static void LCD_Hardware_Init() -{ - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_LCD, ENABLE); - - GPIO_InitTypeDef GPIO_InitStructure; - - /*!< Configure lcd CLK\ MOSI\ A0pin in output pushpull mode *************/ - GPIO_InitStructure.GPIO_Pin =PIN_LCD_MOSI | PIN_LCD_CLK | PIN_LCD_A0; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(GPIO_LCD, &GPIO_InitStructure); - - /*!< Configure lcd NCS pin in output pushpull mode ,PULLUP *************/ - GPIO_InitStructure.GPIO_Pin = PIN_LCD_NCS | PIN_LCD_RST ; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - - GPIO_Init(GPIO_LCD, &GPIO_InitStructure); -} - -static void LCD_Init() -{ - LCD_BL_Config() ; - /*Hardware Reset need delay*/ - /*LCD_RST_LOW(); - Delay(50); - LCD_RST_HIGH();*/ - - AspiCmd(0x25); //Temperature compensation curve definition: 0x25 = -0.05%/oC - AspiCmd(0x2b); //Panel loading set ,Internal VLCD. - AspiCmd(0xEA); //set bias=1/10 :Command table NO.27 - AspiCmd(0x81); //Set Vop - AspiCmd(25+CONTRAST_OFS); //0--255 - AspiCmd(0xA6); //inverse display off - AspiCmd(0xD1); //SET RGB:Command table NO.21 .SET RGB or BGR. D1=RGB - AspiCmd(0xD5); //set color mode 4K and 12bits :Command table NO.22 - AspiCmd(0xA0); //line rates,25.2 Klps - AspiCmd(0xC8); //SET N-LINE INVERSION - AspiCmd(0x1D); //Disable NIV - AspiCmd(0xF1); //Set CEN - AspiCmd(0x3F); // 1/64DUTY - AspiCmd(0x84); //Disable Partial Display - AspiCmd(0xC4); //MY=1,MX=0 - AspiCmd(0x89); //WA=1,column (CA) increment (+1) first until CA reaches CA boundary, then RA will increment by (+1). - - AspiCmd(0xF8); //Set Window Program Enable ,inside modle - AspiCmd(0xF4); //starting column address of RAM program window. - AspiCmd(0x00); - AspiCmd(0xF5); //starting row address of RAM program window. - AspiCmd(0x60); - AspiCmd(0xF6); //ending column address of RAM program window. - AspiCmd(0x47); - AspiCmd(0xF7); //ending row address of RAM program window. - AspiCmd(0x9F); - - AspiCmd(0xAF); //dc2=1,IC into exit SLEEP MODE, dc3=1 gray=ON ���ҽ� ,dc4=1 Green Enhanc mode disabled ��ɫ��ǿģʽ�� - -} - -static void Delay(volatile unsigned int ms) -{ - volatile u8 i; - while(ms != 0) - { - for(i=0;i<250;i++) {} - for(i=0;i<75;i++) {} - ms--; - } -} - -void lcd_init() -{ - GPIO_TypeDef *gpiod = GPIOD ; - - LCD_BL_Config(); - LCD_Hardware_Init(); - - gpiod->BSRRL = PIN_LCD_RST ; // RST high - Delay(5); - - gpiod->BSRRH = PIN_LCD_RST ; // RST low - Delay(120); //11ms - - gpiod->BSRRL = PIN_LCD_RST ; // RST high - Delay(2500); - - AspiCmd(0xE2); - Delay(2500); - - LCD_Init(); - Delay(120); - AspiCmd(0xAF); //dc2=1, IC into exit SLEEP MODE, dc3=1 gray=ON, dc4=1 Green Enhanc mode disabled -} - -void lcdSetRefVolt(uint8_t val) -{ - AspiCmd(0x81); //Set Vop - AspiCmd(val+CONTRAST_OFS); //0--255 -} diff --git a/radio/bootloader/usbd_storage_msd.cpp b/radio/bootloader/usbd_storage_msd.cpp index 4aa3804d3..2552e02be 100644 --- a/radio/bootloader/usbd_storage_msd.cpp +++ b/radio/bootloader/usbd_storage_msd.cpp @@ -27,7 +27,7 @@ /* Includes ------------------------------------------------------------------*/ #include "radio.h" -#include "eeprom_rlc.h" +#include "../src/eeprom_rlc.h" #include #include //#include diff --git a/radio/src/eeprom_rlc.h b/radio/src/eeprom_rlc.h index db285a6fe..76bf5cdff 100644 --- a/radio/src/eeprom_rlc.h +++ b/radio/src/eeprom_rlc.h @@ -34,11 +34,16 @@ * */ -#ifndef eeprom_avr_h -#define eeprom_avr_h +#ifndef eeprom_rlc_h +#define eeprom_rlc_h #include +// TODO duplicated +#ifndef PACK +#define PACK( __Declaration__ ) __Declaration__ __attribute__((__packed__)) +#endif + #if defined(PCBTARANIS) #define blkid_t uint16_t #if !defined(EESIZE) @@ -67,7 +72,7 @@ #define BS 16 #endif -PACK(struct DirEnt{ +PACK(struct DirEnt { blkid_t startBlk; uint16_t size:12; uint16_t typ:4; @@ -79,7 +84,7 @@ PACK(struct DirEnt{ #define EEFS_EXTRA_FIELDS #endif -PACK(struct EeFs{ +PACK(struct EeFs { uint8_t version; blkid_t mySize; blkid_t freeList; diff --git a/radio/src/lcd.cpp b/radio/src/lcd.cpp index 0bfd78820..f65811a0a 100644 --- a/radio/src/lcd.cpp +++ b/radio/src/lcd.cpp @@ -49,6 +49,7 @@ void lcd_clear() memset(displayBuf, 0, sizeof(displayBuf)); } +#if !defined(BOOT) void lcd_img(xcoord_t x, uint8_t y, const pm_uchar * img, uint8_t idx, LcdFlags att) { const pm_uchar *q = img; @@ -84,6 +85,7 @@ void lcd_img(xcoord_t x, uint8_t y, const pm_uchar * img, uint8_t idx, LcdFlags } } } +#endif uint8_t lcdLastPos; uint8_t lcdNextPos; @@ -177,7 +179,7 @@ void lcd_putcAtt(xcoord_t x, uint8_t y, const unsigned char c, LcdFlags flags) } } -#if defined(CPUARM) +#if defined(CPUARM) && !defined(BOOT) else if (flags & MIDSIZE) { /* each letter consists of ten top bytes followed by * by ten bottom bytes (20 bytes per * char) */ @@ -329,7 +331,7 @@ void lcd_putcAtt(xcoord_t x, uint8_t y, const unsigned char c, LcdFlags flags) LCD_BYTE_FILTER(r, ~mask, b >> (8-ym8)); } -#if defined(PCBTARANIS) +#if defined(PCBTARANIS) && !defined(BOOT) if (inv) { if (ym8) lcd_mask(p, 0x01 << (ym8-1), FORCE); else if (y) { @@ -369,9 +371,11 @@ void lcd_putsnAtt(xcoord_t x, uint8_t y, const pm_char * s, uint8_t len, LcdFlag case BSS: c = *s; break; +#if !defined(BOOT) case ZCHAR: c = idx2char(*s); break; +#endif default: c = pgm_read_byte(s); break; @@ -854,6 +858,7 @@ void lcd_invert_line(int8_t y) } } +#if !defined(BOOT) #if defined(PCBTARANIS) void lcdDrawTelemetryTopBar() { @@ -885,6 +890,7 @@ void lcdDrawTelemetryTopBar() lcd_invert_line(0); } #endif +#endif void putsTime(xcoord_t x, uint8_t y, putstime_t tme, LcdFlags att, LcdFlags att2) { @@ -929,6 +935,7 @@ void putsTime(xcoord_t x, uint8_t y, putstime_t tme, LcdFlags att, LcdFlags att2 lcd_outdezNAtt(lcdNextPos, y, qr.rem, att2|LEADING0|LEFT, 2); } +#if !defined(BOOT) // TODO to be optimized with putsTelemetryValue void putsVolts(xcoord_t x, uint8_t y, uint16_t volts, LcdFlags att) { @@ -1175,7 +1182,7 @@ void putsRotaryEncoderMode(xcoord_t x, uint8_t y, uint8_t phase, uint8_t idx, Lc } #endif -#if defined(FRSKY) || defined(CPUARM) +#if (defined(FRSKY) || defined(CPUARM)) && !defined(BOOT) void putsTelemetryValue(xcoord_t x, uint8_t y, lcdint_t val, uint8_t unit, uint8_t att) { convertUnit(val, unit); @@ -1333,3 +1340,4 @@ void lcdSetContrast() { lcdSetRefVolt(g_eeGeneral.contrast); } +#endif diff --git a/radio/src/lcd.h b/radio/src/lcd.h index 5becc5c57..29dcf4b16 100644 --- a/radio/src/lcd.h +++ b/radio/src/lcd.h @@ -149,6 +149,12 @@ extern uint8_t lcdNextPos; extern volatile uint32_t lcdInputs ; #endif +#if defined(BOOT) +// TODO quick & dirty :( +typedef const unsigned char pm_uchar; +typedef const char pm_char; +#endif + void lcd_putc(xcoord_t x, uint8_t y, const unsigned char c); void lcd_putcAtt(xcoord_t x, uint8_t y, const unsigned char c, LcdFlags mode); void lcd_putsAtt(xcoord_t x, uint8_t y, const pm_char * s, LcdFlags mode); @@ -169,7 +175,7 @@ void putsModelName(xcoord_t x, uint8_t y, char *name, uint8_t id, LcdFlags att); void putsSwitches(xcoord_t x, uint8_t y, int8_t swtch, LcdFlags att=0); void putsMixerSource(xcoord_t x, uint8_t y, uint8_t idx, LcdFlags att=0); void putsFlightPhase(xcoord_t x, uint8_t y, int8_t idx, LcdFlags att=0); -#if defined(PCBTARANIS) +#if defined(PCBTARANIS) && !defined(BOOT) void putsCurveRef(xcoord_t x, uint8_t y, CurveRef &curve, LcdFlags att); #endif void putsCurve(xcoord_t x, uint8_t y, int8_t idx, LcdFlags att=0); @@ -249,7 +255,11 @@ void lcdRefresh(); const pm_char * bmpLoad(bmp_ptr_t &dest, const char *filename, const xcoord_t width, const uint8_t height); #endif -#define BLINK_ON_PHASE (g_blinkTmr10ms & (1<<6)) +#if defined(BOOT) + #define BLINK_ON_PHASE (0) +#else + #define BLINK_ON_PHASE (g_blinkTmr10ms & (1<<6)) +#endif #ifdef SIMU extern bool lcd_refresh; diff --git a/radio/src/opentx.h b/radio/src/opentx.h index 9534ae9e1..22c49abe5 100644 --- a/radio/src/opentx.h +++ b/radio/src/opentx.h @@ -1513,9 +1513,7 @@ enum AUDIO_SOUNDS { #include "targets/gruvin9x/somo14d.h" #endif -#if !defined(BOOT) #include "translations.h" -#endif #if defined(HAPTIC) #include "haptic.h" @@ -1634,7 +1632,7 @@ extern union ReusableBuffer reusableBuffer; void checkFlashOnBeep(); #if defined(FRSKY) || defined(CPUARM) -FORCEINLINE void convertUnit(getvalue_t & val, uint8_t & unit); +void convertUnit(getvalue_t & val, uint8_t & unit); // TODO check FORCEINLINE on stock void putsTelemetryValue(xcoord_t x, uint8_t y, lcdint_t val, uint8_t unit, uint8_t att); #else #define convertUnit(...) diff --git a/radio/src/targets/taranis/lcd_driver.cpp b/radio/src/targets/taranis/lcd_driver.cpp index 991fb952b..5b8c2a6bd 100644 --- a/radio/src/targets/taranis/lcd_driver.cpp +++ b/radio/src/targets/taranis/lcd_driver.cpp @@ -9,7 +9,7 @@ ****************************************************************************** */ -#include "../opentx.h" +#include "../../opentx.h" #define WriteData(x) AspiData(x) #define WriteCommand(x) AspiCmd(x) @@ -21,7 +21,11 @@ static void LCD_Init() AspiCmd(0x25); //Temperature compensation curve definition: 0x25 = -0.05%/oC AspiCmd(0xEA); //set bias=1/10 :Command table NO.27 AspiCmd(0x81); //Set Vop +#if defined(BOOT) + AspiCmd(CONTRAST_OFS); +#else AspiCmd(g_eeGeneral.contrast+CONTRAST_OFS); //0--255 +#endif AspiCmd(0xA6); //inverse display off AspiCmd(0xD1); //SET RGB:Command table NO.21 .SET RGB or BGR. D1=RGB AspiCmd(0xD5); //set color mode 4K and 12bits :Command table NO.22 From b506259d76fcbbbc576ac786f02173108b8a65f5 Mon Sep 17 00:00:00 2001 From: mhotar Date: Tue, 4 Mar 2014 21:52:54 +0100 Subject: [PATCH 028/285] Conflicts fix --- radio/src/translations.cpp | 2 - radio/src/translations.h | 2 - radio/src/translations/de.h.txt | 229 +++++++++-------- radio/src/translations/en.h.txt | 95 +++---- radio/src/translations/fr.h.txt | 441 ++++++++++++++++---------------- 5 files changed, 390 insertions(+), 379 deletions(-) diff --git a/radio/src/translations.cpp b/radio/src/translations.cpp index 98c1066f1..8e9e8f2d7 100644 --- a/radio/src/translations.cpp +++ b/radio/src/translations.cpp @@ -499,8 +499,6 @@ const pm_char STR_VIEW_TEXT[] PROGMEM = "View text"; const pm_char STR_PREFLIGHT[] PROGMEM = TR_PREFLIGHT; const pm_char STR_CHECKLIST[] PROGMEM = TR_CHECKLIST; const pm_char STR_UART3MODE[] PROGMEM = TR_UART3MODE; - const pm_char STR_POT1TYPE[] PROGMEM = TR_POT1TYPE; - const pm_char STR_POT2TYPE[] PROGMEM = TR_POT2TYPE; const pm_char STR_THROTTLE_LABEL[] PROGMEM = TR_THROTTLE_LABEL; #endif diff --git a/radio/src/translations.h b/radio/src/translations.h index e51a262b6..ac0436349 100644 --- a/radio/src/translations.h +++ b/radio/src/translations.h @@ -690,8 +690,6 @@ extern const pm_char STR_VIEW_TEXT[]; extern const pm_char STR_PREFLIGHT[]; extern const pm_char STR_CHECKLIST[]; extern const pm_char STR_UART3MODE[]; - extern const pm_char STR_POT1TYPE[]; - extern const pm_char STR_POT2TYPE[]; extern const pm_char STR_THROTTLE_LABEL[]; #endif diff --git a/radio/src/translations/de.h.txt b/radio/src/translations/de.h.txt index 857d8a341..f6ca1c69d 100644 --- a/radio/src/translations/de.h.txt +++ b/radio/src/translations/de.h.txt @@ -3,9 +3,6 @@ * - Bertrand Songis * - Bernet Andre * - Helle - * - Kjell Kernen - * - Martin Hotar - * - Romolo Manfredini * * opentx is based on code named * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, @@ -235,13 +232,13 @@ #endif #define TR_CFN_RESERVE "[Reserve]\0" - #define TR_VFSWFUNC "Sicher\0 ""Lehrer \0 ""Inst. Trim""Rücksetz.\0""Setze \0 " TR_ADJUST_GVAR "Lautstr.\0 " TR_CFN_RESERVE TR_CFN_RESERVE TR_CFN_RESERVE TR_SOUND TR_PLAY_TRACK TR_PLAY_VALUE TR_CFN_RESERVE TR_CFN_RESERVE TR_CFN_RESERVE TR_CFN_BG_MUSIC TR_VVARIO TR_HAPTIC TR_SDCLOGS "LCD Licht\0" TR_CFN_TEST + #if defined(CPUARM) - #define TR_VFSWFUNC "Sicher\0 ""Lehrer \0 ""Inst. Trim""Rücksetz.\0" TR_ADJUST_GVAR TR_SOUND TR_PLAY_TRACK TR_PLAY_BOTH TR_PLAY_VALUE TR_VVARIO TR_HAPTIC TR_SDCLOGS "LCD Licht\0" TR_CFN_TEST + #define TR_VFSWFUNC "Sicher\0 ""Lehrer \0 ""Inst. Trim""Rücksetz.\0""Setze \0 " TR_ADJUST_GVAR "Lautstr.\0 " TR_CFN_RESERVE TR_CFN_RESERVE TR_CFN_RESERVE TR_SOUND TR_PLAY_TRACK TR_PLAY_VALUE TR_CFN_RESERVE TR_CFN_RESERVE TR_CFN_RESERVE TR_CFN_BG_MUSIC TR_VVARIO TR_HAPTIC TR_SDCLOGS "LCD Licht\0" TR_CFN_TEST #elif defined(PCBGRUVIN9X) - #define TR_VFSWFUNC "Sicher\0 ""Lehrer \0 ""Inst. Trim""Rücksetz.\0" TR_ADJUST_GVAR TR_SOUND TR_PLAY_TRACK TR_PLAY_BOTH TR_PLAY_VALUE TR_VVARIO TR_HAPTIC "LCD Licht\0" TR_CFN_TEST + #define TR_VFSWFUNC "Sicher\0 ""Lehrer \0 ""Inst. Trim""Rücksetz.\0" TR_ADJUST_GVAR TR_SOUND TR_PLAY_TRACK TR_PLAY_BOTH TR_PLAY_VALUE TR_VVARIO TR_HAPTIC TR_SDCLOGS "LCD Licht\0" TR_CFN_TEST #else - #define TR_VFSWFUNC "Sicher\0 ""Lehrer \0 ""Inst. Trim""R\205cksetz.\0" TR_ADJUST_GVAR TR_SOUND TR_PLAY_TRACK TR_PLAY_BOTH TR_PLAY_VALUE TR_VVARIO TR_HAPTIC "LCD Licht\0" TR_CFN_TEST + #define TR_VFSWFUNC "Sicher\0 ""Lehrer \0 ""Inst. Trim""Rücksetz.\0" TR_ADJUST_GVAR TR_SOUND TR_PLAY_TRACK TR_PLAY_BOTH TR_PLAY_VALUE TR_VVARIO TR_HAPTIC "LCD Licht\0" TR_CFN_TEST #endif #define LEN_VFSWRESET TR("\004", "\011") @@ -251,11 +248,11 @@ #else #define TR_FSW_RESET_TELEM #endif - #define TR_FSW_RESET_ROTENC TR("DGa\0""DGb\0", "DrehGb A\0""DrehGb B\0") + #if ROTARY_ENCODERS == 2 - #define TR_FSW_RESET_ROTENC TR("D.G.", "DrehGb\0 ") + #define TR_FSW_RESET_ROTENC TR("DGa\0""DGb\0", "DrehGb A\0""DrehGb B\0") #elif ROTARY_ENCODERS == 1 - #define TR_FSW_RESET_ROTENC TR("R.E.", "RotEnc\0 ") + #define TR_FSW_RESET_ROTENC TR("D.G.", "DrehGb\0 ") #else #define TR_FSW_RESET_ROTENC #endif @@ -266,18 +263,26 @@ #define TR_FUNCSOUNDS TR("Bp1\0""Bp2\0""Bp3\0""Wrn1""Wrn2""Chee""Rata""Tick""Sirn""Ring""SciF""Robt""Chrp""Tada""Crck""Alrm", "Piep1\0""Piep2\0""Piep3\0""Warn1 ""Warn2 ""Cheep ""Ratata""Tick ""Siren ""Ring ""SciFi ""Robot ""Chirp ""Tada ""Crickt""AlmClk") #define LEN_VTELEMCHNS "\004" -#if defined(PCBTARANIS) - #define TR_RSSI_0 "SWR\0" - #define TR_RSSI_1 "RSSI" -#else - #define TR_RSSI_0 "Tx\0 " - #define TR_RSSI_1 "Rx\0 " -#endif -#define TR_VTELEMCHNS "---\0""Batt""Uhr1""Uhr2" TR_RSSI_0 TR_RSSI_1 "A1\0 ""A2\0 ""H\203he""Umdr""Fuel""T1\0 ""T2\0 ""Gesc""Dist""GH\203h""Zell""Zels""Vfas""Strm""Verb""Leis""BesX""BesY""BesZ""Rich""VGes""ASpd""dTE\0""A1-\0""A2-\0""H\203h-""H\203h+""Umd+""T1+\0""T2+\0""Ges+""Dst+""Cel-""Cls-""Vfs-""Str+""Pwr+""Besc""Zeit" #if defined(CPUARM) - #define LEN_VUNITSSYSTEM TR("\006", "\010") - #define TR_VUNITSSYSTEM TR("Metrik""Imper.", "Metrisch\0 ""Imperial") + #define TR_TELEM_RESERVE "[--]" + #define TR_SWR "SWR\0" + #define TR_RX_BATT "RxBt" + #define TR_A3_A4 "A3\0 ""A4\0 " + #define TR_A3_A4_MIN "A3-\0""A4-\0" +#else + #define TR_TELEM_RESERVE + #define TR_SWR + #define TR_RX_BATT + #define TR_A3_A4 + #define TR_A3_A4_MIN +#endif + +#define TR_VTELEMCHNS "---\0""Batt""Tmr1""Tmr2" TR_SWR "Tx\0 ""Rx\0 " TR_RX_BATT "A1\0 ""A2\0 " TR_A3_A4 "Alt\0""Rpm\0""Fuel""T1\0 ""T2\0 ""Spd\0""Dist""GAlt""Cell""Cels""Vfas""Curr""Cnsp""Powr""AccX""AccY""AccZ""Hdg\0""VSpd""ASpd""dTE\0" TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE "A1-\0""A2-\0" TR_A3_A4_MIN "Alt-""Alt+""Rpm+""T1+\0""T2+\0""Spd+""Dst+""Cel-""Cls-""Vfs-""Cur+""Pwr+" TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE "Acc\0""Time" + +#if defined(CPUARM) + #define LEN_VUNITSSYSTEM TR("\006", "\012") + #define TR_VUNITSSYSTEM TR("Metrik""Imper.", "Metrisch\0 ""Imperial\0 ") #define LEN_VTELEMUNIT_NORM "\003" #define TR_VTELEMUNIT_NORM "V\0 ""A\0 ""m/s""-\0 ""kmh""m\0 ""@\0 ""%\0 ""mA\0""mAh""W\0 " #define LEN_VTELEMUNIT_IMP "\003" @@ -316,15 +321,15 @@ #define TR_VARIOSRC "Alti\0""Alti+""Vario""A1\0 ""A2\0" #endif -#define LEN_VSCREEN "\006" +#define LEN_VSCREEN "\006" #define TR_VSCREEN "Werte\0""Balken" //Telemetrie Werte oder Balken #define LEN_GPSFORMAT "\004" #define TR_GPSFORMAT "HMS\0""NMEA" //Koordinatenanzeige -#define LEN2_VTEMPLATES 15 // max String L\201nge f\205r Men\205 (original=13) -#define LEN_VTEMPLATES "\017" // max String L\201nge 15+cr+lf -#define TR_VTEMPLATES "Misch. L\203sch.\0 ""Einfach. 4-CH\0 ""Fixe Gassperre\0""V-Stabilisator\0""Delta Mischer\0 ""eCCPM\0 ""Hubschrauber\0 ""Servo Tester\0 " +#define LEN2_VTEMPLATES 15 // max String Länge für Menü (original=13) +#define LEN_VTEMPLATES "\017" // max String Länge 15+cr+lf +#define TR_VTEMPLATES "Misch. Lösch.\0 ""Einfach. 4-CH\0 ""Fixe Gassperre\0""V-Stabilisator\0""Delta Mischer\0 ""eCCPM\0 ""Hubschrauber\0 ""Servo Tester\0 " #define LEN_VSWASHTYPE "\004" #define TR_VSWASHTYPE "--- ""120 ""120X""140 ""90\0" @@ -339,7 +344,7 @@ #define LEN_VSRCRAW "\004" #if defined(PCBTARANIS) - #define TR_POTS_VSRCRAW "S1\0 ""S2\0 ""LS\0 ""RS\0 " //4 Potis S1,S2,Links,Rechts + #define TR_POTS_VSRCRAW "S1\0 ""S2\0 ""S3\0 ""LS\0 ""RS\0 " //4 Potis S1,S2,Links,Rechts #define TR_SW_VSRCRAW "SA\0 ""SB\0 ""SC\0 ""SD\0 ""SE\0 ""SF\0 ""SG\0 ""SH\0 " #elif defined(EXTRA_3POS) #define TR_POTS_VSRCRAW "P1\0 ""P2\0 " @@ -352,14 +357,14 @@ #endif #if defined(CPUARM) -#define TR_LOGICALSW "PS1""PS2""PS3""PS4""PS5""PS6""PS7""PS8""PS9""PSA""PSB""PSC""PSD""PSE""PSF""PSG""PSH""PSI""PSJ""PSK""PSL""PSM""PSN""PSO""PSP""PSQ""PSR""PSS""PST""PSU""PSV""PSW" + #define TR_LOGICALSW "LS1""LS2""LS3""LS4""LS5""LS6""LS7""LS8""LS9""LSA""LSB""LSC""LSD""LSE""LSF""LSG""LSH""LSI""LSJ""LSK""LSL""LSM""LSN""LSO""LSP""LSQ""LSR""LSS""LST""LSU""LSV""LSW" #elif defined(PCBGRUVIN9X) || defined(CPUM2561) || defined(CPUM128) - #define TR_LOGICALSW "PS1""PS2""PS3""PS4""PS5""PS6""PS7""PS8""PS9""PSA""PSB""PSC""PSD""PSE""PSF" + #define TR_LOGICALSW "LS1""LS2""LS3""LS4""LS5""LS6""LS7""LS8""LS9""LSA""LSB""LSC""LSD""LSE""LSF" #else - #define TR_LOGICALSW "PS1""PS2""PS3""PS4""PS5""PS6""PS7""PS8""PS9""PSA""PSB""PSC" + #define TR_LOGICALSW "LS1""LS2""LS3""LS4""LS5""LS6""LS7""LS8""LS9""LSA""LSB""LSC" #endif -#define TR_TRIMS_SWITCHES "tRl""tRr""tEd""tEu""tTd""tTu""tAl""tAr" +#define TR_TRIMS_SWITCHES "tSl""tSr""tHd""tHu""tGd""tGu""tQl""tQr" #if defined(PCBSKY9X) #define TR_ROTARY_ENCODERS "DGa\0" @@ -373,12 +378,12 @@ #endif #if defined(PCBTARANIS) - #define TR_6POS_POTS "P11""P12""P13""P14""P15""P16""P21""P22""P23""P24""P25""P26" + #define TR_6POS_POTS "P11""P12""P13""P14""P15""P16""P21""P22""P23""P24""P25""P26""P31""P32""P33""P34""P35""P36" #define TR_VSWITCHES "SA\300""SA-""SA\301""SB\300""SB-""SB\301""SC\300""SC-""SC\301""SD\300""SD-""SD\301""SE\300""SE-""SE\301""SF\300""SF\301""SG\300""SG-""SG\301""SH\300""SH\301" TR_6POS_POTS TR_TRIMS_SWITCHES TR_ROTENC_SWITCHES TR_LOGICALSW #elif defined(CPUARM) - #define TR_VSWITCHES TR_9X_3POS_SWITCHES "THR""RUD""ELE""AIL""GEA""TRN" TR_TRIMS_SWITCHES TR_ROTENC_SWITCHES TR_LOGICALSW + #define TR_VSWITCHES TR_9X_3POS_SWITCHES "THR""RUD""ELE""AIL""GEA""TRN" TR_TRIMS_SWITCHES TR_ROTENC_SWITCHES TR_CUSTOMSW #else - #define TR_VSWITCHES TR_9X_3POS_SWITCHES "THR""RUD""ELE""AIL""GEA""TRN" TR_TRIMS_SWITCHES TR_ROTENC_SWITCHES TR_LOGICALSW + #define TR_VSWITCHES TR_9X_3POS_SWITCHES "THR""RUD""ELE""AIL""GEA""TRN" TR_TRIMS_SWITCHES TR_ROTENC_SWITCHES TR_CUSTOMSW #endif #if defined(HELI) @@ -387,13 +392,13 @@ #define TR_CYC_VSRCRAW "[C1]""[C2]""[C3]" #endif -#define TR_VSRCRAW "---\0""Sei\0""H\203h\0""Gas\0""Que\0" TR_POTS_VSRCRAW TR_ROTARY_ENCODERS "MAX\0" TR_CYC_VSRCRAW "TrmS" "TrmH" "TrmG" "TrmQ" TR_SW_VSRCRAW +#define TR_VSRCRAW "---\0""Sei\0""Höh\0""Gas\0""Que\0" TR_POTS_VSRCRAW TR_ROTARY_ENCODERS "MAX\0" TR_CYC_VSRCRAW "TrmS" "TrmH" "TrmG" "TrmQ" TR_SW_VSRCRAW #define LEN_VTMRMODES "\003" #define TR_VTMRMODES "AUS""ABS""GSs""GS%""GSt" #define LEN_VTRAINERMODES "\007" // "\006" -#define TR_VTRAINERMODES "Lehrer\0""Sch\205ler\0" // "Master""Slave\0" +#define TR_VTRAINERMODES "Lehrer\0""Schüler\0" // "Master""Slave\0" #define LEN_VFAILSAFE "\011" #define TR_VFAILSAFE "Hold\0 ""Custom\0 ""No pulses" @@ -423,7 +428,7 @@ #define TR_MENUWHENDONE CENTER"\010"TR_ENTER" > Weiter" #define TR_FREE "frei" -#define TR_DELETEMODEL "Modell l\203schen?" +#define TR_DELETEMODEL "Modell löschen?" #define TR_COPYINGMODEL "Kopiere Modell" #define TR_MOVINGMODEL "Schiebe Modell" #define TR_LOADINGMODEL "Lade Modell..." @@ -438,12 +443,12 @@ #define TR_EXPONAME "Expo Name" #endif #define TR_BITMAP "Modell Bild" -#define TR_TIMER TR("Stoppuhr","Stoppuhr ") +#define TR_TIMER TR("Timer","Timer ") #define TR_ELIMITS TR("Erw.Limit","Erweit. Limits") -#define TR_TTRACE TR("Gasquelle","Gas Verfolgung") -#define TR_TTRIM TR("Gastrim","Gas Trimmung") -#define TR_TTRACE TR("Gasquelle","Gas Quelle") -#define TR_TTRIM TR("Gastrim","Gas Trimmung") +#define TR_ETRIMS TR("Erw.Trims","Erweit. Trimmung") +#define TR_TRIMINC TR("Trim Schr.","Trimm Schritte") +#define TR_TTRACE TR("Gasquelle", INDENT "Gas Verfolgung") +#define TR_TTRIM TR("Gastrim", INDENT "Gas Trimmung") #define TR_BEEPCTR TR("Mitt.Piep","Mittelst. Pieps") #define TR_PROTO TR(INDENT"Proto.",INDENT"Protokoll") #define TR_PPMFRAME "PPM Einst." @@ -453,14 +458,14 @@ #define TR_FADEIN "Langs. Ein" #define TR_FADEOUT "Langs. Aus" #define TR_DEFAULT "(Normal)" -#define TR_CHECKTRIMS "\006Trims\012Pr\205fen" +#define TR_CHECKTRIMS "\006Trims\012Prüfen" #define OFS_CHECKTRIMS (9*FW) #define TR_SWASHTYPE TR("Typ Taumelsch","Typ Taumelscheibe") #define TR_COLLECTIVE TR("Kollekt.Pitch","Kollekt. Pitch Kanal") #define TR_SWASHRING TR("Zykl. Begrenz","Zyklische Begrenzung") -#define TR_ELEDIRECTION TR("Nick Richtung"," Nick Servo Richtung") -#define TR_AILDIRECTION TR("Roll Richtung"," Roll Servo Richtung") -#define TR_COLDIRECTION TR("Pit. Richtung","Pitch Servo Richtung") +#define TR_ELEDIRECTION TR("Nick Richtung"," Nick Servo Richtung") +#define TR_AILDIRECTION TR("Roll Richtung"," Roll Servo Richtung") +#define TR_COLDIRECTION TR("Pit. Richtung"," Pitch Servo Richtung") #define TR_MODE INDENT"Modus" #define TR_NOFREEEXPO "Expos voll!" #define TR_NOFREEMIXER "Mischer voll!" @@ -491,36 +496,37 @@ #define TR_BAR "Streifen" #define TR_ALARM INDENT"Alarm" #define TR_USRDATA "Daten" -#define TR_BLADES INDENT"Bl\201tter" +#define TR_BLADES INDENT"Blätter" #define TR_SCREEN "Bild " -#define TR_SOUND_LABEL "T\203ne" -#define TR_LENGTH INDENT"Dauer" -#define TR_SPKRPITCH INDENT"Tonh\203he" +#define TR_SOUND_LABEL "----Töne---------" +#define TR_LENGTH INDENT"Dauer" +#define TR_SPKRPITCH INDENT"Tonhöhe" #define TR_HAPTIC_LABEL "Vibration" -#define TR_HAPTICSTRENGTH INDENT"St\201rke" -#define TR_CONTRAST "Kontrast" -#define TR_ALARMS_LABEL "Alarm wenn" +#define TR_HAPTICSTRENGTH INDENT"Stärke" +#define TR_CONTRAST "LCD Kontrast" +#define TR_ALARMS_LABEL "----Alarm wenn---" #define TR_BATTERY_RANGE TR("Akku Bereich","Akku Spg-Bereich") // Symbol Akku Ladezustand -#define TR_BATTERYWARNING INDENT"Akku Spg kl." -#define TR_INACTIVITYALARM INDENT"Inaktivit\201t " +#define TR_BATTERYWARNING INDENT"Akku Spg kleiner" +#define TR_INACTIVITYALARM INDENT"Inaktivität " #define TR_MEMORYWARNING INDENT"Speicher voll" #define TR_ALARMWARNING INDENT"Ton aus" #define TR_RENAVIG "Drehgeb. Navig." -#define TR_THROTTLEREVERSE TR("Gas invers", "Vollgas hinten?") //Änderung wg TH9x, Taranis +#define TR_THROTTLE_LABEL "Gas" +#define TR_THROTTLEREVERSE TR("Gas invers", INDENT "Vollgas hinten?") //Änderung wg TH9x, Taranis #define TR_MINUTEBEEP TR(INDENT"Minute",INDENT"Jede Minute") #define TR_BEEPCOUNTDOWN INDENT"Countdown" #define TR_PERSISTENT TR(INDENT"M-Zeit",INDENT"Modell Zeit") -#define TR_BACKLIGHT_LABEL "LCD Licht an" +#define TR_BACKLIGHT_LABEL "----LCD Licht----" #define TR_BLDELAY INDENT"Dauer" #define TR_BLONBRIGHTNESS INDENT"An Helligkeit" -#define TR_THROTTLEWARNING "Gas Alarm" -#define TR_SWITCHWARNING TR("Sch. Alarm","Schalter Alarm") -#define TR_POTWARNING TR("Pot Warn.","Poti Warnung") -#define TR_SWITCHWARNING TR("Sch. Alarm","Schalter Alarm") -#define TR_POTWARNING TR("Pot Warn.","Pot Warning") +#define TR_BLOFFBRIGHTNESS INDENT"Aus Helligkeit" +#define TR_SPLASHSCREEN "Startbild" +#define TR_THROTTLEWARNING TR("Gas Alarm", INDENT "Gas Alarm") +#define TR_SWITCHWARNING TR("Sch. Alarm", INDENT "Schalter Alarm") +#define TR_POTWARNING TR("Pot Warn.", INDENT "Poti Warnung") #define TR_TIMEZONE TR("Zeitzone","GPS Zeit Zone") #define TR_RXCHANNELORD TR("Kanalanordnung","Kanalvoreinstellung") -#define TR_SLAVE "Sch\205ler PPM1-8 als Ausgang" +#define TR_SLAVE "Schüler PPM1-8 als Ausgang" #define TR_MODESRC " Modus\002% Quelle" #define TR_MULTIPLIER "Multiplikator" #define TR_CAL "Kal." @@ -548,7 +554,7 @@ #define TR_FREESTACKMINB "Free Stack\037\124b" #endif -#define TR_MENUTORESET CENTER TR_ENTER" f\205r Reset" +#define TR_MENUTORESET CENTER TR_ENTER" für Reset" #define TR_PPM "PPM" #define TR_CH "CH" #define TR_MODEL "MODELL" @@ -556,33 +562,33 @@ #define TR_MIX "MIX" #define TR_EEPROMLOWMEM "EEPROM voll" #define TR_ALERT "WARNUNG" -#define TR_PRESSANYKEYTOSKIP "Taste dr\205cken" +#define TR_PRESSANYKEYTOSKIP "Taste drücken" #define TR_THROTTLENOTIDLE "Gas nicht Null!" #define TR_ALARMSDISABLED "Alarme ausgeschaltet" -#define TR_PRESSANYKEY TR("Taste dr\205cken",CENTER"Taste dr\205cken") -#define TR_BADEEPROMDATA "EEPROM ung\205ltig" +#define TR_PRESSANYKEY TR("Taste drücken",CENTER"Taste drücken") +#define TR_BADEEPROMDATA "EEPROM ungültig" #define TR_EEPROMFORMATTING "EEPROM Initialisieren" -#define TR_EEPROMOVERFLOW "EEPROM \204berlauf" +#define TR_EEPROMOVERFLOW "EEPROM Überlauf" #define TR_MENURADIOSETUP TR("SENDER EINST.","SENDER GRUNGEINSTELLUNGEN") #define TR_MENUDATEANDTIME "DATUM UND ZEIT" -#define TR_MENUTRAINER TR("Lehr./Sch\204l.","LEHRER/SCH\204LER") +#define TR_MENUTRAINER TR("Lehr./Schül.","LEHRER/SCHÜLER") #define TR_MENUVERSION "VERSION" #define TR_MENUDIAG TR("Schalt.","Schalter Test") #define TR_MENUANA "Analog Test" #define TR_MENUCALIBRATION TR("KALIB. ANALOG","KALIBRIERUNG STICKS+POTIS") #define TR_TRIMS2OFFSETS "\006Trims => Offset" -#define TR_MENUMODELSEL TR("MODELLE","MODELL W\200HLEN") +#define TR_MENUMODELSEL TR("MODELLE","MODELL WÄHLEN") #define TR_MENUSETUP TR("KONF.","MODELL EINSTELLUNGEN") #define TR_MENUFLIGHTPHASE "FLUGPHASE" #define TR_MENUFLIGHTPHASES "FLUGPHASEN" #define TR_MENUHELISETUP "HUBSCHRAUBER" #if defined(PCBTARANIS) - #define TR_MENUINPUTS "EING\200NGE" - #define TR_MENULIMITS "AUSG\200NGE" -#elif defined(PPM_CENTER_ADJUSTABLE) || defined(PPM_LIMITS_SYMETRICAL) // The right menu titles for the gurus ... #define TR_MENUDREXPO "KN\204PPEL" - #define TR_MENUINPUTS "EING\200NGE" - #define TR_MENULIMITS "AUSG\200NGE" + #define TR_MENUINPUTS "INPUTS" + #define TR_MENULIMITS "AUSGÄNGE" +#elif defined(PPM_CENTER_ADJUSTABLE) || defined(PPM_LIMITS_SYMETRICAL) // The right menu titles for the gurus ... #define TR_MENUDREXPO "KNÜPPEL" + #define TR_MENUINPUTS "INPUTS" + #define TR_MENULIMITS "AUSGÄNGE" #else #define TR_MENUINPUTS TR("DR/EXPO","DUALRATE/EXPO") #define TR_MENULIMITS TR("GRENZEN","SERVO WEG") @@ -590,32 +596,32 @@ #define TR_MENUCURVES "KURVEN" #define TR_MENUCURVE "KURVE" -#define TR_MENULOGICALSWITCH "PROG.SCHALTER" -#define TR_MENULOGICALSWITCHES TR_MENULOGICALSWITCH +#define TR_MENULOGICALSWITCH "LOGIK SCHALTER" +#define TR_MENULOGICALSWITCHES "LOGIK SCHALTER" #define TR_MENUCUSTOMFUNC "SPEZ. FUNKTIONEN" #define TR_MENUTELEMETRY "TELEMETRIE" #define TR_MENUTEMPLATES "VORLAGEN" #define TR_MENUSTAT "STAT" #define TR_MENUDEBUG "DEBUG" -#define TR_RXNUM TR("Rx Nummer",INDENT"Empf\201nger Nr.") +#define TR_RXNUM TR("Rx Nummer",INDENT"Empfänger Nr.") #define TR_SYNCMENU "Sync [MENU]" -#define TR_LIMIT INDENT"Limite" +#define TR_LIMIT INDENT"Grenzen" #define TR_MINRSSI "Min. RSSI" #define TR_LATITUDE "Breite:" -#define TR_LONGITUDE "L\201nge:" +#define TR_LONGITUDE "Länge:" #define TR_GPSCOORD TR("Gps Koord.","GPS Koordinaten Format") -#define TR_VARIO TR("Vario","Variometer") +#define TR_VARIO TR("Vario","----Variometer----") #define TR_SHUTDOWN "Herunterfahren" #define TR_BATT_CALIB "Akku. Kalib." #define TR_CURRENT_CALIB "Stromkalib." #define TR_VOLTAGE INDENT"Spann." #define TR_CURRENT INDENT"Strom" -#define TR_SELECT_MODEL "Modell W\201hlen" +#define TR_SELECT_MODEL "Modell Wählen" #define TR_CREATE_MODEL "Neues Modell" #define TR_COPY_MODEL "Kopiere Modell" #define TR_MOVE_MODEL "Verschiebe Modell" #define TR_BACKUP_MODEL "Modell Backup" -#define TR_DELETE_MODEL "Modell L\203schen" // TODO merged into DELETEMODEL? +#define TR_DELETE_MODEL "Modell Löschen" // TODO merged into DELETEMODEL? #define TR_RESTORE_MODEL "Modell Restore" #define TR_SDCARD_ERROR "SDcard Fehler" #define TR_NO_SDCARD "Keine SDcard" @@ -625,8 +631,8 @@ #define TR_THROTTLEWARN "GAS" #define TR_ALARMSWARN "ALARM" #define TR_SWITCHWARN "SCHALTER" -#define TR_INVERT_THR TR("Gas umkehren?","Vollgas hinten?") //\200nderung wg Th9x -#define TR_SPEAKER_VOLUME INDENT "Lautst\201rke" +#define TR_INVERT_THR TR("Gas umkehren?","Vollgas hinten?") //Änderung wg Th9x +#define TR_SPEAKER_VOLUME INDENT "Lautstärke" #define TR_LCD "Bildschirm" #define TR_BRIGHTNESS INDENT "Helligkeit" #define TR_CPU_TEMP "CPU Temp.\016>" @@ -635,27 +641,27 @@ #define TR_COPROC "CoProz." #define TR_COPROC_TEMP "MB Temp. \016>" #define TR_CAPAWARNING INDENT "Kapaz. niedrig" -#define TR_TEMPWARNING INDENT "Temperatur gr\203er" +#define TR_TEMPWARNING INDENT "Temperatur größer" #define TR_FUNC "Funktion" #define TR_V1 "V1" #define TR_V2 "V2" #define TR_DURATION "Dauer" -#define TR_DELAY "Verz\203g." +#define TR_DELAY "Verzög." #define TR_SD_CARD "SD Karte" #define TR_SDHC_CARD "SD-HC Karte" -#define TR_NO_SOUNDS_ON_SD "Keine T\203ne auf SD" +#define TR_NO_SOUNDS_ON_SD "Keine Töne auf SD" #define TR_NO_MODELS_ON_SD "Keine Modelle auf SD" #define TR_NO_BITMAPS_ON_SD "Keine Bitmaps auf SD" #define TR_PLAY_FILE "Spielen" -#define TR_DELETE_FILE "L\203schen" +#define TR_DELETE_FILE "Löschen" #define TR_COPY_FILE "Kopieren" #define TR_RENAME_FILE "Umbenennen" #define TR_ASSIGN_BITMAP "Assign Bitmap" -#define TR_REMOVED " gel\203scht" +#define TR_REMOVED " gelöscht" #define TR_SD_INFO "Information" #define TR_SD_FORMAT "Formattieren" -#define TR_NA "N/V" //NV=Nicht Verf\205gbar Kurz-Meldung -#define TR_HARDWARE "Hardware" +#define TR_NA "N/V" //NV=Nicht Verfügbar Kurz-Meldung +#define TR_HARDWARE "Hardware einstellen" #define TR_FORMATTING "Formattierung..." #define TR_TEMP_CALIB "Temp. Kalib." #define TR_TIME "Uhrzeit:" @@ -664,7 +670,7 @@ #define TR_SD_TYPE "Typ:" #define TR_SD_SPEED "Geschw:" #define TR_SD_SECTORS "Sektoren:" -#define TR_SD_SIZE "Gr\203\206e:" +#define TR_SD_SIZE "Größe:" #define TR_TYPE "Typ" #define TR_GLOBAL_VARS "Globale Variablen" #define TR_GLOBAL_V "GLOBAL V." @@ -708,15 +714,14 @@ #define TR_ANTENNAPROBLEM CENTER "TX Antennen Problem!" #define TR_MODELIDUSED TR("ID schon benutzt","Modell ID schon benutzt") #define TR_MODULE INDENT "Modul-Typ" -#define TR_CHANNELRANGE INDENT "Ausgangs Kan\201le" +#define TR_CHANNELRANGE INDENT "Ausgangs Kanäle" #define TR_LOWALARM INDENT "Low Alarm" #define TR_CRITICALALARM INDENT "Kritisch Alarm" -#define TR_PERSISTENT_MAH INDENT "Store mAh" -#define TR_CHECKLIST "Display Checklist" +#define TR_PERSISTENT_MAH INDENT "Speichern mAh" +#define TR_PREFLIGHT "Preflight Checks" +#define TR_CHECKLIST INDENT "Display Checklist" #define TR_FAS_OFFSET TR(INDENT "FAS Ofs", INDENT "FAS Offset") -#define TR_UART3MODE "Serial port" -#define TR_POT1TYPE "S1 Type" -#define TR_POT2TYPE "S2 Type" +#define TR_UART3MODE "Serial Port" #if defined(MAVLINK) #define TR_MAVLINK_RC_RSSI_SCALE_LABEL "Max RSSI" @@ -744,8 +749,8 @@ #define TR_MAVLINK_LON "LON" #endif -// Taranis column headers -#define TR_PHASES_HEADERS { " Name ", " Schalter ", " Trimmung ", " Fade In ", " Fade Out " } +// Taranis Info Zeile Anzeigen +#define TR_PHASES_HEADERS { " Name ", " Schalter ", " Seite Trim ", " Höhe Trim ", " Gas Trim ", " Quer Trim ", " Fade In ", " Fade Out " } #define TR_LIMITS_HEADERS { " Name ", " Subtrim ", " Min ", " Max ", " Richtung ", " Kurve ", " PPM Mitte ", " Subtrim Mode " } #define TR_CSW_HEADERS { " Funktion ", " Var1 ", " Var2 ", " Var2 ", " UND Schalter ", " Dauer ", " Delay " } @@ -787,7 +792,7 @@ #define TR_ABOUT_HARDWARE_3 "Firmware Vertrieb" #else #define TR_ABOUT_HARDWARE_1 "Brent Nelson" - #define TR_ABOUT_HARDWARE_2 "Sky9x Design/produktion" + #define TR_ABOUT_HARDWARE_2 "Sky9x Design/Produktion" #define TR_ABOUT_HARDWARE_3 "" #endif @@ -796,18 +801,18 @@ #define TR_ABOUT_PARENTS_3 "ER9X (Erez Raviv)" #define TR_ABOUT_PARENTS_4 "TH9X (Thomas Husterer)" -#define TR_CHR_SHORT 's' //Taste short -#define TR_CHR_LONG 'l' //Taste long -#define TR_CHR_TOGGLE 't' //Taste als togglefunktion = Ein Aus Ein -#define TR_CHR_HOUR 'h' //Stunden -#define TR_CHR_INPUT 'I' // Values between A-I will work +#define TR_CHR_SHORT 's' // Taste short +#define TR_CHR_LONG 'l' // Taste long +#define TR_CHR_TOGGLE 't' // Taste als togglefunktion = Ein Aus Ein +#define TR_CHR_HOUR 'h' // Stunden +#define TR_CHR_INPUT 'I' // Values between A-I will work -#define TR_BEEP_VOLUME "Beep Lautst" -#define TR_WAV_VOLUME "Wav Lautst" +#define TR_BEEP_VOLUME "Beep Lautst" +#define TR_WAV_VOLUME "Wav Lautst" #define TR_VARIO_VOLUME "Vario Lautst" -#define TR_BG_VOLUME "Bg Lautst" +#define TR_BG_VOLUME "Bg Lautst" -#define TR_TOP_BAR "Top Bar" -#define TR_ALTITUDE INDENT "Altitude" -#define TR_MODS_FORBIDDEN "Modifications forbidden!" -#define TR_UNLOCKED "Unlocked" +#define TR_TOP_BAR "Info Zeile" +#define TR_ALTITUDE INDENT "Höhe" +#define TR_MODS_FORBIDDEN "Veränderungen verboten!" +#define TR_UNLOCKED "Entsperrt" diff --git a/radio/src/translations/en.h.txt b/radio/src/translations/en.h.txt index a7c5f9938..48f356d62 100644 --- a/radio/src/translations/en.h.txt +++ b/radio/src/translations/en.h.txt @@ -72,7 +72,7 @@ #define TR_UART3MODES "OFF\0 ""S-Port Mirror\0 ""Debug\0 " #define LEN_POTTYPES "\017" -#define TR_POTTYPES "Pot\0 ""Multipos Switch" +#define TR_POTTYPES "None\0 ""Pot\0 ""Multipos Switch" #define LEN_DATETIME "\005" #define TR_DATETIME "DATE:""TIME:" @@ -168,7 +168,7 @@ #endif #if defined(CPUARM) - #define TR_CSWEQUAL "a=x\0 " + #define TR_CSWEQUAL "a=x\0 " #else #define TR_CSWEQUAL #endif @@ -283,20 +283,25 @@ #define TR_VTELEMCHNS "---\0""Batt""Tmr1""Tmr2" TR_SWR "Tx\0 ""Rx\0 " TR_RX_BATT "A1\0 ""A2\0 " TR_A3_A4 "Alt\0""Rpm\0""Fuel""T1\0 ""T2\0 ""Spd\0""Dist""GAlt""Cell""Cels""Vfas""Curr""Cnsp""Powr""AccX""AccY""AccZ""Hdg\0""VSpd""ASpd""dTE\0" TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE "A1-\0""A2-\0" TR_A3_A4_MIN "Alt-""Alt+""Rpm+""T1+\0""T2+\0""Spd+""Dst+""Cel-""Cls-""Vfs-""Cur+""Pwr+" TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE TR_TELEM_RESERVE "Acc\0""Time" +#define LENGTH_UNIT_IMP "ft\0" +#define SPEED_UNIT_IMP "mph" +#define LENGTH_UNIT_METR "m\0 " +#define SPEED_UNIT_METR "kmh" + #if defined(CPUARM) #define LEN_VUNITSSYSTEM TR("\006", "\010") #define TR_VUNITSSYSTEM TR("Metric""Imper.", "Metric\0 ""Imperial") - #define LEN_VTELEMUNIT_NORM "\003" - #define TR_VTELEMUNIT_NORM "v\0 ""A\0 ""m/s""-\0 ""kmh""m\0 ""@\0 ""%\0 ""mA\0""mAh""W\0 " + #define LEN_VTELEMUNIT_METR "\003" + #define TR_VTELEMUNIT_METR "v\0 ""A\0 ""m/s""-\0 " SPEED_UNIT_METR LENGTH_UNIT_METR "@\0 ""%\0 ""mA\0""mAh""W\0 " #define LEN_VTELEMUNIT_IMP "\003" - #define TR_VTELEMUNIT_IMP "v\0 ""A\0 ""m/s""-\0 ""kts""ft\0""@\0 ""%\0 ""mA\0""mAh""W\0 " + #define TR_VTELEMUNIT_IMP "v\0 ""A\0 ""m/s""-\0 " SPEED_UNIT_IMP LENGTH_UNIT_IMP "@\0 ""%\0 ""mA\0""mAh""W\0 " #else #if defined(IMPERIAL_UNITS) - #define LENGTH_UNIT "ft\0" - #define SPEED_UNIT "kts" + #define LENGTH_UNIT LENGTH_UNIT_IMP + #define SPEED_UNIT SPEED_UNIT_IMP #else - #define LENGTH_UNIT "m\0 " - #define SPEED_UNIT "kmh" + #define LENGTH_UNIT LENGTH_UNIT_METR + #define SPEED_UNIT SPEED_UNIT_METR #endif #define LEN_VTELEMUNIT "\003" #define TR_VTELEMUNIT "v\0 ""A\0 ""m/s""-\0 " SPEED_UNIT LENGTH_UNIT "@\0 ""%\0 ""mA\0""mAh""W\0 " @@ -328,7 +333,7 @@ #define TR_VSCREEN "Nums""Bars" #define LEN_GPSFORMAT "\004" -#define TR_GPSFORMAT "HMS NMEA" +#define TR_GPSFORMAT "HMS ""NMEA" #define LEN2_VTEMPLATES 13 #define LEN_VTEMPLATES "\015" @@ -347,7 +352,7 @@ #define LEN_VSRCRAW "\004" #if defined(PCBTARANIS) - #define TR_POTS_VSRCRAW "S1\0 ""S2\0 ""LS\0 ""RS\0 " + #define TR_POTS_VSRCRAW "S1\0 ""S2\0 ""S3\0 ""LS\0 ""RS\0 " #define TR_SW_VSRCRAW "SA\0 ""SB\0 ""SC\0 ""SD\0 ""SE\0 ""SF\0 ""SG\0 ""SH\0 " #elif defined(EXTRA_3POS) #define TR_POTS_VSRCRAW "P1\0 ""P2\0 " @@ -381,7 +386,7 @@ #endif #if defined(PCBTARANIS) - #define TR_6POS_POTS "P11""P12""P13""P14""P15""P16""P21""P22""P23""P24""P25""P26" + #define TR_6POS_POTS "P11""P12""P13""P14""P15""P16""P21""P22""P23""P24""P25""P26""P31""P32""P33""P34""P35""P36" #define TR_VSWITCHES "SA\300""SA-""SA\301""SB\300""SB-""SB\301""SC\300""SC-""SC\301""SD\300""SD-""SD\301""SE\300""SE-""SE\301""SF\300""SF\301""SG\300""SG-""SG\301""SH\300""SH\301" TR_6POS_POTS TR_TRIMS_SWITCHES TR_ROTENC_SWITCHES TR_LOGICALSW #elif defined(CPUARM) #define TR_VSWITCHES TR_9X_3POS_SWITCHES "THR""RUD""ELE""AIL""GEA""TRN" TR_TRIMS_SWITCHES TR_ROTENC_SWITCHES TR_LOGICALSW @@ -451,7 +456,7 @@ #define TR_ETRIMS TR("E.Trims", "Extended Trims") #define TR_TRIMINC "Trim Step" #define TR_TTRACE TR("T-Source", INDENT "Source") -#define TR_TTRIM TR("T-IdleTrim", INDENT "Idle Trim") +#define TR_TTRIM TR("T-Trim", INDENT "Idle Trim") #define TR_BEEPCTR TR("Ctr Beep", "Center Beep") #define TR_PROTO TR(INDENT "Proto", INDENT "Protocol") #define TR_PPMFRAME TR("PPM frame", INDENT "PPM frame") @@ -469,17 +474,17 @@ #define TR_ELEDIRECTION TR("ELE Direction","Long. cyc. direction") #define TR_AILDIRECTION TR("AIL Direction","Lateral cyc. direction") #define TR_COLDIRECTION TR("PIT Direction","Coll. pitch direction") -#define TR_MODE INDENT"Mode" +#define TR_MODE INDENT "Mode" #define TR_NOFREEEXPO "No free expo!" #define TR_NOFREEMIXER "No free mixer!" #define TR_INSERTMIX "INSERT MIX " #define TR_EDITMIX "EDIT MIX " -#define TR_SOURCE INDENT"Source" +#define TR_SOURCE INDENT "Source" #define TR_WEIGHT "Weight" #define TR_EXPO TR("Expo","Exponential") #define TR_SIDE "Side" #define TR_DIFFERENTIAL "Differ" -#define TR_OFFSET INDENT"Offset" +#define TR_OFFSET INDENT "Offset" #define TR_TRIM "Trim" #define TR_DREX "DRex" #define TR_CURVE "Curve" @@ -495,37 +500,37 @@ #define TR_CV "CV" #define TR_GV "GV" #define TR_ACHANNEL "A\004channel" -#define TR_RANGE INDENT"Range" +#define TR_RANGE INDENT "Range" #define TR_BAR "Bar" -#define TR_ALARM INDENT"Alarm" +#define TR_ALARM INDENT "Alarm" #define TR_USRDATA "UsrData" -#define TR_BLADES INDENT"Blades" +#define TR_BLADES INDENT "Blades" #define TR_SCREEN "Screen " #define TR_SOUND_LABEL "Sound" -#define TR_LENGTH INDENT"Length" -#define TR_SPKRPITCH INDENT"Pitch" +#define TR_LENGTH INDENT "Length" +#define TR_SPKRPITCH INDENT "Pitch" #define TR_HAPTIC_LABEL "Haptic" -#define TR_HAPTICSTRENGTH INDENT"Strength" +#define TR_HAPTICSTRENGTH INDENT "Strength" #define TR_CONTRAST "Contrast" #define TR_ALARMS_LABEL "Alarms" #define TR_BATTERY_RANGE TR("Battery range","Battery meter range") -#define TR_BATTERYWARNING INDENT"Battery Low" -#define TR_INACTIVITYALARM INDENT"Inactivity" -#define TR_MEMORYWARNING INDENT"Memory Low" -#define TR_ALARMWARNING INDENT"Sound Off" +#define TR_BATTERYWARNING INDENT "Battery Low" +#define TR_INACTIVITYALARM INDENT "Inactivity" +#define TR_MEMORYWARNING INDENT "Memory Low" +#define TR_ALARMWARNING INDENT "Sound Off" #define TR_RENAVIG "RotEnc Navig" #define TR_THROTTLE_LABEL "Throttle" #define TR_THROTTLEREVERSE TR("T-Reverse", INDENT "Reverse") -#define TR_MINUTEBEEP TR(INDENT"Minute",INDENT"Minute call") -#define TR_BEEPCOUNTDOWN INDENT"Countdown" -#define TR_PERSISTENT TR(INDENT"Persist.",INDENT"Persistent") +#define TR_MINUTEBEEP TR(INDENT "Minute",INDENT "Minute call") +#define TR_BEEPCOUNTDOWN INDENT "Countdown" +#define TR_PERSISTENT TR(INDENT "Persist.",INDENT "Persistent") #define TR_BACKLIGHT_LABEL "Backlight" -#define TR_BLDELAY INDENT"Duration" -#define TR_BLONBRIGHTNESS INDENT"ON Brightness" -#define TR_BLOFFBRIGHTNESS INDENT"OFF Brightness" +#define TR_BLDELAY INDENT "Duration" +#define TR_BLONBRIGHTNESS INDENT "ON Brightness" +#define TR_BLOFFBRIGHTNESS INDENT "OFF Brightness" #define TR_SPLASHSCREEN "Splash screen" #define TR_THROTTLEWARNING TR("T-Warning", INDENT "Throttle State") -#define TR_SWITCHWARNING TR("S-Warning", INDENT "Switch Positions") +#define TR_SWITCHWARNING TR("S-Warning", INDENT "Switch Position") #define TR_POTWARNING TR("Pot Warn.", INDENT "Pot Setup") #define TR_TIMEZONE TR("Time Zone","GPS Time zone") #define TR_RXCHANNELORD TR("Rx Channel Ord","Default channel order") @@ -606,9 +611,9 @@ #define TR_MENUTEMPLATES "TEMPLATES" #define TR_MENUSTAT "STATS" #define TR_MENUDEBUG "DEBUG" -#define TR_RXNUM TR("RxNum", INDENT"Receiver No.") +#define TR_RXNUM TR("RxNum", INDENT "Receiver No.") #define TR_SYNCMENU "[Sync]" -#define TR_LIMIT INDENT"Limit" +#define TR_LIMIT INDENT "Limit" #define TR_MINRSSI "Min Rssi" #define TR_LATITUDE "Latitude" #define TR_LONGITUDE "Longitude" @@ -617,8 +622,8 @@ #define TR_SHUTDOWN "SHUTTING DOWN" #define TR_BATT_CALIB "Battery Calib" #define TR_CURRENT_CALIB "Current Calib" -#define TR_VOLTAGE INDENT"Voltage" -#define TR_CURRENT INDENT"Current" +#define TR_VOLTAGE INDENT "Voltage" +#define TR_CURRENT INDENT "Current" #define TR_SELECT_MODEL "Select Model" #define TR_CREATE_MODEL "Create Model" #define TR_COPY_MODEL "Copy Model" @@ -706,8 +711,8 @@ #define TR_ABOUT_US "About" #define TR_AND_SWITCH "AND Switch" #define TR_CF "CF" -#define TR_SPEAKER INDENT"Speaker" -#define TR_BUZZER INDENT"Buzzer" +#define TR_SPEAKER INDENT "Speaker" +#define TR_BUZZER INDENT "Buzzer" #define TR_BYTES "bytes" #define TR_MODULE_BIND "[Bind]" #define TR_MODULE_RANGE "[Range]" @@ -725,8 +730,6 @@ #define TR_CHECKLIST INDENT "Display Checklist" #define TR_FAS_OFFSET TR(INDENT "FAS Ofs", INDENT "FAS Offset") #define TR_UART3MODE "Serial port" -#define TR_POT1TYPE "S1 Type" -#define TR_POT2TYPE "S2 Type" #if defined(MAVLINK) #define TR_MAVLINK_RC_RSSI_SCALE_LABEL "Max RSSI" @@ -806,11 +809,11 @@ #define TR_ABOUT_PARENTS_3 "ER9X (Erez Raviv)" #define TR_ABOUT_PARENTS_4 "TH9X (Thomas Husterer)" -#define TR_CHR_SHORT 's' -#define TR_CHR_LONG 'l' -#define TR_CHR_TOGGLE 't' -#define TR_CHR_HOUR 'h' -#define TR_CHR_INPUT 'I' // Values between A-I will work +#define TR_CHR_SHORT 's' +#define TR_CHR_LONG 'l' +#define TR_CHR_TOGGLE 't' +#define TR_CHR_HOUR 'h' +#define TR_CHR_INPUT 'I' // Values between A-I will work #define TR_BEEP_VOLUME "Beep Volume" #define TR_WAV_VOLUME "Wav Volume" diff --git a/radio/src/translations/fr.h.txt b/radio/src/translations/fr.h.txt index c26d95018..828b25b79 100644 --- a/radio/src/translations/fr.h.txt +++ b/radio/src/translations/fr.h.txt @@ -2,10 +2,6 @@ * Authors (alphabetical order) * - Andre Bernet * - Bertrand Songis - * - Bernet Andre - * - Kjell Kernen - * - Martin Hotar - * - Romolo Manfredini * * opentx is based on code named * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, @@ -40,90 +36,90 @@ * \001 to \035 -extended spacing (value * FW/2) * \0 -ends actual string */ - + // NON ZERO TERMINATED STRINGS -#define LEN_OFFON "\003" -#define TR_OFFON "OFF""ON\0" +#define LEN_OFFON "\003" +#define TR_OFFON "OFF""ON\0" -#define LEN_MMMINV "\003" -#define TR_MMMINV "---""INV" +#define LEN_MMMINV "\003" +#define TR_MMMINV "---""INV" -#define LEN_NCHANNELS "\004" -#define TR_NCHANNELS "\0014CH\0016CH\0018CH10CH12CH14CH16CH" +#define LEN_NCHANNELS "\004" +#define TR_NCHANNELS "\0014CH\0016CH\0018CH10CH12CH14CH16CH" -#define LEN_VBEEPMODE "\005" -#define TR_VBEEPMODE "Aucun""Alarm""NoKey""Tout\0" +#define LEN_VBEEPMODE "\005" +#define TR_VBEEPMODE "Aucun""Alarm""NoKey""Tout\0" -#define LEN_VBEEPLEN "\005" -#define TR_VBEEPLEN "0====""=0===""==0==""===0=""====0" +#define LEN_VBEEPLEN "\005" +#define TR_VBEEPLEN "0====""=0===""==0==""===0=""====0" -#define LEN_VRENAVIG "\003" -#define TR_VRENAVIG "NonREaREb" +#define LEN_VRENAVIG "\003" +#define TR_VRENAVIG "NonREaREb" -#define LEN_VBLMODE TR("\004","\011") -#define TR_VBLMODE TR("OFF\0""Btns""Ctrl""Tous""ON\0","OFF\0 ""Touches\0 ""Controles""Tous\0 ""ON\0 ") +#define LEN_VBLMODE TR("\004","\011") +#define TR_VBLMODE TR("OFF\0""Btns""Ctrl""Tous""ON\0","OFF\0 ""Touches\0 ""Controles""Tous\0 ""ON\0 ") -#define LEN_TRNMODE "\003" -#define TR_TRNMODE "OFF"" +="" :=" +#define LEN_TRNMODE "\003" +#define TR_TRNMODE "OFF"" +="" :=" -#define LEN_TRNCHN "\003" -#define TR_TRNCHN "CH1CH2CH3CH4" +#define LEN_TRNCHN "\003" +#define TR_TRNCHN "CH1CH2CH3CH4" -#define LEN_UART3MODES "\017" -#define TR_UART3MODES "OFF\0 ""Recopie S-Port\0""Debug\0 " +#define LEN_UART3MODES "\017" +#define TR_UART3MODES "OFF\0 ""Recopie S-Port\0""Debug\0 " -#define LEN_POTTYPES "\017" -#define TR_POTTYPES "Potentiomètre\0 ""Inter multi-pos" +#define LEN_POTTYPES "\017" +#define TR_POTTYPES "Rien\0 ""Potentiomètre\0 ""Inter multi-pos" -#define LEN_DATETIME "\005" -#define TR_DATETIME "DATE:""HEURE" +#define LEN_DATETIME "\005" +#define TR_DATETIME "DATE:""HEURE" -#define LEN_VLCD "\006" -#define TR_VLCD "NormalOptrex" +#define LEN_VLCD "\006" +#define TR_VLCD "NormalOptrex" -#define LEN_COUNTRYCODES TR("\002", "\006") -#define TR_COUNTRYCODES TR("US""JP""EU", "USA\0 ""Japon\0""Europe") +#define LEN_COUNTRYCODES TR("\002", "\006") +#define TR_COUNTRYCODES TR("US""JP""EU", "USA\0 ""Japon\0""Europe") -#define LEN_VTRIMINC TR("\006","\013") -#define TR_VTRIMINC TR("Expo\0 ""ExFin\0""Fin\0 ""Moyen\0""Gros\0 ","Exponentiel""Extra Fin\0 ""Fin\0 ""Moyen\0 ""Grossier\0 ") +#define LEN_VTRIMINC TR("\006","\013") +#define TR_VTRIMINC TR("Expo\0 ""ExFin\0""Fin\0 ""Moyen\0""Gros\0 ","Exponentiel""Extra Fin\0 ""Fin\0 ""Moyen\0 ""Grossier\0 ") #define LEN_VBEEPCOUNTDOWN "\006" #define TR_VBEEPCOUNTDOWN "SilentBeeps\0Voice\0" -#define LEN_RETA123 "\001" +#define LEN_RETA123 "\001" #if defined(PCBGRUVIN9X) #if ROTARY_ENCODERS > 2 - #define TR_RETA123 "DPGA123abcd" + #define TR_RETA123 "DPGA123abcd" #else - #define TR_RETA123 "DPGA123ab" + #define TR_RETA123 "DPGA123ab" #endif #elif defined(PCBTARANIS) - #define TR_RETA123 "DPGA12LR" -#else - #define TR_RETA123 "DPGA123" + #define TR_RETA123 "DPGA12LR" +#else + #define TR_RETA123 "DPGA123" #endif -#define LEN_VPROTOS "\006" +#define LEN_VPROTOS "\006" #if defined(PXX) - #define TR_PXX "PXX\0 " + #define TR_PXX "PXX\0 " #elif defined(DSM2) || defined(IRPROTOS) - #define TR_PXX "[PXX]\0" + #define TR_PXX "[PXX]\0" #else #define TR_PXX #endif #if defined(DSM2) - #define TR_DSM2 "LP45\0 ""DSM2\0 ""DSMX\0 " + #define TR_DSM2 "LP45\0 ""DSM2\0 ""DSMX\0 " #elif defined(IRPROTOS) - #define TR_DSM2 "[LP45]""[DSM2]""[DSMX]" + #define TR_DSM2 "[LP45]""[DSM2]""[DSMX]" #else #define TR_DSM2 #endif #if defined(IRPROTOS) - #define TR_IRPROTOS "SILV TRAC09PICZ SWIFT\0" + #define TR_IRPROTOS "SILV TRAC09PICZ SWIFT\0" #else #define TR_IRPROTOS #endif @@ -131,25 +127,25 @@ #if defined(CPUARM) #define TR_XPPM #else - #define TR_XPPM "PPM16\0""PPMsim" + #define TR_XPPM "PPM16\0""PPMsim" #endif -#define TR_VPROTOS "PPM\0 " TR_XPPM TR_PXX TR_DSM2 TR_IRPROTOS +#define TR_VPROTOS "PPM\0 " TR_XPPM TR_PXX TR_DSM2 TR_IRPROTOS -#define LEN_POSNEG "\003" -#define TR_POSNEG "POS""NEG" +#define LEN_POSNEG "\003" +#define TR_POSNEG "POS""NEG" -#define LEN_VCURVEFUNC "\003" -#define TR_VCURVEFUNC "---""x>0""x<0""|x|""f>0""f<0""|f|" +#define LEN_VCURVEFUNC "\003" +#define TR_VCURVEFUNC "---""x>0""x<0""|x|""f>0""f<0""|f|" -#define LEN_VMLTPX TR("\010","\013") -#define TR_VMLTPX TR("Ajoute\0 ""Multipl.""Remplace","Additionner""Multiplier\0""Remplacer\0 ") +#define LEN_VMLTPX TR("\010", "\013") +#define TR_VMLTPX TR("Ajoute\0 ""Multipl.""Remplace","Additionner""Multiplier\0""Remplacer\0 ") -#define LEN_VMLTPX2 "\002" -#define TR_VMLTPX2 "+=""*="":=" +#define LEN_VMLTPX2 "\002" +#define TR_VMLTPX2 "+=""*="":=" -#define LEN_VMIXTRIMS "\003" -#define TR_VMIXTRIMS "OFF""ON\0""Dir""Prf""Gaz""Ail" +#define LEN_VMIXTRIMS "\003" +#define TR_VMIXTRIMS "OFF""ON\0""Dir""Prf""Gaz""Ail" #if defined(PCBTARANIS) #define TR_CSWTIMER "Tempo" @@ -169,86 +165,86 @@ #endif #if defined(CPUARM) - #define TR_CSWEQUAL "a=x\0 " + #define TR_CSWEQUAL "a=x\0 " #else #define TR_CSWEQUAL #endif -#define LEN_VCSWFUNC "\005" +#define LEN_VCSWFUNC "\005" #if defined(CPUARM) -#define TR_VCSWFUNC "---\0 " TR_CSWEQUAL "a{x\0 ""a>x\0 ""ax""|a|b\0 ""ax\0 ""ax""|a|b\0 ""ax\0 ""ax""|a|b\0 ""ax\0 ""ax""|a|b\0 ""a" +#define LEN_VALARMFN "\001" +#define TR_VALARMFN "<>" -#define LEN_VTELPROTO "\007" -#define TR_VTELPROTO "Aucun ""Hub\0 ""WSHHigh""Halcyon" +#define LEN_VTELPROTO "\007" +#define TR_VTELPROTO "Aucun ""Hub\0 ""WSHHigh""Halcyon" -#define LEN_VOLTSRC "\003" -#define TR_VOLTSRC "---""A1\0""A2\0""FAS""Cel" +#define LEN_VOLTSRC "\003" +#define TR_VOLTSRC "---""A1\0""A2\0""FAS""Cel" -#define LEN_VARIOSRC "\005" +#define LEN_VARIOSRC "\005" #if defined(FRSKY_SPORT) - #define TR_VARIOSRC "Vario""A1\0 ""A2\0" + #define TR_VARIOSRC "Vario""A1\0 ""A2\0""dTE\0" #else #define TR_VARIOSRC "Alti\0""Alti+""Vario""A1\0 ""A2\0" #endif -#define LEN_VSCREEN TR("\004","\007") -#define TR_VSCREEN TR("Val.""Bars","Valeurs""Barres\0") +#define LEN_VSCREEN TR("\004", "\007") +#define TR_VSCREEN TR("Val.""Bars", "Valeurs""Barres\0") -#define LEN_GPSFORMAT "\004" -#define TR_GPSFORMAT "DMS\0NMEA" +#define LEN_GPSFORMAT "\004" +#define TR_GPSFORMAT "DMS\0""NMEA" -#define LEN2_VTEMPLATES 15 -#define LEN_VTEMPLATES "\017" -#define TR_VTEMPLATES "Suppr Mixages\0 ""4 Voies simple\0""Coupure Gaz\0 ""Empennage V\0 ""Elevon\\Delta\0 ""eCCPM\0 ""Conf. Hélico\0 ""Test Servo\0 " +#define LEN2_VTEMPLATES 15 +#define LEN_VTEMPLATES "\017" +#define TR_VTEMPLATES "Suppr Mixages\0 ""4 Voies simple\0""Coupure Gaz\0 ""Empennage V\0 ""Elevon\\Delta\0 ""eCCPM\0 ""Conf. Hélico\0 ""Test Servo\0 " -#define LEN_VSWASHTYPE "\004" -#define TR_VSWASHTYPE "--- ""120 ""120X""140 ""90\0" +#define LEN_VSWASHTYPE "\004" +#define TR_VSWASHTYPE "--- ""120 ""120X""140 ""90\0" -#define LEN_VKEYS "\005" -#define TR_VKEYS TR("Menu\0""Exit\0""Bas\0 ""Haut\0""Droit""Gauch", "Menu\0""Exit\0""Enter""Page\0""Plus\0""Minus") +#define LEN_VKEYS "\005" +#define TR_VKEYS TR("Menu\0""Exit\0""Bas\0 ""Haut\0""Droit""Gauch", "Menu\0""Exit\0""Enter""Page\0""Plus\0""Minus") -#define LEN_VRENCODERS "\003" -#define TR_VRENCODERS "REa""REb" +#define LEN_VRENCODERS "\003" +#define TR_VRENCODERS "REa""REb" -#define LEN_VSWITCHES "\003" -#define LEN_VSRCRAW "\004" +#define LEN_VSWITCHES "\003" +#define LEN_VSRCRAW "\004" #if defined(PCBTARANIS) - #define TR_POTS_VSRCRAW "S1\0 ""S2\0 ""LS\0 ""RS\0 " + #define TR_POTS_VSRCRAW "S1\0 ""S2\0 ""S3\0 ""LS\0 ""RS\0 " #define TR_SW_VSRCRAW "SA\0 ""SB\0 ""SC\0 ""SD\0 ""SE\0 ""SF\0 ""SG\0 ""SH\0 " #elif defined(EXTRA_3POS) #define TR_POTS_VSRCRAW "P1\0 ""P2\0 " @@ -351,11 +360,11 @@ #endif #if defined(CPUARM) - #define TR_LOGICALSW "IL1""IL2""IL3""IL4""IL5""IL6""IL7""IL8""IL9""ILA""ILB""ILC""ILD""ILE""ILF""ILG""ILH""ILI""ILJ""ILK""ILL""ILM""ILN""ILO""ILP""ILQ""ILR""ILS""ILT""ILU""ILV""ILW" + #define TR_LOGICALSW "IL1""IL2""IL3""IL4""IL5""IL6""IL7""IL8""IL9""ILA""ILB""ILC""ILD""ILE""ILF""ILG""ILH""ILI""ILJ""ILK""ILL""ILM""ILN""ILO""ILP""ILQ""ILR""ILS""ILT""ILU""ILV""ILW" #elif defined(PCBGRUVIN9X) || defined(CPUM2561) || defined(CPUM128) - #define TR_LOGICALSW "IL1""IL2""IL3""IL4""IL5""IL6""IL7""IL8""IL9""ILA""ILB""ILC""ILD""ILE""ILF" + #define TR_LOGICALSW "IL1""IL2""IL3""IL4""IL5""IL6""IL7""IL8""IL9""ILA""ILB""ILC""ILD""ILE""ILF" #else - #define TR_LOGICALSW "IL1""IL2""IL3""IL4""IL5""IL6""IL7""IL8""IL9""ILA""ILB""ILC" + #define TR_LOGICALSW "IL1""IL2""IL3""IL4""IL5""IL6""IL7""IL8""IL9""ILA""ILB""ILC" #endif #define TR_TRIMS_SWITCHES "tDg""tDd""tPb""tPh""tGb""tGh""tAg""tAd" @@ -372,7 +381,7 @@ #endif #if defined(PCBTARANIS) - #define TR_6POS_POTS "P11""P12""P13""P14""P15""P16""P21""P22""P23""P24""P25""P26" + #define TR_6POS_POTS "P11""P12""P13""P14""P15""P16""P21""P22""P23""P24""P25""P26""P31""P32""P33""P34""P35""P36" #define TR_VSWITCHES "SA\300""SA-""SA\301""SB\300""SB-""SB\301""SC\300""SC-""SC\301""SD\300""SD-""SD\301""SE\300""SE-""SE\301""SF\300""SF\301""SG\300""SG-""SG\301""SH\300""SH\301" TR_6POS_POTS TR_TRIMS_SWITCHES TR_ROTENC_SWITCHES TR_LOGICALSW #elif defined(CPUARM) #define TR_VSWITCHES TR_9X_3POS_SWITCHES "THR""RUD""ELE""AIL""GEA""TRN" TR_TRIMS_SWITCHES TR_ROTENC_SWITCHES TR_LOGICALSW @@ -381,21 +390,21 @@ #endif #if defined(HELI) -#define TR_CYC_VSRCRAW "CYC1""CYC2""CYC3" + #define TR_CYC_VSRCRAW "CYC1""CYC2""CYC3" #else -#define TR_CYC_VSRCRAW "[C1]""[C2]""[C3]" + #define TR_CYC_VSRCRAW "[C1]""[C2]""[C3]" #endif -#define TR_VSRCRAW "---\0""Dir\0""Prf\0""Gaz\0""Ail\0" TR_POTS_VSRCRAW TR_ROTARY_ENCODERS "MAX\0" TR_CYC_VSRCRAW "TrmD" "TrmP" "TrmG" "TrmA" TR_SW_VSRCRAW +#define TR_VSRCRAW "---\0""Dir\0""Prf\0""Gaz\0""Ail\0" TR_POTS_VSRCRAW TR_ROTARY_ENCODERS "MAX\0" TR_CYC_VSRCRAW "TrmD" "TrmP" "TrmG" "TrmA" TR_SW_VSRCRAW -#define LEN_VTMRMODES "\003" -#define TR_VTMRMODES "OFF""ABS""GZs""GZ%""GZt" +#define LEN_VTMRMODES "\003" +#define TR_VTMRMODES "OFF""ABS""GZs""GZ%""GZt" #define LEN_VTRAINERMODES "\006" #define TR_VTRAINERMODES "Maître""Elève\0" -#define LEN_VFAILSAFE "\011" -#define TR_VFAILSAFE "Maintien\0""Prédéfini""Pas d'imp" +#define LEN_VFAILSAFE "\011" +#define TR_VFAILSAFE "Maintien\0""Prédéfini""Pas d'imp" #if defined(MAVLINK) #define LEN_MAVLINK_BAUDS "\006" @@ -438,43 +447,43 @@ #endif #define TR_BITMAP "Image du modèle" #define TR_TIMER "Chrono " -#define TR_ELIMITS TR("Limites ét","Limites étendues") -#define TR_ETRIMS TR("Trims ét.","Trims étendus") -#define TR_TRIMINC TR("Pas Trim","Pas des trims") +#define TR_ELIMITS TR("Limites ét", "Limites étendues") +#define TR_ETRIMS TR("Trims ét.", "Trims étendus") +#define TR_TRIMINC TR("Pas Trim", "Pas des trims") #define TR_TTRACE TR("Source gaz", INDENT "Source gaz") #define TR_TTRIM TR("Trim gaz", INDENT "Trim gaz") -#define TR_BEEPCTR TR("Bips centr","Bips centrage") -#define TR_PROTO TR(INDENT"Proto.",INDENT"Protocole") -#define TR_PPMFRAME INDENT"Trame PPM" +#define TR_BEEPCTR TR("Bips centr", "Bips centrage") +#define TR_PROTO TR(INDENT "Proto.", INDENT "Protocole") +#define TR_PPMFRAME INDENT "Trame PPM" #define TR_MS "ms" -#define TR_SWITCH TR("Inter","Interrupteur") +#define TR_SWITCH TR("Inter", "Interrupteur") #define TR_TRIMS "Trims" #define TR_FADEIN "Fondu ON" #define TR_FADEOUT "Fondu OFF" #define TR_DEFAULT "(défaut)" #define TR_CHECKTRIMS "\006Vérif\012Trims" #define OFS_CHECKTRIMS (9*FW) -#define TR_SWASHTYPE TR("Type de Plat.","Type de plateau") -#define TR_COLLECTIVE TR("Collectif","Voie du pas collectif") -#define TR_SWASHRING TR("Limite Cycl.","Limite du cyclique") -#define TR_ELEDIRECTION TR("Inv. longitud.","Inversion longitudinal") -#define TR_AILDIRECTION TR("Inv. latéral","Inversion latéral") -#define TR_COLDIRECTION TR("Inv. collectif","Inversion collectif") -#define TR_MODE INDENT"Mode" +#define TR_SWASHTYPE TR("Type de Plat.", "Type de plateau") +#define TR_COLLECTIVE TR("Collectif", "Voie du pas collectif") +#define TR_SWASHRING TR("Limite Cycl.", "Limite du cyclique") +#define TR_ELEDIRECTION TR("Inv. longitud.", "Inversion longitudinal") +#define TR_AILDIRECTION TR("Inv. latéral", "Inversion latéral") +#define TR_COLDIRECTION TR("Inv. collectif", "Inversion collectif") +#define TR_MODE INDENT "Mode" #define TR_NOFREEEXPO "Max expos atteint!" #define TR_NOFREEMIXER "Max mixages atteint!" #define TR_INSERTMIX "INSERER MIXAGE" #define TR_EDITMIX "EDITER MIXAGE" -#define TR_SOURCE INDENT"Source" +#define TR_SOURCE INDENT "Source" #define TR_WEIGHT "Ratio" -#define TR_EXPO TR("Expo","Exponentiel") +#define TR_EXPO TR("Expo", "Exponentiel") #define TR_SIDE "Coté" #define TR_DIFFERENTIAL "Différentiel" -#define TR_OFFSET INDENT"Décalage" +#define TR_OFFSET INDENT "Décalage" #define TR_TRIM "Trim" #define TR_DREX "DRex" #define TR_CURVE "Courbe" -#define TR_FLMODE TR("Phase","Phases") +#define TR_FLMODE TR("Phase", "Phases") #define TR_MIXWARNING "Alerte" #define TR_OFF "OFF" #define TR_MULTPX "Opération" @@ -486,34 +495,34 @@ #define TR_CV "CB" #define TR_GV "VG" #define TR_ACHANNEL "A" -#define TR_RANGE INDENT"Plage" +#define TR_RANGE INDENT "Plage" #define TR_BAR "Barre" -#define TR_ALARM INDENT"Alarme" +#define TR_ALARM INDENT "Alarme" #define TR_USRDATA "Données" -#define TR_BLADES INDENT"Pales" +#define TR_BLADES INDENT "Pales" #define TR_SCREEN "Ecran " #define TR_SOUND_LABEL "Son" -#define TR_LENGTH INDENT"Durée" -#define TR_SPKRPITCH INDENT"Tonalité" +#define TR_LENGTH INDENT "Durée" +#define TR_SPKRPITCH INDENT "Tonalité" #define TR_HAPTIC_LABEL "Vibreur" -#define TR_HAPTICSTRENGTH INDENT"Force" +#define TR_HAPTICSTRENGTH INDENT "Force" #define TR_CONTRAST "Contraste" #define TR_ALARMS_LABEL "Alarmes" #define TR_BATTERY_RANGE "Plage batterie" -#define TR_BATTERYWARNING TR(INDENT"Batterie",INDENT"Batterie faible") -#define TR_INACTIVITYALARM INDENT"Inactivité" -#define TR_MEMORYWARNING INDENT"Mémoire pleine" -#define TR_ALARMWARNING TR(INDENT"Silence",INDENT"Sons désactivés") +#define TR_BATTERYWARNING TR(INDENT "Batterie",INDENT "Batterie faible") +#define TR_INACTIVITYALARM INDENT "Inactivité" +#define TR_MEMORYWARNING INDENT "Mémoire pleine" +#define TR_ALARMWARNING TR(INDENT "Silence",INDENT "Sons désactivés") #define TR_RENAVIG "Navig EncRot" #define TR_THROTTLE_LABEL "Gaz" #define TR_THROTTLEREVERSE TR("Inv. gaz", INDENT "Inversion gaz") -#define TR_MINUTEBEEP TR(INDENT"Bip min.",INDENT"Annonces minutes") -#define TR_BEEPCOUNTDOWN TR(INDENT"Bip fin",INDENT"Compte à rebours") -#define TR_PERSISTENT TR(INDENT"Persist.",INDENT"Persistant") +#define TR_MINUTEBEEP TR(INDENT "Bip min.",INDENT "Annonces minutes") +#define TR_BEEPCOUNTDOWN TR(INDENT "Bip fin",INDENT "Compte à rebours") +#define TR_PERSISTENT TR(INDENT "Persist.",INDENT "Persistant") #define TR_BACKLIGHT_LABEL "Rétroéclairage" -#define TR_BLDELAY INDENT"Durée" -#define TR_BLONBRIGHTNESS INDENT"Luminosité ON" -#define TR_BLOFFBRIGHTNESS INDENT"Luminosité OFF" +#define TR_BLDELAY INDENT "Durée" +#define TR_BLONBRIGHTNESS INDENT "Luminosité ON" +#define TR_BLOFFBRIGHTNESS INDENT "Luminosité OFF" #define TR_SPLASHSCREEN "Logo d'accueil" #define TR_THROTTLEWARNING TR("Alerte gaz", INDENT "Alerte gaz") #define TR_SWITCHWARNING TR("Alerte int", INDENT "Alerte interrupt.") @@ -578,28 +587,28 @@ #define TR_MENUHELISETUP TR("CONF.HELI","CONFIGURATION HELICO") #if defined(PCBTARANIS) - #define TR_MENUINPUTS "ENTREES" - #define TR_MENULIMITS "SORTIES" + #define TR_MENUINPUTS "ENTREES" + #define TR_MENULIMITS "SORTIES" #elif defined(PPM_CENTER_ADJUSTABLE) || defined(PPM_LIMITS_SYMETRICAL) // The right menu titles for the gurus ... - #define TR_MENUINPUTS "MANCHES" - #define TR_MENULIMITS "SORTIES" + #define TR_MENUINPUTS "MANCHES" + #define TR_MENULIMITS "SORTIES" #else - #define TR_MENUINPUTS "DR/EXPO" - #define TR_MENULIMITS "LIMITES" + #define TR_MENUINPUTS "DR/EXPO" + #define TR_MENULIMITS "LIMITES" #endif #define TR_MENUCURVES "COURBES" #define TR_MENUCURVE "COURBE" -#define TR_MENULOGICALSWITCH "INTER LOG." -#define TR_MENULOGICALSWITCHES TR("INTERS LOG.","INTERS LOGIQUES") +#define TR_MENULOGICALSWITCH "INTER LOG." +#define TR_MENULOGICALSWITCHES TR("INTERS LOG.","INTERS LOGIQUES") #define TR_MENUCUSTOMFUNC TR("FONCTIONS SPEC.","FONCTIONS SPECIALES") #define TR_MENUTELEMETRY "TELEMESURE" #define TR_MENUTEMPLATES "GABARITS" #define TR_MENUSTAT TR("STATS","STATISTIQUES") #define TR_MENUDEBUG "DEBUG" -#define TR_RXNUM TR(INDENT"NumRx",INDENT"No. récepteur") +#define TR_RXNUM TR(INDENT "NumRx",INDENT "No. récepteur") #define TR_SYNCMENU "Sync [MENU]" -#define TR_LIMIT INDENT"Limite" +#define TR_LIMIT INDENT "Limite" #define TR_MINRSSI "RSSI Min." #define TR_LATITUDE "Latitude" #define TR_LONGITUDE "Longitude" @@ -608,8 +617,8 @@ #define TR_SHUTDOWN "ARRET EN COURS" #define TR_BATT_CALIB "Calib. Batterie" #define TR_CURRENT_CALIB "Calib. Courant" -#define TR_VOLTAGE INDENT"Tension" -#define TR_CURRENT INDENT"Courant" +#define TR_VOLTAGE INDENT "Tension" +#define TR_CURRENT INDENT "Courant" #define TR_SELECT_MODEL "Sélect. Modèle" #define TR_CREATE_MODEL "Créer Modèle" #define TR_COPY_MODEL "Copier Modèle" @@ -676,10 +685,10 @@ #define TR_CHANNELS_MONITOR "MONITEUR CANAUX" #define TR_INTERNALRF "HF interne" #define TR_EXTERNALRF "HF externe" -#define TR_FAILSAFE INDENT"Type failsafe" +#define TR_FAILSAFE INDENT "Type failsafe" #define TR_FAILSAFESET "REGLAGES FAILSAFE" #define TR_COUNTRYCODE "Zone géo." -#define TR_VOICELANG TR("Langue voix","Langue annonces vocales") +#define TR_VOICELANG TR("Langue voix", "Langue annonces vocales") #define TR_UNITSSYSTEM "Unités" #define TR_EDIT "Editer" #define TR_INSERT_BEFORE "Insérer avant" @@ -689,16 +698,16 @@ #define TR_PASTE "Coller" #define TR_DELETE "Effacer" #define TR_INSERT "Insérer" -#define TR_RESET_FLIGHT TR("Réinit. vol","Réinitialiser vol") -#define TR_RESET_TIMER1 TR("Réinit. Timer1","Réinitialiser Timer1") -#define TR_RESET_TIMER2 TR("Réinit. Timer2","Réinitialiser Timer2") -#define TR_RESET_TELEMETRY TR("Réinit. Télém.","Réinit. Télémesure") +#define TR_RESET_FLIGHT TR("Réinit. vol", "Réinitialiser vol") +#define TR_RESET_TIMER1 TR("Réinit. Timer1", "Réinitialiser Timer1") +#define TR_RESET_TIMER2 TR("Réinit. Timer2", "Réinitialiser Timer2") +#define TR_RESET_TELEMETRY TR("Réinit. Télém.", "Réinit. Télémesure") #define TR_STATISTICS "Statistiques" #define TR_ABOUT_US "A propos" #define TR_AND_SWITCH "ET suppl." #define TR_CF "FS" -#define TR_SPEAKER INDENT"Haut-p." -#define TR_BUZZER INDENT"Bipeur" +#define TR_SPEAKER INDENT "Haut-p." +#define TR_BUZZER INDENT "Bipeur" #define TR_BYTES "bytes" #define TR_MODULE_BIND "[Bind]" #define TR_MODULE_RANGE "[Port.]" @@ -706,18 +715,16 @@ #define TR_SET "[Déf.]" #define TR_TRAINER "Ecolage" #define TR_ANTENNAPROBLEM CENTER "Antenne radio défectueuse!" -#define TR_MODELIDUSED TR("ID déjà affecté","No de modèle déjà utilisé") +#define TR_MODELIDUSED TR("ID déjà affecté", "No de modèle déjà utilisé") #define TR_MODULE INDENT "Type de module" #define TR_CHANNELRANGE INDENT "Plage de canaux" #define TR_LOWALARM INDENT "Alarme basse" #define TR_CRITICALALARM INDENT "Alarme critique" -#define TR_PERSISTENT_MAH TR(INDENT "Enr. mAh",INDENT "Enregistrer mAh") +#define TR_PERSISTENT_MAH TR(INDENT "Enr. mAh", INDENT "Enregistrer mAh") #define TR_PREFLIGHT "Preflight Checks" #define TR_CHECKLIST INDENT "Afficher notes" #define TR_FAS_OFFSET TR(INDENT "Corr FAS", INDENT "Correction FAS") #define TR_UART3MODE "Port série" -#define TR_POT1TYPE "Type S1" -#define TR_POT2TYPE "Type S2" #if defined(MAVLINK) #define TR_MAVLINK_RC_RSSI_SCALE_LABEL "RSSI Max" @@ -751,17 +758,17 @@ #define TR_CSW_HEADERS { " Fonction ", " V1 ", " V2 ", " V2 ", " ET suppl. ", " Durée ", " Délai " } //Taranis About screen -#define TR_ABOUTUS TR(" A PROPOS ","A PROPOS") +#define TR_ABOUTUS TR(" A PROPOS ", "A PROPOS") -#define TR_ABOUT_OPENTX_1 TR("OpenTX\001est\001libre,\001non-","OpenTX est libre, non-") -#define TR_ABOUT_OPENTX_2 TR("commercial,\001et\001offert\001sans","commercial et n'offre aucune") -#define TR_ABOUT_OPENTX_3 TR("garantie.\001Il\001est\001développé","garantie. Il a été développé") -#define TR_ABOUT_OPENTX_4 TR("gratuitement.\001Donations","gratuitement. Vos donations") -#define TR_ABOUT_OPENTX_5 TR("bienvenues!","sont bienvenues!") +#define TR_ABOUT_OPENTX_1 TR("OpenTX\001est\001libre,\001non-", "OpenTX est libre, non-") +#define TR_ABOUT_OPENTX_2 TR("commercial,\001et\001offert\001sans", "commercial et n'offre aucune") +#define TR_ABOUT_OPENTX_3 TR("garantie.\001Il\001est\001développé", "garantie. Il a été développé") +#define TR_ABOUT_OPENTX_4 TR("gratuitement.\001Donations", "gratuitement. Vos donations") +#define TR_ABOUT_OPENTX_5 TR("bienvenues!", "sont bienvenues!") #define TR_ABOUT_BERTRAND_1 "Bertrand Songis" -#define TR_ABOUT_BERTRAND_2 TR("Auteur\001principal\001d'OpenTX","Auteur principal d'OpenTX") -#define TR_ABOUT_BERTRAND_3 TR("Codéveloppeur\001de\001C9X","Codéveloppeur de Companion9x") +#define TR_ABOUT_BERTRAND_2 TR("Auteur\001principal\001d'OpenTX", "Auteur principal d'OpenTX") +#define TR_ABOUT_BERTRAND_3 TR("Codéveloppeur\001de\001C9X", "Codéveloppeur de Companion9x") #define TR_ABOUT_MIKE_1 "Mike Blandford" #define TR_ABOUT_MIKE_2 "Maître du code et des" @@ -783,13 +790,13 @@ #define TR_ABOUT_MARTIN_2 "Design graphique" #if defined(PCBTARANIS) - #define TR_ABOUT_HARDWARE_1 "FrSky" - #define TR_ABOUT_HARDWARE_2 "Développeur/fabricant" - #define TR_ABOUT_HARDWARE_3 "du matériel" + #define TR_ABOUT_HARDWARE_1 "FrSky" + #define TR_ABOUT_HARDWARE_2 "Développeur/fabricant" + #define TR_ABOUT_HARDWARE_3 "du matériel" #else - #define TR_ABOUT_HARDWARE_1 "Brent Nelson" - #define TR_ABOUT_HARDWARE_2 "Développeur/fabricant" - #define TR_ABOUT_HARDWARE_3 "de la carte Sky9x" + #define TR_ABOUT_HARDWARE_1 "Brent Nelson" + #define TR_ABOUT_HARDWARE_2 "Développeur/fabricant" + #define TR_ABOUT_HARDWARE_3 "de la carte Sky9x" #endif #define TR_ABOUT_PARENTS_1 "Projets parents" @@ -797,10 +804,10 @@ #define TR_ABOUT_PARENTS_3 "ER9X (Erez Raviv)" #define TR_ABOUT_PARENTS_4 "TH9X (Thomas Husterer)" -#define TR_CHR_SHORT 's' -#define TR_CHR_LONG 'l' -#define TR_CHR_TOGGLE 't' -#define TR_CHR_HOUR 'h' +#define TR_CHR_SHORT 's' +#define TR_CHR_LONG 'l' +#define TR_CHR_TOGGLE 't' +#define TR_CHR_HOUR 'h' #define TR_CHR_INPUT 'E' // Values between A-I will work #define TR_BEEP_VOLUME "Beep Volume" From b919773b56b39efde43d27601069a2847b15d821 Mon Sep 17 00:00:00 2001 From: mhotar Date: Tue, 4 Mar 2014 22:26:15 +0100 Subject: [PATCH 029/285] TR_POTTYPES "None" was missing in some translations --- radio/src/translations/de.h.txt | 2 +- radio/src/translations/es.h.txt | 2 +- radio/src/translations/fi.h.txt | 2 +- radio/src/translations/it.h.txt | 2 +- radio/src/translations/pl.h.txt | 2 +- radio/src/translations/pt.h.txt | 2 +- radio/src/translations/se.h.txt | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/radio/src/translations/de.h.txt b/radio/src/translations/de.h.txt index f6ca1c69d..31ef5569e 100644 --- a/radio/src/translations/de.h.txt +++ b/radio/src/translations/de.h.txt @@ -69,7 +69,7 @@ #define TR_UART3MODES "AUS\0 ""S-Port Data Out\0""Debug\0 " #define LEN_POTTYPES "\017" -#define TR_POTTYPES "Poti\0 ""Stufen-Schalter " +#define TR_POTTYPES "None\0 ""Poti\0 ""Stufen-Schalter " #define LEN_DATETIME "\005" #define TR_DATETIME "DATE:""ZEIT:" diff --git a/radio/src/translations/es.h.txt b/radio/src/translations/es.h.txt index 9f8ea38aa..a54fd03f8 100644 --- a/radio/src/translations/es.h.txt +++ b/radio/src/translations/es.h.txt @@ -72,7 +72,7 @@ #define TR_UART3MODES "OFF\0 ""S-Port Mirror\0 ""Debug\0 " #define LEN_POTTYPES "\017" -#define TR_POTTYPES "Pot\0 ""Multipos Switch" +#define TR_POTTYPES "None\0 ""Pot\0 ""Multipos Switch" #define LEN_DATETIME "\005" #define TR_DATETIME "DATA:""HORA:" diff --git a/radio/src/translations/fi.h.txt b/radio/src/translations/fi.h.txt index 096247a56..e7e25fbc4 100644 --- a/radio/src/translations/fi.h.txt +++ b/radio/src/translations/fi.h.txt @@ -72,7 +72,7 @@ #define TR_UART3MODES "OFF\0 ""S-Port Mirror\0 ""Debug\0 " #define LEN_POTTYPES "\017" -#define TR_POTTYPES "Pot\0 ""Multipos Switch" +#define TR_POTTYPES "None\0 ""Pot\0 ""Multipos Switch" #define LEN_DATETIME "\005" #define TR_DATETIME "DATE:""TIME:" diff --git a/radio/src/translations/it.h.txt b/radio/src/translations/it.h.txt index f98270685..7e7a2eeaa 100644 --- a/radio/src/translations/it.h.txt +++ b/radio/src/translations/it.h.txt @@ -72,7 +72,7 @@ #define TR_UART3MODES "OFF\0 ""S-Port Mirror\0 ""Debug\0 " #define LEN_POTTYPES "\017" -#define TR_POTTYPES "Pot\0 ""Multipos Switch" +#define TR_POTTYPES "None\0 ""Pot\0 ""Multipos Switch" #define LEN_DATETIME "\005" #define TR_DATETIME "DATA:""ORA :" diff --git a/radio/src/translations/pl.h.txt b/radio/src/translations/pl.h.txt index b8366499a..eedb2d9d4 100644 --- a/radio/src/translations/pl.h.txt +++ b/radio/src/translations/pl.h.txt @@ -72,7 +72,7 @@ #define TR_UART3MODES "Wyłącz\0 ""S-Port Mirror\0 ""Debug\0 " #define LEN_POTTYPES "\017" -#define TR_POTTYPES "Potencjometr\0 ""Przeł.Wielopoz." +#define TR_POTTYPES "None\0 ""Potencjometr\0 ""Przeł.Wielopoz." #define LEN_DATETIME "\006" #define TR_DATETIME "DATA:\0""CZAS:\0" diff --git a/radio/src/translations/pt.h.txt b/radio/src/translations/pt.h.txt index fe01c626b..6505786e4 100644 --- a/radio/src/translations/pt.h.txt +++ b/radio/src/translations/pt.h.txt @@ -72,7 +72,7 @@ #define TR_UART3MODES "OFF\0 ""S-Port Mirror\0 ""Debug\0 " #define LEN_POTTYPES "\017" -#define TR_POTTYPES "Pot\0 ""Multipos Switch" +#define TR_POTTYPES "None\0 ""Pot\0 ""Multipos Switch" #define LEN_DATETIME "\005" #define TR_DATETIME "DATA:""HORA:" diff --git a/radio/src/translations/se.h.txt b/radio/src/translations/se.h.txt index b9cae485e..94fb53c1c 100644 --- a/radio/src/translations/se.h.txt +++ b/radio/src/translations/se.h.txt @@ -72,7 +72,7 @@ #define TR_UART3MODES "Av\0 ""Spegling av S-Port""Debug\0 " #define LEN_POTTYPES "\020" -#define TR_POTTYPES "Potentiometer\0 ""Flerlägesväljare" +#define TR_POTTYPES "None\0 ""Potentiometer\0 ""Flerlägesväljare" #define LEN_DATETIME "\005" #define TR_DATETIME "DAG: ""TID: " From 21f2130d1320872d525d4b4cadea523d86ddc11d Mon Sep 17 00:00:00 2001 From: mhotar Date: Tue, 4 Mar 2014 22:31:41 +0100 Subject: [PATCH 030/285] TR_POTTYPES "None" in cz.h.txt --- radio/src/translations/cz.h.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/radio/src/translations/cz.h.txt b/radio/src/translations/cz.h.txt index 35a21e470..dbe10d791 100644 --- a/radio/src/translations/cz.h.txt +++ b/radio/src/translations/cz.h.txt @@ -72,7 +72,7 @@ #define TR_UART3MODES "OFF\0 ""S-Port Mirror\0 ""Debug\0 " #define LEN_POTTYPES "\017" -#define TR_POTTYPES "Pot\0 ""Multipos Switch" +#define TR_POTTYPES "None\0 ""Pot\0 ""Multipos Switch" #define LEN_DATETIME "\006" #define TR_DATETIME "DATUM:""ČAS: " @@ -330,7 +330,7 @@ #define TR_VTEMPLATES "Smazat mixy\0\0""Zákl. 4kanál\0""Sticky-T-Cut\0""V-Tail \0""Elevon\\Delta\0""eCCPM \0""Heli Setup \0""Servo Test \0" #define LEN_VSWASHTYPE "\004" -#define TR_VSWASHTYPE "--- ""120 ""120X""140 ""90\0" +#define TR_VSWASHTYPE "---\0""120\0""120X""140\0""90\0" #define LEN_VKEYS "\005" #define TR_VKEYS TR("Menu\0""Exit\0""Dolů\0""Nhoru""Vprvo""Vlevo", "Menu\0""Exit\0""Enter""Page\0""Plus\0""Mínus") From 3f231585a981d0c6fd7ac7747ad4f28afd49100a Mon Sep 17 00:00:00 2001 From: mhotar Date: Tue, 4 Mar 2014 22:52:37 +0100 Subject: [PATCH 031/285] Neverending conflicts --- radio/src/translations/en.h.txt | 61 +++-- radio/src/translations/fr.h.txt | 419 ++++++++++++++++---------------- 2 files changed, 241 insertions(+), 239 deletions(-) diff --git a/radio/src/translations/en.h.txt b/radio/src/translations/en.h.txt index aaadfba49..7f26756f8 100644 --- a/radio/src/translations/en.h.txt +++ b/radio/src/translations/en.h.txt @@ -168,7 +168,7 @@ #endif #if defined(CPUARM) - #define TR_CSWEQUAL "a=x\0 " + #define TR_CSWEQUAL "a=x\0 " #else #define TR_CSWEQUAL #endif @@ -333,7 +333,7 @@ #define TR_VSCREEN "Nums""Bars" #define LEN_GPSFORMAT "\004" -#define TR_GPSFORMAT "HMS NMEA" +#define TR_GPSFORMAT "HMS ""NMEA" #define LEN2_VTEMPLATES 13 #define LEN_VTEMPLATES "\015" @@ -474,17 +474,17 @@ #define TR_ELEDIRECTION TR("ELE Direction","Long. cyc. direction") #define TR_AILDIRECTION TR("AIL Direction","Lateral cyc. direction") #define TR_COLDIRECTION TR("PIT Direction","Coll. pitch direction") -#define TR_MODE INDENT"Mode" +#define TR_MODE INDENT "Mode" #define TR_NOFREEEXPO "No free expo!" #define TR_NOFREEMIXER "No free mixer!" #define TR_INSERTMIX "INSERT MIX " #define TR_EDITMIX "EDIT MIX " -#define TR_SOURCE INDENT"Source" +#define TR_SOURCE INDENT "Source" #define TR_WEIGHT "Weight" #define TR_EXPO TR("Expo","Exponential") #define TR_SIDE "Side" #define TR_DIFFERENTIAL "Differ" -#define TR_OFFSET INDENT"Offset" +#define TR_OFFSET INDENT "Offset" #define TR_TRIM "Trim" #define TR_DREX "DRex" #define TR_CURVE "Curve" @@ -500,34 +500,33 @@ #define TR_CV "CV" #define TR_GV "GV" #define TR_ACHANNEL "A\004channel" -#define TR_RANGE INDENT"Range" +#define TR_RANGE INDENT "Range" #define TR_BAR "Bar" -#define TR_ALARM INDENT"Alarm" +#define TR_ALARM INDENT "Alarm" #define TR_USRDATA "UsrData" -#define TR_BLADES INDENT"Blades" +#define TR_BLADES INDENT "Blades" #define TR_SCREEN "Screen " #define TR_SOUND_LABEL "Sound" -#define TR_LENGTH INDENT"Length" -#define TR_SPKRPITCH INDENT"Pitch" +#define TR_LENGTH INDENT "Length" +#define TR_SPKRPITCH INDENT "Pitch" #define TR_HAPTIC_LABEL "Haptic" -#define TR_HAPTICSTRENGTH INDENT"Strength" +#define TR_HAPTICSTRENGTH INDENT "Strength" #define TR_CONTRAST "Contrast" #define TR_ALARMS_LABEL "Alarms" #define TR_BATTERY_RANGE TR("Battery range","Battery meter range") -#define TR_BATTERYWARNING INDENT"Battery Low" -#define TR_INACTIVITYALARM INDENT"Inactivity" -#define TR_MEMORYWARNING INDENT"Memory Low" -#define TR_ALARMWARNING INDENT"Sound Off" +#define TR_BATTERYWARNING INDENT "Battery Low" +#define TR_INACTIVITYALARM INDENT "Inactivity" +#define TR_MEMORYWARNING INDENT "Memory Low" +#define TR_ALARMWARNING INDENT "Sound Off" #define TR_RENAVIG "RotEnc Navig" -#define TR_THROTTLE_LABEL "Throttle" -#define TR_THROTTLEREVERSE TR("T-Reverse", INDENT "Reverse") +#define TR_THROTTLEREVERSE TR("T-Reverse", "Throttle reverse") #define TR_MINUTEBEEP TR(INDENT "Minute",INDENT "Minute call") #define TR_BEEPCOUNTDOWN INDENT "Countdown" #define TR_PERSISTENT TR(INDENT "Persist.",INDENT "Persistent") #define TR_BACKLIGHT_LABEL "Backlight" -#define TR_BLDELAY INDENT"Duration" -#define TR_BLONBRIGHTNESS INDENT"ON Brightness" -#define TR_BLOFFBRIGHTNESS INDENT"OFF Brightness" +#define TR_BLDELAY INDENT "Duration" +#define TR_BLONBRIGHTNESS INDENT "ON Brightness" +#define TR_BLOFFBRIGHTNESS INDENT "OFF Brightness" #define TR_SPLASHSCREEN "Splash screen" #define TR_THROTTLEWARNING TR("T-Warning","Throttle Warning") #define TR_SWITCHWARNING TR("S-Warning","Switch Warning") @@ -611,9 +610,9 @@ #define TR_MENUTEMPLATES "TEMPLATES" #define TR_MENUSTAT "STATS" #define TR_MENUDEBUG "DEBUG" -#define TR_RXNUM TR("RxNum", INDENT"Receiver No.") +#define TR_RXNUM TR("RxNum", INDENT "Receiver No.") #define TR_SYNCMENU "[Sync]" -#define TR_LIMIT INDENT"Limit" +#define TR_LIMIT INDENT "Limit" #define TR_MINRSSI "Min Rssi" #define TR_LATITUDE "Latitude" #define TR_LONGITUDE "Longitude" @@ -622,8 +621,8 @@ #define TR_SHUTDOWN "SHUTTING DOWN" #define TR_BATT_CALIB "Battery Calib" #define TR_CURRENT_CALIB "Current Calib" -#define TR_VOLTAGE INDENT"Voltage" -#define TR_CURRENT INDENT"Current" +#define TR_VOLTAGE INDENT "Voltage" +#define TR_CURRENT INDENT "Current" #define TR_SELECT_MODEL "Select Model" #define TR_CREATE_MODEL "Create Model" #define TR_COPY_MODEL "Copy Model" @@ -711,8 +710,8 @@ #define TR_ABOUT_US "About" #define TR_AND_SWITCH "AND Switch" #define TR_CF "CF" -#define TR_SPEAKER INDENT"Speaker" -#define TR_BUZZER INDENT"Buzzer" +#define TR_SPEAKER INDENT "Speaker" +#define TR_BUZZER INDENT "Buzzer" #define TR_BYTES "bytes" #define TR_MODULE_BIND "[Bind]" #define TR_MODULE_RANGE "[Range]" @@ -808,11 +807,11 @@ #define TR_ABOUT_PARENTS_3 "ER9X (Erez Raviv)" #define TR_ABOUT_PARENTS_4 "TH9X (Thomas Husterer)" -#define TR_CHR_SHORT 's' -#define TR_CHR_LONG 'l' -#define TR_CHR_TOGGLE 't' -#define TR_CHR_HOUR 'h' -#define TR_CHR_INPUT 'I' // Values between A-I will work +#define TR_CHR_SHORT 's' +#define TR_CHR_LONG 'l' +#define TR_CHR_TOGGLE 't' +#define TR_CHR_HOUR 'h' +#define TR_CHR_INPUT 'I' // Values between A-I will work #define TR_BEEP_VOLUME "Beep Volume" #define TR_WAV_VOLUME "Wav Volume" diff --git a/radio/src/translations/fr.h.txt b/radio/src/translations/fr.h.txt index 5cdb604fa..b28416cee 100644 --- a/radio/src/translations/fr.h.txt +++ b/radio/src/translations/fr.h.txt @@ -1,10 +1,7 @@ /* * Authors (alphabetical order) + * - Andre Bernet * - Bertrand Songis - * - Bernet Andre - * - Kjell Kernen - * - Martin Hotar - * - Romolo Manfredini * * opentx is based on code named * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, @@ -39,90 +36,90 @@ * \001 to \035 -extended spacing (value * FW/2) * \0 -ends actual string */ - + // NON ZERO TERMINATED STRINGS -#define LEN_OFFON "\003" -#define TR_OFFON "OFF""ON\0" +#define LEN_OFFON "\003" +#define TR_OFFON "OFF""ON\0" -#define LEN_MMMINV "\003" -#define TR_MMMINV "---""INV" +#define LEN_MMMINV "\003" +#define TR_MMMINV "---""INV" -#define LEN_NCHANNELS "\004" -#define TR_NCHANNELS "\0014CH\0016CH\0018CH10CH12CH14CH16CH" +#define LEN_NCHANNELS "\004" +#define TR_NCHANNELS "\0014CH\0016CH\0018CH10CH12CH14CH16CH" -#define LEN_VBEEPMODE "\005" -#define TR_VBEEPMODE "Aucun""Alarm""NoKey""Tout\0" +#define LEN_VBEEPMODE "\005" +#define TR_VBEEPMODE "Aucun""Alarm""NoKey""Tout\0" -#define LEN_VBEEPLEN "\005" -#define TR_VBEEPLEN "0====""=0===""==0==""===0=""====0" +#define LEN_VBEEPLEN "\005" +#define TR_VBEEPLEN "0====""=0===""==0==""===0=""====0" -#define LEN_VRENAVIG "\003" -#define TR_VRENAVIG "NonREaREb" +#define LEN_VRENAVIG "\003" +#define TR_VRENAVIG "NonREaREb" -#define LEN_VBLMODE TR("\004","\011") -#define TR_VBLMODE TR("OFF\0""Btns""Ctrl""Tous""ON\0","OFF\0 ""Touches\0 ""Controles""Tous\0 ""ON\0 ") +#define LEN_VBLMODE TR("\004","\011") +#define TR_VBLMODE TR("OFF\0""Btns""Ctrl""Tous""ON\0","OFF\0 ""Touches\0 ""Controles""Tous\0 ""ON\0 ") -#define LEN_TRNMODE "\003" -#define TR_TRNMODE "OFF"" +="" :=" +#define LEN_TRNMODE "\003" +#define TR_TRNMODE "OFF"" +="" :=" -#define LEN_TRNCHN "\003" -#define TR_TRNCHN "CH1CH2CH3CH4" +#define LEN_TRNCHN "\003" +#define TR_TRNCHN "CH1CH2CH3CH4" -#define LEN_UART3MODES "\017" -#define TR_UART3MODES "OFF\0 ""Recopie S-Port\0""Debug\0 " +#define LEN_UART3MODES "\017" +#define TR_UART3MODES "OFF\0 ""Recopie S-Port\0""Debug\0 " -#define LEN_POTTYPES "\017" -#define TR_POTTYPES "Potentiomètre\0 ""Inter multi-pos" +#define LEN_POTTYPES "\017" +#define TR_POTTYPES "Rien\0 ""Potentiomètre\0 ""Inter multi-pos" -#define LEN_DATETIME "\005" -#define TR_DATETIME "DATE:""HEURE" +#define LEN_DATETIME "\005" +#define TR_DATETIME "DATE:""HEURE" -#define LEN_VLCD "\006" -#define TR_VLCD "NormalOptrex" +#define LEN_VLCD "\006" +#define TR_VLCD "NormalOptrex" -#define LEN_COUNTRYCODES TR("\002", "\006") -#define TR_COUNTRYCODES TR("US""JP""EU", "USA\0 ""Japon\0""Europe") +#define LEN_COUNTRYCODES TR("\002", "\006") +#define TR_COUNTRYCODES TR("US""JP""EU", "USA\0 ""Japon\0""Europe") -#define LEN_VTRIMINC TR("\006","\013") -#define TR_VTRIMINC TR("Expo\0 ""ExFin\0""Fin\0 ""Moyen\0""Gros\0 ","Exponentiel""Extra Fin\0 ""Fin\0 ""Moyen\0 ""Grossier\0 ") +#define LEN_VTRIMINC TR("\006","\013") +#define TR_VTRIMINC TR("Expo\0 ""ExFin\0""Fin\0 ""Moyen\0""Gros\0 ","Exponentiel""Extra Fin\0 ""Fin\0 ""Moyen\0 ""Grossier\0 ") #define LEN_VBEEPCOUNTDOWN "\006" #define TR_VBEEPCOUNTDOWN "SilentBeeps\0Voice\0" -#define LEN_RETA123 "\001" +#define LEN_RETA123 "\001" #if defined(PCBGRUVIN9X) #if ROTARY_ENCODERS > 2 - #define TR_RETA123 "DPGA123abcd" + #define TR_RETA123 "DPGA123abcd" #else - #define TR_RETA123 "DPGA123ab" + #define TR_RETA123 "DPGA123ab" #endif #elif defined(PCBTARANIS) - #define TR_RETA123 "DPGA12LR" -#else - #define TR_RETA123 "DPGA123" + #define TR_RETA123 "DPGA12LR" +#else + #define TR_RETA123 "DPGA123" #endif -#define LEN_VPROTOS "\006" +#define LEN_VPROTOS "\006" #if defined(PXX) - #define TR_PXX "PXX\0 " + #define TR_PXX "PXX\0 " #elif defined(DSM2) || defined(IRPROTOS) - #define TR_PXX "[PXX]\0" + #define TR_PXX "[PXX]\0" #else #define TR_PXX #endif #if defined(DSM2) - #define TR_DSM2 "LP45\0 ""DSM2\0 ""DSMX\0 " + #define TR_DSM2 "LP45\0 ""DSM2\0 ""DSMX\0 " #elif defined(IRPROTOS) - #define TR_DSM2 "[LP45]""[DSM2]""[DSMX]" + #define TR_DSM2 "[LP45]""[DSM2]""[DSMX]" #else #define TR_DSM2 #endif #if defined(IRPROTOS) - #define TR_IRPROTOS "SILV TRAC09PICZ SWIFT\0" + #define TR_IRPROTOS "SILV TRAC09PICZ SWIFT\0" #else #define TR_IRPROTOS #endif @@ -130,25 +127,25 @@ #if defined(CPUARM) #define TR_XPPM #else - #define TR_XPPM "PPM16\0""PPMsim" + #define TR_XPPM "PPM16\0""PPMsim" #endif -#define TR_VPROTOS "PPM\0 " TR_XPPM TR_PXX TR_DSM2 TR_IRPROTOS +#define TR_VPROTOS "PPM\0 " TR_XPPM TR_PXX TR_DSM2 TR_IRPROTOS -#define LEN_POSNEG "\003" -#define TR_POSNEG "POS""NEG" +#define LEN_POSNEG "\003" +#define TR_POSNEG "POS""NEG" -#define LEN_VCURVEFUNC "\003" -#define TR_VCURVEFUNC "---""x>0""x<0""|x|""f>0""f<0""|f|" +#define LEN_VCURVEFUNC "\003" +#define TR_VCURVEFUNC "---""x>0""x<0""|x|""f>0""f<0""|f|" -#define LEN_VMLTPX TR("\010","\013") -#define TR_VMLTPX TR("Ajoute\0 ""Multipl.""Remplace","Additionner""Multiplier\0""Remplacer\0 ") +#define LEN_VMLTPX TR("\010", "\013") +#define TR_VMLTPX TR("Ajoute\0 ""Multipl.""Remplace","Additionner""Multiplier\0""Remplacer\0 ") -#define LEN_VMLTPX2 "\002" -#define TR_VMLTPX2 "+=""*="":=" +#define LEN_VMLTPX2 "\002" +#define TR_VMLTPX2 "+=""*="":=" -#define LEN_VMIXTRIMS "\003" -#define TR_VMIXTRIMS "OFF""ON\0""Dir""Prf""Gaz""Ail" +#define LEN_VMIXTRIMS "\003" +#define TR_VMIXTRIMS "OFF""ON\0""Dir""Prf""Gaz""Ail" #if defined(PCBTARANIS) #define TR_CSWTIMER "Tempo" @@ -168,86 +165,86 @@ #endif #if defined(CPUARM) - #define TR_CSWEQUAL "a=x\0 " + #define TR_CSWEQUAL "a=x\0 " #else #define TR_CSWEQUAL #endif -#define LEN_VCSWFUNC "\005" +#define LEN_VCSWFUNC "\005" #if defined(CPUARM) -#define TR_VCSWFUNC "---\0 " TR_CSWEQUAL "a{x\0 ""a>x\0 ""ax""|a|b\0 ""ax\0 ""ax""|a|b\0 ""ax\0 ""ax""|a|b\0 ""ax\0 ""ax""|a|b\0 ""a" +#define LEN_VALARMFN "\001" +#define TR_VALARMFN "<>" -#define LEN_VTELPROTO "\007" -#define TR_VTELPROTO "Aucun ""Hub\0 ""WSHHigh""Halcyon" +#define LEN_VTELPROTO "\007" +#define TR_VTELPROTO "Aucun ""Hub\0 ""WSHHigh""Halcyon" -#define LEN_VOLTSRC "\003" -#define TR_VOLTSRC "---""A1\0""A2\0""FAS""Cel" +#define LEN_VOLTSRC "\003" +#define TR_VOLTSRC "---""A1\0""A2\0""FAS""Cel" -#define LEN_VARIOSRC "\005" +#define LEN_VARIOSRC "\005" #if defined(FRSKY_SPORT) - #define TR_VARIOSRC "Vario""A1\0 ""A2\0" + #define TR_VARIOSRC "Vario""A1\0 ""A2\0""dTE\0" #else #define TR_VARIOSRC "Alti\0""Alti+""Vario""A1\0 ""A2\0" #endif -#define LEN_VSCREEN TR("\004","\007") -#define TR_VSCREEN TR("Val.""Bars","Valeurs""Barres\0") +#define LEN_VSCREEN TR("\004", "\007") +#define TR_VSCREEN TR("Val.""Bars", "Valeurs""Barres\0") -#define LEN_GPSFORMAT "\004" -#define TR_GPSFORMAT "DMS\0NMEA" +#define LEN_GPSFORMAT "\004" +#define TR_GPSFORMAT "DMS\0""NMEA" -#define LEN2_VTEMPLATES 15 -#define LEN_VTEMPLATES "\017" -#define TR_VTEMPLATES "Suppr Mixages\0 ""4 Voies simple\0""Coupure Gaz\0 ""Empennage V\0 ""Elevon\\Delta\0 ""eCCPM\0 ""Conf. Hélico\0 ""Test Servo\0 " +#define LEN2_VTEMPLATES 15 +#define LEN_VTEMPLATES "\017" +#define TR_VTEMPLATES "Suppr Mixages\0 ""4 Voies simple\0""Coupure Gaz\0 ""Empennage V\0 ""Elevon\\Delta\0 ""eCCPM\0 ""Conf. Hélico\0 ""Test Servo\0 " -#define LEN_VSWASHTYPE "\004" -#define TR_VSWASHTYPE "--- ""120 ""120X""140 ""90\0" +#define LEN_VSWASHTYPE "\004" +#define TR_VSWASHTYPE "--- ""120 ""120X""140 ""90\0" -#define LEN_VKEYS "\005" -#define TR_VKEYS TR("Menu\0""Exit\0""Bas\0 ""Haut\0""Droit""Gauch", "Menu\0""Exit\0""Enter""Page\0""Plus\0""Minus") +#define LEN_VKEYS "\005" +#define TR_VKEYS TR("Menu\0""Exit\0""Bas\0 ""Haut\0""Droit""Gauch", "Menu\0""Exit\0""Enter""Page\0""Plus\0""Minus") -#define LEN_VRENCODERS "\003" -#define TR_VRENCODERS "REa""REb" +#define LEN_VRENCODERS "\003" +#define TR_VRENCODERS "REa""REb" -#define LEN_VSWITCHES "\003" -#define LEN_VSRCRAW "\004" +#define LEN_VSWITCHES "\003" +#define LEN_VSRCRAW "\004" #if defined(PCBTARANIS) #define TR_POTS_VSRCRAW "S1\0 ""S2\0 ""S3\0 ""LS\0 ""RS\0 " @@ -355,11 +360,11 @@ #endif #if defined(CPUARM) - #define TR_LOGICALSW "IL1""IL2""IL3""IL4""IL5""IL6""IL7""IL8""IL9""ILA""ILB""ILC""ILD""ILE""ILF""ILG""ILH""ILI""ILJ""ILK""ILL""ILM""ILN""ILO""ILP""ILQ""ILR""ILS""ILT""ILU""ILV""ILW" + #define TR_LOGICALSW "IL1""IL2""IL3""IL4""IL5""IL6""IL7""IL8""IL9""ILA""ILB""ILC""ILD""ILE""ILF""ILG""ILH""ILI""ILJ""ILK""ILL""ILM""ILN""ILO""ILP""ILQ""ILR""ILS""ILT""ILU""ILV""ILW" #elif defined(PCBGRUVIN9X) || defined(CPUM2561) || defined(CPUM128) - #define TR_LOGICALSW "IL1""IL2""IL3""IL4""IL5""IL6""IL7""IL8""IL9""ILA""ILB""ILC""ILD""ILE""ILF" + #define TR_LOGICALSW "IL1""IL2""IL3""IL4""IL5""IL6""IL7""IL8""IL9""ILA""ILB""ILC""ILD""ILE""ILF" #else - #define TR_LOGICALSW "IL1""IL2""IL3""IL4""IL5""IL6""IL7""IL8""IL9""ILA""ILB""ILC" + #define TR_LOGICALSW "IL1""IL2""IL3""IL4""IL5""IL6""IL7""IL8""IL9""ILA""ILB""ILC" #endif #define TR_TRIMS_SWITCHES "tDg""tDd""tPb""tPh""tGb""tGh""tAg""tAd" @@ -385,21 +390,21 @@ #endif #if defined(HELI) -#define TR_CYC_VSRCRAW "CYC1""CYC2""CYC3" + #define TR_CYC_VSRCRAW "CYC1""CYC2""CYC3" #else -#define TR_CYC_VSRCRAW "[C1]""[C2]""[C3]" + #define TR_CYC_VSRCRAW "[C1]""[C2]""[C3]" #endif -#define TR_VSRCRAW "---\0""Dir\0""Prf\0""Gaz\0""Ail\0" TR_POTS_VSRCRAW TR_ROTARY_ENCODERS "MAX\0" TR_CYC_VSRCRAW "TrmD" "TrmP" "TrmG" "TrmA" TR_SW_VSRCRAW +#define TR_VSRCRAW "---\0""Dir\0""Prf\0""Gaz\0""Ail\0" TR_POTS_VSRCRAW TR_ROTARY_ENCODERS "MAX\0" TR_CYC_VSRCRAW "TrmD" "TrmP" "TrmG" "TrmA" TR_SW_VSRCRAW -#define LEN_VTMRMODES "\003" -#define TR_VTMRMODES "OFF""ABS""GZs""GZ%""GZt" +#define LEN_VTMRMODES "\003" +#define TR_VTMRMODES "OFF""ABS""GZs""GZ%""GZt" #define LEN_VTRAINERMODES "\006" #define TR_VTRAINERMODES "Maître""Elève\0" -#define LEN_VFAILSAFE "\011" -#define TR_VFAILSAFE "Maintien\0""Prédéfini""Pas d'imp" +#define LEN_VFAILSAFE "\011" +#define TR_VFAILSAFE "Maintien\0""Prédéfini""Pas d'imp" #if defined(MAVLINK) #define LEN_MAVLINK_BAUDS "\006" @@ -445,40 +450,40 @@ #define TR_ELIMITS TR("Limites ét", "Limites étendues") #define TR_ETRIMS TR("Trims ét.", "Trims étendus") #define TR_TRIMINC TR("Pas Trim", "Pas des trims") -#define TR_TTRACE TR("Source gaz", INDENT "Source gaz") -#define TR_TTRIM TR("Trim gaz", INDENT "Trim gaz") +#define TR_TTRACE "Source gaz" +#define TR_TTRIM "Trim gaz" #define TR_BEEPCTR TR("Bips centr", "Bips centrage") #define TR_PROTO TR(INDENT "Proto.", INDENT "Protocole") #define TR_PPMFRAME INDENT "Trame PPM" #define TR_MS "ms" -#define TR_SWITCH TR("Inter","Interrupteur") +#define TR_SWITCH TR("Inter", "Interrupteur") #define TR_TRIMS "Trims" #define TR_FADEIN "Fondu ON" #define TR_FADEOUT "Fondu OFF" #define TR_DEFAULT "(défaut)" #define TR_CHECKTRIMS "\006Vérif\012Trims" #define OFS_CHECKTRIMS (9*FW) -#define TR_SWASHTYPE TR("Type de Plat.","Type de plateau") -#define TR_COLLECTIVE TR("Collectif","Voie du pas collectif") -#define TR_SWASHRING TR("Limite Cycl.","Limite du cyclique") -#define TR_ELEDIRECTION TR("Inv. longitud.","Inversion longitudinal") -#define TR_AILDIRECTION TR("Inv. latéral","Inversion latéral") -#define TR_COLDIRECTION TR("Inv. collectif","Inversion collectif") -#define TR_MODE INDENT"Mode" +#define TR_SWASHTYPE TR("Type de Plat.", "Type de plateau") +#define TR_COLLECTIVE TR("Collectif", "Voie du pas collectif") +#define TR_SWASHRING TR("Limite Cycl.", "Limite du cyclique") +#define TR_ELEDIRECTION TR("Inv. longitud.", "Inversion longitudinal") +#define TR_AILDIRECTION TR("Inv. latéral", "Inversion latéral") +#define TR_COLDIRECTION TR("Inv. collectif", "Inversion collectif") +#define TR_MODE INDENT "Mode" #define TR_NOFREEEXPO "Max expos atteint!" #define TR_NOFREEMIXER "Max mixages atteint!" #define TR_INSERTMIX "INSERER MIXAGE" #define TR_EDITMIX "EDITER MIXAGE" -#define TR_SOURCE INDENT"Source" +#define TR_SOURCE INDENT "Source" #define TR_WEIGHT "Ratio" -#define TR_EXPO TR("Expo","Exponentiel") +#define TR_EXPO TR("Expo", "Exponentiel") #define TR_SIDE "Coté" #define TR_DIFFERENTIAL "Différentiel" -#define TR_OFFSET INDENT"Décalage" +#define TR_OFFSET INDENT "Décalage" #define TR_TRIM "Trim" #define TR_DREX "DRex" #define TR_CURVE "Courbe" -#define TR_FLMODE TR("Phase","Phases") +#define TR_FLMODE TR("Phase", "Phases") #define TR_MIXWARNING "Alerte" #define TR_OFF "OFF" #define TR_MULTPX "Opération" @@ -490,34 +495,33 @@ #define TR_CV "CB" #define TR_GV "VG" #define TR_ACHANNEL "A" -#define TR_RANGE INDENT"Plage" +#define TR_RANGE INDENT "Plage" #define TR_BAR "Barre" -#define TR_ALARM INDENT"Alarme" +#define TR_ALARM INDENT "Alarme" #define TR_USRDATA "Données" -#define TR_BLADES INDENT"Pales" +#define TR_BLADES INDENT "Pales" #define TR_SCREEN "Ecran " #define TR_SOUND_LABEL "Son" -#define TR_LENGTH INDENT"Durée" -#define TR_SPKRPITCH INDENT"Tonalité" +#define TR_LENGTH INDENT "Durée" +#define TR_SPKRPITCH INDENT "Tonalité" #define TR_HAPTIC_LABEL "Vibreur" -#define TR_HAPTICSTRENGTH INDENT"Force" +#define TR_HAPTICSTRENGTH INDENT "Force" #define TR_CONTRAST "Contraste" #define TR_ALARMS_LABEL "Alarmes" #define TR_BATTERY_RANGE "Plage batterie" -#define TR_BATTERYWARNING TR(INDENT"Batterie",INDENT"Batterie faible") -#define TR_INACTIVITYALARM INDENT"Inactivité" -#define TR_MEMORYWARNING INDENT"Mémoire pleine" -#define TR_ALARMWARNING TR(INDENT"Silence",INDENT"Sons désactivés") +#define TR_BATTERYWARNING TR(INDENT "Batterie",INDENT "Batterie faible") +#define TR_INACTIVITYALARM INDENT "Inactivité" +#define TR_MEMORYWARNING INDENT "Mémoire pleine" +#define TR_ALARMWARNING TR(INDENT "Silence",INDENT "Sons désactivés") #define TR_RENAVIG "Navig EncRot" -#define TR_THROTTLE_LABEL "Gaz" -#define TR_THROTTLEREVERSE TR("Inv. gaz", INDENT "Inversion gaz") +#define TR_THROTTLEREVERSE TR("Inv. gaz","Inversion gaz") #define TR_MINUTEBEEP TR(INDENT "Bip min.",INDENT "Annonces minutes") #define TR_BEEPCOUNTDOWN TR(INDENT "Bip fin",INDENT "Compte à rebours") #define TR_PERSISTENT TR(INDENT "Persist.",INDENT "Persistant") #define TR_BACKLIGHT_LABEL "Rétroéclairage" -#define TR_BLDELAY INDENT"Durée" -#define TR_BLONBRIGHTNESS INDENT"Luminosité ON" -#define TR_BLOFFBRIGHTNESS INDENT"Luminosité OFF" +#define TR_BLDELAY INDENT "Durée" +#define TR_BLONBRIGHTNESS INDENT "Luminosité ON" +#define TR_BLOFFBRIGHTNESS INDENT "Luminosité OFF" #define TR_SPLASHSCREEN "Logo d'accueil" #define TR_THROTTLEWARNING "Alerte gaz" #define TR_SWITCHWARNING TR("Alerte int","Alerte interrupt.") @@ -582,28 +586,28 @@ #define TR_MENUHELISETUP TR("CONF.HELI","CONFIGURATION HELICO") #if defined(PCBTARANIS) - #define TR_MENUINPUTS "ENTREES" - #define TR_MENULIMITS "SORTIES" + #define TR_MENUINPUTS "ENTREES" + #define TR_MENULIMITS "SORTIES" #elif defined(PPM_CENTER_ADJUSTABLE) || defined(PPM_LIMITS_SYMETRICAL) // The right menu titles for the gurus ... - #define TR_MENUINPUTS "MANCHES" - #define TR_MENULIMITS "SORTIES" + #define TR_MENUINPUTS "MANCHES" + #define TR_MENULIMITS "SORTIES" #else - #define TR_MENUINPUTS "DR/EXPO" - #define TR_MENULIMITS "LIMITES" + #define TR_MENUINPUTS "DR/EXPO" + #define TR_MENULIMITS "LIMITES" #endif #define TR_MENUCURVES "COURBES" #define TR_MENUCURVE "COURBE" -#define TR_MENULOGICALSWITCH "INTER LOG." -#define TR_MENULOGICALSWITCHES TR("INTERS LOG.","INTERS LOGIQUES") +#define TR_MENULOGICALSWITCH "INTER LOG." +#define TR_MENULOGICALSWITCHES TR("INTERS LOG.","INTERS LOGIQUES") #define TR_MENUCUSTOMFUNC TR("FONCTIONS SPEC.","FONCTIONS SPECIALES") #define TR_MENUTELEMETRY "TELEMESURE" #define TR_MENUTEMPLATES "GABARITS" #define TR_MENUSTAT TR("STATS","STATISTIQUES") #define TR_MENUDEBUG "DEBUG" -#define TR_RXNUM TR(INDENT"NumRx",INDENT"No. récepteur") +#define TR_RXNUM TR(INDENT "NumRx",INDENT "No. récepteur") #define TR_SYNCMENU "Sync [MENU]" -#define TR_LIMIT INDENT"Limite" +#define TR_LIMIT INDENT "Limite" #define TR_MINRSSI "RSSI Min." #define TR_LATITUDE "Latitude" #define TR_LONGITUDE "Longitude" @@ -612,8 +616,8 @@ #define TR_SHUTDOWN "ARRET EN COURS" #define TR_BATT_CALIB "Calib. Batterie" #define TR_CURRENT_CALIB "Calib. Courant" -#define TR_VOLTAGE INDENT"Tension" -#define TR_CURRENT INDENT"Courant" +#define TR_VOLTAGE INDENT "Tension" +#define TR_CURRENT INDENT "Courant" #define TR_SELECT_MODEL "Sélect. Modèle" #define TR_CREATE_MODEL "Créer Modèle" #define TR_COPY_MODEL "Copier Modèle" @@ -680,10 +684,10 @@ #define TR_CHANNELS_MONITOR "MONITEUR CANAUX" #define TR_INTERNALRF "HF interne" #define TR_EXTERNALRF "HF externe" -#define TR_FAILSAFE INDENT"Type failsafe" +#define TR_FAILSAFE INDENT "Type failsafe" #define TR_FAILSAFESET "REGLAGES FAILSAFE" #define TR_COUNTRYCODE "Zone géo." -#define TR_VOICELANG TR("Langue voix","Langue annonces vocales") +#define TR_VOICELANG TR("Langue voix", "Langue annonces vocales") #define TR_UNITSSYSTEM "Unités" #define TR_EDIT "Editer" #define TR_INSERT_BEFORE "Insérer avant" @@ -693,16 +697,16 @@ #define TR_PASTE "Coller" #define TR_DELETE "Effacer" #define TR_INSERT "Insérer" -#define TR_RESET_FLIGHT TR("Réinit. vol","Réinitialiser vol") -#define TR_RESET_TIMER1 TR("Réinit. Timer1","Réinitialiser Timer1") -#define TR_RESET_TIMER2 TR("Réinit. Timer2","Réinitialiser Timer2") -#define TR_RESET_TELEMETRY TR("Réinit. Télém.","Réinit. Télémesure") +#define TR_RESET_FLIGHT TR("Réinit. vol", "Réinitialiser vol") +#define TR_RESET_TIMER1 TR("Réinit. Timer1", "Réinitialiser Timer1") +#define TR_RESET_TIMER2 TR("Réinit. Timer2", "Réinitialiser Timer2") +#define TR_RESET_TELEMETRY TR("Réinit. Télém.", "Réinit. Télémesure") #define TR_STATISTICS "Statistiques" #define TR_ABOUT_US "A propos" #define TR_AND_SWITCH "ET suppl." #define TR_CF "FS" -#define TR_SPEAKER INDENT"Haut-p." -#define TR_BUZZER INDENT"Bipeur" +#define TR_SPEAKER INDENT "Haut-p." +#define TR_BUZZER INDENT "Bipeur" #define TR_BYTES "bytes" #define TR_MODULE_BIND "[Bind]" #define TR_MODULE_RANGE "[Port.]" @@ -710,14 +714,13 @@ #define TR_SET "[Déf.]" #define TR_TRAINER "Ecolage" #define TR_ANTENNAPROBLEM CENTER "Antenne radio défectueuse!" -#define TR_MODELIDUSED TR("ID déjà affecté","No de modèle déjà utilisé") +#define TR_MODELIDUSED TR("ID déjà affecté", "No de modèle déjà utilisé") #define TR_MODULE INDENT "Type de module" #define TR_CHANNELRANGE INDENT "Plage de canaux" #define TR_LOWALARM INDENT "Alarme basse" #define TR_CRITICALALARM INDENT "Alarme critique" #define TR_PERSISTENT_MAH TR(INDENT "Enr. mAh", INDENT "Enregistrer mAh") -#define TR_PREFLIGHT "Preflight Checks" -#define TR_CHECKLIST INDENT "Afficher notes" +#define TR_CHECKLIST "Afficher notes" #define TR_FAS_OFFSET TR(INDENT "Corr FAS", INDENT "Correction FAS") #define TR_UART3MODE "Port série" @@ -753,17 +756,17 @@ #define TR_CSW_HEADERS { " Fonction ", " V1 ", " V2 ", " V2 ", " ET suppl. ", " Durée ", " Délai " } //Taranis About screen -#define TR_ABOUTUS TR(" A PROPOS ","A PROPOS") +#define TR_ABOUTUS TR(" A PROPOS ", "A PROPOS") -#define TR_ABOUT_OPENTX_1 TR("OpenTX\001est\001libre,\001non-","OpenTX est libre, non-") -#define TR_ABOUT_OPENTX_2 TR("commercial,\001et\001offert\001sans","commercial et n'offre aucune") -#define TR_ABOUT_OPENTX_3 TR("garantie.\001Il\001est\001développé","garantie. Il a été développé") -#define TR_ABOUT_OPENTX_4 TR("gratuitement.\001Donations","gratuitement. Vos donations") -#define TR_ABOUT_OPENTX_5 TR("bienvenues!","sont bienvenues!") +#define TR_ABOUT_OPENTX_1 TR("OpenTX\001est\001libre,\001non-", "OpenTX est libre, non-") +#define TR_ABOUT_OPENTX_2 TR("commercial,\001et\001offert\001sans", "commercial et n'offre aucune") +#define TR_ABOUT_OPENTX_3 TR("garantie.\001Il\001est\001développé", "garantie. Il a été développé") +#define TR_ABOUT_OPENTX_4 TR("gratuitement.\001Donations", "gratuitement. Vos donations") +#define TR_ABOUT_OPENTX_5 TR("bienvenues!", "sont bienvenues!") #define TR_ABOUT_BERTRAND_1 "Bertrand Songis" -#define TR_ABOUT_BERTRAND_2 TR("Auteur\001principal\001d'OpenTX","Auteur principal d'OpenTX") -#define TR_ABOUT_BERTRAND_3 TR("Codéveloppeur\001de\001C9X","Codéveloppeur de Companion9x") +#define TR_ABOUT_BERTRAND_2 TR("Auteur\001principal\001d'OpenTX", "Auteur principal d'OpenTX") +#define TR_ABOUT_BERTRAND_3 TR("Codéveloppeur\001de\001C9X", "Codéveloppeur de Companion9x") #define TR_ABOUT_MIKE_1 "Mike Blandford" #define TR_ABOUT_MIKE_2 "Maître du code et des" @@ -785,13 +788,13 @@ #define TR_ABOUT_MARTIN_2 "Design graphique" #if defined(PCBTARANIS) - #define TR_ABOUT_HARDWARE_1 "FrSky" - #define TR_ABOUT_HARDWARE_2 "Développeur/fabricant" - #define TR_ABOUT_HARDWARE_3 "du matériel" + #define TR_ABOUT_HARDWARE_1 "FrSky" + #define TR_ABOUT_HARDWARE_2 "Développeur/fabricant" + #define TR_ABOUT_HARDWARE_3 "du matériel" #else - #define TR_ABOUT_HARDWARE_1 "Brent Nelson" - #define TR_ABOUT_HARDWARE_2 "Développeur/fabricant" - #define TR_ABOUT_HARDWARE_3 "de la carte Sky9x" + #define TR_ABOUT_HARDWARE_1 "Brent Nelson" + #define TR_ABOUT_HARDWARE_2 "Développeur/fabricant" + #define TR_ABOUT_HARDWARE_3 "de la carte Sky9x" #endif #define TR_ABOUT_PARENTS_1 "Projets parents" @@ -799,10 +802,10 @@ #define TR_ABOUT_PARENTS_3 "ER9X (Erez Raviv)" #define TR_ABOUT_PARENTS_4 "TH9X (Thomas Husterer)" -#define TR_CHR_SHORT 's' -#define TR_CHR_LONG 'l' -#define TR_CHR_TOGGLE 't' -#define TR_CHR_HOUR 'h' +#define TR_CHR_SHORT 's' +#define TR_CHR_LONG 'l' +#define TR_CHR_TOGGLE 't' +#define TR_CHR_HOUR 'h' #define TR_CHR_INPUT 'E' // Values between A-I will work #define TR_BEEP_VOLUME "Beep Volume" From 708411c272aaf858f38da9cae17338be17075b29 Mon Sep 17 00:00:00 2001 From: mhotar Date: Tue, 4 Mar 2014 23:08:18 +0100 Subject: [PATCH 032/285] EN,FR translations --- radio/src/translations/en.h.txt | 16 +++++++++------- radio/src/translations/fr.h.txt | 16 +++++++++------- 2 files changed, 18 insertions(+), 14 deletions(-) diff --git a/radio/src/translations/en.h.txt b/radio/src/translations/en.h.txt index 7f26756f8..48f356d62 100644 --- a/radio/src/translations/en.h.txt +++ b/radio/src/translations/en.h.txt @@ -455,8 +455,8 @@ #define TR_ELIMITS TR("E.Limits", "Extended Limits") #define TR_ETRIMS TR("E.Trims", "Extended Trims") #define TR_TRIMINC "Trim Step" -#define TR_TTRACE TR("T-Source", "Throttle Source") -#define TR_TTRIM TR("T-Trim", "Throttle Trim") +#define TR_TTRACE TR("T-Source", INDENT "Source") +#define TR_TTRIM TR("T-Trim", INDENT "Idle Trim") #define TR_BEEPCTR TR("Ctr Beep", "Center Beep") #define TR_PROTO TR(INDENT "Proto", INDENT "Protocol") #define TR_PPMFRAME TR("PPM frame", INDENT "PPM frame") @@ -519,7 +519,8 @@ #define TR_MEMORYWARNING INDENT "Memory Low" #define TR_ALARMWARNING INDENT "Sound Off" #define TR_RENAVIG "RotEnc Navig" -#define TR_THROTTLEREVERSE TR("T-Reverse", "Throttle reverse") +#define TR_THROTTLE_LABEL "Throttle" +#define TR_THROTTLEREVERSE TR("T-Reverse", INDENT "Reverse") #define TR_MINUTEBEEP TR(INDENT "Minute",INDENT "Minute call") #define TR_BEEPCOUNTDOWN INDENT "Countdown" #define TR_PERSISTENT TR(INDENT "Persist.",INDENT "Persistent") @@ -528,9 +529,9 @@ #define TR_BLONBRIGHTNESS INDENT "ON Brightness" #define TR_BLOFFBRIGHTNESS INDENT "OFF Brightness" #define TR_SPLASHSCREEN "Splash screen" -#define TR_THROTTLEWARNING TR("T-Warning","Throttle Warning") -#define TR_SWITCHWARNING TR("S-Warning","Switch Warning") -#define TR_POTWARNING TR("Pot Warn.","Pot Warning") +#define TR_THROTTLEWARNING TR("T-Warning", INDENT "Throttle State") +#define TR_SWITCHWARNING TR("S-Warning", INDENT "Switch Position") +#define TR_POTWARNING TR("Pot Warn.", INDENT "Pot Setup") #define TR_TIMEZONE TR("Time Zone","GPS Time zone") #define TR_RXCHANNELORD TR("Rx Channel Ord","Default channel order") #define TR_SLAVE "Slave" @@ -725,7 +726,8 @@ #define TR_LOWALARM INDENT "Low Alarm" #define TR_CRITICALALARM INDENT "Critical Alarm" #define TR_PERSISTENT_MAH INDENT "Store mAh" -#define TR_CHECKLIST "Display Checklist" +#define TR_PREFLIGHT "Preflight Checks" +#define TR_CHECKLIST INDENT "Display Checklist" #define TR_FAS_OFFSET TR(INDENT "FAS Ofs", INDENT "FAS Offset") #define TR_UART3MODE "Serial port" diff --git a/radio/src/translations/fr.h.txt b/radio/src/translations/fr.h.txt index b28416cee..828b25b79 100644 --- a/radio/src/translations/fr.h.txt +++ b/radio/src/translations/fr.h.txt @@ -450,8 +450,8 @@ #define TR_ELIMITS TR("Limites ét", "Limites étendues") #define TR_ETRIMS TR("Trims ét.", "Trims étendus") #define TR_TRIMINC TR("Pas Trim", "Pas des trims") -#define TR_TTRACE "Source gaz" -#define TR_TTRIM "Trim gaz" +#define TR_TTRACE TR("Source gaz", INDENT "Source gaz") +#define TR_TTRIM TR("Trim gaz", INDENT "Trim gaz") #define TR_BEEPCTR TR("Bips centr", "Bips centrage") #define TR_PROTO TR(INDENT "Proto.", INDENT "Protocole") #define TR_PPMFRAME INDENT "Trame PPM" @@ -514,7 +514,8 @@ #define TR_MEMORYWARNING INDENT "Mémoire pleine" #define TR_ALARMWARNING TR(INDENT "Silence",INDENT "Sons désactivés") #define TR_RENAVIG "Navig EncRot" -#define TR_THROTTLEREVERSE TR("Inv. gaz","Inversion gaz") +#define TR_THROTTLE_LABEL "Gaz" +#define TR_THROTTLEREVERSE TR("Inv. gaz", INDENT "Inversion gaz") #define TR_MINUTEBEEP TR(INDENT "Bip min.",INDENT "Annonces minutes") #define TR_BEEPCOUNTDOWN TR(INDENT "Bip fin",INDENT "Compte à rebours") #define TR_PERSISTENT TR(INDENT "Persist.",INDENT "Persistant") @@ -523,9 +524,9 @@ #define TR_BLONBRIGHTNESS INDENT "Luminosité ON" #define TR_BLOFFBRIGHTNESS INDENT "Luminosité OFF" #define TR_SPLASHSCREEN "Logo d'accueil" -#define TR_THROTTLEWARNING "Alerte gaz" -#define TR_SWITCHWARNING TR("Alerte int","Alerte interrupt.") -#define TR_POTWARNING TR("Alerte pot","Alerte potentiom.") +#define TR_THROTTLEWARNING TR("Alerte gaz", INDENT "Alerte gaz") +#define TR_SWITCHWARNING TR("Alerte int", INDENT "Alerte interrupt.") +#define TR_POTWARNING TR("Alerte pot", INDENT "Alerte potentiom.") #define TR_TIMEZONE "Fuseau horaire" #define TR_RXCHANNELORD TR("Ordre voies RX","Ordre des voies préféré") #define TR_SLAVE "Elève" @@ -720,7 +721,8 @@ #define TR_LOWALARM INDENT "Alarme basse" #define TR_CRITICALALARM INDENT "Alarme critique" #define TR_PERSISTENT_MAH TR(INDENT "Enr. mAh", INDENT "Enregistrer mAh") -#define TR_CHECKLIST "Afficher notes" +#define TR_PREFLIGHT "Preflight Checks" +#define TR_CHECKLIST INDENT "Afficher notes" #define TR_FAS_OFFSET TR(INDENT "Corr FAS", INDENT "Correction FAS") #define TR_UART3MODE "Port série" From 5b0835cecbbc905e56a43cf7932b611e69fe05f2 Mon Sep 17 00:00:00 2001 From: bsongis Date: Wed, 5 Mar 2014 10:59:52 +0100 Subject: [PATCH 033/285] translations.h/.cpp files splitted into translations.h/.ccp and fonts.h/.cpp --- radio/bootloader/Makefile | 2 +- radio/src/Makefile | 2 +- radio/src/fonts.cpp | 163 +++++++++++++++++++++++++++++++++++++ radio/src/fonts.h | 57 +++++++++++++ radio/src/lcd.cpp | 152 +++++++++++++++++----------------- radio/src/opentx.h | 1 + radio/src/translations.cpp | 128 +---------------------------- radio/src/translations.h | 19 +---- 8 files changed, 306 insertions(+), 218 deletions(-) create mode 100755 radio/src/fonts.cpp create mode 100755 radio/src/fonts.h diff --git a/radio/bootloader/Makefile b/radio/bootloader/Makefile index 9f406db8b..8cee2f3b3 100644 --- a/radio/bootloader/Makefile +++ b/radio/bootloader/Makefile @@ -146,7 +146,7 @@ CPPSRC = ../src/targets/taranis/lcd_driver.cpp \ ../src/targets/taranis/usbd_usr.cpp \ usbd_storage_msd.cpp \ ../src/lcd.cpp \ - ../src/translations.cpp \ + ../src/fonts.cpp \ power.cpp \ boot.cpp diff --git a/radio/src/Makefile b/radio/src/Makefile index b583e8868..cda31aa0f 100644 --- a/radio/src/Makefile +++ b/radio/src/Makefile @@ -742,7 +742,7 @@ else TTS_SRC = $(shell sh -c "if test -f $(STD_TTS_SRC); then echo $(STD_TTS_SRC); else echo translations/tts_en.cpp; fi") endif -CPPSRC += opentx.cpp $(PULSESSRC) stamp.cpp gui/menus.cpp gui/menu_model.cpp gui/menu_general.cpp gui/view_main.cpp gui/view_statistics.cpp $(EEPROMSRC) lcd.cpp keys.cpp maths.cpp translations.cpp $(TTS_SRC) +CPPSRC += opentx.cpp $(PULSESSRC) stamp.cpp gui/menus.cpp gui/menu_model.cpp gui/menu_general.cpp gui/view_main.cpp gui/view_statistics.cpp $(EEPROMSRC) lcd.cpp keys.cpp maths.cpp translations.cpp fonts.cpp $(TTS_SRC) # Debugging format. # Native formats for AVR-GCC's -g are dwarf-2 [default] or stabs. diff --git a/radio/src/fonts.cpp b/radio/src/fonts.cpp new file mode 100755 index 000000000..5c1ec8bc4 --- /dev/null +++ b/radio/src/fonts.cpp @@ -0,0 +1,163 @@ +/* + * Authors (alphabetical order) + * - Andre Bernet + * - Andreas Weitl + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Gabriel Birkus + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * opentx is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "opentx.h" + +const pm_uchar font_5x7[] PROGMEM = { +#if defined (CPUARM) +#include "font_05x07.lbm" +#else +#include "font_05x07_avr.lbm" +#endif +#if defined(TRANSLATIONS_DE) +#include "font_de_05x07.lbm" +#elif defined(TRANSLATIONS_CZ) +#include "font_cz_05x07.lbm" +#elif defined(TRANSLATIONS_ES) +#include "font_es_05x07.lbm" +#elif defined(TRANSLATIONS_FI) +#include "font_fi_05x07.lbm" +#elif defined(TRANSLATIONS_FR) +#include "font_fr_05x07.lbm" +#elif defined(TRANSLATIONS_IT) +#include "font_it_05x07.lbm" +#elif defined(TRANSLATIONS_PL) +#include "font_pl_05x07.lbm" +#elif defined(TRANSLATIONS_PT) +#include "font_pt_05x07.lbm" +#elif defined(TRANSLATIONS_SE) +#include "font_se_05x07.lbm" +#endif +}; + +#if defined(BOLD_FONT) && (!defined(CPUM64) || defined(EXTSTD)) +const pm_uchar font_5x7_B[] PROGMEM = { +#include "font_05x07_B_compressed.lbm" +}; +#endif + +#if !defined(BOOT) +const pm_uchar font_10x14[] PROGMEM = { +#include "font_10x14_compressed.lbm" +#if defined(CPUARM) + #if defined(TRANSLATIONS_DE) + #include "font_de_10x14.lbm" + #elif defined(TRANSLATIONS_CZ) + #include "font_cz_10x14.lbm" + #elif defined(TRANSLATIONS_ES) + #include "font_es_10x14.lbm" + #elif defined(TRANSLATIONS_FI) + #include "font_fi_10x14.lbm" + #elif defined(TRANSLATIONS_FR) + #include "font_fr_10x14.lbm" + #elif defined(TRANSLATIONS_IT) + #include "font_it_10x14.lbm" + #elif defined(TRANSLATIONS_PL) + #include "font_pl_10x14.lbm" + #elif defined(TRANSLATIONS_PT) + #include "font_pt_10x14.lbm" + #elif defined(TRANSLATIONS_SE) + #include "font_se_10x14.lbm" + #endif +#endif +}; +#endif + +#if defined(CPUARM) && !defined(BOOT) +const pm_uchar font_3x5[] PROGMEM = { +#include "font_03x05.lbm" +}; + +const pm_uchar font_4x6[] PROGMEM = { +#include "font_04x06.lbm" +#if defined(TRANSLATIONS_DE) +#include "font_de_04x06.lbm" +#elif defined(TRANSLATIONS_CZ) +#include "font_cz_04x06.lbm" +#elif defined(TRANSLATIONS_ES) +#include "font_es_04x06.lbm" +#elif defined(TRANSLATIONS_FI) +#include "font_fi_04x06.lbm" +#elif defined(TRANSLATIONS_FR) +#include "font_fr_04x06.lbm" +#elif defined(TRANSLATIONS_IT) +#include "font_it_04x06.lbm" +#elif defined(TRANSLATIONS_PL) +#include "font_pl_04x06.lbm" +#elif defined(TRANSLATIONS_PT) +#include "font_pt_04x06.lbm" +#elif defined(TRANSLATIONS_SE) +#include "font_se_04x06.lbm" +#endif +}; + +const pm_uchar font_8x10[] PROGMEM = { +#include "font_08x10.lbm" +#if defined(TRANSLATIONS_DE) +#include "font_de_08x10.lbm" +#elif defined(TRANSLATIONS_CZ) +#include "font_cz_08x10.lbm" +#elif defined(TRANSLATIONS_ES) +#include "font_es_08x10.lbm" +#elif defined(TRANSLATIONS_FI) +#include "font_fi_08x10.lbm" +#elif defined(TRANSLATIONS_FR) +#include "font_fr_08x10.lbm" +#elif defined(TRANSLATIONS_IT) +#include "font_it_08x10.lbm" +#elif defined(TRANSLATIONS_PL) +#include "font_pl_08x10.lbm" +#elif defined(TRANSLATIONS_PT) +#include "font_pt_08x10.lbm" +#elif defined(TRANSLATIONS_SE) +#include "font_se_08x10.lbm" +#endif +}; + +const pm_uchar font_4x6_extra[] PROGMEM = { +#include "font_04x06_extra.lbm" +}; + +const pm_uchar font_5x7_extra[] PROGMEM = { +#include "font_05x07_extra.lbm" +}; + +const pm_uchar font_10x14_extra[] PROGMEM = { +#include "font_10x14_extra.lbm" +}; + +#endif + diff --git a/radio/src/fonts.h b/radio/src/fonts.h new file mode 100755 index 000000000..f254800dc --- /dev/null +++ b/radio/src/fonts.h @@ -0,0 +1,57 @@ +/* + * Authors (alphabetical order) + * - Andre Bernet + * - Andreas Weitl + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Gabriel Birkus + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * opentx is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef fonts_h +#define fonts_h + +extern const pm_uchar font_5x7[]; +extern const pm_uchar font_10x14[]; + +#if defined(BOLD_FONT) && (!defined(CPUM64) || defined(EXTSTD)) && !defined(BOOT) + #define BOLD_SPECIFIC_FONT + extern const pm_uchar font_5x7_B[]; +#endif + +#if defined(CPUARM) +extern const pm_uchar font_3x5[]; +extern const pm_uchar font_4x6[]; +extern const pm_uchar font_8x10[]; +extern const pm_uchar font_5x7_extra[]; +extern const pm_uchar font_10x14_extra[]; +extern const pm_uchar font_4x6_extra[]; +#endif + +#endif diff --git a/radio/src/lcd.cpp b/radio/src/lcd.cpp index f65811a0a..51793bed7 100644 --- a/radio/src/lcd.cpp +++ b/radio/src/lcd.cpp @@ -49,44 +49,6 @@ void lcd_clear() memset(displayBuf, 0, sizeof(displayBuf)); } -#if !defined(BOOT) -void lcd_img(xcoord_t x, uint8_t y, const pm_uchar * img, uint8_t idx, LcdFlags att) -{ - const pm_uchar *q = img; -#if LCD_W >= 260 - xcoord_t w = pgm_read_byte(q++); - if (w == 255) w += pgm_read_byte(q++); -#else - uint8_t w = pgm_read_byte(q++); -#endif - uint8_t hb = (pgm_read_byte(q++)+7)/8; - bool inv = (att & INVERS) ? true : (att & BLINK ? BLINK_ON_PHASE : false); - q += idx*w*hb; - for (uint8_t yb = 0; yb < hb; yb++) { - uint8_t *p = &displayBuf[ (y / 8 + yb) * LCD_W + x ]; - for (xcoord_t i=0; i> (8-ym8)); } -#if defined(PCBTARANIS) && !defined(BOOT) +#if defined(PCBTARANIS) if (inv) { if (ym8) lcd_mask(p, 0x01 << (ym8-1), FORCE); else if (y) { @@ -354,13 +321,6 @@ void lcd_putc(xcoord_t x, uint8_t y, const unsigned char c) lcd_putcAtt(x, y, c, 0); } -void lcd_putsiAtt(xcoord_t x, uint8_t y,const pm_char * s,uint8_t idx, LcdFlags flags) -{ - uint8_t length; - length = pgm_read_byte(s++); - lcd_putsnAtt(x,y,s+length*idx,length,flags & ~(BSS|ZCHAR)); -} - void lcd_putsnAtt(xcoord_t x, uint8_t y, const pm_char * s, uint8_t len, LcdFlags mode) { xcoord_t orig_x = x; @@ -440,6 +400,14 @@ void lcd_putsLeft(uint8_t y, const pm_char * s) lcd_puts(0, y, s); } +#if !defined(BOOT) +void lcd_putsiAtt(xcoord_t x, uint8_t y,const pm_char * s,uint8_t idx, LcdFlags flags) +{ + uint8_t length; + length = pgm_read_byte(s++); + lcd_putsnAtt(x,y,s+length*idx,length,flags & ~(BSS|ZCHAR)); +} + void lcd_outhex4(xcoord_t x, uint8_t y, uint16_t val) { x+=FWNUM*4+1; @@ -596,6 +564,7 @@ void lcd_outdezNAtt(xcoord_t x, uint8_t y, lcdint_t val, LcdFlags flags, uint8_t } if (neg) lcd_putcAtt(x, y, '-', flags); } +#endif #if defined(PCBTARANIS) void lcd_mask(uint8_t *p, uint8_t mask, LcdFlags att) @@ -817,6 +786,21 @@ void lcd_vline(xcoord_t x, int8_t y, int8_t h) lcd_vlineStip(x, y, h, 0xff); } +void lcd_invert_line(int8_t y) +{ + uint8_t *p = &displayBuf[y * LCD_W]; + for (xcoord_t x=0; x= 260 + xcoord_t w = pgm_read_byte(q++); + if (w == 255) w += pgm_read_byte(q++); +#else + uint8_t w = pgm_read_byte(q++); +#endif + uint8_t hb = (pgm_read_byte(q++)+7)/8; + bool inv = (att & INVERS) ? true : (att & BLINK ? BLINK_ON_PHASE : false); + q += idx*w*hb; + for (uint8_t yb = 0; yb < hb; yb++) { + uint8_t *p = &displayBuf[ (y / 8 + yb) * LCD_W + x ]; + for (xcoord_t i=0; i= 212 - #define TR(x,y) y + #define TR(x, y) y #else - #define TR(x,y) x + #define TR(x, y) x #endif // The non-0-terminated-strings @@ -547,21 +547,6 @@ extern const pm_char STR_RESET_BTN[]; #define STR_UPDATE_LIST STR_DELAYDOWN #endif -extern const pm_uchar font_5x7[]; -extern const pm_uchar font_10x14[]; -#if !defined(CPUM64) || defined(EXTSTD) -extern const pm_uchar font_5x7_B[]; -#endif - -#if defined(CPUARM) -extern const pm_uchar font_3x5[]; -extern const pm_uchar font_4x6[]; -extern const pm_uchar font_8x10[]; -extern const pm_uchar font_5x7_extra[]; -extern const pm_uchar font_10x14_extra[]; -extern const pm_uchar font_4x6_extra[]; -#endif - extern const pm_char STR_WARNING[]; extern const pm_char STR_EEPROMWARN[]; extern const pm_char STR_THROTTLEWARN[]; From 55349d46da307c81e5bff341d5e1d492776f72b4 Mon Sep 17 00:00:00 2001 From: bsongis Date: Wed, 5 Mar 2014 11:45:57 +0100 Subject: [PATCH 034/285] 5 more files removed --- radio/bootloader/Makefile | 2 +- radio/bootloader/boot.cpp | 5 +- radio/bootloader/ff.cpp | 3822 ------------------------- radio/bootloader/ff_lfn.cpp | 113 - radio/bootloader/include/diskio.h | 176 -- radio/bootloader/include/ff.h | 575 ---- radio/bootloader/include/ffconf.h | 231 -- radio/bootloader/usbd_storage_msd.cpp | 6 +- radio/src/FatFs/ffconf.h | 16 +- radio/src/targets/taranis/diskio.cpp | 11 +- 10 files changed, 22 insertions(+), 4935 deletions(-) delete mode 100644 radio/bootloader/ff.cpp delete mode 100644 radio/bootloader/ff_lfn.cpp delete mode 100644 radio/bootloader/include/diskio.h delete mode 100644 radio/bootloader/include/ff.h delete mode 100644 radio/bootloader/include/ffconf.h diff --git a/radio/bootloader/Makefile b/radio/bootloader/Makefile index 8cee2f3b3..a458568b0 100644 --- a/radio/bootloader/Makefile +++ b/radio/bootloader/Makefile @@ -123,6 +123,7 @@ SRC = system_stm32f2xx.c \ ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_gpio.c \ ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_spi.c \ ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/misc.c \ + ../src/FatFs/ff.c \ ../src/FatFs/option/ccsbcs.c \ ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/src/usb_core.c \ ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/src/usb_dcd.c \ @@ -141,7 +142,6 @@ SRC = system_stm32f2xx.c \ CPPSRC = ../src/targets/taranis/lcd_driver.cpp \ driversboot.cpp \ logicioboot.cpp \ - ff.cpp \ ../src/targets/taranis/diskio.cpp \ ../src/targets/taranis/usbd_usr.cpp \ usbd_storage_msd.cpp \ diff --git a/radio/bootloader/boot.cpp b/radio/bootloader/boot.cpp index b8a186455..479208ed2 100644 --- a/radio/bootloader/boot.cpp +++ b/radio/bootloader/boot.cpp @@ -79,9 +79,8 @@ extern "C" { #include "../src/lcd.h" #include "radio.h" -// #include "lcd.h" -#include "ff.h" -#include "diskio.h" +#include "../src/FatFs/ff.h" +#include "../src/FatFs/diskio.h" #include "drivers.h" #include "logicio.h" diff --git a/radio/bootloader/ff.cpp b/radio/bootloader/ff.cpp deleted file mode 100644 index 38102103b..000000000 --- a/radio/bootloader/ff.cpp +++ /dev/null @@ -1,3822 +0,0 @@ -/* - * Authors (alphabetical order) - * - Bertrand Songis - * - Bryan J. Rentoul (Gruvin) - * - Cameron Weeks - * - Erez Raviv - * - Jean-Pierre Parisy - * - Karl Szmutny - * - Michael Blandford - * - Michal Hlavinka - * - Pat Mackenzie - * - Philip Moss - * - Rob Thomson - * - Romolo Manfredini - * - Thomas Husterer - * - * open9x is based on code named - * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, - * er9x by Erez Raviv: http://code.google.com/p/er9x/, - * and the original (and ongoing) project by - * Thomas Husterer, th9x: http://code.google.com/p/th9x/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/*----------------------------------------------------------------------------/ -/ FatFs - FAT file system module R0.08a (C)ChaN, 2010 -/-----------------------------------------------------------------------------/ -/ FatFs module is a generic FAT file system module for small embedded systems. -/ This is a free software that opened for education, research and commercial -/ developments under license policy of following terms. -/ -/ Copyright (C) 2010, ChaN, all right reserved. -/ -/ * The FatFs module is a free software and there is NO WARRANTY. -/ * No restriction on use. You can use, modify and redistribute it for -/ personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY. -/ * Redistributions of source code must retain the above copyright notice. -/ -/-----------------------------------------------------------------------------/ -/ Feb 26,'06 R0.00 Prototype. -/ -/ Apr 29,'06 R0.01 First stable version. -/ -/ Jun 01,'06 R0.02 Added FAT12 support. -/ Removed unbuffered mode. -/ Fixed a problem on small (<32M) partition. -/ Jun 10,'06 R0.02a Added a configuration option (_FS_MINIMUM). -/ -/ Sep 22,'06 R0.03 Added f_rename(). -/ Changed option _FS_MINIMUM to _FS_MINIMIZE. -/ Dec 11,'06 R0.03a Improved cluster scan algorithm to write files fast. -/ Fixed f_mkdir() creates incorrect directory on FAT32. -/ -/ Feb 04,'07 R0.04 Supported multiple drive system. -/ Changed some interfaces for multiple drive system. -/ Changed f_mountdrv() to f_mount(). -/ Added f_mkfs(). -/ Apr 01,'07 R0.04a Supported multiple partitions on a physical drive. -/ Added a capability of extending file size to f_lseek(). -/ Added minimization level 3. -/ Fixed an endian sensitive code in f_mkfs(). -/ May 05,'07 R0.04b Added a configuration option _USE_NTFLAG. -/ Added FSInfo support. -/ Fixed DBCS name can result FR_INVALID_NAME. -/ Fixed short seek (<= csize) collapses the file object. -/ -/ Aug 25,'07 R0.05 Changed arguments of f_read(), f_write() and f_mkfs(). -/ Fixed f_mkfs() on FAT32 creates incorrect FSInfo. -/ Fixed f_mkdir() on FAT32 creates incorrect directory. -/ Feb 03,'08 R0.05a Added f_truncate() and f_utime(). -/ Fixed off by one error at FAT sub-type determination. -/ Fixed btr in f_read() can be mistruncated. -/ Fixed cached sector is not flushed when create and close without write. -/ -/ Apr 01,'08 R0.06 Added fputc(), fputs(), fprintf() and fgets(). -/ Improved performance of f_lseek() on moving to the same or following cluster. -/ -/ Apr 01,'09 R0.07 Merged Tiny-FatFs as a buffer configuration option. (_FS_TINY) -/ Added long file name support. -/ Added multiple code page support. -/ Added re-entrancy for multitask operation. -/ Added auto cluster size selection to f_mkfs(). -/ Added rewind option to f_readdir(). -/ Changed result code of critical errors. -/ Renamed string functions to avoid name collision. -/ Apr 14,'09 R0.07a Separated out OS dependent code on reentrant cfg. -/ Added multiple sector size support. -/ Jun 21,'09 R0.07c Fixed f_unlink() can return FR_OK on error. -/ Fixed wrong cache control in f_lseek(). -/ Added relative path feature. -/ Added f_chdir() and f_chdrive(). -/ Added proper case conversion to extended char. -/ Nov 03,'09 R0.07e Separated out configuration options from ff.h to ffconf.h. -/ Fixed f_unlink() fails to remove a sub-dir on _FS_RPATH. -/ Fixed name matching error on the 13 char boundary. -/ Added a configuration option, _LFN_UNICODE. -/ Changed f_readdir() to return the SFN with always upper case on non-LFN cfg. -/ -/ May 15,'10 R0.08 Added a memory configuration option. (_USE_LFN = 3) -/ Added file lock feature. (_FS_SHARE) -/ Added fast seek feature. (_USE_FASTSEEK) -/ Changed some types on the API, XCHAR->TCHAR. -/ Changed fname member in the FILINFO structure on Unicode cfg. -/ String functions support UTF-8 encoding files on Unicode cfg. -/ Aug 16,'10 R0.08a Added f_getcwd(). (_FS_RPATH = 2) -/ Added sector erase feature. (_USE_ERASE) -/ Moved file lock semaphore table from fs object to the bss. -/ Fixed a wrong directory entry is created on non-LFN cfg when the given name contains ';'. -/ Fixed f_mkfs() creates wrong FAT32 volume. -/---------------------------------------------------------------------------*/ - -#include "ff.h" /* FatFs configurations and declarations */ -#include "diskio.h" /* Declarations of low level disk I/O functions */ -#include "gtime.h" - -/*-------------------------------------------------------------------------- - - Module Private Definitions - ----------------------------------------------------------------------------*/ - -#if _FATFS != 8255 -#error Wrong include file (ff.h). -#endif - - -/* Definitions on sector size */ -#if _MAX_SS != 512 && _MAX_SS != 1024 && _MAX_SS != 2048 && _MAX_SS != 4096 -#error Wrong sector size. -#endif -#if _MAX_SS != 512 -#define SS(fs) ((fs)->ssize) /* Multiple sector size */ -#else -#define SS(fs) 512U /* Fixed sector size */ -#endif - - -/* Reentrancy related */ -#if _FS_REENTRANT -#if _USE_LFN == 1 -#error Static LFN work area must not be used in re-entrant configuration. -#endif -#define ENTER_FF(fs) { if (!lock_fs(fs)) return FR_TIMEOUT; } -#define LEAVE_FF(fs, res) { unlock_fs(fs, res); return res; } -#else -#define ENTER_FF(fs) -#define LEAVE_FF(fs, res) return res -#endif - -#define ABORT(fs, res) { fp->flag |= FA__ERROR; LEAVE_FF(fs, res); } - - -/* File shareing feature */ -#if _FS_SHARE -#if _FS_READONLY -#error _FS_SHARE must be 0 on read-only cfg. -#endif -typedef struct { - FATFS *fs; /* File ID 1, volume (NULL:blank entry) */ - DWORD clu; /* File ID 2, directory */ - WORD idx; /* File ID 3, directory index */ - WORD ctr; /* File open counter, 0:none, 0x01..0xFF:read open count, 0x100:write mode */ -} FILESEM; -#endif - - -/* Misc definitions */ -#define LD_CLUST(dir) (((DWORD)LD_WORD(dir+DIR_FstClusHI)<<16) | LD_WORD(dir+DIR_FstClusLO)) -#define ST_CLUST(dir,cl) {ST_WORD(dir+DIR_FstClusLO, cl); ST_WORD(dir+DIR_FstClusHI, (DWORD)cl>>16);} - - -/* Character code support macros */ -#define IsUpper(c) (((c)>='A')&&((c)<='Z')) -#define IsLower(c) (((c)>='a')&&((c)<='z')) -#define IsDigit(c) (((c)>='0')&&((c)<='9')) - -#if _DF1S /* Code page is DBCS */ - -#ifdef _DF2S /* Two 1st byte areas */ -#define IsDBCS1(c) (((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E)) -#else /* One 1st byte area */ -#define IsDBCS1(c) ((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) -#endif - -#ifdef _DS3S /* Three 2nd byte areas */ -#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E)) -#else /* Two 2nd byte areas */ -#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E)) -#endif - -#else /* Code page is SBCS */ - -#define IsDBCS1(c) 0 -#define IsDBCS2(c) 0 - -#endif /* _DF1S */ - - -/* Name status flags */ -#define NS 11 /* Offset of name status byte */ -#define NS_LOSS 0x01 /* Out of 8.3 format */ -#define NS_LFN 0x02 /* Force to create LFN entry */ -#define NS_LAST 0x04 /* Last segment */ -#define NS_BODY 0x08 /* Lower case flag (body) */ -#define NS_EXT 0x10 /* Lower case flag (ext) */ -#define NS_DOT 0x20 /* Dot entry */ - - -/* FAT sub-type boundaries */ -/* Note that the FAT spec by Microsoft says 4085 but Windows works with 4087! */ -#define MIN_FAT16 4086 /* Minimum number of clusters for FAT16 */ -#define MIN_FAT32 65526 /* Minimum number of clusters for FAT32 */ - - -/* FatFs refers the members in the FAT structures as byte array instead of -/ structure member because there are incompatibility of the packing option -/ between compilers. */ - -#define BS_jmpBoot 0 -#define BS_OEMName 3 -#define BPB_BytsPerSec 11 -#define BPB_SecPerClus 13 -#define BPB_RsvdSecCnt 14 -#define BPB_NumFATs 16 -#define BPB_RootEntCnt 17 -#define BPB_TotSec16 19 -#define BPB_Media 21 -#define BPB_FATSz16 22 -#define BPB_SecPerTrk 24 -#define BPB_NumHeads 26 -#define BPB_HiddSec 28 -#define BPB_TotSec32 32 -#define BS_DrvNum 36 -#define BS_BootSig 38 -#define BS_VolID 39 -#define BS_VolLab 43 -#define BS_FilSysType 54 -#define BPB_FATSz32 36 -#define BPB_ExtFlags 40 -#define BPB_FSVer 42 -#define BPB_RootClus 44 -#define BPB_FSInfo 48 -#define BPB_BkBootSec 50 -#define BS_DrvNum32 64 -#define BS_BootSig32 66 -#define BS_VolID32 67 -#define BS_VolLab32 71 -#define BS_FilSysType32 82 -#define FSI_LeadSig 0 -#define FSI_StrucSig 484 -#define FSI_Free_Count 488 -#define FSI_Nxt_Free 492 -#define MBR_Table 446 -#define BS_55AA 510 - -#define DIR_Name 0 -#define DIR_Attr 11 -#define DIR_NTres 12 -#define DIR_CrtTime 14 -#define DIR_CrtDate 16 -#define DIR_FstClusHI 20 -#define DIR_WrtTime 22 -#define DIR_WrtDate 24 -#define DIR_FstClusLO 26 -#define DIR_FileSize 28 -#define LDIR_Ord 0 -#define LDIR_Attr 11 -#define LDIR_Type 12 -#define LDIR_Chksum 13 -#define LDIR_FstClusLO 26 - - - -/*------------------------------------------------------------*/ -/* Work area */ - -#if _VOLUMES -static -FATFS *FatFs[_VOLUMES]; /* Pointer to the file system objects (logical drives) */ -#else -#error Number of drives must not be 0. -#endif - -static -WORD Fsid; /* File system mount ID */ - -#if _FS_RPATH -static -BYTE CurrVol; /* Current drive */ -#endif - -#if _FS_SHARE -static -FILESEM Files[_FS_SHARE]; /* File lock semaphores */ -#endif - -#if _USE_LFN == 0 /* No LFN */ -#define DEF_NAMEBUF BYTE sfn[12] -#define INIT_BUF(dobj) (dobj).fn = sfn -#define FREE_BUF() - -#elif _USE_LFN == 1 /* LFN with static LFN working buffer */ -static WCHAR LfnBuf[_MAX_LFN+1]; -#define DEF_NAMEBUF BYTE sfn[12] -#define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = LfnBuf; } -#define FREE_BUF() - -#elif _USE_LFN == 2 /* LFN with dynamic LFN working buffer on the stack */ -#define DEF_NAMEBUF BYTE sfn[12]; WCHAR lbuf[_MAX_LFN+1] -#define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = lbuf; } -#define FREE_BUF() - -#elif _USE_LFN == 3 /* LFN with dynamic LFN working buffer on the heap */ -#define DEF_NAMEBUF BYTE sfn[12]; WCHAR *lfn -#define INIT_BUF(dobj) { lfn = ff_memalloc((_MAX_LFN + 1) * 2); \ - if (!lfn) LEAVE_FF((dobj).fs, FR_NOT_ENOUGH_CORE); \ - (dobj).lfn = lfn; (dobj).fn = sfn; } -#define FREE_BUF() ff_memfree(lfn) - -#else -#error Wrong LFN configuration. -#endif - - - - -/*-------------------------------------------------------------------------- - - Module Private Functions - ----------------------------------------------------------------------------*/ - - -/*-----------------------------------------------------------------------*/ -/* String functions */ -/*-----------------------------------------------------------------------*/ - -/* Copy memory to memory */ -static -void mem_cpy (void* dst, const void* src, UINT cnt) { - BYTE *d = (BYTE*)dst; - const BYTE *s = (const BYTE*)src; - -#if _WORD_ACCESS == 1 - while (cnt >= sizeof(int)) { - *(int*)d = *(int*)s; - d += sizeof(int); s += sizeof(int); - cnt -= sizeof(int); - } -#endif - while (cnt--) - *d++ = *s++; -} - -/* Fill memory */ -static -void mem_set (void* dst, int val, UINT cnt) { - BYTE *d = (BYTE*)dst; - - while (cnt--) - *d++ = (BYTE)val; -} - -/* Compare memory to memory */ -static -int mem_cmp (const void* dst, const void* src, UINT cnt) { - const BYTE *d = (const BYTE *)dst, *s = (const BYTE *)src; - int r = 0; - - while (cnt-- && (r = *d++ - *s++) == 0) ; - return r; -} - -/* Check if chr is contained in the string */ -static -int chk_chr (const char* str, int chr) { - while (*str && *str != chr) str++; - return *str; -} - - - -/*-----------------------------------------------------------------------*/ -/* Request/Release grant to access the volume */ -/*-----------------------------------------------------------------------*/ -#if _FS_REENTRANT - -static -int lock_fs ( - FATFS *fs /* File system object */ -) -{ - return ff_req_grant(fs->sobj); -} - - -static -void unlock_fs ( - FATFS *fs, /* File system object */ - FRESULT res /* Result code to be returned */ -) -{ - if (fs && - res != FR_NOT_ENABLED && - res != FR_INVALID_DRIVE && - res != FR_INVALID_OBJECT && - res != FR_TIMEOUT) { - ff_rel_grant(fs->sobj); - } -} -#endif - - - -/*-----------------------------------------------------------------------*/ -/* File shareing control functions */ -/*-----------------------------------------------------------------------*/ -#if _FS_SHARE - -static -FRESULT chk_lock ( /* Check if the file can be accessed */ - DIR* dj, /* Directory object pointing the file to be checked */ - int acc /* Desired access (0:Read, 1:Write, 2:Delete/Rename) */ -) -{ - UINT i, be; - - /* Search file semaphore table */ - for (i = be = 0; i < _FS_SHARE; i++) { - if (Files[i].fs) { /* Existing entry */ - if (Files[i].fs == dj->fs && /* Check if the file matched with an open file */ - Files[i].clu == dj->sclust && - Files[i].idx == dj->index) break; - } else { /* Blank entry */ - be++; - } - } - if (i == _FS_SHARE) /* The file is not opened */ - return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES; /* Is there a blank entry for new file? */ - - /* The file has been opened. Reject any open against writing file and all write mode open */ - return (acc || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK; -} - - -static -int enq_lock ( /* Check if an entry is available for a new file */ - FATFS* fs /* File system object */ -) -{ - UINT i; - - for (i = 0; i < _FS_SHARE && Files[i].fs; i++) ; - return (i == _FS_SHARE) ? 0 : 1; -} - - -static -UINT inc_lock ( /* Increment file open counter and returns its index (0:int error) */ - DIR* dj, /* Directory object pointing the file to register or increment */ - int acc /* Desired access mode (0:Read, !0:Write) */ -) -{ - UINT i; - - - for (i = 0; i < _FS_SHARE; i++) { /* Find the file */ - if (Files[i].fs == dj->fs && - Files[i].clu == dj->sclust && - Files[i].idx == dj->index) break; - } - - if (i == _FS_SHARE) { /* Not opened. Register it as new. */ - for (i = 0; i < _FS_SHARE && Files[i].fs; i++) ; - if (i == _FS_SHARE) return 0; /* No space to register (int err) */ - Files[i].fs = dj->fs; - Files[i].clu = dj->sclust; - Files[i].idx = dj->index; - Files[i].ctr = 0; - } - - if (acc && Files[i].ctr) return 0; /* Access violation (int err) */ - - Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1; /* Set semaphore value */ - - return i + 1; -} - - -static -FRESULT dec_lock ( /* Decrement file open counter */ - UINT i /* Semaphore index */ -) -{ - WORD n; - FRESULT res; - - - if (--i < _FS_SHARE) { - n = Files[i].ctr; - if (n == 0x100) n = 0; - if (n) n--; - Files[i].ctr = n; - if (!n) Files[i].fs = 0; - res = FR_OK; - } else { - res = FR_INT_ERR; - } - return res; -} - - -static -void clear_lock ( /* Clear lock entries of the volume */ - FATFS *fs -) -{ - UINT i; - - for (i = 0; i < _FS_SHARE; i++) { - if (Files[i].fs == fs) Files[i].fs = 0; - } -} -#endif - - - -/*-----------------------------------------------------------------------*/ -/* Change window offset */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT move_window ( - FATFS *fs, /* File system object */ - DWORD sector /* Sector number to make appearance in the fs->win[] */ -) /* Move to zero only writes back dirty window */ -{ - DWORD wsect; - - - wsect = fs->winsect; - if (wsect != sector) { /* Changed current window */ -#if !_FS_READONLY - if (fs->wflag) { /* Write back dirty window if needed */ - if (disk_write(fs->drv, fs->win, wsect, 1) != RES_OK) - return FR_DISK_ERR; - fs->wflag = 0; - if (wsect < (fs->fatbase + fs->fsize)) { /* In FAT area */ - BYTE nf; - for (nf = fs->n_fats; nf > 1; nf--) { /* Reflect the change to all FAT copies */ - wsect += fs->fsize; - disk_write(fs->drv, fs->win, wsect, 1); - } - } - } -#endif - if (sector) { - if (disk_read(fs->drv, fs->win, sector, 1) != RES_OK) - return FR_DISK_ERR; - fs->winsect = sector; - } - } - - return FR_OK; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Clean-up cached data */ -/*-----------------------------------------------------------------------*/ -#if !_FS_READONLY -static -FRESULT sync ( /* FR_OK: successful, FR_DISK_ERR: failed */ - FATFS *fs /* File system object */ -) -{ - FRESULT res; - - - res = move_window(fs, 0); - if (res == FR_OK) { - /* Update FSInfo sector if needed */ - if (fs->fs_type == FS_FAT32 && fs->fsi_flag) { - fs->winsect = 0; - mem_set(fs->win, 0, 512); - ST_WORD(fs->win+BS_55AA, 0xAA55); - ST_DWORD(fs->win+FSI_LeadSig, 0x41615252); - ST_DWORD(fs->win+FSI_StrucSig, 0x61417272); - ST_DWORD(fs->win+FSI_Free_Count, fs->free_clust); - ST_DWORD(fs->win+FSI_Nxt_Free, fs->last_clust); - disk_write(fs->drv, fs->win, fs->fsi_sector, 1); - fs->fsi_flag = 0; - } - /* Make sure that no pending write process in the physical drive */ - if (disk_ioctl(fs->drv, CTRL_SYNC, (BYTE*)0) != RES_OK) - res = FR_DISK_ERR; - } - - return res; -} -#endif - - - - -/*-----------------------------------------------------------------------*/ -/* Get sector# from cluster# */ -/*-----------------------------------------------------------------------*/ - - -DWORD clust2sect ( /* !=0: Sector number, 0: Failed - invalid cluster# */ - FATFS *fs, /* File system object */ - DWORD clst /* Cluster# to be converted */ -) -{ - clst -= 2; - if (clst >= (fs->n_fatent - 2)) return 0; /* Invalid cluster# */ - return clst * fs->csize + fs->database; -} - - - - -/*-----------------------------------------------------------------------*/ -/* FAT access - Read value of a FAT entry */ -/*-----------------------------------------------------------------------*/ - - -DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, Else:Cluster status */ - FATFS *fs, /* File system object */ - DWORD clst /* Cluster# to get the link information */ -) -{ - UINT wc, bc; - BYTE *p; - - - if (clst < 2 || clst >= fs->n_fatent) /* Check range */ - return 1; - - switch (fs->fs_type) { - case FS_FAT12 : - bc = (UINT)clst; bc += bc / 2; - if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break; - wc = fs->win[bc % SS(fs)]; bc++; - if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break; - wc |= fs->win[bc % SS(fs)] << 8; - return (clst & 1) ? (wc >> 4) : (wc & 0xFFF); - - case FS_FAT16 : - if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)))) break; - p = &fs->win[clst * 2 % SS(fs)]; - return LD_WORD(p); - - case FS_FAT32 : - if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)))) break; - p = &fs->win[clst * 4 % SS(fs)]; - return LD_DWORD(p) & 0x0FFFFFFF; - } - - return 0xFFFFFFFF; /* An error occurred at the disk I/O layer */ -} - - - - -/*-----------------------------------------------------------------------*/ -/* FAT access - Change value of a FAT entry */ -/*-----------------------------------------------------------------------*/ -#if !_FS_READONLY - -FRESULT put_fat ( - FATFS *fs, /* File system object */ - DWORD clst, /* Cluster# to be changed in range of 2 to fs->n_fatent - 1 */ - DWORD val /* New value to mark the cluster */ -) -{ - UINT bc; - BYTE *p; - FRESULT res; - - - if (clst < 2 || clst >= fs->n_fatent) { /* Check range */ - res = FR_INT_ERR; - - } else { - switch (fs->fs_type) { - case FS_FAT12 : - bc = clst; bc += bc / 2; - res = move_window(fs, fs->fatbase + (bc / SS(fs))); - if (res != FR_OK) break; - p = &fs->win[bc % SS(fs)]; - *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; - bc++; - fs->wflag = 1; - res = move_window(fs, fs->fatbase + (bc / SS(fs))); - if (res != FR_OK) break; - p = &fs->win[bc % SS(fs)]; - *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F)); - break; - - case FS_FAT16 : - res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))); - if (res != FR_OK) break; - p = &fs->win[clst * 2 % SS(fs)]; - ST_WORD(p, (WORD)val); - break; - - case FS_FAT32 : - res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))); - if (res != FR_OK) break; - p = &fs->win[clst * 4 % SS(fs)]; - val |= LD_DWORD(p) & 0xF0000000; - ST_DWORD(p, val); - break; - - default : - res = FR_INT_ERR; - } - fs->wflag = 1; - } - - return res; -} -#endif /* !_FS_READONLY */ - - - - -/*-----------------------------------------------------------------------*/ -/* FAT handling - Remove a cluster chain */ -/*-----------------------------------------------------------------------*/ -#if !_FS_READONLY -static -FRESULT remove_chain ( - FATFS *fs, /* File system object */ - DWORD clst /* Cluster# to remove a chain from */ -) -{ - FRESULT res; - DWORD nxt; -#if _USE_ERASE - DWORD scl = clst, ecl = clst, resion[2]; -#endif - - if (clst < 2 || clst >= fs->n_fatent) { /* Check range */ - res = FR_INT_ERR; - - } else { - res = FR_OK; - while (clst < fs->n_fatent) { /* Not a last link? */ - nxt = get_fat(fs, clst); /* Get cluster status */ - if (nxt == 0) break; /* Empty cluster? */ - if (nxt == 1) { res = FR_INT_ERR; break; } /* Internal error? */ - if (nxt == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } /* Disk error? */ - res = put_fat(fs, clst, 0); /* Mark the cluster "empty" */ - if (res != FR_OK) break; - if (fs->free_clust != 0xFFFFFFFF) { /* Update FSInfo */ - fs->free_clust++; - fs->fsi_flag = 1; - } -#if _USE_ERASE - if (ecl + 1 == nxt) { /* Next cluster is contiguous */ - ecl = nxt; - } else { /* End of contiguous clusters */ - resion[0] = clust2sect(fs, scl); /* Start sector */ - resion[1] = clust2sect(fs, ecl) + fs->csize - 1; /* End sector */ - disk_ioctl(fs->drv, CTRL_ERASE_SECTOR, resion); /* Erase the block */ - scl = ecl = nxt; - } -#endif - clst = nxt; /* Next cluster */ - } - } - - return res; -} -#endif - - - - -/*-----------------------------------------------------------------------*/ -/* FAT handling - Stretch or Create a cluster chain */ -/*-----------------------------------------------------------------------*/ -#if !_FS_READONLY -static -DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */ - FATFS *fs, /* File system object */ - DWORD clst /* Cluster# to stretch. 0 means create a new chain. */ -) -{ - DWORD cs, ncl, scl; - FRESULT res; - - - if (clst == 0) { /* Create a new chain */ - scl = fs->last_clust; /* Get suggested start point */ - if (!scl || scl >= fs->n_fatent) scl = 1; - } - else { /* Stretch the current chain */ - cs = get_fat(fs, clst); /* Check the cluster status */ - if (cs < 2) return 1; /* It is an invalid cluster */ - if (cs < fs->n_fatent) return cs; /* It is already followed by next cluster */ - scl = clst; - } - - ncl = scl; /* Start cluster */ - for (;;) { - ncl++; /* Next cluster */ - if (ncl >= fs->n_fatent) { /* Wrap around */ - ncl = 2; - if (ncl > scl) return 0; /* No free cluster */ - } - cs = get_fat(fs, ncl); /* Get the cluster status */ - if (cs == 0) break; /* Found a free cluster */ - if (cs == 0xFFFFFFFF || cs == 1)/* An error occurred */ - return cs; - if (ncl == scl) return 0; /* No free cluster */ - } - - res = put_fat(fs, ncl, 0x0FFFFFFF); /* Mark the new cluster "last link" */ - if (res == FR_OK && clst != 0) { - res = put_fat(fs, clst, ncl); /* Link it to the previous one if needed */ - } - if (res == FR_OK) { - fs->last_clust = ncl; /* Update FSINFO */ - if (fs->free_clust != 0xFFFFFFFF) { - fs->free_clust--; - fs->fsi_flag = 1; - } - } else { - ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1; - } - - return ncl; /* Return new cluster number or error code */ -} -#endif /* !_FS_READONLY */ - - - - -/*-----------------------------------------------------------------------*/ -/* Directory handling - Set directory index */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT dir_sdi ( - DIR *dj, /* Pointer to directory object */ - WORD idx /* Directory index number */ -) -{ - DWORD clst; - WORD ic; - - - dj->index = idx; - clst = dj->sclust; - if (clst == 1 || clst >= dj->fs->n_fatent) /* Check start cluster range */ - return FR_INT_ERR; - if (!clst && dj->fs->fs_type == FS_FAT32) /* Replace cluster# 0 with root cluster# if in FAT32 */ - clst = dj->fs->dirbase; - - if (clst == 0) { /* Static table (root-dir in FAT12/16) */ - dj->clust = clst; - if (idx >= dj->fs->n_rootdir) /* Index is out of range */ - return FR_INT_ERR; - dj->sect = dj->fs->dirbase + idx / (SS(dj->fs) / 32); /* Sector# */ - } - else { /* Dynamic table (sub-dirs or root-dir in FAT32) */ - ic = SS(dj->fs) / 32 * dj->fs->csize; /* Entries per cluster */ - while (idx >= ic) { /* Follow cluster chain */ - clst = get_fat(dj->fs, clst); /* Get next cluster */ - if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ - if (clst < 2 || clst >= dj->fs->n_fatent) /* Reached to end of table or int error */ - return FR_INT_ERR; - idx -= ic; - } - dj->clust = clst; - dj->sect = clust2sect(dj->fs, clst) + idx / (SS(dj->fs) / 32); /* Sector# */ - } - - dj->dir = dj->fs->win + (idx % (SS(dj->fs) / 32)) * 32; /* Ptr to the entry in the sector */ - - return FR_OK; /* Seek succeeded */ -} - - - - -/*-----------------------------------------------------------------------*/ -/* Directory handling - Move directory index next */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT dir_next ( /* FR_OK:Succeeded, FR_NO_FILE:End of table, FR_DENIED:EOT and could not stretch */ - DIR *dj, /* Pointer to directory object */ - int stretch /* 0: Do not stretch table, 1: Stretch table if needed */ -) -{ - DWORD clst; - WORD i; - - - i = dj->index + 1; - if (!i || !dj->sect) /* Report EOT when index has reached 65535 */ - return FR_NO_FILE; - - if (!(i % (SS(dj->fs) / 32))) { /* Sector changed? */ - dj->sect++; /* Next sector */ - - if (dj->clust == 0) { /* Static table */ - if (i >= dj->fs->n_rootdir) /* Report EOT when end of table */ - return FR_NO_FILE; - } - else { /* Dynamic table */ - if (((i / (SS(dj->fs) / 32)) & (dj->fs->csize - 1)) == 0) { /* Cluster changed? */ - clst = get_fat(dj->fs, dj->clust); /* Get next cluster */ - if (clst <= 1) return FR_INT_ERR; - if (clst == 0xFFFFFFFF) return FR_DISK_ERR; - if (clst >= dj->fs->n_fatent) { /* When it reached end of dynamic table */ -#if !_FS_READONLY - BYTE c; - if (!stretch) return FR_NO_FILE; /* When do not stretch, report EOT */ - clst = create_chain(dj->fs, dj->clust); /* Stretch cluster chain */ - if (clst == 0) return FR_DENIED; /* No free cluster */ - if (clst == 1) return FR_INT_ERR; - if (clst == 0xFFFFFFFF) return FR_DISK_ERR; - /* Clean-up stretched table */ - if (move_window(dj->fs, 0)) return FR_DISK_ERR; /* Flush active window */ - mem_set(dj->fs->win, 0, SS(dj->fs)); /* Clear window buffer */ - dj->fs->winsect = clust2sect(dj->fs, clst); /* Cluster start sector */ - for (c = 0; c < dj->fs->csize; c++) { /* Fill the new cluster with 0 */ - dj->fs->wflag = 1; - if (move_window(dj->fs, 0)) return FR_DISK_ERR; - dj->fs->winsect++; - } - dj->fs->winsect -= c; /* Rewind window address */ -#else - return FR_NO_FILE; /* Report EOT */ -#endif - } - dj->clust = clst; /* Initialize data for new cluster */ - dj->sect = clust2sect(dj->fs, clst); - } - } - } - - dj->index = i; - dj->dir = dj->fs->win + (i % (SS(dj->fs) / 32)) * 32; - - return FR_OK; -} - - - - -/*-----------------------------------------------------------------------*/ -/* LFN handling - Test/Pick/Fit an LFN segment from/to directory entry */ -/*-----------------------------------------------------------------------*/ -#if _USE_LFN -static -const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30}; /* Offset of LFN chars in the directory entry */ - - -static -int cmp_lfn ( /* 1:Matched, 0:Not matched */ - WCHAR *lfnbuf, /* Pointer to the LFN to be compared */ - BYTE *dir /* Pointer to the directory entry containing a part of LFN */ -) -{ - UINT i, s; - WCHAR wc, uc; - - - i = ((dir[LDIR_Ord] & 0xBF) - 1) * 13; /* Get offset in the LFN buffer */ - s = 0; wc = 1; - do { - uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */ - if (wc) { /* Last char has not been processed */ - wc = ff_wtoupper(uc); /* Convert it to upper case */ - if (i >= _MAX_LFN || wc != ff_wtoupper(lfnbuf[i++])) /* Compare it */ - return 0; /* Not matched */ - } else { - if (uc != 0xFFFF) return 0; /* Check filler */ - } - } while (++s < 13); /* Repeat until all chars in the entry are checked */ - - if ((dir[LDIR_Ord] & 0x40) && wc && lfnbuf[i]) /* Last segment matched but different length */ - return 0; - - return 1; /* The part of LFN matched */ -} - - - -static -int pick_lfn ( /* 1:Succeeded, 0:Buffer overflow */ - WCHAR *lfnbuf, /* Pointer to the Unicode-LFN buffer */ - BYTE *dir /* Pointer to the directory entry */ -) -{ - UINT i, s; - WCHAR wc, uc; - - - i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13; /* Offset in the LFN buffer */ - - s = 0; wc = 1; - do { - uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */ - if (wc) { /* Last char has not been processed */ - if (i >= _MAX_LFN) return 0; /* Buffer overflow? */ - lfnbuf[i++] = wc = uc; /* Store it */ - } else { - if (uc != 0xFFFF) return 0; /* Check filler */ - } - } while (++s < 13); /* Read all character in the entry */ - - if (dir[LDIR_Ord] & 0x40) { /* Put terminator if it is the last LFN part */ - if (i >= _MAX_LFN) return 0; /* Buffer overflow? */ - lfnbuf[i] = 0; - } - - return 1; -} - - -#if !_FS_READONLY -static -void fit_lfn ( - const WCHAR *lfnbuf, /* Pointer to the LFN buffer */ - BYTE *dir, /* Pointer to the directory entry */ - BYTE ord, /* LFN order (1-20) */ - BYTE sum /* SFN sum */ -) -{ - UINT i, s; - WCHAR wc; - - - dir[LDIR_Chksum] = sum; /* Set check sum */ - dir[LDIR_Attr] = AM_LFN; /* Set attribute. LFN entry */ - dir[LDIR_Type] = 0; - ST_WORD(dir+LDIR_FstClusLO, 0); - - i = (ord - 1) * 13; /* Get offset in the LFN buffer */ - s = wc = 0; - do { - if (wc != 0xFFFF) wc = lfnbuf[i++]; /* Get an effective char */ - ST_WORD(dir+LfnOfs[s], wc); /* Put it */ - if (!wc) wc = 0xFFFF; /* Padding chars following last char */ - } while (++s < 13); - if (wc == 0xFFFF || !lfnbuf[i]) ord |= 0x40; /* Bottom LFN part is the start of LFN sequence */ - dir[LDIR_Ord] = ord; /* Set the LFN order */ -} - -#endif -#endif - - - -/*-----------------------------------------------------------------------*/ -/* Create numbered name */ -/*-----------------------------------------------------------------------*/ -#if _USE_LFN -void gen_numname ( - BYTE *dst, /* Pointer to generated SFN */ - const BYTE *src, /* Pointer to source SFN to be modified */ - const WCHAR *lfn, /* Pointer to LFN */ - WORD seq /* Sequence number */ -) -{ - BYTE ns[8], c; - UINT i, j; - - - mem_cpy(dst, src, 11); - - if (seq > 5) { /* On many collisions, generate a hash number instead of sequential number */ - do seq = (seq >> 1) + (seq << 15) + (WORD)*lfn++; while (*lfn); - } - - /* itoa */ - i = 7; - do { - c = (seq % 16) + '0'; - if (c > '9') c += 7; - ns[i--] = c; - seq /= 16; - } while (seq); - ns[i] = '~'; - - /* Append the number */ - for (j = 0; j < i && dst[j] != ' '; j++) { - if (IsDBCS1(dst[j])) { - if (j == i - 1) break; - j++; - } - } - do { - dst[j++] = (i < 8) ? ns[i++] : ' '; - } while (j < 8); -} -#endif - - - - -/*-----------------------------------------------------------------------*/ -/* Calculate sum of an SFN */ -/*-----------------------------------------------------------------------*/ -#if _USE_LFN -static -BYTE sum_sfn ( - const BYTE *dir /* Ptr to directory entry */ -) -{ - BYTE sum = 0; - UINT n = 11; - - do sum = (sum >> 1) + (sum << 7) + *dir++; while (--n); - return sum; -} -#endif - - - - -/*-----------------------------------------------------------------------*/ -/* Directory handling - Find an object in the directory */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT dir_find ( - DIR *dj /* Pointer to the directory object linked to the file name */ -) -{ - FRESULT res; - BYTE c, *dir; -#if _USE_LFN - BYTE a, ord, sum; -#endif - - res = dir_sdi(dj, 0); /* Rewind directory object */ - if (res != FR_OK) return res; - -#if _USE_LFN - ord = sum = 0xFF; -#endif - do { - res = move_window(dj->fs, dj->sect); - if (res != FR_OK) break; - dir = dj->dir; /* Ptr to the directory entry of current index */ - c = dir[DIR_Name]; - if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ -#if _USE_LFN /* LFN configuration */ - a = dir[DIR_Attr] & AM_MASK; - if (c == 0xE5 || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */ - ord = 0xFF; - } else { - if (a == AM_LFN) { /* An LFN entry is found */ - if (dj->lfn) { - if (c & 0x40) { /* Is it start of LFN sequence? */ - sum = dir[LDIR_Chksum]; - c &= 0xBF; ord = c; /* LFN start order */ - dj->lfn_idx = dj->index; - } - /* Check validity of the LFN entry and compare it with given name */ - ord = (c == ord && sum == dir[LDIR_Chksum] && cmp_lfn(dj->lfn, dir)) ? ord - 1 : 0xFF; - } - } else { /* An SFN entry is found */ - if (!ord && sum == sum_sfn(dir)) break; /* LFN matched? */ - ord = 0xFF; dj->lfn_idx = 0xFFFF; /* Reset LFN sequence */ - if (!(dj->fn[NS] & NS_LOSS) && !mem_cmp(dir, dj->fn, 11)) break; /* SFN matched? */ - } - } -#else /* Non LFN configuration */ - if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dj->fn, 11)) /* Is it a valid entry? */ - break; -#endif - res = dir_next(dj, 0); /* Next entry */ - } while (res == FR_OK); - - return res; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Read an object from the directory */ -/*-----------------------------------------------------------------------*/ -#if _FS_MINIMIZE <= 1 -static -FRESULT dir_read ( - DIR *dj /* Pointer to the directory object that pointing the entry to be read */ -) -{ - FRESULT res; - BYTE c, *dir; -#if _USE_LFN - BYTE a, ord = 0xFF, sum = 0xFF; -#endif - - res = FR_NO_FILE; - while (dj->sect) { - res = move_window(dj->fs, dj->sect); - if (res != FR_OK) break; - dir = dj->dir; /* Ptr to the directory entry of current index */ - c = dir[DIR_Name]; - if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ -#if _USE_LFN /* LFN configuration */ - a = dir[DIR_Attr] & AM_MASK; - if (c == 0xE5 || (!_FS_RPATH && c == '.') || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */ - ord = 0xFF; - } else { - if (a == AM_LFN) { /* An LFN entry is found */ - if (c & 0x40) { /* Is it start of LFN sequence? */ - sum = dir[LDIR_Chksum]; - c &= 0xBF; ord = c; - dj->lfn_idx = dj->index; - } - /* Check LFN validity and capture it */ - ord = (c == ord && sum == dir[LDIR_Chksum] && pick_lfn(dj->lfn, dir)) ? ord - 1 : 0xFF; - } else { /* An SFN entry is found */ - if (ord || sum != sum_sfn(dir)) /* Is there a valid LFN? */ - dj->lfn_idx = 0xFFFF; /* It has no LFN. */ - break; - } - } -#else /* Non LFN configuration */ - if (c != 0xE5 && (_FS_RPATH || c != '.') && !(dir[DIR_Attr] & AM_VOL)) /* Is it a valid entry? */ - break; -#endif - res = dir_next(dj, 0); /* Next entry */ - if (res != FR_OK) break; - } - - if (res != FR_OK) dj->sect = 0; - - return res; -} -#endif - - - -/*-----------------------------------------------------------------------*/ -/* Register an object to the directory */ -/*-----------------------------------------------------------------------*/ -#if !_FS_READONLY -static -FRESULT dir_register ( /* FR_OK:Successful, FR_DENIED:No free entry or too many SFN collision, FR_DISK_ERR:Disk error */ - DIR *dj /* Target directory with object name to be created */ -) -{ - FRESULT res; - BYTE c, *dir; -#if _USE_LFN /* LFN configuration */ - WORD n, ne, is; - BYTE sn[12], *fn, sum; - WCHAR *lfn; - - - fn = dj->fn; lfn = dj->lfn; - mem_cpy(sn, fn, 12); - - if (_FS_RPATH && (sn[NS] & NS_DOT)) /* Cannot create dot entry */ - return FR_INVALID_NAME; - - if (sn[NS] & NS_LOSS) { /* When LFN is out of 8.3 format, generate a numbered name */ - fn[NS] = 0; dj->lfn = 0; /* Find only SFN */ - for (n = 1; n < 100; n++) { - gen_numname(fn, sn, lfn, n); /* Generate a numbered name */ - res = dir_find(dj); /* Check if the name collides with existing SFN */ - if (res != FR_OK) break; - } - if (n == 100) return FR_DENIED; /* Abort if too many collisions */ - if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */ - fn[NS] = sn[NS]; dj->lfn = lfn; - } - - if (sn[NS] & NS_LFN) { /* When LFN is to be created, reserve an SFN + LFN entries. */ - for (ne = 0; lfn[ne]; ne++) ; - ne = (ne + 25) / 13; - } else { /* Otherwise reserve only an SFN entry. */ - ne = 1; - } - - /* Reserve contiguous entries */ - res = dir_sdi(dj, 0); - if (res != FR_OK) return res; - n = is = 0; - do { - res = move_window(dj->fs, dj->sect); - if (res != FR_OK) break; - c = *dj->dir; /* Check the entry status */ - if (c == 0xE5 || c == 0) { /* Is it a blank entry? */ - if (n == 0) is = dj->index; /* First index of the contiguous entry */ - if (++n == ne) break; /* A contiguous entry that required count is found */ - } else { - n = 0; /* Not a blank entry. Restart to search */ - } - res = dir_next(dj, 1); /* Next entry with table stretch */ - } while (res == FR_OK); - - if (res == FR_OK && ne > 1) { /* Initialize LFN entry if needed */ - res = dir_sdi(dj, is); - if (res == FR_OK) { - sum = sum_sfn(dj->fn); /* Sum of the SFN tied to the LFN */ - ne--; - do { /* Store LFN entries in bottom first */ - res = move_window(dj->fs, dj->sect); - if (res != FR_OK) break; - fit_lfn(dj->lfn, dj->dir, (BYTE)ne, sum); - dj->fs->wflag = 1; - res = dir_next(dj, 0); /* Next entry */ - } while (res == FR_OK && --ne); - } - } - -#else /* Non LFN configuration */ - res = dir_sdi(dj, 0); - if (res == FR_OK) { - do { /* Find a blank entry for the SFN */ - res = move_window(dj->fs, dj->sect); - if (res != FR_OK) break; - c = *dj->dir; - if (c == 0xE5 || c == 0) break; /* Is it a blank entry? */ - res = dir_next(dj, 1); /* Next entry with table stretch */ - } while (res == FR_OK); - } -#endif - - if (res == FR_OK) { /* Initialize the SFN entry */ - res = move_window(dj->fs, dj->sect); - if (res == FR_OK) { - dir = dj->dir; - mem_set(dir, 0, 32); /* Clean the entry */ - mem_cpy(dir, dj->fn, 11); /* Put SFN */ -#if _USE_LFN - dir[DIR_NTres] = *(dj->fn+NS) & (NS_BODY | NS_EXT); /* Put NT flag */ -#endif - dj->fs->wflag = 1; - } - } - - return res; -} -#endif /* !_FS_READONLY */ - - - - -/*-----------------------------------------------------------------------*/ -/* Remove an object from the directory */ -/*-----------------------------------------------------------------------*/ -#if !_FS_READONLY && !_FS_MINIMIZE -static -FRESULT dir_remove ( /* FR_OK: Successful, FR_DISK_ERR: A disk error */ - DIR *dj /* Directory object pointing the entry to be removed */ -) -{ - FRESULT res; -#if _USE_LFN /* LFN configuration */ - WORD i; - - i = dj->index; /* SFN index */ - res = dir_sdi(dj, (WORD)((dj->lfn_idx == 0xFFFF) ? i : dj->lfn_idx)); /* Goto the SFN or top of the LFN entries */ - if (res == FR_OK) { - do { - res = move_window(dj->fs, dj->sect); - if (res != FR_OK) break; - *dj->dir = 0xE5; /* Mark the entry "deleted" */ - dj->fs->wflag = 1; - if (dj->index >= i) break; /* When reached SFN, all entries of the object has been deleted. */ - res = dir_next(dj, 0); /* Next entry */ - } while (res == FR_OK); - if (res == FR_NO_FILE) res = FR_INT_ERR; - } - -#else /* Non LFN configuration */ - res = dir_sdi(dj, dj->index); - if (res == FR_OK) { - res = move_window(dj->fs, dj->sect); - if (res == FR_OK) { - *dj->dir = 0xE5; /* Mark the entry "deleted" */ - dj->fs->wflag = 1; - } - } -#endif - - return res; -} -#endif /* !_FS_READONLY */ - - - - -/*-----------------------------------------------------------------------*/ -/* Pick a segment and create the object name in directory form */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT create_name ( - DIR *dj, /* Pointer to the directory object */ - const TCHAR **path /* Pointer to pointer to the segment in the path string */ -) -{ -#ifdef _EXCVT - static const BYTE excvt[] = _EXCVT; /* Upper conversion table for extended chars */ -#endif - -#if _USE_LFN /* LFN configuration */ - BYTE b, cf; - WCHAR w, *lfn; - UINT i, ni, si, di; - const TCHAR *p; - - /* Create LFN in Unicode */ - si = di = 0; - p = *path; - lfn = dj->lfn; - for (;;) { - w = p[si++]; /* Get a character */ - if (w < ' ' || w == '/' || w == '\\') break; /* Break on end of segment */ - if (di >= _MAX_LFN) /* Reject too long name */ - return FR_INVALID_NAME; -#if !_LFN_UNICODE - w &= 0xFF; - if (IsDBCS1(w)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */ - b = (BYTE)p[si++]; /* Get 2nd byte */ - if (!IsDBCS2(b)) - return FR_INVALID_NAME; /* Reject invalid sequence */ - w = (w << 8) + b; /* Create a DBC */ - } - w = ff_convert(w, 1); /* Convert ANSI/OEM to Unicode */ - if (!w) return FR_INVALID_NAME; /* Reject invalid code */ -#endif - if (w < 0x80 && chk_chr("\"*:<>\?|\x7F", w)) /* Reject illegal chars for LFN */ - return FR_INVALID_NAME; - lfn[di++] = w; /* Store the Unicode char */ - } - *path = &p[si]; /* Return pointer to the next segment */ - cf = (w < ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */ -#if _FS_RPATH - if ((di == 1 && lfn[di-1] == '.') || /* Is this a dot entry? */ - (di == 2 && lfn[di-1] == '.' && lfn[di-2] == '.')) { - lfn[di] = 0; - for (i = 0; i < 11; i++) - dj->fn[i] = (i < di) ? '.' : ' '; - dj->fn[i] = cf | NS_DOT; /* This is a dot entry */ - return FR_OK; - } -#endif - while (di) { /* Strip trailing spaces and dots */ - w = lfn[di-1]; - if (w != ' ' && w != '.') break; - di--; - } - if (!di) return FR_INVALID_NAME; /* Reject nul string */ - - lfn[di] = 0; /* LFN is created */ - - /* Create SFN in directory form */ - mem_set(dj->fn, ' ', 11); - for (si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++) ; /* Strip leading spaces and dots */ - if (si) cf |= NS_LOSS | NS_LFN; - while (di && lfn[di - 1] != '.') di--; /* Find extension (di<=si: no extension) */ - - b = i = 0; ni = 8; - for (;;) { - w = lfn[si++]; /* Get an LFN char */ - if (!w) break; /* Break on end of the LFN */ - if (w == ' ' || (w == '.' && si != di)) { /* Remove spaces and dots */ - cf |= NS_LOSS | NS_LFN; continue; - } - - if (i >= ni || si == di) { /* Extension or end of SFN */ - if (ni == 11) { /* Long extension */ - cf |= NS_LOSS | NS_LFN; break; - } - if (si != di) cf |= NS_LOSS | NS_LFN; /* Out of 8.3 format */ - if (si > di) break; /* No extension */ - si = di; i = 8; ni = 11; /* Enter extension section */ - b <<= 2; continue; - } - - if (w >= 0x80) { /* Non ASCII char */ -#ifdef _EXCVT - w = ff_convert(w, 0); /* Unicode -> OEM code */ - if (w) w = excvt[w - 0x80]; /* Convert extended char to upper (SBCS) */ -#else - w = ff_convert(ff_wtoupper(w), 0); /* Upper converted Unicode -> OEM code */ -#endif - cf |= NS_LFN; /* Force create LFN entry */ - } - - if (_DF1S && w >= 0x100) { /* Double byte char (always false on SBCS cfg) */ - if (i >= ni - 1) { - cf |= NS_LOSS | NS_LFN; i = ni; continue; - } - dj->fn[i++] = (BYTE)(w >> 8); - } else { /* Single byte char */ - if (!w || chk_chr("+,;=[]", w)) { /* Replace illegal chars for SFN */ - w = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */ - } else { - if (IsUpper(w)) { /* ASCII large capital */ - b |= 2; - } else { - if (IsLower(w)) { /* ASCII small capital */ - b |= 1; w -= 0x20; - } - } - } - } - dj->fn[i++] = (BYTE)w; - } - - if (dj->fn[0] == 0xE5) dj->fn[0] = 0x05; /* If the first char collides with deleted mark, replace it with 0x05 */ - - if (ni == 8) b <<= 2; - if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) /* Create LFN entry when there are composite capitals */ - cf |= NS_LFN; - if (!(cf & NS_LFN)) { /* When LFN is in 8.3 format without extended char, NT flags are created */ - if ((b & 0x03) == 0x01) cf |= NS_EXT; /* NT flag (Extension has only small capital) */ - if ((b & 0x0C) == 0x04) cf |= NS_BODY; /* NT flag (Filename has only small capital) */ - } - - dj->fn[NS] = cf; /* SFN is created */ - - return FR_OK; - - -#else /* Non-LFN configuration */ - BYTE b, c, d, *sfn; - UINT ni, si, i; - const char *p; - - /* Create file name in directory form */ - sfn = dj->fn; - mem_set(sfn, ' ', 11); - si = i = b = 0; ni = 8; - p = *path; -#if _FS_RPATH - if (p[si] == '.') { /* Is this a dot entry? */ - for (;;) { - c = (BYTE)p[si++]; - if (c != '.' || si >= 3) break; - sfn[i++] = c; - } - if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME; - *path = &p[si]; /* Return pointer to the next segment */ - sfn[NS] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT; /* Set last segment flag if end of path */ - return FR_OK; - } -#endif - for (;;) { - c = (BYTE)p[si++]; - if (c <= ' ' || c == '/' || c == '\\') break; /* Break on end of segment */ - if (c == '.' || i >= ni) { - if (ni != 8 || c != '.') return FR_INVALID_NAME; - i = 8; ni = 11; - b <<= 2; continue; - } - if (c >= 0x80) { /* Extended char? */ - b |= 3; /* Eliminate NT flag */ -#ifdef _EXCVT - c = excvt[c-0x80]; /* Upper conversion (SBCS) */ -#else -#if !_DF1S /* ASCII only cfg */ - return FR_INVALID_NAME; -#endif -#endif - } - if (IsDBCS1(c)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */ - d = (BYTE)p[si++]; /* Get 2nd byte */ - if (!IsDBCS2(d) || i >= ni - 1) /* Reject invalid DBC */ - return FR_INVALID_NAME; - sfn[i++] = c; - sfn[i++] = d; - } else { /* Single byte code */ - if (chk_chr("\"*+,:;<=>\?[]|\x7F", c)) /* Reject illegal chrs for SFN */ - return FR_INVALID_NAME; - if (IsUpper(c)) { /* ASCII large capital? */ - b |= 2; - } else { - if (IsLower(c)) { /* ASCII small capital? */ - b |= 1; c -= 0x20; - } - } - sfn[i++] = c; - } - } - *path = &p[si]; /* Return pointer to the next segment */ - c = (c <= ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */ - - if (!i) return FR_INVALID_NAME; /* Reject nul string */ - if (sfn[0] == 0xE5) sfn[0] = 0x05; /* When first char collides with 0xE5, replace it with 0x05 */ - - if (ni == 8) b <<= 2; - if ((b & 0x03) == 0x01) c |= NS_EXT; /* NT flag (Name extension has only small capital) */ - if ((b & 0x0C) == 0x04) c |= NS_BODY; /* NT flag (Name body has only small capital) */ - - sfn[NS] = c; /* Store NT flag, File name is created */ - - return FR_OK; -#endif -} - - - - -/*-----------------------------------------------------------------------*/ -/* Get file information from directory entry */ -/*-----------------------------------------------------------------------*/ -#if _FS_MINIMIZE <= 1 -static -void get_fileinfo ( /* No return code */ - DIR *dj, /* Pointer to the directory object */ - FILINFO *fno /* Pointer to the file information to be filled */ -) -{ - UINT i; - BYTE nt, *dir; - TCHAR *p, c; - - - p = fno->fname; - if (dj->sect) { - dir = dj->dir; - nt = dir[DIR_NTres]; /* NT flag */ - for (i = 0; i < 8; i++) { /* Copy name body */ - c = dir[i]; - if (c == ' ') break; - if (c == 0x05) c = (TCHAR)0xE5; - if (_USE_LFN && (nt & NS_BODY) && IsUpper(c)) c += 0x20; -#if _LFN_UNICODE - if (IsDBCS1(c) && i < 7 && IsDBCS2(dir[i+1])) - c = (c << 8) | dir[++i]; - c = ff_convert(c, 1); - if (!c) c = '?'; -#endif - *p++ = c; - } - if (dir[8] != ' ') { /* Copy name extension */ - *p++ = '.'; - for (i = 8; i < 11; i++) { - c = dir[i]; - if (c == ' ') break; - if (_USE_LFN && (nt & NS_EXT) && IsUpper(c)) c += 0x20; -#if _LFN_UNICODE - if (IsDBCS1(c) && i < 10 && IsDBCS2(dir[i+1])) - c = (c << 8) | dir[++i]; - c = ff_convert(c, 1); - if (!c) c = '?'; -#endif - *p++ = c; - } - } - fno->fattrib = dir[DIR_Attr]; /* Attribute */ - fno->fsize = LD_DWORD(dir+DIR_FileSize); /* Size */ - fno->fdate = LD_WORD(dir+DIR_WrtDate); /* Date */ - fno->ftime = LD_WORD(dir+DIR_WrtTime); /* Time */ - } - *p = 0; /* Terminate SFN str by a \0 */ - -#if _USE_LFN - if (fno->lfname && fno->lfsize) { - TCHAR *tp = fno->lfname; - WCHAR w, *lfn; - - i = 0; - if (dj->sect && dj->lfn_idx != 0xFFFF) {/* Get LFN if available */ - lfn = dj->lfn; - while ((w = *lfn++) != 0) { /* Get an LFN char */ -#if !_LFN_UNICODE - w = ff_convert(w, 0); /* Unicode -> OEM conversion */ - if (!w) { i = 0; break; } /* Could not convert, no LFN */ - if (_DF1S && w >= 0x100) /* Put 1st byte if it is a DBC (always false on SBCS cfg) */ - tp[i++] = (TCHAR)(w >> 8); -#endif - if (i >= fno->lfsize - 1) { i = 0; break; } /* Buffer overflow, no LFN */ - tp[i++] = (TCHAR)w; - } - } - tp[i] = 0; /* Terminate the LFN str by a \0 */ - } -#endif -} -#endif /* _FS_MINIMIZE <= 1 */ - - - - -/*-----------------------------------------------------------------------*/ -/* Follow a file path */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */ - DIR *dj, /* Directory object to return last directory and found object */ - const TCHAR *path /* Full-path string to find a file or directory */ -) -{ - FRESULT res; - BYTE *dir, ns; - - -#if _FS_RPATH - if (*path == '/' || *path == '\\') { /* There is a heading separator */ - path++; dj->sclust = 0; /* Strip it and start from the root dir */ - } else { /* No heading separator */ - dj->sclust = dj->fs->cdir; /* Start from the current dir */ - } -#else - if (*path == '/' || *path == '\\') /* Strip heading separator if exist */ - path++; - dj->sclust = 0; /* Start from the root dir */ -#endif - - if ((UINT)*path < ' ') { /* Nul path means the start directory itself */ - res = dir_sdi(dj, 0); - dj->dir = 0; - - } else { /* Follow path */ - for (;;) { - res = create_name(dj, &path); /* Get a segment */ - if (res != FR_OK) break; - res = dir_find(dj); /* Find it */ - ns = *(dj->fn+NS); - if (res != FR_OK) { /* Failed to find the object */ - if (res != FR_NO_FILE) break; /* Abort if any hard error occured */ - /* Object not found */ - if (_FS_RPATH && (ns & NS_DOT)) { /* If dot entry is not exit */ - dj->sclust = 0; dj->dir = 0; /* It is the root dir */ - res = FR_OK; - if (!(ns & NS_LAST)) continue; - } else { /* Could not find the object */ - if (!(ns & NS_LAST)) res = FR_NO_PATH; - } - break; - } - if (ns & NS_LAST) break; /* Last segment match. Function completed. */ - dir = dj->dir; /* There is next segment. Follow the sub directory */ - if (!(dir[DIR_Attr] & AM_DIR)) { /* Cannot follow because it is a file */ - res = FR_NO_PATH; break; - } - dj->sclust = LD_CLUST(dir); - } - } - - return res; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Load boot record and check if it is an FAT boot record */ -/*-----------------------------------------------------------------------*/ - -static -BYTE check_fs ( /* 0:The FAT BR, 1:Valid BR but not an FAT, 2:Not a BR, 3:Disk error */ - FATFS *fs, /* File system object */ - DWORD sect /* Sector# (lba) to check if it is an FAT boot record or not */ -) -{ - if (disk_read(fs->drv, fs->win, sect, 1) != RES_OK) /* Load boot record */ - return 3; - if (LD_WORD(&fs->win[BS_55AA]) != 0xAA55) /* Check record signature (always placed at offset 510 even if the sector size is >512) */ - return 2; - - if ((LD_DWORD(&fs->win[BS_FilSysType]) & 0xFFFFFF) == 0x544146) /* Check "FAT" string */ - return 0; - if ((LD_DWORD(&fs->win[BS_FilSysType32]) & 0xFFFFFF) == 0x544146) - return 0; - - return 1; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Check if the file system object is valid or not */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT chk_mounted ( /* FR_OK(0): successful, !=0: any error occurred */ - const TCHAR **path, /* Pointer to pointer to the path name (drive number) */ - FATFS **rfs, /* Pointer to pointer to the found file system object */ - BYTE chk_wp /* !=0: Check media write protection for write access */ -) -{ - BYTE fmt, b, *tbl; - UINT vol; - DSTATUS stat; - DWORD bsect, fasize, tsect, sysect, nclst, szbfat; - WORD nrsv; - const TCHAR *p = *path; - FATFS *fs; - - /* Get logical drive number from the path name */ - vol = p[0] - '0'; /* Is there a drive number? */ - if (vol <= 9 && p[1] == ':') { /* Found a drive number, get and strip it */ - p += 2; *path = p; /* Return pointer to the path name */ - } else { /* No drive number is given */ -#if _FS_RPATH - vol = CurrVol; /* Use current drive */ -#else - vol = 0; /* Use drive 0 */ -#endif - } - - /* Check if the logical drive is valid or not */ - if (vol >= _VOLUMES) /* Is the drive number valid? */ - return FR_INVALID_DRIVE; - *rfs = fs = FatFs[vol]; /* Return pointer to the corresponding file system object */ - if (!fs) return FR_NOT_ENABLED; /* Is the file system object available? */ - - ENTER_FF(fs); /* Lock file system */ - - if (fs->fs_type) { /* If the logical drive has been mounted */ - stat = disk_status(fs->drv); - if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized (has not been changed), */ -#if !_FS_READONLY - if (chk_wp && (stat & STA_PROTECT)) /* Check write protection if needed */ - return FR_WRITE_PROTECTED; -#endif - return FR_OK; /* The file system object is valid */ - } - } - - /* The logical drive must be mounted. */ - /* Following code attempts to mount a volume. (analyze BPB and initialize the fs object) */ - - fs->fs_type = 0; /* Clear the file system object */ - fs->drv = (BYTE)LD2PD(vol); /* Bind the logical drive and a physical drive */ - stat = disk_initialize(fs->drv); /* Initialize low level disk I/O layer */ - if (stat & STA_NOINIT) /* Check if the initialization succeeded */ - return FR_NOT_READY; /* Failed to initialize due to no media or hard error */ -#if _MAX_SS != 512 /* Get disk sector size (variable sector size cfg only) */ - if (disk_ioctl(fs->drv, GET_SECTOR_SIZE, &fs->ssize) != RES_OK) - return FR_DISK_ERR; -#endif -#if !_FS_READONLY - if (chk_wp && (stat & STA_PROTECT)) /* Check disk write protection if needed */ - return FR_WRITE_PROTECTED; -#endif - /* Search FAT partition on the drive. Supports only generic partitionings, FDISK and SFD. */ - fmt = check_fs(fs, bsect = 0); /* Check sector 0 if it is a VBR */ - if (fmt == 1) { /* Not an FAT-VBR, the disk may be partitioned */ - /* Check the partition listed in top of the partition table */ - tbl = &fs->win[MBR_Table + LD2PT(vol) * 16]; /* Partition table */ - if (tbl[4]) { /* Is the partition existing? */ - bsect = LD_DWORD(&tbl[8]); /* Partition offset in LBA */ - fmt = check_fs(fs, bsect); /* Check the partition */ - } - } - if (fmt == 3) return FR_DISK_ERR; - if (fmt) return FR_NO_FILESYSTEM; /* No FAT volume is found */ - - /* Following code initializes the file system object */ - - if (LD_WORD(fs->win+BPB_BytsPerSec) != SS(fs)) /* (BPB_BytsPerSec must be equal to the physical sector size) */ - return FR_NO_FILESYSTEM; - - fasize = LD_WORD(fs->win+BPB_FATSz16); /* Number of sectors per FAT */ - if (!fasize) fasize = LD_DWORD(fs->win+BPB_FATSz32); - fs->fsize = fasize; - - fs->n_fats = b = fs->win[BPB_NumFATs]; /* Number of FAT copies */ - if (b != 1 && b != 2) return FR_NO_FILESYSTEM; /* (Must be 1 or 2) */ - fasize *= b; /* Number of sectors for FAT area */ - - fs->csize = b = fs->win[BPB_SecPerClus]; /* Number of sectors per cluster */ - if (!b || (b & (b - 1))) return FR_NO_FILESYSTEM; /* (Must be power of 2) */ - - fs->n_rootdir = LD_WORD(fs->win+BPB_RootEntCnt); /* Number of root directory entries */ - if (fs->n_rootdir % (SS(fs) / 32)) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be sector aligned) */ - - tsect = LD_WORD(fs->win+BPB_TotSec16); /* Number of sectors on the volume */ - if (!tsect) tsect = LD_DWORD(fs->win+BPB_TotSec32); - - nrsv = LD_WORD(fs->win+BPB_RsvdSecCnt); /* Number of reserved sectors */ - if (!nrsv) return FR_NO_FILESYSTEM; /* (BPB_RsvdSecCnt must not be 0) */ - - /* Determine the FAT sub type */ - sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / 32); /* RSV+FAT+DIR */ - if (tsect < sysect) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ - nclst = (tsect - sysect) / fs->csize; /* Number of clusters */ - if (!nclst) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ - fmt = FS_FAT12; - if (nclst >= MIN_FAT16) fmt = FS_FAT16; - if (nclst >= MIN_FAT32) fmt = FS_FAT32; - - /* Boundaries and Limits */ - fs->n_fatent = nclst + 2; /* Number of FAT entries */ - fs->database = bsect + sysect; /* Data start sector */ - fs->fatbase = bsect + nrsv; /* FAT start sector */ - if (fmt == FS_FAT32) { - if (fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */ - fs->dirbase = LD_DWORD(fs->win+BPB_RootClus); /* Root directory start cluster */ - szbfat = fs->n_fatent * 4; /* (Required FAT size) */ - } else { - if (!fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must not be 0) */ - fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */ - szbfat = (fmt == FS_FAT16) ? /* (Required FAT size) */ - fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1); - } - if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) /* (FAT size must not be less than FAT sectors */ - return FR_NO_FILESYSTEM; - -#if !_FS_READONLY - /* Initialize cluster allocation information */ - fs->free_clust = 0xFFFFFFFF; - fs->last_clust = 0; - - /* Get fsinfo if available */ - if (fmt == FS_FAT32) { - fs->fsi_flag = 0; - fs->fsi_sector = bsect + LD_WORD(fs->win+BPB_FSInfo); - if (disk_read(fs->drv, fs->win, fs->fsi_sector, 1) == RES_OK && - LD_WORD(fs->win+BS_55AA) == 0xAA55 && - LD_DWORD(fs->win+FSI_LeadSig) == 0x41615252 && - LD_DWORD(fs->win+FSI_StrucSig) == 0x61417272) { - fs->last_clust = LD_DWORD(fs->win+FSI_Nxt_Free); - fs->free_clust = LD_DWORD(fs->win+FSI_Free_Count); - } - } -#endif - fs->fs_type = fmt; /* FAT sub-type */ - fs->id = ++Fsid; /* File system mount ID */ - fs->winsect = 0; /* Invalidate sector cache */ - fs->wflag = 0; -#if _FS_RPATH - fs->cdir = 0; /* Current directory (root dir) */ -#endif -#if _FS_SHARE /* Clear file lock semaphores */ - clear_lock(fs); -#endif - - return FR_OK; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Check if the file/dir object is valid or not */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT validate ( /* FR_OK(0): The object is valid, !=0: Invalid */ - FATFS *fs, /* Pointer to the file system object */ - WORD id /* Member id of the target object to be checked */ -) -{ - if (!fs || !fs->fs_type || fs->id != id) - return FR_INVALID_OBJECT; - - ENTER_FF(fs); /* Lock file system */ - - if (disk_status(fs->drv) & STA_NOINIT) - return FR_NOT_READY; - - return FR_OK; -} - - - - -/*-------------------------------------------------------------------------- - - Public Functions - ---------------------------------------------------------------------------*/ - - - -/*-----------------------------------------------------------------------*/ -/* Mount/Unmount a Logical Drive */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_mount ( - BYTE vol, /* Logical drive number to be mounted/unmounted */ - FATFS *fs /* Pointer to new file system object (NULL for unmount)*/ -) -{ - FATFS *rfs; - - - if (vol >= _VOLUMES) /* Check if the drive number is valid */ - return FR_INVALID_DRIVE; - rfs = FatFs[vol]; /* Get current fs object */ - - if (rfs) { -#if _FS_SHARE - clear_lock(rfs); -#endif -#if _FS_REENTRANT /* Discard sync object of the current volume */ - if (!ff_del_syncobj(rfs->sobj)) return FR_INT_ERR; -#endif - rfs->fs_type = 0; /* Clear old fs object */ - } - - if (fs) { - fs->fs_type = 0; /* Clear new fs object */ -#if _FS_REENTRANT /* Create sync object for the new volume */ - if (!ff_cre_syncobj(vol, &fs->sobj)) return FR_INT_ERR; -#endif - } - FatFs[vol] = fs; /* Register new fs object */ - - return FR_OK; -} - - -#ifndef BOOT -/*---------------------------------------------------------*/ -/* User Provided Date/Time Function for FatFs module */ -/*---------------------------------------------------------*/ -/* This is a real time clock service to be called from */ -/* FatFs module. Any valid time must be returned even if */ -/* the system does not support a real time clock. */ -/* This is not required in read-only configuration. */ - -gtime_t g_unixTime; // Global date/time register, incremented each second in per10ms() - -uint32_t o9x_get_fattime(void) -{ - struct gtm t; - filltm(&g_unixTime, &t); // create a struct tm date/time structure from global unix time stamp - - /* Pack date and time into a DWORD variable */ - return ((DWORD)(t.tm_year - 80) << 25) - | ((uint32_t)(t.tm_mon+1) << 21) - | ((uint32_t)t.tm_mday << 16) - | ((uint32_t)t.tm_hour << 11) - | ((uint32_t)t.tm_min << 5) - | ((uint32_t)t.tm_sec >> 1); -} -#endif - -/*-----------------------------------------------------------------------*/ -/* Open or Create a File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_open ( - FIL *fp, /* Pointer to the blank file object */ - const TCHAR *path, /* Pointer to the file name */ - BYTE mode /* Access mode and file open mode flags */ -) -{ - FRESULT res; - DIR dj; - BYTE *dir; - DEF_NAMEBUF; - - - fp->fs = 0; /* Clear file object */ - -#if !_FS_READONLY - mode &= FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW; - res = chk_mounted(&path, &dj.fs, (BYTE)(mode & ~FA_READ)); -#else - mode &= FA_READ; - res = chk_mounted(&path, &dj.fs, 0); -#endif - INIT_BUF(dj); - if (res == FR_OK) - res = follow_path(&dj, path); /* Follow the file path */ - dir = dj.dir; - -#if !_FS_READONLY /* R/W configuration */ - if (res == FR_OK) { - if (!dir) /* Current dir itself */ - res = FR_INVALID_NAME; -#if _FS_SHARE - else - res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0); -#endif - } - /* Create or Open a file */ - if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) { - DWORD dw, cl; - - if (res != FR_OK) { /* No file, create new */ - if (res == FR_NO_FILE) /* There is no file to open, create a new entry */ -#if _FS_SHARE - res = enq_lock(dj.fs) ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES; -#else - res = dir_register(&dj); -#endif - mode |= FA_CREATE_ALWAYS; /* File is created */ - dir = dj.dir; /* New entry */ - } - else { /* Any object is already existing */ - if (mode & FA_CREATE_NEW) { /* Cannot create new */ - res = FR_EXIST; - } else { - if (dir[DIR_Attr] & (AM_RDO | AM_DIR)) /* Cannot overwrite it (R/O or DIR) */ - res = FR_DENIED; - } - } - if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) { /* Truncate it if overwrite mode */ - dw = o9x_get_fattime(); /* Created time */ - ST_DWORD(dir+DIR_CrtTime, dw); - dir[DIR_Attr] = 0; /* Reset attribute */ - ST_DWORD(dir+DIR_FileSize, 0); /* size = 0 */ - cl = LD_CLUST(dir); /* Get start cluster */ - ST_CLUST(dir, 0); /* cluster = 0 */ - dj.fs->wflag = 1; - if (cl) { /* Remove the cluster chain if exist */ - dw = dj.fs->winsect; - res = remove_chain(dj.fs, cl); - if (res == FR_OK) { - dj.fs->last_clust = cl - 1; /* Reuse the cluster hole */ - res = move_window(dj.fs, dw); - } - } - } - } - else { /* Open an existing file */ - if (res == FR_OK) { /* Follow succeeded */ - if (dir[DIR_Attr] & AM_DIR) { /* It is a directory */ - res = FR_NO_FILE; - } else { - if ((mode & FA_WRITE) && (dir[DIR_Attr] & AM_RDO)) /* R/O violation */ - res = FR_DENIED; - } - } - } - if (res == FR_OK) { - if (mode & FA_CREATE_ALWAYS) /* Set file change flag if created or overwritten */ - mode |= FA__WRITTEN; - fp->dir_sect = dj.fs->winsect; /* Pointer to the directory entry */ - fp->dir_ptr = dir; -#if _FS_SHARE - fp->lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0); - if (!fp->lockid) res = FR_INT_ERR; -#endif - } - -#else /* R/O configuration */ - if (res == FR_OK) { /* Follow succeeded */ - if (!dir) { /* Current dir itself */ - res = FR_INVALID_NAME; - } else { - if (dir[DIR_Attr] & AM_DIR) /* It is a directory */ - res = FR_NO_FILE; - } - } -#endif - FREE_BUF(); - - if (res == FR_OK) { - fp->flag = mode; /* File access mode */ - fp->org_clust = LD_CLUST(dir); /* File start cluster */ - fp->fsize = LD_DWORD(dir+DIR_FileSize); /* File size */ - fp->fptr = 0; /* File pointer */ - fp->dsect = 0; -#if _USE_FASTSEEK - fp->cltbl = 0; /* No cluster link map table */ -#endif - fp->fs = dj.fs; fp->id = dj.fs->id; /* Validate file object */ - } - - LEAVE_FF(dj.fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Read File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_read ( - FIL *fp, /* Pointer to the file object */ - BYTE *buff, /* Pointer to data buffer */ - UINT btr, /* Number of bytes to read */ - UINT *br /* Pointer to number of bytes read */ -) -{ - FRESULT res; - DWORD clst, sect, remain; - UINT rcnt, cc; - BYTE csect, *rbuff = buff; - - - *br = 0; /* Initialize byte counter */ - - res = validate(fp->fs, fp->id); /* Check validity of the object */ - if (res != FR_OK) LEAVE_FF(fp->fs, res); - if (fp->flag & FA__ERROR) /* Check abort flag */ - LEAVE_FF(fp->fs, FR_INT_ERR); - if (!(fp->flag & FA_READ)) /* Check access mode */ - LEAVE_FF(fp->fs, FR_DENIED); - remain = fp->fsize - fp->fptr; - if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ - - for ( ; btr; /* Repeat until all data transferred */ - rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) { - if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ - csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ - if (!csect) { /* On the cluster boundary? */ - clst = (fp->fptr == 0) ? /* On the top of the file? */ - fp->org_clust : get_fat(fp->fs, fp->curr_clust); - if (clst <= 1) ABORT(fp->fs, FR_INT_ERR); - if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); - fp->curr_clust = clst; /* Update current cluster */ - } - sect = clust2sect(fp->fs, fp->curr_clust); /* Get current sector */ - if (!sect) ABORT(fp->fs, FR_INT_ERR); - sect += csect; - cc = btr / SS(fp->fs); /* When remaining bytes >= sector size, */ - if (cc) { /* Read maximum contiguous sectors directly */ - if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */ - cc = fp->fs->csize - csect; - if (disk_read(fp->fs->drv, rbuff, sect, (BYTE)cc) != RES_OK) - ABORT(fp->fs, FR_DISK_ERR); -#if !_FS_READONLY && _FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it contains a dirty sector */ -#if _FS_TINY - if (fp->fs->wflag && fp->fs->winsect - sect < cc) - mem_cpy(rbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), fp->fs->win, SS(fp->fs)); -#else - if ((fp->flag & FA__DIRTY) && fp->dsect - sect < cc) - mem_cpy(rbuff + ((fp->dsect - sect) * SS(fp->fs)), fp->buf, SS(fp->fs)); -#endif -#endif - rcnt = SS(fp->fs) * cc; /* Number of bytes transferred */ - continue; - } -#if !_FS_TINY -#if !_FS_READONLY - if (fp->flag & FA__DIRTY) { /* Write sector I/O buffer if needed */ - if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) - ABORT(fp->fs, FR_DISK_ERR); - fp->flag &= ~FA__DIRTY; - } -#endif - if (fp->dsect != sect) { /* Fill sector buffer with file data */ - if (disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK) - ABORT(fp->fs, FR_DISK_ERR); - } -#endif - fp->dsect = sect; - } - rcnt = SS(fp->fs) - (fp->fptr % SS(fp->fs)); /* Get partial sector data from sector buffer */ - if (rcnt > btr) rcnt = btr; -#if _FS_TINY - if (move_window(fp->fs, fp->dsect)) /* Move sector window */ - ABORT(fp->fs, FR_DISK_ERR); - mem_cpy(rbuff, &fp->fs->win[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */ -#else - mem_cpy(rbuff, &fp->buf[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */ -#endif - } - - LEAVE_FF(fp->fs, FR_OK); -} - - - - -#if !_FS_READONLY -/*-----------------------------------------------------------------------*/ -/* Write File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_write ( - FIL *fp, /* Pointer to the file object */ - const BYTE *buff, /* Pointer to the data to be written */ - UINT btw, /* Number of bytes to write */ - UINT *bw /* Pointer to number of bytes written */ -) -{ - FRESULT res; - DWORD clst, sect; - UINT wcnt, cc; - const BYTE *wbuff = buff; - BYTE csect; - - - *bw = 0; /* Initialize byte counter */ - - res = validate(fp->fs, fp->id); /* Check validity of the object */ - if (res != FR_OK) LEAVE_FF(fp->fs, res); - if (fp->flag & FA__ERROR) /* Check abort flag */ - LEAVE_FF(fp->fs, FR_INT_ERR); - if (!(fp->flag & FA_WRITE)) /* Check access mode */ - LEAVE_FF(fp->fs, FR_DENIED); - if (fp->fsize + btw < fp->fsize) btw = 0; /* File size cannot reach 4GB */ - - for ( ; btw; /* Repeat until all data transferred */ - wbuff += wcnt, fp->fptr += wcnt, *bw += wcnt, btw -= wcnt) { - if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ - csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ - if (!csect) { /* On the cluster boundary? */ - if (fp->fptr == 0) { /* On the top of the file? */ - clst = fp->org_clust; /* Follow from the origin */ - if (clst == 0) /* When there is no cluster chain, */ - fp->org_clust = clst = create_chain(fp->fs, 0); /* Create a new cluster chain */ - } else { /* Middle or end of the file */ - clst = create_chain(fp->fs, fp->curr_clust); /* Follow or stretch cluster chain */ - } - if (clst == 0) break; /* Could not allocate a new cluster (disk full) */ - if (clst == 1) ABORT(fp->fs, FR_INT_ERR); - if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); - fp->curr_clust = clst; /* Update current cluster */ - } -#if _FS_TINY - if (fp->fs->winsect == fp->dsect && move_window(fp->fs, 0)) /* Write back data buffer prior to following direct transfer */ - ABORT(fp->fs, FR_DISK_ERR); -#else - if (fp->flag & FA__DIRTY) { /* Write back data buffer prior to following direct transfer */ - if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) - ABORT(fp->fs, FR_DISK_ERR); - fp->flag &= ~FA__DIRTY; - } -#endif - sect = clust2sect(fp->fs, fp->curr_clust); /* Get current sector */ - if (!sect) ABORT(fp->fs, FR_INT_ERR); - sect += csect; - cc = btw / SS(fp->fs); /* When remaining bytes >= sector size, */ - if (cc) { /* Write maximum contiguous sectors directly */ - if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */ - cc = fp->fs->csize - csect; - if (disk_write(fp->fs->drv, wbuff, sect, (BYTE)cc) != RES_OK) - ABORT(fp->fs, FR_DISK_ERR); -#if _FS_TINY - if (fp->fs->winsect - sect < cc) { /* Refill sector cache if it gets dirty by the direct write */ - mem_cpy(fp->fs->win, wbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), SS(fp->fs)); - fp->fs->wflag = 0; - } -#else - if (fp->dsect - sect < cc) { /* Refill sector cache if it gets dirty by the direct write */ - mem_cpy(fp->buf, wbuff + ((fp->dsect - sect) * SS(fp->fs)), SS(fp->fs)); - fp->flag &= ~FA__DIRTY; - } -#endif - wcnt = SS(fp->fs) * cc; /* Number of bytes transferred */ - continue; - } -#if _FS_TINY - if (fp->fptr >= fp->fsize) { /* Avoid silly buffer filling at growing edge */ - if (move_window(fp->fs, 0)) ABORT(fp->fs, FR_DISK_ERR); - fp->fs->winsect = sect; - } -#else - if (fp->dsect != sect) { /* Fill sector buffer with file data */ - if (fp->fptr < fp->fsize && - disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK) - ABORT(fp->fs, FR_DISK_ERR); - } -#endif - fp->dsect = sect; - } - wcnt = SS(fp->fs) - (fp->fptr % SS(fp->fs));/* Put partial sector into file I/O buffer */ - if (wcnt > btw) wcnt = btw; -#if _FS_TINY - if (move_window(fp->fs, fp->dsect)) /* Move sector window */ - ABORT(fp->fs, FR_DISK_ERR); - mem_cpy(&fp->fs->win[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */ - fp->fs->wflag = 1; -#else - mem_cpy(&fp->buf[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */ - fp->flag |= FA__DIRTY; -#endif - } - - if (fp->fptr > fp->fsize) fp->fsize = fp->fptr; /* Update file size if needed */ - fp->flag |= FA__WRITTEN; /* Set file change flag */ - - LEAVE_FF(fp->fs, FR_OK); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Synchronize the File Object */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_sync ( - FIL *fp /* Pointer to the file object */ -) -{ - FRESULT res; - DWORD tim; - BYTE *dir; - - - res = validate(fp->fs, fp->id); /* Check validity of the object */ - if (res == FR_OK) { - if (fp->flag & FA__WRITTEN) { /* Has the file been written? */ -#if !_FS_TINY /* Write-back dirty buffer */ - if (fp->flag & FA__DIRTY) { - if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) - LEAVE_FF(fp->fs, FR_DISK_ERR); - fp->flag &= ~FA__DIRTY; - } -#endif - /* Update the directory entry */ - res = move_window(fp->fs, fp->dir_sect); - if (res == FR_OK) { - dir = fp->dir_ptr; - dir[DIR_Attr] |= AM_ARC; /* Set archive bit */ - ST_DWORD(dir+DIR_FileSize, fp->fsize); /* Update file size */ - ST_CLUST(dir, fp->org_clust); /* Update start cluster */ - tim = o9x_get_fattime(); /* Update updated time */ - ST_DWORD(dir+DIR_WrtTime, tim); - fp->flag &= ~FA__WRITTEN; - fp->fs->wflag = 1; - res = sync(fp->fs); - } - } - } - - LEAVE_FF(fp->fs, res); -} - -#endif /* !_FS_READONLY */ - - - - -/*-----------------------------------------------------------------------*/ -/* Close File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_close ( - FIL *fp /* Pointer to the file object to be closed */ -) -{ - FRESULT res; - -#if _FS_READONLY - FATFS *fs = fp->fs; - res = validate(fs, fp->id); - if (res == FR_OK) fp->fs = 0; /* Discard file object */ - LEAVE_FF(fs, res); - -#else - res = f_sync(fp); /* Flush cached data */ -#if _FS_SHARE - if (res == FR_OK) { /* Decrement open counter */ -#if _FS_REENTRANT - res = validate(fp->fs, fp->id); - if (res == FR_OK) { - res = dec_lock(fp->lockid); - unlock_fs(fp->fs, FR_OK); - } -#else - res = dec_lock(fp->lockid); -#endif - } -#endif - if (res == FR_OK) fp->fs = 0; /* Discard file object */ - return res; -#endif -} - - - - -/*-----------------------------------------------------------------------*/ -/* Current Drive/Directory Handlings */ -/*-----------------------------------------------------------------------*/ - -#if _FS_RPATH >= 1 - -FRESULT f_chdrive ( - BYTE drv /* Drive number */ -) -{ - if (drv >= _VOLUMES) return FR_INVALID_DRIVE; - - CurrVol = drv; - - return FR_OK; -} - - - -FRESULT f_chdir ( - const TCHAR *path /* Pointer to the directory path */ -) -{ - FRESULT res; - DIR dj; - DEF_NAMEBUF; - - - res = chk_mounted(&path, &dj.fs, 0); - if (res == FR_OK) { - INIT_BUF(dj); - res = follow_path(&dj, path); /* Follow the path */ - FREE_BUF(); - if (res == FR_OK) { /* Follow completed */ - if (!dj.dir) { - dj.fs->cdir = dj.sclust; /* Start directory itself */ - } else { - if (dj.dir[DIR_Attr] & AM_DIR) /* Reached to the directory */ - dj.fs->cdir = LD_CLUST(dj.dir); - else - res = FR_NO_PATH; /* Reached but a file */ - } - } - if (res == FR_NO_FILE) res = FR_NO_PATH; - } - - LEAVE_FF(dj.fs, res); -} - - -#if _FS_RPATH >= 2 -FRESULT f_getcwd ( - TCHAR *path, /* Pointer to the directory path */ - UINT sz_path /* Size of path */ -) -{ - FRESULT res; - DIR dj; - UINT i, n; - DWORD ccl; - TCHAR *tp; - FILINFO fno; - DEF_NAMEBUF; - - - *path = 0; - res = chk_mounted((const TCHAR**)&path, &dj.fs, 0); /* Get current volume */ - if (res == FR_OK) { - INIT_BUF(dj); - i = sz_path; /* Bottom of buffer (dir stack base) */ - dj.sclust = dj.fs->cdir; /* Start to follow upper dir from current dir */ - while ((ccl = dj.sclust) != 0) { /* Repeat while current dir is a sub-dir */ - res = dir_sdi(&dj, 1); /* Get parent dir */ - if (res != FR_OK) break; - res = dir_read(&dj); - if (res != FR_OK) break; - dj.sclust = LD_CLUST(dj.dir); /* Goto parent dir */ - res = dir_sdi(&dj, 0); - if (res != FR_OK) break; - do { /* Find the entry links to the child dir */ - res = dir_read(&dj); - if (res != FR_OK) break; - if (ccl == LD_CLUST(dj.dir)) break; /* Found the entry */ - res = dir_next(&dj, 0); - } while (res == FR_OK); - if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */ - if (res != FR_OK) break; -#if _USE_LFN - fno.lfname = path; - fno.lfsize = i; -#endif - get_fileinfo(&dj, &fno); /* Get the dir name and push it to the buffer */ - tp = fno.fname; - if (_USE_LFN && *path) tp = path; - for (n = 0; tp[n]; n++) ; - if (i < n + 3) { - res = FR_NOT_ENOUGH_CORE; break; - } - while (n) path[--i] = tp[--n]; - path[--i] = '/'; - } - tp = path; - if (res == FR_OK) { - *tp++ = '0' + CurrVol; /* Put drive number */ - *tp++ = ':'; - if (i == sz_path) { /* Root-dir */ - *tp++ = '/'; - } else { /* Sub-dir */ - do /* Add stacked path str */ - *tp++ = path[i++]; - while (i < sz_path); - } - } - *tp = 0; - FREE_BUF(); - } - - LEAVE_FF(dj.fs, res); -} -#endif /* _FS_RPATH >= 2 */ -#endif /* _FS_RPATH >= 1 */ - - - -#if _FS_MINIMIZE <= 2 -/*-----------------------------------------------------------------------*/ -/* Seek File R/W Pointer */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_lseek ( - FIL *fp, /* Pointer to the file object */ - DWORD ofs /* File pointer from top of file */ -) -{ - FRESULT res; - - - res = validate(fp->fs, fp->id); /* Check validity of the object */ - if (res != FR_OK) LEAVE_FF(fp->fs, res); - if (fp->flag & FA__ERROR) /* Check abort flag */ - LEAVE_FF(fp->fs, FR_INT_ERR); - -#if _USE_FASTSEEK - if (fp->cltbl) { /* Fast seek */ - DWORD cl, pcl, ncl, tcl, dsc, tlen, *tbl = fp->cltbl; - BYTE csc; - - tlen = *tbl++; - if (ofs == CREATE_LINKMAP) { /* Create link map table */ - cl = fp->org_clust; - if (cl) { - do { - if (tlen < 4) { /* Not enough table items */ - res = FR_NOT_ENOUGH_CORE; break; - } - tcl = cl; ncl = 0; - do { /* Get a fragment and store the top and length */ - pcl = cl; ncl++; - cl = get_fat(fp->fs, cl); - if (cl <= 1) ABORT(fp->fs, FR_INT_ERR); - if (cl == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); - } while (cl == pcl + 1); - *tbl++ = ncl; *tbl++ = tcl; - tlen -= 2; - } while (cl < fp->fs->n_fatent); - } - *tbl = 0; /* Terminate table */ - - } else { /* Fast seek */ - if (ofs > fp->fsize) /* Clip offset at the file size */ - ofs = fp->fsize; - fp->fptr = ofs; /* Set file pointer */ - if (ofs) { - dsc = (ofs - 1) / SS(fp->fs); - cl = dsc / fp->fs->csize; - for (;;) { - ncl = *tbl++; - if (!ncl) ABORT(fp->fs, FR_INT_ERR); - if (cl < ncl) break; - cl -= ncl; tbl++; - } - fp->curr_clust = cl + *tbl; - csc = (BYTE)(dsc & (fp->fs->csize - 1)); - dsc = clust2sect(fp->fs, fp->curr_clust); - if (!dsc) ABORT(fp->fs, FR_INT_ERR); - dsc += csc; - if (fp->fptr % SS(fp->fs) && dsc != fp->dsect) { -#if !_FS_TINY -#if !_FS_READONLY - if (fp->flag & FA__DIRTY) { /* Flush dirty buffer if needed */ - if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) - ABORT(fp->fs, FR_DISK_ERR); - fp->flag &= ~FA__DIRTY; - } -#endif - if (disk_read(fp->fs->drv, fp->buf, dsc, 1) != RES_OK) - ABORT(fp->fs, FR_DISK_ERR); -#endif - fp->dsect = dsc; - } - } - } - } else -#endif - - /* Normal Seek */ - { - DWORD clst, bcs, nsect, ifptr; - - if (ofs > fp->fsize /* In read-only mode, clip offset with the file size */ -#if !_FS_READONLY - && !(fp->flag & FA_WRITE) -#endif - ) ofs = fp->fsize; - - ifptr = fp->fptr; - fp->fptr = nsect = 0; - if (ofs) { - bcs = (DWORD)fp->fs->csize * SS(fp->fs); /* Cluster size (byte) */ - if (ifptr > 0 && - (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */ - fp->fptr = (ifptr - 1) & ~(bcs - 1); /* start from the current cluster */ - ofs -= fp->fptr; - clst = fp->curr_clust; - } else { /* When seek to back cluster, */ - clst = fp->org_clust; /* start from the first cluster */ -#if !_FS_READONLY - if (clst == 0) { /* If no cluster chain, create a new chain */ - clst = create_chain(fp->fs, 0); - if (clst == 1) ABORT(fp->fs, FR_INT_ERR); - if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); - fp->org_clust = clst; - } -#endif - fp->curr_clust = clst; - } - if (clst != 0) { - while (ofs > bcs) { /* Cluster following loop */ -#if !_FS_READONLY - if (fp->flag & FA_WRITE) { /* Check if in write mode or not */ - clst = create_chain(fp->fs, clst); /* Force stretch if in write mode */ - if (clst == 0) { /* When disk gets full, clip file size */ - ofs = bcs; break; - } - } else -#endif - clst = get_fat(fp->fs, clst); /* Follow cluster chain if not in write mode */ - if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); - if (clst <= 1 || clst >= fp->fs->n_fatent) ABORT(fp->fs, FR_INT_ERR); - fp->curr_clust = clst; - fp->fptr += bcs; - ofs -= bcs; - } - fp->fptr += ofs; - if (ofs % SS(fp->fs)) { - nsect = clust2sect(fp->fs, clst); /* Current sector */ - if (!nsect) ABORT(fp->fs, FR_INT_ERR); - nsect += ofs / SS(fp->fs); - } - } - } - if (fp->fptr % SS(fp->fs) && nsect != fp->dsect) { -#if !_FS_TINY -#if !_FS_READONLY - if (fp->flag & FA__DIRTY) { /* Flush dirty buffer if needed */ - if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) - ABORT(fp->fs, FR_DISK_ERR); - fp->flag &= ~FA__DIRTY; - } -#endif - if (disk_read(fp->fs->drv, fp->buf, nsect, 1) != RES_OK) - ABORT(fp->fs, FR_DISK_ERR); -#endif - fp->dsect = nsect; - } -#if !_FS_READONLY - if (fp->fptr > fp->fsize) { /* Set change flag if the file size is extended */ - fp->fsize = fp->fptr; - fp->flag |= FA__WRITTEN; - } -#endif - } - - LEAVE_FF(fp->fs, res); -} - - - -#if _FS_MINIMIZE <= 1 -/*-----------------------------------------------------------------------*/ -/* Create a Directroy Object */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_opendir ( - DIR *dj, /* Pointer to directory object to create */ - const TCHAR *path /* Pointer to the directory path */ -) -{ - FRESULT res; - DEF_NAMEBUF; - - - res = chk_mounted(&path, &dj->fs, 0); - if (res == FR_OK) { - INIT_BUF(*dj); - res = follow_path(dj, path); /* Follow the path to the directory */ - FREE_BUF(); - if (res == FR_OK) { /* Follow completed */ - if (dj->dir) { /* It is not the root dir */ - if (dj->dir[DIR_Attr] & AM_DIR) { /* The object is a directory */ - dj->sclust = LD_CLUST(dj->dir); - } else { /* The object is not a directory */ - res = FR_NO_PATH; - } - } - if (res == FR_OK) { - dj->id = dj->fs->id; - res = dir_sdi(dj, 0); /* Rewind dir */ - } - } - if (res == FR_NO_FILE) res = FR_NO_PATH; - } - - LEAVE_FF(dj->fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Read Directory Entry in Sequense */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_readdir ( - DIR *dj, /* Pointer to the open directory object */ - FILINFO *fno /* Pointer to file information to return */ -) -{ - FRESULT res; - DEF_NAMEBUF; - - - res = validate(dj->fs, dj->id); /* Check validity of the object */ - if (res == FR_OK) { - if (!fno) { - res = dir_sdi(dj, 0); /* Rewind the directory object */ - } else { - INIT_BUF(*dj); - res = dir_read(dj); /* Read an directory item */ - if (res == FR_NO_FILE) { /* Reached end of dir */ - dj->sect = 0; - res = FR_OK; - } - if (res == FR_OK) { /* A valid entry is found */ - get_fileinfo(dj, fno); /* Get the object information */ - res = dir_next(dj, 0); /* Increment index for next */ - if (res == FR_NO_FILE) { - dj->sect = 0; - res = FR_OK; - } - } - FREE_BUF(); - } - } - - LEAVE_FF(dj->fs, res); -} - - - -#if _FS_MINIMIZE == 0 -/*-----------------------------------------------------------------------*/ -/* Get File Status */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_stat ( - const TCHAR *path, /* Pointer to the file path */ - FILINFO *fno /* Pointer to file information to return */ -) -{ - FRESULT res; - DIR dj; - DEF_NAMEBUF; - - - res = chk_mounted(&path, &dj.fs, 0); - if (res == FR_OK) { - INIT_BUF(dj); - res = follow_path(&dj, path); /* Follow the file path */ - if (res == FR_OK) { /* Follow completed */ - if (dj.dir) /* Found an object */ - get_fileinfo(&dj, fno); - else /* It is root dir */ - res = FR_INVALID_NAME; - } - FREE_BUF(); - } - - LEAVE_FF(dj.fs, res); -} - - - -#if !_FS_READONLY -/*-----------------------------------------------------------------------*/ -/* Get Number of Free Clusters */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_getfree ( - const TCHAR *path, /* Pointer to the logical drive number (root dir) */ - DWORD *nclst, /* Pointer to the variable to return number of free clusters */ - FATFS **fatfs /* Pointer to pointer to corresponding file system object to return */ -) -{ - FRESULT res; - DWORD n, clst, sect, stat; - UINT i; - BYTE fat, *p; - - - /* Get drive number */ - res = chk_mounted(&path, fatfs, 0); - if (res == FR_OK) { - /* If free_clust is valid, return it without full cluster scan */ - if ((*fatfs)->free_clust <= (*fatfs)->n_fatent - 2) { - *nclst = (*fatfs)->free_clust; - } else { - /* Get number of free clusters */ - fat = (*fatfs)->fs_type; - n = 0; - if (fat == FS_FAT12) { - clst = 2; - do { - stat = get_fat(*fatfs, clst); - if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } - if (stat == 1) { res = FR_INT_ERR; break; } - if (stat == 0) n++; - } while (++clst < (*fatfs)->n_fatent); - } else { - clst = (*fatfs)->n_fatent; - sect = (*fatfs)->fatbase; - i = 0; p = 0; - do { - if (!i) { - res = move_window(*fatfs, sect++); - if (res != FR_OK) break; - p = (*fatfs)->win; - i = SS(*fatfs); - } - if (fat == FS_FAT16) { - if (LD_WORD(p) == 0) n++; - p += 2; i -= 2; - } else { - if ((LD_DWORD(p) & 0x0FFFFFFF) == 0) n++; - p += 4; i -= 4; - } - } while (--clst); - } - (*fatfs)->free_clust = n; - if (fat == FS_FAT32) (*fatfs)->fsi_flag = 1; - *nclst = n; - } - } - LEAVE_FF(*fatfs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Truncate File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_truncate ( - FIL *fp /* Pointer to the file object */ -) -{ - FRESULT res; - DWORD ncl; - - - res = validate(fp->fs, fp->id); /* Check validity of the object */ - if (res == FR_OK) { - if (fp->flag & FA__ERROR) { /* Check abort flag */ - res = FR_INT_ERR; - } else { - if (!(fp->flag & FA_WRITE)) /* Check access mode */ - res = FR_DENIED; - } - } - if (res == FR_OK) { - if (fp->fsize > fp->fptr) { - fp->fsize = fp->fptr; /* Set file size to current R/W point */ - fp->flag |= FA__WRITTEN; - if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */ - res = remove_chain(fp->fs, fp->org_clust); - fp->org_clust = 0; - } else { /* When truncate a part of the file, remove remaining clusters */ - ncl = get_fat(fp->fs, fp->curr_clust); - res = FR_OK; - if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR; - if (ncl == 1) res = FR_INT_ERR; - if (res == FR_OK && ncl < fp->fs->n_fatent) { - res = put_fat(fp->fs, fp->curr_clust, 0x0FFFFFFF); - if (res == FR_OK) res = remove_chain(fp->fs, ncl); - } - } - } - if (res != FR_OK) fp->flag |= FA__ERROR; - } - - LEAVE_FF(fp->fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Delete a File or Directory */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_unlink ( - const TCHAR *path /* Pointer to the file or directory path */ -) -{ - FRESULT res; - DIR dj, sdj; - BYTE *dir; - DWORD dclst; - DEF_NAMEBUF; - - - res = chk_mounted(&path, &dj.fs, 1); - if (res == FR_OK) { - INIT_BUF(dj); - res = follow_path(&dj, path); /* Follow the file path */ - if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) - res = FR_INVALID_NAME; /* Cannot remove dot entry */ -#if _FS_SHARE - if (res == FR_OK) res = chk_lock(&dj, 2); /* Cannot remove open file */ -#endif - if (res == FR_OK) { /* The object is accessible */ - dir = dj.dir; - if (!dir) { - res = FR_INVALID_NAME; /* Cannot remove the start directory */ - } else { - if (dir[DIR_Attr] & AM_RDO) - res = FR_DENIED; /* Cannot remove R/O object */ - } - dclst = LD_CLUST(dir); - if (res == FR_OK && (dir[DIR_Attr] & AM_DIR)) { /* Is it a sub-dir? */ - if (dclst < 2) { - res = FR_INT_ERR; - } else { - mem_cpy(&sdj, &dj, sizeof(DIR)); /* Check if the sub-dir is empty or not */ - sdj.sclust = dclst; - res = dir_sdi(&sdj, 2); /* Exclude dot entries */ - if (res == FR_OK) { - res = dir_read(&sdj); - if (res == FR_OK /* Not empty dir */ -#if _FS_RPATH - || dclst == sdj.fs->cdir /* Current dir */ -#endif - ) res = FR_DENIED; - if (res == FR_NO_FILE) res = FR_OK; /* Empty */ - } - } - } - if (res == FR_OK) { - res = dir_remove(&dj); /* Remove the directory entry */ - if (res == FR_OK) { - if (dclst) /* Remove the cluster chain if exist */ - res = remove_chain(dj.fs, dclst); - if (res == FR_OK) res = sync(dj.fs); - } - } - } - FREE_BUF(); - } - LEAVE_FF(dj.fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Create a Directory */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_mkdir ( - const TCHAR *path /* Pointer to the directory path */ -) -{ - FRESULT res; - DIR dj; - BYTE *dir, n; - DWORD dsc, dcl, pcl, tim = o9x_get_fattime(); - DEF_NAMEBUF; - - - res = chk_mounted(&path, &dj.fs, 1); - if (res == FR_OK) { - INIT_BUF(dj); - res = follow_path(&dj, path); /* Follow the file path */ - if (res == FR_OK) res = FR_EXIST; /* Any object with same name is already existing */ - if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NS] & NS_DOT)) - res = FR_INVALID_NAME; - if (res == FR_NO_FILE) { /* Can create a new directory */ - dcl = create_chain(dj.fs, 0); /* Allocate a cluster for the new directory table */ - res = FR_OK; - if (dcl == 0) res = FR_DENIED; /* No space to allocate a new cluster */ - if (dcl == 1) res = FR_INT_ERR; - if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR; - if (res == FR_OK) /* Flush FAT */ - res = move_window(dj.fs, 0); - if (res == FR_OK) { /* Initialize the new directory table */ - dsc = clust2sect(dj.fs, dcl); - dir = dj.fs->win; - mem_set(dir, 0, SS(dj.fs)); - mem_set(dir+DIR_Name, ' ', 8+3); /* Create "." entry */ - dir[DIR_Name] = '.'; - dir[DIR_Attr] = AM_DIR; - ST_DWORD(dir+DIR_WrtTime, tim); - ST_CLUST(dir, dcl); - mem_cpy(dir+32, dir, 32); /* Create ".." entry */ - dir[33] = '.'; pcl = dj.sclust; - if (dj.fs->fs_type == FS_FAT32 && pcl == dj.fs->dirbase) - pcl = 0; - ST_CLUST(dir+32, pcl); - for (n = dj.fs->csize; n; n--) { /* Write dot entries and clear following sectors */ - dj.fs->winsect = dsc++; - dj.fs->wflag = 1; - res = move_window(dj.fs, 0); - if (res != FR_OK) break; - mem_set(dir, 0, SS(dj.fs)); - } - } - if (res == FR_OK) res = dir_register(&dj); /* Register the object to the directoy */ - if (res != FR_OK) { - remove_chain(dj.fs, dcl); /* Could not register, remove cluster chain */ - } else { - dir = dj.dir; - dir[DIR_Attr] = AM_DIR; /* Attribute */ - ST_DWORD(dir+DIR_WrtTime, tim); /* Created time */ - ST_CLUST(dir, dcl); /* Table start cluster */ - dj.fs->wflag = 1; - res = sync(dj.fs); - } - } - FREE_BUF(); - } - - LEAVE_FF(dj.fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Change Attribute */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_chmod ( - const TCHAR *path, /* Pointer to the file path */ - BYTE value, /* Attribute bits */ - BYTE mask /* Attribute mask to change */ -) -{ - FRESULT res; - DIR dj; - BYTE *dir; - DEF_NAMEBUF; - - - res = chk_mounted(&path, &dj.fs, 1); - if (res == FR_OK) { - INIT_BUF(dj); - res = follow_path(&dj, path); /* Follow the file path */ - FREE_BUF(); - if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) - res = FR_INVALID_NAME; - if (res == FR_OK) { - dir = dj.dir; - if (!dir) { /* Is it a root directory? */ - res = FR_INVALID_NAME; - } else { /* File or sub directory */ - mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC; /* Valid attribute mask */ - dir[DIR_Attr] = (value & mask) | (dir[DIR_Attr] & (BYTE)~mask); /* Apply attribute change */ - dj.fs->wflag = 1; - res = sync(dj.fs); - } - } - } - - LEAVE_FF(dj.fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Change Timestamp */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_utime ( - const TCHAR *path, /* Pointer to the file/directory name */ - const FILINFO *fno /* Pointer to the time stamp to be set */ -) -{ - FRESULT res; - DIR dj; - BYTE *dir; - DEF_NAMEBUF; - - - res = chk_mounted(&path, &dj.fs, 1); - if (res == FR_OK) { - INIT_BUF(dj); - res = follow_path(&dj, path); /* Follow the file path */ - FREE_BUF(); - if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) - res = FR_INVALID_NAME; - if (res == FR_OK) { - dir = dj.dir; - if (!dir) { /* Root directory */ - res = FR_INVALID_NAME; - } else { /* File or sub-directory */ - ST_WORD(dir+DIR_WrtTime, fno->ftime); - ST_WORD(dir+DIR_WrtDate, fno->fdate); - dj.fs->wflag = 1; - res = sync(dj.fs); - } - } - } - - LEAVE_FF(dj.fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Rename File/Directory */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_rename ( - const TCHAR *path_old, /* Pointer to the old name */ - const TCHAR *path_new /* Pointer to the new name */ -) -{ - FRESULT res; - DIR djo, djn; - BYTE buf[21], *dir; - DWORD dw; - DEF_NAMEBUF; - - - res = chk_mounted(&path_old, &djo.fs, 1); - if (res == FR_OK) { - djn.fs = djo.fs; - INIT_BUF(djo); - res = follow_path(&djo, path_old); /* Check old object */ - if (_FS_RPATH && res == FR_OK && (djo.fn[NS] & NS_DOT)) - res = FR_INVALID_NAME; -#if _FS_SHARE - if (res == FR_OK) res = chk_lock(&djo, 2); -#endif - if (res == FR_OK) { /* Old object is found */ - if (!djo.dir) { /* Is root dir? */ - res = FR_NO_FILE; - } else { - mem_cpy(buf, djo.dir+DIR_Attr, 21); /* Save the object information except for name */ - mem_cpy(&djn, &djo, sizeof(DIR)); /* Check new object */ - res = follow_path(&djn, path_new); - if (res == FR_OK) res = FR_EXIST; /* The new object name is already existing */ - if (res == FR_NO_FILE) { /* Is it a valid path and no name collision? */ -/* Start critical section that any interruption or error can cause cross-link */ - res = dir_register(&djn); /* Register the new entry */ - if (res == FR_OK) { - dir = djn.dir; /* Copy object information except for name */ - mem_cpy(dir+13, buf+2, 19); - dir[DIR_Attr] = buf[0] | AM_ARC; - djo.fs->wflag = 1; - if (djo.sclust != djn.sclust && (dir[DIR_Attr] & AM_DIR)) { /* Update .. entry in the directory if needed */ - dw = clust2sect(djn.fs, LD_CLUST(dir)); - if (!dw) { - res = FR_INT_ERR; - } else { - res = move_window(djn.fs, dw); - dir = djn.fs->win+32; /* .. entry */ - if (res == FR_OK && dir[1] == '.') { - dw = (djn.fs->fs_type == FS_FAT32 && djn.sclust == djn.fs->dirbase) ? 0 : djn.sclust; - ST_CLUST(dir, dw); - djn.fs->wflag = 1; - } - } - } - if (res == FR_OK) { - res = dir_remove(&djo); /* Remove old entry */ - if (res == FR_OK) - res = sync(djo.fs); - } - } -/* End critical section */ - } - } - } - FREE_BUF(); - } - LEAVE_FF(djo.fs, res); -} - -#endif /* !_FS_READONLY */ -#endif /* _FS_MINIMIZE == 0 */ -#endif /* _FS_MINIMIZE <= 1 */ -#endif /* _FS_MINIMIZE <= 2 */ - - - -/*-----------------------------------------------------------------------*/ -/* Forward data to the stream directly (available on only tiny cfg) */ -/*-----------------------------------------------------------------------*/ -#if _USE_FORWARD && _FS_TINY - -FRESULT f_forward ( - FIL *fp, /* Pointer to the file object */ - UINT (*func)(const BYTE*,UINT), /* Pointer to the streaming function */ - UINT btr, /* Number of bytes to forward */ - UINT *bf /* Pointer to number of bytes forwarded */ -) -{ - FRESULT res; - DWORD remain, clst, sect; - UINT rcnt; - BYTE csect; - - - *bf = 0; /* Initialize byte counter */ - - res = validate(fp->fs, fp->id); /* Check validity of the object */ - if (res != FR_OK) LEAVE_FF(fp->fs, res); - if (fp->flag & FA__ERROR) /* Check error flag */ - LEAVE_FF(fp->fs, FR_INT_ERR); - if (!(fp->flag & FA_READ)) /* Check access mode */ - LEAVE_FF(fp->fs, FR_DENIED); - - remain = fp->fsize - fp->fptr; - if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ - - for ( ; btr && (*func)(0, 0); /* Repeat until all data transferred or stream becomes busy */ - fp->fptr += rcnt, *bf += rcnt, btr -= rcnt) { - csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ - if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ - if (!csect) { /* On the cluster boundary? */ - clst = (fp->fptr == 0) ? /* On the top of the file? */ - fp->org_clust : get_fat(fp->fs, fp->curr_clust); - if (clst <= 1) ABORT(fp->fs, FR_INT_ERR); - if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); - fp->curr_clust = clst; /* Update current cluster */ - } - } - sect = clust2sect(fp->fs, fp->curr_clust); /* Get current data sector */ - if (!sect) ABORT(fp->fs, FR_INT_ERR); - sect += csect; - if (move_window(fp->fs, sect)) /* Move sector window */ - ABORT(fp->fs, FR_DISK_ERR); - fp->dsect = sect; - rcnt = SS(fp->fs) - (WORD)(fp->fptr % SS(fp->fs)); /* Forward data from sector window */ - if (rcnt > btr) rcnt = btr; - rcnt = (*func)(&fp->fs->win[(WORD)fp->fptr % SS(fp->fs)], rcnt); - if (!rcnt) ABORT(fp->fs, FR_INT_ERR); - } - - LEAVE_FF(fp->fs, FR_OK); -} -#endif /* _USE_FORWARD */ - - - -#if _USE_MKFS && !_FS_READONLY -/*-----------------------------------------------------------------------*/ -/* Create File System on the Drive */ -/*-----------------------------------------------------------------------*/ -#define N_ROOTDIR 512 /* Multiple of 32 */ -#define N_FATS 1 /* 1 or 2 */ - - -FRESULT f_mkfs ( - BYTE drv, /* Logical drive number */ - BYTE sfd, /* Partitioning rule 0:FDISK, 1:SFD */ - UINT au /* Allocation unit size [bytes] */ -) -{ - static const WORD vst[] = { 1024, 512, 256, 128, 64, 32, 16, 8, 4, 2, 0}; - static const WORD cst[] = {32768, 16384, 8192, 4096, 2048, 16384, 8192, 4096, 2048, 1024, 512}; - BYTE fmt, md, *tbl; - DWORD n_clst, vs, n, wsect; - UINT i; - DWORD b_vol, b_fat, b_dir, b_data; /* Offset (LBA) */ - DWORD n_vol, n_rsv, n_fat, n_dir; /* Size */ - FATFS *fs; - DSTATUS stat; - - - /* Check mounted drive and clear work area */ - if (drv >= _VOLUMES) return FR_INVALID_DRIVE; - fs = FatFs[drv]; - if (!fs) return FR_NOT_ENABLED; - fs->fs_type = 0; - drv = LD2PD(drv); - - /* Get disk statics */ - stat = disk_initialize(drv); - if (stat & STA_NOINIT) return FR_NOT_READY; - if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; -#if _MAX_SS != 512 /* Get disk sector size */ - if (disk_ioctl(drv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK) - return FR_DISK_ERR; -#endif - if (disk_ioctl(drv, GET_SECTOR_COUNT, (BYTE*)&n_vol) != RES_OK || n_vol < 128) - return FR_DISK_ERR; - b_vol = (sfd) ? 0 : 63; /* Volume start sector */ - n_vol -= b_vol; - if (au & (au - 1)) au = 0; /* Check validity of the allocation unit size */ - if (!au) { /* AU auto selection */ - vs = n_vol / (2000 / (SS(fs) / 512)); - for (i = 0; vs < vst[i]; i++) ; - au = cst[i]; - } - au /= SS(fs); /* Number of sectors per cluster */ - if (au == 0) au = 1; - if (au > 128) au = 128; - - /* Pre-compute number of clusters and FAT syb-type */ - n_clst = n_vol / au; - fmt = FS_FAT12; - if (n_clst >= MIN_FAT16) fmt = FS_FAT16; - if (n_clst >= MIN_FAT32) fmt = FS_FAT32; - - /* Determine offset and size of FAT structure */ - if (fmt == FS_FAT32) { - n_fat = ((n_clst * 4) + 8 + SS(fs) - 1) / SS(fs); - n_rsv = 32; - n_dir = 0; - } else { - n_fat = (fmt == FS_FAT12) ? (n_clst * 3 + 1) / 2 + 3 : (n_clst * 2) + 4; - n_fat = (n_fat + SS(fs) - 1) / SS(fs); - n_rsv = 1; - n_dir = N_ROOTDIR * 32UL / SS(fs); - } - b_fat = b_vol + n_rsv; /* FAT area start sector */ - b_dir = b_fat + n_fat * N_FATS; /* Directory area start sector */ - b_data = b_dir + n_dir; /* Data area start sector */ - if (n_vol < b_data + au) return FR_MKFS_ABORTED; /* Too small volume */ - - /* Align data start sector to erase block boundary (for flash memory media) */ - if (disk_ioctl(drv, GET_BLOCK_SIZE, (BYTE*)&n) != RES_OK || !n || n > 32768) n = 1; - n = (b_data + n - 1) & ~(n - 1); /* Next nearest erase block from current data start */ - n = (n - b_data) / N_FATS; - if (fmt == FS_FAT32) { /* FAT32: Move FAT offset */ - n_rsv += n; - b_fat += n; - } else { /* FAT12/16: Expand FAT size */ - n_fat += n; - } - - /* Determine number of cluster and final check of validity of the FAT sub-type */ - n_clst = (n_vol - n_rsv - n_fat * N_FATS - n_dir) / au; - if ( (fmt == FS_FAT16 && n_clst < MIN_FAT16) - || (fmt == FS_FAT32 && n_clst < MIN_FAT32)) - return FR_MKFS_ABORTED; - - /* Create partition table if required */ - if (sfd) { - md = 0xF0; - } else { - DWORD n_disk = b_vol + n_vol; - - mem_set(fs->win, 0, SS(fs)); - tbl = fs->win+MBR_Table; - ST_DWORD(tbl, 0x00010180); /* Partition start in CHS */ - if (n_disk < 63UL * 255 * 1024) { /* Partition end in CHS */ - n_disk = n_disk / 63 / 255; - tbl[7] = (BYTE)n_disk; - tbl[6] = (BYTE)((n_disk >> 2) | 63); - } else { - ST_WORD(&tbl[6], 0xFFFF); - } - tbl[5] = 254; - if (fmt != FS_FAT32) /* System ID */ - tbl[4] = (n_vol < 0x10000) ? 0x04 : 0x06; - else - tbl[4] = 0x0c; - ST_DWORD(tbl+8, 63); /* Partition start in LBA */ - ST_DWORD(tbl+12, n_vol); /* Partition size in LBA */ - ST_WORD(tbl+64, 0xAA55); /* Signature */ - if (disk_write(drv, fs->win, 0, 1) != RES_OK) - return FR_DISK_ERR; - md = 0xF8; - } - - /* Create volume boot record */ - tbl = fs->win; /* Clear sector */ - mem_set(tbl, 0, SS(fs)); - mem_cpy(tbl, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot code, OEM name */ - i = SS(fs); /* Sector size */ - ST_WORD(tbl+BPB_BytsPerSec, i); - tbl[BPB_SecPerClus] = (BYTE)au; /* Sectors per cluster */ - ST_WORD(tbl+BPB_RsvdSecCnt, n_rsv); /* Reserved sectors */ - tbl[BPB_NumFATs] = N_FATS; /* Number of FATs */ - i = (fmt == FS_FAT32) ? 0 : N_ROOTDIR; /* Number of rootdir entries */ - ST_WORD(tbl+BPB_RootEntCnt, i); - if (n_vol < 0x10000) { /* Number of total sectors */ - ST_WORD(tbl+BPB_TotSec16, n_vol); - } else { - ST_DWORD(tbl+BPB_TotSec32, n_vol); - } - tbl[BPB_Media] = md; /* Media descriptor */ - ST_WORD(tbl+BPB_SecPerTrk, 63); /* Number of sectors per track */ - ST_WORD(tbl+BPB_NumHeads, 255); /* Number of heads */ - ST_DWORD(tbl+BPB_HiddSec, b_vol); /* Hidden sectors */ - n = o9x_get_fattime(); /* Use current time as VSN */ - if (fmt == FS_FAT32) { - ST_DWORD(tbl+BS_VolID32, n); /* VSN */ - ST_DWORD(tbl+BPB_FATSz32, n_fat); /* Number of sectors per FAT */ - ST_DWORD(tbl+BPB_RootClus, 2); /* Root directory start cluster (2) */ - ST_WORD(tbl+BPB_FSInfo, 1); /* FSInfo record offset (VBR+1) */ - ST_WORD(tbl+BPB_BkBootSec, 6); /* Backup boot record offset (VBR+6) */ - tbl[BS_DrvNum32] = 0x80; /* Drive number */ - tbl[BS_BootSig32] = 0x29; /* Extended boot signature */ - mem_cpy(tbl+BS_VolLab32, "NO NAME " "FAT32 ", 19); /* Volume label, FAT signature */ - } else { - ST_DWORD(tbl+BS_VolID, n); /* VSN */ - ST_WORD(tbl+BPB_FATSz16, n_fat); /* Number of sectors per FAT */ - tbl[BS_DrvNum] = 0x80; /* Drive number */ - tbl[BS_BootSig] = 0x29; /* Extended boot signature */ - mem_cpy(tbl+BS_VolLab, "NO NAME " "FAT ", 19); /* Volume label, FAT signature */ - } - ST_WORD(tbl+BS_55AA, 0xAA55); /* Signature (Offset is fixed here regardless of sector size) */ - if (disk_write(drv, tbl, b_vol, 1) != RES_OK)/* Write original (VBR) */ - return FR_DISK_ERR; - if (fmt == FS_FAT32) /* Write backup (VBR+6) */ - disk_write(drv, tbl, b_vol + 6, 1); - - /* Initialize FAT area */ - wsect = b_fat; - for (i = 0; i < N_FATS; i++) { - mem_set(tbl, 0, SS(fs)); /* 1st sector of the FAT */ - n = md; /* Media descriptor byte */ - if (fmt != FS_FAT32) { - n |= (fmt == FS_FAT12) ? 0x00FFFF00 : 0xFFFFFF00; - ST_DWORD(tbl+0, n); /* Reserve cluster #0-1 (FAT12/16) */ - } else { - n |= 0xFFFFFF00; - ST_DWORD(tbl+0, n); /* Reserve cluster #0-1 (FAT32) */ - ST_DWORD(tbl+4, 0xFFFFFFFF); - ST_DWORD(tbl+8, 0x0FFFFFFF); /* Reserve cluster #2 for root dir */ - } - if (disk_write(drv, tbl, wsect++, 1) != RES_OK) - return FR_DISK_ERR; - mem_set(tbl, 0, SS(fs)); /* Fill following FAT entries with zero */ - for (n = 1; n < n_fat; n++) { /* This loop may take a time on FAT32 volume due to many single sector write */ - if (disk_write(drv, tbl, wsect++, 1) != RES_OK) - return FR_DISK_ERR; - } - } - - /* Initialize root directory */ - i = (fmt == FS_FAT32) ? au : n_dir; - do { - if (disk_write(drv, tbl, wsect++, 1) != RES_OK) - return FR_DISK_ERR; - } while (--i); - -#if _USE_ERASE /* Erase data area if needed */ - { - DWORD eb[2]; - - eb[0] = wsect; eb[1] = wsect + n_clst * au - 1; - disk_ioctl(drv, CTRL_ERASE_SECTOR, eb); - } -#endif - - /* Create FSInfo if needed */ - if (fmt == FS_FAT32) { - ST_WORD(tbl+BS_55AA, 0xAA55); - ST_DWORD(tbl+FSI_LeadSig, 0x41615252); - ST_DWORD(tbl+FSI_StrucSig, 0x61417272); - ST_DWORD(tbl+FSI_Free_Count, n_clst - 1); - ST_DWORD(tbl+FSI_Nxt_Free, 0xFFFFFFFF); - disk_write(drv, tbl, b_vol + 1, 1); /* Write original (VBR+1) */ - disk_write(drv, tbl, b_vol + 7, 1); /* Write backup (VBR+7) */ - } - - return (disk_ioctl(drv, CTRL_SYNC, (BYTE*)0) == RES_OK) ? FR_OK : FR_DISK_ERR; -} - -#endif /* _USE_MKFS && !_FS_READONLY */ - -#if _USE_LFN == 3 /* LFN with a working buffer on the heap */ -/*------------------------------------------------------------------------*/ -/* Allocate a memory block */ -/*------------------------------------------------------------------------*/ -/* If a NULL is returned, the file function fails with FR_NOT_ENOUGH_CORE. - */ - -void* ff_memalloc ( /* Returns pointer to the allocated memory block */ - UINT size /* Number of bytes to allocate */ - ) -{ - return malloc(size); -} - - -/*------------------------------------------------------------------------*/ -/* Free a memory block */ -/*------------------------------------------------------------------------*/ - -void ff_memfree( - void* mblock /* Pointer to the memory block to free */ - ) -{ - free(mblock); -} - -#endif - - - - -#if _USE_STRFUNC -/*-----------------------------------------------------------------------*/ -/* Get a string from the file */ -/*-----------------------------------------------------------------------*/ -TCHAR* f_gets ( - TCHAR* buff, /* Pointer to the string buffer to read */ - int len, /* Size of string buffer (characters) */ - FIL* fil /* Pointer to the file object */ -) -{ - int n = 0; - TCHAR c, *p = buff; - BYTE s[2]; - UINT rc; - - - while (n < len - 1) { /* Read bytes until buffer gets filled */ - f_read(fil, s, 1, &rc); - if (rc != 1) break; /* Break on EOF or error */ - c = s[0]; -#if _LFN_UNICODE /* Read a character in UTF-8 encoding */ - if (c >= 0x80) { - if (c < 0xC0) continue; /* Skip stray trailer */ - if (c < 0xE0) { /* Two-byte sequense */ - f_read(fil, s, 1, &rc); - if (rc != 1) break; - c = ((c & 0x1F) << 6) | (s[0] & 0x3F); - if (c < 0x80) c = '?'; - } else { - if (c < 0xF0) { /* Three-byte sequense */ - f_read(fil, s, 2, &rc); - if (rc != 2) break; - c = (c << 12) | ((s[0] & 0x3F) << 6) | (s[1] & 0x3F); - if (c < 0x800) c = '?'; - } else { /* Reject four-byte sequense */ - c = '?'; - } - } - } -#endif -#if _USE_STRFUNC >= 2 - if (c == '\r') continue; /* Strip '\r' */ -#endif - *p++ = c; - n++; - if (c == '\n') break; /* Break on EOL */ - } - *p = 0; - return n ? buff : 0; /* When no data read (eof or error), return with error. */ -} - - - -#if !_FS_READONLY -#include -/*-----------------------------------------------------------------------*/ -/* Put a character to the file */ -/*-----------------------------------------------------------------------*/ -int f_putc ( - TCHAR c, /* A character to be output */ - FIL* fil /* Pointer to the file object */ -) -{ - UINT bw, btw; - BYTE s[3]; - - -#if _USE_STRFUNC >= 2 - if (c == '\n') f_putc ('\r', fil); /* LF -> CRLF conversion */ -#endif - -#if _LFN_UNICODE /* Write the character in UTF-8 encoding */ - if (c < 0x80) { /* 7-bit */ - s[0] = (BYTE)c; - btw = 1; - } else { - if (c < 0x800) { /* 11-bit */ - s[0] = (BYTE)(0xC0 | (c >> 6)); - s[1] = (BYTE)(0x80 | (c & 0x3F)); - btw = 2; - } else { /* 16-bit */ - s[0] = (BYTE)(0xE0 | (c >> 12)); - s[1] = (BYTE)(0x80 | ((c >> 6) & 0x3F)); - s[2] = (BYTE)(0x80 | (c & 0x3F)); - btw = 3; - } - } -#else /* Write the character without conversion */ - s[0] = (BYTE)c; - btw = 1; -#endif - f_write(fil, s, btw, &bw); /* Write the char to the file */ - return (bw == btw) ? 1 : EOF; /* Return the result */ -} - - - - -/*-----------------------------------------------------------------------*/ -/* Put a string to the file */ -/*-----------------------------------------------------------------------*/ -int f_puts ( - const TCHAR* str, /* Pointer to the string to be output */ - FIL* fil /* Pointer to the file object */ -) -{ - int n; - - - for (n = 0; *str; str++, n++) { - if (f_putc(*str, fil) == EOF) return EOF; - } - return n; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Put a formatted string to the file */ -/*-----------------------------------------------------------------------*/ -int f_printf ( - FIL* fil, /* Pointer to the file object */ - const TCHAR* str, /* Pointer to the format string */ - ... /* Optional arguments... */ -) -{ - va_list arp; - BYTE f, r; - UINT i, w; - ULONG val; - TCHAR c, d, s[16]; - int res, cc; - - - va_start(arp, str); - - for (cc = res = 0; cc != EOF; res += cc) { - c = *str++; - if (c == 0) break; /* End of string */ - if (c != '%') { /* Non escape character */ - cc = f_putc(c, fil); - if (cc != EOF) cc = 1; - continue; - } - w = f = 0; - c = *str++; - if (c == '0') { /* Flag: '0' padding */ - f = 1; c = *str++; - } - while (IsDigit(c)) { /* Precision */ - w = w * 10 + c - '0'; - c = *str++; - } - if (c == 'l' || c == 'L') { /* Prefix: Size is long int */ - f |= 2; c = *str++; - } - if (!c) break; - d = c; - if (IsLower(d)) d -= 0x20; - switch (d) { /* Type is... */ - case 'S' : /* String */ - cc = f_puts(va_arg(arp, TCHAR*), fil); continue; - case 'C' : /* Character */ - cc = f_putc((TCHAR)va_arg(arp, int), fil); continue; - case 'B' : /* Binary */ - r = 2; break; - case 'O' : /* Octal */ - r = 8; break; - case 'D' : /* Signed decimal */ - case 'U' : /* Unsigned decimal */ - r = 10; break; - case 'X' : /* Hexdecimal */ - r = 16; break; - default: /* Unknown */ - cc = f_putc(c, fil); continue; - } - - /* Get an argument */ - val = (f & 2) ? va_arg(arp, long) : ((d == 'D') ? (long)va_arg(arp, int) : va_arg(arp, unsigned int)); - if (d == 'D' && (val & 0x80000000)) { - val = 0 - val; - f |= 4; - } - /* Put it in numeral string */ - i = 0; - do { - d = (TCHAR)(val % r); val /= r; - if (d > 9) { - d += 7; - if (c == 'x') d += 0x20; - } - s[i++] = d + '0'; - } while (val && i < sizeof(s) / sizeof(s[0])); - if (f & 4) s[i++] = '-'; - cc = 0; - while (i < w-- && cc != EOF) { - cc = f_putc((TCHAR)((f & 1) ? '0' : ' '), fil); - res++; - } - do { - cc = f_putc(s[--i], fil); - res++; - } while (i && cc != EOF); - if (cc != EOF) cc = 0; - } - - va_end(arp); - return (cc == EOF) ? cc : res; -} - -#endif /* !_FS_READONLY */ -#endif /* _USE_STRFUNC */ diff --git a/radio/bootloader/ff_lfn.cpp b/radio/bootloader/ff_lfn.cpp deleted file mode 100644 index 377cc8ce3..000000000 --- a/radio/bootloader/ff_lfn.cpp +++ /dev/null @@ -1,113 +0,0 @@ -/**************************************************************************** -* Copyright (c) 2014 by Michael Blandford. All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* 1. Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* 3. Neither the name of the author nor the names of its contributors may -* be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL -* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -* SUCH DAMAGE. -* -**************************************************************************** -* Other Authors: - * - Andre Bernet - * - Bertrand Songis - * - Bryan J. Rentoul (Gruvin) - * - Cameron Weeks - * - Erez Raviv - * - Jean-Pierre Parisy - * - Karl Szmutny - * - Michal Hlavinka - * - Pat Mackenzie - * - Philip Moss - * - Rob Thomson - * - Romolo Manfredini - * - Thomas Husterer -* -****************************************************************************/ - -#include "ff.h" - -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP437(0x80-0xFF) to Unicode conversion table */ - 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, - 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, - 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, - 0x00FF, 0x00D6, 0x00DC, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, - 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, - 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, - 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, - 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, - 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, - 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 -}; - - -WCHAR ff_convert ( /* Converted character, Returns zero on error */ - WCHAR chr, /* Character code to be converted */ - UINT dir /* 0: Unicode to OEMCP, 1: OEMCP to Unicode */ -) -{ - WCHAR c; - - - if (chr < 0x80) { /* ASCII */ - c = chr; - - } else { - if (dir) { /* OEMCP to Unicode */ - c = (chr >= 0x100) ? 0 : Tbl[chr - 0x80]; - - } else { /* Unicode to OEMCP */ - for (c = 0; c < 0x80; c++) { - if (chr == Tbl[c]) break; - } - c = (c + 0x80) & 0xFF; - } - } - - return c; -} - - -WCHAR ff_wtoupper ( /* Upper converted character */ - WCHAR chr /* Input character */ -) -{ - static const WCHAR tbl_lower[] = { 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0xA1, 0x00A2, 0x00A3, 0x00A5, 0x00AC, 0x00AF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0x0FF, 0x101, 0x103, 0x105, 0x107, 0x109, 0x10B, 0x10D, 0x10F, 0x111, 0x113, 0x115, 0x117, 0x119, 0x11B, 0x11D, 0x11F, 0x121, 0x123, 0x125, 0x127, 0x129, 0x12B, 0x12D, 0x12F, 0x131, 0x133, 0x135, 0x137, 0x13A, 0x13C, 0x13E, 0x140, 0x142, 0x144, 0x146, 0x148, 0x14B, 0x14D, 0x14F, 0x151, 0x153, 0x155, 0x157, 0x159, 0x15B, 0x15D, 0x15F, 0x161, 0x163, 0x165, 0x167, 0x169, 0x16B, 0x16D, 0x16F, 0x171, 0x173, 0x175, 0x177, 0x17A, 0x17C, 0x17E, 0x192, 0x3B1, 0x3B2, 0x3B3, 0x3B4, 0x3B5, 0x3B6, 0x3B7, 0x3B8, 0x3B9, 0x3BA, 0x3BB, 0x3BC, 0x3BD, 0x3BE, 0x3BF, 0x3C0, 0x3C1, 0x3C3, 0x3C4, 0x3C5, 0x3C6, 0x3C7, 0x3C8, 0x3C9, 0x3CA, 0x430, 0x431, 0x432, 0x433, 0x434, 0x435, 0x436, 0x437, 0x438, 0x439, 0x43A, 0x43B, 0x43C, 0x43D, 0x43E, 0x43F, 0x440, 0x441, 0x442, 0x443, 0x444, 0x445, 0x446, 0x447, 0x448, 0x449, 0x44A, 0x44B, 0x44C, 0x44D, 0x44E, 0x44F, 0x451, 0x452, 0x453, 0x454, 0x455, 0x456, 0x457, 0x458, 0x459, 0x45A, 0x45B, 0x45C, 0x45E, 0x45F, 0x2170, 0x2171, 0x2172, 0x2173, 0x2174, 0x2175, 0x2176, 0x2177, 0x2178, 0x2179, 0x217A, 0x217B, 0x217C, 0x217D, 0x217E, 0x217F, 0xFF41, 0xFF42, 0xFF43, 0xFF44, 0xFF45, 0xFF46, 0xFF47, 0xFF48, 0xFF49, 0xFF4A, 0xFF4B, 0xFF4C, 0xFF4D, 0xFF4E, 0xFF4F, 0xFF50, 0xFF51, 0xFF52, 0xFF53, 0xFF54, 0xFF55, 0xFF56, 0xFF57, 0xFF58, 0xFF59, 0xFF5A, 0 }; - static const WCHAR tbl_upper[] = { 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x21, 0xFFE0, 0xFFE1, 0xFFE5, 0xFFE2, 0xFFE3, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0x178, 0x100, 0x102, 0x104, 0x106, 0x108, 0x10A, 0x10C, 0x10E, 0x110, 0x112, 0x114, 0x116, 0x118, 0x11A, 0x11C, 0x11E, 0x120, 0x122, 0x124, 0x126, 0x128, 0x12A, 0x12C, 0x12E, 0x130, 0x132, 0x134, 0x136, 0x139, 0x13B, 0x13D, 0x13F, 0x141, 0x143, 0x145, 0x147, 0x14A, 0x14C, 0x14E, 0x150, 0x152, 0x154, 0x156, 0x158, 0x15A, 0x15C, 0x15E, 0x160, 0x162, 0x164, 0x166, 0x168, 0x16A, 0x16C, 0x16E, 0x170, 0x172, 0x174, 0x176, 0x179, 0x17B, 0x17D, 0x191, 0x391, 0x392, 0x393, 0x394, 0x395, 0x396, 0x397, 0x398, 0x399, 0x39A, 0x39B, 0x39C, 0x39D, 0x39E, 0x39F, 0x3A0, 0x3A1, 0x3A3, 0x3A4, 0x3A5, 0x3A6, 0x3A7, 0x3A8, 0x3A9, 0x3AA, 0x410, 0x411, 0x412, 0x413, 0x414, 0x415, 0x416, 0x417, 0x418, 0x419, 0x41A, 0x41B, 0x41C, 0x41D, 0x41E, 0x41F, 0x420, 0x421, 0x422, 0x423, 0x424, 0x425, 0x426, 0x427, 0x428, 0x429, 0x42A, 0x42B, 0x42C, 0x42D, 0x42E, 0x42F, 0x401, 0x402, 0x403, 0x404, 0x405, 0x406, 0x407, 0x408, 0x409, 0x40A, 0x40B, 0x40C, 0x40E, 0x40F, 0x2160, 0x2161, 0x2162, 0x2163, 0x2164, 0x2165, 0x2166, 0x2167, 0x2168, 0x2169, 0x216A, 0x216B, 0x216C, 0x216D, 0x216E, 0x216F, 0xFF21, 0xFF22, 0xFF23, 0xFF24, 0xFF25, 0xFF26, 0xFF27, 0xFF28, 0xFF29, 0xFF2A, 0xFF2B, 0xFF2C, 0xFF2D, 0xFF2E, 0xFF2F, 0xFF30, 0xFF31, 0xFF32, 0xFF33, 0xFF34, 0xFF35, 0xFF36, 0xFF37, 0xFF38, 0xFF39, 0xFF3A, 0 }; - int i; - - - for (i = 0; tbl_lower[i] && chr != tbl_lower[i]; i++) ; - - return tbl_lower[i] ? tbl_upper[i] : chr; -} - - diff --git a/radio/bootloader/include/diskio.h b/radio/bootloader/include/diskio.h deleted file mode 100644 index e091b709c..000000000 --- a/radio/bootloader/include/diskio.h +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Authors (alphabetical order) - * - Bertrand Songis - * - Bryan J. Rentoul (Gruvin) - * - Cameron Weeks - * - Erez Raviv - * - Jean-Pierre Parisy - * - Karl Szmutny - * - Michael Blandford - * - Michal Hlavinka - * - Pat Mackenzie - * - Philip Moss - * - Rob Thomson - * - Romolo Manfredini - * - Thomas Husterer - * - * open9x is based on code named - * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, - * er9x by Erez Raviv: http://code.google.com/p/er9x/, - * and the original (and ongoing) project by - * Thomas Husterer, th9x: http://code.google.com/p/th9x/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/*----------------------------------------------------------------------- -/ Low level disk interface modlue include file (C)ChaN, 2010 -/-----------------------------------------------------------------------*/ - -#ifndef DEF_DISKIO -#define DEF_DISKIO - -#ifdef PCBSKY -#include "board.h" -#endif - -#ifdef PCBTARANIS -#include "stm32f2xx.h" -#endif - -#if !defined(SIMU) -#include "core_cm3.h" -#endif -#include "integer.h" - -#define DN_MCI 0 /* Physical drive number for MCI */ -#define DN_NAND 1 /* Physical drive number for NAND flash */ - - -/* These functions are defined in asmfunc.S */ -void Copy_al2un (BYTE *dst, const DWORD *src, int count); /* Copy aligned to unaligned. */ -void Copy_un2al (DWORD *dst, const BYTE *src, int count); /* Copy unaligned to aligned. */ - - -/* Status of Disk Functions */ -typedef BYTE DSTATUS; - -/* Results of Disk Functions */ -typedef enum { - RES_OK = 0, /* 0: Successful */ - RES_ERROR, /* 1: R/W Error */ - RES_WRPRT, /* 2: Write Protected */ - RES_NOTRDY, /* 3: Not Ready */ - RES_PARERR /* 4: Invalid Parameter */ -} DRESULT; - - -/*---------------------------------------*/ -/* Prototypes for disk control functions */ - -#ifdef __cplusplus -extern "C" { -#endif -DSTATUS disk_initialize (BYTE); -DSTATUS disk_status (BYTE); -DRESULT disk_read (BYTE, BYTE*, DWORD, BYTE); -DRESULT disk_write (BYTE, const BYTE*, DWORD, BYTE); -DRESULT disk_ioctl (BYTE, BYTE, BYTE*); -#ifdef __cplusplus -} -#endif - -void disk_timerproc (void); - - -/* Disk Status Bits (DSTATUS) */ - -#define STA_NOINIT 0x01 /* Drive not initialized */ -#define STA_NODISK 0x02 /* No medium in the drive */ -#define STA_PROTECT 0x04 /* Write protected */ - - -/* Command code for disk_ioctrl fucntion */ - -/* Generic ioctl command (defined for FatFs) */ -#define CTRL_SYNC 0 /* Flush disk cache (for write functions) */ -#define GET_SECTOR_COUNT 1 /* Get media size (for only f_mkfs()) */ -#define GET_SECTOR_SIZE 2 /* Get sector size (for multiple sector size (_MAX_SS >= 1024)) */ -#define GET_BLOCK_SIZE 3 /* Get erase block size (for only f_mkfs()) */ -#define CTRL_ERASE_SECTOR 4 /* Force erased a block of sectors (for only _USE_ERASE) */ - -/* Generic ioctl command */ -#define CTRL_POWER 5 /* Get/Set power status */ -#define CTRL_LOCK 6 /* Lock/Unlock media removal */ -#define CTRL_EJECT 7 /* Eject media */ - -/* MMC/SDC specific ioctl command */ -#define MMC_GET_TYPE 10 /* Get card type */ -#define MMC_GET_CSD 11 /* Get CSD */ -#define MMC_GET_CID 12 /* Get CID */ -#define MMC_GET_OCR 13 /* Get OCR */ -#define MMC_GET_SDSTAT 14 /* Get SD status */ - -/* ATA/CF specific ioctl command */ -#define ATA_GET_REV 20 /* Get F/W revision */ -#define ATA_GET_MODEL 21 /* Get model name */ -#define ATA_GET_SN 22 /* Get serial number */ - -/* NAND specific ioctl command */ -#define NAND_FORMAT 30 /* Create physical format */ - - - -#ifdef PCBSKY -volatile extern BYTE Timer1, Timer2; /* 100Hz decrement timer */ -#endif - -//------------------------------------------------------------------------------ -/// Detect if SD card is connected -//------------------------------------------------------------------------------ -#define CardIsConnected() ( (PIOB->PIO_PDSR & PIO_PB7) == 0 ) - -extern uint32_t Card_ID[4] ; -extern uint32_t Card_SCR[2] ; -extern uint32_t Card_CSD[4] ; -extern uint32_t Sd_128_resp[4] ; -extern uint32_t Sd_rca ; -//extern uint32_t Cmd_55_resp ; - -extern uint32_t SD_SetBusWidth( uint32_t busWidth) ; -extern void SD_EnableHsMode( uint8_t hsEnable) ; -extern uint32_t SD_SetSpeed( uint32_t mciSpeed ) ; -extern void SD_Reset( uint8_t keepSettings) ; -extern uint32_t sd_cmd55( void ) ; -extern uint32_t sd_acmd41( void ) ; -extern uint32_t sd_cmd2( void ) ; -extern uint32_t sd_cmd3( void ) ; -extern uint32_t sd_cmd7( void ) ; -extern uint32_t sd_cmd9( void ) ; -extern uint32_t sd_cmd16( void ) ; -extern uint32_t sd_acmd6( void ) ; -extern uint32_t sd_acmd51( uint32_t *presult ) ; -extern uint32_t sd_cmd13( uint32_t *status) ; -extern void sd_poll_10mS( void ) ; -#ifdef PCBTARANIS -extern void sdPoll10ms( void ) ; -extern void sdInit( void ) ; -uint32_t sdMounted(void); -#endif -extern uint32_t sd_card_ready( void ) ; -extern uint32_t sd_read_block( uint32_t block_no, uint32_t *data ) ; - -extern DWORD socket_is_empty( void ) ; - -extern int8_t SD_ReadSectors(uint8_t *buff, uint32_t sector, uint32_t count) ; -extern int8_t SD_WriteSectors(uint8_t *buff, uint32_t sector, uint32_t count) ; - -#endif diff --git a/radio/bootloader/include/ff.h b/radio/bootloader/include/ff.h deleted file mode 100644 index 6e1f260e2..000000000 --- a/radio/bootloader/include/ff.h +++ /dev/null @@ -1,575 +0,0 @@ -/* - * Authors (alphabetical order) - * - Bertrand Songis - * - Bryan J. Rentoul (Gruvin) - * - Cameron Weeks - * - Erez Raviv - * - Jean-Pierre Parisy - * - Karl Szmutny - * - Michael Blandford - * - Michal Hlavinka - * - Pat Mackenzie - * - Philip Moss - * - Rob Thomson - * - Romolo Manfredini - * - Thomas Husterer - * - * open9x is based on code named - * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, - * er9x by Erez Raviv: http://code.google.com/p/er9x/, - * and the original (and ongoing) project by - * Thomas Husterer, th9x: http://code.google.com/p/th9x/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/*---------------------------------------------------------------------------/ -/ FatFs - FAT file system module include file R0.08a (C)ChaN, 2010 -/----------------------------------------------------------------------------/ -/ FatFs module is a generic FAT file system module for small embedded systems. -/ This is a free software that opened for education, research and commercial -/ developments under license policy of following trems. -/ -/ Copyright (C) 2010, ChaN, all right reserved. -/ -/ * The FatFs module is a free software and there is NO WARRANTY. -/ * No restriction on use. You can use, modify and redistribute it for -/ personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY. -/ * Redistributions of source code must retain the above copyright notice. -/ -/----------------------------------------------------------------------------*/ - -#ifndef _FATFS -#define _FATFS 8255 /* Revision ID */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "inttypes.h" -#include "integer.h" /* Basic integer types */ -#include "ffconf.h" /* FatFs configuration options */ - -#if _FATFS != _FFCONF -#error Wrong configuration file (ffconf.h). -#endif - - -/* DBCS code ranges and SBCS extend char conversion table */ - -#if _CODE_PAGE == 932 /* Japanese Shift-JIS */ -#define _DF1S 0x81 /* DBC 1st byte range 1 start */ -#define _DF1E 0x9F /* DBC 1st byte range 1 end */ -#define _DF2S 0xE0 /* DBC 1st byte range 2 start */ -#define _DF2E 0xFC /* DBC 1st byte range 2 end */ -#define _DS1S 0x40 /* DBC 2nd byte range 1 start */ -#define _DS1E 0x7E /* DBC 2nd byte range 1 end */ -#define _DS2S 0x80 /* DBC 2nd byte range 2 start */ -#define _DS2E 0xFC /* DBC 2nd byte range 2 end */ - -#elif _CODE_PAGE == 936 /* Simplified Chinese GBK */ -#define _DF1S 0x81 -#define _DF1E 0xFE -#define _DS1S 0x40 -#define _DS1E 0x7E -#define _DS2S 0x80 -#define _DS2E 0xFE - -#elif _CODE_PAGE == 949 /* Korean */ -#define _DF1S 0x81 -#define _DF1E 0xFE -#define _DS1S 0x41 -#define _DS1E 0x5A -#define _DS2S 0x61 -#define _DS2E 0x7A -#define _DS3S 0x81 -#define _DS3E 0xFE - -#elif _CODE_PAGE == 950 /* Traditional Chinese Big5 */ -#define _DF1S 0x81 -#define _DF1E 0xFE -#define _DS1S 0x40 -#define _DS1E 0x7E -#define _DS2S 0xA1 -#define _DS2E 0xFE - -#elif _CODE_PAGE == 437 /* U.S. (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F,0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 720 /* Arabic (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x45,0x41,0x84,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x49,0x49,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 737 /* Greek (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \ - 0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xE7,0xE8,0xF1,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 775 /* Baltic (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ - 0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 850 /* Multilingual Latin 1 (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ - 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 852 /* Latin 2 (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F,0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0x9F, \ - 0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF} - -#elif _CODE_PAGE == 855 /* Cyrillic (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F,0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \ - 0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \ - 0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 857 /* Turkish (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x98,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \ - 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0x59,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 858 /* Multilingual Latin 1 + Euro (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ - 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 862 /* Hebrew (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 866 /* Russian (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0x90,0x91,0x92,0x93,0x9d,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 874 /* Thai (OEM, Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 1250 /* Central Europe (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \ - 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xA3,0xB4,0xB5,0xB6,0xB7,0xB8,0xA5,0xAA,0xBB,0xBC,0xBD,0xBC,0xAF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF} - -#elif _CODE_PAGE == 1251 /* Cyrillic (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x82,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x80,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \ - 0xA0,0xA2,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB2,0xA5,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xA3,0xBD,0xBD,0xAF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF} - -#elif _CODE_PAGE == 1252 /* Latin 1 (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0xAd,0x9B,0x8C,0x9D,0xAE,0x9F, \ - 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F} - -#elif _CODE_PAGE == 1253 /* Greek (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xA2,0xB8,0xB9,0xBA, \ - 0xE0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xFB,0xBC,0xFD,0xBF,0xFF} - -#elif _CODE_PAGE == 1254 /* Turkish (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x9D,0x9E,0x9F, \ - 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F} - -#elif _CODE_PAGE == 1255 /* Hebrew (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 1256 /* Arabic (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x8C,0x9D,0x9E,0x9F, \ - 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0x41,0xE1,0x41,0xE3,0xE4,0xE5,0xE6,0x43,0x45,0x45,0x45,0x45,0xEC,0xED,0x49,0x49,0xF0,0xF1,0xF2,0xF3,0x4F,0xF5,0xF6,0xF7,0xF8,0x55,0xFA,0x55,0x55,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 1257 /* Baltic (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xBC,0xBD,0xBE,0xAF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF} - -#elif _CODE_PAGE == 1258 /* Vietnam (OEM, Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0xAC,0x9D,0x9E,0x9F, \ - 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xEC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xFE,0x9F} - -#elif _CODE_PAGE == 1 /* ASCII (for only non-LFN cfg) */ -#define _DF1S 0 - -#else -#error Unknown code page - -#endif - - - -/* Definitions of volume management */ - -#if _MULTI_PARTITION /* Multiple partition configuration */ -#define LD2PD(vol) (VolToPart[vol].pd) /* Get physical drive# */ -#define LD2PT(vol) (VolToPart[vol].pt) /* Get partition# */ -typedef struct { - BYTE pd; /* Physical drive# */ - BYTE pt; /* Partition # (0-3) */ -} PARTITION; -extern const PARTITION VolToPart[]; /* Volume - Physical location resolution table */ - -#else /* Single partition configuration */ -#define LD2PD(vol) (vol) /* Logical drive# is bound to the same physical drive# */ -#define LD2PT(vol) 0 /* Always mounts the 1st partition */ - -#endif - - - -/* Type of path name strings on FatFs API */ - -#if _LFN_UNICODE /* Unicode string */ -#if !_USE_LFN -#error _LFN_UNICODE must be 0 in non-LFN cfg. -#endif -#ifndef _INC_TCHAR -typedef WCHAR TCHAR; -#define _T(x) L ## x -#define _TEXT(x) L ## x -#endif - -#else /* ANSI/OEM string */ -#ifndef _INC_TCHAR -typedef char TCHAR; -#define _T(x) x -#define _TEXT(x) x -#endif - -#endif - - - -/* File system object structure (FATFS) */ - -typedef struct { - BYTE fs_type; /* FAT sub-type (0:Not mounted) */ - BYTE drv; /* Physical drive number */ - BYTE csize; /* Sectors per cluster (1,2,4...128) */ - BYTE n_fats; /* Number of FAT copies (1,2) */ - BYTE wflag; /* win[] dirty flag (1:must be written back) */ - BYTE fsi_flag; /* fsinfo dirty flag (1:must be written back) */ - WORD id; /* File system mount ID */ - WORD n_rootdir; /* Number of root directory entries (FAT12/16) */ -#if _MAX_SS != 512 - WORD ssize; /* Bytes per sector (512,1024,2048,4096) */ -#endif -#if _FS_REENTRANT - _SYNC_t sobj; /* Identifier of sync object */ -#endif -#if !_FS_READONLY - DWORD last_clust; /* Last allocated cluster */ - DWORD free_clust; /* Number of free clusters */ - DWORD fsi_sector; /* fsinfo sector (FAT32) */ -#endif -#if _FS_RPATH - DWORD cdir; /* Current directory start cluster (0:root) */ -#endif - DWORD n_fatent; /* Number of FAT entries (= number of clusters + 2) */ - DWORD fsize; /* Sectors per FAT */ - DWORD fatbase; /* FAT start sector */ - DWORD dirbase; /* Root directory start sector (FAT32:Cluster#) */ - DWORD database; /* Data start sector */ - DWORD winsect; /* Current sector appearing in the win[] */ - BYTE win[_MAX_SS]; /* Disk access window for Directory, FAT (and Data on tiny cfg) */ -} FATFS; - - - -/* File object structure (FIL) */ - -typedef struct { - FATFS* fs; /* Pointer to the owner file system object */ - WORD id; /* Owner file system mount ID */ - BYTE flag; /* File status flags */ - BYTE pad1; - DWORD fptr; /* File read/write pointer (0 on file open) */ - DWORD fsize; /* File size */ - DWORD org_clust; /* File start cluster (0 when fsize==0) */ - DWORD curr_clust; /* Current cluster */ - DWORD dsect; /* Current data sector */ -#if !_FS_READONLY - DWORD dir_sect; /* Sector containing the directory entry */ - BYTE* dir_ptr; /* Ponter to the directory entry in the window */ -#endif -#if _USE_FASTSEEK - DWORD* cltbl; /* Pointer to the cluster link map table (null on file open) */ -#endif -#if _FS_SHARE - UINT lockid; /* File lock ID (index of file semaphore table) */ -#endif -#if !_FS_TINY - BYTE buf[_MAX_SS]; /* File data read/write buffer */ -#endif -} FIL; - - - -/* Directory object structure (DIR) */ - -typedef struct { - FATFS* fs; /* Pointer to the owner file system object */ - WORD id; /* Owner file system mount ID */ - WORD index; /* Current read/write index number */ - DWORD sclust; /* Table start cluster (0:Root dir) */ - DWORD clust; /* Current cluster */ - DWORD sect; /* Current sector */ - BYTE* dir; /* Pointer to the current SFN entry in the win[] */ - BYTE* fn; /* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */ -#if _USE_LFN - WCHAR* lfn; /* Pointer to the LFN working buffer */ - WORD lfn_idx; /* Last matched LFN index number (0xFFFF:No LFN) */ -#endif -} DIR; - - - -/* File status structure (FILINFO) */ - -typedef struct { - DWORD fsize; /* File size */ - WORD fdate; /* Last modified date */ - WORD ftime; /* Last modified time */ - BYTE fattrib; /* Attribute */ - TCHAR fname[13]; /* Short file name (8.3 format) */ -#if _USE_LFN - TCHAR* lfname; /* Pointer to the LFN buffer */ - UINT lfsize; /* Size of LFN buffer in TCHAR */ -#endif -} FILINFO; - - - -/* File function return code (FRESULT) */ - -typedef enum { - FR_OK = 0, // (0) Succeeded - FR_DISK_ERR, // (1) A hard error occured in the low level disk I/O layer - FR_INT_ERR, // (2) Assertion failed - FR_NOT_READY, // (3) The physical drive cannot work - FR_NO_FILE, // (4) Could not find the file - FR_NO_PATH, // (5) Could not find the path - FR_INVALID_NAME, // (6) The path name format is invalid - FR_DENIED, // (7) Acces denied due to prohibited access or directory full - FR_EXIST, // (8) Acces denied due to prohibited access - FR_INVALID_OBJECT, // (9) The file/directory object is invalid - FR_WRITE_PROTECTED, // (10) The physical drive is write protected - FR_INVALID_DRIVE, // (11) The logical drive number is invalid - FR_NOT_ENABLED, // (12) The volume has no work area - FR_NO_FILESYSTEM, // (13) There is no valid FAT volume on the physical drive - FR_MKFS_ABORTED, // (14) The f_mkfs() aborted due to any parameter error - FR_TIMEOUT, // (15) Could not get a grant to access the volume within defined period - FR_LOCKED, // (16) The operation is rejected according to the file shareing policy - FR_NOT_ENOUGH_CORE, // (17) LFN working buffer could not be allocated - FR_TOO_MANY_OPEN_FILES // (18) Number of open files > _FS_SHARE -} FRESULT; - - - -/*--------------------------------------------------------------*/ -/* FatFs module application interface */ - -FRESULT f_mount (BYTE, FATFS*); /* Mount/Unmount a logical drive */ -FRESULT f_open (FIL*, const TCHAR*, BYTE); /* Open or create a file */ -FRESULT f_read (FIL*, BYTE*, UINT, UINT*); /* Read data from a file */ -FRESULT f_lseek (FIL*, DWORD); /* Move file pointer of a file object */ -FRESULT f_close (FIL*); /* Close an open file object */ -FRESULT f_opendir (DIR*, const TCHAR*); /* Open an existing directory */ -FRESULT f_readdir (DIR*, FILINFO*); /* Read a directory item */ -FRESULT f_stat (const TCHAR*, FILINFO*); /* Get file status */ - -#if !_FS_READONLY -FRESULT f_write (FIL*, const BYTE *, UINT, UINT*); /* Write data to a file */ -FRESULT f_getfree (const TCHAR*, DWORD*, FATFS**); /* Get number of free clusters on the drive */ -FRESULT f_truncate (FIL*); /* Truncate file */ -FRESULT f_sync (FIL*); /* Flush cached data of a writing file */ -FRESULT f_unlink (const TCHAR*); /* Delete an existing file or directory */ -FRESULT f_mkdir (const TCHAR*); /* Create a new directory */ -FRESULT f_chmod (const TCHAR*, BYTE, BYTE); /* Change attriburte of the file/dir */ -FRESULT f_utime (const TCHAR*, const FILINFO*); /* Change timestamp of the file/dir */ -FRESULT f_rename (const TCHAR *oldf, const TCHAR *newf); /* Rename/Move a file or directory */ -#endif - -#if _USE_FORWARD -FRESULT f_forward (FIL*, UINT(*)(const BYTE*,UINT), UINT, UINT*); /* Forward data to the stream */ -#endif - -#if _USE_MKFS -FRESULT f_mkfs (BYTE, BYTE, UINT); /* Create a file system on the drive */ -#endif - -#if _FS_RPATH -FRESULT f_chdrive (BYTE); /* Change current drive */ -FRESULT f_chdir (const TCHAR*); /* Change current directory */ -FRESULT f_getcwd (TCHAR*, UINT); /* Get current directory */ -#endif - -#if _USE_STRFUNC -int f_putc (TCHAR, FIL*); /* Put a character to the file */ -int f_puts (const TCHAR*, FIL*); /* Put a string to the file */ -int f_printf (FIL*, const TCHAR*, ...); /* Put a formatted string to the file */ -TCHAR* f_gets (TCHAR*, int, FIL*); /* Get a string from the file */ -#ifndef EOF -#define EOF (-1) -#endif -#endif - -#define f_eof(fp) (((fp)->fptr == (fp)->fsize) ? 1 : 0) -#define f_error(fp) (((fp)->flag & FA__ERROR) ? 1 : 0) -#define f_tell(fp) ((fp)->fptr) -#define f_size(fp) ((fp)->fsize) - - - -/*--------------------------------------------------------------*/ -/* Additional user defined functions */ - -/* RTC function */ -#if !_FS_READONLY -extern uint32_t o9x_get_fattime (void); /* Returns 32-bit packed date and time */ -#endif - -/* Unicode support functions */ -#if _USE_LFN /* Unicode - OEM code conversion */ -WCHAR ff_convert (WCHAR, UINT); /* OEM-Unicode bidirectional conversion */ -WCHAR ff_wtoupper (WCHAR); /* Unicode upper-case conversion */ -#if _USE_LFN == 3 /* Memory functions */ -void* ff_memalloc (UINT); /* Allocate memory block */ -void ff_memfree (void*); /* Free memory block */ -#endif -#endif - -/* Sync functions */ -#if _FS_REENTRANT -int ff_cre_syncobj (BYTE, _SYNC_t*);/* Create a sync object */ -int ff_del_syncobj (_SYNC_t); /* Delete a sync object */ -int ff_req_grant (_SYNC_t); /* Lock sync object */ -void ff_rel_grant (_SYNC_t); /* Unlock sync object */ -#endif - - - - -/*--------------------------------------------------------------*/ -/* Flags and offset address */ - - -/* File access control and file status flags (FIL.flag) */ - -#define FA_READ 0x01 -#define FA_OPEN_EXISTING 0x00 -#define FA__ERROR 0x80 - -#if !_FS_READONLY -#define FA_WRITE 0x02 -#define FA_CREATE_NEW 0x04 -#define FA_CREATE_ALWAYS 0x08 -#define FA_OPEN_ALWAYS 0x10 -#define FA__WRITTEN 0x20 -#define FA__DIRTY 0x40 -#endif - - -/* FAT sub type (FATFS.fs_type) */ - -#define FS_FAT12 1 -#define FS_FAT16 2 -#define FS_FAT32 3 - - -/* File attribute bits for directory entry */ - -#define AM_RDO 0x01 /* Read only */ -#define AM_HID 0x02 /* Hidden */ -#define AM_SYS 0x04 /* System */ -#define AM_VOL 0x08 /* Volume label */ -#define AM_LFN 0x0F /* LFN entry */ -#define AM_DIR 0x10 /* Directory */ -#define AM_ARC 0x20 /* Archive */ -#define AM_MASK 0x3F /* Mask of defined bits */ - - -/* Fast seek function */ -#define CREATE_LINKMAP 0xFFFFFFFF - - -/*--------------------------------*/ -/* Multi-byte word access macros */ - -#if _WORD_ACCESS == 1 /* Enable word access to the FAT structure */ -#define LD_WORD(ptr) (WORD)(*(WORD*)(BYTE*)(ptr)) -#define LD_DWORD(ptr) (DWORD)(*(DWORD*)(BYTE*)(ptr)) -#define ST_WORD(ptr,val) *(WORD*)(BYTE*)(ptr)=(WORD)(val) -#define ST_DWORD(ptr,val) *(DWORD*)(BYTE*)(ptr)=(DWORD)(val) -#else /* Use byte-by-byte access to the FAT structure */ -#define LD_WORD(ptr) (WORD)(((WORD)*(BYTE*)((ptr)+1)<<8)|(WORD)*(BYTE*)(ptr)) -#define LD_DWORD(ptr) (DWORD)(((DWORD)*(BYTE*)((ptr)+3)<<24)|((DWORD)*(BYTE*)((ptr)+2)<<16)|((WORD)*(BYTE*)((ptr)+1)<<8)|*(BYTE*)(ptr)) -#define ST_WORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *(BYTE*)((ptr)+1)=(BYTE)((WORD)(val)>>8) -#define ST_DWORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *(BYTE*)((ptr)+1)=(BYTE)((WORD)(val)>>8); *(BYTE*)((ptr)+2)=(BYTE)((DWORD)(val)>>16); *(BYTE*)((ptr)+3)=(BYTE)((DWORD)(val)>>24) -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* _FATFS */ diff --git a/radio/bootloader/include/ffconf.h b/radio/bootloader/include/ffconf.h deleted file mode 100644 index 8b21864ee..000000000 --- a/radio/bootloader/include/ffconf.h +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Authors (alphabetical order) - * - Bertrand Songis - * - Bryan J. Rentoul (Gruvin) - * - Cameron Weeks - * - Erez Raviv - * - Jean-Pierre Parisy - * - Karl Szmutny - * - Michael Blandford - * - Michal Hlavinka - * - Pat Mackenzie - * - Philip Moss - * - Rob Thomson - * - Romolo Manfredini - * - Thomas Husterer - * - * open9x is based on code named - * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, - * er9x by Erez Raviv: http://code.google.com/p/er9x/, - * and the original (and ongoing) project by - * Thomas Husterer, th9x: http://code.google.com/p/th9x/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/*---------------------------------------------------------------------------/ -/ FatFs - FAT file system module configuration file R0.08a (C)ChaN, 2010 -/----------------------------------------------------------------------------/ -/ -/ CAUTION! Do not forget to make clean the project after any changes to -/ the configuration options. -/ -/----------------------------------------------------------------------------*/ -#ifndef _FFCONF -#define _FFCONF 8255 /* Revision ID */ - - -/*---------------------------------------------------------------------------/ -/ Function and Buffer Configurations -/----------------------------------------------------------------------------*/ - -#define _FS_TINY 1 /* 0:Normal or 1:Tiny */ -/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system -/ object instead of the sector buffer in the individual file object for file -/ data transfer. This reduces memory consumption 512 bytes each file object. */ - -#ifdef BOOT -#define _FS_READONLY 1 /* 0:Read/Write or 1:Read only */ -#else -#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */ -#endif -/* Setting _FS_READONLY to 1 defines read only configuration. This removes -/ writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename, -/ f_truncate and useless f_getfree. */ - -#ifdef BOOT -#define _FS_MINIMIZE 1 /* 0 to 3 */ -#else -#define _FS_MINIMIZE 0 /* 0 to 3 */ -#endif -/* The _FS_MINIMIZE option defines minimization level to remove some functions. -/ -/ 0: Full function. -/ 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename -/ are removed. -/ 2: f_opendir and f_readdir are removed in addition to 1. -/ 3: f_lseek is removed in addition to 2. */ - - -#ifdef BOOT -#define _USE_STRFUNC 0 /* 0:Disable or 1/2:Enable */ -#else -#define _USE_STRFUNC 1 /* 0:Disable or 1/2:Enable */ -#endif -/* To enable string functions, set _USE_STRFUNC to 1 or 2. */ - - -#define _USE_MKFS 1 /* 0:Disable or 1:Enable */ -/* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */ - - -#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */ -/* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */ - - -#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */ -/* To enable fast seek feature, set _USE_FASTSEEK to 1. */ - - - -/*---------------------------------------------------------------------------/ -/ Locale and Namespace Configurations -/----------------------------------------------------------------------------*/ - -#define _CODE_PAGE 437 -/* The _CODE_PAGE specifies the OEM code page to be used on the target system. -/ Incorrect setting of the code page can cause a file open failure. -/ -/ 932 - Japanese Shift-JIS (DBCS, OEM, Windows) -/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows) -/ 949 - Korean (DBCS, OEM, Windows) -/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows) -/ 1250 - Central Europe (Windows) -/ 1251 - Cyrillic (Windows) -/ 1252 - Latin 1 (Windows) -/ 1253 - Greek (Windows) -/ 1254 - Turkish (Windows) -/ 1255 - Hebrew (Windows) -/ 1256 - Arabic (Windows) -/ 1257 - Baltic (Windows) -/ 1258 - Vietnam (OEM, Windows) -/ 437 - U.S. (OEM) -/ 720 - Arabic (OEM) -/ 737 - Greek (OEM) -/ 775 - Baltic (OEM) -/ 850 - Multilingual Latin 1 (OEM) -/ 858 - Multilingual Latin 1 + Euro (OEM) -/ 852 - Latin 2 (OEM) -/ 855 - Cyrillic (OEM) -/ 866 - Russian (OEM) -/ 857 - Turkish (OEM) -/ 862 - Hebrew (OEM) -/ 874 - Thai (OEM, Windows) -/ 1 - ASCII only (Valid for non LFN cfg.) -*/ - - -#define _USE_LFN 2 /* 0 to 3 */ -#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */ -/* The _USE_LFN option switches the LFN support. -/ -/ 0: Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect. -/ 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant. -/ 2: Enable LFN with dynamic working buffer on the STACK. -/ 3: Enable LFN with dynamic working buffer on the HEAP. -/ -/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. To enable LFN, -/ Unicode handling functions ff_convert() and ff_wtoupper() must be added -/ to the project. When enable to use heap, memory control functions -/ ff_memalloc() and ff_memfree() must be added to the project. */ - - -#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */ -/* To switch the character code set on FatFs API to Unicode, -/ enable LFN feature and set _LFN_UNICODE to 1. */ - - -#define _FS_RPATH 2 /* 0 to 2 */ -/* The _FS_RPATH option configures relative path feature. -/ -/ 0: Disable relative path feature and remove related functions. -/ 1: Enable relative path. f_chdrive() and f_chdir() are available. -/ 2: f_getcwd() is available in addition to 1. -/ -/ Note that output of the f_readdir fnction is affected by this option. */ - - - -/*---------------------------------------------------------------------------/ -/ Physical Drive Configurations -/----------------------------------------------------------------------------*/ - -#define _VOLUMES 1 -/* Number of volumes (logical drives) to be used. */ - - -#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */ -/* Maximum sector size to be handled. -/ Always set 512 for memory card and hard disk but a larger value may be -/ required for floppy disk (512/1024) and optical disk (512/2048). -/ When _MAX_SS is larger than 512, GET_SECTOR_SIZE command must be implememted -/ to the disk_ioctl function. */ - - -#define _MULTI_PARTITION 0 /* 0:Single partition or 1:Multiple partition */ -/* When set to 0, each volume is bound to the same physical drive number and -/ it can mount only first primaly partition. When it is set to 1, each volume -/ is tied to the partitions listed in VolToPart[]. */ - - -#define _USE_ERASE 0 /* 0:Disable or 1:Enable */ -/* To enable sector erase feature, set _USE_ERASE to 1. */ - - - -/*---------------------------------------------------------------------------/ -/ System Configurations -/----------------------------------------------------------------------------*/ - -#define _WORD_ACCESS 0 /* 0 or 1 */ -/* Set 0 first and it is always compatible with all platforms. The _WORD_ACCESS -/ option defines which access method is used to the word data on the FAT volume. -/ -/ 0: Byte-by-byte access. -/ 1: Word access. Do not choose this unless following condition is met. -/ -/ When the byte order on the memory is big-endian or address miss-aligned word -/ access results incorrect behavior, the _WORD_ACCESS must be set to 0. -/ If it is not the case, the value can also be set to 1 to improve the -/ performance and code size. */ - - -/* Include a header file here to define sync object types on the O/S */ -/* #include , , or ohters. */ - -#define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */ -#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */ -#define _SYNC_t HANDLE /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */ - -/* The _FS_REENTRANT option switches the reentrancy of the FatFs module. -/ -/ 0: Disable reentrancy. _SYNC_t and _FS_TIMEOUT have no effect. -/ 1: Enable reentrancy. Also user provided synchronization handlers, -/ ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj -/ function must be added to the project. */ - - -#define _FS_SHARE 0 /* 0:Disable or >=1:Enable */ -/* To enable file shareing feature, set _FS_SHARE to 1 or greater. The value - defines how many files can be opened simultaneously. */ - - -#endif /* _FFCONFIG */ diff --git a/radio/bootloader/usbd_storage_msd.cpp b/radio/bootloader/usbd_storage_msd.cpp index 2552e02be..bd97ecc7c 100644 --- a/radio/bootloader/usbd_storage_msd.cpp +++ b/radio/bootloader/usbd_storage_msd.cpp @@ -33,7 +33,9 @@ //#include #include "drivers.h" #include "../src/targets/taranis/i2c.h" -#include "diskio.h" +extern "C" { +#include "../src/FatFs/diskio.h" +} //#include "board_taranis.h" #include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_gpio.h" @@ -166,7 +168,7 @@ int8_t STORAGE_GetCapacity (uint8_t lun, uint32_t *block_num, uint32_t *block_si static DWORD sector_count = 0; if (sector_count == 0) { - if (disk_ioctl(0, GET_SECTOR_COUNT, (BYTE*)§or_count) != RES_OK) { + if (disk_ioctl(0, GET_SECTOR_COUNT, §or_count) != RES_OK) { sector_count = 0; return -1; } diff --git a/radio/src/FatFs/ffconf.h b/radio/src/FatFs/ffconf.h index fcdf65533..48e579763 100644 --- a/radio/src/FatFs/ffconf.h +++ b/radio/src/FatFs/ffconf.h @@ -28,14 +28,20 @@ extern "C" { / object instead of the sector buffer in the individual file object for file / data transfer. This reduces memory consumption 512 bytes each file object. */ - +#if defined(BOOT) +#define _FS_READONLY 1 /* 0:Read/Write or 1:Read only */ +#else #define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */ +#endif /* Setting _FS_READONLY to 1 defines read only configuration. This removes / writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename, / f_truncate and useless f_getfree. */ - +#if defined(BOOT) +#define _FS_MINIMIZE 1 /* 0 to 3 */ +#else #define _FS_MINIMIZE 0 /* 0 to 3 */ +#endif /* The _FS_MINIMIZE option defines minimization level to remove some functions. / / 0: Full function. @@ -45,7 +51,11 @@ extern "C" { / 3: f_lseek is removed in addition to 2. */ +#if defined(BOOT) +#define _USE_STRFUNC 0 /* 0:Disable or 1-2:Enable */ +#else #define _USE_STRFUNC 1 /* 0:Disable or 1-2:Enable */ +#endif /* To enable string functions, set _USE_STRFUNC to 1 or 2. */ @@ -186,7 +196,7 @@ extern "C" { /* A header file that defines sync object types on the O/S, such as / windows.h, ucos_ii.h and semphr.h, must be included prior to ff.h. */ -#if defined(CPUARM) +#if defined(CPUARM) && !defined(BOOT) #define _FS_REENTRANT 1 /* 0:Disable or 1:Enable */ #define _SYNC_t unsigned char /*OS_MutexID*/ /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */ #else diff --git a/radio/src/targets/taranis/diskio.cpp b/radio/src/targets/taranis/diskio.cpp index 9d7a24b11..8f80c8841 100644 --- a/radio/src/targets/taranis/diskio.cpp +++ b/radio/src/targets/taranis/diskio.cpp @@ -180,12 +180,10 @@ static void card_power(BYTE on) on=on; } -#if (STM32_SD_DISK_IOCTRL == 1) static int chk_power(void) { return 1; /* fake powered */ } -#endif /*-----------------------------------------------------------------------*/ /* Transmit/Receive a byte to MMC via SPI (Platform dependent) */ @@ -503,7 +501,6 @@ BOOL rcvr_datablock ( /* Send a data packet to MMC */ /*-----------------------------------------------------------------------*/ -#if _FS_READONLY == 0 static BOOL xmit_datablock ( const BYTE *buff, /* 512 byte data block to be transmitted */ @@ -539,8 +536,6 @@ BOOL xmit_datablock ( return TRUE; } -#endif /* _READONLY */ - /*-----------------------------------------------------------------------*/ @@ -731,8 +726,6 @@ DRESULT disk_read ( /* Write Sector(s) */ /*-----------------------------------------------------------------------*/ -#if _FS_READONLY == 0 - // TODO quick & dirty int8_t SD_WriteSectors(uint8_t *buff, uint32_t sector, uint32_t count) { @@ -752,6 +745,8 @@ int8_t SD_WriteSectors(uint8_t *buff, uint32_t sector, uint32_t count) return 0; } +#if _FS_READONLY == 0 + DRESULT disk_write ( BYTE drv, /* Physical drive number (0) */ const BYTE *buff, /* Pointer to the data to be written */ @@ -793,7 +788,6 @@ DRESULT disk_write ( /* Miscellaneous Functions */ /*-----------------------------------------------------------------------*/ -#if (STM32_SD_DISK_IOCTRL == 1) DRESULT disk_ioctl ( BYTE drv, /* Physical drive number (0) */ BYTE ctrl, /* Control code */ @@ -919,7 +913,6 @@ DRESULT disk_ioctl ( return res; } -#endif /* _USE_IOCTL != 0 */ /*-----------------------------------------------------------------------*/ From 1d181ae30084df0b171155ffec4ab85ddf43eac2 Mon Sep 17 00:00:00 2001 From: bsongis Date: Wed, 5 Mar 2014 11:46:50 +0100 Subject: [PATCH 035/285] one more file removed --- radio/bootloader/lcdboot.cpp | 618 ----------------------------------- 1 file changed, 618 deletions(-) delete mode 100644 radio/bootloader/lcdboot.cpp diff --git a/radio/bootloader/lcdboot.cpp b/radio/bootloader/lcdboot.cpp deleted file mode 100644 index 06d23bffe..000000000 --- a/radio/bootloader/lcdboot.cpp +++ /dev/null @@ -1,618 +0,0 @@ -/* - * Author - Mike Blandford - * - * Based on er9x by Erez Raviv - * - * Based on th9x -> http://code.google.com/p/th9x/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -// This version for ARM based ERSKY9X board - -#include -#include -#include - -#ifdef PCBSKY -#include "AT91SAM3S4.h" -#include "radio.h" -//#include "myeeprom.h" -#endif - -#ifdef PCBTARANIS - #include "radio.h" -#endif - -#include "lcd.h" -#include "drivers.h" -#include "logicio.h" - -#include "font.lbm" -#define font_5x8_x20_x7f (font) - -#include "font_dblsize.lbm" -#define font_10x16_x20_x7f (font_dblsize) - -// Local data -uint8_t OptrexDisplay = 0 ; -uint8_t Lcd_lastPos ; -uint8_t DisplayBuf[DISPLAY_W*DISPLAY_H/8] ; -#define DISPLAY_END (DisplayBuf+sizeof(DisplayBuf)) - -#ifdef PCBTARANIS -#define X9D_OFFSET 0 -#define DISPLAY_START (DisplayBuf + X9D_OFFSET) -#else -#define DISPLAY_START (DisplayBuf + 0) -#endif - - - -/// invers: 0 no 1=yes 2=blink -void lcd_putc(uint8_t x,uint8_t y,const char c ) -{ - lcd_putcAtt(x,y,c,0); -} - -uint8_t lcd_putcAtt(uint8_t x,uint8_t y,const char c,uint8_t mode) -{ - register int32_t i ; - register uint8_t *p = &DISPLAY_START[ y / 8 * DISPLAY_W + x ]; - //uint8_t *pmax = &displayBuf[ DISPLAY_H/8 * DISPLAY_W ]; - if ( c < 22 ) // Move to specific x position (c)*FW - { - x = c*FW ; - if(mode&DBLSIZE) - { - x += x ; - } - return x ; - } - x += FW ; - register uint8_t *q ; - if( c < 0xC0 ) - { - q = (uint8_t *) &font_5x8_x20_x7f[(c-0x20)*5] ; - } - else - { - q = (uint8_t *) &font_5x8_x20_x7f[0] ; - } - register bool inv = (mode & INVERS) ? true : false ; - - if(mode&DBLSIZE) - { - if ( (c!=0x2E)) x+=FW; //check for decimal point - /* each letter consists of ten top bytes followed by - * five bottom by ten bottom bytes (20 bytes per - * char) */ - unsigned char c_mapped ; - if( c < 0xC0 ) - { - if ( c == 'B' ) - { - c_mapped = 1 ; - } - else if ( c == 'S' ) - { - c_mapped = 2 ; - } - else if ( c == 'U' ) - { - c_mapped = 3 ; - } - else - { - c_mapped = 0 ; - } - q = (uint8_t *) &font_10x16_x20_x7f[(c_mapped)*20] ; -// q = (uint8_t *) &font_10x16_x20_x7f[(c-0x20)*10 + ((c-0x20)/16)*160]; - } - else - { - q = (uint8_t *) &font_10x16_x20_x7f[0] ; - } - for( i=5 ; i>=0 ; i-- ) - { - uint8_t b1 ; - uint8_t b3 ; - uint8_t b2 ; - uint8_t b4 ; - - if( c < 0xC0 ) - { - /*top byte*/ - b1 = i>0 ? *q : 0; - /*bottom byte*/ - b3 = i>0 ? *(q+10) : 0; - /*top byte*/ - b2 = i>0 ? *(++q) : 0; - /*bottom byte*/ - b4 = i>0 ? *(q+10) : 0; - q++; - } - else - { - /*top byte*/ - b1 = i>0 ? *q++ : 0 ; - /*bottom byte*/ - b3 = i>0 ? *q++ : 0 ; - /*top byte*/ - b2 = i>0 ? *q++ : 0 ; - /*bottom byte*/ - b4 = i>0 ? *q++ : 0 ; - } - if(inv) - { - b1=~b1; - b2=~b2; - b3=~b3; - b4=~b4; - } - - if(&p[DISPLAY_W+1] < DISPLAY_END) - { - p[0]=b1; - p[1]=b2; - p[DISPLAY_W] = b3; - p[DISPLAY_W+1] = b4; - p+=2; - } - } - } - else - { - uint8_t condense=0; - - if (mode & CONDENSED) - { - *p++ = inv ? ~0 : 0; - condense=1; - x += FWNUM-FW ; - } - - for( i=5 ; i!=0 ; i-- ) - { - uint8_t b = *q++ ; - if (condense && i==4) - { - /*condense the letter by skipping column 4 */ - continue; - } - if(p9 ? c+'A'-10 : c+'0'; - lcd_putcAtt(x,y,c,c>='A'?CONDENSED:0); - val>>=4; - } -} -uint8_t plotType = PLOT_XOR ; - -void lcd_write_bits( uint8_t *p, uint8_t mask ) -{ - if(p=DISPLAY_END) - { - break ; - } - if(pat&1) - { - lcd_write_bits( p, msk ) ; - pat = (pat >> 1) | 0x80; - } - else - { - pat = pat >> 1; - } - w--; - p++; - } -} - - -// Reverse video 8 pixels high, w pixels wide -// Vertically on an 8 pixel high boundary -void lcd_char_inverse( uint8_t x, uint8_t y, uint8_t w, uint8_t blink ) -{ -// if ( blink && BLINK_ON_PHASE ) -// { -// return ; -// } - uint8_t end = x + w ; - uint8_t *p = &DISPLAY_START[ y / 8 * DISPLAY_W + x ]; - - while ( x < end ) - { - *p++ ^= 0xFF ; - x += 1 ; - } -} - -void lcd_hline( uint8_t x, uint8_t y, int8_t w ) -{ - lcd_hlineStip(x,y,w,0xff); -} - -void lcd_vline( uint8_t x, uint8_t y, int8_t h ) -{ - if (h<0) { y+=h; h=-h; } - register uint8_t *p = &DISPLAY_START[ y / 8 * DISPLAY_W + x ]; - - y &= 0x07 ; - if ( y ) - { - uint8_t msk = ~(BITMASK(y)-1) ; - h -= 8-y ; - if (h < 0) - msk -= ~(BITMASK(8+h)-1) ; - lcd_write_bits( p, msk ) ; - p += DISPLAY_W ; - } - - while( h >= 8 ) - { - h -= 8 ; - lcd_write_bits( p, 0xFF ) ; - p += DISPLAY_W ; - } - if ( h > 0 ) - { - lcd_write_bits( p, (BITMASK(h)-1) ) ; - } -} - -#ifdef SIMU -bool lcd_refresh = true; -uint8_t lcd_buf[DISPLAY_W*DISPLAY_H/8]; -#endif - - -void lcd_clear() -{ - //for(unsigned i=0; iPIO_PDSR << 1 ; // 6 LEFT, 5 RIGHT, 4 DOWN, 3 UP () - LcdLock = 1 ; -// pioptr = PIOA ; -// pioptr->PIO_PER = LCD_A0 ; // Enable bit 7 (LCD-A0) -// pioptr->PIO_CODR = LCD_A0 ; -// pioptr->PIO_OER = LCD_A0 ; // Set bit 7 output - pioptr = PIOC ; - -#ifdef REVX - pioptr->PIO_PER = PIO_PC27 | PIO_PC12 | 0xFF ; // Enable bits 27,26,13,12,7-0 -#else - pioptr->PIO_PER = PIO_PC27 | PIO_PC26 | PIO_PC13 | PIO_PC12 | 0xFF ; // Enable bits 27,26,13,12,7-0 -#endif // REVX - -//#ifndef REVX -// pioptr->PIO_CODR = LCD_E | LCD_RnW ; -// pioptr->PIO_SODR = LCD_RES | LCD_CS1 ; -//#else -#ifdef REVX - pioptr->PIO_CODR = LCD_E ; - pioptr->PIO_CODR = LCD_RnW | LCD_CS1 ; // No longer needed, used elsewhere -#else - pioptr->PIO_CODR = LCD_E | LCD_RnW | LCD_CS1 ; -#endif // REVX - pioptr->PIO_SODR = LCD_RES ; -//#endif - pioptr->PIO_OER = PIO_PC27 | PIO_PC26 | PIO_PC13 | PIO_PC12 | 0xFF ; // Set bits 27,26,13,12,7-0 output - pioptr->PIO_OWER = 0x000000FFL ; // Allow write to ls 8 bits in ODSR - - pioptr->PIO_CODR = LCD_RES ; // Reset LCD - TC0->TC_CHANNEL[0].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) - while ( TC0->TC_CHANNEL[0].TC_CV < 200 ) // >10 uS, Value depends on MCK/2 (used 18MHz) - { - // Wait - } - pioptr->PIO_SODR = LCD_RES ; // Remove LCD reset - TC0->TC_CHANNEL[0].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) - while ( TC0->TC_CHANNEL[0].TC_CV < 27000 ) // 1500 uS, Value depends on MCK/2 (used 18MHz) - { - // Wait - } - for ( i = 0 ; i < 12 ; i += 1 ) - { - lcdSendCtl( Lcdinit[i] ) ; - } - - pioptr->PIO_ODR = 0x0000003AL ; // Set bits 1, 3, 4, 5 input - pioptr->PIO_PUER = 0x0000003AL ; // Set bits 1, 3, 4, 5 with pullups - pioptr->PIO_ODSR = 0 ; // Drive D0 low - LcdLock = 0 ; - -#ifdef REVX - lcdSetRefVolt( 23 ) ; -#else - lcdSetRefVolt( 30 ) ; -#endif - -} - - -void lcdSetRefVolt(uint8_t val) -{ -#ifndef SIMU - register Pio *pioptr ; - pioptr = PIOC ; - -// read the inputs, and lock the LCD lines - LcdInputs = PIOC->PIO_PDSR << 1 ; // 6 LEFT, 5 RIGHT, 4 DOWN, 3 UP () - LcdLock = 1 ; - - pioptr->PIO_OER = 0x0C00B0FFL ; // Set bits 27,26,15,13,12,7-0 output - - lcdSendCtl(0x81); - if ( val == 0 ) - { - val = 0x22 ; - } - lcdSendCtl(val); - - pioptr->PIO_ODR = 0x0000003AL ; // Set bits 1, 3, 4, 5 input - pioptr->PIO_PUER = 0x0000003AL ; // Set bits 1, 3, 4, 5 with pullups - pioptr->PIO_ODSR = 0 ; // Drive D0 low -#endif // SIMU - LcdLock = 0 ; -} - - - -void lcdSendCtl(uint8_t val) -{ - register Pio *pioptr ; - - pioptr = PIOC ; -#ifndef REVX - pioptr->PIO_CODR = LCD_CS1 ; // Select LCD -#endif - PIOA->PIO_CODR = LCD_A0 ; -#ifndef REVX - pioptr->PIO_CODR = LCD_RnW ; // Write -#endif - pioptr->PIO_ODSR = val ; - - pioptr->PIO_SODR = LCD_E ; // Start E pulse - // Need a delay here (250nS) - TC0->TC_CHANNEL[0].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) - while ( TC0->TC_CHANNEL[0].TC_CV < 9 ) // Value depends on MCK/2 (used 18MHz) - { - // Wait - } - pioptr->PIO_CODR = LCD_E ; // End E pulse - PIOA->PIO_SODR = LCD_A0 ; // Data -} - -#ifdef SIMU -void refreshDisplay() -{ - memcpy(lcd_buf, DisplayBuf, sizeof(DisplayBuf)); - lcd_refresh = true; -} -#else -void refreshDisplay() -{ - register Pio *pioptr ; - register uint8_t *p=DisplayBuf; - register uint32_t y ; - register uint32_t x ; - register uint32_t z ; - register uint32_t ebit ; - - ebit = LCD_E ; - - pioptr = PIOA ; - pioptr->PIO_PER = 0x00000080 ; // Enable bit 7 (LCD-A0) - pioptr->PIO_OER = 0x00000080 ; // Set bit 7 output - -// read the inputs, and lock the LCD lines - LcdInputs = PIOC->PIO_PDSR << 1 ; // 6 LEFT, 5 RIGHT, 4 DOWN, 3 UP () - LcdLock = 1 ; - - pioptr = PIOC ; - pioptr->PIO_OER = 0x0C0030FFL ; // Set bits 27,26,15,13,12,7-0 output - for( y=0; y < 8; y++) { - lcdSendCtl( OptrexDisplay ? 0 : 0x04 ) ; - lcdSendCtl(0x10); //column addr 0 - lcdSendCtl( y | 0xB0); //page addr y - -#ifndef REVX - pioptr->PIO_CODR = LCD_CS1 ; // Select LCD -#endif // REVX - - PIOA->PIO_SODR = LCD_A0 ; // Data -#ifndef REVX - pioptr->PIO_CODR = LCD_RnW ; // Write -#endif // REVX - - x = *p ; - for( z=0; z<128; z+=1) - { - pioptr->PIO_ODSR = x ; - pioptr->PIO_SODR = ebit ; // Start E pulse - // Need a delay here (250nS) - p += 1 ; - x = *p ; - pioptr->PIO_CODR = ebit ; // End E pulse - } - } - pioptr->PIO_ODSR = 0xFF ; // Drive lines high - pioptr->PIO_PUER = 0x0000003AL ; // Set bits 1, 3, 4, 5 with pullups - pioptr->PIO_ODR = 0x0000003AL ; // Set bits 1, 3, 4, 5 input - pioptr->PIO_ODSR = 0xFE ; // Drive D0 low - - LcdLock = 0 ; - -} - -#endif // PCBSKY -#endif // PCBSKY - -#ifdef PCBSKY -// This specially for the 9XR -extern void start_timer0( void ) ; -extern void stop_timer0( void ) ; - -extern "C" void dispUSB( void ) ; -void dispUSB() -{ - // Put USB on display here? - start_timer0() ; - lcd_init() ; - OptrexDisplay = 1 ; - lcd_clear() ; - refreshDisplay() ; - OptrexDisplay = 0 ; - lcd_clear() ; - lcd_putcAtt( 48, 24, 'U', DBLSIZE ) ; - lcd_putcAtt( 60, 24, 'S', DBLSIZE ) ; - lcd_putcAtt( 72, 24, 'B', DBLSIZE ) ; - refreshDisplay() ; - stop_timer0() ; -} - -#endif - From 072f305cfea976731a5e476f8d62840ddbfe11b7 Mon Sep 17 00:00:00 2001 From: bsongis Date: Wed, 5 Mar 2014 11:47:30 +0100 Subject: [PATCH 036/285] 3 more files removed --- radio/bootloader/include/gtime.h | 63 --------------- radio/bootloader/include/integer.h | 70 ----------------- radio/bootloader/include/lcd.h | 122 ----------------------------- 3 files changed, 255 deletions(-) delete mode 100644 radio/bootloader/include/gtime.h delete mode 100644 radio/bootloader/include/integer.h delete mode 100644 radio/bootloader/include/lcd.h diff --git a/radio/bootloader/include/gtime.h b/radio/bootloader/include/gtime.h deleted file mode 100644 index 8126d8375..000000000 --- a/radio/bootloader/include/gtime.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Authors (alphabetical order) - * - Bertrand Songis - * - Bryan J. Rentoul (Gruvin) - * - Cameron Weeks - * - Erez Raviv - * - Jean-Pierre Parisy - * - Karl Szmutny - * - Michael Blandford - * - Michal Hlavinka - * - Pat Mackenzie - * - Philip Moss - * - Rob Thomson - * - Romolo Manfredini - * - Thomas Husterer - * - * open9x is based on code named - * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, - * er9x by Erez Raviv: http://code.google.com/p/er9x/, - * and the original (and ongoing) project by - * Thomas Husterer, th9x: http://code.google.com/p/th9x/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef g9x_time_h -#define g9x_time_h - -#include -#include - -#undef CHAR_BIT -#define CHAR_BIT 8 - -typedef long int gtime_t; - -struct gtm -{ - int8_t tm_sec; /* Seconds. [0-60] (1 leap second) */ - int8_t tm_min; /* Minutes. [0-59] */ - int8_t tm_hour; /* Hours. [0-23] */ - int8_t tm_mday; /* Day. [1-31] */ - int8_t tm_mon; /* Month. [0-11] */ - int8_t tm_year; /* Year - 1900. Limited to the year 2115. Oh no! :P */ - int8_t tm_wday; /* Day of week. [0-6] */ - int16_t tm_yday; /* Day of year. [0-365] Needed internally for calculations */ -}; - -extern const unsigned short int __mon_yday[2][13]; - -extern gtime_t gmktime(struct gtm *tp); -extern gtime_t filltm(gtime_t *t, struct gtm *tp); - -#endif - diff --git a/radio/bootloader/include/integer.h b/radio/bootloader/include/integer.h deleted file mode 100644 index 608873bdf..000000000 --- a/radio/bootloader/include/integer.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Authors (alphabetical order) - * - Bertrand Songis - * - Bryan J. Rentoul (Gruvin) - * - Cameron Weeks - * - Erez Raviv - * - Jean-Pierre Parisy - * - Karl Szmutny - * - Michael Blandford - * - Michal Hlavinka - * - Pat Mackenzie - * - Philip Moss - * - Rob Thomson - * - Romolo Manfredini - * - Thomas Husterer - * - * open9x is based on code named - * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, - * er9x by Erez Raviv: http://code.google.com/p/er9x/, - * and the original (and ongoing) project by - * Thomas Husterer, th9x: http://code.google.com/p/th9x/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/*-------------------------------------------*/ -/* Integer type definitions for FatFs module */ -/*-------------------------------------------*/ - -#ifndef _INTEGER -#define _INTEGER - -#ifdef _WIN32 /* FatFs development platform */ - -#include -#include - -#else /* Embedded platform */ - -/* These types must be 16-bit, 32-bit or larger integer */ -typedef int INT; -typedef unsigned int UINT; - -/* These types must be 8-bit integer */ -typedef char CHAR; -typedef unsigned char UCHAR; -typedef unsigned char BYTE; - -/* These types must be 16-bit integer */ -typedef short SHORT; -typedef unsigned short USHORT; -typedef unsigned short WORD; -typedef unsigned short WCHAR; - -/* These types must be 32-bit integer */ -typedef long LONG; -typedef unsigned long ULONG; -typedef unsigned long DWORD; - -#endif - -#endif diff --git a/radio/bootloader/include/lcd.h b/radio/bootloader/include/lcd.h deleted file mode 100644 index a9e39d09e..000000000 --- a/radio/bootloader/include/lcd.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Author - Mike Blandford - * - * Based on er9x by Erez Raviv - * - * which was Based on th9x -> http://code.google.com/p/th9x/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -// This version for ARM based ERSKY9X board - -#ifndef lcd_h -#define lcd_h - -#ifdef PCBTARANIS -#define DISPLAY_W 212 -#define DISPLAY_H 64 -#endif - -#ifdef PCBSKY -#define DISPLAY_W 128 -#define DISPLAY_H 64 -#endif - -#define FW 6 -#define FWNUM 5 -#define FH 8 - -/* lcd common flags */ -#define INVERS 0x01 -#define BLINK 0x02 -#define DBLSIZE 0x04 -#define CONDENSED 0x08 - -// putsChnRaw flags -#define MIX_SOURCE 0x10 - -/* lcd outdez flags */ -#define LEADING0 0x10 -#define PREC1 0x20 -#define PREC2 0x30 /* 4 modes in 2bits! */ -#define LEFT 0x40 /* align left */ - -/* time & telemetry flags */ -#define NO_UNIT 0x80 - - - -extern uint8_t LcdLock ; -extern uint8_t LcdInputs ; - -extern uint8_t Lcd_lastPos; -extern uint8_t DisplayBuf[] ; - -extern const uint8_t font_se_extra[] ; -extern const uint8_t font_fr_extra[] ; -extern const uint8_t font_de_extra[] ; - -extern const uint8_t font_se_big_extra[] ; -extern const uint8_t font_fr_big_extra[] ; -extern const uint8_t font_de_big_extra[] ; - -extern const uint8_t *ExtraFont ; -extern const uint8_t *ExtraBigFont ; - -#define PLOT_XOR 0 -#define PLOT_BLACK 1 -#define PLOT_WHITE 2 - -extern uint8_t plotType ; - -extern void lcd_putc(uint8_t x,uint8_t y,const char c ) ; -extern uint8_t lcd_putcAtt( uint8_t x, uint8_t y, const char c, uint8_t mode ) ; -extern void lcd_putsAttIdx(uint8_t x,uint8_t y,const char * s,uint8_t idx,uint8_t att) ; -extern void lcd_putsnAtt(uint8_t x,uint8_t y,const char * s,uint8_t len,uint8_t mode) ; -extern void lcd_putsn_P(uint8_t x,uint8_t y,const char * s,uint8_t len) ; -extern void lcd_outhex4(uint8_t x,uint8_t y,uint16_t val) ; -extern void lcd_outhex2(uint8_t x,uint8_t y,uint8_t val) ; -extern void lcd_img( uint8_t i_x, uint8_t i_y, const unsigned char *imgdat, uint8_t idx, uint8_t mode ) ; -extern uint8_t lcd_putsAtt( uint8_t x, uint8_t y, const char *s, uint8_t mode ) ; -extern void lcd_puts_Pleft( uint8_t y, const char *s ) ; -extern void lcd_puts_P( uint8_t x, uint8_t y, const char *s ) ; -extern void lcd_outdez( uint8_t x, uint8_t y, int16_t val ) ; -extern void lcd_outdezAtt( uint8_t x, uint8_t y, int16_t val, uint8_t mode ) ; -extern void lcd_outdezNAtt( uint8_t x, uint8_t y, int32_t val, uint8_t mode, int8_t len ) ; - -extern void lcd_hbar( uint8_t x, uint8_t y, uint8_t w, uint8_t h, uint8_t percent ) ; -extern void lcd_rect(uint8_t x, uint8_t y, uint8_t w, uint8_t h ) ; -extern void lcd_char_inverse( uint8_t x, uint8_t y, uint8_t w, uint8_t blink ) ; -extern void lcd_plot( uint8_t x, uint8_t y ) ; -extern void lcd_hlineStip( unsigned char x, unsigned char y, signed char w, uint8_t pat ) ; -extern void lcd_hline( uint8_t x, uint8_t y, int8_t w ) ; -extern void lcd_vline( uint8_t x, uint8_t y, int8_t h ) ; -extern void lcd_clear( void ) ; -extern void lcd_init( void ) ; -extern void lcdSetRefVolt(uint8_t val) ; -extern void lcdSendCtl(uint8_t val) ; -extern void refreshDisplay( void ) ; - -extern void putsTime(uint8_t x,uint8_t y,int16_t tme,uint8_t att,uint8_t att2) ; -extern void putsVolts(uint8_t x,uint8_t y, uint8_t volts, uint8_t att) ; -extern void putsVBat(uint8_t x,uint8_t y,uint8_t att) ; - -#ifdef PCBTARANIS -extern void backlight_set( uint16_t brightness ) ; -#endif - -#define BLINK_ON_PHASE (g_blinkTmr10ms & (1<<6)) -#define BLINK_SYNC g_blinkTmr10ms = (3<<5) - -#endif - - From 404c58d447d290de3896ea568c27b4b4810955c0 Mon Sep 17 00:00:00 2001 From: bsongis Date: Wed, 5 Mar 2014 11:48:28 +0100 Subject: [PATCH 037/285] 3 more files removed --- radio/bootloader/font.lbm | 8 - radio/bootloader/font_dblsize.lbm | 16 - radio/bootloader/x9ddiskio.cpp | 1008 ----------------------------- 3 files changed, 1032 deletions(-) delete mode 100644 radio/bootloader/font.lbm delete mode 100644 radio/bootloader/font_dblsize.lbm delete mode 100644 radio/bootloader/x9ddiskio.cpp diff --git a/radio/bootloader/font.lbm b/radio/bootloader/font.lbm deleted file mode 100644 index e95bed6c6..000000000 --- a/radio/bootloader/font.lbm +++ /dev/null @@ -1,8 +0,0 @@ -const uint8_t font[] = { -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x6f,0x00,0x00,0x07,0x00,0x07,0x00,0x14,0x7f,0x14,0x7f,0x14,0x24,0x2a,0x7f,0x2a,0x12,0x23,0x13,0x08,0x64,0x62,0x36,0x49,0x55,0x22,0x50,0x00,0x05,0x03,0x00,0x00,0x00,0x1c,0x22,0x41,0x00,0x00,0x41,0x22,0x1c,0x00,0x14,0x08,0x3e,0x08,0x14,0x08,0x08,0x3e,0x08,0x08,0x00,0x50,0x30,0x00,0x00,0x08,0x08,0x08,0x08,0x08,0x00,0x60,0x60,0x00,0x00,0x20,0x10,0x08,0x04,0x02, -0x00,0x3e,0x49,0x45,0x3e,0x00,0x00,0x42,0x7f,0x40,0x00,0x62,0x51,0x49,0x46,0x00,0x41,0x49,0x49,0x36,0x00,0x18,0x14,0x12,0x7f,0x00,0x27,0x45,0x45,0x39,0x00,0x3e,0x49,0x49,0x32,0x00,0x01,0x79,0x05,0x03,0x00,0x36,0x49,0x49,0x36,0x00,0x06,0x49,0x29,0x1e,0x00,0x00,0x36,0x36,0x00,0x00,0x00,0x56,0x36,0x00,0x00,0x08,0x14,0x22,0x41,0x14,0x14,0x14,0x14,0x14,0x41,0x22,0x14,0x08,0x00,0x02,0x01,0x51,0x09,0x06, -0x00,0x06,0x09,0x09,0x06,0x7e,0x09,0x09,0x09,0x7e,0x7f,0x49,0x49,0x49,0x36,0x3e,0x41,0x41,0x41,0x22,0x7f,0x41,0x41,0x22,0x1c,0x7f,0x49,0x49,0x49,0x41,0x7f,0x09,0x09,0x09,0x01,0x3e,0x41,0x49,0x49,0x7a,0x7f,0x08,0x08,0x08,0x7f,0x00,0x41,0x7f,0x41,0x00,0x20,0x40,0x41,0x3f,0x01,0x7f,0x08,0x14,0x22,0x41,0x7f,0x40,0x40,0x40,0x40,0x7f,0x02,0x0c,0x02,0x7f,0x7f,0x04,0x08,0x10,0x7f,0x3e,0x41,0x41,0x41,0x3e, -0x7f,0x09,0x09,0x09,0x06,0x3e,0x41,0x51,0x21,0x5e,0x7f,0x09,0x19,0x29,0x46,0x26,0x49,0x49,0x49,0x32,0x01,0x01,0x7f,0x01,0x01,0x3f,0x40,0x40,0x40,0x3f,0x1f,0x20,0x40,0x20,0x1f,0x3f,0x40,0x30,0x40,0x3f,0x63,0x14,0x08,0x14,0x63,0x07,0x08,0x70,0x08,0x07,0x61,0x51,0x49,0x45,0x43,0x00,0x7f,0x41,0x41,0x00,0x02,0x04,0x08,0x10,0x20,0x00,0x41,0x41,0x7f,0x00,0x04,0x02,0x01,0x02,0x04,0x40,0x40,0x40,0x40,0x40, -0x00,0x01,0x02,0x04,0x00,0x20,0x54,0x54,0x54,0x78,0x7f,0x48,0x44,0x44,0x38,0x38,0x44,0x44,0x44,0x20,0x38,0x44,0x44,0x48,0x7f,0x38,0x54,0x54,0x54,0x18,0x08,0x7e,0x09,0x01,0x02,0x0c,0x52,0x52,0x52,0x3e,0x7f,0x08,0x04,0x04,0x78,0x00,0x44,0x7d,0x40,0x00,0x20,0x40,0x44,0x3d,0x00,0x7f,0x10,0x28,0x44,0x00,0x00,0x41,0x7f,0x40,0x00,0x7c,0x04,0x18,0x04,0x78,0x7c,0x08,0x04,0x04,0x78,0x38,0x44,0x44,0x44,0x38, -0x7c,0x14,0x14,0x14,0x08,0x08,0x14,0x14,0x18,0x7c,0x7c,0x08,0x04,0x04,0x08,0x48,0x54,0x54,0x54,0x20,0x04,0x3f,0x44,0x40,0x20,0x3c,0x40,0x40,0x20,0x7c,0x1c,0x20,0x40,0x20,0x1c,0x3c,0x40,0x20,0x40,0x3c,0x44,0x28,0x10,0x28,0x44,0x0c,0x50,0x50,0x50,0x3c,0x44,0x64,0x54,0x4c,0x44,0x00,0x08,0x36,0x41,0x00,0x00,0x00,0x7f,0x00,0x00,0x00,0x41,0x36,0x08,0x00,0x08,0x08,0x22,0x1c,0x08,0x08,0x1c,0x22,0x08,0x08, -}; diff --git a/radio/bootloader/font_dblsize.lbm b/radio/bootloader/font_dblsize.lbm deleted file mode 100644 index f8533a669..000000000 --- a/radio/bootloader/font_dblsize.lbm +++ /dev/null @@ -1,16 +0,0 @@ -const uint8_t font_dblsize[] = { - -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, //' ' -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - -0xff,0xff,0xc3,0xc3,0xc3,0xc3,0xc3,0xe7,0xfe,0x3c, //'B' -0x3f,0x3f,0x30,0x30,0x30,0x30,0x30,0x39,0x1f,0x0f, - - -0x3c,0x7e,0xe7,0xc3,0xc3,0xc3,0xc3,0xc7,0x8e,0x0c, //'S' -0x0c,0x1c,0x38,0x30,0x30,0x30,0x30,0x39,0x1f,0x0f, - -0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0xff,0xff, //'U' -0x0f,0x1f,0x38,0x30,0x30,0x30,0x30,0x38,0x1f,0x0f, - -}; diff --git a/radio/bootloader/x9ddiskio.cpp b/radio/bootloader/x9ddiskio.cpp deleted file mode 100644 index 1fce8b45c..000000000 --- a/radio/bootloader/x9ddiskio.cpp +++ /dev/null @@ -1,1008 +0,0 @@ -/* - * Authors (alphabetical order) - * - Andre Bernet - * - Bertrand Songis - * - Bryan J. Rentoul (Gruvin) - * - Cameron Weeks - * - Erez Raviv - * - Jean-Pierre Parisy - * - Karl Szmutny - * - Michael Blandford - * - Michal Hlavinka - * - Pat Mackenzie - * - Philip Moss - * - Rob Thomson - * - Romolo Manfredini - * - Thomas Husterer - * - * open9x is based on code named - * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, - * er9x by Erez Raviv: http://code.google.com/p/er9x/, - * and the original (and ongoing) project by - * Thomas Husterer, th9x: http://code.google.com/p/th9x/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include "radio.h" -#include "diskio.h" -#include "ff.h" -#include "stm32f2xx_gpio.h" -#include "stm32f2xx_spi.h" -#include "stm32f2xx_rcc.h" -#include "logicio.h" -#include "hal.h" - -#define BOOL bool -#define FALSE false -#define TRUE true - -/* Definitions for MMC/SDC command */ -#define CMD0 (0x40+0) /* GO_IDLE_STATE */ -#define CMD1 (0x40+1) /* SEND_OP_COND (MMC) */ -#define ACMD41 (0xC0+41) /* SEND_OP_COND (SDC) */ -#define CMD8 (0x40+8) /* SEND_IF_COND */ -#define CMD9 (0x40+9) /* SEND_CSD */ -#define CMD10 (0x40+10) /* SEND_CID */ -#define CMD12 (0x40+12) /* STOP_TRANSMISSION */ -#define ACMD13 (0xC0+13) /* SD_STATUS (SDC) */ -#define CMD16 (0x40+16) /* SET_BLOCKLEN */ -#define CMD17 (0x40+17) /* READ_SINGLE_BLOCK */ -#define CMD18 (0x40+18) /* READ_MULTIPLE_BLOCK */ -#define CMD23 (0x40+23) /* SET_BLOCK_COUNT (MMC) */ -#define ACMD23 (0xC0+23) /* SET_WR_BLK_ERASE_COUNT (SDC) */ -#define CMD24 (0x40+24) /* WRITE_BLOCK */ -#define CMD25 (0x40+25) /* WRITE_MULTIPLE_BLOCK */ -#define CMD55 (0x40+55) /* APP_CMD */ -#define CMD58 (0x40+58) /* READ_OCR */ - -/* Card-Select Controls (Platform dependent) */ -#define SELECT() GPIO_ResetBits(GPIO_SPI_SD, GPIO_Pin_SPI_SD_CS) /* MMC CS = L */ -#define DESELECT() GPIO_SetBits(GPIO_SPI_SD, GPIO_Pin_SPI_SD_CS) /* MMC CS = H */ - -#if (_MAX_SS != 512) || (_FS_READONLY == 0) || (STM32_SD_DISK_IOCTRL_FORCE == 1) -#define STM32_SD_DISK_IOCTRL 1 -#else -#define STM32_SD_DISK_IOCTRL 0 -#endif - -#define BOOL bool -//#define FALSE false -//#define TRUE true - -/* Card type flags (CardType) */ -#define CT_MMC 0x01 -#define CT_SD1 0x02 -#define CT_SD2 0x04 -#define CT_SDC (CT_SD1|CT_SD2) -#define CT_BLOCK 0x08 - -int32_t Card_state; // = SD_ST_STARTUP ; -/*uint32_t Card_ID[4] ; -uint32_t Card_SCR[2] ; -uint32_t Card_CSD[4] ; -volatile uint32_t Card_initialized = 0; -uint32_t Sd_rca ; -uint32_t Cmd_A41_resp ; -uint8_t cardType; -uint32_t transSpeed; */ - -/*-----------------------------------------------------------------------*/ -/* Lock / unlock functions */ -/*-----------------------------------------------------------------------*/ -//int ff_cre_syncobj (BYTE vol, _SYNC_t *mutex) -//{ -// *mutex = CoCreateMutex(); -// return 1; -//} - -//int ff_req_grant (_SYNC_t mutex) -//{ -// CoEnterMutexSection(mutex); -// return 1; -//} - -//void ff_rel_grant (_SYNC_t mutex) -//{ -// CoLeaveMutexSection(mutex); -//} - -//int ff_del_syncobj (_SYNC_t mutex) -//{ -// return 1; -//} - -static const DWORD socket_state_mask_cp = (1 << 0); -static const DWORD socket_state_mask_wp = (1 << 1); - -static volatile -DSTATUS Stat = STA_NOINIT; /* Disk status */ - -static volatile -DWORD Timer1, Timer2; /* 100Hz decrement timers */ - -//static -BYTE CardType; /* Card type flags */ - -enum speed_setting { INTERFACE_SLOW, INTERFACE_FAST }; - -static void interface_speed( enum speed_setting speed ) -{ - DWORD tmp; - - tmp = SPI_SD->CR1; - if ( speed == INTERFACE_SLOW ) { - /* Set slow clock (100k-400k) */ - tmp = ( tmp | SPI_BaudRatePrescaler_128 ); - } else { - /* Set fast clock (depends on the CSD) */ - tmp = ( tmp & ~SPI_BaudRatePrescaler_128 ) | SPI_BaudRatePrescaler_SPI_SD; - } - SPI_SD->CR1 = tmp; -} - -static void socket_wp_init(void) -{ - return; -} - -static inline DWORD socket_is_write_protected(void) -{ - return 0; /* fake not protected */ -} - -static void socket_cp_init(void) -{ - return; -} - -DWORD socket_is_empty(void) -{ -// return 0; /* fake inserted */ - return GPIOD->IDR & GPIO_Pin_9 ; -} - -static void card_power(BYTE on) -{ - on=on; -} - -//#if (STM32_SD_DISK_IOCTRL == 1) -static int chk_power(void) -{ - return 1; /* fake powered */ -} -//#endif - -/*-----------------------------------------------------------------------*/ -/* Transmit/Receive a byte to MMC via SPI (Platform dependent) */ -/*-----------------------------------------------------------------------*/ -static BYTE stm32_spi_rw( BYTE out ) -{ - /* Loop while DR register in not empty */ - /// not needed: while (SPI_I2S_GetFlagStatus(SPI_SD, SPI_I2S_FLAG_TXE) == RESET) { ; } - - /* Send byte through the SPI peripheral */ - SPI_I2S_SendData(SPI_SD, out); - - /* Wait to receive a byte */ - while (SPI_I2S_GetFlagStatus(SPI_SD, SPI_I2S_FLAG_RXNE) == RESET) { ; } - - /* Return the byte read from the SPI bus */ - return SPI_I2S_ReceiveData(SPI_SD); -} - - - -/*-----------------------------------------------------------------------*/ -/* Transmit a byte to MMC via SPI (Platform dependent) */ -/*-----------------------------------------------------------------------*/ - -#define xmit_spi(dat) stm32_spi_rw(dat) - -/*-----------------------------------------------------------------------*/ -/* Receive a byte from MMC via SPI (Platform dependent) */ -/*-----------------------------------------------------------------------*/ - -static -BYTE rcvr_spi (void) -{ - return stm32_spi_rw(0xff); -} - -/* Alternative macro to receive data fast */ -#define rcvr_spi_m(dst) *(dst)=stm32_spi_rw(0xff) - - - -/*-----------------------------------------------------------------------*/ -/* Wait for card ready */ -/*-----------------------------------------------------------------------*/ - -static -BYTE wait_ready (void) -{ - BYTE res; - - - Timer2 = 50; /* Wait for ready in timeout of 500ms */ - rcvr_spi(); - do - res = rcvr_spi(); - while ((res != 0xFF) && Timer2); - - return res; -} - - - -/*-----------------------------------------------------------------------*/ -/* Deselect the card and release SPI bus */ -/*-----------------------------------------------------------------------*/ - -static -void release_spi (void) -{ - DESELECT(); - rcvr_spi(); -} - -#ifdef STM32_SD_USE_DMA -/*-----------------------------------------------------------------------*/ -/* Transmit/Receive Block using DMA (Platform dependent. STM32 here) */ -/*-----------------------------------------------------------------------*/ -static -void stm32_dma_transfer( - BOOL receive, /* FALSE for buff->SPI, TRUE for SPI->buff */ - const BYTE *buff, /* receive TRUE : 512 byte data block to be transmitted - receive FALSE : Data buffer to store received data */ - UINT btr /* receive TRUE : Byte count (must be multiple of 2) - receive FALSE : Byte count (must be 512) */ -) -{ - DMA_InitTypeDef DMA_InitStructure; - WORD rw_workbyte[] = { 0xffff }; - - /* shared DMA configuration values */ - DMA_InitStructure.DMA_PeripheralBaseAddr = (DWORD)(&(SPI_SD->DR)); - DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; - DMA_InitStructure.DMA_BufferSize = btr; - DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; - DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; - DMA_InitStructure.DMA_M2M = DMA_M2M_Disable; - - DMA_DeInit(DMA_Channel_SPI_SD_RX); - DMA_DeInit(DMA_Channel_SPI_SD_TX); - - if ( receive ) { - - /* DMA1 channel2 configuration SPI1 RX ---------------------------------------------*/ - /* DMA1 channel4 configuration SPI2 RX ---------------------------------------------*/ - DMA_InitStructure.DMA_MemoryBaseAddr = (DWORD)buff; - DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC; - DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; - DMA_Init(DMA_Channel_SPI_SD_RX, &DMA_InitStructure); - - /* DMA1 channel3 configuration SPI1 TX ---------------------------------------------*/ - /* DMA1 channel5 configuration SPI2 TX ---------------------------------------------*/ - DMA_InitStructure.DMA_MemoryBaseAddr = (DWORD)rw_workbyte; - DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST; - DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable; - DMA_Init(DMA_Channel_SPI_SD_TX, &DMA_InitStructure); - - } else { - -//#if _FS_READONLY == 0 - /* DMA1 channel2 configuration SPI1 RX ---------------------------------------------*/ - /* DMA1 channel4 configuration SPI2 RX ---------------------------------------------*/ - DMA_InitStructure.DMA_MemoryBaseAddr = (DWORD)rw_workbyte; - DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC; - DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable; - DMA_Init(DMA_Channel_SPI_SD_RX, &DMA_InitStructure); - - /* DMA1 channel3 configuration SPI1 TX ---------------------------------------------*/ - /* DMA1 channel5 configuration SPI2 TX ---------------------------------------------*/ - DMA_InitStructure.DMA_MemoryBaseAddr = (DWORD)buff; - DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST; - DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; - DMA_Init(DMA_Channel_SPI_SD_TX, &DMA_InitStructure); -//#endif - - } - - /* Enable DMA RX Channel */ - DMA_Cmd(DMA_Channel_SPI_SD_RX, ENABLE); - /* Enable DMA TX Channel */ - DMA_Cmd(DMA_Channel_SPI_SD_TX, ENABLE); - - /* Enable SPI TX/RX request */ - SPI_I2S_DMACmd(SPI_SD, SPI_I2S_DMAReq_Rx | SPI_I2S_DMAReq_Tx, ENABLE); - - /* Wait until DMA1_Channel 3 Transfer Complete */ - /// not needed: while (DMA_GetFlagStatus(DMA_FLAG_SPI_SD_TC_TX) == RESET) { ; } - /* Wait until DMA1_Channel 2 Receive Complete */ - while (DMA_GetFlagStatus(DMA_FLAG_SPI_SD_TC_RX) == RESET) { ; } - // same w/o function-call: - // while ( ( ( DMA1->ISR ) & DMA_FLAG_SPI_SD_TC_RX ) == RESET ) { ; } - - /* Disable DMA RX Channel */ - DMA_Cmd(DMA_Channel_SPI_SD_RX, DISABLE); - /* Disable DMA TX Channel */ - DMA_Cmd(DMA_Channel_SPI_SD_TX, DISABLE); - - /* Disable SPI RX/TX request */ - SPI_I2S_DMACmd(SPI_SD, SPI_I2S_DMAReq_Rx | SPI_I2S_DMAReq_Tx, DISABLE); -} -#endif /* STM32_SD_USE_DMA */ - - -/*-----------------------------------------------------------------------*/ -/* Power Control and interface-initialization (Platform dependent) */ -/*-----------------------------------------------------------------------*/ - -static void power_on (void) -{ - SPI_InitTypeDef SPI_InitStructure; - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable GPIO clock for CS */ - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIO_CS, ENABLE); - /* Enable SPI clock, SPI1: APB2, SPI2: APB1 */ - RCC_APBPeriphClockCmd_SPI_SD(RCC_APBPeriph_SPI_SD, ENABLE); - - GPIO_PinAFConfig(GPIO_SPI_SD,GPIO_PinSource_SCK ,GPIO_AF_SD); - GPIO_PinAFConfig(GPIO_SPI_SD,GPIO_PinSource_MISO,GPIO_AF_SD); - GPIO_PinAFConfig(GPIO_SPI_SD,GPIO_PinSource_MOSI,GPIO_AF_SD); - - card_power(1); - - socket_cp_init();//Empty return - socket_wp_init();//Empty return. - -#ifdef BOOT -extern void hw_delay( uint16_t time ) ; - uint32_t count = 125 ; - do - { - hw_delay(20000) ; - wdt_reset() ; - } while ( --count ) ; -#else - CoTickDelay(125); -#endif - // for (Timer1 = 25; Timer1; ); /* Wait for 250ms */ - - /* SPI configuration */ - SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; - SPI_InitStructure.SPI_Mode = SPI_Mode_Master; - SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; - SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; - SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; - SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; - SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_SPI_SD; // - SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; - SPI_InitStructure.SPI_CRCPolynomial = 7; - - SPI_Init(SPI_SD, &SPI_InitStructure); - SPI_CalculateCRC(SPI_SD, DISABLE); - SPI_Cmd(SPI_SD, ENABLE); - - /* De-select the Card: Chip Select high */ - DESELECT(); - - /* Configure I/O for Flash Chip select */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_SPI_SD_CS; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIO_SPI_SD, &GPIO_InitStructure); - - /* Configure SPI pins: SCK MISO and MOSI with alternate function push-down */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_SPI_SD_SCK | GPIO_Pin_SPI_SD_MOSI ; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(GPIO_SPI_SD, &GPIO_InitStructure); - - /* Configure SPI pins: SCK MISO and MOSI with alternate function push-down */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_SPI_SD_MISO; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(GPIO_SPI_SD, &GPIO_InitStructure); - -#ifdef STM32_SD_USE_DMA - /* enable DMA clock */ - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE); -#endif -} - -static -void power_off (void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - if (!(Stat & STA_NOINIT)) { - SELECT(); - wait_ready(); - release_spi(); - } - - SPI_I2S_DeInit(SPI_SD); - SPI_Cmd(SPI_SD, DISABLE); - RCC_APBPeriphClockCmd_SPI_SD(RCC_APBPeriph_SPI_SD, DISABLE); - - //All SPI-Pins to input with weak internal pull-downs // - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_SPI_SD_SCK | GPIO_Pin_SPI_SD_MISO | GPIO_Pin_SPI_SD_MOSI; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; - GPIO_Init(GPIO_SPI_SD, &GPIO_InitStructure); - - card_power(0); - - Stat |= STA_NOINIT; /* Set STA_NOINIT */ -} - - -/*-----------------------------------------------------------------------*/ -/* Receive a data packet from MMC */ -/*-----------------------------------------------------------------------*/ - -static -BOOL rcvr_datablock ( - BYTE *buff, /* Data buffer to store received data */ - UINT btr /* Byte count (must be multiple of 4) */ -) -{ - BYTE token; - - - Timer1 = 10; - do { /* Wait for data packet in timeout of 100ms */ - token = rcvr_spi(); - } while ((token == 0xFF) && Timer1); - if(token != 0xFE) return FALSE; /* If not valid data token, return with error */ - -#ifdef STM32_SD_USE_DMA - stm32_dma_transfer( TRUE, buff, btr ); -#else - do { /* Receive the data block into buffer */ - rcvr_spi_m(buff++); - rcvr_spi_m(buff++); - rcvr_spi_m(buff++); - rcvr_spi_m(buff++); - } while (btr -= 4); -#endif /* STM32_SD_USE_DMA */ - - rcvr_spi(); /* Discard CRC */ - rcvr_spi(); - - return TRUE; /* Return with success */ -} - - - -/*-----------------------------------------------------------------------*/ -/* Send a data packet to MMC */ -/*-----------------------------------------------------------------------*/ - -//#if _FS_READONLY == 0 -static -BOOL xmit_datablock ( - const BYTE *buff, /* 512 byte data block to be transmitted */ - BYTE token /* Data/Stop token */ -) -{ - BYTE resp; -#ifndef STM32_SD_USE_DMA - BYTE wc; -#endif - - if (wait_ready() != 0xFF) return FALSE; - - xmit_spi(token); /* transmit data token */ - if (token != 0xFD) { /* Is data token */ - -#ifdef STM32_SD_USE_DMA - stm32_dma_transfer( FALSE, buff, 512 ); -#else - wc = 0; - do { /* transmit the 512 byte data block to MMC */ - xmit_spi(*buff++); - xmit_spi(*buff++); - } while (--wc); -#endif /* STM32_SD_USE_DMA */ - - xmit_spi(0xFF); /* CRC (Dummy) */ - xmit_spi(0xFF); - resp = rcvr_spi(); /* Receive data response */ - if ((resp & 0x1F) != 0x05) /* If not accepted, return with error */ - return FALSE; - } - - return TRUE; -} -//#endif /* _READONLY */ - - - -/*-----------------------------------------------------------------------*/ -/* Send a command packet to MMC */ -/*-----------------------------------------------------------------------*/ - -static -BYTE send_cmd ( - BYTE cmd, /* Command byte */ - DWORD arg /* Argument */ -) -{ - BYTE n, res; - - - if (cmd & 0x80) { /* ACMD is the command sequence of CMD55-CMD */ - cmd &= 0x7F; - res = send_cmd(CMD55, 0); - if (res > 1) return res; - } - - /* Select the card and wait for ready */ - SELECT(); - if (wait_ready() != 0xFF) { - return 0xFF; - } - - /* Send command packet */ - xmit_spi(cmd); /* Start + Command index */ - xmit_spi((BYTE)(arg >> 24)); /* Argument[31..24] */ - xmit_spi((BYTE)(arg >> 16)); /* Argument[23..16] */ - xmit_spi((BYTE)(arg >> 8)); /* Argument[15..8] */ - xmit_spi((BYTE)arg); /* Argument[7..0] */ - n = 0x01; /* Dummy CRC + Stop */ - if (cmd == CMD0) n = 0x95; /* Valid CRC for CMD0(0) */ - if (cmd == CMD8) n = 0x87; /* Valid CRC for CMD8(0x1AA) */ - xmit_spi(n); - - /* Receive command response */ - if (cmd == CMD12) rcvr_spi(); /* Skip a stuff byte when stop reading */ - - n = 10; /* Wait for a valid response in timeout of 10 attempts */ - do - res = rcvr_spi(); - while ((res & 0x80) && --n); - - return res; /* Return with the response value */ -} - - - -/*-------------------------------------------------------------------------- - - Public Functions - ----------------------------------------------------------------------------*/ - - -/*-----------------------------------------------------------------------*/ -/* Initialize Disk Drive */ -/*-----------------------------------------------------------------------*/ - -DSTATUS disk_initialize ( - BYTE drv /* Physical drive number (0) */ -) -{ - BYTE n, cmd, ty, ocr[4]; - - if (drv) return STA_NOINIT; /* Supports only single drive */ - if (Stat & STA_NODISK) return Stat; /* No card in the socket */ - - power_on(); /* Force socket power on and initialize interface */ - interface_speed(INTERFACE_SLOW); - for (n = 10; n; n--) rcvr_spi(); /* 80 dummy clocks */ - - ty = 0; - if (send_cmd(CMD0, 0) == 1) { /* Enter Idle state */ - Timer1 = 100; /* Initialization timeout of 1000 milliseconds */ - if (send_cmd(CMD8, 0x1AA) == 1) { /* SDHC */ - for (n = 0; n < 4; n++) ocr[n] = rcvr_spi(); /* Get trailing return value of R7 response */ - if (ocr[2] == 0x01 && ocr[3] == 0xAA) { /* The card can work at VDD range of 2.7-3.6V */ - while (Timer1 && send_cmd(ACMD41, 1UL << 30)); /* Wait for leaving idle state (ACMD41 with HCS bit) */ - if (Timer1 && send_cmd(CMD58, 0) == 0) { /* Check CCS bit in the OCR */ - for (n = 0; n < 4; n++) ocr[n] = rcvr_spi(); - ty = (ocr[0] & 0x40) ? CT_SD2 | CT_BLOCK : CT_SD2; - } - } - } else { /* SDSC or MMC */ - if (send_cmd(ACMD41, 0) <= 1) { - ty = CT_SD1; cmd = ACMD41; /* SDSC */ - } else { - ty = CT_MMC; cmd = CMD1; /* MMC */ - } - while (Timer1 && send_cmd(cmd, 0)); /* Wait for leaving idle state */ - if (!Timer1 || send_cmd(CMD16, 512) != 0) /* Set R/W block length to 512 */ - ty = 0; - } - } - CardType = ty; - release_spi(); - - if (ty) { /* Initialization succeeded */ - Stat &= ~STA_NOINIT; /* Clear STA_NOINIT */ - interface_speed(INTERFACE_FAST); - } else { /* Initialization failed */ -// power_off(); - } - - return Stat; -} - - - -/*-----------------------------------------------------------------------*/ -/* Get Disk Status */ -/*-----------------------------------------------------------------------*/ - -DSTATUS disk_status ( - BYTE drv /* Physical drive number (0) */ -) -{ - if (drv) return STA_NOINIT; /* Supports only single drive */ - return Stat; -} - - - -/*-----------------------------------------------------------------------*/ -/* Read Sector(s) */ -/*-----------------------------------------------------------------------*/ - -// TODO quick & dirty -int8_t SD_ReadSectors(uint8_t *buff, uint32_t sector, uint32_t count) -{ - if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert to byte address if needed */ - - if (send_cmd(CMD18, sector) == 0) { /* READ_MULTIPLE_BLOCK */ - do { - if (!rcvr_datablock(buff, 512)) { - break; - } - buff += 512; - } while (--count); - send_cmd(CMD12, 0); /* STOP_TRANSMISSION */ - } - - release_spi(); - - return 0; -} - -DRESULT disk_read ( - BYTE drv, /* Physical drive number (0) */ - BYTE *buff, /* Pointer to the data buffer to store read data */ - DWORD sector, /* Start sector number (LBA) */ - BYTE count /* Sector count (1..255) */ -) -{ - if (drv || !count) return RES_PARERR; - if (Stat & STA_NOINIT) return RES_NOTRDY; - - if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert to byte address if needed */ - - if (count == 1) { /* Single block read */ - if (send_cmd(CMD17, sector) == 0) { /* READ_SINGLE_BLOCK */ - if (rcvr_datablock(buff, 512)) { - count = 0; - } - } - } - else { /* Multiple block read */ - if (send_cmd(CMD18, sector) == 0) { /* READ_MULTIPLE_BLOCK */ - do { - if (!rcvr_datablock(buff, 512)) { - break; - } - buff += 512; - } while (--count); - send_cmd(CMD12, 0); /* STOP_TRANSMISSION */ - } - } - release_spi(); - - return count ? RES_ERROR : RES_OK; -} - - - -/*-----------------------------------------------------------------------*/ -/* Write Sector(s) */ -/*-----------------------------------------------------------------------*/ - -//#if _FS_READONLY == 0 - -// TODO quick & dirty -int8_t SD_WriteSectors(uint8_t *buff, uint32_t sector, uint32_t count) -{ - if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert to byte address if needed */ - if (CardType & CT_SDC) send_cmd(ACMD23, count); - if (send_cmd(CMD25, sector) == 0) { /* WRITE_MULTIPLE_BLOCK */ - do { - if (!xmit_datablock(buff, 0xFC)) break; - buff += 512; - } while (--count); - if (!xmit_datablock(0, 0xFD)) /* STOP_TRAN token */ - count = 1; - } - - release_spi(); - - return 0; -} - -DRESULT disk_write ( - BYTE drv, /* Physical drive number (0) */ - const BYTE *buff, /* Pointer to the data to be written */ - DWORD sector, /* Start sector number (LBA) */ - BYTE count /* Sector count (1..255) */ -) -{ - if (drv || !count) return RES_PARERR; - if (Stat & STA_NOINIT) return RES_NOTRDY; - if (Stat & STA_PROTECT) return RES_WRPRT; - - if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert to byte address if needed */ - - if (count == 1) { /* Single block write */ - if ((send_cmd(CMD24, sector) == 0) /* WRITE_BLOCK */ - && xmit_datablock(buff, 0xFE)) - count = 0; - } - else { /* Multiple block write */ - if (CardType & CT_SDC) send_cmd(ACMD23, count); - if (send_cmd(CMD25, sector) == 0) { /* WRITE_MULTIPLE_BLOCK */ - do { - if (!xmit_datablock(buff, 0xFC)) break; - buff += 512; - } while (--count); - if (!xmit_datablock(0, 0xFD)) /* STOP_TRAN token */ - count = 1; - } - } - release_spi(); - - return count ? RES_ERROR : RES_OK; -} -//#endif /* _READONLY == 0 */ - - - -/*-----------------------------------------------------------------------*/ -/* Miscellaneous Functions */ -/*-----------------------------------------------------------------------*/ - -//#if (STM32_SD_DISK_IOCTRL == 1) -DRESULT disk_ioctl ( - BYTE drv, /* Physical drive number (0) */ - BYTE ctrl, /* Control code */ - BYTE *buff /* Buffer to send/receive control data */ -) -{ - DRESULT res; - BYTE n, csd[16], *ptr = (BYTE *)buff; - WORD csize; - - if (drv) return RES_PARERR; - - res = RES_ERROR; - - if (ctrl == CTRL_POWER) { - switch (*ptr) { - case 0: /* Sub control code == 0 (POWER_OFF) */ - if (chk_power()) - power_off(); /* Power off */ - res = RES_OK; - break; - case 1: /* Sub control code == 1 (POWER_ON) */ - power_on(); /* Power on */ - res = RES_OK; - break; - case 2: /* Sub control code == 2 (POWER_GET) */ - *(ptr+1) = (BYTE)chk_power(); - res = RES_OK; - break; - default : - res = RES_PARERR; - } - } - else { - if (Stat & STA_NOINIT) return RES_NOTRDY; - - switch (ctrl) { - case CTRL_SYNC : /* Make sure that no pending write process */ - SELECT(); - if (wait_ready() == 0xFF) - res = RES_OK; - break; - - case GET_SECTOR_COUNT : /* Get number of sectors on the disk (DWORD) */ - if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { - if ((csd[0] >> 6) == 1) { /* SDC version 2.00 */ - csize = csd[9] + ((WORD)csd[8] << 8) + 1; - *(DWORD*)buff = (DWORD)csize << 10; - } else { /* SDC version 1.XX or MMC*/ - n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + ((csd[9] & 3) << 1) + 2; - csize = (csd[8] >> 6) + ((WORD)csd[7] << 2) + ((WORD)(csd[6] & 3) << 10) + 1; - *(DWORD*)buff = (DWORD)csize << (n - 9); - } - res = RES_OK; - } - break; - - case GET_SECTOR_SIZE : /* Get R/W sector size (WORD) */ - *(WORD*)buff = 512; - res = RES_OK; - break; - - case GET_BLOCK_SIZE : /* Get erase block size in unit of sector (DWORD) */ - if (CardType & CT_SD2) { /* SDC version 2.00 */ - if (send_cmd(ACMD13, 0) == 0) { /* Read SD status */ - rcvr_spi(); - if (rcvr_datablock(csd, 16)) { /* Read partial block */ - for (n = 64 - 16; n; n--) rcvr_spi(); /* Purge trailing data */ - *(DWORD*)buff = 16UL << (csd[10] >> 4); - res = RES_OK; - } - } - } else { /* SDC version 1.XX or MMC */ - if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { /* Read CSD */ - if (CardType & CT_SD1) { /* SDC version 1.XX */ - *(DWORD*)buff = (((csd[10] & 63) << 1) + ((WORD)(csd[11] & 128) >> 7) + 1) << ((csd[13] >> 6) - 1); - } else { /* MMC */ - *(DWORD*)buff = ((WORD)((csd[10] & 124) >> 2) + 1) * (((csd[11] & 3) << 3) + ((csd[11] & 224) >> 5) + 1); - } - res = RES_OK; - } - } - break; - - case MMC_GET_TYPE : /* Get card type flags (1 byte) */ - *ptr = CardType; - res = RES_OK; - break; - - case MMC_GET_CSD : /* Receive CSD as a data block (16 bytes) */ - if (send_cmd(CMD9, 0) == 0 /* READ_CSD */ - && rcvr_datablock(ptr, 16)) - res = RES_OK; - break; - - case MMC_GET_CID : /* Receive CID as a data block (16 bytes) */ - if (send_cmd(CMD10, 0) == 0 /* READ_CID */ - && rcvr_datablock(ptr, 16)) - res = RES_OK; - break; - - case MMC_GET_OCR : /* Receive OCR as an R3 resp (4 bytes) */ - if (send_cmd(CMD58, 0) == 0) { /* READ_OCR */ - for (n = 4; n; n--) *ptr++ = rcvr_spi(); - res = RES_OK; - } - break; - - case MMC_GET_SDSTAT : /* Receive SD status as a data block (64 bytes) */ - if (send_cmd(ACMD13, 0) == 0) { /* SD_STATUS */ - rcvr_spi(); - if (rcvr_datablock(ptr, 64)) - res = RES_OK; - } - break; - - default: - res = RES_PARERR; - } - - release_spi(); - } - - return res; -} -//#endif /* _USE_IOCTL != 0 */ - - -/*-----------------------------------------------------------------------*/ -/* Device Timer Interrupt Procedure (Platform dependent) */ -/*-----------------------------------------------------------------------*/ -/* This function must be called in period of 10ms */ - -void sdPoll10ms() -{ - static DWORD pv; - DWORD ns; - BYTE n, s; - - - n = Timer1; /* 100Hz decrement timers */ - if (n) Timer1 = --n; - n = Timer2; - if (n) Timer2 = --n; - - ns = pv; - pv = socket_is_empty() | socket_is_write_protected(); /* Sample socket switch */ - - if (ns == pv) { /* Have contacts stabled? */ - s = Stat; - - if (pv & socket_state_mask_wp) /* WP is H (write protected) */ - s |= STA_PROTECT; - else /* WP is L (write enabled) */ - s &= ~STA_PROTECT; - - if (pv & socket_state_mask_cp) /* INS = H (Socket empty) */ - s |= (STA_NODISK | STA_NOINIT); - else /* INS = L (Card inserted) */ - s &= ~STA_NODISK; - - Stat = s; - } -} - -FATFS g_FATFS_Obj; - -void sdInit() -{ - FRESULT fr ; - if (( fr = f_mount(0, &g_FATFS_Obj)) == FR_OK) - { - -// refreshSystemAudioFiles() ; - Card_state = 100 ; - } -} - -uint32_t sdMounted() -{ - // Should check for card present as well - return Card_state == 100 ; -} - -void sdMountPoll() -{ - /* TODO a define - static uint8_t mountTimer; - if (mountTimer-- == 0) { - mountTimer = 100; - if (!sdMounted()) { - sdInit(); - } - }*/ -} - - -// Checks for card ready for read/write -// returns 1 for YES, 0 for NO -uint32_t sd_card_ready( void ) -{ -// if ( CardIsConnected() ) -// { - if ( Card_state == 100 ) - { - return 1 ; - } -// } - return 0 ; -} - - From 43733d4e660c4a4ac13f5475d5013b8f06e41af1 Mon Sep 17 00:00:00 2001 From: bsongis Date: Wed, 5 Mar 2014 11:53:21 +0100 Subject: [PATCH 038/285] 4 more files removed --- radio/bootloader/include/core_cm3.h | 1818 ----- radio/bootloader/include/stm32f2xx.h | 6966 ------------------- radio/bootloader/include/stm32f2xx_flash.h | 340 - radio/bootloader/include/system_stm32f2xx.h | 105 - radio/bootloader/logicioboot.cpp | 9 - 5 files changed, 9238 deletions(-) delete mode 100644 radio/bootloader/include/core_cm3.h delete mode 100644 radio/bootloader/include/stm32f2xx.h delete mode 100644 radio/bootloader/include/stm32f2xx_flash.h delete mode 100644 radio/bootloader/include/system_stm32f2xx.h diff --git a/radio/bootloader/include/core_cm3.h b/radio/bootloader/include/core_cm3.h deleted file mode 100644 index 4afe42cda..000000000 --- a/radio/bootloader/include/core_cm3.h +++ /dev/null @@ -1,1818 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V1.30 - * @date 30. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CM3_CORE_H__ -#define __CM3_CORE_H__ - -/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration - * - * List of Lint messages which will be suppressed and not shown: - * - Error 10: \n - * register uint32_t __regBasePri __asm("basepri"); \n - * Error 10: Expecting ';' - * . - * - Error 530: \n - * return(__regBasePri); \n - * Warning 530: Symbol '__regBasePri' (line 264) not initialized - * . - * - Error 550: \n - * __regBasePri = (basePri & 0x1ff); \n - * Warning 550: Symbol '__regBasePri' (line 271) not accessed - * . - * - Error 754: \n - * uint32_t RESERVED0[24]; \n - * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced - * . - * - Error 750: \n - * #define __CM3_CORE_H__ \n - * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced - * . - * - Error 528: \n - * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n - * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced - * . - * - Error 751: \n - * } InterruptType_Type; \n - * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced - * . - * Note: To re-enable a Message, insert a space before 'lint' * - * - */ - -/*lint -save */ -/*lint -e10 */ -/*lint -e530 */ -/*lint -e550 */ -/*lint -e754 */ -/*lint -e750 */ -/*lint -e528 */ -/*lint -e751 */ - - -/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core registers and bitfields - - Cortex-M core peripheral base address - @{ - */ - -#ifdef __cplusplus - extern "C" { -#endif - -#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex core */ - -#include /* Include standard types */ - -#if defined (__ICCARM__) - #include /* IAR Intrinsics */ -#endif - - -#ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ -#endif - - - - -/** - * IO definitions - * - * define access restrictions to peripheral registers - */ - -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register - @{ -*/ - - -/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC - memory mapped structure for Nested Vectored Interrupt Controller (NVIC) - @{ - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ -} NVIC_Type; -/*@}*/ /* end of group CMSIS_CM3_NVIC */ - - -/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB - memory mapped structure for System Control Block (SCB) - @{ - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (0x1ul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ -/*@}*/ /* end of group CMSIS_CM3_SCB */ - - -/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick - memory mapped structure for SysTick - @{ - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ -/*@}*/ /* end of group CMSIS_CM3_SysTick */ - - -/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM - memory mapped structure for Instrumentation Trace Macrocell (ITM) - @{ - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ - __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ - __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ -/*@}*/ /* end of group CMSIS_CM3_ITM */ - - -/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type - memory mapped structure for Interrupt Type - @{ - */ -typedef struct -{ - uint32_t RESERVED0; - __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ -#else - uint32_t RESERVED1; -#endif -} InterruptType_Type; - -/* Interrupt Controller Type Register Definitions */ -#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ -#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ -#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ - -#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ -#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ - -#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ -#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ -/*@}*/ /* end of group CMSIS_CM3_InterruptType */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) -/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU - memory mapped structure for Memory Protection Unit (MPU) - @{ - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ -#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ -#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ -#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ -#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ -#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ -#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@}*/ /* end of group CMSIS_CM3_MPU */ -#endif - - -/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug - memory mapped structure for Core Debug Register - @{ - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ -/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ - - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ - -#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ -#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ -#endif - -/*@}*/ /* end of group CMSIS_CM3_core_register */ - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#define __enable_fault_irq __enable_fiq -#define __disable_fault_irq __disable_fiq - -#define __NOP __nop -#define __WFI __wfi -#define __WFE __wfe -#define __SEV __sev -#define __ISB() __isb(0) -#define __DSB() __dsb(0) -#define __DMB() __dmb(0) -#define __REV __rev -#define __RBIT __rbit -#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) -#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) -#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) -#define __STREXB(value, ptr) __strex(value, ptr) -#define __STREXH(value, ptr) __strex(value, ptr) -#define __STREXW(value, ptr) __strex(value, ptr) - - -/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ -/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -extern int32_t __REVSH(int16_t value); - - -#if (__ARMCC_VERSION < 400000) - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -extern void __CLREX(void); - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -extern uint32_t __get_BASEPRI(void); - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -extern void __set_BASEPRI(uint32_t basePri); - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -extern uint32_t __get_PRIMASK(void); - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -extern void __set_PRIMASK(uint32_t priMask); - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -extern uint32_t __get_FAULTMASK(void); - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -extern void __set_FAULTMASK(uint32_t faultMask); - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -extern uint32_t __get_CONTROL(void); - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -extern void __set_CONTROL(uint32_t control); - -#else /* (__ARMCC_VERSION >= 400000) */ - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -#define __CLREX __clrex - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -static __INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -static __INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -static __INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -static __INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & 1); -} - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -static __INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -static __INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ -#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ - -static __INLINE void __enable_fault_irq( void ) { __ASM ("cpsie f"); } -static __INLINE void __disable_fault_irq( void ) { __ASM ("cpsid f"); } - -#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ -static __INLINE void __WFI( void ) { __ASM ("wfi"); } -static __INLINE void __WFE( void ) { __ASM ("wfe"); } -static __INLINE void __SEV( void ) { __ASM ("sev"); } -static __INLINE void __CLREX( void ) { __ASM ("clrex"); } - -/* intrinsic void __ISB(void) */ -/* intrinsic void __DSB(void) */ -/* intrinsic void __DMB(void) */ -/* intrinsic void __set_PRIMASK(); */ -/* intrinsic void __get_PRIMASK(); */ -/* intrinsic void __set_FAULTMASK(); */ -/* intrinsic void __get_FAULTMASK(); */ -/* intrinsic uint32_t __REV(uint32_t value); */ -/* intrinsic uint32_t __REVSH(uint32_t value); */ -/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ -/* intrinsic unsigned long __LDREX(unsigned long *); */ - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -extern uint32_t __RBIT(uint32_t value); - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit values) - */ -extern uint8_t __LDREXB(uint8_t *addr); - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -extern uint16_t __LDREXH(uint16_t *addr); - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -extern uint32_t __LDREXW(uint32_t *addr); - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -extern uint32_t __STREXB(uint8_t value, uint8_t *addr); - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -extern uint32_t __STREXH(uint16_t value, uint16_t *addr); - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -extern uint32_t __STREXW(uint32_t value, uint32_t *addr); - - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -static __INLINE void __enable_irq(void) { __ASM volatile ("cpsie i"); } -static __INLINE void __disable_irq(void) { __ASM volatile ("cpsid i"); } - -static __INLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f"); } -static __INLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f"); } - -static __INLINE void __NOP(void) { __ASM volatile ("nop"); } -static __INLINE void __WFI(void) { __ASM volatile ("wfi"); } -static __INLINE void __WFE(void) { __ASM volatile ("wfe"); } -static __INLINE void __SEV(void) { __ASM volatile ("sev"); } -static __INLINE void __ISB(void) { __ASM volatile ("isb"); } -static __INLINE void __DSB(void) { __ASM volatile ("dsb"); } -static __INLINE void __DMB(void) { __ASM volatile ("dmb"); } -static __INLINE void __CLREX(void) { __ASM volatile ("clrex"); } - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -extern uint32_t __get_BASEPRI(void); - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -extern void __set_BASEPRI(uint32_t basePri); - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -extern uint32_t __get_PRIMASK(void); - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -extern void __set_PRIMASK(uint32_t priMask); - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -extern uint32_t __get_FAULTMASK(void); - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -extern void __set_FAULTMASK(uint32_t faultMask); - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -extern uint32_t __get_CONTROL(void); - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -extern void __set_CONTROL(uint32_t control); - -/** - * @brief Reverse byte order in integer value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -extern uint32_t __REV(uint32_t value); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -extern int32_t __REVSH(int16_t value); - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -extern uint32_t __RBIT(uint32_t value); - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit value - */ -extern uint8_t __LDREXB(uint8_t *addr); - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -extern uint16_t __LDREXH(uint16_t *addr); - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -extern uint32_t __LDREXW(uint32_t *addr); - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -extern uint32_t __STREXB(uint8_t value, uint8_t *addr); - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -extern uint32_t __STREXH(uint16_t value, uint16_t *addr); - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -extern uint32_t __STREXW(uint32_t value, uint32_t *addr); - - -#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - - -/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface - Core Function Interface containing: - - Core NVIC Functions - - Core SysTick Functions - - Core Reset Functions -*/ -/*@{*/ - -/* ########################## NVIC functions #################################### */ - -/** - * @brief Set the Priority Grouping in NVIC Interrupt Controller - * - * @param PriorityGroup is priority grouping field - * - * Set the priority grouping field using the required unlock sequence. - * The parameter priority_grouping is assigned to the field - * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - */ -static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - (0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - -/** - * @brief Get the Priority Grouping from NVIC Interrupt Controller - * - * @return priority grouping field - * - * Get the priority grouping from NVIC Interrupt Controller. - * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. - */ -static __INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - -/** - * @brief Enable Interrupt in NVIC Interrupt Controller - * - * @param IRQn The positive number of the external interrupt to enable - * - * Enable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - -/** - * @brief Disable the interrupt line for external interrupt specified - * - * @param IRQn The positive number of the external interrupt to disable - * - * Disable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - -/** - * @brief Read the interrupt pending bit for a device specific interrupt source - * - * @param IRQn The number of the device specifc interrupt - * @return 1 = interrupt pending, 0 = interrupt not pending - * - * Read the pending register in NVIC and return 1 if its status is pending, - * otherwise it returns 0 - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - -/** - * @brief Set the pending bit for an external interrupt - * - * @param IRQn The number of the interrupt for set pending - * - * Set the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - -/** - * @brief Clear the pending bit for an external interrupt - * - * @param IRQn The number of the interrupt for clear pending - * - * Clear the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - -/** - * @brief Read the active bit for an external interrupt - * - * @param IRQn The number of the interrupt for read active bit - * @return 1 = interrupt active, 0 = interrupt not active - * - * Read the active register in NVIC and returns 1 if its status is active, - * otherwise it returns 0. - */ -static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - -/** - * @brief Set the priority for an interrupt - * - * @param IRQn The number of the interrupt for set priority - * @param priority The priority to set - * - * Set the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - -/** - * @brief Read the priority for an interrupt - * - * @param IRQn The number of the interrupt for get priority - * @return The priority for the interrupt - * - * Read the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * The returned priority value is automatically aligned to the implemented - * priority bits of the microcontroller. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** - * @brief Encode the priority for an interrupt - * - * @param PriorityGroup The used priority group - * @param PreemptPriority The preemptive priority value (starting from 0) - * @param SubPriority The sub priority value (starting from 0) - * @return The encoded priority for the interrupt - * - * Encode the priority for an interrupt with the given priority group, - * preemptive priority value and sub priority value. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - * - * The returned priority value can be used for NVIC_SetPriority(...) function - */ -static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** - * @brief Decode the priority of an interrupt - * - * @param Priority The priority for the interrupt - * @param PriorityGroup The used priority group - * @param pPreemptPriority The preemptive priority value (starting from 0) - * @param pSubPriority The sub priority value (starting from 0) - * - * Decode an interrupt priority value with the given priority group to - * preemptive priority value and sub priority value. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - * - * The priority value can be retrieved with NVIC_GetPriority(...) function - */ -static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - - -/* ################################## SysTick function ############################################ */ - -#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) - -/** - * @brief Initialize and start the SysTick counter and its interrupt. - * - * @param ticks number of ticks between two interrupts - * @return 1 = failed, 0 = successful - * - * Initialise the system tick timer and its interrupt and start the - * system tick timer / counter in free running mode to generate - * periodical interrupts. - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - - - - -/* ################################## Reset function ############################################ */ - -/** - * @brief Initiate a system reset request. - * - * Initiate a system reset request to reset the MCU - */ -static __INLINE void NVIC_SystemReset(void) -{ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ - - - -/* ##################################### Debug In/Output function ########################################### */ - -/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface - Core Debug Interface containing: - - Core Debug Receive / Transmit Functions - - Core Debug Defines - - Core Debug Variables -*/ -/*@{*/ - -extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ - - -/** - * @brief Outputs a character via the ITM channel 0 - * - * @param ch character to output - * @return character to output - * - * The function outputs a character via the ITM channel 0. - * The function returns when no debugger is connected that has booked the output. - * It is blocking when a debugger is connected, but the previous character send is not transmitted. - */ -static __INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ - (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** - * @brief Inputs a character via variable ITM_RxBuffer - * - * @return received character, -1 = no character received - * - * The function inputs a character via variable ITM_RxBuffer. - * The function returns when no debugger is connected that has booked the output. - * It is blocking when a debugger is connected, but the previous character send is not transmitted. - */ -static __INLINE int ITM_ReceiveChar (void) { - int ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - * @brief Check if a character via variable ITM_RxBuffer is available - * - * @return 1 = character available, 0 = no character available - * - * The function checks variable ITM_RxBuffer whether a character is available or not. - * The function returns '1' if a character is available and '0' if no character is available. - */ -static __INLINE int ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ /* end of group CMSIS_CM3_core_definitions */ - -#endif /* __CM3_CORE_H__ */ - -/*lint -restore */ diff --git a/radio/bootloader/include/stm32f2xx.h b/radio/bootloader/include/stm32f2xx.h deleted file mode 100644 index d62d9396a..000000000 --- a/radio/bootloader/include/stm32f2xx.h +++ /dev/null @@ -1,6966 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx.h - * @author MCD Application Team - * @version V1.1.3 - * @date 05-March-2012 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32F2xx devices. - * - * The file is the unique include file that the application programmer - * is using in the C source code, usually in main.c. This file contains: - * - Configuration section that allows to select: - * - The device used in the target application - * - To use or not the peripherals drivers in application code(i.e. - * code will be based on direct access to peripherals registers - * rather than drivers API), this option is controlled by - * "#define USE_STDPERIPH_DRIVER" - * - To change few application-specific parameters such as the HSE - * crystal frequency - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f2xx - * @{ - */ - -#ifndef __STM32F2xx_H -#define __STM32F2xx_H - -// TODO added by BSS -#define assert_param(xx) - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/* Uncomment the line below according to the target STM32 device used in your - application - */ - -#if !defined (STM32F2XX) - #define STM32F2XX -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ - -#if !defined (STM32F2XX) - #error "Please select first the target STM32F2XX device used in your application (in stm32f2xx.h file)" -#endif - -#if !defined (USE_STDPERIPH_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_STDPERIPH_DRIVER*/ -#endif /* USE_STDPERIPH_DRIVER */ - -/** - * @brief In the following line adjust the value of External High Speed oscillator (HSE) - used in your application - - Tip: To avoid modifying this file each time you need to use different HSE, you - can define the HSE value in your toolchain compiler preprocessor. - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -/** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - Timeout value - */ -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ -#endif /* HSE_STARTUP_TIMEOUT */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief STM32F2XX Standard Peripherals Library version number V1.1.3 - */ -#define __STM32F2XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F2XX_STDPERIPH_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ -#define __STM32F2XX_STDPERIPH_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ -#define __STM32F2XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32F2XX_STDPERIPH_VERSION ((__STM32F2XX_STDPERIPH_VERSION_MAIN << 24)\ - |(__STM32F2XX_STDPERIPH_VERSION_SUB1 << 16)\ - |(__STM32F2XX_STDPERIPH_VERSION_SUB2 << 8)\ - |(__STM32F2XX_STDPERIPH_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */ -#define __MPU_PRESENT 1 /*!< STM32F2XX provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32F2XX uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @brief STM32F2XX Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ****************************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ -/****** STM32 specific Interrupt Numbers **********************************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ - DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ - DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ - DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ - DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ - DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ - DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ - ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ - OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ - OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ - OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ - DCMI_IRQn = 78, /*!< DCMI global interrupt */ - CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ - HASH_RNG_IRQn = 80 /*!< Hash and Rng global interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm3.h" -#include "system_stm32f2xx.h" -#include - -/** @addtogroup Exported_types - * @{ - */ -/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ -typedef int32_t s32; -typedef int16_t s16; -typedef int8_t s8; - -typedef const int32_t sc32; /*!< Read Only */ -typedef const int16_t sc16; /*!< Read Only */ -typedef const int8_t sc8; /*!< Read Only */ - -typedef __IO int32_t vs32; -typedef __IO int16_t vs16; -typedef __IO int8_t vs8; - -typedef __I int32_t vsc32; /*!< Read Only */ -typedef __I int16_t vsc16; /*!< Read Only */ -typedef __I int8_t vsc8; /*!< Read Only */ - -typedef uint32_t u32; -typedef uint16_t u16; -typedef uint8_t u8; - -typedef const uint32_t uc32; /*!< Read Only */ -typedef const uint16_t uc16; /*!< Read Only */ -typedef const uint8_t uc8; /*!< Read Only */ - -typedef __IO uint32_t vu32; -typedef __IO uint16_t vu16; -typedef __IO uint8_t vu8; - -typedef __I uint32_t vuc32; /*!< Read Only */ -typedef __I uint16_t vuc16; /*!< Read Only */ -typedef __I uint8_t vuc8; /*!< Read Only */ - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - -/** - * @} - */ - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ - __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ - __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ - __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ - __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ - __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ - __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual - AND triple modes, Address offset: ADC1 base address + 0x308 */ -} ADC_Common_TypeDef; - - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ - __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ - __IO uint32_t TDLR; /*!< CAN mailbox data low register */ - __IO uint32_t TDHR; /*!< CAN mailbox data high register */ -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ - __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ - __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ - __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ - __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ - __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ - __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ - __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ - __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ - __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ - __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ - __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ - uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ - CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ - uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ - __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ - __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ - uint32_t RESERVED2; /*!< Reserved, 0x208 */ - __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ - uint32_t RESERVED3; /*!< Reserved, 0x210 */ - __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ - uint32_t RESERVED4; /*!< Reserved, 0x218 */ - __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ - CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ -} CAN_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, 0x05 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DCMI - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ - __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ - __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ - __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ - __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ - __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ - __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ - __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ - __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ - __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ - __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ -} DCMI_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DMA stream x configuration register */ - __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ - __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ -} DMA_Stream_TypeDef; - -typedef struct -{ - __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ - __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ - __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ - __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ -} DMA_TypeDef; - -/** - * @brief Ethernet MAC - */ - -typedef struct -{ - __IO uint32_t MACCR; - __IO uint32_t MACFFR; - __IO uint32_t MACHTHR; - __IO uint32_t MACHTLR; - __IO uint32_t MACMIIAR; - __IO uint32_t MACMIIDR; - __IO uint32_t MACFCR; - __IO uint32_t MACVLANTR; /* 8 */ - uint32_t RESERVED0[2]; - __IO uint32_t MACRWUFFR; /* 11 */ - __IO uint32_t MACPMTCSR; - uint32_t RESERVED1[2]; - __IO uint32_t MACSR; /* 15 */ - __IO uint32_t MACIMR; - __IO uint32_t MACA0HR; - __IO uint32_t MACA0LR; - __IO uint32_t MACA1HR; - __IO uint32_t MACA1LR; - __IO uint32_t MACA2HR; - __IO uint32_t MACA2LR; - __IO uint32_t MACA3HR; - __IO uint32_t MACA3LR; /* 24 */ - uint32_t RESERVED2[40]; - __IO uint32_t MMCCR; /* 65 */ - __IO uint32_t MMCRIR; - __IO uint32_t MMCTIR; - __IO uint32_t MMCRIMR; - __IO uint32_t MMCTIMR; /* 69 */ - uint32_t RESERVED3[14]; - __IO uint32_t MMCTGFSCCR; /* 84 */ - __IO uint32_t MMCTGFMSCCR; - uint32_t RESERVED4[5]; - __IO uint32_t MMCTGFCR; - uint32_t RESERVED5[10]; - __IO uint32_t MMCRFCECR; - __IO uint32_t MMCRFAECR; - uint32_t RESERVED6[10]; - __IO uint32_t MMCRGUFCR; - uint32_t RESERVED7[334]; - __IO uint32_t PTPTSCR; - __IO uint32_t PTPSSIR; - __IO uint32_t PTPTSHR; - __IO uint32_t PTPTSLR; - __IO uint32_t PTPTSHUR; - __IO uint32_t PTPTSLUR; - __IO uint32_t PTPTSAR; - __IO uint32_t PTPTTHR; - __IO uint32_t PTPTTLR; - __IO uint32_t RESERVED8; - __IO uint32_t PTPTSSR; /* added for STM32F2xx */ - uint32_t RESERVED9[565]; - __IO uint32_t DMABMR; - __IO uint32_t DMATPDR; - __IO uint32_t DMARPDR; - __IO uint32_t DMARDLAR; - __IO uint32_t DMATDLAR; - __IO uint32_t DMASR; - __IO uint32_t DMAOMR; - __IO uint32_t DMAIER; - __IO uint32_t DMAMFBOCR; - __IO uint32_t DMARSWTR; /* added for STM32F2xx */ - uint32_t RESERVED10[8]; - __IO uint32_t DMACHTDR; - __IO uint32_t DMACHRDR; - __IO uint32_t DMACHTBAR; - __IO uint32_t DMACHRBAR; -} ETH_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ -} EXTI_TypeDef; - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ - __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ - __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ - __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ - __IO uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x14 */ -} FLASH_TypeDef; - -/** - * @brief Flexible Static Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ -} FSMC_Bank1_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ -} FSMC_Bank1E_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank2 - */ - -typedef struct -{ - __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ - __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ - __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ - __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ - uint32_t RESERVED0; /*!< Reserved, 0x70 */ - __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ -} FSMC_Bank2_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank3 - */ - -typedef struct -{ - __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ - __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ - __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ - __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ - uint32_t RESERVED0; /*!< Reserved, 0x90 */ - __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ -} FSMC_Bank3_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank4 - */ - -typedef struct -{ - __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ - __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ - __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ - __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ - __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ -} FSMC_Bank4_TypeDef; - -/** - * @brief General Purpose I/O - */ - -typedef struct -{ - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ - __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ -} GPIO_TypeDef; - -/** - * @brief System configuration controller - */ - -typedef struct -{ - __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ - __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ - __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ - uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ - __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ -} SYSCFG_TypeDef; - -/** - * @brief Inter-integrated Circuit Interface - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ - __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ - __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ -} IWDG_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ - __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ -} PWR_TypeDef; - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ - __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ - __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ - __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ - __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ - __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ - __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ - uint32_t RESERVED0; /*!< Reserved, 0x1C */ - __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ - __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ - __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ - __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ - __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ - uint32_t RESERVED2; /*!< Reserved, 0x3C */ - __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ - __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ - uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ - __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ - __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ - __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ - uint32_t RESERVED4; /*!< Reserved, 0x5C */ - __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ - __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ - uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ - __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ - __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ - uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ - __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ - __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ - __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - uint32_t RESERVED1; /*!< Reserved, 0x28 */ - uint32_t RESERVED2; /*!< Reserved, 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - uint32_t RESERVED3; /*!< Reserved, 0x38 */ - uint32_t RESERVED4; /*!< Reserved, 0x3C */ - __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ - uint32_t RESERVED5; /*!< Reserved, 0x44 */ - uint32_t RESERVED6; /*!< Reserved, 0x48 */ - uint32_t RESERVED7; /*!< Reserved, 0x4C */ - __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ - __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ - __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ - __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ - __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ - __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ - __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ - __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ - __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ - __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ - __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ - __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ - __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ - __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ - __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ - __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ - __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ - __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ - __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ - __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ -} RTC_TypeDef; - -/** - * @brief SD host Interface - */ - -typedef struct -{ - __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ - __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ - __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ - __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ - __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ - __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ - __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ - __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ - __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ - __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ - __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ - __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ - __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ - __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ - __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ - __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ - uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ - __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ - uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ - __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ -} SDIO_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ -} SPI_TypeDef; - -/** - * @brief TIM - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ - __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ - __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ - __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ - __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ - __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ - __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ - __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - uint16_t RESERVED11; /*!< Reserved, 0x46 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ - uint16_t RESERVED14; /*!< Reserved, 0x52 */ -} TIM_TypeDef; - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ -} USART_TypeDef; - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ - __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ -} WWDG_TypeDef; - -/** - * @brief Crypto Processor - */ - -typedef struct -{ - __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */ - __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ - __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ - __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ - __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ - __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ - __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ - __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ - __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ - __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ - __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ - __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ - __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ - __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ - __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ - __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ - __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ - __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ -} CRYP_TypeDef; - -/** - * @brief HASH - */ - -typedef struct -{ - __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ - __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ - __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ - __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ - __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ - __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ - uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ - __IO uint32_t CSR[51]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1C0 */ -} HASH_TypeDef; - -/** - * @brief HASH - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ -} RNG_TypeDef; - -/** - * @} - */ - -/** @addtogroup Peripheral_memory_map - * @{ - */ - -#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ - -#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ - -#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) - -/*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) -#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) -#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) -#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) - -/*!< APB2 peripherals */ -#define TIM1_BASE (APB2PERIPH_BASE + 0x0000) -#define TIM8_BASE (APB2PERIPH_BASE + 0x0400) -#define USART1_BASE (APB2PERIPH_BASE + 0x1000) -#define USART6_BASE (APB2PERIPH_BASE + 0x1400) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2100) -#define ADC3_BASE (APB2PERIPH_BASE + 0x2200) -#define ADC_BASE (APB2PERIPH_BASE + 0x2300) -#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) -#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) -#define TIM9_BASE (APB2PERIPH_BASE + 0x4000) -#define TIM10_BASE (APB2PERIPH_BASE + 0x4400) -#define TIM11_BASE (APB2PERIPH_BASE + 0x4800) - -/*!< AHB1 peripherals */ -#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) -#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) -#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) -#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) -#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) -#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) -#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) -#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) -#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) -#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) -#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) -#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) -#define BKPSRAM_BASE (AHB1PERIPH_BASE + 0x4000) -#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) -#define DMA1_Stream0_BASE (DMA1_BASE + 0x010) -#define DMA1_Stream1_BASE (DMA1_BASE + 0x028) -#define DMA1_Stream2_BASE (DMA1_BASE + 0x040) -#define DMA1_Stream3_BASE (DMA1_BASE + 0x058) -#define DMA1_Stream4_BASE (DMA1_BASE + 0x070) -#define DMA1_Stream5_BASE (DMA1_BASE + 0x088) -#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) -#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) -#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) -#define DMA2_Stream0_BASE (DMA2_BASE + 0x010) -#define DMA2_Stream1_BASE (DMA2_BASE + 0x028) -#define DMA2_Stream2_BASE (DMA2_BASE + 0x040) -#define DMA2_Stream3_BASE (DMA2_BASE + 0x058) -#define DMA2_Stream4_BASE (DMA2_BASE + 0x070) -#define DMA2_Stream5_BASE (DMA2_BASE + 0x088) -#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) -#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) -#define ETH_BASE (AHB1PERIPH_BASE + 0x8000) -#define ETH_MAC_BASE (ETH_BASE) -#define ETH_MMC_BASE (ETH_BASE + 0x0100) -#define ETH_PTP_BASE (ETH_BASE + 0x0700) -#define ETH_DMA_BASE (ETH_BASE + 0x1000) - -/*!< AHB2 peripherals */ -#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) -#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000) -#define HASH_BASE (AHB2PERIPH_BASE + 0x60400) -#define RNG_BASE (AHB2PERIPH_BASE + 0x60800) - -/*!< FSMC Bankx registers base address */ -#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) -#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) -#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) -#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) -#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) - -/* Debug MCU registers base address */ -#define DBGMCU_BASE ((uint32_t )0xE0042000) - -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define TIM12 ((TIM_TypeDef *) TIM12_BASE) -#define TIM13 ((TIM_TypeDef *) TIM13_BASE) -#define TIM14 ((TIM_TypeDef *) TIM14_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define I2C3 ((I2C_TypeDef *) I2C3_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define CAN2 ((CAN_TypeDef *) CAN2_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define TIM8 ((TIM_TypeDef *) TIM8_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define USART6 ((USART_TypeDef *) USART6_BASE) -#define ADC ((ADC_Common_TypeDef *) ADC_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) -#define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define TIM9 ((TIM_TypeDef *) TIM9_BASE) -#define TIM10 ((TIM_TypeDef *) TIM10_BASE) -#define TIM11 ((TIM_TypeDef *) TIM11_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) -#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) -#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) -#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) -#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) -#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) -#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) -#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) -#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) -#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) -#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) -#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) -#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) -#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) -#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) -#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) -#define ETH ((ETH_TypeDef *) ETH_BASE) -#define DCMI ((DCMI_TypeDef *) DCMI_BASE) -#define CRYP ((CRYP_TypeDef *) CRYP_BASE) -#define HASH ((HASH_TypeDef *) HASH_BASE) -#define RNG ((RNG_TypeDef *) RNG_BASE) -#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) -#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) -#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) -#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) -#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter */ -/* */ -/******************************************************************************/ -/******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD ((uint8_t)0x01) /*!*/ - -#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!*/ - -/***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!
© COPYRIGHT 2012 STMicroelectronics
- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_FLASH_H -#define __STM32F2xx_FLASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** - * @brief FLASH Status - */ -typedef enum -{ - FLASH_BUSY = 1, - FLASH_ERROR_PGS, - FLASH_ERROR_PGP, - FLASH_ERROR_PGA, - FLASH_ERROR_WRP, - FLASH_ERROR_PROGRAM, - FLASH_ERROR_OPERATION, - FLASH_COMPLETE -}FLASH_Status; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup FLASH_Exported_Constants - * @{ - */ - -/** @defgroup Flash_Latency - * @{ - */ -#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */ -#define FLASH_Latency_1 ((uint8_t)0x0001) /*!< FLASH One Latency cycle */ -#define FLASH_Latency_2 ((uint8_t)0x0002) /*!< FLASH Two Latency cycles */ -#define FLASH_Latency_3 ((uint8_t)0x0003) /*!< FLASH Three Latency cycles */ -#define FLASH_Latency_4 ((uint8_t)0x0004) /*!< FLASH Four Latency cycles */ -#define FLASH_Latency_5 ((uint8_t)0x0005) /*!< FLASH Five Latency cycles */ -#define FLASH_Latency_6 ((uint8_t)0x0006) /*!< FLASH Six Latency cycles */ -#define FLASH_Latency_7 ((uint8_t)0x0007) /*!< FLASH Seven Latency cycles */ - -#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ - ((LATENCY) == FLASH_Latency_1) || \ - ((LATENCY) == FLASH_Latency_2) || \ - ((LATENCY) == FLASH_Latency_3) || \ - ((LATENCY) == FLASH_Latency_4) || \ - ((LATENCY) == FLASH_Latency_5) || \ - ((LATENCY) == FLASH_Latency_6) || \ - ((LATENCY) == FLASH_Latency_7)) -/** - * @} - */ - -/** @defgroup FLASH_Voltage_Range - * @{ - */ -#define VoltageRange_1 ((uint8_t)0x00) /*!< Device operating range: 1.8V to 2.1V */ -#define VoltageRange_2 ((uint8_t)0x01) /*!= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\ - (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F))) -/** - * @} - */ - -/** @defgroup Option_Bytes_Write_Protection - * @{ - */ -#define OB_WRP_Sector_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */ -#define OB_WRP_Sector_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */ -#define OB_WRP_Sector_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */ -#define OB_WRP_Sector_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */ -#define OB_WRP_Sector_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */ -#define OB_WRP_Sector_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */ -#define OB_WRP_Sector_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */ -#define OB_WRP_Sector_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */ -#define OB_WRP_Sector_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */ -#define OB_WRP_Sector_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */ -#define OB_WRP_Sector_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */ -#define OB_WRP_Sector_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */ -#define OB_WRP_Sector_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */ - -#define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_Read_Protection - * @{ - */ -#define OB_RDP_Level_0 ((uint8_t)0xAA) -#define OB_RDP_Level_1 ((uint8_t)0x55) -/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2 - it's no more possible to go back to level 1 or 0 */ -#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\ - ((LEVEL) == OB_RDP_Level_1))/*||\ - ((LEVEL) == OB_RDP_Level_2))*/ -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_IWatchdog - * @{ - */ -#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */ -#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ -#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_nRST_STOP - * @{ - */ -#define OB_STOP_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ -#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) -/** - * @} - */ - - -/** @defgroup FLASH_Option_Bytes_nRST_STDBY - * @{ - */ -#define OB_STDBY_NoRST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ -#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) -/** - * @} - */ - -/** @defgroup FLASH_BOR_Reset_Level - * @{ - */ -#define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */ -#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */ -#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */ -#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */ -#define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\ - ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF)) -/** - * @} - */ - -/** @defgroup FLASH_Interrupts - * @{ - */ -#define FLASH_IT_EOP ((uint32_t)0x01000000) /*!< End of FLASH Operation Interrupt source */ -#define FLASH_IT_ERR ((uint32_t)0x02000000) /*!< Error Interrupt source */ -#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000)) -/** - * @} - */ - -/** @defgroup FLASH_Flags - * @{ - */ -#define FLASH_FLAG_EOP ((uint32_t)0x00000001) /*!< FLASH End of Operation flag */ -#define FLASH_FLAG_OPERR ((uint32_t)0x00000002) /*!< FLASH operation Error flag */ -#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ -#define FLASH_FLAG_PGAERR ((uint32_t)0x00000020) /*!< FLASH Programming Alignment error flag */ -#define FLASH_FLAG_PGPERR ((uint32_t)0x00000040) /*!< FLASH Programming Parallelism error flag */ -#define FLASH_FLAG_PGSERR ((uint32_t)0x00000080) /*!< FLASH Programming Sequence error flag */ -#define FLASH_FLAG_BSY ((uint32_t)0x00010000) /*!< FLASH Busy flag */ -#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF0C) == 0x00000000) && ((FLAG) != 0x00000000)) -#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \ - ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \ - ((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \ - ((FLAG) == FLASH_FLAG_BSY)) -/** - * @} - */ - -/** @defgroup FLASH_Program_Parallelism - * @{ - */ -#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000) -#define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100) -#define FLASH_PSIZE_WORD ((uint32_t)0x00000200) -#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300) -#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF) -/** - * @} - */ - -/** @defgroup FLASH_Keys - * @{ - */ -#define RDP_KEY ((uint16_t)0x00A5) -#define FLASH_KEY1 ((uint32_t)0x45670123) -#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) -#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B) -#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F) -/** - * @} - */ - -/** - * @brief ACR register byte 0 (Bits[8:0]) base address - */ -#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00) -/** - * @brief OPTCR register byte 3 (Bits[24:16]) base address - */ -#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14) -#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15) -#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16) - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* FLASH Interface configuration functions ************************************/ -void FLASH_SetLatency(uint32_t FLASH_Latency); -void FLASH_PrefetchBufferCmd(FunctionalState NewState); -void FLASH_InstructionCacheCmd(FunctionalState NewState); -void FLASH_DataCacheCmd(FunctionalState NewState); -void FLASH_InstructionCacheReset(void); -void FLASH_DataCacheReset(void); - -/* FLASH Memory Programming functions *****************************************/ -void FLASH_Unlock(void); -void FLASH_Lock(void); -FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange); -FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange); -FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data); -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); -FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data); - -/* Option Bytes Programming functions *****************************************/ -void FLASH_OB_Unlock(void); -void FLASH_OB_Lock(void); -void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState); -void FLASH_OB_RDPConfig(uint8_t OB_RDP); -void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); -void FLASH_OB_BORConfig(uint8_t OB_BOR); -FLASH_Status FLASH_OB_Launch(void); -uint8_t FLASH_OB_GetUser(void); -uint16_t FLASH_OB_GetWRP(void); -FlagStatus FLASH_OB_GetRDP(void); -uint8_t FLASH_OB_GetBOR(void); - -/* Interrupts and flags management functions **********************************/ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); -void FLASH_ClearFlag(uint32_t FLASH_FLAG); -FLASH_Status FLASH_GetStatus(void); -FLASH_Status FLASH_WaitForLastOperation(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F2xx_FLASH_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/include/system_stm32f2xx.h b/radio/bootloader/include/system_stm32f2xx.h deleted file mode 100644 index eef082fcd..000000000 --- a/radio/bootloader/include/system_stm32f2xx.h +++ /dev/null @@ -1,105 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f2xx.h - * @author MCD Application Team - * @version V1.1.3 - * @date 05-March-2012 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f2xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32F2XX_H -#define __SYSTEM_STM32F2XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32F2xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32F2xx_System_Exported_types - * @{ - */ - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32F2XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/logicioboot.cpp b/radio/bootloader/logicioboot.cpp index 67f44866a..3b7f02dce 100644 --- a/radio/bootloader/logicioboot.cpp +++ b/radio/bootloader/logicioboot.cpp @@ -32,17 +32,8 @@ #include "hal.h" #endif - -#ifndef SIMU -#include "core_cm3.h" -#endif - #include "logicio.h" -#ifdef PCBSKY -#include "lcd.h" -#endif - #ifndef SIMU #ifdef PCBSKY From a2235f1bda1d194e4ac03c5bd149b55d1655395b Mon Sep 17 00:00:00 2001 From: bsongis Date: Wed, 5 Mar 2014 11:54:03 +0100 Subject: [PATCH 039/285] 2 more files removed --- radio/bootloader/include/board.h | 714 ------------------------------- radio/bootloader/include/chip.h | 130 ------ 2 files changed, 844 deletions(-) delete mode 100644 radio/bootloader/include/board.h delete mode 100644 radio/bootloader/include/chip.h diff --git a/radio/bootloader/include/board.h b/radio/bootloader/include/board.h deleted file mode 100644 index 0af66e835..000000000 --- a/radio/bootloader/include/board.h +++ /dev/null @@ -1,714 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/** - * \page sam3s_ek_board_desc "SAM3S-EK - Board Description" - * - * \section - * A file is dedicated to descibe the AT91SAM3S-EK board. - * - * \section Contents - * - The code for booting the board is provided by board_cstartup.S and - * board_lowlevel.c. - * - For using board PIOs, board characteristics (clock, etc.) and external - * components, see board.h. - * - For manipulating memories (remapping, SDRAM, etc.), see board_memories.h. - * - * To get more software details and the full list of parameters related to the - * SAM3S-EK board configuration, please have a look at the source file: \n - * \ref board.h\n - * - * This file can be used as a template and modified to fit a custom board, with - * specific PIOs usage or memory connections. - **/ -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -/// \file board.h -/// -/// \par Purpose -/// -/// Definition of AT91SAM3S-EK characteristics, AT91SAM3S-dependant PIOs and -/// external components interfacing. -/// -/// \par Usage -/// -# For operating frequency information, see "SAM3S-EK - Operating frequencies". -/// -# For using portable PIO definitions, see "SAM3S-EK - PIO definitions". -/// -# Several USB definitions are included here (see "SAM3S-EK - USB device"). -//------------------------------------------------------------------------------ - -#ifndef BOARD_H -#define BOARD_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -/* These headers were introduced in C99 by working group ISO/IEC JTC1/SC22/WG14. */ -#include - -#ifdef SIMU -#define CONVERT_PTR(x) ((uint32_t)(uint64_t)(x)) -#else -//#include "core_cm3.h" -#define CONVERT_PTR(x) ((uint32_t)(x)) -#endif - -#ifndef SIMU -#include -#if defined(at91sam3s4) - #include "chip.h" - #include "AT91SAM3S4.h" -#else - #if defined(at91sam3s8) - #include "chip.h" - #include "AT91SAM3S4.h" - #else - #error Board does not support the specified chip. - #endif -#endif -#endif - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \par -/// This page lists several definition related to the board description. -/// -/// Definitions -/// - BOARD_NAME - -/// Name of the board. -#define BOARD_NAME "AT91SAM3S-EK" -/// Board definition. -#define at91sam3sek -/// Family definition (already defined). -#define at91sam3s -/// Core definition -#define cortexm3 - -//#define BOARD_REV_A -#define BOARD_REV_B - -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \par sam3s_ek_opfreq "SAM3S-EK - Operating frequencies" -/// This page lists several definition related to the board operating frequency -/// (when using the initialization done by board_lowlevel.c). -/// -/// !Definitions -/// - BOARD_MAINOSC -/// - BOARD_MCK - -/// Frequency of the board main oscillator. -#define BOARD_MAINOSC 12000000 - -/// Master clock frequency (when using board_lowlevel.c). -//#define BOARD_MCK 48000000 -#define BOARD_MCK 64000000 - -//------------------------------------------------------------------------------ -// ADC -//------------------------------------------------------------------------------ - -/// Startup time max, return from Idle mode (in s) -#define ADC_STARTUP_TIME_MAX 15 -/// Track and hold Acquisition Time min (in ns) -#define ADC_TRACK_HOLD_TIME_MIN 1200 - -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// USB attributes configuration descriptor (bus or self powered, remote wakeup) -//#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_RWAKEUP -#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \par sam3s_ek_piodef "SAM3S-EK - PIO definitions" -/// This pages lists all the pio definitions contained in board.h. The constants -/// are named using the following convention: PIN_* for a constant which defines -/// a single Pin instance (but may include several PIOs sharing the same -/// controller), and PINS_* for a list of Pin instances. -/// -/// !ADC -/// - PIN_ADC0_AD0 -/// - PIN_ADC0_AD1 -/// - PIN_ADC0_AD2 -/// - PIN_ADC0_AD3 -/// - PIN_ADC0_AD4 -/// - PIN_ADC0_AD5 -/// - PIN_ADC0_AD6 -/// - PIN_ADC0_AD7 -/// - PINS_ADC0 -/// -/// !UART -/// - PINS_UART -/// -/// !EBI -/// - PIN_EBI_DATA_BUS -/// - PIN_EBI_NCS0 -/// - PIN_EBI_NRD -/// - PIN_EBI_NWE -/// - PIN_EBI_ADDR_BUS -/// - PIN_EBI_PSRAM_NBS -/// - PIN_EBI_A1 -/// - PIN_EBI_LCD_RS -/// -/// !LEDs -/// - PIN_LED_0 -/// - PIN_LED_1 -/// - PIN_LED_2 -/// - PINS_LEDS -/// -/// !MCI -/// - PINS_MCI -/// -/// !Push buttons -/// - PIN_PUSHBUTTON_1 -/// - PIN_PUSHBUTTON_2 -/// - PINS_PUSHBUTTONS -/// - PUSHBUTTON_BP1 -/// - PUSHBUTTON_BP2 -/// -/// !PWMC -/// - PIN_PWMC_PWMH0 -/// - PIN_PWMC_PWML0 -/// - PIN_PWMC_PWMH1 -/// - PIN_PWMC_PWML1 -/// - PIN_PWMC_PWMH2 -/// - PIN_PWMC_PWML2 -/// - PIN_PWMC_PWMH3 -/// - PIN_PWMC_PWML3 -/// - PIN_PWM_LED0 -/// - PIN_PWM_LED1 -/// - PIN_PWM_LED2 -/// - CHANNEL_PWM_LED0 -/// - CHANNEL_PWM_LED1 -/// - CHANNEL_PWM_LED2 -/// -/// !SPI -/// - PIN_SPI_MISO -/// - PIN_SPI_MOSI -/// - PIN_SPI_SPCK -/// - PINS_SPI -/// - PIN_SPI_NPCS0_PA11 -/// -/// ! SSC -/// - PIN_SSC_TD -/// - PIN_SSC_TK -/// - PIN_SSC_TF -/// - PINS_SSC_CODEC -/// -/// ! PCK0 -/// - PIN_PCK0 -/// -/// !TWI -/// - PIN_TWI_TWD0 -/// - PIN_TWI_TWCK0 -/// - PINS_TWI -/// -/// !USART0 -/// - PIN_USART0_RXD -/// - PIN_USART0_TXD -/// - PIN_USART0_CTS -/// - PIN_USART0_RTS -/// - PIN_USART0_SCK -/// -/// !USB -/// - PIN_USB_PULLUP -/// - -/// ADC_AD0 pin definition. -#define PIN_ADC0_AD0 {1 << 21, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD1 pin definition. -#define PIN_ADC0_AD1 {1 << 30, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD2 pin definition. -#define PIN_ADC0_AD2 {1 << 3, PIOB, ID_PIOB, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD3 pin definition. -#define PIN_ADC0_AD3 {1 << 4, PIOB, ID_PIOB, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD4 pin definition. -#define PIN_ADC0_AD4 {1 << 15, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD5 pin definition. -#define PIN_ADC0_AD5 {1 << 16, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD6 pin definition. -#define PIN_ADC0_AD6 {1 << 17, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD7 pin definition. -#define PIN_ADC0_AD7 {1 << 18, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} - -/// Pins ADC -#define PINS_ADC PIN_ADC0_AD0, PIN_ADC0_AD1, PIN_ADC0_AD2, PIN_ADC0_AD3, PIN_ADC0_AD4, PIN_ADC0_AD5, PIN_ADC0_AD6, PIN_ADC0_AD7 - -/** UART pins (UTXD0 and URXD0) definitions, PA9,10. */ -#define PINS_UART {0x00000600, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} - -/// EBI -#define PIN_EBI_DATA_BUS {0xFF, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_NRD {1 << 11, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_NWE {1 << 8, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} - -#define PIN_EBI_NCS0 {1 << 20, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_PSRAM_ADDR_BUS {0x3f00fff, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_PSRAM_NBS {1 << 7, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_PULLUP}, \ - {1 << 15, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_A1 {1 << 19, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} - -#define PIN_EBI_NCS1 {1 << 15, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} /* LCD CS pin */ -#define PIN_EBI_LCD_RS {1 << 19, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} /* LCD RS pin */ - -#ifdef BOARD_REV_A -/** LED #0 pin definition. */ -#define PIN_LED_0 {1 << 20, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} -/** LED #1 pin definition. */ -#define PIN_LED_1 {1 << 21, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} -/** LED #2 pin definition. */ -#define PIN_LED_2 {1 << 22, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} -#endif -#ifdef BOARD_REV_B -/** LED #0 pin definition. */ -#define PIN_LED_0 {1 << 19, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} -/** LED #1 pin definition. */ -#define PIN_LED_1 {1 << 20, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} -/** LED #2 pin definition. */ -#define PIN_LED_2 {1 << 20, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} -#endif - -/** List of all LEDs definitions. */ -#define PINS_LEDS PIN_LED_0, PIN_LED_1, PIN_LED_2 - -/// MCI pins definition. -#define PINS_MCI {0x1f8, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_PULLUP}, \ - {1 << 3, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} - -/// MCI pin Card Detect -#define PIN_MCI_CD \ - {AT91C_PIO_PA25, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP} - -/** Push button #0 definition. Attributes = pull-up + debounce + interrupt on rising edge. */ -#define PIN_PUSHBUTTON_1 {1 << 3, PIOB, ID_PIOB, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE} -/** Push button #1 definition. Attributes = pull-up + debounce + interrupt on falling edge. */ -#define PIN_PUSHBUTTON_2 {1 << 12, PIOC, ID_PIOC, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE} -/** List of all push button definitions. */ -#define PINS_PUSHBUTTONS PIN_PUSHBUTTON_1, PIN_PUSHBUTTON_2 - -/** Push button #1 index. */ -#define PUSHBUTTON_BP1 0 -/** Push button #2 index. */ -#define PUSHBUTTON_BP2 1 - -/// Simulated joystick LEFT index. -#define JOYSTICK_LEFT 0 -/// Simulated joystick RIGHT index. -#define JOYSTICK_RIGHT 1 - -/** PWMC PWM0 pin definition. */ -#define PIN_PWMC_PWMH0 {1 << 18, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} -#define PIN_PWMC_PWML0 {1 << 19, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} -/** PWMC PWM1 pin definition. */ -#define PIN_PWMC_PWMH1 {1 << 19, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} -#define PIN_PWMC_PWML1 {1 << 20, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} -/** PWMC PWM2 pin definition. */ -#define PIN_PWMC_PWMH2 {1 << 20, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} -#define PIN_PWMC_PWML2 {1 << 16, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT} -/** PWMC PWM3 pin definition. */ -#define PIN_PWMC_PWMH3 {1 << 21, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} -#define PIN_PWMC_PWML3 {1 << 15, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT} -/** PWM pin definition for LED0 */ -#define PIN_PWM_LED0 PIN_PWMC_PWMH0, PIN_PWMC_PWML0 -/** PWM pin definition for LED1 */ -#define PIN_PWM_LED1 PIN_PWMC_PWMH2, PIN_PWMC_PWML2 -/** PWM pin definition for LED2 */ -#define PIN_PWM_LED2 PIN_PWMC_PWMH3, PIN_PWMC_PWML3 -/** PWM channel for LED0 */ -#define CHANNEL_PWM_LED0 0 -/** PWM channel for LED1 */ -#define CHANNEL_PWM_LED1 2 -/** PWM channel for LED2 */ -#define CHANNEL_PWM_LED2 3 - -/** SPI MISO pin definition. */ -#define PIN_SPI_MISO {1 << 12, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -/** SPI MOSI pin definition. */ -#define PIN_SPI_MOSI {1 << 13, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -/** SPI SPCK pin definition. */ -#define PIN_SPI_SPCK {1 << 14, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -/** SPI chip select pin definition. */ -#define PIN_SPI_NPCS0_PA11 {1 << 11, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -/** List of SPI pin definitions (MISO, MOSI & SPCK). */ -#define PINS_SPI PIN_SPI_MISO, PIN_SPI_MOSI, PIN_SPI_SPCK - -/// SSC pins definition. -#define PIN_SSC_TD {0x1 << 26, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_SSC_TK {0x1 << 28, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_SSC_TF {0x1 << 30, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PINS_SSC_CODEC PIN_SSC_TD, PIN_SSC_TK, PIN_SSC_TF - -/// PCK0 -#define PIN_PCK0 {0x1 << 21, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} - -/// TWI pins definition. -#define TWI_V3XX -#define PIN_TWI_TWD0 {0x1 << 9, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_TWI_TWCK0 {0x1 << 10, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PINS_TWI0 PIN_TWI_TWD0, PIN_TWI_TWCK0 -#define PIN_TWI_TWD1 {0x1 << 24, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_TWI_TWCK1 {0x1 << 25, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PINS_TWI1 PIN_TWI_TWD1, PIN_TWI_TWCK1 - -/// USART0 -#define PIN_USART0_RXD {0x1 << 19, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART0_TXD {0x1 << 18, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART0_CTS {0x1 << 8, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART0_RTS {0x1 << 7, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART0_SCK {0x1 << 17, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} - -/// USART1 -#define PIN_USART1_RXD {0x1 << 21, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART1_TXD {0x1 << 22, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART1_CTS {0x1 << 25, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART1_RTS {0x1 << 24, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART1_EN {0x1 << 23, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT} - - - -/// USB VBus monitoring pin definition. -#ifdef BOARD_REV_A -#define PIN_USB_VBUS {1 << 23, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} -#endif -#ifdef BOARD_REV_B -#define PIN_USB_VBUS {1 << 21, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} -#endif - -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \par sam3s_ek_extcomp "SAM3S-EK - External components" -/// This page lists the definitions related to external on-board components -/// located in the board.h file for the AT91SAM3S-EK. -/// -/// !AT45 Dataflash Card -/// - BOARD_AT45_A_SPI_BASE -/// - BOARD_AT45_A_SPI_ID -/// - BOARD_AT45_A_SPI_PINS -/// - BOARD_AT45_A_SPI -/// - BOARD_AT45_A_NPCS -/// - BOARD_AT45_A_NPCS_PIN -/// -/// !AT45 Dataflash (serial onboard DataFlash) -/// - BOARD_AT45_B_SPI_BASE -/// - BOARD_AT45_B_SPI_ID -/// - BOARD_AT45_B_SPI_PINS -/// - BOARD_AT45_B_SPI -/// - BOARD_AT45_B_NPCS -/// - BOARD_AT45_B_NPCS_PIN -/// -/// !AT26 Serial Flash -/// - BOARD_AT26_A_SPI_BASE -/// - BOARD_AT26_A_SPI_ID -/// - BOARD_AT26_A_SPI_PINS -/// - BOARD_AT26_A_SPI -/// - BOARD_AT26_A_NPCS -/// - BOARD_AT26_A_NPCS_PIN -/// -/// !SD Card -/// - MCI2_INTERFACE -/// - BOARD_SD_MCI_BASE -/// - BOARD_SD_MCI_ID -/// - BOARD_SD_PINS -/// - BOARD_SD_SLOT -/// -/// !PSRAM -/// - BOARD_PSRAM_PINS -/// -/// !LCD -/// - BOARD_LCD_ILI9325 -/// - BOARD_LCD_PINS -/// - BOARD_BACKLIGHT_PIN -/// - BOARD_LCD_BASE -/// - BOARD_LCD_RS -/// - BOARD_LCD_WIDTH -/// - BOARD_LCD_HEIGHT -/// -/// !TouchScreen -/// - BOARD_TSC_ADS7843 -/// - PIN_TCS_IRQ -/// - PIN_TCS_BUSY -/// - BOARD_TSC_SPI_BASE -/// - BOARD_TSC_SPI_ID -/// - BOARD_TSC_SPI_PINS -/// - BOARD_TSC_NPCS -/// - BOARD_TSC_NPCS_PIN -/// -/// Base address of SPI peripheral connected to the dataflash. -//#define BOARD_AT45_A_SPI_BASE SPI0 -///// Identifier of SPI peripheral connected to the dataflash. -//#define BOARD_AT45_A_SPI_ID ID_SPI0 -///// Pins of the SPI peripheral connected to the dataflash. -//#define BOARD_AT45_A_SPI_PINS PINS_SPI0 -///// Dataflahs SPI number. -//#define BOARD_AT45_A_SPI 0 -///// Chip select connected to the dataflash. -//#define BOARD_AT45_A_NPCS 3 -///// Chip select pin connected to the dataflash. -//#define BOARD_AT45_A_NPCS_PIN PIN_SPI0_NPCS3 - -/// Base address of SPI peripheral connected to the dataflash. -//#define BOARD_AT45_B_SPI_BASE SPI1 -///// Identifier of SPI peripheral connected to the dataflash. -//#define BOARD_AT45_B_SPI_ID ID_SPI1 -///// Pins of the SPI peripheral connected to the dataflash. -//#define BOARD_AT45_B_SPI_PINS PINS_SPI1 -///// Dataflahs SPI number. -//#define BOARD_AT45_B_SPI 1 -///// Chip select connected to the dataflash. -//#define BOARD_AT45_B_NPCS 3 -///// Chip select pin connected to the dataflash. -//#define BOARD_AT45_B_NPCS_PIN PIN_SPI1_NPCS3 - -/// Base address of SPI peripheral connected to the serialflash. -//#define BOARD_AT26_A_SPI_BASE SPI0 -///// Identifier of SPI peripheral connected to the serialflash. -//#define BOARD_AT26_A_SPI_ID ID_SPI0 -///// Pins of the SPI peripheral connected to the serialflash. -//#define BOARD_AT26_A_SPI_PINS PINS_SPI0 -///// Serialflash SPI number. -//#define BOARD_AT26_A_SPI 0 -///// Chip select connected to the serialflash. -//#define BOARD_AT26_A_NPCS 3 -///// Chip select pin connected to the serialflash. -//#define BOARD_AT26_A_NPCS_PIN PIN_SPI0_NPCS3 - -/// ISO7816 -/// - PIN_SMARTCARD_CONNECT -/// - PIN_ISO7816_RSTMC -/// - PINS_ISO7816 - -/// Smartcard detection pin -//#define PIN_SMARTCARD_CONNECT {1 << 5, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT} -/// PIN used for reset the smartcard -//#define PIN_ISO7816_RSTMC {1 << 7, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT} -/// Pins used for connect the smartcard -//#define PINS_ISO7816 PIN_USART0_TXD, PIN_USART0_SCK, PIN_ISO7816_RSTMC - -/// Dma channel number -#define BOARD_MCI_DMA_CHANNEL 0 -/// MCI0 DMA hardware handshaking ID -#define DMA_HW_SRC_REQ_ID_MCI0 AT91C_HDMA_SRC_PER_0 -#define DMA_HW_DEST_REQ_ID_MCI0 AT91C_HDMA_DST_PER_0 -/// MCI1 DMA hardware handshaking ID -#define DMA_HW_SRC_REQ_ID_MCI1 AT91C_HDMA_SRC_PER_13 -#define DMA_HW_DEST_REQ_ID_MCI1 AT91C_HDMA_DST_PER_13 -/// SD DMA hardware handshaking ID -#define BOARD_SD_DMA_HW_SRC_REQ_ID DMA_HW_SRC_REQ_ID_MCI0 -#define BOARD_SD_DMA_HW_DEST_REQ_ID DMA_HW_DEST_REQ_ID_MCI0 - - -/// HS MCI interface -#define MCI2_INTERFACE -/// Base address of the MCI peripheral connected to the SD card. -#define BOARD_SD_MCI_BASE MCI0//MCI -///// Peripheral identifier of the MCI connected to the SD card. -#define BOARD_SD_MCI_ID ID_MCI0 //ID_MCI -///// MCI pins that shall be configured to access the SD card. -#define BOARD_SD_PINS PINS_MCI -///// MCI slot to which the SD card is connected to. -#define BOARD_SD_SLOT MCI_SD_SLOTA -///// MCI Card Detect pin. -#define BOARD_SD_PIN_CD PIN_MCI_CD - -/* -#define BOARD_PSRAM_PINS PIN_EBI_DATA_BUS, PIN_EBI_NCS0, PIN_EBI_NRD, PIN_EBI_NWE, \ - PIN_EBI_PSRAM_ADDR_BUS, PIN_EBI_PSRAM_NBS, PIN_EBI_A1 -*/ - -/** Indicates board has an ILI9325 external component to manage LCD. */ -#define BOARD_LCD_ILI9325 - -/** LCD pins definition. */ -#define BOARD_LCD_PINS PIN_EBI_DATA_BUS, PIN_EBI_NRD, PIN_EBI_NWE, \ - PIN_EBI_NCS1, PIN_EBI_LCD_RS -/** Backlight pin definition. */ -#define BOARD_BACKLIGHT_PIN {1 << 13, PIOC, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT} -/** Define ILI9325 base address. */ -#define BOARD_LCD_BASE 0x61000000 -/** Define ILI9325 register select signal. */ -#define BOARD_LCD_RS (1 << 1) -/** Display width in pixels. */ -#define BOARD_LCD_WIDTH 240 -/** Display height in pixels. */ -#define BOARD_LCD_HEIGHT 320 - -/** Indicates board has an ADS7843 external component to manage Touch Screen */ -#define BOARD_TSC_ADS7843 - -#ifdef BOARD_REV_A -/** Touchscreen controller IRQ pin definition. */ -#define PIN_TCS_IRQ {PIO_PA4, PIOA, ID_PIOA, PIO_INPUT, PIO_DEBOUNCE | PIO_IT_AIME | PIO_IT_EDGE} -#define PIN_TCS_IRQ_WUP_ID (1 << 3) -/** Touchscreen controller Busy pin definition. */ -#define PIN_TCS_BUSY {PIO_PA5, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP} -#endif -#ifdef BOARD_REV_B -/** Touchscreen controller IRQ pin definition. */ -#define PIN_TCS_IRQ {PIO_PA16, PIOA, ID_PIOA, PIO_INPUT, PIO_DEBOUNCE | PIO_IT_AIME | PIO_IT_EDGE} -#define PIN_TCS_IRQ_WUP_ID (1 << 15) -/** Touchscreen controller Busy pin definition. */ -#define PIN_TCS_BUSY {PIO_PA17, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP} -#endif - -/** Base address of SPI peripheral connected to the touchscreen controller. */ -#define BOARD_TSC_SPI_BASE SPI -/** Identifier of SPI peripheral connected to the touchscreen controller. */ -#define BOARD_TSC_SPI_ID ID_SPI -/** Pins of the SPI peripheral connected to the touchscreen controller. */ -#define BOARD_TSC_SPI_PINS PINS_SPI -/** Chip select connected to the touchscreen controller. */ -#define BOARD_TSC_NPCS 0 -/** Chip select pin connected to the touchscreen controller. */ -#define BOARD_TSC_NPCS_PIN PIN_SPI_NPCS0_PA11 - -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \par sam3s_ek_mem "SAM3S-EK - Memories" -/// This page lists definitions related to internal & external on-board memories. -/// -/// !Embedded Flash -/// - BOARD_FLASH_EFC - -/// Internal SRAM address -#define AT91C_ISRAM AT91C_IRAM -#define AT91C_ISRAM_SIZE 0x00008000 - -#define AT91C_IFLASH_SIZE (0x40000) -#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH 0 Page Size: 256 bytes -#define AT91C_IFLASH_NB_OF_PAGES (1024) // Internal FLASH 0 Number of Pages: 512 -#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH 0 Lock Region Size: 16 Kbytes -#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH 0 Number of Lock Bits: 16 - -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -/// \section sam3s_ek_extcomp "SAM3S-EK - External components" -/// This page lists the definitions related to external on-board components -/// located in the board.h file for the SAM3S-EK. -/// -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \par sam3s_ek_chipdef "SAM3S-EK - Individual chip definition" -/// This page lists the definitions related to different chip's definition -/// located in the board.h file for the SAM3S-EK. - -/// DBGU -#define BOARD_DBGU_ID ID_DBGU - -/// Rtc -#define BOARD_RTC_ID ID_RTC - -/// Twi eeprom -#define BOARD_ID_TWI_EEPROM ID_TWI1 -#define BOARD_BASE_TWI_EEPROM TWI1 -#define BOARD_PINS_TWI_EEPROM PINS_TWI1 - -/// USART -#define BOARD_PIN_USART_RXD PIN_USART1_RXD -#define BOARD_PIN_USART_TXD PIN_USART1_TXD -#define BOARD_PIN_USART_CTS PIN_USART1_CTS -#define BOARD_PIN_USART_RTS PIN_USART1_RTS -#define BOARD_PIN_USART_EN PIN_USART1_EN -#define BOARD_USART_BASE USART1 -#define BOARD_ID_USART ID_USART1 - -//------------------------------------------------------------------------------ - - -#define PIN_EBI_NANDOE {1 << 9, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_NANDWE {1 << 10, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_NANDCLE {1 << 17, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_NANDALE {1 << 16, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_NANDIO {0x000000FF, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} - -/// Nandflash chip enable pin definition. -#define BOARD_NF_CE_PIN {1 << 14, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} -/// Nandflash ready/busy pin definition. -#define BOARD_NF_RB_PIN {1 << 18, PIOC, ID_PIOC, PIO_INPUT, PIO_PULLUP} - -/// Nandflash controller peripheral pins definition. -#define PINS_NANDFLASH PIN_EBI_NANDIO, BOARD_NF_CE_PIN, BOARD_NF_RB_PIN, PIN_EBI_NANDOE, \ - PIN_EBI_NANDWE, PIN_EBI_NANDCLE, PIN_EBI_NANDALE - -/// Address for transferring command bytes to the nandflash. -#define BOARD_NF_COMMAND_ADDR 0x60400000 -/// Address for transferring address bytes to the nandflash. -#define BOARD_NF_ADDRESS_ADDR 0x60200000 -/// Address for transferring data bytes to the nandflash. -#define BOARD_NF_DATA_ADDR 0x60000000 - -extern uint32_t Cmd_A41_resp ; - -#define OCR_SD_CCS (1UL << 30) - -#define SD_CSD(csd, bitfield, bits) ((csd[3-(bitfield)/32] >> ((bitfield)%32)) & ((1 << (bits)) - 1)) - -#define SD_CSD_C_SIZE(pSd) ((SD_CSD(pSd, 72, 2) << 10) + \ - (SD_CSD(pSd, 64, 8) << 2) + \ - SD_CSD(pSd, 62, 2)) ///< Device size - -#define SD_CSD_C_SIZE_HC(csd) ((SD_CSD(csd, 64, 6) << 16) + \ - (SD_CSD(csd, 56, 8) << 8) + \ - SD_CSD(csd, 48, 8)) ///< Device size v2.0 High Capacity - -#define SD_CSD_C_SIZE_MULT(pSd) SD_CSD(pSd, 47, 3) ///< Device size multiplier - -#define SD_CSD_MULT(pSd) (1 << (SD_CSD_C_SIZE_MULT(pSd) + 2)) - -#define SD_CSD_BLKLEN(pSd) (1 << ( SD_CSD(pSd, 80, 4) - 9 ) ) - -#define SD_CSD_BLOCKNR(pSd) ((SD_CSD_C_SIZE(pSd) + 1) * SD_CSD_MULT(pSd)) * SD_CSD_BLKLEN(pSd) - -#define SD_CSD_BLOCKNR_HC(pSd) ((SD_CSD_C_SIZE_HC(pSd) + 1) * 1024) - -#if !defined(SIMU) -#define SD_IS_HC() (Cmd_A41_resp & OCR_SD_CCS) -#define SD_GET_BLOCKNR() (SD_IS_HC() ? (SD_CSD_BLOCKNR_HC(Card_CSD)) : (SD_CSD_BLOCKNR(Card_CSD))) - -#define SD_GET_SPEED() (transSpeed) - -#define SD_GET_SIZE_MB() (SD_GET_BLOCKNR() / 2048) -#endif - -#endif //#ifndef BOARD_H - diff --git a/radio/bootloader/include/chip.h b/radio/bootloader/include/chip.h deleted file mode 100644 index 8b6984086..000000000 --- a/radio/bootloader/include/chip.h +++ /dev/null @@ -1,130 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Definition of AT91SAM3S4 characteristics and features -/// -/// !Usage -/// -# For ARM core feature, see "AT91SAM3S4 - ARM core features". -/// -# For IP features, see "AT91SAM3S4 - IP features". -/// -# For misc, see "AT91SAM3S4 - Misc". -//------------------------------------------------------------------------------ - -#ifndef CHIP_H -#define CHIP_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "AT91SAM3S4 - ARM core features" -/// This page lists several characteristics related to the ARM core -/// - -//ARM core features - -/// ARM core definition. -#define cortexm3 - -/// family definition. -#define at91sam3s - -//------------------------------------------------------------------------------ -/// \page "AT91SAM3S4 - IP features" -/// This page lists several characteristics related to the embedded IP -/// - -//IP FEATURES - -// EFC GPNVM number -#define CHIP_EFC_NUM_GPNVMS 3 - -/// Indicates chip has an Enhanced EFC. -#define CHIP_FLASH_EEFC - -// DMA channels number -#define CHIP_DMA_CHANNEL_NUM 4 - -// Indicate chip's MCI interface. -#define MCI2_INTERFACE - -// Indicate chip SSC has DMA interface. -#define CHIP_SSC_DMA - -// Indicate chip SPI has DMA interface. -#define CHIP_SPI_DMA - -/// Indicates chip has an UDP Full Speed. -#define CHIP_USB_UDP - -/// Indicates chip has an internal pull-up. -#define CHIP_USB_PULLUP_INTERNAL - -/// Number of USB endpoints -#define CHIP_USB_NUMENDPOINTS 8 - -/// Endpoints max paxcket size -#define CHIP_USB_ENDPOINTS_MAXPACKETSIZE(i) \ - ((i == 0) ? 64 : \ - ((i == 1) ? 64 : \ - ((i == 2) ? 64 : \ - ((i == 3) ? 64 : \ - ((i == 4) ? 512 : \ - ((i == 5) ? 512 : \ - ((i == 6) ? 64 : \ - ((i == 7) ? 64 : 0 )))))))) - -/// Endpoints Number of Bank -#define CHIP_USB_ENDPOINTS_BANKS(i) \ - ((i == 0) ? 1 : \ - ((i == 1) ? 2 : \ - ((i == 2) ? 2 : \ - ((i == 3) ? 1 : \ - ((i == 4) ? 2 : \ - ((i == 5) ? 2 : \ - ((i == 6) ? 2 : \ - ((i == 7) ? 2 : 0 )))))))) - -//------------------------------------------------------------------------------ -/// \page "AT91SAM3S4 - Misc " -/// This page lists misc features -/// - -//Misc - -#endif //#ifndef CHIP_H - From 3b1ac9f5d8bec985c772080ba5333e248b69b0f8 Mon Sep 17 00:00:00 2001 From: bsongis Date: Wed, 5 Mar 2014 11:58:40 +0100 Subject: [PATCH 040/285] 4 more files removed --- radio/bootloader/include/debug.h | 25 - radio/bootloader/include/ersky9x.h | 758 ----------------------------- radio/bootloader/include/file.h | 116 ----- radio/bootloader/include/rtc.h | 71 --- 4 files changed, 970 deletions(-) delete mode 100644 radio/bootloader/include/debug.h delete mode 100644 radio/bootloader/include/ersky9x.h delete mode 100644 radio/bootloader/include/file.h delete mode 100644 radio/bootloader/include/rtc.h diff --git a/radio/bootloader/include/debug.h b/radio/bootloader/include/debug.h deleted file mode 100644 index 57fb289cb..000000000 --- a/radio/bootloader/include/debug.h +++ /dev/null @@ -1,25 +0,0 @@ -#include - -#define TRACE_DEBUG(...) { } -#define TRACE_DEBUG_WP(...) { } -#define TRACE_INFO(...) { } -#define TRACE_INFO_WP(...) { } -#define TRACE_WARNING(...) { } -#define TRACE_WARNING_WP(...) { } -#define TRACE_ERROR(...) { } - -extern void handle_serial( void* pdata ) ; -//extern uint32_t read_switch( enum EnumKeys enuk ) ; -extern void txmit( uint8_t c ) ; -//extern void disp_mem( register uint32_t address ) ; -//extern void disp_256( uint32_t address, uint32_t lines ) ; -#ifdef __cplusplus -extern "C" void utxmit( uint8_t c ) ; -extern "C" void up8hex( uint32_t value ) ; -#else -extern void utxmit( uint8_t c ) ; -extern void up8hex( uint32_t value ) ; -#endif - - - diff --git a/radio/bootloader/include/ersky9x.h b/radio/bootloader/include/ersky9x.h deleted file mode 100644 index e0e0b8640..000000000 --- a/radio/bootloader/include/ersky9x.h +++ /dev/null @@ -1,758 +0,0 @@ -/* - * Author - Mike Blandford - * - * Based on er9x by Erez Raviv - * - * Based on th9x -> http://code.google.com/p/th9x/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -// This version for ARM based ERSKY9X board - -#ifndef ersky9x_h -#define ersky9x_h - -#include - -#define FIX_MODE 1 - -#ifdef SIMU -#include "simpgmspace.h" -#else -// Items set to make things compile, will need to be sorted eventually -#define assert(x) -#ifdef PCBSKY -#define wdt_reset() (WDT->WDT_CR = 0xA5000001) -#endif -#ifdef PCBTARANIS -#define wdt_reset() (IWDG->KR = 0x0000AAAAL) -#endif -#endif - -#define VERSION "V0.26" - -#define GVARS 1 - -//#define DATE_STR "xx.xx.2012" -//#define TIME_STR "xx:xx:xx" -//#define SUB_VERS VERSION -//#define SVN_VERS "trunk-rxxx" -//#define MOD_VERS "Normal" - -//#define STR2(s) #s -//#define DEFNUMSTR(s) STR2(s) - -extern const char stamp1[] ; -extern const char stamp2[] ; -extern const char stamp3[] ; -extern const char stamp4[] ; -extern const char stamp5[] ; - -//extern const char *Str_OFF ; -//extern const char *Str_ON ; -//extern const char *Str_Switches ; -//extern const char *Str_Switch_warn ; - -#define CPU_INT int32_t -#define CPU_UINT uint32_t - -#define BITMASK(bit) (1<<(bit)) - -extern const char * const *Language ; -extern const char * const English[] ; -extern const char * const French[] ; -extern const char * const German[] ; -extern const char * const Norwegian[] ; -extern const char * const Swedish[] ; - -#define PSTR(a) Language[a] -#define XPSTR(a) (char *)a - -#define PROGMEM const unsigned char -#define strcpy_P(a,b) strcpy(a,b) -#define strncpy_P(a,b,c) strncpy(a,b,c) -#define pgm_read_byte(p) (*(p)) - - -#ifdef PCBTARANIS - #define NUMBER_ANALOG 9 -#else -#ifdef REVX -#define NUMBER_ANALOG 10 -#define CURRENT_ANALOG 8 -#else - #ifdef REVB - #define NUMBER_ANALOG 9 - #define CURRENT_ANALOG 8 - #else - #define NUMBER_ANALOG 8 - #endif -#endif -#endif - -#define DIM(arr) (sizeof((arr))/sizeof((arr)[0])) - -enum EnumKeys { - KEY_MENU , - KEY_EXIT , - KEY_DOWN , - KEY_UP , - KEY_RIGHT , - KEY_LEFT , - TRM_LH_DWN , - TRM_LH_UP , - TRM_LV_DWN , - TRM_LV_UP , - TRM_RV_DWN , - TRM_RV_UP , - TRM_RH_DWN , - TRM_RH_UP , - BTN_RE, - -#ifdef PCBSKY - //SW_NC , - //SW_ON , - SW_ThrCt , - SW_RuddDR , - SW_ElevDR , - SW_ID0 , - SW_ID1 , - SW_ID2 , - SW_AileDR , - SW_Gear , - SW_Trainer -#endif - -#ifdef PCBTARANIS - SW_SA0, - SW_SA1, - SW_SA2, - SW_SB0, - SW_SB1, - SW_SB2, - SW_SC0, - SW_SC1, - SW_SC2, - SW_SD0, - SW_SD1, - SW_SD2, - SW_SE0, - SW_SE1, - SW_SE2, - SW_SF0, - SW_SF2, - SW_SG0, - SW_SG1, - SW_SG2, - SW_SH0, - SW_SH2 -#endif -}; - -// c17-c24 added for timer mode A display -//#define CURV_STR "\003---x>0x<0|x|f>0f<0|f|c1 c2 c3 c4 c5 c6 c7 c8 c9 c10c11c12c13c14c15c16c17c18c19c20c21c22c23c24" -#define CURVE_BASE 7 - -//#define CSWITCH_STR "---- v>ofs vofs|v|v2 ""v1=v2 ""v1<=v2 TimeOff" -#define CSW_LEN_FUNC 7 - - -#define CS_OFF 0 -#define CS_VPOS 1 //v>offset -#define CS_VNEG 2 //voffset -#define CS_ANEG 4 //|v| inline t min(t a, t b){ return a inline t max(t a, t b){ return a>b?a:b; } -template inline t limit(t mi, t x, t ma){ return min(max(mi,x),ma); } - -// This doesn't need protection on this processor -#define get_tmr10ms() g_tmr10ms - -#define sysFLAG_OLD_EEPROM (0x01) -extern uint8_t sysFlags; -extern uint8_t StickScrollAllowed ; - -const char s_charTab[]=" ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789_-."; -#define NUMCHARS (sizeof(s_charTab)-1) - -///number of real input channels (1-9) plus virtual input channels X1-X4 -#define PPM_BASE MIX_CYC3 -#define CHOUT_BASE (PPM_BASE+NUM_PPM) - -//extern const char *Str_telemItems ; -extern const int8_t TelemIndex[] ; -extern int16_t convertTelemConstant( int8_t channel, int8_t value) ; -#define NUM_TELEM_ITEMS 35 - -#define NUM_XCHNRAW (CHOUT_BASE+NUM_CHNOUT) // NUMCH + P1P2P3+ AIL/RUD/ELE/THR + MAX/FULL + CYC1/CYC2/CYC3 -#define NUM_SKYXCHNRAW (CHOUT_BASE+NUM_SKYCHNOUT) // NUMCH + P1P2P3+ AIL/RUD/ELE/THR + MAX/FULL + CYC1/CYC2/CYC3 -///number of real output channels (CH1-CH8) plus virtual output channels X1-X4 -#define NUM_XCHNOUT (NUM_CHNOUT) //(NUM_CHNOUT)//+NUM_VIRT) -#define NUM_SKYXCHNOUT (NUM_SKYCHNOUT) //(NUM_CHNOUT)//+NUM_VIRT) - -#define MIX_3POS (NUM_SKYXCHNRAW+1) - -inline int32_t calc100toRESX(register int8_t x) -{ - return ((uint32_t)x*655)>>6 ; -} - -inline int16_t calc1000toRESX( register int32_t x) // improve calc time by Pat MacKenzie -{ - register int32_t y = x>>5; - x+=y; - y=y>>2; - x-=y; - return x+(y>>2); - // return x + x/32 - x/128 + x/512; -} - -extern uint32_t Current_used ; -extern uint16_t Current_max ; -extern uint16_t MAh_used ; -extern uint16_t Run_time ; - -#ifdef FIX_MODE -extern const char stickScramble[] ; -//extern const char modeFix[] ; -uint8_t modeFixValue( uint8_t value ) ; -#else -extern const char modn12x3[] ; -#endif - -extern const uint8_t bchout_ar[] ; - -//convert from mode 1 to mode g_eeGeneral.stickMode -//NOTICE! => 1..4 -> 1..4 -extern uint8_t convert_mode_helper(uint8_t x) ; - -#define CONVERT_MODE(x) (((x)<=4) ? convert_mode_helper(x) : (x)) -//#define CHANNEL_ORDER(x) (chout_ar[g_eeGeneral.templateSetup*4 + (x)-1]) -#define CHANNEL_ORDER(x) ( ( (bchout_ar[g_eeGeneral.templateSetup] >> (6-(x-1) * 2)) & 3 ) + 1 ) -#define THR_STICK (2-(g_eeGeneral.stickMode&1)) -#define ELE_STICK (1+(g_eeGeneral.stickMode&1)) -#define AIL_STICK ((g_eeGeneral.stickMode&2) ? 0 : 3) -#define RUD_STICK ((g_eeGeneral.stickMode&2) ? 3 : 0) - -#define STORE_MODELVARS_TRIM eeDirty(EE_MODEL|EE_TRIM) -#define STORE_MODELVARS eeDirty(EE_MODEL) -#define STORE_GENERALVARS eeDirty(EE_GENERAL) - -#ifdef PCBSKY -#define BACKLIGHT_ON (PWM->PWM_CH_NUM[0].PWM_CDTY = g_eeGeneral.bright) -#define BACKLIGHT_OFF (PWM->PWM_CH_NUM[0].PWM_CDTY = 100) -#endif - -#ifdef PCBTARANIS -extern void backlight_on( void ) ; -extern void backlight_off( void ) ; -#define BACKLIGHT_ON backlight_on() -#define BACKLIGHT_OFF backlight_off() -#endif - -// Options for mainSequence() -#define NO_MENU 1 -#define MENUS 0 - -extern uint16_t evalChkSum( void ) ; - -struct t_calib -{ - int16_t midVals[8]; - int16_t loVals[8]; - int16_t hiVals[8]; - uint8_t idxState; -} ; - -union t_xmem -{ -// struct MixTab s_mixTab[MAX_MIXERS+NUM_XCHNOUT+1] ; - struct t_calib Cal_data ; -#ifndef CPUARM - char buf[sizeof(g_model.name)+5]; -#endif -//#if defined(CPUM128) || defined(CPUM2561) -// uint8_t file_buffer[256]; -//#else -// uint8_t file_buffer[128]; -//#endif -} ; - -extern union t_xmem Xmem ; - - -typedef void (*MenuFuncP)(uint8_t event); - -typedef struct -{ - unsigned char second; //enter the current time, date, month, and year - unsigned char minute; - unsigned char hour; - unsigned char date; - unsigned char month; - unsigned int year; - } t_time ; - -extern t_time Time ; - -extern bool checkIncDec_Ret;//global helper vars -extern uint8_t s_editMode; //global editmode - -int16_t checkIncDec16(uint8_t event, int16_t i_pval, int16_t i_min, int16_t i_max, uint8_t i_flags); -int8_t checkIncDec(uint8_t event, int8_t i_val, int8_t i_min, int8_t i_max, uint8_t i_flags); -int8_t checkIncDec_hm(uint8_t event, int8_t i_val, int8_t i_min, int8_t i_max); -int8_t checkIncDec_vm(uint8_t event, int8_t i_val, int8_t i_min, int8_t i_max); -int8_t checkIncDec_hg(uint8_t event, int8_t i_val, int8_t i_min, int8_t i_max); - -#define CHECK_INCDEC_H_GENVAR( event, var, min, max) \ - var = checkIncDec_hg(event,var,min,max) - -#define CHECK_INCDEC_H_MODELVAR( event, var, min, max) \ - var = checkIncDec_hm(event,var,min,max) - -#define CHECK_INCDEC_MODELSWITCH(event, var, min, max) \ - var = checkIncDec(event,var,min,max,EE_MODEL|INCDEC_SWITCH) - -#define CHECK_INCDEC_GENERALSWITCH( event, var, min, max) \ - var = checkIncDec(event,var,min,max,EE_GENERAL|INCDEC_SWITCH) - - -extern uint8_t heartbeat ; -extern int16_t g_chans512[NUM_SKYCHNOUT]; -//extern uint8_t eeprom[4096] ; - -uint8_t char2idx(char c); -char idx2char(uint8_t idx); - -//extern volatile uint32_t Timer2_count ; // Modified in interrupt routine -extern volatile uint16_t g_tmr10ms ; -extern volatile uint8_t g_blinkTmr10ms; -extern volatile uint8_t tick10ms ; -extern uint32_t Master_frequency ; - -extern void alert(const char * s, bool defaults=false); -extern void message(const char * s); - -void resetTimer(); - - -//extern uint8_t Timer2_running ; -//extern uint16_t Timer2 ; -//void resetTimer2( void ) ; - -extern void putsTime(uint8_t x,uint8_t y,int16_t tme,uint8_t att,uint8_t att2) ; -extern void putsVolts(uint8_t x,uint8_t y, uint8_t volts, uint8_t att) ; -extern void putsVBat(uint8_t x,uint8_t y,uint8_t att) ; -extern void putsVBat(uint8_t x,uint8_t y,uint8_t att) ; -extern void putsChnRaw(uint8_t x,uint8_t y,uint8_t idx,uint8_t att) ; -extern void putsChn(uint8_t x,uint8_t y,uint8_t idx1,uint8_t att) ; -extern void putsDrSwitches(uint8_t x,uint8_t y,int8_t idx1,uint8_t att) ; //, bool nc) ; -extern void putsTmrMode(uint8_t x, uint8_t y, uint8_t attr, uint8_t timer, uint8_t type ) ; -extern const char *get_switches_string( void ) ; - -extern void interrupt5ms() ; - - -extern int16_t intpol(int16_t x, uint8_t idx); - -extern uint16_t anaIn(uint8_t chan) ; - -extern int8_t phyStick[4] ; -extern int16_t ex_chans[NUM_SKYCHNOUT]; - -extern void modelDefault( uint8_t id ) ; -extern uint8_t VoiceCheckFlag ; - -//void eeWaitComplete( void ) ; -void eeDirty(uint8_t msk); -//void eeCheck(bool immediately=false ) ; -void eeReadAll( void ) ; -//void eeLoadModelName(uint8_t id,char*buf,uint8_t len); -//uint16_t eeFileSize(uint8_t id); -//void eeLoadModel(uint8_t id); -//void eeSaveModel(uint8_t id); -bool eeDuplicateModel(uint8_t id); -//bool eeModelExists(uint8_t id); - -extern char idx2char(uint8_t idx) ; -extern uint8_t char2idx(char c) ; - -extern int16_t g_ppmIns[]; -extern uint8_t ppmInState ; //0=unsync 1..8= wait for value i-1 -extern uint8_t ppmInValid ; - -/// goto given Menu, but substitute current menu in menuStack -extern void chainMenu(MenuFuncP newMenu); -/// goto given Menu, store current menu in menuStack -extern void pushMenu(MenuFuncP newMenu); -///deliver address of last menu which was popped from -extern MenuFuncP lastPopMenu(); -/// return to last menu in menustack -/// if uppermost is set true, thenmenu return to uppermost menu in menustack -void popMenu(bool uppermost=false); - -#define NO_TRAINER 0x01 -#define NO_INPUT 0x02 - -// Timeout, in seconds, stick scroll remains active -#define STICK_SCROLL_TIMEOUT 5 - -extern bool getSwitch(int8_t swtch, bool nc, uint8_t level = 0 ) ; -extern int8_t getMovedSwitch( void ) ; -extern uint8_t g_vbat100mV ; -//extern uint16_t Timer2 ; -extern void doSplash( void ) ; -extern void mainSequence( uint32_t no_menu ) ; -#ifdef FRSKY -extern uint8_t putsTelemValue(uint8_t x, uint8_t y, uint8_t val, uint8_t channel, uint8_t att, uint8_t scale) ; -extern void telem_byte_to_bt( uint8_t data ) ; -extern uint16_t scale_telem_value( uint16_t val, uint8_t channel, uint8_t times2, uint8_t *p_att ) ; -#endif -uint8_t telemItemValid( uint8_t index ) ; - -extern int16_t get_telemetry_value( int8_t channel ) ; - -extern void putVoiceQueue( uint16_t value ) ; -void voice_numeric( int16_t value, uint8_t num_decimals, uint8_t units_index ) ; -extern void voice_telem_item( int8_t index ) ; -extern uint8_t *cpystr( uint8_t *dest, uint8_t *source ) ; -extern int16_t m_to_ft( int16_t metres ) ; - -uint8_t getCurrentSwitchStates( void ) ; - -extern uint32_t check_soft_power( void ) ; -extern uint32_t getFlightPhase( void ) ; -extern int16_t getRawTrimValue( uint8_t phase, uint8_t idx ) ; -extern int16_t getTrimValue( uint8_t phase, uint8_t idx ) ; -extern void setTrimValue(uint8_t phase, uint8_t idx, int16_t trim) ; - -extern void checkSwitches( void ) ; -extern void setLanguage( void ) ; - -struct t_timer -{ - uint16_t s_sum ; - uint8_t lastSwPos ; - uint8_t sw_toggled ; - uint16_t s_timeCumSw ; //laufzeit in 1/16 sec - uint8_t s_timerState ; - uint16_t s_timeCumThr ; //gewichtete laufzeit in 1/16 sec - uint16_t s_timeCum16ThrP ; //gewichtete laufzeit in 1/16 sec - int16_t s_timerVal ; -} ; - -extern struct t_timer s_timer[] ; - -// Rotary encoder movement states -#define ROTARY_MENU_LR 0 -#define ROTARY_MENU_UD 1 -#define ROTARY_SUBMENU_LR 2 -#define ROTARY_VALUE 3 - -extern uint8_t RotaryState ; // Defaults to ROTARY_MENU_LR - -#if GVARS -extern int8_t REG(int8_t x, int8_t min, int8_t max) ; -#endif - -enum PowerState -{ - e_power_on, - e_power_trainer, - e_power_usb, - e_power_off -} ; - -struct t_p1 -{ - int16_t p1val ; - int16_t p1valdiff ; - int16_t p1valprev ; - int16_t p2valprev ; - int16_t p3valprev ; -} ; - -extern struct t_p1 P1values ; - -#ifdef PCBSKY -extern uint16_t ResetReason ; -#endif -#ifdef PCBTARANIS -extern uint32_t ResetReason ; -#endif -extern uint8_t unexpectedShutdown ; -extern uint8_t SdMounted ; - -#ifdef PCBTARANIS -#include "stm32f2xx.h" -#include "rtc.h" -#include "stm32f2xx_rtc.h" -void rtcSetTime( t_time *t ) ; -void rtc_gettime( t_time *t ) ; -void rtcInit( void ) ; -#endif - -extern void setVolume( uint8_t value ) ; -extern uint8_t HoldVolume ; - -#ifdef PCBTARANIS -#define INTERNAL_MODULE 0 -#define EXTERNAL_MODULE 1 -#define TRAINER_MODULE 2 -#endif - -#endif diff --git a/radio/bootloader/include/file.h b/radio/bootloader/include/file.h deleted file mode 100644 index f72d8f47b..000000000 --- a/radio/bootloader/include/file.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Author - Erez Raviv - * - * Based on th9x -> http://code.google.com/p/th9x/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#ifndef file_h -#define file_h - -#include -#include - - -extern void init_eeprom( void ) ; - -extern uint32_t ee32_check_finished( void ) ; -extern void ee32StoreGeneral( void ) ; -extern void ee32StoreModel( uint8_t modelNumber, uint8_t trim ) ; -extern bool ee32LoadGeneral( void ) ; -extern void ee32LoadModel(uint8_t id) ; -extern void ee32WaitLoadModel(uint8_t id) ; -extern void ee32_delete_model( uint8_t id ) ; -extern bool ee32ModelExists(uint8_t id) ; -extern void ee32_process( void ) ; -extern bool ee32CopyModel( uint8_t dst, uint8_t src ) ; -extern void ee32SwapModels( uint8_t id1, uint8_t id2 ) ; -extern uint32_t ee32_read_512( uint32_t sector, uint8_t *buffer ) ; - - -struct t_file_entry -{ - uint32_t block_no ; - uint32_t sequence_no ; - uint16_t size ; - uint8_t flags ; -} ; - -extern struct t_file_entry File_system[] ; -//extern unsigned char ModelNames[][sizeof(g_model.name)+1] ; // Allow for general - -//extern EEGeneral g_eeGeneral; -//extern ModelData g_model; - -extern uint8_t Spi_tx_buf[] ; -extern uint8_t Spi_rx_buf[] ; - -/// fileId of general file -//#define FILE_GENERAL 0 -/// convert model number 0..MAX_MODELS-1 int fileId -//#define FILE_MODEL(n) (1+n) -//#define FILE_TMP (1+16) - -//bool EeFsOpen(); -//int8_t EeFsck(); -//void EeFsFormat(); -//uint16_t EeFsGetFree(); -//#define ERR_NONE 0 -//#define ERR_FULL 1 -//#define ERR_TMO 2 -//class EFile -//{ -// uint8_t m_fileId; //index of file in directory = filename -// uint16_t m_pos; //over all filepos -// uint8_t m_currBlk; //current block.id -// uint8_t m_ofs; //offset inside of the current block -// uint8_t m_bRlc; //control byte for run length decoder -// uint8_t m_err; //error reasons -// uint16_t m_stopTime10ms; //maximum point of time for writing -//public: - ///remove contents of given file -// static void rm(uint8_t i_fileId); - - ///swap contents of file1 with them of file2 -// static void swap(uint8_t i_fileId1,uint8_t i_fileId2); - - ///return true if the file with given fileid exists -// static bool exists(uint8_t i_fileId); - - ///open file for reading, no close necessary - ///for writing use writeRlc() or create() -// uint8_t openRd(uint8_t i_fileId); - /// create a new file with given fileId, - /// !!! if this file already exists, then all blocks are reused - /// and all contents will be overwritten. - /// after writing closeTrunc has to be called -// void create(uint8_t i_fileId, uint8_t typ, uint16_t maxTme10ms); - /// close file and truncate the blockchain if to long. -// void closeTrunc(); - - ///open file, write to file and close it. - ///If file existed before, then contents is overwritten. - ///If file was larger before, then unused blocks are freed -// uint16_t writeRlc(uint8_t i_fileId, uint8_t typ,uint8_t*buf,uint16_t i_len, uint8_t maxTme10ms); - -// uint8_t read(uint8_t*buf,uint16_t i_len); -// uint8_t write(uint8_t*buf,uint8_t i_len); - - ///return size of compressed file without block overhead -// uint16_t size(); - ///read from opened file and decode rlc-coded data -// uint16_t readRlc(uint8_t*buf,uint16_t i_len); - ///deliver current errno, this is reset in open -// uint8_t errno(){return m_err;} -//}; - -#endif -/*eof*/ diff --git a/radio/bootloader/include/rtc.h b/radio/bootloader/include/rtc.h deleted file mode 100644 index 42557e411..000000000 --- a/radio/bootloader/include/rtc.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Authors (alphabetical order) - * - Andre Bernet - * - Andreas Weitl - * - Bertrand Songis - * - Bryan J. Rentoul (Gruvin) - * - Cameron Weeks - * - Erez Raviv - * - Gabriel Birkus - * - Jean-Pierre Parisy - * - Karl Szmutny - * - Michael Blandford - * - Michal Hlavinka - * - Pat Mackenzie - * - Philip Moss - * - Rob Thomson - * - Romolo Manfredini - * - Thomas Husterer - * - * opentx is based on code named - * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, - * er9x by Erez Raviv: http://code.google.com/p/er9x/, - * and the original (and ongoing) project by - * Thomas Husterer, th9x: http://code.google.com/p/th9x/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef RTC_H -#define RTC_H - -#include - -typedef long int gtime_t; - -struct gtm -{ - int8_t tm_sec; /* Seconds. [0-60] (1 leap second) */ - int8_t tm_min; /* Minutes. [0-59] */ - int8_t tm_hour; /* Hours. [0-23] */ - int8_t tm_mday; /* Day. [1-31] */ - int8_t tm_mon; /* Month. [0-11] */ - int8_t tm_year; /* Year - 1900. Limited to the year 2115. Oh no! :P */ - int8_t tm_wday; /* Day of week. [0-6] */ - int16_t tm_yday; /* Day of year. [0-365] Needed internally for calculations */ -}; - -extern gtime_t g_rtcTime; -extern uint8_t g_ms100; // global to allow time set function to reset to zero - -void rtcInit(); - -#ifdef __cplusplus -extern "C" { -#endif -void rtcSetTime(struct gtm * tm); -void gettime(struct gtm * tm); -gtime_t gmktime (struct gtm *tm); -#ifdef __cplusplus -} -#endif - -#endif From 7f6a137ce8d40b6db60c5a19400127b8ceff4852 Mon Sep 17 00:00:00 2001 From: bsongis Date: Wed, 5 Mar 2014 14:24:51 +0100 Subject: [PATCH 041/285] 2 more files removed --- radio/bootloader/Makefile | 7 +- radio/bootloader/boot.cpp | 59 +---- radio/bootloader/driversboot.cpp | 129 +--------- radio/bootloader/include/drivers.h | 5 - radio/bootloader/include/logicio.h | 123 ---------- radio/bootloader/logicioboot.cpp | 97 +------- radio/bootloader/power.cpp | 117 --------- radio/src/keys.cpp | 13 +- radio/src/keys.h | 231 ++++++++++++++++++ radio/src/opentx.cpp | 1 - radio/src/opentx.h | 200 +-------------- radio/src/pwr.h | 47 ++++ radio/src/targets/taranis/board_taranis.cpp | 42 ---- radio/src/targets/taranis/board_taranis.h | 26 +- .../taranis/{pwr_driver.cpp => pwr_driver.c} | 44 ++-- radio/src/targets/taranis/usb_driver.c | 59 +++++ 16 files changed, 432 insertions(+), 768 deletions(-) delete mode 100644 radio/bootloader/include/logicio.h delete mode 100644 radio/bootloader/power.cpp create mode 100755 radio/src/keys.h create mode 100755 radio/src/pwr.h rename radio/src/targets/taranis/{pwr_driver.cpp => pwr_driver.c} (92%) create mode 100755 radio/src/targets/taranis/usb_driver.c diff --git a/radio/bootloader/Makefile b/radio/bootloader/Makefile index a458568b0..f67923ab8 100644 --- a/radio/bootloader/Makefile +++ b/radio/bootloader/Makefile @@ -137,17 +137,20 @@ SRC = system_stm32f2xx.c \ ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_core.c \ ../src/targets/taranis/usbd_desc.c \ ../src/targets/taranis/aspi.c \ - ../src/targets/taranis/usb_bsp.c + ../src/targets/taranis/usb_bsp.c \ + ../src/targets/taranis/usb_driver.c \ + ../src/targets/taranis/pwr_driver.c CPPSRC = ../src/targets/taranis/lcd_driver.cpp \ + ../src/targets/taranis/keys_driver.cpp \ driversboot.cpp \ logicioboot.cpp \ ../src/targets/taranis/diskio.cpp \ ../src/targets/taranis/usbd_usr.cpp \ usbd_storage_msd.cpp \ ../src/lcd.cpp \ + ../src/keys.cpp \ ../src/fonts.cpp \ - power.cpp \ boot.cpp # List ASM source files here diff --git a/radio/bootloader/boot.cpp b/radio/bootloader/boot.cpp index 479208ed2..b4c39a97d 100644 --- a/radio/bootloader/boot.cpp +++ b/radio/bootloader/boot.cpp @@ -53,17 +53,12 @@ #include #include #include -#ifdef PCBSKY -#include "AT91SAM3S4.h" -#include "core_cm3.h" -#endif #ifdef PCBTARANIS #include "stm32f2xx.h" #include "stm32f2xx_flash.h" #include "../src/targets/taranis/i2c.h" #include "hal.h" -// #include "timers.h" extern "C" { #include "usb_dcd_int.h" @@ -76,13 +71,15 @@ extern "C" { #endif #include "board_taranis.h" +#include "../src/pwr.h" #include "../src/lcd.h" +#include "../src/keys.h" -#include "radio.h" +// #include "radio.h" #include "../src/FatFs/ff.h" #include "../src/FatFs/diskio.h" -#include "drivers.h" -#include "logicio.h" +//#include "drivers.h" +// #include "logicio.h" #ifdef PCBSKY extern void usbMassStorage( void ) ; @@ -204,37 +201,7 @@ void delay2ms() } #endif -static bool usbPlugged(void) -{ -#ifdef PCBSKY - return PIOC->PIO_PDSR & 0x02000000 ; -#endif - #ifdef PCBTARANIS - return GPIOA->IDR & 0x0200 ; -#endif -} - -#ifdef PCBTARANIS - -extern "C" { -USB_OTG_CORE_HANDLE USB_OTG_dev; - -void OTG_FS_IRQHandler(void) -{ - USBD_OTG_ISR_Handler (&USB_OTG_dev); -} -} - -static void usbInit() -{ - USB_OTG_BSP_Init(&USB_OTG_dev); -} - -static void usbStart() -{ - USBD_Init(&USB_OTG_dev, USB_OTG_FS_CORE_ID, &USR_desc, &USBD_MSC_cb, &USR_cb); -} uint32_t isFirmwareStart( uint32_t *block ) { @@ -358,7 +325,8 @@ void clearLockBits() } #endif -void interrupt10ms() +void per10ms(void); +void interrupt10ms(void) { Tenms |= 1 ; // 10 mS has passed per10ms() ; @@ -760,7 +728,7 @@ int main() RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ; // Enable portA clock #endif - init_soft_power() ; + pwrInit() ; #ifdef PCBSKY MATRIX->CCFG_SYSIO |= 0x000000F0L ; // Disable syspins, enable B4,5,6,7 @@ -788,7 +756,7 @@ extern uint8_t OptrexDisplay ; #endif #ifdef PCBTARANIS - init_keys() ; + keysInit() ; I2C_EE_Init() ; init_hw_timer() ; #endif @@ -821,7 +789,7 @@ extern uint8_t OptrexDisplay ; #ifdef PCBTARANIS // SD card detect pin - configure_pins( SD_PRESENT_GPIO_Pin, PIN_PORTD | PIN_INPUT | PIN_PULLUP ) ; + // configure_pins( SD_PRESENT_GPIO_Pin, PIN_PORTD | PIN_INPUT | PIN_PULLUP ) ; disk_initialize( 0 ) ; sdInit() ; unlockFlash() ; @@ -1134,9 +1102,8 @@ extern uint8_t OptrexDisplay ; } if ((state < ST_FLASH_CHECK) || (state == ST_FLASH_DONE)) { - if ( check_soft_power() == POWER_OFF ) - { - soft_power_off() ; + if (pwrCheck() == e_power_off ) { + pwrOff() ; for(;;) { // Wait for power to go off @@ -1152,7 +1119,7 @@ extern uint8_t OptrexDisplay ; } if ( state == ST_REBOOT ) { - if ( (~read_keys() & 0x7E) == 0 ) + if ( (~readKeys() & 0x7E) == 0 ) { NVIC_SystemReset() ; } diff --git a/radio/bootloader/driversboot.cpp b/radio/bootloader/driversboot.cpp index ca3c917d9..4df371a16 100644 --- a/radio/bootloader/driversboot.cpp +++ b/radio/bootloader/driversboot.cpp @@ -21,137 +21,14 @@ #include #include -#ifdef PCBSKY -#include "radio.h" -#include "drivers.h" -#endif +#include "../src/opentx.h" - -#ifdef PCBTARANIS -#include "radio.h" -#include "hal.h" -#include "stm32f2xx.h" -#include "stm32f2xx_gpio.h" -#include "stm32f2xx_rcc.h" -#endif -#include "drivers.h" -#include "logicio.h" - -#ifdef EVT_KEY_MASK -#undef EVT_KEY_MASK -#endif - -#define EVT_KEY_MASK 0x0f - - -void b_putEvent( register uint8_t evt) ; -void per10ms( void ) ; -uint8_t getEvent( void ) ; -void pauseEvents(uint8_t event) ; -void killEvents(uint8_t event) ; - -uint8_t s_evt; -void b_putEvent( uint8_t evt) -{ - s_evt = evt; -} - - -uint8_t getEvent() -{ - register uint8_t evt = s_evt; - s_evt=0; - return evt; -} - -Key keys[NUM_KEYS] ; - -void Key::input(bool val, EnumKeys enuk) -{ - // uint8_t old=m_vals; - m_vals <<= 1; if(val) m_vals |= 1; //portbit einschieben - m_cnt++; - - if(m_state && m_vals==0){ //gerade eben sprung auf 0 - if(m_state!=KSTATE_KILLED) { - b_putEvent(EVT_KEY_BREAK(enuk)); - } - m_cnt = 0; - m_state = KSTATE_OFF; - } - switch(m_state){ - case KSTATE_OFF: - if(m_vals==FFVAL){ //gerade eben sprung auf ff - m_state = KSTATE_START; - m_cnt = 0; - } - break; - //fallthrough - case KSTATE_START: - b_putEvent(EVT_KEY_FIRST(enuk)); -#ifdef KSTATE_RPTDELAY - m_state = KSTATE_RPTDELAY; -#else - m_state = 16; -#endif - m_cnt = 0; - break; -#ifdef KSTATE_RPTDELAY - case KSTATE_RPTDELAY: // gruvin: longer delay before first key repeat - if(m_cnt == 32) b_putEvent(EVT_KEY_LONG(enuk)); // need to catch this inside RPTDELAY time - if (m_cnt == 40) { - m_state = 16; - m_cnt = 0; - } - break; -#endif - case 16: -#ifndef KSTATE_RPTDELAY - if(m_cnt == 32) b_putEvent(EVT_KEY_LONG(enuk)); - //fallthrough -#endif - case 8: - case 4: - case 2: - if(m_cnt >= 48) { //3 6 12 24 48 pulses in every 480ms - m_state >>= 1; - m_cnt = 0; - } - //fallthrough - case 1: - if( (m_cnt & (m_state-1)) == 0) b_putEvent(EVT_KEY_REPT(enuk)); - break; - - case KSTATE_PAUSE: //pause - if(m_cnt >= 64) { - m_state = 8; - m_cnt = 0; - } - break; - - case KSTATE_KILLED: //killed - break; - } -} - -void b_pauseEvents(uint8_t event) -{ - event=event & EVT_KEY_MASK; - if(event < (int)DIM(keys)) keys[event].pauseEvents(); -} - -void killEvents(uint8_t event) -{ - event=event & EVT_KEY_MASK; - if(event < (int)DIM(keys)) keys[event].killEvents(); -} - -void per10ms() +void per10ms(void) { register uint32_t i ; uint8_t enuk = KEY_MENU; - uint8_t in = ~read_keys() ; + uint8_t in = ~readKeys() ; // Bits 3-6 are down, up, right and left // Try to only allow one at a #ifdef REVX diff --git a/radio/bootloader/include/drivers.h b/radio/bootloader/include/drivers.h index bca87090c..2ba37370d 100644 --- a/radio/bootloader/include/drivers.h +++ b/radio/bootloader/include/drivers.h @@ -4,12 +4,7 @@ extern volatile uint32_t Spi_complete ; -extern void putEvent( register uint8_t evt) ; - extern void per10ms( void ) ; -extern uint8_t getEvent( void ) ; -extern void pauseEvents(uint8_t event) ; -extern void killEvents(uint8_t event) ; extern void init_spi( void ) ; extern void end_spi( void ) ; diff --git a/radio/bootloader/include/logicio.h b/radio/bootloader/include/logicio.h deleted file mode 100644 index a8b004eca..000000000 --- a/radio/bootloader/include/logicio.h +++ /dev/null @@ -1,123 +0,0 @@ -/**************************************************************************** -* Copyright (c) 2012 by Michael Blandford. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License version 2 as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* -****************************************************************************/ - -#ifdef PCBTARANIS -#define PIN_MODE_MASK 0x0003 -#define PIN_INPUT 0x0000 -#define PIN_OUTPUT 0x0001 -#define PIN_PERIPHERAL 0x0002 -#define PIN_ANALOG 0x0003 -#define PIN_PULL_MASK 0x000C -#define PIN_PULLUP 0x0004 -#define PIN_NO_PULLUP 0x0000 -#define PIN_PULLDOWN 0x0008 -#define PIN_NO_PULLDOWN 0x0000 -#define PIN_NO_PULL 0x0000 -#define PIN_PERI_MASK 0x00F0 -//#define PIN_PERI_MASK_H 0x0020 -#define PIN_PER_0 0x0000 -#define PIN_PER_1 0x0010 -#define PIN_PER_2 0x0020 -#define PIN_PER_3 0x0030 -#define PIN_PER_4 0x0040 -#define PIN_PER_5 0x0050 -#define PIN_PER_6 0x0060 -#define PIN_PER_7 0x0070 -#define PIN_PER_8 0x0080 -#define PIN_PER_9 0x0090 -#define PIN_PER_10 0x00A0 -#define PIN_PER_11 0x00B0 -#define PIN_PER_12 0x00C0 -#define PIN_PER_13 0x00D0 -#define PIN_PER_14 0x00E0 -#define PIN_PER_15 0x00F0 -#define PIN_PORT_MASK 0x0700 -#define PIN_PORTA 0x0000 -#define PIN_PORTB 0x0100 -#define PIN_PORTC 0x0200 -#define PIN_PORTD 0x0300 -#define PIN_PORTE 0x0400 -#define PIN_LOW 0x0000 -#define PIN_HIGH 0x1000 -#define PIN_SPEED_MASK 0x6000 -#define PIN_OS2 0x0000 -#define PIN_OS25 0x2000 -#define PIN_OS50 0x4000 -#define PIN_OS100 0x6000 -#define PIN_PUSHPULL 0x0000 -#define PIN_ODRAIN 0x8000 - -#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ -#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ -#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ -#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ -#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ -#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ -#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ -#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ -#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ -#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ -#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ -#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ -#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ -#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ -#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ -#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ -#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ - -#endif - - -#ifdef PCBSKY -#define PIN_ENABLE 0x001 -#define PIN_PERIPHERAL 0x000 -#define PIN_INPUT 0x002 -#define PIN_OUTPUT 0x000 -#define PIN_PULLUP 0x004 -#define PIN_NO_PULLUP 0x000 -#define PIN_PULLDOWN 0x008 -#define PIN_NO_PULLDOWN 0x000 -#define PIN_PERI_MASK_L 0x010 -#define PIN_PERI_MASK_H 0x020 -#define PIN_PER_A 0x000 -#define PIN_PER_B 0x010 -#define PIN_PER_C 0x020 -#define PIN_PER_D 0x030 -#define PIN_PORT_MASK 0x0C0 -#define PIN_PORTA 0x000 -#define PIN_PORTB 0x040 -#define PIN_PORTC 0x080 -#define PIN_LOW 0x000 -#define PIN_HIGH 0x100 -#endif - - -extern void configure_pins( uint32_t pins, uint16_t config ) ; -extern void init_keys( void ) ; -extern uint32_t read_keys( void ) ; -extern uint32_t read_trims( void ) ; -extern uint32_t keyState( enum EnumKeys enuk) ; -extern void init_trims( void ) ; -extern void setup_switches( void ) ; -extern void config_free_pins( void ) ; - -#define GPIO_ResetBits( port, bits ) (port->BSRRH = bits) -#define GPIO_SetBits( port, bits ) (port->BSRRL = bits) -#define GPIO_ReadInputDataBit( port, bit) ( (port->IDR & bit) ? Bit_SET : Bit_RESET) - -#ifdef PCBTARANIS -uint32_t switchPosition( uint32_t swtch ) ; -#endif - diff --git a/radio/bootloader/logicioboot.cpp b/radio/bootloader/logicioboot.cpp index 3b7f02dce..cc3df751a 100644 --- a/radio/bootloader/logicioboot.cpp +++ b/radio/bootloader/logicioboot.cpp @@ -25,14 +25,7 @@ #include "drivers.h" #endif -#ifdef PCBTARANIS -#include "stm32f2xx.h" -#include "stm32f2xx_gpio.h" -#include "radio.h" -#include "hal.h" -#endif - -#include "logicio.h" +#include "../src/opentx.h" #ifndef SIMU @@ -40,7 +33,7 @@ void configure_pins( uint32_t pins, uint16_t config ) { register Pio *pioptr ; - + pioptr = PIOA + ( ( config & PIN_PORT_MASK ) >> 6) ; if ( config & PIN_PULLUP ) { @@ -64,11 +57,11 @@ void configure_pins( uint32_t pins, uint16_t config ) if ( config & PIN_HIGH ) { - pioptr->PIO_SODR = pins ; + pioptr->PIO_SODR = pins ; } else { - pioptr->PIO_CODR = pins ; + pioptr->PIO_CODR = pins ; } if ( config & PIN_INPUT ) @@ -99,11 +92,11 @@ void configure_pins( uint32_t pins, uint16_t config ) if ( config & PIN_ENABLE ) { - pioptr->PIO_PER = pins ; + pioptr->PIO_PER = pins ; } else { - pioptr->PIO_PDR = pins ; + pioptr->PIO_PDR = pins ; } } #endif @@ -153,17 +146,17 @@ void configure_pins( uint32_t pins, uint16_t config ) } } } - + #endif #ifdef PCBSKY - + void init_keys() { register Pio *pioptr ; - + pioptr = PIOC ; // Next section configures the key inputs on the LCD data pioptr->PIO_PER = 0x0000003BL ; // Enable bits 1,3,4,5, 0 @@ -230,7 +223,7 @@ void setup_switches() // PC21, PC19, PC15 (PPM2 output) void config_free_pins() { - + configure_pins( PIO_PB14, PIN_ENABLE | PIN_INPUT | PIN_PORTB | PIN_PULLUP ) ; } @@ -255,7 +248,7 @@ uint32_t read_keys() register uint32_t y ; x = LcdLock ? LcdInputs : PIOC->PIO_PDSR << 1 ; // 6 LEFT, 5 RIGHT, 4 DOWN, 3 UP () - + y = x & 0x00000020 ; // RIGHT if ( x & 0x00000004 ) { @@ -300,7 +293,7 @@ uint32_t read_trims() { trims |= 1 ; } - + // TRIM_LV_DOWN PA27 (PA24) if ( ( trima & 0x01000000 ) == 0 ) { @@ -375,74 +368,10 @@ uint32_t initReadTrims( void ) { __asm("nop") ; } - + return read_trims() ; } #endif // PCBSKY -#ifdef PCBTARANIS -void init_keys() -{ -// Buttons PE10, 11, 12, PD2, 3, 7 - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOEEN ; // Enable portE clock - configure_pins( 0x1C00, PIN_INPUT | PIN_PULLUP | PIN_PORTE ) ; - configure_pins( 0x008C, PIN_INPUT | PIN_PULLUP | PIN_PORTD ) ; -} -// Reqd. bit 6 LEFT, 5 RIGHT, 4 UP, 3 DOWN 2 EXIT 1 MENU -uint32_t read_keys() -{ - register uint32_t x ; - register uint32_t y ; - - x = GPIOD->IDR ; // 7 MENU, 3 PAGE(UP), 2 EXIT - - y = 0 ; - if ( x & PIN_BUTTON_MENU ) - { - y |= 0x02 << KEY_MENU ; // up -// y |= 0x02 << KEY_MENU ; // MENU - } - if ( x & PIN_BUTTON_PAGE ) - { - y |= 0x02 << KEY_PAGE ; // LEFT - } - if ( x & PIN_BUTTON_EXIT ) - { - y |= 0x02 << KEY_EXIT ; // DOWN -// y |= 0x02 << KEY_EXIT ; // EXIT - } - - x = GPIOE->IDR ; // 10 RIGHT(+), 11 LEFT(-), 12 ENT(DOWN) - if ( x & PIN_BUTTON_PLUS ) - { - y |= 0x02 << KEY_PLUS ; // MENU -// y |= 0x02 << KEY_UP ; // up - } - if ( x & PIN_BUTTON_MINUS ) - { - y |= 0x02 << KEY_MINUS ; // RIGHT -// y |= 0x02 << KEY_DOWN ; // DOWN - } - if ( x & PIN_BUTTON_ENTER ) - { - y |= 0x02 << KEY_ENTER ; // EXIT -// y |= 0x02 << KEY_RIGHT ; // RIGHT - } - return y ; -} - -// -void setup_switches() -{ - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ; // Enable portA clock - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN ; // Enable portB clock - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOEEN ; // Enable portE clock - configure_pins( 0x0020, PIN_INPUT | PIN_PULLUP | PIN_PORTA ) ; - configure_pins( 0x003A, PIN_INPUT | PIN_PULLUP | PIN_PORTB ) ; - configure_pins( 0xE307, PIN_INPUT | PIN_PULLUP | PIN_PORTE ) ; - -} - -#endif // PCBTARANIS diff --git a/radio/bootloader/power.cpp b/radio/bootloader/power.cpp deleted file mode 100644 index 5873d62e1..000000000 --- a/radio/bootloader/power.cpp +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Authors (alphabetical order) - * - Andre Bernet - * - Bertrand Songis - * - Bryan J. Rentoul (Gruvin) - * - Cameron Weeks - * - Erez Raviv - * - Jean-Pierre Parisy - * - Karl Szmutny - * - Michael Blandford - * - Michal Hlavinka - * - Pat Mackenzie - * - Philip Moss - * - Rob Thomson - * - Romolo Manfredini - * - Thomas Husterer - * - * open9x is based on code named - * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, - * er9x by Erez Raviv: http://code.google.com/p/er9x/, - * and the original (and ongoing) project by - * Thomas Husterer, th9x: http://code.google.com/p/th9x/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#ifdef PCBSKY -#include "AT91SAM3S4.h" -#endif - - -#ifdef PCBTARANIS -#include "stm32f2xx_gpio.h" -#include "stm32f2xx_rcc.h" -#include "hal.h" -#endif - -#include "radio.h" -#include "logicio.h" - -#ifdef PCBSKY - - -void init_soft_power() -{ - // Configure RF_power (PC17) - configure_pins( PIO_PC17, PIN_ENABLE | PIN_INPUT | PIN_PORTC | PIN_NO_PULLUP | PIN_PULLDOWN ) ; - - configure_pins( PIO_PA8, PIN_ENABLE | PIN_INPUT | PIN_PORTA | PIN_PULLUP ) ; -} - - -// Returns zero if power is switched off -// 1 if power switch is on -// 2 if power switch off, trainer power on -uint32_t check_soft_power() -{ - if ( PIOC->PIO_PDSR & PIO_PC17 ) // Power on - { - return POWER_ON ; - } - return POWER_OFF ; -} - - -// turn off soft power -void soft_power_off() -{ - configure_pins( PIO_PA8, PIN_ENABLE | PIN_OUTPUT | PIN_LOW | PIN_PORTA | PIN_NO_PULLUP ) ; -} - -#endif - -#ifdef PCBTARANIS - -void soft_power_off() -{ - GPIO_ResetBits(GPIOPWR,PIN_MCU_PWR); -} - -uint32_t check_soft_power() -{ - if (GPIO_ReadInputDataBit(GPIOPWR, PIN_PWR_STATUS) == Bit_RESET) - return POWER_ON; - else - return POWER_OFF; -} - -void init_soft_power() -{ - RCC->AHB1ENR |= RCC_AHB1ENR_GPIODEN ; // Enable portD clock - GPIO_ResetBits(GPIOPWR, PIN_INT_RF_PWR | PIN_EXT_RF_PWR); - - /* GPIO Configuration*/ - configure_pins( PIN_INT_RF_PWR | PIN_EXT_RF_PWR | PIN_MCU_PWR, PIN_OUTPUT | PIN_PUSHPULL | PIN_OS25 | PIN_PORTD ) ; - - configure_pins( PIN_PWR_STATUS, PIN_INPUT | PIN_PULLUP | PIN_PORTD ) ; - - configure_pins( PIN_TRNDET, PIN_INPUT | PIN_PULLUP | PIN_PORTA ) ; - - // Soft power ON - - GPIO_SetBits(GPIOPWR,PIN_MCU_PWR); - -} - -#endif - diff --git a/radio/src/keys.cpp b/radio/src/keys.cpp index 3c76e5bba..c6f7c4096 100644 --- a/radio/src/keys.cpp +++ b/radio/src/keys.cpp @@ -37,6 +37,7 @@ #include "opentx.h" uint8_t s_evt; +struct t_inactivity inactivity = {0}; #if defined(CPUARM) uint8_t getEvent(bool trim) @@ -97,7 +98,9 @@ void Key::input(bool val, EnumKeys enuk) break; case KSTATE_RPTDELAY: // gruvin: delay state before first key repeat - if(m_cnt == KEY_LONG_DELAY) putEvent(EVT_KEY_LONG(enuk)); + if (m_cnt == KEY_LONG_DELAY) { + putEvent(EVT_KEY_LONG(enuk)); + } if (m_cnt == 40) { m_state = 16; m_cnt = 0; @@ -108,17 +111,19 @@ void Key::input(bool val, EnumKeys enuk) case 8: case 4: case 2: - if(m_cnt >= 48) { //3 6 12 24 48 pulses in every 480ms + if (m_cnt >= 48) { //3 6 12 24 48 pulses in every 480ms m_state >>= 1; m_cnt = 0; } // no break case 1: - if( (m_cnt & (m_state-1)) == 0) putEvent(EVT_KEY_REPT(enuk)); + if ((m_cnt & (m_state-1)) == 0) { + putEvent(EVT_KEY_REPT(enuk)); + } break; case KSTATE_PAUSE: //pause - if(m_cnt >= 64) { + if (m_cnt >= 64) { m_state = 8; m_cnt = 0; } diff --git a/radio/src/keys.h b/radio/src/keys.h new file mode 100755 index 000000000..350ab81d5 --- /dev/null +++ b/radio/src/keys.h @@ -0,0 +1,231 @@ +/* + * Authors (alphabetical order) + * - Andre Bernet + * - Andreas Weitl + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Gabriel Birkus + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * opentx is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef keys_h +#define keys_h + +enum EnumKeys { + KEY_MENU, + KEY_EXIT, +#if defined(PCBTARANIS) + KEY_ENTER, + KEY_PAGE, + KEY_PLUS, + KEY_MINUS, +#else + KEY_DOWN, + KEY_UP, + KEY_RIGHT, + KEY_LEFT, +#endif + + TRM_BASE, + TRM_LH_DWN = TRM_BASE, + TRM_LH_UP, + TRM_LV_DWN, + TRM_LV_UP, + TRM_RV_DWN, + TRM_RV_UP, + TRM_RH_DWN, + TRM_RH_UP, + +#if ROTARY_ENCODERS > 0 || defined(ROTARY_ENCODER_NAVIGATION) + BTN_REa, +#endif +#if ROTARY_ENCODERS > 0 + BTN_REb, +#endif + + NUM_KEYS, + SW_BASE=NUM_KEYS, + +#if defined(PCBTARANIS) + SW_SA0=SW_BASE, + SW_SA1, + SW_SA2, + SW_SB0, + SW_SB1, + SW_SB2, + SW_SC0, + SW_SC1, + SW_SC2, + SW_SD0, + SW_SD1, + SW_SD2, + SW_SE0, + SW_SE1, + SW_SE2, + SW_SF0, + SW_SF2, + SW_SG0, + SW_SG1, + SW_SG2, + SW_SH0, + SW_SH2, +#else + SW_ID0=SW_BASE, + SW_ID1, + SW_ID2, +#if defined(EXTRA_3POS) + SW_ID3, + SW_ID4, + SW_ID5, +#endif + + SW_THR, + SW_RUD, + SW_ELE, + SW_AIL, + SW_GEA, + SW_TRN, +#endif + +}; + +#define EVT_KEY_MASK(e) ((e) & 0x1f) + +#define _MSK_KEY_BREAK 0x20 +#define _MSK_KEY_REPT 0x40 +#define _MSK_KEY_FIRST 0x60 +#define _MSK_KEY_LONG 0x80 + +#define EVT_KEY_BREAK(key) ((key)|_MSK_KEY_BREAK) +#define EVT_KEY_FIRST(key) ((key)|_MSK_KEY_FIRST) +#define EVT_KEY_REPT(key) ((key)|_MSK_KEY_REPT) +#define EVT_KEY_LONG(key) ((key)|_MSK_KEY_LONG) + +#define IS_KEY_BREAK(evt) (((evt)&0xe0) == _MSK_KEY_BREAK) +#define IS_KEY_FIRST(evt) (((evt)&0xe0) == _MSK_KEY_FIRST) +#define IS_KEY_LONG(evt) (((evt)&0xe0) == _MSK_KEY_LONG) + +#define EVT_ENTRY 0xbf +#define EVT_ENTRY_UP 0xbe +#define EVT_MENU_UP 0xbd + +#if defined(PCBTARANIS) + #define EVT_ROTARY_BREAK EVT_KEY_BREAK(KEY_ENTER) + #define EVT_ROTARY_LONG EVT_KEY_LONG(KEY_ENTER) +#else + #define EVT_ROTARY_BREAK 0xcf + #define EVT_ROTARY_LONG 0xce + #define EVT_ROTARY_LEFT 0xdf + #define EVT_ROTARY_RIGHT 0xde +#endif + +#if defined(PCBTARANIS) + #define IS_ROTARY_LEFT(evt) (evt==EVT_KEY_FIRST(KEY_MINUS) || evt==EVT_KEY_REPT(KEY_MINUS)) + #define IS_ROTARY_RIGHT(evt) (evt==EVT_KEY_FIRST(KEY_PLUS) || evt==EVT_KEY_REPT(KEY_PLUS)) + #define IS_ROTARY_UP(evt) (evt==EVT_KEY_FIRST(KEY_PLUS) || evt==EVT_KEY_REPT(KEY_PLUS)) + #define IS_ROTARY_DOWN(evt) (evt==EVT_KEY_FIRST(KEY_MINUS) || evt==EVT_KEY_REPT(KEY_MINUS)) + #define IS_ROTARY_BREAK(evt) (evt==EVT_KEY_BREAK(KEY_ENTER)) + #define IS_ROTARY_LONG(evt) (evt==EVT_KEY_LONG(KEY_ENTER)) + #define IS_ROTARY_EVENT(evt) (0) + #define CASE_EVT_ROTARY_BREAK /*case EVT_KEY_BREAK(KEY_ENTER):*/ + #define CASE_EVT_ROTARY_LONG /*case EVT_KEY_LONG(KEY_ENTER):*/ + #define CASE_EVT_ROTARY_LEFT case EVT_KEY_FIRST(KEY_MOVE_DOWN): case EVT_KEY_REPT(KEY_MOVE_DOWN): + #define CASE_EVT_ROTARY_RIGHT case EVT_KEY_FIRST(KEY_MOVE_UP): case EVT_KEY_REPT(KEY_MOVE_UP): +#elif defined(ROTARY_ENCODER_NAVIGATION) + #define IS_ROTARY_LEFT(evt) (evt == EVT_ROTARY_LEFT) + #define IS_ROTARY_RIGHT(evt) (evt == EVT_ROTARY_RIGHT) + #define IS_ROTARY_UP(evt) IS_ROTARY_LEFT(evt) + #define IS_ROTARY_DOWN(evt) IS_ROTARY_RIGHT(evt) + #define IS_ROTARY_BREAK(evt) (evt == EVT_ROTARY_BREAK) + #define IS_ROTARY_LONG(evt) (evt == EVT_ROTARY_LONG) + #define IS_ROTARY_EVENT(evt) (EVT_KEY_MASK(evt) >= 0x0e) + #define CASE_EVT_ROTARY_BREAK case EVT_ROTARY_BREAK: + #define CASE_EVT_ROTARY_LONG case EVT_ROTARY_LONG: + #define CASE_EVT_ROTARY_LEFT case EVT_ROTARY_LEFT: + #define CASE_EVT_ROTARY_RIGHT case EVT_ROTARY_RIGHT: +#else + #define IS_ROTARY_LEFT(evt) (0) + #define IS_ROTARY_RIGHT(evt) (0) + #define IS_ROTARY_UP(evt) (0) + #define IS_ROTARY_DOWN(evt) (0) + #define IS_ROTARY_BREAK(evt) (0) + #define IS_ROTARY_LONG(evt) (0) + #define IS_ROTARY_EVENT(evt) (0) + #define CASE_EVT_ROTARY_BREAK + #define CASE_EVT_ROTARY_LONG + #define CASE_EVT_ROTARY_LEFT + #define CASE_EVT_ROTARY_RIGHT +#endif + +class Key +{ +#define FILTERBITS 4 + +#ifdef SIMU + #define FFVAL 1 +#else + #define FFVAL ((1< 0; } + void pauseEvents() { m_state = KSTATE_PAUSE; m_cnt = 0; } + void killEvents() { m_state = KSTATE_KILLED; } +}; + +extern Key keys[NUM_KEYS]; + +extern uint8_t s_evt; + +#define putEvent(evt) s_evt = evt + +void clearKeyEvents(); +void pauseEvents(uint8_t enuk); +void killEvents(uint8_t enuk); + +#if defined(CPUARM) + uint8_t getEvent(bool trim=false); +#else + uint8_t getEvent(); +#endif + +uint8_t keyDown(); + +#endif diff --git a/radio/src/opentx.cpp b/radio/src/opentx.cpp index a8090a9aa..2e3183b14 100644 --- a/radio/src/opentx.cpp +++ b/radio/src/opentx.cpp @@ -45,7 +45,6 @@ int16_t anas [NUM_INPUTS] = {0}; int16_t trims[NUM_STICKS] = {0}; int32_t chans[NUM_CHNOUT] = {0}; BeepANACenter bpanaCenter = 0; -struct t_inactivity inactivity = {0}; int24_t act [MAX_MIXERS] = {0}; SwOn swOn [MAX_MIXERS]; // TODO better name later... diff --git a/radio/src/opentx.h b/radio/src/opentx.h index aafcdacf6..d1fc73358 100644 --- a/radio/src/opentx.h +++ b/radio/src/opentx.h @@ -297,83 +297,6 @@ extern void boardInit(); #define NUM_STICKS 4 -enum EnumKeys { - KEY_MENU, - KEY_EXIT, -#if defined(PCBTARANIS) - KEY_ENTER, - KEY_PAGE, - KEY_PLUS, - KEY_MINUS, -#else - KEY_DOWN, - KEY_UP, - KEY_RIGHT, - KEY_LEFT, -#endif - - TRM_BASE, - TRM_LH_DWN = TRM_BASE, - TRM_LH_UP, - TRM_LV_DWN, - TRM_LV_UP, - TRM_RV_DWN, - TRM_RV_UP, - TRM_RH_DWN, - TRM_RH_UP, - -#if ROTARY_ENCODERS > 0 || defined(ROTARY_ENCODER_NAVIGATION) - BTN_REa, -#endif -#if ROTARY_ENCODERS > 0 - BTN_REb, -#endif - - NUM_KEYS, - SW_BASE=NUM_KEYS, - -#if defined(PCBTARANIS) - SW_SA0=SW_BASE, - SW_SA1, - SW_SA2, - SW_SB0, - SW_SB1, - SW_SB2, - SW_SC0, - SW_SC1, - SW_SC2, - SW_SD0, - SW_SD1, - SW_SD2, - SW_SE0, - SW_SE1, - SW_SE2, - SW_SF0, - SW_SF2, - SW_SG0, - SW_SG1, - SW_SG2, - SW_SH0, - SW_SH2, -#else - SW_ID0=SW_BASE, - SW_ID1, - SW_ID2, -#if defined(EXTRA_3POS) - SW_ID3, - SW_ID4, - SW_ID5, -#endif - - SW_THR, - SW_RUD, - SW_ELE, - SW_AIL, - SW_GEA, - SW_TRN, -#endif - -}; #if defined(PCBTARANIS) #define NUM_SWITCHES 8 @@ -587,35 +510,6 @@ extern uint8_t stickMode; extern uint8_t channel_order(uint8_t x); -class Key -{ -#define FILTERBITS 4 - -#ifdef SIMU - #define FFVAL 1 -#else - #define FFVAL ((1< 0; } - void pauseEvents() { m_state = KSTATE_PAUSE; m_cnt = 0; } - void killEvents() { m_state = KSTATE_KILLED; } -}; - -extern Key keys[NUM_KEYS]; - enum BaseCurves { CURVE_NONE, CURVE_X_GT0, @@ -630,77 +524,9 @@ enum BaseCurves { #define THRCHK_DEADBAND 16 #if defined(FSPLASH) || defined(XSPLASH) -#define SPLASH_TIMEOUT (g_eeGeneral.splashMode == 0 ? 60000/*infinite=10mn*/ : ((4*100) * (g_eeGeneral.splashMode & 0x03))) + #define SPLASH_TIMEOUT (g_eeGeneral.splashMode == 0 ? 60000/*infinite=10mn*/ : ((4*100) * (g_eeGeneral.splashMode & 0x03))) #else -#define SPLASH_TIMEOUT (4*100) // 4 seconds -#endif - -#define EVT_KEY_MASK(e) ((e) & 0x1f) - -#define _MSK_KEY_BREAK 0x20 -#define _MSK_KEY_REPT 0x40 -#define _MSK_KEY_FIRST 0x60 -#define _MSK_KEY_LONG 0x80 - -#define EVT_KEY_BREAK(key) ((key)|_MSK_KEY_BREAK) -#define EVT_KEY_FIRST(key) ((key)|_MSK_KEY_FIRST) -#define EVT_KEY_REPT(key) ((key)|_MSK_KEY_REPT) -#define EVT_KEY_LONG(key) ((key)|_MSK_KEY_LONG) - -#define IS_KEY_BREAK(evt) (((evt)&0xe0) == _MSK_KEY_BREAK) -#define IS_KEY_FIRST(evt) (((evt)&0xe0) == _MSK_KEY_FIRST) -#define IS_KEY_LONG(evt) (((evt)&0xe0) == _MSK_KEY_LONG) - -#define EVT_ENTRY 0xbf -#define EVT_ENTRY_UP 0xbe -#define EVT_MENU_UP 0xbd - -#if defined(PCBTARANIS) - #define EVT_ROTARY_BREAK EVT_KEY_BREAK(KEY_ENTER) - #define EVT_ROTARY_LONG EVT_KEY_LONG(KEY_ENTER) -#else - #define EVT_ROTARY_BREAK 0xcf - #define EVT_ROTARY_LONG 0xce - #define EVT_ROTARY_LEFT 0xdf - #define EVT_ROTARY_RIGHT 0xde -#endif - -#if defined(PCBTARANIS) - #define IS_ROTARY_LEFT(evt) (evt==EVT_KEY_FIRST(KEY_MINUS) || evt==EVT_KEY_REPT(KEY_MINUS)) - #define IS_ROTARY_RIGHT(evt) (evt==EVT_KEY_FIRST(KEY_PLUS) || evt==EVT_KEY_REPT(KEY_PLUS)) - #define IS_ROTARY_UP(evt) (evt==EVT_KEY_FIRST(KEY_PLUS) || evt==EVT_KEY_REPT(KEY_PLUS)) - #define IS_ROTARY_DOWN(evt) (evt==EVT_KEY_FIRST(KEY_MINUS) || evt==EVT_KEY_REPT(KEY_MINUS)) - #define IS_ROTARY_BREAK(evt) (evt==EVT_KEY_BREAK(KEY_ENTER)) - #define IS_ROTARY_LONG(evt) (evt==EVT_KEY_LONG(KEY_ENTER)) - #define IS_ROTARY_EVENT(evt) (0) - #define CASE_EVT_ROTARY_BREAK /*case EVT_KEY_BREAK(KEY_ENTER):*/ - #define CASE_EVT_ROTARY_LONG /*case EVT_KEY_LONG(KEY_ENTER):*/ - #define CASE_EVT_ROTARY_LEFT case EVT_KEY_FIRST(KEY_MOVE_DOWN): case EVT_KEY_REPT(KEY_MOVE_DOWN): - #define CASE_EVT_ROTARY_RIGHT case EVT_KEY_FIRST(KEY_MOVE_UP): case EVT_KEY_REPT(KEY_MOVE_UP): -#elif defined(ROTARY_ENCODER_NAVIGATION) - #define IS_ROTARY_LEFT(evt) (evt == EVT_ROTARY_LEFT) - #define IS_ROTARY_RIGHT(evt) (evt == EVT_ROTARY_RIGHT) - #define IS_ROTARY_UP(evt) IS_ROTARY_LEFT(evt) - #define IS_ROTARY_DOWN(evt) IS_ROTARY_RIGHT(evt) - #define IS_ROTARY_BREAK(evt) (evt == EVT_ROTARY_BREAK) - #define IS_ROTARY_LONG(evt) (evt == EVT_ROTARY_LONG) - #define IS_ROTARY_EVENT(evt) (EVT_KEY_MASK(evt) >= 0x0e) - #define CASE_EVT_ROTARY_BREAK case EVT_ROTARY_BREAK: - #define CASE_EVT_ROTARY_LONG case EVT_ROTARY_LONG: - #define CASE_EVT_ROTARY_LEFT case EVT_ROTARY_LEFT: - #define CASE_EVT_ROTARY_RIGHT case EVT_ROTARY_RIGHT: -#else - #define IS_ROTARY_LEFT(evt) (0) - #define IS_ROTARY_RIGHT(evt) (0) - #define IS_ROTARY_UP(evt) (0) - #define IS_ROTARY_DOWN(evt) (0) - #define IS_ROTARY_BREAK(evt) (0) - #define IS_ROTARY_LONG(evt) (0) - #define IS_ROTARY_EVENT(evt) (0) - #define CASE_EVT_ROTARY_BREAK - #define CASE_EVT_ROTARY_LONG - #define CASE_EVT_ROTARY_LEFT - #define CASE_EVT_ROTARY_RIGHT + #define SPLASH_TIMEOUT (4*100) // 4 seconds #endif #if defined(PCBTARANIS) @@ -734,6 +560,7 @@ struct t_inactivity uint16_t counter; uint8_t sum; }; + extern struct t_inactivity inactivity; #if defined(PXX) @@ -754,25 +581,8 @@ void str2zchar(char *dest, const char *src, int size); void zchar2str(char *dest, const char *src, int size); #endif -extern uint8_t s_evt; -#define putEvent(evt) s_evt = evt -void clearKeyEvents(); -void pauseEvents(uint8_t enuk); -void killEvents(uint8_t enuk); -#if defined(CPUARM) - uint8_t getEvent(bool trim); -#else - uint8_t getEvent(); -#endif - -uint8_t keyDown(); - -enum PowerState { - e_power_on, - e_power_trainer, - e_power_usb, - e_power_off -}; +#include "keys.h" +#include "pwr.h" bool switchState(EnumKeys enuk); uint8_t trimDown(uint8_t idx); diff --git a/radio/src/pwr.h b/radio/src/pwr.h new file mode 100755 index 000000000..b6816d590 --- /dev/null +++ b/radio/src/pwr.h @@ -0,0 +1,47 @@ +/* + * Authors (alphabetical order) + * - Andre Bernet + * - Andreas Weitl + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Gabriel Birkus + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * opentx is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef pwr_h +#define pwr_h + +enum PowerState { + e_power_on, + e_power_trainer, + e_power_usb, + e_power_off +}; + +#endif diff --git a/radio/src/targets/taranis/board_taranis.cpp b/radio/src/targets/taranis/board_taranis.cpp index 754f6e6c1..5266f1c98 100644 --- a/radio/src/targets/taranis/board_taranis.cpp +++ b/radio/src/targets/taranis/board_taranis.cpp @@ -44,22 +44,6 @@ extern "C" { volatile uint32_t Tenms ; // TODO to remove everywhere / use a #define -#define PIN_MODE_MASK 0x0003 -#define PIN_INPUT 0x0000 -#define PIN_OUTPUT 0x0001 -#define PIN_PERIPHERAL 0x0002 -#define PIN_ANALOG 0x0003 -#define PIN_PULL_MASK 0x000C -#define PIN_PULLUP 0x0004 -#define PIN_NO_PULLUP 0x0000 -#define PIN_PULLDOWN 0x0008 -#define PIN_NO_PULLDOWN 0x0000 -#define PIN_PERI_MASK 0x00F0 -#define PIN_PUSHPULL 0x0000 -#define PIN_ODRAIN 0x8000 -#define PIN_PORT_MASK 0x0700 -#define PIN_SPEED_MASK 0x6000 - #if !defined(SIMU) void configure_pins( uint32_t pins, uint16_t config ) { @@ -106,32 +90,6 @@ void configure_pins( uint32_t pins, uint16_t config ) } #endif -bool usbPlugged(void) -{ - return GPIO_ReadInputDataBit(GPIOA, PIN_FS_VBUS); -} - -#if !defined(SIMU) -extern "C" { -USB_OTG_CORE_HANDLE USB_OTG_dev; - -void OTG_FS_IRQHandler(void) -{ - USBD_OTG_ISR_Handler (&USB_OTG_dev); -} -} - -void usbInit() -{ - USB_OTG_BSP_Init(&USB_OTG_dev); -} - -void usbStart() -{ - USBD_Init(&USB_OTG_dev, USB_OTG_FS_CORE_ID, &USR_desc, &USBD_MSC_cb, &USR_cb); -} -#endif - void watchdogInit(unsigned int duration) { IWDG->KR = 0x5555 ; // Unlock registers diff --git a/radio/src/targets/taranis/board_taranis.h b/radio/src/targets/taranis/board_taranis.h index f561e979d..6a1a1e783 100644 --- a/radio/src/targets/taranis/board_taranis.h +++ b/radio/src/targets/taranis/board_taranis.h @@ -75,6 +75,22 @@ extern "C" { #define JACK_PPM_OUT() #define JACK_PPM_IN() +#define PIN_MODE_MASK 0x0003 +#define PIN_INPUT 0x0000 +#define PIN_OUTPUT 0x0001 +#define PIN_PERIPHERAL 0x0002 +#define PIN_ANALOG 0x0003 +#define PIN_PULL_MASK 0x000C +#define PIN_PULLUP 0x0004 +#define PIN_NO_PULLUP 0x0000 +#define PIN_PULLDOWN 0x0008 +#define PIN_NO_PULLDOWN 0x0000 +#define PIN_PERI_MASK 0x00F0 +#define PIN_PUSHPULL 0x0000 +#define PIN_ODRAIN 0x8000 +#define PIN_PORT_MASK 0x0700 +#define PIN_SPEED_MASK 0x6000 + void configure_pins( uint32_t pins, uint16_t config ); #define strcpy_P strcpy @@ -160,6 +176,10 @@ extern volatile uint16_t Analog_values[]; #define BATT_SCALE 150 #endif +#ifdef __cplusplus +extern "C" { +#endif + // Power driver void pwrInit(void); uint32_t pwrCheck(void); @@ -176,13 +196,15 @@ void pwrOff(void); #define __BACKLIGHT_OFF TIM10->CCR1 = 0 #define IS_BACKLIGHT_ON() (TIM10->CCR1 != 0) -#if !defined(BOOT) // USB driver +int usbPlugged(void); #define BOOTLOADER_REQUEST() (0) #define usbBootloader() void usbInit(void); void usbStart(void); -bool usbPlugged(void); + +#ifdef __cplusplus +} #endif // EEPROM driver diff --git a/radio/src/targets/taranis/pwr_driver.cpp b/radio/src/targets/taranis/pwr_driver.c similarity index 92% rename from radio/src/targets/taranis/pwr_driver.cpp rename to radio/src/targets/taranis/pwr_driver.c index dd43832c6..43c353a6a 100644 --- a/radio/src/targets/taranis/pwr_driver.cpp +++ b/radio/src/targets/taranis/pwr_driver.c @@ -34,26 +34,8 @@ * */ -#include "../../opentx.h" - -void pwrOff() -{ - GPIO_ResetBits(GPIOPWR,PIN_MCU_PWR); -} - -uint32_t pwrCheck() -{ -#if defined(SIMU) - return e_power_on; -#else - if (GPIO_ReadInputDataBit(GPIOPWR, PIN_PWR_STATUS) == Bit_RESET) - return e_power_on; - else if (usbPlugged()) - return e_power_usb; - else - return e_power_off; -#endif -} +#include "board_taranis.h" +#include "../src/pwr.h" void pwrInit() { @@ -101,5 +83,25 @@ void pwrInit() #endif // Soft power ON - GPIO_SetBits(GPIOPWR,PIN_MCU_PWR); + GPIO_SetBits(GPIOPWR, PIN_MCU_PWR); +} + +void pwrOff() +{ + GPIO_ResetBits(GPIOPWR, PIN_MCU_PWR); +} + +// TODO enums should be UPPERCASE +uint32_t pwrCheck() +{ +#if defined(SIMU) + return e_power_on; +#else + if (GPIO_ReadInputDataBit(GPIOPWR, PIN_PWR_STATUS) == Bit_RESET) + return e_power_on; + else if (usbPlugged()) + return e_power_usb; + else + return e_power_off; +#endif } diff --git a/radio/src/targets/taranis/usb_driver.c b/radio/src/targets/taranis/usb_driver.c new file mode 100755 index 000000000..734756c09 --- /dev/null +++ b/radio/src/targets/taranis/usb_driver.c @@ -0,0 +1,59 @@ +/* + * Authors (alphabetical order) + * - Andre Bernet + * - Andreas Weitl + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Gabriel Birkus + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * opentx is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "board_taranis.h" + +int usbPlugged(void) +{ + return GPIO_ReadInputDataBit(GPIOA, PIN_FS_VBUS); +} + +USB_OTG_CORE_HANDLE USB_OTG_dev; + +void OTG_FS_IRQHandler(void) +{ + USBD_OTG_ISR_Handler (&USB_OTG_dev); +} + +void usbInit() +{ + USB_OTG_BSP_Init(&USB_OTG_dev); +} + +void usbStart() +{ + USBD_Init(&USB_OTG_dev, USB_OTG_FS_CORE_ID, &USR_desc, &USBD_MSC_cb, &USR_cb); +} From 0dbf9d8b81a51995e18e1aaf0d7da1cdfdb3450b Mon Sep 17 00:00:00 2001 From: bsongis Date: Wed, 5 Mar 2014 14:46:55 +0100 Subject: [PATCH 042/285] 5 more files removed --- radio/bootloader/Fat12.cpp | 562 -------------------------- radio/bootloader/Makefile | 3 - radio/bootloader/boot.cpp | 40 +- radio/bootloader/driversboot.cpp | 83 ---- radio/bootloader/include/drivers.h | 69 ---- radio/bootloader/include/misc.h | 178 -------- radio/bootloader/include/radio.h | 64 --- radio/bootloader/logicioboot.cpp | 377 ----------------- radio/bootloader/usbd_storage_msd.cpp | 7 +- 9 files changed, 14 insertions(+), 1369 deletions(-) delete mode 100644 radio/bootloader/Fat12.cpp delete mode 100644 radio/bootloader/driversboot.cpp delete mode 100644 radio/bootloader/include/drivers.h delete mode 100644 radio/bootloader/include/misc.h delete mode 100644 radio/bootloader/include/radio.h delete mode 100644 radio/bootloader/logicioboot.cpp diff --git a/radio/bootloader/Fat12.cpp b/radio/bootloader/Fat12.cpp deleted file mode 100644 index 44d9b2e34..000000000 --- a/radio/bootloader/Fat12.cpp +++ /dev/null @@ -1,562 +0,0 @@ -/**************************************************************************** -* Copyright (c) 2013 by Michael Blandford. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License version 2 as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* Original source of this code: Primoz Beltram -* http://sourceforge.net/projects/fat12ctrlface/files/ -* - * Other Authors (alphabetical order) - * - Andre Bernet - * - Andreas Weitl - * - Bertrand Songis - * - Bryan J. Rentoul (Gruvin) - * - Cameron Weeks - * - Erez Raviv - * - Gabriel Birkus - * - Jean-Pierre Parisy - * - Karl Szmutny - * - Michal Hlavinka - * - Pat Mackenzie - * - Philip Moss - * - Rob Thomson - * - Romolo Manfredini - * - Thomas Husterer -* -****************************************************************************/ - - - -#include -#include "string.h" -//#include "myeeprom.h" -#include "file.h" - -#define BLOCKSIZE 512 - -//------------------------------------------------------------------------------ -/** - * FAT12 boot sector partition. - */ -const char g_FATboot[BLOCKSIZE] = { - // See http://en.wikipedia.org/wiki/FAT12#Boot_Sector - 0xeb, 0x3c, 0x90, // Jump instruction. - 0x39, 0x58, 0x20, 0x54, 0x45, 0x41, 0x4D, 0x00, // OEM Name - 0x00, 0x02, // Bytes per sector - 0x08, // Sectors per FS cluster. - 0x01, 0x00, // Reserved sector count - - 0x01, // Number of FATs - 0x10, 0x00, // Number of root directory entries -#ifdef REVX - 0x03, 0x08, // Total sectors = 2051 -#else - 0x03, 0x06, // Total sectors = 1539 -#endif - 0xf8, // Media descriptor - 0x01, 0x00, // Sectors per FAT table - 0x08, 0x00, // Sectors per track - 0x40, 0x00, // Number of heads - 0x00, 0x00, 0x00, 0x00, // Number of hidden sectors - - 0x00, 0x00, 0x00, 0x00, // Large number of sectors. - 0x00, // Physical drive number - 0x00, // Reserved - 0x29, // Extended boot signature - 0xCE, 0xFA, 0x5C, 0xD1, // Disk ID (serial number) - 0x56, 0x49, 0x52, 0x54, 0x46, 0x53, 0x20, 0x20, 0x20, 0x20, 0x20, // Volume label - 0x46, 0x41, 0x54, 0x31, 0x32, 0x20, 0x20, 0x20, // FAT file system type - 0x00, 0x00, // OS boot code - - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0xaa -}; - -const char g_FAT[BLOCKSIZE] = -{ -#ifdef REVX - 0xF8, 0xFF, 0xFF, 0x03, 0x40, 0x00, 0x05, 0x60, 0x00, 0x07, 0x80, 0x00, 0x09, 0xA0, 0x00, 0x0B, - 0xC0, 0x00, 0x0D, 0xE0, 0x00, 0x0F, 0x00, 0x01, 0x11, 0x20, 0x01, 0x13, 0x40, 0x01, 0x15, 0x60, - 0x01, 0x17, 0x80, 0x01, 0x19, 0xA0, 0x01, 0x1B, 0xC0, 0x01, 0x1D, 0xE0, 0x01, 0x1F, 0x00, 0x02, - 0x21, 0x20, 0x02, 0x23, 0x40, 0x02, 0x25, 0x60, 0x02, 0x27, 0x80, 0x02, 0x29, 0xA0, 0x02, 0x2B, - 0xC0, 0x02, 0x2D, 0xE0, 0x02, 0x2F, 0x00, 0x03, 0x31, 0x20, 0x03, 0x33, 0x40, 0x03, 0x35, 0x60, - 0x03, 0x37, 0x80, 0x03, 0x39, 0xA0, 0x03, 0x3B, 0xC0, 0x03, 0x3D, 0xE0, 0x03, 0x3F, 0x00, 0x04, - 0x41, 0x20, 0x04, 0x43, 0x40, 0x04, 0x45, 0x60, 0x04, 0x47, 0x80, 0x04, 0x49, 0xA0, 0x04, 0x4B, - 0xC0, 0x04, 0x4D, 0xE0, 0x04, 0x4F, 0x00, 0x05, 0x51, 0x20, 0x05, 0x53, 0x40, 0x05, 0x55, 0x60, - 0x05, 0x57, 0x80, 0x05, 0x59, 0xA0, 0x05, 0x5B, 0xC0, 0x05, 0x5D, 0xE0, 0x05, 0x5F, 0x00, 0x06, - 0x61, 0x20, 0x06, 0x63, 0x40, 0x06, 0x65, 0x60, 0x06, 0x67, 0x80, 0x06, 0x69, 0xA0, 0x06, 0x6B, - 0xC0, 0x06, 0x6D, 0xE0, 0x06, 0x6F, 0x00, 0x07, 0x71, 0x20, 0x07, 0x73, 0x40, 0x07, 0x75, 0x60, - 0x07, 0x77, 0x80, 0x07, 0x79, 0xA0, 0x07, 0x7B, 0xC0, 0x07, 0x7D, 0xE0, 0x07, 0x7F, 0x00, 0x08, - 0x81, 0xF0, 0xFF, 0x83, 0x40, 0x08, 0x85, 0x60, 0x08, 0x87, 0x80, 0x08, 0x89, 0xA0, 0x08, 0x8B, - 0xC0, 0x08, 0x8D, 0xE0, 0x08, 0x8F, 0x00, 0x09, 0x91, 0x20, 0x09, 0x93, 0x40, 0x09, 0x95, 0x60, - 0x09, 0x97, 0x80, 0x09, 0x99, 0xA0, 0x09, 0x9B, 0xC0, 0x09, 0x9D, 0xE0, 0x09, 0x9F, 0x00, 0x0A, - 0xA1, 0x20, 0x0A, 0xA3, 0x40, 0x0A, 0xA5, 0x60, 0x0A, 0xA7, 0x80, 0x0A, 0xA9, 0xA0, 0x0A, 0xAB, - 0xC0, 0x0A, 0xAD, 0xE0, 0x0A, 0xAF, 0x00, 0x0B, 0xB1, 0x20, 0x0B, 0xB3, 0x40, 0x0B, 0xB5, 0x60, - 0x0B, 0xB7, 0x80, 0x0B, 0xB9, 0xA0, 0x0B, 0xBB, 0xC0, 0x0B, 0xBD, 0xE0, 0x0B, 0xBF, 0x00, 0x0C, - 0xC1, 0x20, 0x0C, 0xC3, 0x40, 0x0C, 0xC5, 0x60, 0x0C, 0xC7, 0x80, 0x0C, 0xC9, 0xA0, 0x0C, 0xCB, - 0xC0, 0x0C, 0xCD, 0xE0, 0x0C, 0xCF, 0x00, 0x0D, 0xD1, 0x20, 0x0D, 0xD3, 0x40, 0x0D, 0xD5, 0x60, - 0x0D, 0xD7, 0x80, 0x0D, 0xD9, 0xA0, 0x0D, 0xDB, 0xC0, 0x0D, 0xDD, 0xE0, 0x0D, 0xDF, 0x00, 0x0E, - 0xE1, 0x20, 0x0E, 0xE3, 0x40, 0x0E, 0xE5, 0x60, 0x0E, 0xE7, 0x80, 0x0E, 0xE9, 0xA0, 0x0E, 0xEB, - 0xC0, 0x0E, 0xED, 0xE0, 0x0E, 0xEF, 0x00, 0x0F, 0xF1, 0x20, 0x0F, 0xF3, 0x40, 0x0F, 0xF5, 0x60, - 0x0F, 0xF7, 0x80, 0x0F, 0xF9, 0xA0, 0x0F, 0xFB, 0xC0, 0x0F, 0xFD, 0xE0, 0x0F, 0xFF, 0x00, 0x10, - 0x01, 0xF1, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -#else - 0xF8, 0xFF, 0xFF, 0x03, 0x40, 0x00, 0x05, 0x60, 0x00, 0x07, 0x80, 0x00, 0x09, 0xA0, 0x00, 0x0B, - 0xC0, 0x00, 0x0D, 0xE0, 0x00, 0x0F, 0x00, 0x01, 0x11, 0x20, 0x01, 0x13, 0x40, 0x01, 0x15, 0x60, - 0x01, 0x17, 0x80, 0x01, 0x19, 0xA0, 0x01, 0x1B, 0xC0, 0x01, 0x1D, 0xE0, 0x01, 0x1F, 0x00, 0x02, - 0x21, 0x20, 0x02, 0x23, 0x40, 0x02, 0x25, 0x60, 0x02, 0x27, 0x80, 0x02, 0x29, 0xA0, 0x02, 0x2B, - 0xC0, 0x02, 0x2D, 0xE0, 0x02, 0x2F, 0x00, 0x03, 0x31, 0x20, 0x03, 0x33, 0x40, 0x03, 0x35, 0x60, - 0x03, 0x37, 0x80, 0x03, 0x39, 0xA0, 0x03, 0x3B, 0xC0, 0x03, 0x3D, 0xE0, 0x03, 0x3F, 0x00, 0x04, - 0x41, 0x20, 0x04, 0x43, 0x40, 0x04, 0x45, 0x60, 0x04, 0x47, 0x80, 0x04, 0x49, 0xA0, 0x04, 0x4B, - 0xC0, 0x04, 0x4D, 0xE0, 0x04, 0x4F, 0x00, 0x05, 0x51, 0x20, 0x05, 0x53, 0x40, 0x05, 0x55, 0x60, - 0x05, 0x57, 0x80, 0x05, 0x59, 0xA0, 0x05, 0x5B, 0xC0, 0x05, 0x5D, 0xE0, 0x05, 0x5F, 0x00, 0x06, - 0x61, 0x20, 0x06, 0x63, 0x40, 0x06, 0x65, 0x60, 0x06, 0x67, 0x80, 0x06, 0x69, 0xA0, 0x06, 0x6B, - 0xC0, 0x06, 0x6D, 0xE0, 0x06, 0x6F, 0x00, 0x07, 0x71, 0x20, 0x07, 0x73, 0x40, 0x07, 0x75, 0x60, - 0x07, 0x77, 0x80, 0x07, 0x79, 0xA0, 0x07, 0x7B, 0xC0, 0x07, 0x7D, 0xE0, 0x07, 0x7F, 0x00, 0x08, - 0x81, 0xF0, 0xFF, 0x83, 0x40, 0x08, 0x85, 0x60, 0x08, 0x87, 0x80, 0x08, 0x89, 0xA0, 0x08, 0x8B, - 0xC0, 0x08, 0x8D, 0xE0, 0x08, 0x8F, 0x00, 0x09, 0x91, 0x20, 0x09, 0x93, 0x40, 0x09, 0x95, 0x60, - 0x09, 0x97, 0x80, 0x09, 0x99, 0xA0, 0x09, 0x9B, 0xC0, 0x09, 0x9D, 0xE0, 0x09, 0x9F, 0x00, 0x0A, - 0xA1, 0x20, 0x0A, 0xA3, 0x40, 0x0A, 0xA5, 0x60, 0x0A, 0xA7, 0x80, 0x0A, 0xA9, 0xA0, 0x0A, 0xAB, - 0xC0, 0x0A, 0xAD, 0xE0, 0x0A, 0xAF, 0x00, 0x0B, 0xB1, 0x20, 0x0B, 0xB3, 0x40, 0x0B, 0xB5, 0x60, - 0x0B, 0xB7, 0x80, 0x0B, 0xB9, 0xA0, 0x0B, 0xBB, 0xC0, 0x0B, 0xBD, 0xE0, 0x0B, 0xBF, 0x00, 0x0C, - 0xC1, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -#endif -}; - - -// File Attributes -// 0 0x01 Read Only. -// 1 0x02 Hidden. -// 2 0x04 System. -// 3 0x08 Volume Label. -// 4 0x10 Subdirectory. -// 5 0x20 Archive. -// 6 0x40 Device. -// 7 0x80 Reserved. - -typedef struct -{ - uint8_t name[8]; - uint8_t ext[3]; - uint8_t attribute; - uint8_t reserved; - uint8_t create_time_ms; - uint16_t create_time; - uint16_t create_date; - uint16_t access_date; - uint16_t ea_index; - uint16_t modify_time; - uint16_t modify_date; - uint16_t start_cluster; - uint32_t file_size; -} FATDirEntry_t; - -// First 16 FAT root directory entries (1 sector) -const FATDirEntry_t g_DIRroot[16] = -{ - { - { 'E', 'R', 'S', 'K', 'Y', '_', '9', 'X'}, - { ' ', ' ', ' '}, - 0x08, // Volume - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - }, - { - { 'E', 'R', 'S', 'K', 'Y', '9', 'X', ' '}, - { 'B', 'I', 'N'}, - 0x26, // Archive, hidden, system, read-only - 0x00, - 0x3E, - 0xA301, - 0x3D55, - 0x3D55, - 0x0000, - 0xA302, - 0x3D55, - 0x0002, - 0x00080000 - }, - { - { 'F', 'I', 'R', 'M', 'W', 'A', 'R', 'E'}, - { 'B', 'I', 'N'}, - 0x26, - 0x00, - 0x3E, - 0xA301, - 0x3D55, - 0x3D55, - 0x0000, - 0xA302, - 0x3D55, - 0x0082, -#ifdef REVX - 0x00080000 -#else - 0x00040000 -#endif - }, - { - { 'A', '2', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x27, - 0x00, - 0x3E, - 0xA301, - 0x3D55, - 0x3D55, - 0x0000, - 0xA302, - 0x3D55, - 0x0000, - 0x00000000 - }, - { - { 'A', '3', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x27, - 0x00, - 0x3E, - 0xA301, - 0x3D55, - 0x3D55, - 0x0000, - 0xA302, - 0x3D55, - 0x0000, - 0x00000000 - }, - { - { 'A', '4', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x27, - 0x00, - 0x3E, - 0xA301, - 0x3D55, - 0x3D55, - 0x0000, - 0xA302, - 0x3D55, - 0x0000, - 0x00000000 - }, - { - { 'A', '5', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x27, - 0x00, - 0x3E, - 0xA301, - 0x3D55, - 0x3D55, - 0x0000, - 0xA302, - 0x3D55, - 0x0000, - 0x00000000 - }, - { - { 'A', '6', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x27, - 0x00, - 0x3E, - 0xA301, - 0x3D55, - 0x3D55, - 0x0000, - 0xA302, - 0x3D55, - 0x0000, - 0x00000000 - }, - { - { 'A', '7', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x27, - 0x00, - 0x3E, - 0xA301, - 0x3D55, - 0x3D55, - 0x0000, - 0xA302, - 0x3D55, - 0x0000, - 0x00000000 - }, - { - { 'A', '8', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x27, - 0x00, - 0x3E, - 0xA301, - 0x3D55, - 0x3D55, - 0x0000, - 0xA302, - 0x3D55, - 0x0000, - 0x00000000 - }, - { - { 'A', '9', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x27, - 0x00, - 0x3E, - 0xA301, - 0x3D55, - 0x3D55, - 0x0000, - 0xA302, - 0x3D55, - 0x0000, - 0x00000000 - }, - { - { 'A', 'A', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x27, - 0x00, - 0x3E, - 0xA301, - 0x3D55, - 0x3D55, - 0x0000, - 0xA302, - 0x3D55, - 0x0000, - 0x00000000 - }, - { - { 'A', 'B', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x27, - 0x00, - 0x3E, - 0xA301, - 0x3D55, - 0x3D55, - 0x0000, - 0xA302, - 0x3D55, - 0x0000, - 0x00000000 - }, - { - { 'A', 'C', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x27, - 0x00, - 0x3E, - 0xA301, - 0x3D55, - 0x3D55, - 0x0000, - 0xA302, - 0x3D55, - 0x0000, - 0x00000000 - }, - { - { '\0', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x00, - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - }, -// { -// { 'A', 'E', ' ', ' ', ' ', ' ', ' ', ' '}, -// { ' ', ' ', ' '}, -// 0x27, -// 0x00, -// 0x3E, -// 0xA301, -// 0x3D55, -// 0x3D55, -// 0x0000, -// 0xA302, -// 0x3D55, -// 0x0000, -// 0x00000000 -// } - { - { '\0', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x00, - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - } -}; - - -int fat12Read( uint8_t *buffer, uint16_t sector ) -{ - if (sector == 0) - { - memcpy( buffer, g_FATboot, BLOCKSIZE ) ; - return TRUE; - } - else if ( sector == 1/*Reserved sector count*/) - { - // FAT table. - memcpy( buffer, g_FAT, BLOCKSIZE); - return TRUE; - } - else if ( sector == 2) - { - // Directory - memcpy( buffer, g_DIRroot, BLOCKSIZE ) ; - return TRUE; - } - - sector -= 3 ; - if ( sector < 1024 ) - { - ee32_read_512( sector, buffer ) ; - } -#ifdef REVX - else if ( sector < 2048 ) -#else - else if ( sector < 1536 ) -#endif - { - uint32_t address ; - address = sector - 1024 ; - address *= 512 ; - address += 0x00400000 ; - memcpy( buffer, (uint8_t *)address, BLOCKSIZE ) ; - } - else - { - memset( buffer, 0, BLOCKSIZE ) ; - } - return TRUE; -} - - -uint32_t program( uint32_t *address, uint32_t *buffer ) ; // size is 256 bytes -uint32_t ee32_write( const uint8_t *buffer, uint32_t sector, uint32_t count ) ; - -int fat12Write( const uint8_t *buffer, uint16_t sector, uint32_t count ) -{ - // TO DO, actually write to the EEPROM - if ( sector >= 3 ) - { - sector -= 3 ; - // Look for a 4K block boundary, writing 4K+ - if ( sector < 1024 ) - { - ee32_write( buffer, sector, count ) ; - } -#ifdef REVX - else if ( sector < 2048 ) -#else - else if ( sector < 1536 ) -#endif - { - // FIRMWARE - uint32_t address ; - address = sector - 1024 ; - address *= 512 ; - address += 0x00400000 ; - // Write to flash - uint32_t i ; - while ( count ) - { - for ( i = 0 ; i < 2 ; i += 1 ) - { - if ( address >= 0x00408000 ) // Protect bootloader - { - program( (uint32_t *)address, (uint32_t *) buffer ) ; // size is 256 bytes - } - address += 256 ; - buffer += 256 ; - } - count -= 1 ; - } - } - } - return TRUE; -} - - diff --git a/radio/bootloader/Makefile b/radio/bootloader/Makefile index f67923ab8..d756d8518 100644 --- a/radio/bootloader/Makefile +++ b/radio/bootloader/Makefile @@ -98,7 +98,6 @@ else CPPDEFS += -DHSE_VALUE=12000000 CPPDEFS += -DPCBTARANIS FULL_PRJ = $(PROJECT)_ramBoot - EXTRAINCDIRS += include EXTRAINCDIRS += ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc EXTRAINCDIRS += ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include EXTRAINCDIRS += ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/inc @@ -143,8 +142,6 @@ SRC = system_stm32f2xx.c \ CPPSRC = ../src/targets/taranis/lcd_driver.cpp \ ../src/targets/taranis/keys_driver.cpp \ - driversboot.cpp \ - logicioboot.cpp \ ../src/targets/taranis/diskio.cpp \ ../src/targets/taranis/usbd_usr.cpp \ usbd_storage_msd.cpp \ diff --git a/radio/bootloader/boot.cpp b/radio/bootloader/boot.cpp index b4c39a97d..91f0f94e4 100644 --- a/radio/bootloader/boot.cpp +++ b/radio/bootloader/boot.cpp @@ -75,31 +75,14 @@ extern "C" { #include "../src/lcd.h" #include "../src/keys.h" -// #include "radio.h" #include "../src/FatFs/ff.h" #include "../src/FatFs/diskio.h" -//#include "drivers.h" -// #include "logicio.h" - -#ifdef PCBSKY -extern void usbMassStorage( void ) ; -#endif - -#ifdef PCBSKY -#define BOOT_KEY_UP KEY_UP -#define BOOT_KEY_DOWN KEY_DOWN -#define BOOT_KEY_LEFT KEY_LEFT -#define BOOT_KEY_RIGHT KEY_RIGHT -#define BOOT_KEY_MENU KEY_MENU -#define BOOT_KEY_EXIT KEY_EXIT -#define DISPLAY_CHAR_WIDTH 21 -#endif #ifdef PCBTARANIS -#define BOOT_KEY_UP KEY_PLUS +#define BOOT_KEY_UP KEY_PLUS #define BOOT_KEY_DOWN KEY_MINUS #define BOOT_KEY_LEFT KEY_MENU -#define BOOT_KEY_RIGHT KEY_PAGE +#define BOOT_KEY_RIGHT KEY_PAGE #define BOOT_KEY_MENU KEY_ENTER #define BOOT_KEY_EXIT KEY_EXIT #define DISPLAY_CHAR_WIDTH 35 @@ -117,10 +100,6 @@ extern void usbMassStorage( void ) ; #define ST_REBOOT 11 - - - - /*---------------------------------------------------------------------------- * Local variables *----------------------------------------------------------------------------*/ @@ -131,8 +110,6 @@ uint32_t Master_frequency ; volatile uint8_t Tenms ; uint8_t EE_timer ; -extern uint32_t sd_card_ready( void ) ; - TCHAR FlashFilename[60] ; FATFS g_FATFS ; FIL FlashFile ; @@ -325,11 +302,18 @@ void clearLockBits() } #endif -void per10ms(void); void interrupt10ms(void) { - Tenms |= 1 ; // 10 mS has passed - per10ms() ; + Tenms |= 1 ; // 10 mS has passed + + uint8_t enuk = KEY_MENU; + uint8_t in = ~readKeys(); + + for (int i=1; i<7; i++) { + uint8_t value = in & (1< - * - * Based on th9x -> http://code.google.com/p/th9x/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - - - -#include -#include - -#include "../src/opentx.h" - -void per10ms(void) -{ - register uint32_t i ; - - uint8_t enuk = KEY_MENU; - uint8_t in = ~readKeys() ; - // Bits 3-6 are down, up, right and left - // Try to only allow one at a -#ifdef REVX - static uint8_t current ; - uint8_t dir_keys ; - uint8_t lcurrent ; - - dir_keys = in & 0x78 ; // Mask to direction keys - if ( ( lcurrent = current ) ) - { // Something already pressed - if ( ( lcurrent & dir_keys ) == 0 ) - { - lcurrent = 0 ; // No longer pressed - } - else - { - in &= lcurrent | 0x06 ; // current or MENU or EXIT allowed - } - } - if ( lcurrent == 0 ) - { // look for a key - if ( dir_keys & 0x20 ) // right - { - lcurrent = 0x60 ; // Allow L and R for 9X - } - else if ( dir_keys & 0x40 ) // left - { - lcurrent = 0x60 ; // Allow L and R for 9X - } - else if ( dir_keys & 0x08 ) // down - { - lcurrent = 0x08 ; - } - else if ( dir_keys & 0x10 ) // up - { - lcurrent = 0x10 ; - } - in &= lcurrent | 0x06 ; // current or MENU or EXIT allowed - } - current = lcurrent ; -#endif - - for( i=1; i<7; i++) - { - uint8_t value = in & (1<PIO_PDSR & PIO_PB7) == 0 ) -#endif - -extern uint32_t Card_ID[4] ; -extern uint32_t Card_SCR[2] ; -extern uint32_t Card_CSD[4] ; -extern uint32_t Sd_128_resp[4] ; -extern uint32_t Sd_rca ; -//extern uint32_t Cmd_55_resp ; - -extern uint32_t Card_state ; - -extern uint32_t SD_SetBusWidth( uint32_t busWidth) ; -extern void SD_EnableHsMode( uint8_t hsEnable) ; -extern uint32_t SD_SetSpeed( uint32_t mciSpeed ) ; -extern void SD_Reset( uint8_t keepSettings) ; -extern uint32_t sd_cmd55( void ) ; -extern uint32_t sd_acmd41( void ) ; -extern uint32_t sd_cmd2( void ) ; -extern uint32_t sd_cmd3( void ) ; -extern uint32_t sd_cmd7( void ) ; -extern uint32_t sd_cmd9( void ) ; -extern uint32_t sd_cmd17( uint32_t address, uint32_t *presult ) ; -extern uint32_t sd_acmd6( void ) ; -extern uint32_t sd_acmd51( uint32_t *presult ) ; -extern void sd_poll_10mS( void ) ; -extern uint32_t sd_card_ready( void ) ; -extern uint32_t sd_read_block( uint32_t block_no, uint32_t *data ) ; - -class Key -{ -#define FILTERBITS 4 -#define FFVAL ((1<
© COPYRIGHT 2012 STMicroelectronics
- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MISC_H -#define __MISC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup MISC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief NVIC Init Structure definition - */ - -typedef struct -{ - uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. - This parameter can be an enumerator of @ref IRQn_Type - enumeration (For the complete STM32 Devices IRQ Channels - list, please refer to stm32f2xx.h file) */ - - uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel - specified in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table - A lower priority value indicates a higher priority */ - - uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified - in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table - A lower priority value indicates a higher priority */ - - FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel - will be enabled or disabled. - This parameter can be set either to ENABLE or DISABLE */ -} NVIC_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup MISC_Exported_Constants - * @{ - */ - -/** @defgroup MISC_Vector_Table_Base - * @{ - */ - -#define NVIC_VectTab_RAM ((uint32_t)0x20000000) -#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) -#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ - ((VECTTAB) == NVIC_VectTab_FLASH)) -/** - * @} - */ - -/** @defgroup MISC_System_Low_Power - * @{ - */ - -#define NVIC_LP_SEVONPEND ((uint8_t)0x10) -#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) -#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) -#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ - ((LP) == NVIC_LP_SLEEPDEEP) || \ - ((LP) == NVIC_LP_SLEEPONEXIT)) -/** - * @} - */ - -/** @defgroup MISC_Preemption_Priority_Group - * @{ - */ - -#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority - 4 bits for subpriority */ -#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority - 3 bits for subpriority */ -#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority - 2 bits for subpriority */ -#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority - 1 bits for subpriority */ -#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority - 0 bits for subpriority */ - -#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ - ((GROUP) == NVIC_PriorityGroup_1) || \ - ((GROUP) == NVIC_PriorityGroup_2) || \ - ((GROUP) == NVIC_PriorityGroup_3) || \ - ((GROUP) == NVIC_PriorityGroup_4)) - -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) - -/** - * @} - */ - -/** @defgroup MISC_SysTick_clock_source - * @{ - */ - -#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) -#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ - ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); - -#ifdef __cplusplus -} -#endif - -#endif /* __MISC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/include/radio.h b/radio/bootloader/include/radio.h deleted file mode 100644 index afc5e5b46..000000000 --- a/radio/bootloader/include/radio.h +++ /dev/null @@ -1,64 +0,0 @@ - - -#include - -#ifdef PCBSKY -#define wdt_reset() (WDT->WDT_CR = 0xA5000001) -#endif -#ifdef PCBTARANIS -#define wdt_reset() (IWDG->KR = 0x0000AAAAL) -#endif - -#define POWER_OFF 0 -#define POWER_ON 1 - -#define DIM(arr) (sizeof((arr))/sizeof((arr)[0])) - -#define BITMASK(bit) (1<<(bit)) - -#define _MSK_KEY_REPT 0x40 -#define _MSK_KEY_DBL 0x10 -#define IS_KEY_BREAK(key) (((key)&0xf0) == 0x20) -#define EVT_KEY_BREAK(key) ((key)| 0x20) -#define EVT_KEY_FIRST(key) ((key)| _MSK_KEY_REPT|0x20) -#define EVT_KEY_REPT(key) ((key)| _MSK_KEY_REPT ) -#define EVT_KEY_LONG(key) ((key)|0x80) -#define EVT_KEY_DBL(key) ((key)|_MSK_KEY_DBL) -//#define EVT_KEY_DBL(key) ((key)|0x10) -#define EVT_ENTRY (0xff - _MSK_KEY_REPT) -#define EVT_ENTRY_UP (0xfe - _MSK_KEY_REPT) -#define EVT_KEY_MASK 0x0f - - -#define NUM_KEYS 6 - -#ifdef PCBSKY -enum EnumKeys { - KEY_MENU , - KEY_EXIT , - KEY_DOWN , - KEY_UP , - KEY_RIGHT , - KEY_LEFT -} ; -#endif - -#ifdef PCBTARANIS -enum EnumKeys { - KEY_MENU , - KEY_EXIT , - KEY_ENTER , - KEY_PAGE , - KEY_PLUS , - KEY_MINUS -} ; -#endif - -extern void init_SDcard( void ) ; -extern unsigned long Master_frequency ; - -extern void init_soft_power( void ) ; -extern uint32_t check_soft_power( void ) ; -extern void soft_power_off( void ) ; - - diff --git a/radio/bootloader/logicioboot.cpp b/radio/bootloader/logicioboot.cpp deleted file mode 100644 index cc3df751a..000000000 --- a/radio/bootloader/logicioboot.cpp +++ /dev/null @@ -1,377 +0,0 @@ -/**************************************************************************** -* Copyright (c) 2012 by Michael Blandford. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License version 2 as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* -****************************************************************************/ - -#include -#include -#include -#include - - -#ifdef PCBSKY -#include "AT91SAM3S4.h" -#include "radio.h" -#include "drivers.h" -#endif - -#include "../src/opentx.h" - - -#ifndef SIMU -#ifdef PCBSKY -void configure_pins( uint32_t pins, uint16_t config ) -{ - register Pio *pioptr ; - - pioptr = PIOA + ( ( config & PIN_PORT_MASK ) >> 6) ; - if ( config & PIN_PULLUP ) - { - pioptr->PIO_PPDDR = pins ; - pioptr->PIO_PUER = pins ; - } - else - { - pioptr->PIO_PUDR = pins ; - } - - if ( config & PIN_PULLDOWN ) - { - pioptr->PIO_PUDR = pins ; - pioptr->PIO_PPDER = pins ; - } - else - { - pioptr->PIO_PPDDR = pins ; - } - - if ( config & PIN_HIGH ) - { - pioptr->PIO_SODR = pins ; - } - else - { - pioptr->PIO_CODR = pins ; - } - - if ( config & PIN_INPUT ) - { - pioptr->PIO_ODR = pins ; - } - else - { - pioptr->PIO_OER = pins ; - } - - if ( config & PIN_PERI_MASK_L ) - { - pioptr->PIO_ABCDSR[0] |= pins ; - } - else - { - pioptr->PIO_ABCDSR[0] &= ~pins ; - } - if ( config & PIN_PERI_MASK_H ) - { - pioptr->PIO_ABCDSR[1] |= pins ; - } - else - { - pioptr->PIO_ABCDSR[1] &= ~pins ; - } - - if ( config & PIN_ENABLE ) - { - pioptr->PIO_PER = pins ; - } - else - { - pioptr->PIO_PDR = pins ; - } -} -#endif - - -#ifdef PCBTARANIS -void configure_pins( uint32_t pins, uint16_t config ) -{ - uint32_t address ; - GPIO_TypeDef *pgpio ; - uint32_t thispin ; - uint32_t pos ; - - address = ( config & PIN_PORT_MASK ) >> 8 ; - address *= (GPIOB_BASE-GPIOA_BASE) ; - address += GPIOA_BASE ; - pgpio = (GPIO_TypeDef* ) address ; - - /* -------------------------Configure the port pins---------------- */ - /*-- GPIO Mode Configuration --*/ - for (thispin = 0x0001, pos = 0; thispin < 0x10000; thispin <<= 1, pos +=1 ) - { - if ( pins & thispin) - { - pgpio->MODER &= ~(GPIO_MODER_MODER0 << (pos * 2)) ; - pgpio->MODER |= (config & PIN_MODE_MASK) << (pos * 2) ; - - if ( ( (config & PIN_MODE_MASK ) == PIN_OUTPUT) || ( (config & PIN_MODE_MASK) == PIN_PERIPHERAL) ) - { - /* Speed mode configuration */ - pgpio->OSPEEDR &= ~GPIO_OSPEEDER_OSPEEDR0 << (pos * 2) ; - pgpio->OSPEEDR |= ((config & PIN_SPEED_MASK) >> 13 ) << (pos * 2) ; - - /* Output mode configuration*/ - pgpio->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pos)) ; - if ( config & PIN_ODRAIN ) - { - pgpio->OTYPER |= (GPIO_OTYPER_OT_0) << pos ; - } - } - /* Pull-up Pull down resistor configuration*/ - pgpio->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pos * 2)); - pgpio->PUPDR |= ((config & PIN_PULL_MASK) >> 2) << (pos * 2) ; - - pgpio->AFR[pos >> 3] &= ~(0x000F << ((pos & 7)*4)) ; - pgpio->AFR[pos >> 3] |= ((config & PIN_PERI_MASK) >> 4) << ((pos & 7)*4) ; - } - } -} - -#endif - - - -#ifdef PCBSKY - -void init_keys() -{ - register Pio *pioptr ; - - pioptr = PIOC ; - // Next section configures the key inputs on the LCD data - pioptr->PIO_PER = 0x0000003BL ; // Enable bits 1,3,4,5, 0 - pioptr->PIO_OER = PIO_PC0 ; // Set bit 0 output - pioptr->PIO_ODR = 0x0000003AL ; // Set bits 1, 3, 4, 5 input - pioptr->PIO_PUER = 0x0000003AL ; // Set bits 1, 3, 4, 5 with pullups - - pioptr = PIOB ; - pioptr->PIO_PUER = PIO_PB5 ; // Enable pullup on bit B5 (MENU) - pioptr->PIO_PER = PIO_PB5 ; // Enable bit B5 -} - -// Assumes PMC has already enabled clocks to ports -void setup_switches() -{ - configure_pins( 0x01808087, PIN_ENABLE | PIN_INPUT | PIN_PORTA | PIN_PULLUP ) ; - configure_pins( 0x00000030, PIN_ENABLE | PIN_INPUT | PIN_PORTB | PIN_PULLUP ) ; - configure_pins( 0x91114900, PIN_ENABLE | PIN_INPUT | PIN_PORTC | PIN_PULLUP ) ; -} - - -// Switch input pins -// Needs updating for REVB board ******** -// AIL-DR PA2 -// TRIM_LH_DOWN PA7 (PA23) -// ELE_DR PA8 (PC31) -// RUN_DR PA15 -// TRIM_LV_DOWN PA27 (PA24) -// SW_TCUT PA28 (PC20) -// TRIM_RH_DOWN PA29 (PA0) -// TRIM_RV_UP PA30 (PA1) -// TRIM_LH_UP //PB4 -// SW-TRAIN PC8 -// TRIM_RH_UP PC9 -// TRIM_RV_DOWN PC10 -// SW_IDL2 PC11 -// SW_IDL1 PC14 -// SW_GEAR PC16 -// TRIM_LV_UP PC28 - -// KEY_MENU PB6 (PB5) -// KEY_EXIT PA31 (PC24) -// Shared with LCD data -// KEY_DOWN LCD5 PC3 -// KEY_UP LCD6 PC2 -// KEY_RIGHT LCD4 PC4 -// KEY_LEFT LCD3 PC5 - -// PORTA 1111 1000 0000 0000 1000 0001 1000 0100 = 0xF8008184 proto -// PORTA 0000 0001 1000 0000 1000 0000 0000 0111 = 0x01808087 REVB -// PORTB 0000 0000 0001 0000 = 0x0010 proto -// PORTB 0000 0000 0010 0000 = 0x0030 REVB -// PORTC 0001 0000 0000 0001 0100 1001 0000 0000 = 0x10014900 proto -// PORTC 1001 0001 0001 0001 0100 1001 0000 0000 = 0x91114900 REVB - - -// Prototype -// Free pins (PA16 is stock buzzer) -// PA23, PA24, PA25, PB7, PB13 -// PC20, PC21(labelled 17), PC22, PC24 -// REVB -// PA25, use for stock buzzer -// PB14, PB6 -// PC21, PC19, PC15 (PPM2 output) -void config_free_pins() -{ - - configure_pins( PIO_PB14, PIN_ENABLE | PIN_INPUT | PIN_PORTB | PIN_PULLUP ) ; - -} - -#endif - -#endif // ndef BOOT - -// keys: -// KEY_EXIT PA31 (PC24) -// KEY_MENU PB6 (PB5) -// KEY_DOWN LCD5 PC3 (PC5) -// KEY_UP LCD6 PC2 (PC1) -// KEY_RIGHT LCD4 PC4 (PC4) -// KEY_LEFT LCD3 PC5 (PC3) -// Reqd. bit 6 LEFT, 5 RIGHT, 4 UP, 3 DOWN 2 EXIT 1 MENU -// LCD pins 5 DOWN, 4 RIGHT, 3 LEFT, 1 UP -#ifdef PCBSKY -uint32_t read_keys() -{ - register uint32_t x ; - register uint32_t y ; - - x = LcdLock ? LcdInputs : PIOC->PIO_PDSR << 1 ; // 6 LEFT, 5 RIGHT, 4 DOWN, 3 UP () - - y = x & 0x00000020 ; // RIGHT - if ( x & 0x00000004 ) - { - y |= 0x00000010 ; // UP - } - if ( x & 0x00000010 ) - { - y |= 0x00000040 ; // LEFT - } - if ( x & 0x00000040 ) - { - y |= 0x00000008 ; // DOWN - } - - if ( PIOC->PIO_PDSR & 0x01000000 ) - { - y |= 4 ; // EXIT - } - if ( PIOB->PIO_PDSR & 0x000000020 ) - { - y |= 2 ; // MENU - } - return y ; -} -#endif - -#ifdef PCBSKY -uint32_t read_trims() -{ - uint32_t trims ; - uint32_t trima ; - - trims = 0 ; - - trima = PIOA->PIO_PDSR ; -// TRIM_LH_DOWN PA7 (PA23) -#ifndef REVX - if ( ( trima & 0x00800000 ) == 0 ) -#else - if ( ( PIOB->PIO_PDSR & 0x10 ) == 0 ) -#endif - { - trims |= 1 ; - } - -// TRIM_LV_DOWN PA27 (PA24) - if ( ( trima & 0x01000000 ) == 0 ) - { - trims |= 4 ; - } - -// TRIM_RV_UP PA30 (PA1) -#ifndef REVX - if ( ( trima & 0x00000002 ) == 0 ) -#else - if ( ( PIOC->PIO_PDSR & 0x00000400 ) == 0 ) -#endif - { - trims |= 0x20 ; - } - -// TRIM_RH_DOWN PA29 (PA0) - if ( ( trima & 0x00000001 ) == 0 ) - { - trims |= 0x40 ; - } - -// TRIM_LH_UP PB4 -#ifndef REVX - if ( ( PIOB->PIO_PDSR & 0x10 ) == 0 ) -#else - if ( ( trima & 0x00800000 ) == 0 ) -#endif - { - trims |= 2 ; - } - - trima = PIOC->PIO_PDSR ; -// TRIM_LV_UP PC28 - if ( ( trima & 0x10000000 ) == 0 ) - { - trims |= 8 ; - } - -// TRIM_RV_DOWN PC10 -#ifndef REVX - if ( ( trima & 0x00000400 ) == 0 ) -#else - if ( ( PIOA->PIO_PDSR & 0x00000002 ) == 0 ) -#endif - { - trims |= 0x10 ; - } - -// TRIM_RH_UP PC9 - if ( ( trima & 0x00000200 ) == 0 ) - { - trims |= 0x80 ; - } - - return trims ; -} - -#endif - -#ifdef PCBSKY -extern "C" uint32_t initReadTrims( void ) ; - -uint32_t initReadTrims( void ) -{ - PMC->PMC_PCER0 = (1< #include -//#include -#include "drivers.h" #include "../src/targets/taranis/i2c.h" +#include "../src/keys.h" +#include "../src/eeprom_rlc.h" extern "C" { #include "../src/FatFs/diskio.h" } From 197708c9678880952f2af41a40ba05eb94ddf89d Mon Sep 17 00:00:00 2001 From: bsongis Date: Wed, 5 Mar 2014 15:16:13 +0100 Subject: [PATCH 043/285] Last files removed, only the minimum left and moved to another directory --- radio/bootloader/system_stm32f2xx.c | 559 ------------ radio/bootloader/usbd_storage_msd.cpp | 819 ------------------ radio/src/Makefile | 13 +- radio/{ => src}/bootloader/Makefile | 82 +- radio/{ => src}/bootloader/boot.cpp | 14 +- radio/src/targets/taranis/audio_driver.cpp | 6 +- radio/src/targets/taranis/audio_driver.h | 2 +- radio/src/targets/taranis/pwr_driver.c | 2 +- .../targets/taranis}/stm32_ramBoot.ld | 0 .../src/targets/taranis/usbd_storage_msd.cpp | 4 +- 10 files changed, 62 insertions(+), 1439 deletions(-) delete mode 100644 radio/bootloader/system_stm32f2xx.c delete mode 100644 radio/bootloader/usbd_storage_msd.cpp rename radio/{ => src}/bootloader/Makefile (68%) rename radio/{ => src}/bootloader/boot.cpp (99%) rename radio/{bootloader => src/targets/taranis}/stm32_ramBoot.ld (100%) diff --git a/radio/bootloader/system_stm32f2xx.c b/radio/bootloader/system_stm32f2xx.c deleted file mode 100644 index 687b6fd3d..000000000 --- a/radio/bootloader/system_stm32f2xx.c +++ /dev/null @@ -1,559 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f2xx.c - * @author MCD Application Team - * @version V1.1.3 - * @date 05-March-2012 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. - * This file contains the system clock configuration for STM32F2xx devices, - * and is generated by the clock configuration tool - * "STM32f2xx_Clock_Configuration_V1.0.0.xls" - * - * 1. This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier - * and Divider factors, AHB/APBx prescalers and Flash settings), - * depending on the configuration made in the clock xls tool. - * This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f2xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * 2. After each device reset the HSI (16 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to - * configure the system clock before to branch to main program. - * - * 3. If the system clock source selected by user fails to startup, the SystemInit() - * function will do nothing and HSI still used as system clock source. User can - * add some code to deal with this issue inside the SetSysClock() function. - * - * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define - * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or - * through PLL, and you are using different crystal you have to adapt the HSE - * value to your own configuration. - * - * 5. This file configures the system clock as follows: - *============================================================================= - *============================================================================= - * Supported STM32F2xx device revision | Rev B and Y - *----------------------------------------------------------------------------- - * System Clock source | PLL (HSE) - *----------------------------------------------------------------------------- - * SYSCLK(Hz) | 120000000 - *----------------------------------------------------------------------------- - * HCLK(Hz) | 120000000 - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 4 - *----------------------------------------------------------------------------- - * APB2 Prescaler | 2 - *----------------------------------------------------------------------------- - * HSE Frequency(Hz) | 25000000 - *----------------------------------------------------------------------------- - * PLL_M | 25 - *----------------------------------------------------------------------------- - * PLL_N | 240 - *----------------------------------------------------------------------------- - * PLL_P | 2 - *----------------------------------------------------------------------------- - * PLL_Q | 5 - *----------------------------------------------------------------------------- - * PLLI2S_N | NA - *----------------------------------------------------------------------------- - * PLLI2S_R | NA - *----------------------------------------------------------------------------- - * I2S input clock | NA - *----------------------------------------------------------------------------- - * VDD(V) | 3.3 - *----------------------------------------------------------------------------- - * Flash Latency(WS) | 3 - *----------------------------------------------------------------------------- - * Prefetch Buffer | ON - *----------------------------------------------------------------------------- - * Instruction cache | ON - *----------------------------------------------------------------------------- - * Data cache | ON - *----------------------------------------------------------------------------- - * Require 48MHz for USB OTG FS, | Enabled - * SDIO and RNG clock | - *----------------------------------------------------------------------------- - *============================================================================= - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f2xx_system - * @{ - */ - -/** @addtogroup STM32F2xx_System_Private_Includes - * @{ - */ - -#include "stm32f2xx.h" - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Defines - * @{ - */ - -/*!< Uncomment the following line if you need to use external SRAM mounted - on STM322xG_EVAL board as data memory */ -/* #define DATA_IN_ExtSRAM */ - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ - - -/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ -// Gives 60MHz -#define PLL_M 12 -#define PLL_N 240 - -/* SYSCLK = PLL_VCO / PLL_P */ -#define PLL_P 4 - -/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ -#define PLL_Q 5 - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Variables - * @{ - */ - - uint32_t SystemCoreClock = 60000000; - - __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes - * @{ - */ - -extern uint32_t Master_frequency ; -uint32_t Peri1_frequency ; -uint32_t Peri2_frequency ; -uint32_t Timer_mult1 ; -uint32_t Timer_mult2 ; - -static void SetSysClock(void); -#ifdef DATA_IN_ExtSRAM - static void SystemInit_ExtMemCtl(void); -#endif /* DATA_IN_ExtSRAM */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Functions - * @{ - */ - - -/** - * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemFrequency variable. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x24003010; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; - -#ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); -#endif /* DATA_IN_ExtSRAM */ - - /* Configure the System clock source, PLL Multiplier and Divider factors, - AHB/APBx prescalers and Flash settings ----------------------------------*/ - SetSysClock(); - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else -// SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -extern uint32_t g_pfnVectors ; - SCB->VTOR = (uint32_t) &g_pfnVectors ; /* Vector Table Relocation in Internal FLASH */ - -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value - * 25 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N - SYSCLK = PLL_VCO / PLL_P - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - SystemCoreClock = pllvco/pllp; - break; - default: - SystemCoreClock = HSI_VALUE; - break; - } - /* Compute HCLK frequency --------------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @Note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ -static void SetSysClock(void) -{ -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK / 1*/ - RCC->CFGR |= RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK / 2*/ - RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; - - /* PCLK1 = HCLK / 4*/ - RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; - - /* Configure the main PLL */ - RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | - (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); - - /* Enable the main PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till the main PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ - FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; - - /* Select the main PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= RCC_CFGR_SW_PLL; - - /* Wait till the main PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } - - Master_frequency = 60000000 ; - Peri1_frequency = 15000000 ; - Peri2_frequency = 30000000 ; - Timer_mult1 = 2 ; - Timer_mult2 = 2 ; - -} - -/** - * @brief Setup the external memory controller. Called in startup_stm32f2xx.s - * before jump to __main - * @param None - * @retval None - */ -#ifdef DATA_IN_ExtSRAM -/** - * @brief Setup the external memory controller. - * Called in startup_stm32f2xx.s before jump to main. - * This function configures the external SRAM mounted on STM322xG_EVAL board - * This SRAM will be used as program data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ -/*-- GPIOs Configuration -----------------------------------------------------*/ -/* - +-------------------+--------------------+------------------+------------------+ - + SRAM pins assignment + - +-------------------+--------------------+------------------+------------------+ - | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | - | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | - | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | - | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | - | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | - | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | - | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | - | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ - | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | - | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | - | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ - +-------------------+--------------------+ -*/ - /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ - RCC->AHB1ENR = 0x00000078; - - /* Connect PDx pins to FSMC Alternate function */ - GPIOD->AFR[0] = 0x00cc00cc; - GPIOD->AFR[1] = 0xcc0ccccc; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xa2aa0a0a; - /* Configure PDx pins speed to 100 MHz */ - GPIOD->OSPEEDR = 0xf3ff0f0f; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x00000000; - - /* Connect PEx pins to FSMC Alternate function */ - GPIOE->AFR[0] = 0xc00000cc; - GPIOE->AFR[1] = 0xcccccccc; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xaaaa800a; - /* Configure PEx pins speed to 100 MHz */ - GPIOE->OSPEEDR = 0xffffc00f; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x00000000; - - /* Connect PFx pins to FSMC Alternate function */ - GPIOF->AFR[0] = 0x00cccccc; - GPIOF->AFR[1] = 0xcccc0000; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xaa000aaa; - /* Configure PFx pins speed to 100 MHz */ - GPIOF->OSPEEDR = 0xff000fff; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x00000000; - - /* Connect PGx pins to FSMC Alternate function */ - GPIOG->AFR[0] = 0x00cccccc; - GPIOG->AFR[1] = 0x000000c0; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0x00080aaa; - /* Configure PGx pins speed to 100 MHz */ - GPIOG->OSPEEDR = 0x000c0fff; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x00000000; - -/*-- FSMC Configuration ------------------------------------------------------*/ - /* Enable the FSMC interface clock */ - RCC->AHB3ENR = 0x00000001; - - /* Configure and enable Bank1_SRAM2 */ - FSMC_Bank1->BTCR[2] = 0x00001015; - FSMC_Bank1->BTCR[3] = 0x00010400; - FSMC_Bank1E->BWTR[2] = 0x0fffffff; -/* - Bank1_SRAM2 is configured as follow: - - p.FSMC_AddressSetupTime = 0; - p.FSMC_AddressHoldTime = 0; - p.FSMC_DataSetupTime = 4; - p.FSMC_BusTurnAroundDuration = 1; - p.FSMC_CLKDivision = 0; - p.FSMC_DataLatency = 0; - p.FSMC_AccessMode = FSMC_AccessMode_A; - - FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; - FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; - FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; - FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; - FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; - FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; - FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; -*/ - -} -#endif /* DATA_IN_ExtSRAM */ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/bootloader/usbd_storage_msd.cpp b/radio/bootloader/usbd_storage_msd.cpp deleted file mode 100644 index b2dcb530a..000000000 --- a/radio/bootloader/usbd_storage_msd.cpp +++ /dev/null @@ -1,819 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_storage_msd.c - * @author MCD application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief This file provides the disk operations functions. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -#include -#include -#include "../src/targets/taranis/i2c.h" -#include "../src/keys.h" -#include "../src/eeprom_rlc.h" -extern "C" { -#include "../src/FatFs/diskio.h" -} -//#include "board_taranis.h" - -#include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_gpio.h" -#include "hal.h" -#define SD_CARD_PRESENT() (~SD_PRESENT_GPIO->IDR & SD_PRESENT_GPIO_Pin) - -void I2C_EE_BufferWrite(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite) ; -void eeprom_read_block (void *pointer_ram, uint16_t pointer_eeprom, size_t size); - -extern "C" { -#include "misc.h" -#include "usbd_msc_mem.h" -#include "usb_conf.h" - -#define eeWriteBlockCmp I2C_EE_BufferWrite -#define eeprom_read_block I2C_EE_BufferRead - - -#define STORAGE_LUN_NBR 2 -#define BLOCKSIZE 512 - -/* USB Mass storage Standard Inquiry Data */ -const unsigned char STORAGE_Inquirydata[] = {//36 - - /* LUN 0 */ - 0x00, - 0x80, - 0x02, - 0x02, - (USBD_STD_INQUIRY_LENGTH - 5), - 0x00, - 0x00, - 0x00, - 'F', 'r', 'S', 'k', 'y', ' ', ' ', ' ', /* Manufacturer : 8 bytes */ - 'T', 'a', 'r', 'a', 'n', 'i', 's', ' ', /* Product : 16 Bytes */ - 'R', 'a', 'd', 'i', 'o', ' ', ' ', ' ', - '1', '.', '0', '0', /* Version : 4 Bytes */ - /* LUN 1 */ - 0x00, - 0x80, - 0x02, - 0x02, - (USBD_STD_INQUIRY_LENGTH - 5), - 0x00, - 0x00, - 0x00, - 'F', 'r', 'S', 'k', 'y', ' ', ' ', ' ', /* Manufacturer : 8 bytes */ - 'T', 'a', 'r', 'a', 'n', 'i', 's', ' ', /* Product : 16 Bytes */ - 'R', 'a', 'd', 'i', 'o', ' ', ' ', ' ', - '1', '.', '0' ,'0', /* Version : 4 Bytes */ -}; - -int32_t fat12Write( const uint8_t *buffer, uint16_t sector, uint32_t count ) ; -int32_t fat12Read( uint8_t *buffer, uint16_t sector, uint16_t count ) ; - -int8_t STORAGE_Init (uint8_t lun); - -int8_t STORAGE_GetCapacity (uint8_t lun, - uint32_t *block_num, - uint32_t *block_size); - -int8_t STORAGE_IsReady (uint8_t lun); - -int8_t STORAGE_IsWriteProtected (uint8_t lun); - -int8_t STORAGE_Read (uint8_t lun, - uint8_t *buf, - uint32_t blk_addr, - uint16_t blk_len); - -int8_t STORAGE_Write (uint8_t lun, - uint8_t *buf, - uint32_t blk_addr, - uint16_t blk_len); - -int8_t STORAGE_GetMaxLun (void); - -USBD_STORAGE_cb_TypeDef USBD_MICRO_SDIO_fops = -{ - STORAGE_Init, - STORAGE_GetCapacity, - STORAGE_IsReady, - STORAGE_IsWriteProtected, - STORAGE_Read, - STORAGE_Write, - STORAGE_GetMaxLun, - (int8_t *)STORAGE_Inquirydata, -}; - -USBD_STORAGE_cb_TypeDef *USBD_STORAGE_fops = &USBD_MICRO_SDIO_fops; - -__IO uint32_t count = 0; -} - -int8_t STORAGE_Init (uint8_t lun) -{ - NVIC_InitTypeDef NVIC_InitStructure; - NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority =0; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); - -/* TODO if no SD ... if( SD_Init() != 0) - { - return (-1); - } -*/ - return (0); -} - -/** - * @brief return medium capacity and block size - * @param lun : logical unit number - * @param block_num : number of physical block - * @param block_size : size of a physical block - * @retval Status - */ -int8_t STORAGE_GetCapacity (uint8_t lun, uint32_t *block_num, uint32_t *block_size) -{ - if (lun == 1) { - *block_size = BLOCKSIZE; - *block_num = EESIZE/BLOCKSIZE + 3 + 1024 ; - } - else { - if (!SD_CARD_PRESENT()) - return -1; - - *block_size = BLOCKSIZE; - - static DWORD sector_count = 0; - if (sector_count == 0) { - if (disk_ioctl(0, GET_SECTOR_COUNT, §or_count) != RES_OK) { - sector_count = 0; - return -1; - } - } - - *block_num = sector_count; - } - - return 0; -} - -/** - * @brief check whether the medium is ready - * @param lun : logical unit number - * @retval Status - */ -int8_t STORAGE_IsReady (uint8_t lun) -{ - if (lun == 1) { - return 0; - } - else { - return SD_CARD_PRESENT() ? 0 : -1; - } -} - -/** - * @brief check whether the medium is write-protected - * @param lun : logical unit number - * @retval Status - */ -int8_t STORAGE_IsWriteProtected (uint8_t lun) -{ - return 0; -} - -/** - * @brief Read data from the medium - * @param lun : logical unit number - * @param buf : Pointer to the buffer to save data - * @param blk_addr : address of 1st block to be read - * @param blk_len : nmber of blocks to be read - * @retval Status - */ - -int8_t SD_ReadSectors(uint8_t *buff, uint32_t sector, uint32_t count); - -int8_t STORAGE_Read (uint8_t lun, - uint8_t *buf, - uint32_t blk_addr, - uint16_t blk_len) -{ - if (lun == 1) { - if (fat12Read(buf, blk_addr, blk_len) != 0) { - return -1; - } - } - else { - if (SD_ReadSectors(buf, - blk_addr, - blk_len) != 0) { - return -1; - } - } - - return 0; -} -/** - * @brief Write data to the medium - * @param lun : logical unit number - * @param buf : Pointer to the buffer to write from - * @param blk_addr : address of 1st block to be written - * @param blk_len : nmber of blocks to be read - * @retval Status - */ - -int8_t SD_WriteSectors(uint8_t *buf, uint32_t sector, uint32_t count); - -int8_t STORAGE_Write (uint8_t lun, - uint8_t *buf, - uint32_t blk_addr, - uint16_t blk_len) -{ - if (lun == 1) { - if (fat12Write(buf, blk_addr, blk_len) != 0) - return -1; - } - else { - if (SD_WriteSectors(buf, - blk_addr, - blk_len) != 0) - return -1; - } - - return (0); -} - -/** - * @brief Return number of supported logical unit - * @param None - * @retval number of logical unit - */ - -int8_t STORAGE_GetMaxLun (void) -{ - return (STORAGE_LUN_NBR - 1); -} - - -//------------------------------------------------------------------------------ -/** - * FAT12 boot sector partition. - */ -const char g_FATboot[BLOCKSIZE] = -{ - 0xeb, 0x3c, 0x90, // Jump instruction. - 0x39, 0x58, 0x20, 0x54, 0x45, 0x41, 0x4D, 0x00, // OEM Name - 0x00, 0x02, // Bytes per sector - 0x08, // Sectors per FS cluster. - 0x01, 0x00, // Reserved sector count - - 0x01, // Number of FATs - 0x10, 0x00, // Number of root directory entries - (EESIZE/BLOCKSIZE)+3, 0x04, // Total sectors = 1024+131=1155 - 0xf8, // Media descriptor - 0x01, 0x00, // Sectors per FAT table - 0x20, 0x00, // Sectors per track - 0x40, 0x00, // Number of heads - 0x00, 0x00, 0x00, 0x00, // Number of hidden sectors - - 0x00, 0x00, 0x00, 0x00, // Large number of sectors. - 0x00, // Physical drive number - 0x00, // Reserved - 0x29, // Extended boot signature - 0xCE, 0xFA, 0x5C, 0xD1, // Disk ID (serial number) - 0x56, 0x49, 0x52, 0x54, 0x46, 0x53, 0x20, 0x20, 0x20, 0x20, 0x20, // Volume label - 0x46, 0x41, 0x54, 0x31, 0x32, 0x20, 0x20, 0x20, // FAT file system type - 0x00, 0x00, // OS boot code - - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0xaa -}; - -#if defined(REV4a) -const char g_FAT[BLOCKSIZE] = -{ - 0xF8, 0xFF, 0xFF, 0x03, 0x40, 0x00, 0x05, 0x60, 0x00, 0x07, 0x80, 0x00, 0x09, 0xF0, 0xFF, 0x0B, - 0xC0, 0x00, 0x0D, 0xE0, 0x00, 0x0F, 0x00, 0x01, 0x11, 0x20, 0x01, 0x13, 0x40, 0x01, 0x15, 0x60, - 0x01, 0x17, 0x80, 0x01, 0x19, 0xA0, 0x01, 0x1B, 0xC0, 0x01, 0x1D, 0xE0, 0x01, 0x1F, 0x00, 0x02, - 0x21, 0x20, 0x02, 0x23, 0x40, 0x02, 0x25, 0x60, 0x02, 0x27, 0x80, 0x02, 0x29, 0xA0, 0x02, 0x2B, - 0xC0, 0x02, 0x2D, 0xE0, 0x02, 0x2F, 0x00, 0x03, 0x31, 0x20, 0x03, 0x33, 0x40, 0x03, 0x35, 0x60, - 0x03, 0x37, 0x80, 0x03, 0x39, 0xA0, 0x03, 0x3B, 0xC0, 0x03, 0x3D, 0xE0, 0x03, 0x3F, 0x00, 0x04, - 0x41, 0x20, 0x04, 0x43, 0x40, 0x04, 0x45, 0x60, 0x04, 0x47, 0x80, 0x04, 0x49, 0xA0, 0x04, 0x4B, - 0xC0, 0x04, 0x4D, 0xE0, 0x04, 0x4F, 0x00, 0x05, 0x51, 0x20, 0x05, 0x53, 0x40, 0x05, 0x55, 0x60, - 0x05, 0x57, 0x80, 0x05, 0x59, 0xA0, 0x05, 0x5B, 0xC0, 0x05, 0x5D, 0xE0, 0x05, 0x5F, 0x00, 0x06, - 0x61, 0x20, 0x06, 0x63, 0x40, 0x06, 0x65, 0x60, 0x06, 0x67, 0x80, 0x06, 0x69, 0xA0, 0x06, 0x6B, - 0xC0, 0x06, 0x6D, 0xE0, 0x06, 0x6F, 0x00, 0x07, 0x71, 0x20, 0x07, 0x73, 0x40, 0x07, 0x75, 0x60, - 0x07, 0x77, 0x80, 0x07, 0x79, 0xA0, 0x07, 0x7B, 0xC0, 0x07, 0x7D, 0xE0, 0x07, 0x7F, 0x00, 0x08, - 0x81, 0x20, 0x08, 0x83, 0x40, 0x08, 0x85, 0x60, 0x08, 0x87, 0x80, 0x08, 0x89, 0xF0, 0xFF, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; -#else -const char g_FAT[BLOCKSIZE] = -{ - 0xF8, 0xFF, 0xFF, 0x03, 0x40, 0x00, 0x05, 0x60, 0x00, 0x07, 0x80, 0x00, 0x09, 0xF0, 0xFF, 0x0B, - 0xC0, 0x00, 0x0D, 0xE0, 0x00, 0x0F, 0x00, 0x01, 0x11, 0x20, 0x01, 0x13, 0x40, 0x01, 0x15, 0x60, - 0x01, 0x17, 0x80, 0x01, 0x19, 0xA0, 0x01, 0x1B, 0xC0, 0x01, 0x1D, 0xE0, 0x01, 0x1F, 0x00, 0x02, - 0x21, 0x20, 0x02, 0x23, 0x40, 0x02, 0x25, 0x60, 0x02, 0x27, 0x80, 0x02, 0x29, 0xA0, 0x02, 0x2B, - 0xC0, 0x02, 0x2D, 0xE0, 0x02, 0x2F, 0x00, 0x03, 0x31, 0x20, 0x03, 0x33, 0x40, 0x03, 0x35, 0x60, - 0x03, 0x37, 0x80, 0x03, 0x39, 0xA0, 0x03, 0x3B, 0xC0, 0x03, 0x3D, 0xE0, 0x03, 0x3F, 0x00, 0x04, - 0x41, 0x20, 0x04, 0x43, 0x40, 0x04, 0x45, 0x60, 0x04, 0x47, 0x80, 0x04, 0x49, 0xA0, 0x04, 0x4B, - 0xC0, 0x04, 0x4D, 0xE0, 0x04, 0x4F, 0x00, 0x05, 0x51, 0x20, 0x05, 0x53, 0x40, 0x05, 0x55, 0x60, - 0x05, 0x57, 0x80, 0x05, 0x59, 0xA0, 0x05, 0x5B, 0xC0, 0x05, 0x5D, 0xE0, 0x05, 0x5F, 0x00, 0x06, - 0x61, 0x20, 0x06, 0x63, 0x40, 0x06, 0x65, 0x60, 0x06, 0x67, 0x80, 0x06, 0x69, 0xA0, 0x06, 0x6B, - 0xC0, 0x06, 0x6D, 0xE0, 0x06, 0x6F, 0x00, 0x07, 0x71, 0x20, 0x07, 0x73, 0x40, 0x07, 0x75, 0x60, - 0x07, 0x77, 0x80, 0x07, 0x79, 0xA0, 0x07, 0x7B, 0xC0, 0x07, 0x7D, 0xE0, 0x07, 0x7F, 0x00, 0x08, - 0x81, 0x20, 0x08, 0x83, 0x40, 0x08, 0x85, 0x60, 0x08, 0x87, 0x80, 0x08, 0x89, 0xF0, 0xFF, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; -#endif - -// File Attributes -// 0 0x01 Read Only. -// 1 0x02 Hidden. -// 2 0x04 System. -// 3 0x08 Volume Label. -// 4 0x10 Subdirectory. -// 5 0x20 Archive. -// 6 0x40 Device. -// 7 0x80 Reserved. - -typedef struct -{ - uint8_t name[8]; - uint8_t ext[3]; - uint8_t attribute; - uint8_t reserved; - uint8_t create_time_ms; - uint16_t create_time; - uint16_t create_date; - uint16_t access_date; - uint16_t ea_index; - uint16_t modify_time; - uint16_t modify_date; - uint16_t start_cluster; - uint32_t file_size; -} FATDirEntry_t; - -// First 16 FAT root directory entries (1 sector) -const FATDirEntry_t g_DIRroot[16] = -{ - { -#ifdef PCBTARANIS - { 'T', 'A', 'R', 'A', 'N', 'I', 'S', ' '}, - { ' ', ' ', ' '}, -#else - { 'E', 'R', 'S', 'K', 'Y', '_', '9', 'X'}, - { ' ', ' ', ' '}, -#endif - 0x08, // Volume - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - }, - { -#ifdef PCBTARANIS - { 'T', 'A', 'R', 'A', 'N', 'I', 'S', ' '}, - { 'B', 'I', 'N'}, -#else - { 'E', 'R', 'S', 'K', 'Y', '9', 'X', ' '}, - { 'B', 'I', 'N'}, -#endif - 0x24, // Archive, hidden, system - 0x00, - 0x3E, - 0xA301, - 0x3D55, - 0x3D55, - 0x0000, - 0xA302, - 0x3D55, - 0x0002, - EESIZE - }, - { - { 'F', 'I', 'R', 'M', 'W', 'A', 'R', 'E'}, - { 'B', 'I', 'N'}, - 0x24, // Archive, hidden, system - 0x00, - 0x3E, - 0xA301, - 0x3D55, - 0x3D55, - 0x0000, - 0xA302, - 0x3D55, - 0x000A, - 0x00080000 // 512K - }, - { - { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x00, - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - }, - { - { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x00, - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - }, - { - { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x00, - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - }, - { - { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x00, - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - }, - { - { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x00, - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - }, - { - { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x00, - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - }, - { - { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x00, - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - }, - { - { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x00, - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - }, - { - { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x00, - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - }, - { - { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x00, - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - }, - { - { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x00, - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - }, - { - { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x00, - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - }, - { - { '\x00', ' ', ' ', ' ', ' ', ' ', ' ', ' '}, - { ' ', ' ', ' '}, - 0x00, - 0x00, - 0x00, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x00000000 - }, -}; - -// count is number of 512 byte sectors -int32_t fat12Read( uint8_t *buffer, uint16_t sector, uint16_t count ) -{ - while ( count ) - { - if (sector == 0) { - memcpy( buffer, g_FATboot, BLOCKSIZE ) ; - } - else if (sector == 1/*Reserved sector count*/) { - // FAT table. - memcpy( buffer, g_FAT, BLOCKSIZE); - } - else if (sector == 2) { - memcpy( buffer, g_DIRroot, BLOCKSIZE ) ; - } - else if ( sector < 67 ) - { - eeprom_read_block (buffer, (sector-3)*BLOCKSIZE, BLOCKSIZE); - } - else if ( sector < 1155 ) - { - uint32_t address ; - address = sector - 67 ; - address *= 512 ; - address += 0x08000000 ; - memcpy( buffer, (uint8_t *)address, BLOCKSIZE ) ; - } - buffer += BLOCKSIZE ; - sector++ ; - count-- ; - } - return 0 ; -} -//------------------------------------------------------------------------------ - -extern uint32_t program( uint32_t *address, uint32_t *buffer ) ; // size is 256 bytes - -uint32_t isValidEepromStart( const uint8_t *buffer ) -{ - uint32_t size ; - uint32_t bs ; - // Check Taranis format - size = buffer[1] + ( buffer[2] << 8 ) ; - bs = buffer[5] ; - if ( ( size == 0x0100 ) && ( bs == 0x40 ) ) - { - return 1 ; - } - size = buffer[1] ; - bs = buffer[3] ; - if ( ( size == 0x0080 ) && ( bs == 0x80 ) ) - { - return 1 ; - } - return 0 ; -} - - -//------------------------------------------------------------------------------ -//------------------------------------------------------------------------------ -int32_t fat12Write(const uint8_t *buffer, uint16_t sector, uint32_t count ) -{ - static int offset = 0; - -// TRACE("FAT12 Write(sector=%d, count=%d)", sector, count); - - if ( sector >= 3 ) - { - if ( sector < 67 ) - { - while (count) - { - if (offset == 0 && sector == 3 &&/*test->version==EEFS_VERS && */ isValidEepromStart( buffer ) ) - { -// TRACE("EEPROM start found in sector %d", sector); - offset = sector; - } - if (offset && sector >= offset && (sector-offset) < EESIZE/BLOCKSIZE) - { - eeWriteBlockCmp((uint8_t *)buffer, (sector-offset)*BLOCKSIZE, BLOCKSIZE); - } - buffer += BLOCKSIZE; - sector++; - count--; - if (sector-offset >= EESIZE/BLOCKSIZE) - { -// TRACE("EEPROM end written at sector %d", sector-1); - offset = 0; - } - } - } - else if ( sector < 1155 ) - { - // firmware - uint32_t address ; - address = sector - 67 ; - address *= 512 ; - address += 0x08000000 ; - - uint32_t i ; - while ( count ) - { - for ( i = 0 ; i < 2 ; i += 1 ) - { - if ( address >= 0x08008000 ) // Protect bootloader - { - if ( address < (0x08000000 + (512*1024) - 256) ) // in range - { - program( (uint32_t *)address, (uint32_t *) buffer ) ; // size is 256 bytes - } - } - address += 256 ; - buffer += 256 ; - } - count -= 1 ; - } - } - } - return 0 ; -} - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/radio/src/Makefile b/radio/src/Makefile index cda31aa0f..c4c237b79 100644 --- a/radio/src/Makefile +++ b/radio/src/Makefile @@ -638,10 +638,11 @@ ifeq ($(PCB), TARANIS) BOARDSRC = targets/taranis/board_taranis.cpp EXTRABOARDSRC += targets/taranis/lcd_driver.cpp targets/taranis/aspi.c targets/taranis/i2c.c targets/taranis/delays.c SRC += CoOS/kernel/core.c CoOS/kernel/hook.c CoOS/kernel/task.c CoOS/kernel/event.c CoOS/kernel/time.c CoOS/kernel/timer.c CoOS/kernel/flag.c CoOS/kernel/mutex.c CoOS/kernel/serviceReq.c CoOS/portable/GCC/port.c CoOS/portable/arch.c + SRC += targets/taranis/pwr_driver.c EEPROMSRC = eeprom_common.cpp eeprom_rlc.cpp eeprom_conversions.cpp PULSESSRC = protocols/pulses_arm.cpp protocols/ppm_arm.cpp protocols/pxx_arm.cpp CPPSRC += audio_arm.cpp - CPPSRC += targets/taranis/pwr_driver.cpp targets/taranis/pulses_driver.cpp targets/taranis/keys_driver.cpp targets/taranis/adc_driver.cpp targets/taranis/trainer_driver.cpp targets/taranis/audio_driver.cpp targets/taranis/uart3_driver.cpp targets/taranis/sport_driver.cpp + CPPSRC += targets/taranis/pulses_driver.cpp targets/taranis/keys_driver.cpp targets/taranis/adc_driver.cpp targets/taranis/trainer_driver.cpp targets/taranis/audio_driver.cpp targets/taranis/uart3_driver.cpp targets/taranis/sport_driver.cpp CPPSRC += bmp.cpp gui/view_channels.cpp gui/view_about.cpp gui/view_text.cpp SRC += targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c SRC += targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/misc.c @@ -1097,14 +1098,14 @@ all: begin gccversion sizebefore build sizeafter end ifeq ($(ARCH), AVR) build: stamp_header tra lbm allsrc.cpp elf remallsrc hex else - build: stamp_header tra lbm bootloader allsrc.cpp elf remallsrc bin + build: stamp_header tra lbm bootloader.lbm allsrc.cpp elf remallsrc bin endif # build bootloader -.PHONY bootloader: +.PHONY bootloader.lbm: @echo "Building bootloader..." - $(MAKE) -C ../bootloader PCB=$(PCB) - $(BIN2LBM) bootloader.lbm ../bootloader/bootloader_ramBoot.bin + $(MAKE) -C bootloader PCB=$(PCB) + $(BIN2LBM) bootloader.lbm bootloader/bootloader_ramBoot.bin tra: translations/en.h translations/cz.h translations/de.h translations/es.h translations/fi.h translations/fr.h translations/it.h translations/pl.h translations/pt.h translations/se.h lbm: fonts bitmaps/sticks.lbm @@ -1365,7 +1366,7 @@ clean_list : $(REMOVE) allsrc.cpp $(REMOVE) stamp-opentx.h $(REMOVE) `find . -name "*.lbm"` - $(MAKE) -C ../bootloader clean + $(MAKE) -C bootloader clean #### Install diff --git a/radio/bootloader/Makefile b/radio/src/bootloader/Makefile similarity index 68% rename from radio/bootloader/Makefile rename to radio/src/bootloader/Makefile index d756d8518..71f882a6e 100644 --- a/radio/bootloader/Makefile +++ b/radio/src/bootloader/Makefile @@ -93,18 +93,18 @@ ifeq ($(RUN_FROM_FLASH), 1) else ifeq ($(PCB), TARANIS) ARCH = ARM - LDSCRIPT = stm32_ramBoot.ld + LDSCRIPT = ../targets/taranis/stm32_ramBoot.ld TRGT = arm-none-eabi- CPPDEFS += -DHSE_VALUE=12000000 CPPDEFS += -DPCBTARANIS FULL_PRJ = $(PROJECT)_ramBoot - EXTRAINCDIRS += ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc - EXTRAINCDIRS += ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include - EXTRAINCDIRS += ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/inc - EXTRAINCDIRS += ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Core/inc - EXTRAINCDIRS += ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/inc - EXTRAINCDIRS += ../src/targets/taranis - EXTRAINCDIRS += ../src/fonts/std + EXTRAINCDIRS += ../targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc + EXTRAINCDIRS += ../targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include + EXTRAINCDIRS += ../targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/inc + EXTRAINCDIRS += ../targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Core/inc + EXTRAINCDIRS += ../targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/inc + EXTRAINCDIRS += ../targets/taranis + EXTRAINCDIRS += ../fonts/std endif endif @@ -115,43 +115,43 @@ endif UADEFS = ifeq ($(PCB), TARANIS) -SRC = system_stm32f2xx.c \ - ../src/targets/taranis/i2c.c \ - ../src/targets/taranis/delays.c \ - ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rcc.c \ - ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_gpio.c \ - ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_spi.c \ - ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/misc.c \ - ../src/FatFs/ff.c \ - ../src/FatFs/option/ccsbcs.c \ - ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/src/usb_core.c \ - ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/src/usb_dcd.c \ - ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/src/usb_dcd_int.c \ - ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_core.c \ - ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_ioreq.c \ - ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_req.c \ - ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_data.c \ - ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_scsi.c \ - ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_bot.c \ - ../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_core.c \ - ../src/targets/taranis/usbd_desc.c \ - ../src/targets/taranis/aspi.c \ - ../src/targets/taranis/usb_bsp.c \ - ../src/targets/taranis/usb_driver.c \ - ../src/targets/taranis/pwr_driver.c +SRC = ../targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c \ + ../targets/taranis/i2c.c \ + ../targets/taranis/delays.c \ + ../targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rcc.c \ + ../targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_gpio.c \ + ../targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_spi.c \ + ../targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/misc.c \ + ../FatFs/ff.c \ + ../FatFs/option/ccsbcs.c \ + ../targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/src/usb_core.c \ + ../targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/src/usb_dcd.c \ + ../targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/src/usb_dcd_int.c \ + ../targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_core.c \ + ../targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_ioreq.c \ + ../targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_req.c \ + ../targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_data.c \ + ../targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_scsi.c \ + ../targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_bot.c \ + ../targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_core.c \ + ../targets/taranis/usbd_desc.c \ + ../targets/taranis/aspi.c \ + ../targets/taranis/usb_bsp.c \ + ../targets/taranis/usb_driver.c \ + ../targets/taranis/pwr_driver.c -CPPSRC = ../src/targets/taranis/lcd_driver.cpp \ - ../src/targets/taranis/keys_driver.cpp \ - ../src/targets/taranis/diskio.cpp \ - ../src/targets/taranis/usbd_usr.cpp \ - usbd_storage_msd.cpp \ - ../src/lcd.cpp \ - ../src/keys.cpp \ - ../src/fonts.cpp \ +CPPSRC = ../targets/taranis/lcd_driver.cpp \ + ../targets/taranis/keys_driver.cpp \ + ../targets/taranis/diskio.cpp \ + ../targets/taranis/usbd_usr.cpp \ + ../targets/taranis/usbd_storage_msd.cpp \ + ../lcd.cpp \ + ../keys.cpp \ + ../fonts.cpp \ boot.cpp # List ASM source files here -ASRC = ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc_ride7/startup_stm32f2xx.s +ASRC = ../targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc_ride7/startup_stm32f2xx.s else diff --git a/radio/bootloader/boot.cpp b/radio/src/bootloader/boot.cpp similarity index 99% rename from radio/bootloader/boot.cpp rename to radio/src/bootloader/boot.cpp index 91f0f94e4..cf137f00a 100644 --- a/radio/bootloader/boot.cpp +++ b/radio/src/bootloader/boot.cpp @@ -57,13 +57,13 @@ #ifdef PCBTARANIS #include "stm32f2xx.h" #include "stm32f2xx_flash.h" -#include "../src/targets/taranis/i2c.h" +#include "../targets/taranis/i2c.h" #include "hal.h" extern "C" { #include "usb_dcd_int.h" #include "usb_bsp.h" -#include "../src/targets/taranis/usbd_desc.h" +#include "../targets/taranis/usbd_desc.h" #include "usbd_msc_core.h" #include "usbd_usr.h" } @@ -71,12 +71,12 @@ extern "C" { #endif #include "board_taranis.h" -#include "../src/pwr.h" -#include "../src/lcd.h" -#include "../src/keys.h" +#include "../pwr.h" +#include "../lcd.h" +#include "../keys.h" -#include "../src/FatFs/ff.h" -#include "../src/FatFs/diskio.h" +#include "../FatFs/ff.h" +#include "../FatFs/diskio.h" #ifdef PCBTARANIS #define BOOT_KEY_UP KEY_PLUS diff --git a/radio/src/targets/taranis/audio_driver.cpp b/radio/src/targets/taranis/audio_driver.cpp index d0b0508aa..5c2a072bf 100644 --- a/radio/src/targets/taranis/audio_driver.cpp +++ b/radio/src/targets/taranis/audio_driver.cpp @@ -36,7 +36,7 @@ #include "../../opentx.h" -bool dacIdle = true; +int dacIdle = 1; void setSampleRate(uint32_t frequency) { @@ -96,7 +96,7 @@ void dacInit() bool dacQueue(AudioBuffer *buffer) { if (dacIdle) { - dacIdle = false; + dacIdle = 0; DMA1_Stream5->CR &= ~DMA_SxCR_EN ; // Disable DMA channel DMA1->HIFCR = DMA_HIFCR_CTCIF5 | DMA_HIFCR_CHTIF5 | DMA_HIFCR_CTEIF5 | DMA_HIFCR_CDMEIF5 | DMA_HIFCR_CFEIF5 ; // Write ones to clear bits DMA1_Stream5->M0AR = CONVERT_PTR(buffer->data); @@ -149,7 +149,7 @@ extern "C" void DMA1_Stream5_IRQHandler() DAC->SR = DAC_SR_DMAUDR1; // Write 1 to clear flag } else { - dacIdle = true; + dacIdle = 1; } } #endif diff --git a/radio/src/targets/taranis/audio_driver.h b/radio/src/targets/taranis/audio_driver.h index 0a79ea75d..3361cb788 100644 --- a/radio/src/targets/taranis/audio_driver.h +++ b/radio/src/targets/taranis/audio_driver.h @@ -42,7 +42,7 @@ extern void audioEnd( void ) ; extern void setSampleRate(uint32_t frequency); -extern bool dacIdle; +extern int dacIdle; inline void dacStart() { diff --git a/radio/src/targets/taranis/pwr_driver.c b/radio/src/targets/taranis/pwr_driver.c index 43c353a6a..49930141a 100644 --- a/radio/src/targets/taranis/pwr_driver.c +++ b/radio/src/targets/taranis/pwr_driver.c @@ -35,7 +35,7 @@ */ #include "board_taranis.h" -#include "../src/pwr.h" +#include "../pwr.h" void pwrInit() { diff --git a/radio/bootloader/stm32_ramBoot.ld b/radio/src/targets/taranis/stm32_ramBoot.ld similarity index 100% rename from radio/bootloader/stm32_ramBoot.ld rename to radio/src/targets/taranis/stm32_ramBoot.ld diff --git a/radio/src/targets/taranis/usbd_storage_msd.cpp b/radio/src/targets/taranis/usbd_storage_msd.cpp index 65d382b96..1e838c078 100644 --- a/radio/src/targets/taranis/usbd_storage_msd.cpp +++ b/radio/src/targets/taranis/usbd_storage_msd.cpp @@ -26,8 +26,8 @@ */ /* Includes ------------------------------------------------------------------*/ -#include "../opentx.h" -#include "../FatFs/diskio.h" +#include "../../opentx.h" +#include "../../FatFs/diskio.h" #include "board_taranis.h" extern "C" { From 5e6cd0ee7625512fe70d0b7d9f650fa30642952c Mon Sep 17 00:00:00 2001 From: bsongis Date: Wed, 5 Mar 2014 15:40:27 +0100 Subject: [PATCH 044/285] Compilation error fixed --- radio/src/Makefile | 4 ++-- radio/src/targets/taranis/audio_driver.cpp | 14 ++++++++++++++ radio/src/targets/taranis/audio_driver.h | 19 ++++--------------- radio/src/targets/taranis/usb_driver.c | 2 ++ 4 files changed, 22 insertions(+), 17 deletions(-) diff --git a/radio/src/Makefile b/radio/src/Makefile index c4c237b79..a481a13be 100644 --- a/radio/src/Makefile +++ b/radio/src/Makefile @@ -638,7 +638,7 @@ ifeq ($(PCB), TARANIS) BOARDSRC = targets/taranis/board_taranis.cpp EXTRABOARDSRC += targets/taranis/lcd_driver.cpp targets/taranis/aspi.c targets/taranis/i2c.c targets/taranis/delays.c SRC += CoOS/kernel/core.c CoOS/kernel/hook.c CoOS/kernel/task.c CoOS/kernel/event.c CoOS/kernel/time.c CoOS/kernel/timer.c CoOS/kernel/flag.c CoOS/kernel/mutex.c CoOS/kernel/serviceReq.c CoOS/portable/GCC/port.c CoOS/portable/arch.c - SRC += targets/taranis/pwr_driver.c + SRC += targets/taranis/pwr_driver.c targets/taranis/usb_driver.c EEPROMSRC = eeprom_common.cpp eeprom_rlc.cpp eeprom_conversions.cpp PULSESSRC = protocols/pulses_arm.cpp protocols/ppm_arm.cpp protocols/pxx_arm.cpp CPPSRC += audio_arm.cpp @@ -1104,7 +1104,7 @@ endif # build bootloader .PHONY bootloader.lbm: @echo "Building bootloader..." - $(MAKE) -C bootloader PCB=$(PCB) + $(MAKE) -C bootloader PCB=TARANIS $(BIN2LBM) bootloader.lbm bootloader/bootloader_ramBoot.bin tra: translations/en.h translations/cz.h translations/de.h translations/es.h translations/fi.h translations/fr.h translations/it.h translations/pl.h translations/pt.h translations/se.h diff --git a/radio/src/targets/taranis/audio_driver.cpp b/radio/src/targets/taranis/audio_driver.cpp index 5c2a072bf..15d6fdd37 100644 --- a/radio/src/targets/taranis/audio_driver.cpp +++ b/radio/src/targets/taranis/audio_driver.cpp @@ -111,6 +111,20 @@ bool dacQueue(AudioBuffer *buffer) } } +void dacStart() +{ + DMA1->HIFCR = DMA_HIFCR_CTCIF5 | DMA_HIFCR_CHTIF5 | DMA_HIFCR_CTEIF5 | DMA_HIFCR_CDMEIF5 | DMA_HIFCR_CFEIF5 ; // Write ones to clear bits + DMA1_Stream5->CR |= DMA_SxCR_CIRC | DMA_SxCR_EN ; // Enable DMA channel + DAC->SR = DAC_SR_DMAUDR1 ; // Write 1 to clear flag + DAC->CR |= DAC_CR_EN1 | DAC_CR_DMAEN1 ; // Enable DAC +} + +void dacStop() +{ + DMA1_Stream5->CR &= ~DMA_SxCR_CIRC ; +} + + // Sound routines void audioInit() { diff --git a/radio/src/targets/taranis/audio_driver.h b/radio/src/targets/taranis/audio_driver.h index 3361cb788..e357e8627 100644 --- a/radio/src/targets/taranis/audio_driver.h +++ b/radio/src/targets/taranis/audio_driver.h @@ -37,26 +37,15 @@ #ifndef audio_driver_h #define audio_driver_h -extern void audioInit( void ) ; -extern void audioEnd( void ) ; +void audioInit( void ) ; +void audioEnd( void ) ; +void dacStart(); +void dacStop(); extern void setSampleRate(uint32_t frequency); extern int dacIdle; -inline void dacStart() -{ - DMA1->HIFCR = DMA_HIFCR_CTCIF5 | DMA_HIFCR_CHTIF5 | DMA_HIFCR_CTEIF5 | DMA_HIFCR_CDMEIF5 | DMA_HIFCR_CFEIF5 ; // Write ones to clear bits - DMA1_Stream5->CR |= DMA_SxCR_CIRC | DMA_SxCR_EN ; // Enable DMA channel - DAC->SR = DAC_SR_DMAUDR1 ; // Write 1 to clear flag - DAC->CR |= DAC_CR_EN1 | DAC_CR_DMAEN1 ; // Enable DAC -} - -inline void dacStop() -{ - DMA1_Stream5->CR &= ~DMA_SxCR_CIRC ; -} - #define VOLUME_LEVEL_MAX 23 #define VOLUME_LEVEL_DEF 12 static const int8_t volumeScale[VOLUME_LEVEL_MAX+1] = diff --git a/radio/src/targets/taranis/usb_driver.c b/radio/src/targets/taranis/usb_driver.c index 734756c09..ea9ca3bde 100755 --- a/radio/src/targets/taranis/usb_driver.c +++ b/radio/src/targets/taranis/usb_driver.c @@ -35,6 +35,8 @@ */ #include "board_taranis.h" +#include "STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/inc/usb_dcd_int.h" +#include "STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/inc/usb_bsp.h" int usbPlugged(void) { From 4e6def3ba3f93dc545d35498af39d3d5cb674e0d Mon Sep 17 00:00:00 2001 From: bsongis Date: Wed, 5 Mar 2014 17:32:17 +0100 Subject: [PATCH 045/285] Compilation errors on Companion --- companion/src/firmwares/opentx/opentxGruvin9xsimulator.cpp | 1 + companion/src/firmwares/opentx/opentxM128simulator.cpp | 1 + companion/src/firmwares/opentx/opentxSky9xsimulator.cpp | 1 + companion/src/firmwares/opentx/opentxTaranisSimulator.cpp | 3 ++- companion/src/firmwares/opentx/opentxsimulator.cpp | 1 + radio/src/simpgmspace.cpp | 1 + radio/src/targets/taranis/pwr_driver.c | 2 +- 7 files changed, 8 insertions(+), 2 deletions(-) diff --git a/companion/src/firmwares/opentx/opentxGruvin9xsimulator.cpp b/companion/src/firmwares/opentx/opentxGruvin9xsimulator.cpp index fb101b359..bca5842ad 100644 --- a/companion/src/firmwares/opentx/opentxGruvin9xsimulator.cpp +++ b/companion/src/firmwares/opentx/opentxGruvin9xsimulator.cpp @@ -74,6 +74,7 @@ namespace Open9xGruvin9x { #include "radio/src/simpgmspace.cpp" #include "radio/src/templates.cpp" #include "radio/src/translations.cpp" +#include "radio/src/fonts.cpp" #include "radio/src/audio_avr.cpp" #include "radio/src/buzzer.cpp" #include "radio/src/targets/gruvin9x/somo14d.cpp" diff --git a/companion/src/firmwares/opentx/opentxM128simulator.cpp b/companion/src/firmwares/opentx/opentxM128simulator.cpp index a03045c2d..14100e857 100644 --- a/companion/src/firmwares/opentx/opentxM128simulator.cpp +++ b/companion/src/firmwares/opentx/opentxM128simulator.cpp @@ -73,6 +73,7 @@ namespace Open9xM128 { #include "radio/src/simpgmspace.cpp" #include "radio/src/templates.cpp" #include "radio/src/translations.cpp" +#include "radio/src/fonts.cpp" #include "radio/src/audio_avr.cpp" #include "radio/src/targets/stock/voice.cpp" #include "radio/src/telemetry/frsky.cpp" diff --git a/companion/src/firmwares/opentx/opentxSky9xsimulator.cpp b/companion/src/firmwares/opentx/opentxSky9xsimulator.cpp index e17a14be3..0c6fc43b4 100644 --- a/companion/src/firmwares/opentx/opentxSky9xsimulator.cpp +++ b/companion/src/firmwares/opentx/opentxSky9xsimulator.cpp @@ -90,6 +90,7 @@ namespace Open9xSky9x { #include "radio/src/simpgmspace.cpp" #include "radio/src/templates.cpp" #include "radio/src/translations.cpp" +#include "radio/src/fonts.cpp" #include "radio/src/telemetry/frsky.cpp" #include "radio/src/targets/sky9x/audio_driver.cpp" #include "radio/src/audio_arm.cpp" diff --git a/companion/src/firmwares/opentx/opentxTaranisSimulator.cpp b/companion/src/firmwares/opentx/opentxTaranisSimulator.cpp index f147e1fc5..df8e4d197 100644 --- a/companion/src/firmwares/opentx/opentxTaranisSimulator.cpp +++ b/companion/src/firmwares/opentx/opentxTaranisSimulator.cpp @@ -71,7 +71,7 @@ inline int geteepromsize() { #include "radio/src/protocols/ppm_arm.cpp" #include "radio/src/protocols/pxx_arm.cpp" #include "radio/src/protocols/dsm2_arm.cpp" -#include "radio/src/targets/taranis/pwr_driver.cpp" +#include "radio/src/targets/taranis/pwr_driver.c" #include "radio/src/eeprom_common.cpp" #include "radio/src/eeprom_conversions.cpp" #include "radio/src/eeprom_rlc.cpp" @@ -104,6 +104,7 @@ inline int geteepromsize() { #define SDCARD #include "radio/src/templates.cpp" #include "radio/src/translations.cpp" +#include "radio/src/fonts.cpp" #include "radio/src/telemetry/frsky_sport.cpp" #include "radio/src/targets/taranis/audio_driver.cpp" #include "radio/src/audio_arm.cpp" diff --git a/companion/src/firmwares/opentx/opentxsimulator.cpp b/companion/src/firmwares/opentx/opentxsimulator.cpp index dfb7025ea..2124c5865 100644 --- a/companion/src/firmwares/opentx/opentxsimulator.cpp +++ b/companion/src/firmwares/opentx/opentxsimulator.cpp @@ -78,6 +78,7 @@ namespace Open9x { #include "radio/src/telemetry/frsky.cpp" #include "radio/src/templates.cpp" #include "radio/src/translations.cpp" +#include "radio/src/fonts.cpp" #include "radio/src/targets/stock/voice.cpp" #include "radio/src/buzzer.cpp" #include "radio/src/translations/tts_en.cpp" diff --git a/radio/src/simpgmspace.cpp b/radio/src/simpgmspace.cpp index b00c96be7..76a673f12 100644 --- a/radio/src/simpgmspace.cpp +++ b/radio/src/simpgmspace.cpp @@ -638,6 +638,7 @@ void lcdRefresh() #if defined(PCBTARANIS) void usbStart() { } +int usbPlugged() { return false; } void USART_DeInit(USART_TypeDef* ) { } ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) { return SUCCESS; } ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) { return SUCCESS; } diff --git a/radio/src/targets/taranis/pwr_driver.c b/radio/src/targets/taranis/pwr_driver.c index 49930141a..2df7d5d2b 100644 --- a/radio/src/targets/taranis/pwr_driver.c +++ b/radio/src/targets/taranis/pwr_driver.c @@ -35,7 +35,7 @@ */ #include "board_taranis.h" -#include "../pwr.h" +#include "../../pwr.h" void pwrInit() { From b6982a310f3ec9255b1970a7eff5dfe21c663aec Mon Sep 17 00:00:00 2001 From: bsongis Date: Thu, 6 Mar 2014 07:16:17 +0100 Subject: [PATCH 046/285] Version changed to 1.99 for nightly builds --- companion/src/CMakeLists.txt | 2 +- radio/src/Makefile | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/companion/src/CMakeLists.txt b/companion/src/CMakeLists.txt index 73d21daff..7c654cae6 100644 --- a/companion/src/CMakeLists.txt +++ b/companion/src/CMakeLists.txt @@ -1,7 +1,7 @@ PROJECT( companion ) SET( C9X_VERSION_MAJOR "1" ) -SET( C9X_VERSION_MINOR "52" ) +SET( C9X_VERSION_MINOR "99" ) SET( C9X_VERSION ${C9X_VERSION_MAJOR}.${C9X_VERSION_MINOR} ) CMAKE_MINIMUM_REQUIRED( VERSION 2.8 ) diff --git a/radio/src/Makefile b/radio/src/Makefile index e373abd7c..4bda9060e 100644 --- a/radio/src/Makefile +++ b/radio/src/Makefile @@ -272,7 +272,7 @@ MENUS_LOCK == NO SHELL = sh IMG2LBM = -python ../util/img2lbm.py TRANSLATE = -python ../util/translate.py -VERSION = 2.0 +VERSION = 1.99 SRC = CPPSRC = From 47b6c2b771b9e90570f84e224fe9e638d8ddd784 Mon Sep 17 00:00:00 2001 From: bsongis Date: Thu, 6 Mar 2014 12:10:26 +0100 Subject: [PATCH 047/285] Last minute changes before alpha release --- companion/src/mainwindow.cpp | 10 ++++++---- companion/src/mainwindow.h | 2 +- companion/targets/windows/companion-vs.nsi.in | 16 ++++++++-------- companion/targets/windows/license.txt | 4 ++-- 4 files changed, 17 insertions(+), 15 deletions(-) diff --git a/companion/src/mainwindow.cpp b/companion/src/mainwindow.cpp index d419ed99f..aff8ad8cc 100644 --- a/companion/src/mainwindow.cpp +++ b/companion/src/mainwindow.cpp @@ -1530,18 +1530,20 @@ MdiChild *MainWindow::createMdiChild() return child; } -QAction * MainWindow::addAct(QString icon, QString sName, QString lName, QKeySequence::StandardKey shortcut, const char *slot) +QAction * MainWindow::addAct(QString icon, QString sName, QString lName, QKeySequence::StandardKey shortcut, const char *slot, QObject *slotObj) { QAction * newAction = new QAction( this ); if (!icon.isEmpty()) - newAction->setIcon(CompanionIcon(icon)); + newAction->setIcon(CompanionIcon(icon)); if (!sName.isEmpty()) newAction->setText(sName); if (!lName.isEmpty()) newAction->setStatusTip(lName); if (shortcut != 0) newAction->setShortcuts(shortcut); - connect(newAction, SIGNAL(triggered()), this, slot); + if (slotObj == NULL) + slotObj = this; + connect(newAction, SIGNAL(triggered()), slotObj, slot); return newAction; } @@ -1584,7 +1586,7 @@ void MainWindow::createActions() openAct = addAct("open.png", tr("Open Models+Settings..."), tr("Open Models and Settings file"), QKeySequence::Open, SLOT(openFile())); saveAct = addAct("save.png", tr("Save Models+Settings..."), tr("Save Models and Settings file"), QKeySequence::Save, SLOT(save())); saveAsAct = addAct("saveas.png", tr("Save Models+Settings as..."), tr("Save Models and Settings file"), QKeySequence::SaveAs, SLOT(saveAs())); - exitAct = addAct("exit.png", tr("Exit"), tr("Exit the application"), QKeySequence::Quit, SLOT(newFile())); + exitAct = addAct("exit.png", tr("Exit"), tr("Exit the application"), QKeySequence::Quit, SLOT(closeAllWindows()), qApp); cutAct = addAct("cut.png", tr("Cut Model"), tr("Cut current model to the clipboard"), QKeySequence::Cut, SLOT(cut())); copyAct = addAct("copy.png", tr("Copy Model..."), tr("Copy current model to the clipboard"), QKeySequence::Copy, SLOT(copy())); pasteAct = addAct("paste.png", tr("Paste Model..."), tr("Paste model from clipboard"), QKeySequence::Paste, SLOT(paste())); diff --git a/companion/src/mainwindow.h b/companion/src/mainwindow.h index 8bfca1fa8..37535e94b 100644 --- a/companion/src/mainwindow.h +++ b/companion/src/mainwindow.h @@ -158,7 +158,7 @@ private slots: private: void createActions(); - QAction * addAct(QString, QString, QString, QKeySequence::StandardKey, const char *); + QAction * addAct(QString, QString, QString, QKeySequence::StandardKey, const char *, QObject *slotObj=NULL); QAction * addAct(QActionGroup *, QString, QString, const char *); QAction * addAct(QString, QString, QString, const char *); diff --git a/companion/targets/windows/companion-vs.nsi.in b/companion/targets/windows/companion-vs.nsi.in index 64432c62d..7ce8351fb 100644 --- a/companion/targets/windows/companion-vs.nsi.in +++ b/companion/targets/windows/companion-vs.nsi.in @@ -12,14 +12,14 @@ ;General ;Name and file - Name "OpenTX companion" + Name "OpenTX Companion" OutFile "companionInstall_v@C9X_VERSION@.exe" ;Default installation folder - InstallDir "$PROGRAMFILES\OpenTX companion" + InstallDir "$PROGRAMFILES\OpenTX" ;Get installation folder from registry if available - InstallDirRegKey HKCU "Software\companion9x" "" + InstallDirRegKey HKCU "Software\OpenTX" "" ;Compressor options SetCompressor /FINAL /SOLID lzma @@ -66,7 +66,7 @@ ;Start Menu Folder Page Configuration !define MUI_STARTMENUPAGE_REGISTRY_ROOT "HKCU" - !define MUI_STARTMENUPAGE_REGISTRY_KEY "Software\companion9x" + !define MUI_STARTMENUPAGE_REGISTRY_KEY "Software\OpenTX" !define MUI_STARTMENUPAGE_REGISTRY_VALUENAME "Start Menu Folder" !insertmacro MUI_PAGE_STARTMENU Application $StartMenuFolder @@ -77,7 +77,7 @@ !define MUI_FINISHPAGE_NOAUTOCLOSE !define MUI_FINISHPAGE_RUN !define MUI_FINISHPAGE_RUN_CHECKED - !define MUI_FINISHPAGE_RUN_TEXT "Launch companion" + !define MUI_FINISHPAGE_RUN_TEXT "Launch OpenTX Companion" !define MUI_FINISHPAGE_RUN_FUNCTION "LaunchLink" # !define MUI_FINISHPAGE_SHOWREADME_NOTCHECKED # !define MUI_FINISHPAGE_SHOWREADME $INSTDIR\readme.txt @@ -95,7 +95,7 @@ ;-------------------------------- ;Installer Sections -Section "OpenTX companion" SecDummy +Section "OpenTX Companion" SecDummy SetOutPath "$INSTDIR" @@ -129,7 +129,7 @@ Section "OpenTX companion" SecDummy SetOutPath "$INSTDIR" ;Store installation folder - WriteRegStr HKCU "Software\companion9x" "" $INSTDIR + WriteRegStr HKCU "Software\OpenTX" "" $INSTDIR ;Associate with extentions ,bin and .hex ${registerExtension} "$INSTDIR\companion.exe" ".bin" "BIN_File" @@ -207,7 +207,7 @@ Section "Uninstall" Delete "$SMPROGRAMS\$StartMenuFolder\Uninstall.lnk" RMDir "$SMPROGRAMS\$StartMenuFolder" - DeleteRegKey /ifempty HKCU "Software\companion9x" + DeleteRegKey /ifempty HKCU "Software\OpenTX" SectionEnd diff --git a/companion/targets/windows/license.txt b/companion/targets/windows/license.txt index 62dda6edd..383da8e36 100644 --- a/companion/targets/windows/license.txt +++ b/companion/targets/windows/license.txt @@ -1,6 +1,6 @@ -Copyright 2011-2013 Bertrand Songis and Romolo Manfredini +Copyright 2011-2014 OpenTX team -companion9x is based on code named eePe by author - Erez Raviv +OpenTX Companion is based on code named eePe by author - Erez Raviv This software is provided 'as-is', without any express or implied warranty. In no event will the authors be held liable for any damages arising from the use of this software. From eeb5532ffa8a91f05607a3fc57700a4e6d5e48ae Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Thu, 6 Mar 2014 22:11:18 +0100 Subject: [PATCH 048/285] Update DONATIONS.txt --- DONATIONS.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/DONATIONS.txt b/DONATIONS.txt index 7c003ccfd..f569f5bf2 100644 --- a/DONATIONS.txt +++ b/DONATIONS.txt @@ -334,3 +334,4 @@ Roberto Orsello David Finger FrSky - www.frsky-rc.com Jean-marie Oddo +Mike Matheny From 56032872046486f40b93166ab526b14fdf762b74 Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Thu, 6 Mar 2014 22:11:33 +0100 Subject: [PATCH 049/285] Update DONATIONS.txt --- DONATIONS.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/DONATIONS.txt b/DONATIONS.txt index f569f5bf2..f12ab0c37 100644 --- a/DONATIONS.txt +++ b/DONATIONS.txt @@ -333,5 +333,5 @@ Sean Cull Roberto Orsello David Finger FrSky - www.frsky-rc.com -Jean-marie Oddo +Jean-Marie Oddo Mike Matheny From cea4c89fe2f79f843075bf7a05535747adadedaa Mon Sep 17 00:00:00 2001 From: Kjell Kernen Date: Sat, 8 Mar 2014 15:25:22 +0100 Subject: [PATCH 050/285] Turned down the light green color hue od curve 11, 12, 13 to be more readable. Fixes #479 --- companion/src/printdialog.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/companion/src/printdialog.cpp b/companion/src/printdialog.cpp index 215771347..0988a86ae 100644 --- a/companion/src/printdialog.cpp +++ b/companion/src/printdialog.cpp @@ -530,9 +530,9 @@ void printDialog::printCurves() qplot_color[7]=new QColor(0,0,255); qplot_color[8]=new QColor(0,127,255); qplot_color[9]=new QColor(127,0,255); - qplot_color[10]=new QColor(0,255,0); - qplot_color[11]=new QColor(0,255,127); - qplot_color[12]=new QColor(127,255,0); + qplot_color[10]=new QColor(0,200,0); + qplot_color[11]=new QColor(0,200,127); + qplot_color[12]=new QColor(127,200,0); qplot_color[13]=new QColor(255,0,0); qplot_color[14]=new QColor(255,0,127); qplot_color[15]=new QColor(255,127,0); From 02268c54ff947d3b3324169841c126e236bee426 Mon Sep 17 00:00:00 2001 From: Kjell Kernen Date: Sat, 8 Mar 2014 23:34:15 +0100 Subject: [PATCH 051/285] Fixes #784 --- companion/src/modeledit/customfunctions.cpp | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/companion/src/modeledit/customfunctions.cpp b/companion/src/modeledit/customfunctions.cpp index b1805df46..e4c9ddadb 100644 --- a/companion/src/modeledit/customfunctions.cpp +++ b/companion/src/modeledit/customfunctions.cpp @@ -161,6 +161,12 @@ CustomFunctionsPanel::CustomFunctionsPanel(QWidget * parent, ModelData & model, connect(fswtchParamArmT[i], SIGNAL(editTextChanged ( const QString)), this, SLOT(customFunctionEdited())); #ifdef PHONON + phononLock=false; + clickObject = new Phonon::MediaObject(this); + clickOutput = new Phonon::AudioOutput(Phonon::NoCategory, this); + Phonon::createPath(clickObject, clickOutput); + connect(clickObject, SIGNAL(stateChanged(Phonon::State,Phonon::State)), this, SLOT(mediaPlayer_state(Phonon::State,Phonon::State))); + playBT[i] = new QPushButton(this); playBT[i]->setProperty("index", i); playBT[i]->setProperty("state", "play"); @@ -203,6 +209,7 @@ void CustomFunctionsPanel::mediaPlayer_state(Phonon::State newState, Phonon::Sta clickObject->clearQueue(); clickObject->clear(); for (int i=0; igetCapability(CustomFunctions); i++) { + playBT[i]->setProperty("state", "play"); playBT[i]->setObjectName(QString("play_%1").arg(i)); playBT[i]->setIcon(CompanionIcon("play.png")); } From d5da0ad8286f7ef9350781d6fb37392f8fba193c Mon Sep 17 00:00:00 2001 From: Kjell Kernen Date: Sun, 9 Mar 2014 16:06:19 +0100 Subject: [PATCH 052/285] Start of the Finnish translation of Companion made by Janne Huskonen --- companion/src/translations/companion_fi.ts | 12936 ++++++++----------- 1 file changed, 5164 insertions(+), 7772 deletions(-) diff --git a/companion/src/translations/companion_fi.ts b/companion/src/translations/companion_fi.ts index 96023cc65..e7516fdcc 100644 --- a/companion/src/translations/companion_fi.ts +++ b/companion/src/translations/companion_fi.ts @@ -4,409 +4,297 @@ Channels - Name - + Nimi - Offset - + Tasoitus - Min - + Min - Max - + Max - Invert - + Käänteinen - Center - + Keski - Sym - + Sym - Channel %1 - + Kanava %1 - --- - + --- - INV - + KÄÄNT CurveGroup - Diff - + Ero - Expo - + Expo - Func - + Toiminto - Curve - + Käyrä Curves - Form - + Käyrät - Standard - + Vakio - Custom - + Omat - Lines - + Viivat - Smooth - + Pehmeä - Curve type - + Käyrän tyyppi - Curve name - + Käyrän nimi - Curve %1 - + Käyräi %1 - %1 points - + %1 pisteet - Are you sure you want to reset curve %1 ? - + Oletko varma että haluat palauttaa käyrän %1 ? - Editing curve %1 - + Muutetaan käyrää %1 - Not enough free points in EEPROM to store the curve. - + Ei vapaata tilaa EEPROMissa tallentaa käyrää. CustomFunctionsPanel - Switch - + Kytkin - Action - + Toiminto - Parameters - + Parametrit - Enable - + Päälle - CF%1 - + OF%1 - ON - + ON - Error - + Virhe - Unable to find sound file %1! - + Äänitiedostoa ei löydy %1! - &Delete - + &Poista - Delete - + Poista - &Copy - + &Kopio - Ctrl+C - + Ctrl+C - &Cut - + &Leikkaa - Ctrl+X - + Ctrl+X - &Paste - + &Liitä - Ctrl+V - + Ctrl+V Dialog - Dialog - + Käyrä - Curve type - + Tyyppi - Coefficient - + Vaikutus - Both - + Molemmat - x>0 - + x>0 - x<0 - + x<0 - Y at X=0 - + Y suhde X =0 - Side - + Sivu - Y at X=-100 - + Y suhde X =-100 - Y at X=100 - + Y suhde X =100 - Linear - + Suora - Single Expo - + yks expo - Symmetrical f(x)=-f(-x) - + Symmetrinen f(x)=-f(-x) - Symmetrical f(x)=f(-x) - + Symmetrinen f(x)=f(-x) ExpoDialog - - The source for the mixer - - - - - Input name - - - - - Weight - - - - - - GV - - - - - Phase used by the input. - - - - - Flight modes - - - - 0 - + 0 - 1 - + 1 - 2 - + 2 - 3 - + 3 - 4 - + 4 - 5 - + 5 - 6 - + 6 - 7 - + 7 - 8 - + 8 - Switch - + Kytkin - - Switch used by the input. -If blank then the input is considered to be "ON" all the time. - - - - - Stick Side - - - - NEG - + NEG - POS - + POS - ALL - + Kaikki - <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -418,70 +306,100 @@ p, li { white-space: pre-wrap; } <p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">If Delay is not zero the actuation of the mix will be delayed by the specified amount of seconds.</p> <p style="-qt-paragraph-type:empty; margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"></p> <p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">If Slow is not zero then the speed of the mix will be set by the value specified -&gt; the value states the number of seconds it takes to transit from -100 to 100.</p></body></html> + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> +<html><head><meta name="qrichtext" content="1" /><style type="text/css"> +p, li { white-space: pre-wrap; } +</style></head><body style=" font-family:'MS Shell Dlg 2'; font-size:8.25pt; font-weight:400; font-style:normal;"> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-weight:600; text-decoration: underline;">Delay ans Slow</span></p> +<p style="-qt-paragraph-type:empty; margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px; font-weight:600; text-decoration: underline;"></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">These values control the speed and delay of the output of the mix. </p> +<p style="-qt-paragraph-type:empty; margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">If Delay is not zero the actuation of the mix will be delayed by the specified amount of seconds.</p> +<p style="-qt-paragraph-type:empty; margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">If Slow is not zero then the speed of the mix will be set by the value specified -&gt; the value states the number of seconds it takes to transit from -100 to 100.</p></body></html> + + + No + Ei + + + Yes + Kyllä + + + Curve + Käyrä + + + Source + Lähde + + + The source for the mixer + + + + Input name + + + + Weight + + + + GV + + + + Phase used by the input. + + + + Flight modes + + + + Switch used by the input. +If blank then the input is considered to be "ON" all the time. + + + + Stick Side - Scale - Include Trim - - No - - - - - Yes - - - - - Curve - - - - The curve used by the input - - Source - - - - Line name - Edit %1 - Rud - Ele - Thr - Ail @@ -489,77 +407,62 @@ p, li { white-space: pre-wrap; } FlightMode - Form - Fade In - Fade Out - Name - + Nimi - Switch - + Kytkin - trim1 - trim2 - trim4 - trim3 - Rud - Ele - Thr - Ail - Rotary Encoder %1 - GVAR%1 @@ -567,338 +470,123 @@ p, li { white-space: pre-wrap; } FlightModes - Flight Mode %1 - + Lentotila %1 - (%1) - + (%1) - (default) - + (oletus) GeneralEdit - General Edit - + Yleiset muutokset - - Retrieve calib. and hw settings from profile - - - - - Store calib. and hw settings in selected profile - - - - - General settings used throught the transmitter. -These will be relevant for all models in the same EEPROM. - - - - Setup - + Asetukset - Country Code - + Maa koodi - America - + Amerikka - Japan - + Japani - Europe - + Eurooppa - - MAVLink Baud Rate - - - - Voice Language - + Äänen kieli - - Measurement Units - - - - <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } </style></head><body style=" font-family:'MS Shell Dlg 2'; font-size:8.25pt; font-weight:400; font-style:normal;"> <p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-size:8pt;">Single Beep Every whole Minute</span></p></body></html> - + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> +<html><head><meta name="qrichtext" content="1" /><style type="text/css"> +p, li { white-space: pre-wrap; } +</style></head><body style=" font-family:'MS Shell Dlg 2'; font-size:8.25pt; font-weight:400; font-style:normal;"> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-size:8pt;">Single Beep Every whole Minute</span></p></body></html> - Every Minute - + Joka minuutti - - Beeps at 30, 15, 10, and down from5 seconds - - - - - Count Down to Zero - - - - <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } </style></head><body style=" font-family:'MS Shell Dlg 2'; font-size:8.25pt; font-weight:400; font-style:normal;"> <p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-size:8pt;">Flash backlight on timer beep</span></p></body></html> - + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> +<html><head><meta name="qrichtext" content="1" /><style type="text/css"> +p, li { white-space: pre-wrap; } +</style></head><body style=" font-family:'MS Shell Dlg 2'; font-size:8.25pt; font-weight:400; font-style:normal;"> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-size:8pt;">Flash backlight on timer beep</span></p></body></html> - - Flash on beep - - - - - Beep volume - - - - - Wav volume - - - - - Vario volume - - - - - Background volume - - - - - PPMSim - - - - 4800 Baud - + 4800 Baudia - 9600 Baud - + 9600 Baudia - 14400 Baud - + 14400 Baudia - 19200 Baud - + 19200 Baudia - 38400 Baud - + 38400 Baudia - 57600 Baud - + 57600 Baudia - 76800 Baud - + 76800 Baudia - 115200 Baud - + 115200 Baudia - - Beeper Length - - - - - Pot Scrolling Enable - - - - - <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } </style></head><body style=" font-family:'MS Shell Dlg 2'; font-size:8.25pt; font-weight:400; font-style:normal;"> <p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-size:8pt;">LCD Screen Contrast</span></p> <p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-size:8pt;">Values can be 20-45</span></p></body></html> - + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> +<html><head><meta name="qrichtext" content="1" /><style type="text/css"> +p, li { white-space: pre-wrap; } +</style></head><body style=" font-family:'MS Shell Dlg 2'; font-size:8.25pt; font-weight:400; font-style:normal;"> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-size:8pt;">LCD Screen Contrast</span></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-size:8pt;">Values can be 20-45</span></p></body></html> - - Haptic Length - - - - - Mode selection: - -Mode 1: - Left stick: Elevator, Rudder - Right stick: Throttle, Aileron - -Mode 2: - Left stick: Throttle, Rudder - Right stick: Elevator, Aileron - -Mode 3: - Left stick: Elevator, Aileron - Right stick: Throttle, Rudder - -Mode 4: - Left stick: Throttle, Aileron - Right stick: Elevator, Rudder - - - - - - - Mode 1 (RUD ELE THR AIL) - - - - - Mode 2 (RUD THR ELE AIL) - - - - - Mode 3 (AIL ELE THR RUD) - - - - - Mode 4 (AIL THR ELE RUD) - - - - - LCD Display Type - - - - - BackLight On Stick Move - - - - - - sec - - - - - Beeper Mode - - - - - Timeshift from UTC - - - - - RotEnc Navigation - - - - - FrSky Internal Alarm - - - - - THR - - - - - RUD - - - - - ELE - - - - - AIL - - - - - GEA - - - - - ID0 - - - - - ID1 - - - - - ID2 - - - - - - - - <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -910,5719 +598,4736 @@ p, li { white-space: pre-wrap; } <p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">Switch warning - will alert if switches are not in their defaul position</p> <p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">Memory warning - will alert if there's not a lot of memory left</p> <p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">Silent mode warning - will alert you if the beeper is set to quiet (0)</p></body></html> - - - - - GPS Coordinates - - - - - hh° (N/S) mm' ss''.dd - - - - - NMEA - - - - - If you enable FAI, you loose the vario, the play functions, the telemetry screen. This function cannot be disabled by the radio. - - - - - Channel order - -This is used by the templated to determine which channel goes to what number output. - - - - - R E T A - - - - - R E A T - - - - - R T E A - - - - - R T A E - - - - - R A E T - - - - - R A T E - - - - - E R T A - - - - - E R A T - - - - - E T R A - - - - - E T A R - - - - - E A R T - - - - - E A T R - - - - - T R E A - - - - - T R A E - - - - - T E R A - - - - - T E A R - - - - - T A R E - - - - - T A E R - - - - - A R E T - - - - - A R T E - - - - - A E R T - - - - - A E T R - - - - - A T R E - - - - - A T E R - - - - - Show Owner Name on Splash - - - - - Speaker Pitch (spkr only) - - - - - - X-Short - - - - - - Short - - - - - - Normal - - - - - - Long - - - - - - X-Long - - - - - StickScroll - - - - - FAI Mode - - - - - Haptic Strength - - - - - Beeper - - - - - Speaker - - - - - BeeperVoice - - - - - SpeakerVoice - - - - - Show Splash Screen on Startup - - - - - Metric - - - - - Imperial - - - - - Channel Order (For Templates) - - - - - Stick Mode - - - - - Haptic Mode - - - - - Owner Name - - - - - BackLight Invert - - - - - Standard - - - - - Optrex - - - - - - Show splash screen on startup - - - - - - Quiet - - - - - Only Alarms - - - - - - No Keys - - - - - - All - - - - - - - - - - - - - - - Beeper volume - -0 - Quiet. No beeps at all. -1 - No Keys. Normal beeps but menu keys do not beep. -2 - Normal. -3 - Loud. -4 - Extra loud. - - - - - Alarms Only - - - - - If this value is not 0, any keypress will turn on the backlight and turn it off after the specified number of seconds. - - - - - Timer Beeps - - - - - BackLight Brightness - - - - - Contrast - - - - - BackLight Auto OFF after - - - - - Single - - - - - Oversample - - - - - Filter - - - - - This is the switch selectrion for turning on the backlight (if installed). - - - - - - - Bandgap Measuring Enable - - - - - Input Filter - - - - - CrossTrim - - - - - Sound Mode - - - - - BackLight Switch - - - - - Battery calibration: -This value will be added to the measured battery voltage. Use this value to calibrate the meter with an external meter. - - - - - Battery Calibration - - - - - Battery Warning - - - - - Battery warning voltage. -This is the threashhold where the battery warning sounds. - -Acceptable values are 5v..10v - - - - - Telemetry NO DATA Alarm - - - - - Readonly Unlock - - - - - Speaker Volume - - - - - If not zero will sound beeps if the transmitter has been left without inputs for the specified number of minutes. - - - - - min - - - - - Inactivity Timer - - - - - SC - - - - - SE - - - - - SA - - - - - SF - - - - - SH - - - - - SD - - - - - SB - - - - - SG - - - - - Alarm Warning - - - - - Memory Startup Warning - - - - - Trainer - - - - - Mode - - - - - Input - - - - - Weight - - - - - Switch - - - - - - PPM 1 - - - - - - - - Off - - - - - - - - += (Sum) - - - - - - - - := (Replace) - - - - - - - - chn1 - - - - - - - - chn2 - - - - - - - - chn3 - - - - - - - - chn4 - - - - - - PPM 2 - - - - - - PPM 3 - - - - - - PPM 4 - - - - - Telemetry - - - - - RSSI Alarm 1 - - - - - - ---- - - - - - - Yellow - - - - - - Orange - - - - - - Red - - - - - RSSI Alarm 2 - - - - - NO DATA Alarm - - - - - Calibration - - - - - POT 4 - - - - - POT 3 - - - - - POT 2 - - - - - POT 1 - - - - - STICK 3 - - - - - - Negative span - - - - - - Mid value - - - - - - Positive span - - - - - STICK 1 - - - - - STICK 2 - - - - - STICK 4 - - - - - Battery - - - - - v - - - - - PPM Multiplier - - - - - Current - - - - - - Pot (normal) - - - - - - Multipos Switch - - - - - S1 Type - - - - - S2 Type - - - - - If you enable FAI, you loose the vario, the play functions, the telemetry screen. -This function cannot be disabled by the radio. -Are you sure ? - - - - - - Warning - - - - - Wrong data in profile, radio calibration was not retrieved - - - - - Wrong data in profile, hw related parameters were not retrieved - - - - - Do you want to store calibration in %1 profile<br>overwriting existing calibration? - - - - - Calibration and HW parameters saved. - - - - - Heli - - - Form - - - - - Invert Elevator - - - - - Invert Aileron - - - - - Invert Collective - - - - - Invert - - - - - Off - - - - - 120 - - - - - 120X - - - - - 140 - - - - - 90 - - - - - Collective - - - - - Swash Type - - - - - Swash Ring - - - - - InputsPanel - - - - Move Up - - - - - - Ctrl+Up - - - - - - Move Down - - - - - - Ctrl+Down - - - - - Clear All Settings - - - - - Source(%1) - - - - - No Trim - - - - - Weight(%1) - - - - - Switch(%1) - - - - - Not enough available inputs! - - - - - Delete Selected Inputs? - - - - - &Add - - - - - Ctrl+A - - - - - &Edit - - - - - Enter - - - - - &Delete - - - - - Delete - - - - - &Copy - - - - - Ctrl+C - - - - - &Cut - - - - - Ctrl+X - - - - - &Paste - - - - - Ctrl+V - - - - - Du&plicate - - - - - Ctrl+U - - - - - Clear Inputs? - - - - - Really clear all the inputs? - - - - - LogicalSwitchesPanel - - - Condition - - - - - V1 - - - - - V2 - - - - - AND - - - - - Duration - - - - - Delay - - - - - - LS%1 - - - - - &Delete - - - - - Delete - - - - - &Copy - - - - - Ctrl+C - - - - - &Cut - - - - - Ctrl+X - - - - - &Paste - - - - - Ctrl+V - - - - - MainWindow - - - - - - File loaded - - - - - Display previous warning again at startup ? - - - - - Display previous message again at startup ? - - - - - Checking for updates - - - - - - - - - Unable to check for updates. - - - - - A new version of Companion is available (version %1)<br>Would you like to download it? - - - - - - - - - Save As - - - - - Executable (*.exe) - - - - - New release available - - - - - A new release of Companion is available please check the OpenTX website! - - - - - - No updates available at this time. - - - - - Would you like to launch the installer? - - - - - - - - - - - - - - - - - Error - - - - - - - - - Error opening file %1: -%2. - - - - - Firmware does not longer fit in the Tx, due to selected firmware options - - - - - Compilation server temporary failure, try later - - - - - - Compilation server too busy, try later - - - - - - Compilation server requires registration, please check OpenTX web site - - - - - - Unknown server failure, try later - - - - - Firmware does not fit in the Tx, due to selected firmware options - - - - - Compilation server termporary failure, try later - - - - - Do you want to write the firmware to the transmitter now ? - - - - - Firmware %1 does not seem to have ever been downloaded. -Version %2 is available. -Do you want to download it now ? - - - - - - Yes - - - - - - No - - - - - - Release Notes - - - - - - Do you want to download release %1 now ? - - - - - A new version of %1 firmware is available (current %2 - newer %3). -Do you want to download it now ? - - - - - Ignore this version (r%1)? - - - - - Release notes contain very important informations. Do you want to see them now ? - - - - - The selected language will be used the next time you start Companion. - - - - - - - OK - - - - - The new theme will be loaded the next time you start Companion. - - - - - The icon size will be used the next time you start Companion. - - - - - Open - - - - - - File saved - - - - - Firmware updates - - - - - Current firmware does not provide release notes informations. - - - - - Cannot write file %1: -%2. - - - - - - - - - Taranis radio not found - - - - - - - - Impossible to identify the radio on your system, please verify the eeprom disk is connected. - - - - - - - - - Read Models and Settings From Tx - - - - - Write Models and settings from %1 to the Tx? - - - - - The file %1 -has not been recognized as a valid Models and Settings file -Write anyway ? - - - - - - - Backup is impossible - - - - - - - The backup dir set in preferences does not exist - - - - - - - - - - Backup Models and Settings From Tx - - - - - Cannot check Models and Settings compatibility! Continue anyway? - - - - - - Warning - - - - - The transmitter firmware belongs to another product family, check file and preferences! - - - - - The transmitter firmware is outdated, please upgrade! - - - - - - Write Models and Settings To Tx - - - - - - Write Firmware To Tx - - - - - Conversion failed - - - - - Cannot convert Models and Settings for use with this firmware, original data will be used - - - - - Restore Models and Settings To Tx - - - - - Restore failed - - - - - Could not restore Models and Settings to TX. The models and settings data file can be found at: %1 - - - - - Firmware write failed - - - - - Could not write firmware to to transmitter. The models and settings data file can be found at: %1 - - - - - Backup failed - - - - - Cannot backup existing Models and Settings from TX. Firmware write process aborted - - - - - Save transmitter Models and Settings to File - - - - - Impossible to identify the radio on your system, please verify that the eeprom disk is connected. - - - - - Read Tx Firmware to File - - - - - OpenTX Home Page: <a href='%1'>%1</a> - - - - - The OpenTX Companion project was originally forked from <a href='%2'>eePe</a> - - - - - If you've found this program useful, please support by <a href='%1'>donating</a> - - - - - Version %1, %3 - - - - - Copyright - - - - - About Companion - Noin Companion - - - - OpenTX Companion - FW: %1 - Profile: %2 - - - - - - New - - - - - Create a new file - - - - - Open... - - - - - Open an existing file - - - - - Save... - - - - - - Save the document to disk - - - - - Save As... - - - - - Exit - - - - - Exit the application - - - - - Cut - - - - - Cut current selection to the clipboard - - - - - Copy... - - - - - Copy current selection to the clipboard - - - - - Paste... - - - - - Paste clipboard into current selection - - - - - Classical - - - - - The classical Companion icon theme - - - - - The new Companion 2 icon theme - - - - - Monochrome - - - - - A monochrome black icon theme - - - - - MonoWhite - - - - - A monochrome white icon theme - - - - - MonoBlue - - - - - A monochrome blue icon theme - - - - - Small - - - - - Use small toolbar icons - - - - - Normal - - - - - Use normal size toolbar icons - - - - - Big - - - - - Use big toolbar icons - - - - - Huge - - - - - Use huge toolbar icons - - - - - System language - - - - - Use system language in menus - - - - - Czech - - - - - Use Czech in menus - - - - - German - - - - - Use German in menus - - - - - English - - - - - Use English in menus - - - - - French - - - - - Use French in menus - - - - - Italian - - - - - Use Italian in menus - - - - - Hebrew - - - - - Use Hebrew in menus - - - - - Polish - - - - - Use Polish in menus - - - - - Portuguese - - - - - Use Portuguese in menus - - - - - Swedish - - - - - Use Swedish in menus - - - - - Russian - - - - - Use Russian in menus - - - - - About - Noin - - - - Show the application's About box - - - - - Print - - - - - Print current model - - - - - Simulate - - - - - Simulate selected model - - - - - loadBackup... - - - - - Load backup from file - - - - - Logs - - - - - Open log file - - - - - Setting... - - - - - Edit Settings - - - - - Downloads... - - - - - Download firmware and voice files - - - - - Check for updates... - - - - - Check OpenTX and Companion updates - - - - - ChangeLog... - - - - - Show Companion changelog - - - - - Firmware ChangeLog... - - - - - Show firmware changelog - - - - - Compare... - - - - - Compare models - - - - - Edit Tx Splash Image... - - - - - edit the splash screen of your TX - - - - - List programmers - - - - - List available programmers - - - - - Fuses... - - - - - Show fuses dialog - - - - - Read Firmware - - - - - Read firmware from transmitter - - - - - Write Firmware - - - - - Write firmware to transmitter - - - - - New Profile - - - - - Create a new Radio Setting Profile - - - - - Manuals and other Documents - - - - - Open the OpenTX document page in a web browser - - - - - Write Models and Settings to transmitter - - - - - Read Models and Settings from transmitter - - - - - Configure connection software... - - - - - Configure software for reading from and writing to the transmitter - - - - - Write Models and Settings from file to Tx - - - - - Write Models and Settings from file to transmitter - - - - - Save Tx Models and Settings to file - - - - - Save the Models and Settings from the transmitter to a file - - - - - Contributors - - - - - A tribute to those who have contributed to OpenTX and Companion - - - - - - Recent Files - - - - - Set Menu Language - - - - - Set Icon Theme - - - - - Set Icon Size - - - - - - File - - - - - - Edit - - - - - Settings - - - - - Read/Write - - - - - - Help - - - - - Radio Settings Profiles - - - - - Show a selection list of recent documents - - - - - Radio Profiles - - - - - Show a selection list of radio settings profiles - - - - - Write - - - - - Ready - - - - - - &%1 %2 - - - - - Unable to find file %1! - - - - - - Invalid Models and Settings File %1 - - - - - Error reading file %1: -%2. - - - - - Invalid binary Models and Settings File %1 - - - - - MdiChild - - - free bytes - - - - - - - Companion - - - - - Do you want to use model wizard? - - - - - Ask this question again ? - - - - - Editing model %1: - - - - - - - - - - - - - - - - - - - - - - - Error - - - - - - Unable to find file %1! - - - - - - - - Error opening file %1: -%2. - - - - - - Invalid EEPROM File %1 - - - - - - Error reading file %1: -%2. - - - - - Invalid binary EEPROM File %1 - - - - - - - - Save As - - - - - - - - Cannot write file %1: -%2. - - - - - - Error writing file %1: -%2. - - - - - %1 has been modified. -Do you want to save your changes? - - - - - Backup is impossible - - - - - The backup dir set in preferences does not exist - - - - - Cannot write temporary file! - - - - - - - Taranis radio not found - - - - - - - Impossible to identify the radio on your system, please verify the eeprom disk is connected. - - - - - - - Backup EEPROM From Tx - - - - - Cannot check eeprom compatibility! Continue anyway? - - - - - - Warning - - - - - Firmware in radio is of a different family of eeprom written, check file and preferences! - - - - - Firmware in flash is outdated, please upgrade! - - - - - Write EEPROM To Tx - - - - - Open - - - - - Invalid binary backup File %1 - - - - - MixerDialog - - - Dialog - - - - - Delay - - - - - Slow - - - - - Up - - - - - Down - - - - - - - - <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } </style></head><body style=" font-family:'MS Shell Dlg 2'; font-size:8.25pt; font-weight:400; font-style:normal;"> -<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-weight:600; text-decoration: underline;">Delay ans Slow</span></p> -<p style="-qt-paragraph-type:empty; margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px; font-weight:600; text-decoration: underline;"></p> -<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">These values control the speed and delay of the output of the mix. </p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" text-decoration: underline;">Warnings</span></p> <p style="-qt-paragraph-type:empty; margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"></p> -<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">If Delay is not zero the actuation of the mix will be delayed by the specified amount of seconds.</p> -<p style="-qt-paragraph-type:empty; margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"></p> -<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">If Slow is not zero then the speed of the mix will be set by the value specified -&gt; the value states the number of seconds it takes to transit from -100 to 100.</p></body></html> - +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">These will define startup warnings.</p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">Throttle warning - will alert if the throttle is not at idle during startup</p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">Switch warning - will alert if switches are not in their defaul position</p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">Memory warning - will alert if there's not a lot of memory left</p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">Silent mode warning - will alert you if the beeper is set to quiet (0)</p></body></html> - - Include Trim - + RSSI Alarm 1 + RSSI häly 1 - - Offset - - - - - Weight - - - - - 0 - - - - - 1 - - - - - 2 - - - - - 3 - - - - - 4 - - - - - 5 - - - - - 6 - - - - - 7 - - - - - 8 - - - - - Name - - - - - Source - - - - - Multiplex - - - - - Warning - - - - - The curve used by the mix - - - - - Include DR/Expo - - - - - Flight modes - - - - - Switch - - - - - Mixer warning. -Setting this value will cause a beep to be emmitted when this value is active. - - - - - OFF - - - - - 1 Beep - - - - - 2 Beep - - - - - 3 Beep - - - - - No - - - - - Yes - - - - - - - GV - - - - - - - - The source for the mixer - - - - - Multiplexer - -This determines how mixer values are added. - -"+" means the value of the current mix is added to the previous mixes in the same channel. -"*" means the value of the current mix is amultiplied with the previous mixes in the same channel. -"R" means the value replaces the previous values. If the switch is off the value will be ignored. - - - - - ADD - - - - - MULTIPLY - - - - - REPLACE - - - - - Curve - - - - - Switch used by the mix. -If blank then the mix is considered to be "ON" all the time. - - - - - DEST -> X%1 - - - - - DEST -> CH%1%2 - - - - - Rud - - - - - Ele - - - - - Thr - - - - - Ail - - - - - MixesPanel - - - - Move Up - - - - - - Ctrl+Up - - - - - - Move Down - - - - - - Ctrl+Down - - - - - Clear Mixes - - - - - - - X%1 - - - - - - - CH%1%2 - - - - - Weight(%1) - - - - - Switch(%1) - - - - - No Trim - - - - - No DR/Expo - - - - - Offset(%1) - - - - - Delay(u%1:d%2) - - - - - Slow(u%1:d%2) - - - - - Warn(%1) - - - - - Not enough available mixers! - - - - - Delete Selected Mixes? - - - - - &Add - - - - - Ctrl+A - - - - - &Edit - - - - - Enter - - - - - &Delete - - - - - Delete - - - - - &Copy - - - - - Ctrl+C - - - - - &Cut - - - - - Ctrl+X - - - - - &Paste - - - - - Ctrl+V - - - - - Du&plicate - - - - - Ctrl+U - - - - - Clear Mixes? - - - - - Really clear all the mixes? - - - - - ModelEdit - - - Dialog - - - - - Simulate - - - - - Clear Curves? - - - - - Really clear all the curves? - - - - - Setup - - - - - Heli - - - - - Flight Modes - - - - - Inputs - - - - - Mixes - - - - - Channels - - - - - Logical Switches - - - - - Switch Assignment - - - - - Curves - - - - - Telemetry - - - - - ModelsListWidget - - - &Edit - - - - - &Restore from backup - - - - - &Model Wizard - - - - - &Delete - - - - - Delete - - - - - &Copy - - - - - Ctrl+C - - - - - &Cut - - - - - Ctrl+X - - - - - &Paste - - - - - Ctrl+V - - - - - D&uplicate - - - - - Ctrl+U - - - - - &Use as default - - - - - P&rint model - - - - - Alt+R - - - - - &Simulate model - - - - - Alt+S - - - - - General Settings - - - - - Delete Selected Models? - - - - - - Cannot delete default model. - - - - - Cannot cut default model. - - - - - Do you want to overwrite TX general settings? - - - - - You are pasting on an not empty model, are you sure? - - - - - No free slot available, cannot duplicate - - - - - Module - - - Form - - - - - Failsafe Mode - - - - - Start - - - - - PPM delay - - - - - usec - - - - - Negative - - - - - Positive - - - - - RX Number - - - - - Master - - - - - Slave - - - - - Polarity - - - - - Trainer Mode - - - - - mSec - - - - - PPM Frame Length - - - - - Label - - - - - - ch - - - - - Channels - - - - - Hold - - - - - Custom - - - - - No Pulses - - - - - Failsafe Positions - - - - - Protocol - - - - - ModulePanel - - - Trainer Output - - - - - Internal Radio System - - - - - External Radio Module - - - - - QObject - - - FW: %1 - - - - - Pict: %1 - - - - - Profile image - - - - - - Rud - - - - - - Ele - - - - - - Thr - - - - - - Ail - - - - - - - P1 - - - - - - - P2 - - - - - - - P3 - - - - - - S1 - - - - - - S2 - - - - - - LS - - - - - - RS - - - - - - - REa - - - - - - - REb - - - - - TrmR - - - - - TrmE - - - - - TrmT - - - - - TrmA - - - - - Batt - - - - - - - - Timer1 - - - - - - - - Timer2 - - - - - SWR - - - - - Tx - - - - - RSSI - - - - - Rx - - - - - A1 - - - - - A2 - - - - - Alt - - - - - Rpm - - - - - Fuel - - - - - T1 - - - - - T2 - - - - - Speed - - - - - Dist - - - - - GPS Alt - - - - - Cell - - - - - Cels - - - - - Vfas - - - - - Curr - - - - - Cnsp - - - - - Powr - - - - - AccX - - - - - AccY - - - - - AccZ - - - - - HDG - - - - - VSpd - - - - - ASpd - - - - - dTE - - - - - A1- - - - - - A2- - - - - - Alt- - - - - - Alt+ - - - - - Rpm+ - - - - - T1+ - - - - - T2+ - - - - - Spd+ - - - - - Dst+ - - - - - Cel- - - - - - Vfs- - - - - - Cur+ - - - - - Pwr+ - - - - - ACC - - - - - Time - - - - - - LS1 - - - - - - LS2 - - - - - - LS3 - - - - - - LS4 - - - - - - LS5 - - - - - - LS6 - - - - - - LS7 - - - - - - LS8 - - - - - - LS9 - - - - - - LSA - - - - - - LSB - - - - - - LSC - - - - - - LSD - - - - - - LSE - - - - - - LSF - - - - - - LSG - - - - - - LSH - - - - - - LSI - - - - - - LSJ - - - - - - LSK - - - - - - LSL - - - - - - LSM - - - - - - LSN - - - - - - LSO - - - - - - LSP - - - - - - LSQ - - - - - - LSR - - - - - - LSS - - - - - - LST - - - - - - LSU - - - - - - LSV - - - - - - LSW - - - - - - - ---- - + ---- - - Input %1 - - - - - MAX - - - - - CYC%1 - - - - - PPM%1 - - - - - CH%1%2 - - - - - X%1 - - - - - - - GV%1 - - - - - S11 - - - - - S12 - - - - - S13 - - - - - S14 - - - - - S15 - - - - - S16 - - - - - S21 - - - - - S22 - - - - - S23 - - - - - S24 - - - - - S25 - - - - - S26 - - - - - RudTrim Left - - - - - RudTrim Right - - - - - EleTrim Down - - - - - EleTrim Up - - - - - ThrTrim Down - - - - - ThrTrim Up - - - - - AilTrim Left - - - - - AilTrim Right - - - - - - - OFF - - - - - ABS - - - - - THs - - - - - TH% - - - - - THt - - - - - - ON - - - - - ??? - - - - - Diff(%1) - - - - - Expo(%1) - - - - - Function(%1) - - - - - Curve(%1) - - - - - !Curve(%1) - - - - - - - --- - - - - - a>x - - - - - a<x - - - - - |a|>x - - - - - |a|<x - - - - - AND - - - - - OR - - - - - XOR - - - - - a=b - - - - - a!=b - - - - - a>b - - - - - a<b - - - - - a>=b - - - - - a<=b - - - - - d>=x - - - - - |d|>=x - - - - - a~x - - - - - Timer - - - - - Sticky - - - - - Stay - - - - - Unknown - - - - - STAY(%1, [%2:%3]) - - - - - STICKY(%1, %2) - - - - - TIMER(%1, %2) - - - - - Delay %1 sec - - - - - Duration %1 sec - - - - - - - - - - <font color=red><b>Inconsistent parameter</b></font> - - - - - - - All - - - - - - - Telemetry - - - - - - Value - - - - - - Decr: - - - - - - Incr: - - - - - Safety %1 - - - - - Trainer - - - - - Trainer RUD - - - - - Trainer ELE - - - - - Trainer THR - - - - - Trainer AIL - - - - - Instant Trim - - - - - Play Sound - - - - - Play Haptic - - - - - Reset - - - - - Set Timer %1 - - - - - Vario - - - - - Play Track - - - - - Play Both - - - - - Play Value - - - - - Start Logs - - - - - Volume - - - - - Backlight - - - - - Background Music - - - - - Background Music Pause - - - - - Adjust GV%1 - - - - - - No repeat - - - - - %1 sec - - - - - th9x - - - - - er9x - - - - - ersky9x - - - - - - Simultaneous usage of expo and curves is no longer supported - - - - - Simultaneous usage of expo and curves is no longer supported in open9x - - - - - openTx only accepts %1 points in all curves - - - - - - - - OpenTX on this board doesn't accept this function - - - - - - OpenTX doesn't accept this protocol - - - - - OpenTX doesn't allow this number of channels - - - - - Your radio probably uses a wrong firmware, - eeprom size is 4096 but only the first 2048 are used - - - - - - - - Warning - - - - - EEPROM saved with these warnings: - - - - - - Support for frsky telemetry mod - - - - - Support for telemetry easy board - - - - - - Support for jeti telemetry mod - - - - - - Support for receiving ardupilot data - - - - - - Support for receiving NMEA data - - - - - - Support for MAVLINK devices - - - - - Rotary Encoder use in menus navigation - - - - - - - - - Pots use in menus navigation - - - - - Possibility to enable FAI MODE at field - - - - - FAI MODE always enabled - - - - - OpenTX for 9X board - - - - - - - - - Enable heli menu and cyclic mix support - - - - - - - - - - Enable TEMPLATES menu - - - - - - - - No splash screen - - - - - - - - - - No flight modes - - - - - - - - - - Disable curves menus - - - - - - - - Support for radio modified with regular speaker - - - - - - - - - Used if you have modified your radio with voice mode - - - - - - - - Used if you have modified your radio with haptic mode - - - - - - - - - Support for DSM2 modules - - - - - - - - - - PPM center adjustment in limits - - - - - - - - - - - - PPM values displayed in us - - - - - - - - - - Global variables - - - - - - - - - - Symetrical Limits - - - - - - SmartieParts 2.2 Backlight support - - - - - - - - - - In model setup menus automatically set source by moving some of them - - - - - - - - - - In model setup menus automatically set switch by moving some of them - - - - - - - - Enable resetting values by pressing up and down at the same time - - - - - - - - - - No graphical check boxes and sliders - - - - - - - - - - Battery graph - - - - - - - - - - Don't use bold font for highlighting active items - - - - - - - - - - - - Use alternative SQT5 font - - - - - - - - Enable the throttle trace in Statistics - - - - - EEprom write progress bar - - - - - - - - - Imperial units - - - - - - No Winged Shadow How High support - - - - - - No vario support - - - - - - No GPS support - - - - - - No gauges in the custom telemetry screen - - - - - Allow compensating for offset errors in FrSky FAS current sensors - - - - - OpenTX for M128 / 9X board - - - - - - - - EEprom write Progress bar - - - - - OpenTX for 9XR - - - - - OpenTX for 9XR with M128 chip - - - - - OpenTX for Gruvin9x board / 9X - - - - - Support for SD memory card - - - - - Support of FrSky PXX protocol - - - - - Support for DSM2 modules using ppm instead of true serial - - - - - OpenTX for Sky9x board / 9X - - - - - Enable HELI menu and cyclic mix support - - - - - Use FrSky Taranis sticks in a 9X/9XR - - - - - Bluetooth interface - - - - - OpenTX for FrSky Taranis - - - - - - Disable HELI menu and cyclic mix support - - - - - - Disable TEMPLATES menu - - - - - - Disable Global variables - - - - - OpenTX for FrSky Taranis Rev4a - - - - - th9x on this board doesn't have Rotary Encoders - - - - - - FM%1 - - - - - Input%1 - - - - - Rud Trim - - - - - Ele Trim - - - - - Thr Trim - - - - - Ail Trim - - - - - Rot Enc - - - - - English - - - - - French - - - - - Italian - - - - - German - - - - - Czech - - - - - Slovak - - - - - Spanish - - - - - Polish - - - - - Portuguese - - - - - Swedish - - - - - - THR - - - - - CH%1 - - - - - No - - - - - RotEnc A - - - - - Rot Enc B - - - - - Rot Enc C - - - - - Rot Enc D - - - - - Rot Enc E - - - - - !Flight mode %1 - - - - - Flight mode %1 - - - - - Own value - - - - - Flight mode %1 value - - - - - Keys - - - - - Sticks - - - - - Keys + Sticks - - - - - - -GV%1 - - - - Yellow - + Kelt - Orange - + Orans - Red - - - - - Winged Shadow How High - - - - - Winged Shadow How High (not supported) - - - - - FrSky Sensor Hub - - - - - - None - - - - - Imperial - - - - - Metric - - - - - Extra Fine - - - - - Fine - - - - - Medium - - - - - Coarse - - - - - Exponential - - - - - Count Up - - - - - Count Down - - - - - %1:%2, - - - - - : %1 Channels, %2usec Delay - - - - - Flight modes(%1) - - - - - Flight mode(%1) - - - - - Rudder - - - - - Elevator - - - - - Throttle - - - - - Aileron - - - - - - - Simulator for this firmware is not yet available - - - - - Played once, not during startup - - - - - %1s - - - - - Value - - - - - Source - - - - - GVAR - - - - - Increment - - - - - Rotary Encoder - - - - - Trim disabled - - - - - Own Trim - - - - - Use Trim from Flight mode %1 - - - - - Use Trim from Flight mode %1 + Own Trim as an offset - - - - - Thanks all for the donations, kind messages, nice ideas, constructive proposals etc. for the next OpenTX/Companion funding model. - -We are really appreciative for that! - -The OpenTX/Companion Team. - - - - - Setup - - - Form - - - - - Model Image - - - - - Model Name - - - - - Timer2 - - - - - Timer1 - - - - - Throttle Source - - - - - Switch Warnings - - - - - Center beep - - - - - Trim Increment - - - - - Exponential - - - - - Extra Fine - - - - - Fine - - - - - Medium - - - - - Coarse - - - - - Extended Limits - - - - - Extended Trims - - - - - Display Checklist - - - - - Throttle Trim - - - - - Throttle Warning - - - - - Reverse throttle operation. -If this is checked the throttle will be reversed. Idle will be forward, trim will also be reversed and the throttle warning will be reversed as well. - - - - - - - Reverse Throttle - - - - - Pot Warnings - - - - - OFF - - - - - Manual - - - - - Auto - - - - - Telemetry - - - Form - - - - - - - - A1 - - - - - - - - A2 - - - - - RSSI - - - - - Alarm 1 - - - - - - ---- - - - - - - Yellow - - - - - - Orange - - - - - - Red - - - - - Alarm 2 - - - - - Serial Protocol - - - - - Volt source - - - - - Metric - - - - - Imperial - - - - - Current source - - - - - Protocol - - - - - NONE - - - - - - FAS - - - - - None - - - - - FrSky Sensor Hub - - - - - CEL - - - - - 2 - - - - - 3 - - - - - 4 - - - - - Units - + Pun - - Blades - + RSSI Alarm 2 + RSSI häly 2 - - Altimetry / Vario - + Battery + Akku - - Alti - - - - - Alti+ - - - - - Vario - - - - - Sink Max - - - - - Off - - - - - Climb Max - - - - - Sink Min - - - - - Climb Min - - - - - Vario source - - - - - Vario limits - - - - - Use GPS as altitude source - - - - - Display altitude in toolbar - - - - - Various - + v + v - - mAh count - - - - - FAS Offset - - - - - Persistent mAh - - - - - TelemetryAnalog - - - Form - - - - - Unit - - - - - Max Value - - - - - Alarm 1 - - - - - - ---- - - - - - - Yellow - - - - - - Orange - - - - - - Red - - - - - - < - - - - - - > - - - - - Alarm 2 - - - - - Min Value - - - - - Volts (V) - - - - - Amps (A) - - - - - Speed (m/s or ft/s) - - - - - Raw (-) - - - - - Speed (km/h or miles/h) - - - - - Meters (m or ft) - - - - - Temp (°) - - - - - Fuel (%) - - - - - mAmps (mA) - - - - - Range - - - - - TelemetryCustomScreen - - - Form - - - - - Custom Screen Type - - - - - Nums - - - - - Bars - - - - - Min - - - - - Source - - - - - Gauge - - - - - Max - - - - - TelemetryPanel - - - Telemetry screen %1 - - - - - Winged Shadow How High - - - - - Winged Shadow How High (not supported) - - - - - Timer - - - Form - - - - - mm:ss - - - - - Countdown - - - - - MinuteBeep - - - - - Persistent - - - - - (00:00:00) - - - - - TimerPanel - - - None - - - - - Beeps - - - - - Countdown - - - - - appPreferencesDialog - - - Edit Settings - - - - - Application Settings - - - - - Automatic Backup Folder - - - - - User Splash Screens - - - - - Include companion splashes - - - - - Only user defined splashes - - - - - Google Earth Executable - - - - - Automatic check for OpenTX firmware updates - - - - - - - - Open Folder - - - - - Find Executable - - - - - Files to keep - - - - - Splash Screen Library - - - - - Enable automatic backup before writing firmware - - - - - Automatic check for Companion updates - + Current + Virta - - Offer to use wizard for new models + Retrieve calib. and hw settings from profile - - Show splash screen when Companion starts + Store calib. and hw settings in selected profile - - Simulator Settings + General settings used throught the transmitter. +These will be relevant for all models in the same EEPROM. - - Simulator BackLight + MAVLink Baud Rate - - Enable + Measurement Units - - Blue + Beeps at 30, 15, 10, and down from5 seconds - - Green + Count Down to Zero - - Red + Flash on beep - - Orange + Beep volume - - Yellow + Wav volume - - Joystick + Vario volume - - Only capture to clipboard + Background volume - - Calibrate + PPMSim - - Remember simulator switch values + Beeper Length - - Simulator capture folder + Pot Scrolling Enable - - Radio Settings + Haptic Length + + + + Mode selection: + +Mode 1: + Left stick: Elevator, Rudder + Right stick: Throttle, Aileron + +Mode 2: + Left stick: Throttle, Rudder + Right stick: Elevator, Aileron + +Mode 3: + Left stick: Elevator, Aileron + Right stick: Throttle, Rudder + +Mode 4: + Left stick: Throttle, Aileron + Right stick: Elevator, Rudder + + + + + + Mode 1 (RUD ELE THR AIL) + + + + Mode 2 (RUD THR ELE AIL) + + + + Mode 3 (AIL ELE THR RUD) + + + + Mode 4 (AIL THR ELE RUD) + + + + LCD Display Type + + + + BackLight On Stick Move + + + + sec + + + + Beeper Mode + + + + Timeshift from UTC + + + + RotEnc Navigation + + + + FrSky Internal Alarm + + + + THR + KAA + + + RUD + PER + + + ELE + KOR + + + AIL + SII + + + GEA + REN + + + ID0 + ID0 + + + ID1 + ID1 + + + ID2 + ID2 + + + GPS Coordinates + + + + hh° (N/S) mm' ss''.dd + + + + NMEA + + + + If you enable FAI, you loose the vario, the play functions, the telemetry screen. This function cannot be disabled by the radio. + + + + Channel order + +This is used by the templated to determine which channel goes to what number output. + + + + R E T A + + + + R E A T + + + + R T E A + + + + R T A E + + + + R A E T + + + + R A T E + + + + E R T A + + + + E R A T + + + + E T R A + + + + E T A R + + + + E A R T + + + + E A T R + + + + T R E A + + + + T R A E + + + + T E R A + + + + T E A R + + + + T A R E + + + + T A E R + + + + A R E T + + + + A R T E + + + + A E R T + + + + A E T R + + + + A T R E + + + + A T E R + + + + Show Owner Name on Splash + + + + Speaker Pitch (spkr only) + + + + X-Short + + + + Short + + + + Normal + + + + Long + + + + X-Long + + + + StickScroll + + + + FAI Mode + + + + Haptic Strength + + + + Beeper + + + + Speaker + + + + BeeperVoice + + + + SpeakerVoice + + + + Show Splash Screen on Startup + + + + Metric + Metrit + + + Imperial + Imperiaali + + + Channel Order (For Templates) + + + + Stick Mode + + + + Haptic Mode + + + + Owner Name + + + + BackLight Invert + + + + Standard + Vakio + + + Optrex + + + + Show splash screen on startup + + + + Quiet + + + + Only Alarms + + + + No Keys + + + + All + + + + Beeper volume + +0 - Quiet. No beeps at all. +1 - No Keys. Normal beeps but menu keys do not beep. +2 - Normal. +3 - Loud. +4 - Extra loud. + + + + Alarms Only + + + + If this value is not 0, any keypress will turn on the backlight and turn it off after the specified number of seconds. + + + + Timer Beeps + + + + BackLight Brightness + + + + Contrast + + + + BackLight Auto OFF after + + + + Single + + + + Oversample + + + + Filter + + + + This is the switch selectrion for turning on the backlight (if installed). + + + + + + Bandgap Measuring Enable + + + + Input Filter + + + + CrossTrim + + + + Sound Mode + + + + BackLight Switch + + + + Battery calibration: +This value will be added to the measured battery voltage. Use this value to calibrate the meter with an external meter. + + + + Battery Calibration + + + + Battery Warning + + + + Battery warning voltage. +This is the threashhold where the battery warning sounds. + +Acceptable values are 5v..10v + + + + Telemetry NO DATA Alarm + + + + Readonly Unlock + + + + Speaker Volume + + + + If not zero will sound beeps if the transmitter has been left without inputs for the specified number of minutes. + + + + min + + + + Inactivity Timer + + + + SC + SC + + + SE + SE + + + SA + SA + + + SF + SF + + + SH + SH + + + SD + SD + + + SB + SB + + + SG + SG + + + Alarm Warning + + + + Memory Startup Warning + + + + Trainer + + + + Mode + + + + Input + + + + Weight + + + + Switch + Kytkin + + + PPM 1 + + + + Off + Pois + + + += (Sum) + + + + := (Replace) + + + + chn1 + + + + chn2 + + + + chn3 + + + + chn4 + + + + PPM 2 + + + + PPM 3 + + + + PPM 4 + + + + Telemetry + Telemetria + + + NO DATA Alarm + + + + Calibration + + + + POT 4 + + + + POT 3 + + + + POT 2 + + + + POT 1 + + + + STICK 3 + + + + Negative span + + + + Mid value + + + + Positive span + + + + STICK 1 + + + + STICK 2 + + + + STICK 4 + + + + PPM Multiplier + + + + Pot (normal) + + + + Multipos Switch + + + + S1 Type + + + + S2 Type + + + + If you enable FAI, you loose the vario, the play functions, the telemetry screen. +This function cannot be disabled by the radio. +Are you sure ? + + + + Warning + Varoitus + + + Wrong data in profile, radio calibration was not retrieved + + + + Wrong data in profile, hw related parameters were not retrieved + + + + Do you want to store calibration in %1 profile<br>overwriting existing calibration? + + + + Calibration and HW parameters saved. + + + + + Heli + + Form + Kopteri + + + Invert Elevator + Käänt kork + + + Invert Aileron + Käänt siiv + + + Invert Collective + Käänt koll + + + Invert + Käänteinen + + + Off + Pois + + + 120 + 120 + + + 120X + 120X + + + 140 + 140 + + + 90 + 90 + + + Collective + + + + Swash Type + + + + Swash Ring + + + + + InputsPanel + + Move Up + Siirrä ylös + + + Ctrl+Up + Ctrl+Ylös + + + Move Down + Siirrä alas + + + Ctrl+Down + Ctrl+Alas + + + Clear All Settings + Tyhjennä kaikki asetukset + + + Source(%1) + Lähde(%1) + + + No Trim + Ei trimmiä + + + Weight(%1) + Paino(%1) + + + Switch(%1) + Kytkin(%1) + + + Not enough available inputs! + Ei vapaita tuloja vapaana! + + + Delete Selected Inputs? + Poista valitut tulot? + + + &Add + &Lisää + + + Ctrl+A + Ctrl+A + + + &Edit + &Muuta + + + Enter + Entteri + + + &Delete + &Poista + + + Delete + Poista + + + &Copy + &Kopio + + + Ctrl+C + Ctrl+C + + + &Cut + &Leikkaa + + + Ctrl+X + Ctrl+X + + + &Paste + &Liitä + + + Ctrl+V + Ctrl+V + + + Du&plicate + Jäl&jennä + + + Ctrl+U + Ctrl+U + + + Clear Inputs? + Tyhjennä tulot? + + + Really clear all the inputs? + Varmasti tyhjennä kaikki tulot? + + + + LogicalSwitchesPanel + + Condition + Tila + + + V1 + V1 + + + V2 + V2 + + + AND + JA + + + Duration + Kesto + + + Delay + Viive + + + LS%1 + LS%1 + + + &Delete + &Poista + + + Delete + Poista + + + &Copy + &Kopio + + + Ctrl+C + Ctrl+C + + + &Cut + &Leikkaa + + + Ctrl+X + Ctrl+X + + + &Paste + &Liitä + + + Ctrl+V + Ctrl+V + + + + MainWindow + + File loaded + Tiedosto ladattu + + + Save As + Tallenna nimellä + + + Error + Virhe + + + Yes + Kyllä + + + No + Ei + + + OK + Ok + + + Open + Avaa + + + Warning + Varoitus + + + About Companion + Tietoja Companionista + + + Save... + Tallenna... + + + About + Tietoja + + + Print + Tulosta + + + Logs + Logit + + + Open log file + Avaa logi tiedosto + + + Setting... + Asetukset... + + + File + Tiedosto + + + Edit + Muuta + + + Settings + Asetukset + + + Read/Write + Lue/Kirjoita + + + Help + Apu + + + Write + Kirjoita + + + Ready + Valmis + + + Display previous warning again at startup ? + + + + Display previous message again at startup ? + + + + Checking for updates + + + + Unable to check for updates. + + + + A new version of Companion is available (version %1)<br>Would you like to download it? + + + + Executable (*.exe) + + + + New release available + + + + A new release of Companion is available please check the OpenTX website! + + + + No updates available at this time. + + + + Would you like to launch the installer? + + + + Error opening file %1: +%2. + + + + Firmware does not longer fit in the Tx, due to selected firmware options + + + + Compilation server temporary failure, try later + + + + Compilation server too busy, try later + + + + Compilation server requires registration, please check OpenTX web site + + + + Unknown server failure, try later + + + + Firmware does not fit in the Tx, due to selected firmware options + + + + Compilation server termporary failure, try later + + + + Do you want to write the firmware to the transmitter now ? + + + + Firmware %1 does not seem to have ever been downloaded. +Version %2 is available. +Do you want to download it now ? + + + + Release Notes + + + + Do you want to download release %1 now ? + + + + A new version of %1 firmware is available (current %2 - newer %3). +Do you want to download it now ? + + + + Ignore this version (r%1)? + + + + Release notes contain very important informations. Do you want to see them now ? + + + + The selected language will be used the next time you start Companion. + + + + The new theme will be loaded the next time you start Companion. + + + + The icon size will be used the next time you start Companion. + + + + Open Models and Settings file + + + + File saved + + + + Firmware updates + + + + Current firmware does not provide release notes informations. + + + + Cannot write file %1: +%2. + + + + Taranis radio not found + Taranis radiota ei löydy + + + Impossible to identify the radio on your system, please verify the eeprom disk is connected. + + + + Read Models and Settings From Tx + + + + Write Models and settings from %1 to the Tx? + + + + The file %1 +has not been recognized as a valid Models and Settings file +Write anyway ? + + + + Backup is impossible + + + + The backup dir set in preferences does not exist + + + + Backup Models and Settings From Tx + + + + Cannot check Models and Settings compatibility! Continue anyway? + + + + The transmitter firmware belongs to another product family, check file and preferences! + + + + The transmitter firmware is outdated, please upgrade! + + + + Write Models and Settings To Tx + + + + Write Firmware To Tx + + + + Conversion failed + + + + Cannot convert Models and Settings for use with this firmware, original data will be used + + + + Restore Models and Settings To Tx + + + + Restore failed + + + + Could not restore Models and Settings to TX. The models and settings data file can be found at: %1 + + + + Firmware write failed + + + + Could not write firmware to to transmitter. The models and settings data file can be found at: %1 + + + + Backup failed + + + + Cannot backup existing Models and Settings from TX. Firmware write process aborted + + + + Save transmitter Models and Settings to File + + + + Impossible to identify the radio on your system, please verify that the eeprom disk is connected. + + + + Read Tx Firmware to File + + + + OpenTX Home Page: <a href='%1'>%1</a> + + + + The OpenTX Companion project was originally forked from <a href='%2'>eePe</a> + + + + If you've found this program useful, please support by <a href='%1'>donating</a> + + + + Version %1, %3 + + + + Copyright + + + + OpenTX Companion - FW: %1 - Profile: %2 + + + + New Models+Settings + + + + Create a new Models and Settings file + + + + Open Models+Settings... + + + + Save Models+Settings... + + + + Save Models and Settings file + + + + Save Models+Settings as... + + + + Exit + + + + Exit the application + + + + Cut Model + + + + Cut current model to the clipboard + + + + Copy Model... + + + + Copy current model to the clipboard + + + + Paste Model... + + + + Paste model from clipboard + + + + Classical + + + + The classic companion9x icon theme + + + + Yerico + + + + Yellow round honey sweet icon theme + + + + Monochrome + + + + A monochrome black icon theme + + + + MonoWhite + + + + A monochrome white icon theme + + + + MonoBlue + + + + A monochrome blue icon theme + + + + Small + + + + Use small toolbar icons + + + + Normal + + + + Use normal size toolbar icons + + + + Big + + + + Use big toolbar icons + + + + Huge + + + + Use huge toolbar icons + + + + System language + + + + Use system language in menus + + + + Czech + + + + Use Czech in menus + + + + German + + + + Use German in menus + + + + English + + + + Use English in menus + + + + Finnish + + + + Use Finnish in menus + + + + French + + + + Use French in menus + + + + Italian + + + + Use Italian in menus + + + + Hebrew + + + + Use Hebrew in menus + + + + Polish + + + + Use Polish in menus + + + + Portuguese + + + + Use Portuguese in menus + + + + Swedish + + + + Use Swedish in menus + + + + Russian + + + + Use Russian in menus + + + + About... + + + + Show the application's About box + + + + Print... + + + + Print current model + + + + Simulate... + + + + Simulate current model + + + + Load Backup... + + + + Load backup from file + + + + View Log File... + + + + Open and view log file + + + + Settings... + + + + Edit Settings + + + + Download... + + + + Download firmware and voice files + + + + Check for Updates... + + + + Check OpenTX and Companion updates + + + + Companion Changes... + + + + Show Companion change log + + + + Firmware Changes... + + + + Show firmware change log + + + + Compare Models... + + + + Compare models + + + + Edit Tx Splash Image... + + + + Edit the splash image of your TX + + + + List programmers... + + + + List available programmers + + + + Fuses... + + + + Show fuses dialog + + + + Read Firmware + + + + Read firmware from transmitter + + + + Write Firmware + + + + Write firmware to transmitter + + + + Add Radio Profile + + + + Create a new Radio Setting Profile + + + + Manuals and other Documents + + + + Open the OpenTX document page in a web browser + + + + Write Models and Settings to transmitter + + + + Read Models and Settings from transmitter + + + + Configure Communications... + + + + Configure software for communicating with the transmitter + + + + Write Models and Settings from file to Tx + + + + Write Models and Settings from file to transmitter + + + + Save Tx Models and Settings to file + + + + Save the Models and Settings from the transmitter to a file + + + + Contributors... + + + + A tribute to those who have contributed to OpenTX and Companion + + + + Recent Models+Settings + + + + Set Menu Language + + + + Set Icon Theme + + + + Set Icon Size + + + + Radio Settings Profile + + + + Show recent Models+Settings documents + + + + Show a selection list of radio settings profiles + + + + %2 + + + + Unable to find file %1! + + + + Invalid Models and Settings File %1 + + + + Error reading file %1: +%2. + + + + Invalid binary Models and Settings File %1 + + + + + MdiChild + + free bytes + Vapaata tilaa + + + Companion + Companion + + + Error + Virhe + + + Save As + Tallenna nimellä + + + Taranis radio not found + Taranis radiota ei löydy + + + Warning + Varoitus + + + Open + Avaa + + + Do you want to use model wizard? + + + + Ask this question again ? + + + + Editing model %1: + + + + Unable to find file %1! + + + + Error opening file %1: +%2. + + + + Invalid EEPROM File %1 + + + + Error reading file %1: +%2. + + + + Invalid binary EEPROM File %1 + + + + Cannot write file %1: +%2. + + + + Error writing file %1: +%2. + + + + %1 has been modified. +Do you want to save your changes? + + + + Backup is impossible + + + + The backup dir set in preferences does not exist + + + + Cannot write temporary file! + + + + Impossible to identify the radio on your system, please verify the eeprom disk is connected. + + + + Backup EEPROM From Tx + + + + Cannot check eeprom compatibility! Continue anyway? + + + + Firmware in radio is of a different family of eeprom written, check file and preferences! + + + + Firmware in flash is outdated, please upgrade! + + + + Write EEPROM To Tx + + + + Open backup Models and Settings file + + + + Invalid binary backup File %1 + + + + + MixerDialog + + Dialog + + + + Delay + Viive + + + Slow + + + + Up + + + + Down + + + + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> +<html><head><meta name="qrichtext" content="1" /><style type="text/css"> +p, li { white-space: pre-wrap; } +</style></head><body style=" font-family:'MS Shell Dlg 2'; font-size:8.25pt; font-weight:400; font-style:normal;"> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-weight:600; text-decoration: underline;">Delay ans Slow</span></p> +<p style="-qt-paragraph-type:empty; margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px; font-weight:600; text-decoration: underline;"></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">These values control the speed and delay of the output of the mix. </p> +<p style="-qt-paragraph-type:empty; margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">If Delay is not zero the actuation of the mix will be delayed by the specified amount of seconds.</p> +<p style="-qt-paragraph-type:empty; margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">If Slow is not zero then the speed of the mix will be set by the value specified -&gt; the value states the number of seconds it takes to transit from -100 to 100.</p></body></html> + <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> +<html><head><meta name="qrichtext" content="1" /><style type="text/css"> +p, li { white-space: pre-wrap; } +</style></head><body style=" font-family:'MS Shell Dlg 2'; font-size:8.25pt; font-weight:400; font-style:normal;"> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"><span style=" font-weight:600; text-decoration: underline;">Delay ans Slow</span></p> +<p style="-qt-paragraph-type:empty; margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px; font-weight:600; text-decoration: underline;"></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">These values control the speed and delay of the output of the mix. </p> +<p style="-qt-paragraph-type:empty; margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">If Delay is not zero the actuation of the mix will be delayed by the specified amount of seconds.</p> +<p style="-qt-paragraph-type:empty; margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;"></p> +<p style=" margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;">If Slow is not zero then the speed of the mix will be set by the value specified -&gt; the value states the number of seconds it takes to transit from -100 to 100.</p></body></html> + + + Include Trim + + + + Offset + Tasoitus + + + Weight + + + + 0 + 0 + + + 1 + 1 + + + 2 + 2 + + + 3 + 3 + + + 4 + 4 + + + 5 + 5 + + + 6 + 6 + + + 7 + 7 + + + 8 + 8 + + + Name + Nimi + + + Source + Lähde + + + Multiplex + + + + Warning + Varoitus + + + The curve used by the mix + + + + Include DR/Expo + + + + Flight modes + + + + Switch + Kytkin + + + Mixer warning. +Setting this value will cause a beep to be emmitted when this value is active. + + + + OFF + Pois + + + 1 Beep + + + + 2 Beep + + + + 3 Beep + + + + No + Ei + + + Yes + Kyllä + + + GV + + + + The source for the mixer + + + + Multiplexer + +This determines how mixer values are added. + +"+" means the value of the current mix is added to the previous mixes in the same channel. +"*" means the value of the current mix is amultiplied with the previous mixes in the same channel. +"R" means the value replaces the previous values. If the switch is off the value will be ignored. + + + + ADD + + + + MULTIPLY + + + + REPLACE + + + + Curve + Käyrä + + + Switch used by the mix. +If blank then the mix is considered to be "ON" all the time. + + + + DEST -> X%1 + + + + DEST -> CH%1%2 + + + + Rud + + + + Ele + + + + Thr + + + + Ail + + + + + MixesPanel + + Move Up + Siirrä ylös + + + Ctrl+Up + Ctrl+Ylös + + + Move Down + Siirrä alas + + + Ctrl+Down + Ctrl+Alas + + + Clear Mixes + Tyhjennä mikserit + + + X%1 + X%1 + + + CH%1%2 + CH%1%2 + + + Weight(%1) + Paino(%1) + + + Switch(%1) + Kytkin(%1) + + + No Trim + Ei trimmiä + + + &Add + &Lisää + + + Ctrl+A + Ctrl+A + + + &Edit + &Muuta + + + Enter + Entteri + + + &Delete + &Poista + + + Delete + Poista + + + &Copy + &Kopio + + + Ctrl+C + Ctrl+C + + + &Cut + &Leikkaa + + + Ctrl+X + Ctrl+X + + + &Paste + &Liitä + + + Ctrl+V + Ctrl+V + + + Du&plicate + Jäl&jennä + + + Ctrl+U + Ctrl+U + + + Clear Mixes? + Tyhjennä mikserit? + + + Really clear all the mixes? + Varmasti tyhjennä kaikki mikserit? + + + No DR/Expo + + + + Offset(%1) + + + + Delay(u%1:d%2) + + + + Slow(u%1:d%2) + + + + Warn(%1) + + + + Not enough available mixers! + + + + Delete Selected Mixes? + + + + + ModelEdit + + Dialog + Mallin editori + + + Simulate + Simuloi + + + Clear Curves? + Tyhjennä käyrät? + + + Really clear all the curves? + Varmasti tyhjennä kaikki käyrät? + + + Setup + Asetukset + + + Heli + Kopteri + + + Flight Modes + Lento tilat + + + Inputs + Tulot + + + Mixes + Mikserit + + + Channels + Kanavat + + + Logical Switches + Loogiset kytkimet + + + Switch Assignment + Kytkimien asettelu + + + Curves + Käyrät + + + Telemetry + Telemetria + + + + ModelsListWidget + + &Edit + &Muuta + + + &Restore from backup + &Palauta varmuuskopiosta + + + &Model Wizard + &Malli apuri + + + &Delete + &Poista + + + Delete + Poista + + + &Copy + &Kopio + + + Ctrl+C + Ctrl+C + + + &Cut + &Leikkaa + + + Ctrl+X + Ctrl+X + + + &Paste + &Liitä + + + Ctrl+V + Ctrl+V + + + D&uplicate + Jäl&jennä + + + Ctrl+U + Ctrl+U + + + &Use as default + &Käytä perus asetuksena + + + P&rint model + Tu&losta malli + + + Alt+R + Alt+R + + + &Simulate model + &Simuloi malli + + + Alt+S + Alt+S + + + General Settings + Yleiset asetukset + + + Delete Selected Models? + Poista valitut mallit? + + + Cannot delete default model. + Valittuna ollutta mallia ei voida poistaa. + + + Cannot cut default model. + Valittua mallia ei voi leikata. + + + Do you want to overwrite TX general settings? + Haluatko päällekirjoittaa TX:n yleiset asetukset ? + + + You are pasting on an not empty model, are you sure? + Yrität liittää tietoja ei tyhjän mallin tietoihin, haluatko varmasti jatkaa ? + + + No free slot available, cannot duplicate + Ei vapaata tilaa, ei voida monistaa + + + + Module + + Form + Moduuli + + + Failsafe Mode + Turvatila + + + Start + Aloitus + + + PPM delay + PPM viive + + + usec + usec + + + Negative + Negatiivinen + + + Positive + Positiivinen + + + RX Number + RX numero + + + Master + Masteri + + + Slave + Orja + + + Polarity + Napaisuus + + + Trainer Mode + Harjoitus tila + + + mSec + mSec + + + PPM Frame Length + PPM läh pituus + + + Label + Lappu + + + ch + ch + + + Channels + Kanavat + + + Hold + Pidä + + + Custom + Omat + + + No Pulses + Ei pulsseja + + + Failsafe Positions + Turvatila asennot + + + Protocol + Protokolla + + + + ModulePanel + + Trainer Output + Opetus ulostulo + + + Internal Radio System + Sisäinen radio systeemi + + + External Radio Module + Ulkoinen radio systeemi + + + + QObject + + FW: %1 + + + + Pict: %1 + + + + Profile image + + + + -GV%1 + + + + GV%1 + + + + Rud + + + + Ele + + + + Thr + + + + Ail + + + + P1 + P1 + + + P2 + P2 + + + P3 + P3 + + + S1 + S1 + + + S2 + S2 + + + S3 + S3 + + + LS + LS + + + RS + RS + + + REa + + + + REb + + + + TrmR + + + + TrmE + + + + TrmT + + + + TrmA + + + + Batt + + + + Timer1 + Ajastin 1 + + + Timer2 + Ajastin 2 + + + SWR + + + + RSSI Tx + + + + RSSI Rx + + + + Rx Batt + + + + A1 + A1 + + + A2 + A2 + + + A3 + + + + A4 + + + + Alt + + + + Rpm + + + + Fuel + + + + T1 + + + + T2 + + + + Speed + + + + Dist + + + + GPS Alt + + + + Cell + + + + Cels + + + + Vfas + + + + Curr + + + + Cnsp + + + + Powr + + + + AccX + + + + AccY + + + + AccZ + + + + HDG + + + + VSpd + + + + ASpd + + + + dTE + + + + A1- + + + + A2- + + + + A3- + + + + A4- + + + + Alt- + + + + Alt+ + + + + Rpm+ + + + + T1+ + + + + T2+ + + + + Spd+ + + + + Dst+ + + + + Cel- + + + + Cels- + + + + Vfs- + + + + Cur+ + + + + Pwr+ + + + + ACC + + + + Time + + + + LS1 + LS1 + + + LS2 + LS2 + + + LS3 + LS3 + + + LS4 + LS4 + + + LS5 + LS5 + + + LS6 + LS6 + + + LS7 + LS7 + + + LS8 + LS8 + + + LS9 + LS9 + + + LSA + LSA + + + LSB + LSB + + + LSC + LSC + + + LSD + LSD + + + LSE + LSE + + + LSF + LSF + + + LSG + LSG + + + LSH + LSH + + + LSI + LSI + + + LSJ + LSJ + + + LSK + LSK + + + LSL + LSL + + + LSM + LSM + + + LSN + LSN + + + LSO + LSO + + + LSP + LSP + + + LSQ + LSQ + + + LSR + LSR + + + LSS + LSS + + + LST + LST + + + LSU + LSU + + + LSV + LSV + + + LSW + LSW + + + ---- + ---- + + + [I%1] + + + + MAX + + + + CYC%1 + + + + PPM%1 + + + + CH%1%2 + CH%1%2 + + + X%1 + + + + S11 + S11 + + + S12 + S12 + + + S13 + S13 + + + S14 + S14 + + + S15 + S15 + + + S16 + S16 + + + S21 + S21 + + + S22 + S22 + + + S23 + S23 + + + S24 + S24 + + + S25 + S25 + + + S26 + S26 + + + S31 + S31 + + + S32 + S32 + + + S33 + S33 + + + S34 + S34 + + + S35 + S35 + + + S36 + S36 + + + RudTrim Left + + + + RudTrim Right + + + + EleTrim Down + + + + EleTrim Up + + + + ThrTrim Down + + + + ThrTrim Up + + + + AilTrim Left + + + + AilTrim Right + + + + OFF + Pois + + + ABS + + + + THs + + + + TH% + + + + THt + + + + ON + ON + + + ??? + + + + Diff(%1) + + + + Expo(%1) + + + + Function(%1) + + + + Curve(%1) + + + + !Curve(%1) + + + + --- + --- + + + a>x + + + + a<x + + + + |a|>x + + + + |a|<x + + + + AND + JA + + + OR + + + + XOR + + + + a=b + + + + a!=b + + + + a>b + + + + a<b + + + + a>=b + + + + a<=b + + + + d>=x + + + + |d|>=x + + + + a=x + + + + a~x + + + + Timer + + + + Sticky + + + + Stay + + + + Unknown + + + + STAY(%1, [%2:%3]) + + + + STICKY(%1, %2) + + + + TIMER(%1, %2) + + + + Delay %1 sec + + + + Duration %1 sec + + + + <font color=red><b>Inconsistent parameter</b></font> + + + + All + + + + Telemetry + Telemetria + + + Value + + + + Decr: + + + + Incr: + + + + Safety %1 + + + + Trainer + + + + Trainer RUD + + + + Trainer ELE + + + + Trainer THR + + + + Trainer AIL + + + + Instant Trim + + + + Play Sound + + + + Play Haptic + + + + Reset + + + + Set Timer %1 + + + + Vario + Alti+ + + + Play Track + + + + Play Both + + + + Play Value + + + + Start Logs + + + + Volume + + + + Backlight + + + + Background Music + + + + Background Music Pause + + + + Adjust GV%1 + + + + No repeat + + + + %1 sec + + + + Simultaneous usage of expo and curves is no longer supported + + + + Simultaneous usage of expo and curves is no longer supported in open9x + + + + OpenTX only accepts %1 points in all curves + + + + OpenTX on this board doesn't accept this function + + + + OpenTX doesn't accept this protocol + + + + OpenTX doesn't allow this number of channels + + + + Your radio probably uses a wrong firmware, + eeprom size is 4096 but only the first 2048 are used + + + + Warning + Varoitus + + + EEPROM saved with these warnings: + + + + Support for frsky telemetry mod + + + + Support for telemetry easy board + + + + Support for jeti telemetry mod + + + + Support for receiving ardupilot data + + + + Support for receiving NMEA data + + + + Support for MAVLINK devices + + + + Rotary Encoder use in menus navigation + + + + Pots use in menus navigation + + + + Possibility to enable FAI MODE at field + + + + FAI MODE always enabled + + + + OpenTX for 9X board + + + + Enable heli menu and cyclic mix support + + + + Enable TEMPLATES menu + + + + No splash screen + + + + No flight modes + + + + Disable curves menus + + + + Support for radio modified with regular speaker + + + + Used if you have modified your radio with voice mode + + + + Used if you have modified your radio with haptic mode + + + + Support for DSM2 modules + + + + PPM center adjustment in limits + + + + PPM values displayed in us + + + + Global variables + + + + Symetrical Limits + + + + SmartieParts 2.2 Backlight support + + + + In model setup menus automatically set source by moving some of them + + + + In model setup menus automatically set switch by moving some of them + + + + Enable resetting values by pressing up and down at the same time + + + + No graphical check boxes and sliders + + + + Battery graph + + + + Don't use bold font for highlighting active items + + + + Use alternative SQT5 font + + + + Enable the throttle trace in Statistics + + + + EEprom write progress bar + + + + Imperial units + + + + No Winged Shadow How High support + + + + No vario support + + + + No GPS support + + + + No gauges in the custom telemetry screen + + + + Allow compensating for offset errors in FrSky FAS current sensors + + + + OpenTX for M128 / 9X board + + + + EEprom write Progress bar + + + + OpenTX for 9XR + + + + OpenTX for 9XR with M128 chip + + + + OpenTX for Gruvin9x board / 9X + + + + Support for SD memory card + + + + Support of FrSky PXX protocol + + + + Support for DSM2 modules using ppm instead of true serial + + + + OpenTX for Sky9x board / 9X + + + + Enable HELI menu and cyclic mix support + + + + Use FrSky Taranis sticks in a 9X/9XR + + + + Bluetooth interface + + + + OpenTX for FrSky Taranis + + + + Disable HELI menu and cyclic mix support + + + + Disable TEMPLATES menu + + + + Disable Global variables + + + + OpenTX for FrSky Taranis Rev4a + + + + th9x on this board doesn't have Rotary Encoders + + + + FM%1 + + + + Input%1 + + + + Rud Trim + + + + Ele Trim + + + + Thr Trim + + + + Ail Trim + + + + Rot Enc + + + + English + + + + Finnish + + + + French + + + + Italian + + + + German + + + + Czech + + + + Slovak + + + + Spanish + + + + Polish + + + + Portuguese + + + + Swedish + + + + THR + KAA + + + CH%1 + + + + No + Ei + + + RotEnc A + + + + Rot Enc B + + + + Rot Enc C + + + + Rot Enc D + + + + Rot Enc E + + + + !Flight mode %1 + + + + Flight mode %1 + + + + Own value + + + + Flight mode %1 value + + + + Keys + + + + Sticks + + + + Keys + Sticks + + + + Yellow + Kelt + + + Orange + Orans + + + Red + Pun + + + Winged Shadow How High + erikoistoiminto korkea + + + Winged Shadow How High (not supported) + erikoistoiminto korkea (ei tuettu) + + + FrSky Sensor Hub + FrSky:n hubi + + + None + Ei mitään + + + Imperial + Imperiaali + + + Metric + Metrit + + + Extra Fine + Eri hieno + + + Fine + Hieno + + + Medium + Keski + + + Coarse + Karkea + + + Exponential + Expo + + + Count Up + + + + Count Down + + + + %1:%2, + + + + : %1 Channels, %2usec Delay + + + + Flight modes(%1) + + + + Flight mode(%1) + + + + Rudder + + + + Elevator + + + + Throttle + + + + Aileron + + + + Simulator for this firmware is not yet available + + + + Played once, not during startup + + + + %1s + + + + Value + + + + Source + Lähde + + + GVAR + + + + Increment + + + + Rotary Encoder + + + + Trim disabled + + + + Own Trim + + + + Use Trim from Flight mode %1 + + + + Use Trim from Flight mode %1 + Own Trim as an offset + + + + Thanks all for the donations, kind messages, nice ideas, constructive proposals etc. for the next OpenTX/Companion funding model. + +We are really appreciative for that! + +The OpenTX/Companion Team. + + + + + Setup + + Form + + +Asetukset + + + Model Image + Mallin kuva + + + Model Name + Mallin nimi + + + Timer2 + Ajastin 2 + + + Timer1 + Ajastin 1 + + + Throttle Source + Kaasun lähde + + + Switch Warnings + Kytkin varoitukset + + + Center beep + Keski piippaus + + + Trim Increment + Trimmin säätö + + + Exponential + Expo + + + Extra Fine + Eri hieno + + + Fine + Hieno + + + Medium + Keski + + + Coarse + Karkea + + + Extended Limits + Laajemman rajat + + + Extended Trims + Laajemmat trimmit + + + Display Checklist + Näytä teht.lista + + + Throttle Trim + Kaasu trimmi + + + Throttle Warning + Kaasu varoitus + + + Reverse throttle operation. +If this is checked the throttle will be reversed. Idle will be forward, trim will also be reversed and the throttle warning will be reversed as well. + + + Käänteinen kaasu +Jos tämä valittuna, kaasu toimii käänteisesti. Tyhjäkäynti on ylhäällä, myös trimmi on käänteinen. Myös kaasu varoitus käänteinen. + + + + Reverse Throttle + Käänteinen kaasu + + + Pot Warnings + Potikka varoitus + + + OFF + Pois + + + Manual + Käsin + + + Auto + Autom + + + + SimulatorDialog + + Warning + Varoitus + + + Joystick enabled but not configured correctly + + + + Cannot open joystick, joystick disabled + + + + Simulating Tx (%1) + + + + Firmware %1 error: %2 + + + + + SimulatorDialog9X + + Companion Simulator + Companion simulaattori + + + Right Double Click to Reset + + + + THR + KAA + + + RUD + PER + + + ELE + KOR + + + AIL + SII + + + Hold X + Pidä X + + + Fix X + + + + Fix Y + + + + Hold Y + Pidä Y + + + TextLabel + + + + TRN + TRN + + + GEA + REN + + + ID0 + ID0 + + + ID1 + ID1 + + + ID2 + ID2 + + + BEEP + PIIP + + + P1 + P1 + + + 0 % + 0 % + + + P2 + P2 + + + P3 + P3 + + + 9x Simulator + 9x simulaattori + + + Outputs + + + + + SimulatorDialogTaranis + + Companion Simulator + Companion simulaattori + + + Hold Y + Pidä Y + + + Fix Y + + + + Fix X + + + + Hold X + Pidä X + + + SD + SD + + + SC + SC + + + Right Double Click to Reset + + + + S2 + S2 + + + SG + SG + + + RS + RS + + + SH + SH + + + TextLabel + + + + S1 + S1 + + + SB + SB + + + SA + SA + + + SE + SE + + + SF + SF + + + LS + LS + + + Taranis Simulator + Taranis simulaattori + + + Outputs + + + + + Telemetry + + Form + Telemetria + + + A1 + A1 + + + A2 + A2 + + + RSSI + RSSI + + + Alarm 1 + Varoitus 1 + + + ---- + ---- + + + Yellow + Kelt + + + Orange + Orans + + + Red + Puna + + + Alarm 2 + Varoitus 2 + + + Serial Protocol + Sarja protokolla + + + Volt source + Voltti lähde + + + Metric + Metrit + + + Imperial + Imperiaali + + + Current source + Virran lähde + + + Protocol + Protokolla + + + NONE + EI MITÄÄN + + + FAS + FAS + + + None + Ei mitään + + + FrSky Sensor Hub + FrSky:n hubi + + + CEL + CEL + + + 2 + 2 + + + 3 + 3 + + + 4 + 4 + + + Units + Asteikko + + + Blades + Prop lavat + + + Altimetry / Vario + Korkeusm / Variometri + + + Alti + Alti + + + Alti+ + Kork+ + + + Vario + Alti+ + + + Sink Max + Maksimi vajoama + + + Off + Pois + + + Climb Max + Maksimi nousu + + + Sink Min + Minimi vajoama + + + Climb Min + Minimi nousu + + + Vario source + Variom lähde + + + Vario limits + Varionm asetukset + + + Use GPS as altitude source + Käytä GPS:sää kork. lähteenä + + + Display altitude in toolbar + Näytä korkeus työkalupalkissa + + + Various + Useat + + + mAh count + mAh laskuri + + + FAS Offset + FAS asetus + + + Persistent mAh + Yhtm. mAh + + + + TelemetryAnalog + + Form + Telemetria + + + Unit + Yksikkö + + + Max Value + Maks arvo + + + Alarm 1 + Hälytys 1 + + + ---- + ---- + + + Yellow + Kelt + + + Orange + Orans + + + Red + Pun + + + < + < + + + > + > + + + Alarm 2 + Hälytys 2 + + + Min Value + Pienin arvo + + + Volts (V) + Voltit ( V ) + + + Amps (A) + Amp ( A ) + + + Speed (m/s or ft/s) + Nopeus ( m/s tai jalk/s ) + + + Raw (-) + Raaka ( - ) + + + Speed (km/h or miles/h) + Nopeus ( km/h tai mailia/h ) + + + Meters (m or ft) + Metrit (m tai jalkaa ) + + + Temp (°) + Lämpöt (c) + + + Fuel (%) + Bensa (%) + + + mAmps (mA) + mAmp (mA) + + + Range + Matka + + + + TelemetryCustomScreen + + Form + Telemetria oma ruutu + + + Custom Screen Type + Oman ruudun tyyppi + + + Nums + Numerot + + + Bars + Palkit + + + Min + Min + + + Source + Lähde + + + Gauge + Mittari + + + Max + Max + + + + TelemetryPanel + + Telemetry screen %1 + Telemetria ruutu %1 + + + Winged Shadow How High + erikoistoiminto korkea + + + Winged Shadow How High (not supported) + erikoistoiminto korkea (ei tuettu) + + + + Timer + + Form + Ajastin + + + mm:ss + mm:ss + + + Countdown + Laskuri + + + MinuteBeep + Minutti piippaus + + + Persistent + Yhtämittainen + + + (00:00:00) + (00:00:00) + + + + TimerPanel + + None + Ei mitään + + + Beeps + Piipit + + + Countdown + Laskuri + + + + appPreferencesDialog + + Edit Settings + + + + Application Settings + + + + Automatic Backup Folder + + + + User Splash Screens + + + + Only show user splash images + + + + Show user and companion splash images + + + + Google Earth Executable + + + + Automatic check for OpenTX firmware updates + + + + Open Folder + + + + Find Executable + + + + Files to keep + + + + Splash Screen Library + + + + Enable automatic backup before writing firmware + + + + Automatic check for Companion updates + + + + Offer to use wizard for new models + + + + Show splash screen when Companion starts + + + + Simulator Settings + + + + Simulator BackLight + + + + Enable + Päälle + + + Blue + + + + Green + + + + Red + Puna + + + Orange + Orans + + + Yellow + Kelt + + + Joystick + + + + Only capture to clipboard + + + + Calibrate + + + + Remember simulator switch values + + + + Simulator capture folder + + + + Radio Settings Profile - Mode selection: Mode 1: @@ -6645,255 +5350,236 @@ Mode 4: - Mode 1 (RUD ELE THR AIL) - Mode 2 (RUD THR ELE AIL) - Mode 3 (AIL ELE THR RUD) - Mode 4 (AIL THR ELE RUD) - Channel order This is used by the templated to determine which channel goes to what number output. - R E T A - R E A T - R T E A - R T A E - R A E T - R A T E - E R T A - E R A T - E T R A - E T A R - E A R T - E A T R - T R E A - T R A E - T E R A - T E A R - T A R E - T A E R - A R E T - A R T E - A E R T - A E T R - A T R E - A T E R - Default Stick Mode - - Settings Profile + Profile Name - Splash Screen - Channel Order - Append version number to FW file name - SD Structure path - Offer to write FW to Tx after download - Remove Profile - - Firmware - - - - Select Image - + Radio Type + + + Clear Image - + 9X + + + + 9X with m128 + + + + 9XR + + + + 9XR with m128 + + + + Gruvin9x Board + + + + Sky9x Board + + + + Taranis + + + + My Radio + + + Select your snapshot folder - - No joysticks found - Select your library folder - Select your Models and Settings backup folder - Select Google Earth executable - Select the folder replicating your SD structure - Not possible to remove profile - The default profile can not be removed. - Open Image to load - Images (%1) @@ -6901,149 +5587,117 @@ This is used by the templated to determine which channel goes to what number out avrOutputDialog - Dialog - Show Details - result - executable not found - - Error - + Virhe - Cannot open source file - Cannot write destination - Writing file: - ie: OpenTX for 9X board or OpenTX for 9XR board - ie: OpenTX for M128 / 9X board or OpenTX for 9XR board with M128 chip - ie: OpenTX for Gruvin9X board - Your radio uses a %1 CPU!!! Please check advanced burn options to set the correct cpu type. - Your radio uses a %1 CPU!!! Please select an appropriate firmware type to program it. - You are currently using: %1 - - Writing - - Reading - - Verifying - done - exit code %1 - done with errors - - done - SUCCESSFUL - did not finish correctly - did not finish correctly! Do you want some help ? - Copy did not finish correctly - finished correctly - Copy finished correctly - Started - FUSES: Low=%1 High=%2 Ext=%3 @@ -7051,78 +5705,55 @@ Do you want some help ? burnConfigDialog - Programmer Configuration - - Location of sam-ba executable - - - - The location of the AVRDUDE executable. - DFU-Util Location - Location of AVRDUDE executable - - - Use this button to browse and look for the AVRDUDE executable file. - - - Browse... - Programmer - Programmer used for communicating with the controller. Please consult the programmer's documentation and the AVRDUDE documentation to select the appropriate programmer. - List all available programmers. - List Available - - Extra arguments that will be passed to AVRDUDE on every call - - Extra arguments used in AVRDUDE. This can be used for providing extra information to AVRDUDE. @@ -7130,116 +5761,89 @@ Please only use this if you know what you are doing. There are no error checks - Extra Arguments - Show AVRDUDE help - Show Help - Communication port to the programmer. - - Port - AVRDUDE Location - MCU - - CPU of your TX - - CPU present on your 9x radio Should be m64 for stock radios m2560 for v4.1 boards - SAM-BA Location - ARM MCU - sam-ba serial port - Alternate device - Use advanced controls - DFU-UTIL Configuration - SAM-BA Configuration - AVRDUDE Configuration - - - Select Location - - Companion - + Companion - <b><u>WARNING!</u></b><br>This will reset the fuses of %1 to the factory settings.<br>Writing fuses can mess up your radio.<br>Do this only if you are sure they are wrong!<br>Are you sure you want to continue? - <b><u>WARNING!</u></b><br>Normally CPU type is automatically selected according to the chosen firmware.<br>If you change the CPU type the resulting eeprom could be inconsistent. @@ -7247,252 +5851,193 @@ m2560 for v4.1 boards burnDialog - + Cancel + Peruuta + + + SVN + SVN + + + Open + Avaa + + + Warning + Varoitus + + + Error + Virhe + + Customize Splash - - Cancel - - - - - Write to TX - <html><head/><body><p>Modify calibration parameters using settings from current profile</p></body></html> - Patch calibration setting from profile - <html><head/><body><p>Modify HW parameters using settings from current profile</p></body></html> - Patch HW setting from profile - - Date & Time - - - - - SVN - - - - Variant - - + Date & Time + + + Browse for file - Allows Companion to write to older version of the firmware - Check Firmware compatibility - Backup and restore Models and Settings - Current Profile - - Invert Color + Use firmware start screen - - Use image in settings + Use another start screen - - Substitute image in firmware + Use profile start screen - - Load Image + Use library start screen - - Open Splash Library - - - - - ... - - - - Write firmware to TX - Write Models and Settings to TX - Write Models and Settings in %1 to TX - Current profile - - Open + Open Firmware File - Choose file to load Models and Settings from - - - - - - - Warning + %1 may not be a valid firmware file - - %1 is not a known firmware - - - - - Burn anyway ! - - - - - - - - - - - - - - Error - - - - Unable to find file %1! - - - Error opening file %1: %2. - - - Invalid binary Models and Settings File %1, Proceed anyway ? - Error reading file %1: %2. - - Open Image to load + The firmware file is not valid. + + + + There is no start screen image in the firmware file. + + + + The profile image %1 does not contain an image. + + + + Open image file to use as Tx start screen - Images (%1) - - - Cannot load %1. + Image could not be loaded from %1 + + + + The library image could not be loaded - Cannot save customized firmware - Custom image not found - No firmware selected - Wrong radio calibration data in profile, Settings not patched - Wrong radio setting data in profile, Settings not patched - - Cannot write file %1: %2. - Error writing file %1: %2. @@ -7501,513 +6046,322 @@ m2560 for v4.1 boards compareDialog - - Dialog + Compare Models - Drag first model here - Drag second model here - Close - Print - + Tulosta - Print to file - - No name - General Model Settings - - - Name - + Nimi - - EEprom Size - - Timer1 - + Ajastin 1 - - Timer2 - + Ajastin 2 - - Protocol - + Protokolla - - Pulse Polarity - - Throttle Trim - + Kaasu trimmi - - - - Enabled - - - - Disabled - - Throttle Expo - - Trim Increment - + Trimmin säätö - - Center Beep - Flight modes Settings - - Fades - - Trims - - - - - - - - Switch - + Kytkin - - - - Flight mode name - - IN - - OUT - - - - - - - - - - FM - - Gvars - - Rot. Enc. - Limits - - - - - - - Offset - + Tasoitus - - - - - Min - + Min - - - - - Max - + Max - - - Invert - + Käänteinen - - - - - CH - - INV - + KÄÄNT - - NOR - Global Variables - - GV - Expo/Dr Settings - - Weight - - - - Flight modes - - - - Flight mode - - - - DISABLED - Mixers - - noTrim - - Delay(u%1:d%2) - - Slow(u%1:d%2) - - Warn - Curves - + Käyrät - 5 Points Curves - - - - pt %1 - - Curve - + Käyrä - 9 Points Curves - Logical Switches - + Loogiset kytkimet - - LS - + LS - Switch Assignment - + Kytkimien asettelu - - Function - - Param - - Repeat - - Enable - + Päälle - CF - Telemetry Settings - - Analog - - Unit - + Yksikkö - - Scale - - - - A%1 - - Alarm 1 - + Varoitus 1 - - Alarm 2 - - - - Type - - - - Condition - + Tila - - - - Value - - RSSI Alarm - - Custom Telemetry View - - Telemetry Bars - - Bar Number - - Source - + Lähde - Print Document - Select PDF output file @@ -8015,167 +6369,125 @@ m2560 for v4.1 boards contributorsDialog - Dialog - + Kehittäjät - People who have contributed to this project - + Henkilöt jotka on tehnyt töitä projektin eteen - Coders - + Koodaajat - Honors go to Rafal Tomczak (RadioClone), Thomas Husterer (th9x) and Erez Raviv (er9x and eePe) - + Kiitokset: Rafal Tomczak(RadioClone), Thomas Husterer (th9x) sekä Eriz Raviv (er9x ja eePe) - Thank you all !!! - + Kiitokset kaikille !!! - Contributors - + Avustajat - Companion Release Notes - + Companion muistiinpanot - OpenTX Release Notes - + OpenTX muistiinpanot customizeSplashDialog - Transmitter Splash Screen Editor - - Invert - + Käänteinen - - Open Splash Library - - - - ... - + ... - - Load Profile - - Load FW - - Load Pict - - Save - - Open + Open Firmware File - - - - Error + Virhe + + + Can not load embedded image from firmware file %1. - - Cannot load embedded FW image from %1. - - - - Open Image to load - Images (%1) - Cannot load the image file %1. - Cannot load the profile image %1. - Cannot load the library image %1. - File Saved - The image was saved to the file %1 - Image Refresh Error - Failed to refresh image from file %1 - File Save Error - Failed to write image to %1 @@ -8183,35 +6495,29 @@ m2560 for v4.1 boards downloadDialog - Downloading: - + Ladataan: - Unable to save the file %1: %2. - + Ei voida tallentaa tiedstoa %1: %2. - Companion - + Companion - Download failed: %1. - + Lataus epäonnistui %1. fusesDialog - Fuses - <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -8228,12 +6534,10 @@ p, li { white-space: pre-wrap; } - Read Fuses - <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -8252,13 +6556,11 @@ p, li { white-space: pre-wrap; } - Reset Fuses EEPROM - PROTECT - <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -8277,13 +6579,11 @@ p, li { white-space: pre-wrap; } - Reset Fuses EEPROM - DELETE - <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd"> <html><head><meta name="qrichtext" content="1" /><style type="text/css"> p, li { white-space: pre-wrap; } @@ -8298,119 +6598,63 @@ p, li { white-space: pre-wrap; } fwPreferencesDialog - Downloads - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CheckBox - Menu Language - Firmware Type - Check for updates - Voice Language - + Äänen kieli - Set language of voice. May be different from firmware language - Download Voice - Download FW - Options - Processor ID - FwInfo - Last downloaded release: %1 - The selected firmware has never been downloaded by Companion. - The selected firmware cannot be downloaded by Companion. @@ -8418,221 +6662,127 @@ May be different from firmware language joystickDialog - Configure Joystick - Ch2 - - - - - - - - Not Assigned - - - - - - - - Right Vertical - - - - - - - - Right Horizontal - - - - - - - - Left Vertical - - - - - - - - Left Horizontal - - - - - - - - P1 - + P1 - - - - - - - - P2 - + P2 - - - - - - - - P3/LS - - - - - - - - RS - + RS - Ch1 - Ch4 - Ch6 - Ch3 - Ch5 - Ch7 - Ch8 - Instructions - Cancel - + Peruuta - Next - Ok - Move sticks and pots in every direction making full movement Press next when finished - - Error - + Virhe - Cannot open joystick. - Place sticks and pots in middle position. Press next when done - Map joystick channels to controls using comboboxes. Press next when done - Check inversion checkbox to get maximum at top-right position. Press next when done - Press ok to save configuration Press cancel to abort joystick calibration - Duplicated stick assignement @@ -8640,73 +6790,59 @@ Press cancel to abort joystick calibration logsDialog - Companion Log Viewer - Filename - Open LogFile - Zoom - X - Y - Fly sessions - Telemetry logs - Time - Error - + Virhe - Cannot write file %1: %2. - Select your log file - Available fields - The selected logfile contains %1 invalid lines out of %2 total lines @@ -8714,444 +6850,301 @@ Press cancel to abort joystick calibration mdiChild - Simulate Tx - + Simuloi Tx modelConfigDialog - Model Configuration Wizard - Engine - Model Type - Airplane - Helicopter - Glider - Wing - Aileron controls - No Ailerons - 1 Servo (or Y) - - - 2 Servos - Flaps controls - No Flaps - 1 Servo (or inverting Y) - Spoilers - No Spoilers/Airbrakes - 1 Servo (or Y or inverting Y) - Swash Plate - Swash plate - 90° / Fixed / Coax - 120° - 120X° - 140° - FlyBarLess - Tail - Tail controls - 1 Servo Elevator / 1 Servo Rudder - V Tail - 2 Servos Elevator / 1 Servo Rudder - Gyroscope - NoGyro - Switch control - Pot control - Channel style - Open9x Style - Futaba Style - 2 - + 2 - 3 - + 3 - 4 - + 4 - 5 - + 5 - 6 - + 6 - 7 - + 7 - 8 - + 8 - 9 - + 9 - 1 - + 1 - 10 - + 10 - Ele2 - Use advanced controls - Spoiler2 - Flap2 - Flap1 - Rud2 - - - - - - - AUTO - - - - - - - CH01 - + CH01 - - - - - - - CH02 - + CH02 - - - - - - - CH03 - + CH03 - - - - - - - CH04 - + CH04 - - - - - - - CH05 - + CH05 - - - - - - - CH06 - + CH06 - - - - - - - CH07 - + CH07 - - - - - - - CH08 - + CH08 - - - - - - - CH09 - + CH09 - - - - - - - CH10 - + CH10 - Ail2 - Spoiler 1 - Delta wing - - Not present - Present - Rudder - Single rudder - Dual rudder (with 2 servos) - Apply configuration ? - Apply configuration deleting existing model ? @@ -9159,144 +7152,94 @@ Press cancel to abort joystick calibration preferencesDialog - - Preferences - - Simu BackLight - - Simulator capture folder - - Joystick - Remember simulator switches - - Enable - + Päälle - - Use clipboard only - - Calibrate - - Blue - - Green - - Red - - Orange - + Orans - - Yellow - + Kelt - - - - - - Open Folder - - Personal splash library - - Include companion splashes - - Only user defined splashes - - Splash library behaviour - - Custom TX splash screen - - Open Image - - - - ... - + ... - - Invert Pixels - Mode selection: Mode 1: @@ -9319,877 +7262,556 @@ Mode 4: - Mode 1 (RUD ELE THR AIL) - Mode 2 (RUD THR ELE AIL) - Mode 3 (AIL ELE THR RUD) - Mode 4 (AIL THR ELE RUD) - auto backup before write - Automatic Backup Folder - Show Splash At Start - Ask use of wizard for new models - Remember switches in simulator - Channel order This is used by the templated to determine which channel goes to what number output. - R E T A - R E A T - R T E A - R T A E - R A E T - R A T E - E R T A - E R A T - E T R A - E T A R - E A R T - E A T R - T R E A - T R A E - T E R A - T E A R - T A R E - T A E R - A R E T - A R T E - A E R T - A E T R - A T R E - A T E R - FwInfo - Check for updates - Ask for flashing after Download - Export Profile - Save Profile - Import Profile - Profile Name - Default Stick Mode - Default Channel Order - Profile slot - Automatically add version number to the filename after download - Voice - - Download - Set language of voice. May be different from firmware language - Language - Firmware - SD Structure path - Processor ID - Recent History Size - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CheckBox - Check for updates on startup - Check for selected Fw updates - Google Earth Executable - Find Executable - - - Last downloaded release: %1 - - - - - The selected firmware has never been downloaded by Companion. - - - - - The selected firmware cannot be downloaded by Companion. - - - - - Image stored in settings - - - - - - No joysticks found - - - - - Select your library folder - - - - - Select your snapshot folder - - - - - Select your Models and Settings backup folder - - - - - Select Google Earth executable - - - - - - Error - - - - - - Cannot load %1. - - - - - Select the folder replicating your SD structure - - - - - Profile name is empty, profile slot %1 will be deleted.<br>Are you sure ? - - - - - Export profile As - - - - - Profile slot is not empty, profile slot %1 will we overwritten.<br>Are you sure ? - - - - - Open Profile to import - - - - - Open Image to load - - - - - Images (%1) - - printDialog - Dialog - Close - Print - + Tulosta - Print to file - Setup for: - printed on: %1 - General Model Settings - - - - Name - + Nimi - EEprom Size - Timer1 - + Ajastin 1 - Timer2 - + Ajastin 2 - Protocol - + Protokolla - Pulse Polarity - Throttle Trim - + Kaasu trimmi - - - Enabled - - Disabled - Throttle Expo - Trim Increment - + Trimmin säätö - Center Beep - Flight modes Settings - Fades - Trims - Gvars - Rot.Enc. - - - - Switch - + Kytkin - Flight mode name - IN - OUT - - - - FM - Expo/Dr Settings - Weight - - Flight modes - - Flight mode - - DISABLED - Mixers - - - - CH - noTrim - - - - - Offset - + Tasoitus - Delay(u%1:d%2) - Slow(u%1:d%2) - Warn - Limits - - - - Min - + Min - - - - Max - + Max - - - Invert - + Käänteinen - - - INV - + KÄÄNT - - - NOR - Curves - + Käyrät - - - Curve - + Käyrä - pt %1 - Logical Switches - + Loogiset kytkimet - - LS - + LS - Global Variables - GV - Switch Assignments - Function - Parameter - Repeat - Telemetry Settings - - Alarm 1 - + Varoitus 1 - - Alarm 2 - Analog - Unit - + Yksikkö - Scale - - - - Type - - - - Condition - + Tila - - - - Value - A%1 - RSSI Alarm - Frsky serial protocol - System of units - Propeller blades - - Custom Telemetry View - Telemetry Bars - Bar Number - Source - + Lähde - Print Document - Select PDF output file - ODF files (*.odt);;PDF Files(*.pdf);;HTML-Files (*.htm *.html);;All Files (*) @@ -10197,888 +7819,658 @@ May be different from firmware language simulatorDialog - Companion Simulator - + Companion simulaattori - - - - Right Double Click to Reset - + Tuplaklikkaa oikea resetoi - THR - + KAA - RUD - + PER - ELE - + KOR - AIL - + SII - - Hold X - + Pidä X - - Fix X - + Kesk X - - Fix Y - + Kesk Y - - Hold Y - + Pidä Y - - - - TextLabel - + Tekstilappu - TRN - + TRN - GEA - + REN - ID0 - + ID0 - ID1 - + ID1 - ID2 - + ID2 - BEEP - + PIIP - P1 - + P1 - - - 0 % - + 0 % - P2 - + P2 - P3 - + P3 - 9x Simulator - + 9x simulaattori - Outputs - + Ulostulot - LS1 - + LS1 - LS2 - + LS2 - LS3 - + LS3 - LS4 - + LS4 - LS5 - + LS5 - LS6 - + LS6 - LS7 - + LS7 - LS8 - + LS8 - LS9 - + LS9 - LSA - + LSA - LSB - + LSB - LSC - + LSC - LSD - + LSD - LSE - + LSE - LSF - + LSF - LSG - + LSG - LSH - + LSH - LSI - + LSI - LSJ - + LSJ - LSK - + LSK - LSL - + LSL - LSM - + LSM - LSN - + LSN - LSO - + LSO - LSP - + LSP - LSQ - + LSQ - LSR - + LSR - LSS - + LSS - LST - + LST - LSU - + LSU - LSV - + LSV - LSW - + LSW - CH1 - + CH1 - - - - - - - - - - - - - - - - -100.1 - + -100.1 - CH9 - + CH9 - CH2 - + CH2 - CH10 - + CH10 - CH3 - + CH3 - CH11 - + CH11 - CH4 - + CH4 - CH12 - + CH12 - CH5 - + CH5 - CH13 - + CH13 - CH6 - + CH6 - CH14 - + CH14 - CH7 - + CH7 - CH15 - + CH15 - CH8 - + CH8 - CH16 - + CH16 - - Warning - + Varoitus - Joystick enabled but not configured correctly - + Joystick päällä mutta väärin aseteltu - Cannot open joystick, joystick disabled - + Joystickia ei voi avata, pois päältä - Firmware %1 error: %2 - + Firmware %1 virhe: %2 - - Flight mode: %1(%2) - + - Lentotila: %1(%2) - Simulating Tx (%1) - + Simuloi TX (%1) - Simulating - + Simuloi splashLibrary - - ... - + ... - Splash Library - page %1 of %2 - + Kuvakirjasto - sivu %1 tai %2 - Warning - + Varoitus - Invalid image in library %1 - + Väärä kuva kirjastossa %1 - Information - + Info - No valid image found in library, check your settings - + Yhtään kuvaa ei löydy kuva kirjastosta, tarkista asetukset xsimulatorDialog - Companion Simulator - + Companion simulaattori - - Hold Y - + Pidä Y - - Fix Y - + Kesk X - - Fix X - + Kesk Y - - Hold X - + Pidä X - - SD - + SD - - SC - + SC - - - - Right Double Click to Reset - + Tyhjäys, tuplaklikkaa oikeaa - - S2 - + S2 - - SG - + SG - - RS - + RS - - SH - + SH - - - - TextLabel - + Simulaattori - - S1 - + S1 - - SB - + SB - - SA - + SA - - SE - + SE - - - SF - + SF - - LS - + LS - Taranis Simulator - + Taranis simulaattori - Outputs - + Lähdöt - CH1 - + CH1 - - - - - - - - - - - - - - - - -100.1 - + -100.1 - CH9 - + CH9 - CH2 - + CH2 - CH10 - + CH10 - CH3 - + CH3 - CH11 - + CH11 - CH4 - + CH4 - CH12 - + CH12 - CH5 - + CH5 - CH13 - + CH13 - CH6 - + CH6 - CH14 - + CH14 - CH7 - + CH7 - CH15 - + CH15 - CH8 - + CH8 - CH16 - + CH16 - LSK - + LSK - LSC - + LSC - LSD - + LSD - LS7 - + LS7 - LSL - + LSL - LSB - + LSB - LS1 - + LS1 - LSH - + LSH - LSG - + LSG - LSE - + LSE - LSF - + LSF - LS8 - + LS8 - LS9 - + LS9 - LSA - + LSA - LSM - + LSM - LSJ - + LSJ - LSI - + LSI - LS4 - + LS4 - LS5 - + LS5 - LS2 - + LS2 - LS3 - + LS3 - LS6 - + LS6 - LSN - + LSN - LSO - + LSO - LSP - + LSP - LSQ - + LSQ - LSR - + LSR - LSS - + LSS - LST - + LST - LSU - + LSU - LSV - + LSV - LSW - + LSW - - Warning - + Varoitus - Joystick enabled but not configured correctly - + Joystick päällä, mutta konfiguraatio ongelma - Cannot open joystick, joystick disabled - + Ei voi avata joystickia, joystick pois käytöstä - Firmware %1 error: %2 - + Firmware %1 virhe %2 - - Flight mode: %1(%2) - + - Lennätystila %1(%2) - Simulating Tx (%1) - + Simuloi Tx(%1) - Simulating - + Simuloidaan From e2dd42658d580c7f59ce73e7a819a05f6049c133 Mon Sep 17 00:00:00 2001 From: Kjell Kernen Date: Sun, 9 Mar 2014 16:34:06 +0100 Subject: [PATCH 053/285] First Finnish translation of OpenTX (Just a few strings to start with) --- radio/src/translations/fi.h.txt | 42 ++++++++++++++++----------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/radio/src/translations/fi.h.txt b/radio/src/translations/fi.h.txt index fca9d388e..26ed4bc58 100644 --- a/radio/src/translations/fi.h.txt +++ b/radio/src/translations/fi.h.txt @@ -42,16 +42,16 @@ // NON ZERO TERMINATED STRINGS #define LEN_OFFON "\003" -#define TR_OFFON "OFF""ON\0" +#define TR_OFFON "POI""PÄÄ" #define LEN_MMMINV "\003" -#define TR_MMMINV "---""INV" +#define TR_MMMINV "---""KÄÄ" #define LEN_NCHANNELS "\004" #define TR_NCHANNELS "\0014CH\0016CH\0018CH10CH12CH14CH16CH" #define LEN_VBEEPMODE "\005" -#define TR_VBEEPMODE "Quiet""Alarm""NoKey""All " +#define TR_VBEEPMODE "Äänet""Hälyt""EiNap""Kaikk" #define LEN_VBEEPLEN "\005" #define TR_VBEEPLEN "0====""=0===""==0==""===0=""====0" @@ -69,22 +69,22 @@ #define TR_TRNCHN "CH1CH2CH3CH4" #define LEN_UART3MODES "\017" -#define TR_UART3MODES "OFF\0 ""S-Port Mirror\0 ""Debug\0 " +#define TR_UART3MODES "POIS\0 ""S-Port Pelik\0 ""Debug\0 " #define LEN_POTTYPES "\017" -#define TR_POTTYPES "Pot\0 ""Multipos Switch" +#define TR_POTTYPES "Potikka\0 ""Monias. Kytkin\0" #define LEN_DATETIME "\005" -#define TR_DATETIME "DATE:""TIME:" +#define TR_DATETIME "PÄIV:""AIKA:" #define LEN_VLCD "\006" #define TR_VLCD "NormalOptrex" #define LEN_COUNTRYCODES TR("\002", "\007") -#define TR_COUNTRYCODES TR("US""JP""EU", "America""Japan\0 ""Europe\0") +#define TR_COUNTRYCODES TR("US""JP""EU", "Amerikk""Japani\0""Euroopp") #define LEN_VTRIMINC TR("\006", "\013") -#define TR_VTRIMINC TR("Expo\0 ""ExFine""Fine\0 ""Medium""Coarse", "Exponential""Extra Fine\0""Fine\0 ""Medium\0 ""Coarse\0 ") +#define TR_VTRIMINC TR("Expo\0 ""EriHie""Hieno\0""Keski\0""Karkea", "Exponential""Eri Hieno\0 ""Hieno\0 ""Keski\0 ""Karkea\0 ") #define LEN_VBEEPCOUNTDOWN "\006" #define TR_VBEEPCOUNTDOWN "SilentBeeps\0Voice\0" @@ -797,18 +797,18 @@ #define TR_ABOUT_PARENTS_3 "ER9X (Erez Raviv)" #define TR_ABOUT_PARENTS_4 "TH9X (Thomas Husterer)" -#define TR_CHR_SHORT 's' -#define TR_CHR_LONG 'l' -#define TR_CHR_TOGGLE 't' -#define TR_CHR_HOUR 'h' -#define TR_CHR_INPUT 'I' // Values between A-I will work +#define TR_CHR_SHORT 's' +#define TR_CHR_LONG 'l' +#define TR_CHR_TOGGLE 't' +#define TR_CHR_HOUR 'h' +#define TR_CHR_INPUT 'I' // Values between A-I will work -#define TR_BEEP_VOLUME "Beep Volume" -#define TR_WAV_VOLUME "Wav Volume" -#define TR_VARIO_VOLUME "Vario Volume" -#define TR_BG_VOLUME "Bg Volume" +#define TR_BEEP_VOLUME "Piip Voim" +#define TR_WAV_VOLUME "Wav Voim" +#define TR_VARIO_VOLUME "Variom Voim" +#define TR_BG_VOLUME "Tausta Voim" -#define TR_TOP_BAR "Top Bar" -#define TR_ALTITUDE INDENT "Altitude" -#define TR_MODS_FORBIDDEN "Modifications forbidden!" -#define TR_UNLOCKED "Unlocked" +#define TR_TOP_BAR "Ylä palkki" +#define TR_ALTITUDE INDENT "Korkeus" +#define TR_MODS_FORBIDDEN "Muutokset kielletty!" +#define TR_UNLOCKED "Avattu" From cec0a9cd3bafcd07c735eb9a6370c2f3968ba822 Mon Sep 17 00:00:00 2001 From: Kjell Kernen Date: Sun, 9 Mar 2014 16:42:22 +0100 Subject: [PATCH 054/285] Translated latest Swedish strings --- companion/src/translations/companion_sv.ts | 646 +++++++++++++-------- 1 file changed, 389 insertions(+), 257 deletions(-) diff --git a/companion/src/translations/companion_sv.ts b/companion/src/translations/companion_sv.ts index 091cd0560..5ca910c7f 100644 --- a/companion/src/translations/companion_sv.ts +++ b/companion/src/translations/companion_sv.ts @@ -168,12 +168,12 @@ - + ON På - + Error Fel @@ -1844,30 +1844,30 @@ FAI-funktionen kan inte slås av i sändaren. InputsPanel - + Move Up Flytta uppåt - - + + Ctrl+Up Ctrl+Up - - + + Move Down Flytta nedåt - - + + Ctrl+Down Ctrl+Down - + Source(%1) Källa(%1) @@ -1897,7 +1897,7 @@ FAI-funktionen kan inte slås av i sändaren. För få filter är tillgängliga! - + Delete Selected Inputs? Radera valda filter? @@ -1985,7 +1985,7 @@ FAI-funktionen kan inte slås av i sändaren. LogicalSwitchesPanel - + Condition Villkor @@ -2066,13 +2066,13 @@ FAI-funktionen kan inte slås av i sändaren. - - + + File loaded Filen har laddats - + @@ -2128,7 +2128,7 @@ Vill du ladda ned den nya versionen nu ? Filen sparades - + Copyright Copyright @@ -2149,7 +2149,7 @@ Vill du ladda ned den nya versionen nu ? Spara Som... - + Exit Avsluta @@ -2347,7 +2347,7 @@ Vill du ladda ned den nya versionen nu ? &Sök efter uppdateringar... - + Display previous message again at startup ? Skall föregående varning visas igen vid uppstart ? @@ -2381,7 +2381,7 @@ Vill du ladda ned den nu ? Skriv Modeller och Inställningar från %1 till sändaren? - + Conversion failed Konverteringen misslyckades @@ -2405,7 +2405,7 @@ Vill du ladda ned den nu ? &Inställningar... - + Edit Settings Redigera Inställningar @@ -2535,7 +2535,7 @@ Vill du ladda ned den nu ? Companion - Editor för Modeller och Inställningar - %1 - + Checking for updates Letar efter uppdateringar @@ -2550,7 +2550,7 @@ Vill du ladda ned den nu ? Ladda inte ned versionen (r%1)? - + OpenTX Home Page: <a href='%1'>%1</a> OpenTX Hemsida: <a href='%1'>%1</a> @@ -2594,7 +2594,7 @@ Vill du ladda ned den nu ? &Skriv Modeller och Inställningar till sändaren - + Write Models and Settings to transmitter Skriv Modeller och Inställningar till sändaren @@ -2743,29 +2743,29 @@ Vill du ladda ned den nu ? - + Edit Redigera - - + + Help Hjälp - - + + Radio Settings Profile Radioprofil - + Show recent Models+Settings documents Visa senaste Modeller+Inställningar-dokument - + Show a selection list of radio settings profiles Visa en lista med radioprofiler @@ -2779,7 +2779,7 @@ Vill du ladda ned den nu ? &Bidragsgivare... - + Display previous warning again at startup ? SKall föregående varning visas igen vid uppstart ? @@ -2789,19 +2789,19 @@ Vill du ladda ned den nu ? - + - + Error Fel - + Cannot write file %1: %2. Filen %1 kunde inte skrivas: @@ -2815,7 +2815,7 @@ Vill du ladda ned den nu ? - + Error opening file %1: @@ -2824,7 +2824,7 @@ Vill du ladda ned den nu ? %2. - + Compilation server termporary failure, try later Tillfälligt fel i byggservern. Försök igen senare @@ -2845,26 +2845,26 @@ Vill du ladda ned den nu ? Jämför... - + Compare models Jämför modeller - - + + Backup is impossible Säkerhetskopiering kan inte utföras - - + + The backup dir set in preferences does not exist Foldern för säkerhetskopior existerar inte - + Warning Varning @@ -2878,7 +2878,7 @@ Vill du ladda ned den nu ? &Läs/Skriv - + Write Skriv @@ -2894,7 +2894,7 @@ Vill du ladda ned den nu ? Kan inte hitta filen %1 ! - + Error reading file %1: %2. Fel vid inläsning från filen %1: @@ -2905,7 +2905,7 @@ Vill du ladda ned den nu ? ladda&Backup... - + Load backup from file Ladda backup från fil @@ -2922,16 +2922,16 @@ Vill du ladda ned den nu ? Öppna loggfil - + - + Taranis radio not found Hittade inte någon Taranis-sändare - + @@ -3002,12 +3002,12 @@ Vill du ladda ned den nu ? - + Open Models and Settings file Öppna Modeller och Inställningar-fil - + Firmware updates Firmware-uppdatering @@ -3019,14 +3019,14 @@ Vill du ladda ned den nu ? - + - + Read Models and Settings From Tx Läs Modeller och Inställningar från sändaren - + The file %1 has not been recognized as a valid Models and Settings file Write anyway ? @@ -3039,13 +3039,13 @@ Starta skrivningen i alla fall ? - + Backup Models and Settings From Tx Säkerhetskopiera Modeller och Inställningar från sändaren - + Cannot check Models and Settings compatibility! Continue anyway? Det går inte att verifiera att Modeller och Inställningar är kompatibla. Fortsätt i alla fall? @@ -3061,12 +3061,12 @@ Starta skrivningen i alla fall ? - + Write Models and Settings To Tx Skriv Modeller och Inställningar till sändaren - + Write Firmware To Tx Skriv firmware till sändaren @@ -3162,7 +3162,7 @@ Starta skrivningen i alla fall ? Ny Profil - + Create a new Radio Setting Profile Lägg till en ny profil med radio-inställningar @@ -3469,12 +3469,12 @@ Starta skrivningen i alla fall ? - + Recent Models+Settings Senaste Modell+Inställnings-filer - + Set Icon Theme Ställ in Ikontema @@ -3492,13 +3492,13 @@ Starta skrivningen i alla fall ? Profiler för Radioinställningar - + Invalid Models and Settings File %1 Filen innehåller inte Modeller och Inställningar: %1 - + Invalid binary Models and Settings File %1 Den binära filen innehåller inte Modeller och Inställningar: %1 @@ -3988,59 +3988,59 @@ p, li { white-space: pre-wrap; } MixesPanel - + Move Up Flytta uppåt - - + + Ctrl+Up Ctrl+Up - - + + Move Down Flytta nedåt - - + + Ctrl+Down Ctrl+Down - + Clear Mixes Nollställ mixarna - - + + X%1 X%1 - - - + + + CH%1%2 KN%1%2 - + Weight(%1) Vikt(%1) - + Switch(%1) Brytare(%1) - + No Trim Ingen Trim @@ -4519,12 +4519,12 @@ p, li { white-space: pre-wrap; } P3 - + MAX MAX - + A1 A1 @@ -4534,12 +4534,12 @@ p, li { white-space: pre-wrap; } A2 - + T1 T1 - + T2 T2 @@ -4552,7 +4552,7 @@ p, li { white-space: pre-wrap; } er9x - + Trainer Trainer @@ -4592,15 +4592,15 @@ p, li { white-space: pre-wrap; } Starta loggning - - - + + + ---- ---- - + Rud Rod @@ -4624,24 +4624,24 @@ p, li { white-space: pre-wrap; } Ske - - + + Timer1 Timer1 - - + + Timer2 Timer2 - - + + Warning Varning @@ -4660,21 +4660,46 @@ p, li { white-space: pre-wrap; } Det finns ännu ingen simulator för denna typ av firmware - - + + REa REa - - + + REb REb - + + RSSI Tx + RSSI Tx + + + + RSSI Rx + RSSI Rx + + + + Rx Batt + Rx Batt + + + + A3 + A3 + + + + A4 + A4 + + + Alt Höj @@ -4704,209 +4729,208 @@ p, li { white-space: pre-wrap; } GPS Höj - + Cell Batt - - + + LS1 LB1 - - + + LS2 LB2 - - + + LS3 LB3 - - + + LS4 LB4 - - + + LS5 LB5 - - + + LS6 LB6 - - + + LS7 LB7 - - + + LS8 LB8 - - + + LS9 LB9 - - + + LSA LBA - - + + LSB LBB - - + + LSC LBC - - + + LSD LBD - - + + LSE LBE - - + + LSF LBF - - + + LSG LBG - - + + LSH LBH - - + + LSI LBI - - + + LSJ LBJ - - + + LSK LBK - - + + LSL LBL - - + + LSM LBM - - + + LSN LBN - - + + LSO LBO - - + + LSP LBP - - + + LSQ LBQ - - + + LSR LBR - - + + LSS LBS - - + + LST LBT - - + + LSU LBU - - + + LSV LBV - - + + LSW LBW - Input %1 - Filter %1 + Filter %1 - + CYC%1 CYC%1 @@ -4916,13 +4940,13 @@ p, li { white-space: pre-wrap; } PPM%1 - + THR GAS - + ON På @@ -4935,7 +4959,7 @@ p, li { white-space: pre-wrap; } Av - + Safety %1 Säkring %1 @@ -4945,7 +4969,7 @@ p, li { white-space: pre-wrap; } th9x stödjer inte inställningshjul för detta sändarkort - + TrmR TrmR @@ -4965,7 +4989,7 @@ p, li { white-space: pre-wrap; } TrmA - + Play Haptic Spela Vibration @@ -4999,12 +5023,17 @@ p, li { white-space: pre-wrap; } Spela Värde - + Cels Celsius - + + S3 + S3 + + + Vfas Vfas @@ -5014,7 +5043,7 @@ p, li { white-space: pre-wrap; } Ström - + VSpd VHastighet @@ -5029,7 +5058,7 @@ p, li { white-space: pre-wrap; } A2- - + Alt- Hjd- @@ -5064,17 +5093,16 @@ p, li { white-space: pre-wrap; } Avstånd+ - + Cur+ Ström+ - ACC - ACC + ACC - + Time Tid @@ -5109,7 +5137,7 @@ p, li { white-space: pre-wrap; } Inm.Hjul E - + Play Track Spela Spår @@ -5150,7 +5178,7 @@ p, li { white-space: pre-wrap; } Det går inte att använda Expo på en specialkurva i open9x - + Support for frsky telemetry mod Stöd för FrSky telemeri @@ -5400,7 +5428,7 @@ p, li { white-space: pre-wrap; } Slå på helikoptermenyn och stöd för cyklisk mix - + CH%1%2 KN%1%2 @@ -5410,21 +5438,21 @@ p, li { white-space: pre-wrap; } X%1 - - + + GV%1 GV%1 - + - + --- ---- - + Rud Trim Rod.Trim @@ -5464,7 +5492,7 @@ p, li { white-space: pre-wrap; } KN%1 - + Background Music Bakgrundsmusik @@ -5494,7 +5522,7 @@ p, li { white-space: pre-wrap; } Eget värde - + -GV%1 -GV%1 @@ -5546,22 +5574,20 @@ p, li { white-space: pre-wrap; } RS - + Batt Batt - Tx - Tx + Tx - Rx - Rx + Rx - + Cnsp Cnsp @@ -5571,7 +5597,7 @@ p, li { white-space: pre-wrap; } Powr - + AccX AccX @@ -5586,7 +5612,7 @@ p, li { white-space: pre-wrap; } AccZ - + HDG HDG @@ -5602,6 +5628,16 @@ p, li { white-space: pre-wrap; } + A3- + A3- + + + + A4- + A4- + + + Cel- @@ -5611,7 +5647,52 @@ p, li { white-space: pre-wrap; } - + + Cels- + + + + + ACC + + + + + [I%1] + + + + + S31 + S31 + + + + S32 + S32 + + + + S33 + S33 + + + + S34 + S34 + + + + S35 + S35 + + + + S36 + S36 + + + RudTrim Left RoderTrim Vänster @@ -5750,6 +5831,11 @@ p, li { white-space: pre-wrap; } |d|>=x |d|>=x + + + a=x + a=x + a~x @@ -5797,7 +5883,7 @@ p, li { white-space: pre-wrap; } - + No repeat Repetera ej @@ -5855,7 +5941,7 @@ p, li { white-space: pre-wrap; } %1s - + Value Värde @@ -5875,7 +5961,7 @@ p, li { white-space: pre-wrap; } Ökning - + Yellow Gul @@ -6011,22 +6097,21 @@ p, li { white-space: pre-wrap; } Batteriikon - + SWR SWR - RSSI - RSSI + RSSI - + Pwr+ - + S11 S11 @@ -6086,7 +6171,7 @@ p, li { white-space: pre-wrap; } S26 - + Diff(%1) Diff(%1) @@ -6111,7 +6196,7 @@ p, li { white-space: pre-wrap; } !Kurva(%1) - + FM%1 FM%1 @@ -6182,20 +6267,24 @@ p, li { white-space: pre-wrap; } Flygläge %1 värde - openTx only accepts %1 points in all curves - openTX accepterar bar %1 punkter i alla kurvor + openTX accepterar bar %1 punkter i alla kurvor - - + + OpenTX only accepts %1 points in all curves + OpenTX accepterar bara %1 punkter i alla kurvor + + + + OpenTX on this board doesn't accept this function OpenTX stödjer inte funktionen för den aktuella hårdvaran - + OpenTX doesn't accept this protocol OpenTX accepterar inte detta protokoll @@ -6206,14 +6295,14 @@ p, li { white-space: pre-wrap; } OpenTX accepterar inte detta antal kanaler - + Your radio probably uses a wrong firmware, eeprom size is 4096 but only the first 2048 are used Din sändare har antagligen laddats med felaktig programvara. eeprom-storleken är 4096, men enbart den första hälften används - + Support for MAVLINK devices Stöd för MAVLINK-enheter @@ -7282,7 +7371,7 @@ Gasen reverseras om alternativet väljs. Tomgång ligger då uppåt. Trim och ga Programmets Inställningar - + Simulator capture folder Lagra simulatorbilder i @@ -7305,12 +7394,12 @@ Gasen reverseras om alternativet väljs. Tomgång ligger då uppåt. Trim och ga Egna Startbilder - + Edit Settings Redigera Inställningar - + Application Settings Programmet @@ -7554,16 +7643,50 @@ Detta används av mallen för att koppla kanal till output-nummer. Spaktilldelning - + + 9X + 9X + + + + 9X with m128 + 9X med m128 + + + + 9XR + 9XR + + + + 9XR with m128 + 9XR med m128 + + + + Gruvin9x Board + Gruvin9X-kort + + + + Sky9x Board + Sky9x-kort + + + + Taranis + Taranis + + Firmware File - Firmware + Firmware Settings Profile Profil - + Splash Screen Startbild @@ -7583,17 +7706,16 @@ Detta används av mallen för att koppla kanal till output-nummer. Sökväg till SD-struktur - Firmware Variant - Firmware-typ + Firmware-typ - + Select Image Välj Bild - + Offer to write FW to Tx after download Skriv FW till Tx efter nedladdning @@ -7613,7 +7735,12 @@ Detta används av mallen för att koppla kanal till output-nummer. Ta bort Profil - + + Radio Type + Radiotyp + + + Clear Image Ta bort Bild @@ -7630,7 +7757,7 @@ Detta används av mallen för att koppla kanal till output-nummer. Enbart användarens bilder - + Splash Screen Library Bibliotek för startbilder @@ -7705,13 +7832,18 @@ Detta används av mallen för att koppla kanal till output-nummer. Säkerhetskopiera innan firmware-skrivning - + + My Radio + Min Radio + + + Select your snapshot folder Välj katalog för snapshots av Tx-simulatorn - + No joysticks found Ingen joystick hittades @@ -7736,7 +7868,7 @@ Detta används av mallen för att koppla kanal till output-nummer. Välj katalog med en kopia av din SD-struktur - + Not possible to remove profile Det går inte att ta bort profilen @@ -7754,7 +7886,7 @@ Detta används av mallen för att koppla kanal till output-nummer. Det går inte att ladda %1. - + Open Image to load Öppna bild för laddning @@ -7777,7 +7909,7 @@ Detta används av mallen för att koppla kanal till output-nummer. Visa Detaljer - + Writing Skriver @@ -7789,19 +7921,19 @@ Detta används av mallen för att koppla kanal till output-nummer. Läser - + Verifying Verifierar - + FUSES: Low=%1 High=%2 Ext=%3 Vad är EXT? SÄKRINGAR: Låg=%1 Hög=%2 Ext=%3 - + result result resultat @@ -7813,55 +7945,55 @@ Detta används av mallen för att koppla kanal till output-nummer. program hittades ej - + done - exit code %1 done - exit code %1 klar - returkod %1 - + done with errors done with errors klar, men med fel - - + + done - SUCCESSFUL done - SUCCESSFUL klar - FRAMGÅNG - + did not finish correctly did not finish correctly avslutade inte korrekt - + finished correctly finished correctly avslutade korrekt - + Started Started Startade - - + + Error Fel - + Cannot open source file Kan inte öppna ursprungsfilen - + Cannot write destination Det gick inte att skriva till målet @@ -7871,22 +8003,22 @@ Detta används av mallen för att koppla kanal till output-nummer. Skriver till fi: - + ie: OpenTX for 9X board or OpenTX for 9XR board dvs: OpenTX för 9X eller OpenTX för 9XR - + ie: OpenTX for M128 / 9X board or OpenTX for 9XR board with M128 chip dvs: OpenTX för 9X eller 9XR med M128-processor - + ie: OpenTX for Gruvin9X board dvs: OpenTX för 9X med Gruvin9X-kort - + Your radio uses a %1 CPU!!! Please check advanced burn options to set the correct cpu type. @@ -7895,7 +8027,7 @@ Please check advanced burn options to set the correct cpu type. Välj rätt CPU-typ i de avancerade inställningarna i Brännar-menyn. - + Your radio uses a %1 CPU!!! Please select an appropriate firmware type to program it. @@ -7913,7 +8045,7 @@ Du använder för närvarande: %1 - + did not finish correctly! Do you want some help ? did not finish correctly! @@ -7927,7 +8059,7 @@ Vill du ha hjälp ? Kopieringen gick inte bra - + Copy finished correctly Kopieringen gick bra @@ -9162,7 +9294,7 @@ m2560 för v4.1-kort Nedladdning: - + Unable to save the file %1: %2. Kan ej spara filen %1: %2. @@ -9334,7 +9466,7 @@ p, li { white-space: pre-wrap; } - + @@ -9481,7 +9613,7 @@ Används av mallarna för att koppla ihop kanaler med numrerade utgångar.Spara Profil - + Menu Language Menyspråk @@ -9490,7 +9622,7 @@ Används av mallarna för att koppla ihop kanaler med numrerade utgångar.Profil - + Voice Language Röstspråk From b389495e7b5a5a0ee237570634db1b1bac65d831 Mon Sep 17 00:00:00 2001 From: Kjell Kernen Date: Sun, 9 Mar 2014 17:12:16 +0100 Subject: [PATCH 055/285] Translated latest strings. Fixed bug someone had introduced with missing selection string. Changed back to using caps in menus. --- radio/src/translations/se.h.txt | 74 ++++++++++++++++----------------- 1 file changed, 37 insertions(+), 37 deletions(-) diff --git a/radio/src/translations/se.h.txt b/radio/src/translations/se.h.txt index e559b277f..3f0347e9b 100644 --- a/radio/src/translations/se.h.txt +++ b/radio/src/translations/se.h.txt @@ -72,7 +72,7 @@ #define TR_UART3MODES "Av\0 ""Spegling av S-Port""Debug\0 " #define LEN_POTTYPES "\020" -#define TR_POTTYPES "Potentiometer\0 ""Flerlägesväljare" +#define TR_POTTYPES "Ingen\0 ""Potentiometer\0 ""Flerlägesväljare" #define LEN_DATETIME "\005" #define TR_DATETIME "DAG: ""TID: " @@ -168,7 +168,7 @@ #endif #if defined(CPUARM) - #define TR_CSWEQUAL "a=x\0 " + #define TR_CSWEQUAL "a=x\0 " #else #define TR_CSWEQUAL #endif @@ -223,9 +223,9 @@ #endif #ifdef GVARS - #define TR_ADJUST_GVAR "Justera\0 " + #define TR_ADJUST_GVAR "Justera\0 " #else - #define TR_ADJUST_GVAR "[AdjustGV]" + #define TR_ADJUST_GVAR "[Just. GV]" #endif #ifdef DEBUG @@ -511,7 +511,7 @@ #define TR_RENAVIG "RotEnc Navig" #define TR_THROTTLEREVERSE "Revers.Gas" #define TR_MINUTEBEEP INDENT"Minutpip" -#define TR_BEEPCOUNTDOWN INDENT"Räkna Ned" +#define TR_BEEPCOUNTDOWN INDENT"Räkna ned" #define TR_PERSISTENT TR("Jämt på ",INDENT"Alltid På") #define TR_BACKLIGHT_LABEL "Belysning" #define TR_BLDELAY INDENT"Av efter" @@ -566,40 +566,40 @@ #define TR_BADEEPROMDATA "Minnet kan inte tolkas" #define TR_EEPROMFORMATTING "Minnet Nollställs" #define TR_EEPROMOVERFLOW "Minnesfel" -#define TR_MENURADIOSETUP "Inställningar" -#define TR_MENUDATEANDTIME "Dag och Tid" -#define TR_MENUTRAINER "Trainer (PPM in)" -#define TR_MENUVERSION "Version" -#define TR_MENUDIAG TR("Brytare","Test av Brytare") -#define TR_MENUANA "Analoga Värden" -#define TR_MENUCALIBRATION "Kalibrering" +#define TR_MENURADIOSETUP "INSTÄLLNINGAR" +#define TR_MENUDATEANDTIME "DAG OCH TID" +#define TR_MENUTRAINER "TRAINER (PPM IN)" +#define TR_MENUVERSION "VERSION" +#define TR_MENUDIAG TR("BRYTARE","TEST AV BRYTARE") +#define TR_MENUANA "ANALOGA VÄRDEN" +#define TR_MENUCALIBRATION "KALIBRERING" #define TR_TRIMS2OFFSETS "\004[Spara Trimvärden]" -#define TR_MENUMODELSEL TR("Modell","Välj Modell") -#define TR_MENUSETUP TR("Värden","Modellinställningar") -#define TR_MENUFLIGHTPHASE "Flygläge" -#define TR_MENUFLIGHTPHASES "Flyglägen" -#define TR_MENUHELISETUP "Helikopter" +#define TR_MENUMODELSEL TR("MODELL","VÄLJ MODELL") +#define TR_MENUSETUP TR("VÄRDEN","MODELLINSTÄLLNINGAR") +#define TR_MENUFLIGHTPHASE "FLYGLÄGE" +#define TR_MENUFLIGHTPHASES "FLYGLÄGEN" +#define TR_MENUHELISETUP "HELIKOPTER" #if defined(PCBTARANIS) - #define TR_MENUINPUTS TR("Filter","Filtrerad Insignal") - #define TR_MENULIMITS "Gränser" + #define TR_MENUINPUTS TR("FILTER","FILTRERAD INSIGNAL") + #define TR_MENULIMITS "GRÄNSER" #elif defined(PPM_CENTER_ADJUSTABLE) || defined(PPM_LIMITS_SYMETRICAL) // The right menu titles for the gurus ... - #define TR_MENUINPUTS "Spakar" - #define TR_MENULIMITS "Gränser" + #define TR_MENUINPUTS "SPAKAR" + #define TR_MENULIMITS "GRÄNSER" #else - #define TR_MENUINPUTS TR("DR/Expo","DualRates/Expo") - #define TR_MENULIMITS "Gränser" + #define TR_MENUINPUTS TR("DR/EXPO","DUALRATES/EXPO") + #define TR_MENULIMITS "GRÄNSER" #endif -#define TR_MENUCURVES "Kurvor" -#define TR_MENUCURVE "Kurva" -#define TR_MENULOGICALSWITCH "Logisk Brytare" -#define TR_MENULOGICALSWITCHES "Logiska Brytare" -#define TR_MENUCUSTOMFUNC "BrytarFunktioner" -#define TR_MENUTELEMETRY "Telemetri" -#define TR_MENUTEMPLATES "Mallar" -#define TR_MENUSTAT "Statistik" -#define TR_MENUDEBUG "Debug" +#define TR_MENUCURVES "KURVOR" +#define TR_MENUCURVE "KURVA" +#define TR_MENULOGICALSWITCH "LOGISK BRYTARE" +#define TR_MENULOGICALSWITCHES "LOGISKA BRYTARE" +#define TR_MENUCUSTOMFUNC "BRYTARFUNKTIONER" +#define TR_MENUTELEMETRY "TELEMETRI" +#define TR_MENUTEMPLATES "MALLAR" +#define TR_MENUSTAT "STATISTIK" +#define TR_MENUDEBUG "DEBUG" #define TR_RXNUM "RxNum" #define TR_SYNCMENU "Synk [MENU]" #define TR_LIMIT INDENT"Nivå" @@ -672,7 +672,7 @@ #define TR_GLOBAL_VARS "Globala Variabler" #define TR_GLOBAL_V "GLOBAL V." #define TR_GLOBAL_VAR "Global Variabel" -#define TR_MENUGLOBALVARS "Globala Variabler" +#define TR_MENUGLOBALVARS "GLOBALA VARIABLER" #define TR_OWN "Egen" #define TR_DATE "Datum" #define TR_ROTARY_ENCODER "R.Enks" @@ -702,7 +702,7 @@ #define TR_CF "BF" #define TR_SPEAKER INDENT"Högtalare" #define TR_BUZZER INDENT"Summer" -#define TR_BYTES "bytes" +#define TR_BYTES "byte" #define TR_MODULE_BIND "[Bind]" #define TR_MODULE_RANGE "[Testa]" #define TR_RESET_BTN "[Nollställ]" @@ -714,15 +714,15 @@ #define TR_CHANNELRANGE INDENT "Kanalområde" #define TR_LOWALARM INDENT "Låg-alarm" #define TR_CRITICALALARM INDENT "Kritiskt alarm" -#define TR_PERSISTENT_MAH INDENT "Store mAh" -#define TR_CHECKLIST "Display Checklist" +#define TR_PERSISTENT_MAH INDENT "Lagra mAh" +#define TR_CHECKLIST "Visa checklisa" #define TR_FAS_OFFSET TR(INDENT "FAS Ofs", INDENT "FAS Offset") #define TR_UART3MODE "Serieporten" #if defined(MAVLINK) #define TR_MAVLINK_RC_RSSI_SCALE_LABEL "Max RSSI" #define TR_MAVLINK_PC_RSSI_EN_LABEL "PC RSSI EN" - #define TR_MAVMENUSETUP_TITLE "MavlinkInställningar" + #define TR_MAVMENUSETUP_TITLE "MAVLINKINSTÄLLNINGAR" #define TR_MAVLINK_BAUD_LABEL "Baudrate" #define TR_MAVLINK_INFOS "INFOS" #define TR_MAVLINK_MODE "LÄGE" From e000eb586a290b510423e5ed03360d9a056861d2 Mon Sep 17 00:00:00 2001 From: Kjell Kernen Date: Sun, 9 Mar 2014 21:31:45 +0100 Subject: [PATCH 056/285] Fixed width size bug in burndialog Translated versions of the dialog would get the texts cut by the splash images. --- companion/src/burndialog.ui | 42 ++++++++++--------------------------- 1 file changed, 11 insertions(+), 31 deletions(-) diff --git a/companion/src/burndialog.ui b/companion/src/burndialog.ui index 772304390..2428606bc 100644 --- a/companion/src/burndialog.ui +++ b/companion/src/burndialog.ui @@ -6,8 +6,8 @@ 0 0 - 440 - 423 + 399 + 564 @@ -18,7 +18,7 @@ - 440 + 0 0 @@ -171,6 +171,12 @@ 0 + + + 250 + 0 + + true @@ -254,8 +260,8 @@ - - + + @@ -289,32 +295,6 @@ - - - - Qt::Horizontal - - - - 40 - 20 - - - - - - - - Qt::Horizontal - - - - 40 - 20 - - - - From 4f6b60bdd588648b585c87cf28ad0c46bf71bedb Mon Sep 17 00:00:00 2001 From: Kjell Kernen Date: Sun, 9 Mar 2014 22:49:45 +0100 Subject: [PATCH 057/285] Fixing width bug due to fixed dialog width --- companion/src/apppreferencesdialog.ui | 904 +++++++++++++------------- 1 file changed, 439 insertions(+), 465 deletions(-) diff --git a/companion/src/apppreferencesdialog.ui b/companion/src/apppreferencesdialog.ui index f5d4b9deb..342e1b3e7 100644 --- a/companion/src/apppreferencesdialog.ui +++ b/companion/src/apppreferencesdialog.ui @@ -6,8 +6,8 @@ 0 0 - 685 - 462 + 734 + 492 @@ -18,7 +18,7 @@ - 685 + 0 0 @@ -47,450 +47,9 @@ 0 - - - Application Settings - - - - - - Qt::Horizontal - - - - - - - Qt::Horizontal - - - - 40 - 20 - - - - - - - - Automatic Backup Folder - - - - - - - - 40 - 0 - - - - - 50 - 16777215 - - - - 15 - - - 10 - - - - - - - - 0 - 0 - - - - User Splash Screens - - - - - - - - 0 - 0 - - - - - Only show user splash images - - - - - Show user and companion splash images - - - - - - - - Google Earth Executable - - - - - - - Automatic check for OpenTX firmware updates - - - true - - - - - - - - 350 - 0 - - - - true - - - - - - - Open Folder - - - - - - - Qt::Horizontal - - - - - - - - 350 - 0 - - - - true - - - - - - - Find Executable - - - - - - - - 0 - 0 - - - - Files to keep - - - - - - - - 0 - 0 - - - - Splash Screen Library - - - - - - - Enable automatic backup before writing firmware - - - - - - - Open Folder - - - - - - - Qt::Vertical - - - - 20 - 40 - - - - - - - - Qt::Horizontal - - - - - - - Automatic check for Companion updates - - - true - - - - - - - Qt::Horizontal - - - - - - - Offer to use wizard for new models - - - true - - - - - - - Show splash screen when Companion starts - - - true - - - - - - - Qt::Horizontal - - - - 40 - 20 - - - - - - - - true - - - true - - - - - - - - Simulator Settings - - - - - - - 0 - 0 - - - - Simulator BackLight - - - Qt::AlignLeading|Qt::AlignLeft|Qt::AlignVCenter - - - - - - - Enable - - - - - - - Open Folder - - - false - - - - - - - Qt::Horizontal - - - - 40 - 20 - - - - - - - - - 100 - 16777215 - - - - - Blue - - - - - Green - - - - - Red - - - - - Orange - - - - - Yellow - - - - - - - - - 0 - 0 - - - - Joystick - - - - - - - Only capture to clipboard - - - - - - - - 0 - 0 - - - - - - - - Calibrate - - - - - - - Remember simulator switch values - - - - - - - Simulator capture folder - - - - - - - Qt::Vertical - - - - 20 - 40 - - - - - - - - true - - - - 350 - 0 - - - - true - - - - - - Radio Settings Profile + Radio Profile @@ -804,19 +363,6 @@ This is used by the templated to determine which channel goes to what number out - - - - Qt::Horizontal - - - - 40 - 20 - - - - @@ -867,6 +413,13 @@ This is used by the templated to determine which channel goes to what number out + + + + Clear Image + + + @@ -881,13 +434,6 @@ This is used by the templated to determine which channel goes to what number out - - - - Clear Image - - - @@ -987,6 +533,434 @@ This is used by the templated to determine which channel goes to what number out + + + + Qt::Horizontal + + + + 40 + 20 + + + + + + + + + Application Settings + + + + + + Open Folder + + + + + + + Qt::Horizontal + + + + + + + Automatic Backup Folder + + + + + + + + 40 + 0 + + + + + 50 + 16777215 + + + + 15 + + + 10 + + + + + + + + 0 + 0 + + + + User Splash Screens + + + + + + + + 0 + 0 + + + + + Only show user splash images + + + + + Show user and companion splash images + + + + + + + + Google Earth Executable + + + + + + + Automatic check for OpenTX firmware updates + + + true + + + + + + + + 350 + 0 + + + + true + + + + + + + Open Folder + + + + + + + Qt::Horizontal + + + + + + + + 350 + 0 + + + + true + + + + + + + Find Executable + + + + + + + + 0 + 0 + + + + Files to keep + + + + + + + + 0 + 0 + + + + Splash Screen Library + + + + + + + Enable automatic backup before writing firmware + + + + + + + Qt::Horizontal + + + + + + + Automatic check for Companion updates + + + true + + + + + + + Qt::Horizontal + + + + + + + Offer to use wizard for new models + + + true + + + + + + + Show splash screen when Companion starts + + + true + + + + + + + true + + + true + + + + + + + Qt::Vertical + + + + 20 + 40 + + + + + + + + + Simulator Settings + + + + + + + 0 + 0 + + + + Simulator BackLight + + + Qt::AlignLeading|Qt::AlignLeft|Qt::AlignVCenter + + + + + + + Enable + + + + + + + Open Folder + + + false + + + + + + + + 100 + 16777215 + + + + + Blue + + + + + Green + + + + + Red + + + + + Orange + + + + + Yellow + + + + + + + + + 0 + 0 + + + + Joystick + + + + + + + Only capture to clipboard + + + + + + + + 0 + 0 + + + + + + + + Calibrate + + + + + + + Remember simulator switch values + + + + + + + Simulator capture folder + + + + + + + Qt::Vertical + + + + 20 + 40 + + + + + + + + true + + + + 350 + 0 + + + + true + + + + + + + Qt::Horizontal + + + + 40 + 20 + + + + From fcdc6f68bdf58d43a96194506c4e36367d29b95a Mon Sep 17 00:00:00 2001 From: Kjell Kernen Date: Sun, 9 Mar 2014 23:19:20 +0100 Subject: [PATCH 058/285] Fixing image size bugs caused by the use of a frame --- companion/src/apppreferencesdialog.ui | 2 +- companion/src/burndialog.ui | 7 +++++-- companion/src/customizesplashdialog.ui | 8 +++++++- 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/companion/src/apppreferencesdialog.ui b/companion/src/apppreferencesdialog.ui index 342e1b3e7..865c969a5 100644 --- a/companion/src/apppreferencesdialog.ui +++ b/companion/src/apppreferencesdialog.ui @@ -484,7 +484,7 @@ This is used by the templated to determine which channel goes to what number out QFrame::Plain - 1 + 0 diff --git a/companion/src/burndialog.ui b/companion/src/burndialog.ui index 2428606bc..e766d31f9 100644 --- a/companion/src/burndialog.ui +++ b/companion/src/burndialog.ui @@ -277,8 +277,8 @@ - 212 - 64 + 214 + 66 @@ -287,6 +287,9 @@ QFrame::Plain + + 0 + diff --git a/companion/src/customizesplashdialog.ui b/companion/src/customizesplashdialog.ui index 72b241276..9a6971893 100644 --- a/companion/src/customizesplashdialog.ui +++ b/companion/src/customizesplashdialog.ui @@ -10,7 +10,7 @@ 0 0 1087 - 285 + 298 @@ -165,6 +165,9 @@ QFrame::Plain + + 0 + @@ -470,6 +473,9 @@ QFrame::Plain + + 0 + From ce8880e162d2950d5cb9bbe244418a5c6cb516de Mon Sep 17 00:00:00 2001 From: Romolo Manfredini Date: Wed, 12 Mar 2014 02:53:51 +0100 Subject: [PATCH 059/285] Fix segfault in c9x --- companion/src/mainwindow.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/companion/src/mainwindow.h b/companion/src/mainwindow.h index 37535e94b..c3b9ed2e9 100644 --- a/companion/src/mainwindow.h +++ b/companion/src/mainwindow.h @@ -49,7 +49,7 @@ #include "eeprominterface.h" #define SPLASH_TIME 5 -#define MAX_RECENT 10 +#define MAX_RECENT 15 #define MAX_PROFILES 15 class MdiChild; From 68c270760c467f28142313f69b60562b0b74c98e Mon Sep 17 00:00:00 2001 From: bsongis Date: Wed, 12 Mar 2014 16:06:13 +0100 Subject: [PATCH 060/285] Now bootloader OK on Taranis --- radio/src/Makefile | 6 +- radio/src/bootloader/Makefile | 27 +++- radio/src/bootloader/boot.cpp | 141 ++++++++---------- radio/src/gui/menu_general.cpp | 30 ++-- radio/src/lcd.h | 4 + .../Source/Templates/system_stm32f2xx.c | 2 +- radio/src/targets/taranis/diskio.cpp | 47 +++--- radio/src/targets/taranis/lcd_driver.cpp | 6 +- .../src/targets/taranis/usbd_storage_msd.cpp | 11 +- 9 files changed, 123 insertions(+), 151 deletions(-) diff --git a/radio/src/Makefile b/radio/src/Makefile index a481a13be..7448ac076 100644 --- a/radio/src/Makefile +++ b/radio/src/Makefile @@ -1097,14 +1097,16 @@ all: begin gccversion sizebefore build sizeafter end # Change the build target to build a HEX file or a library. ifeq ($(ARCH), AVR) build: stamp_header tra lbm allsrc.cpp elf remallsrc hex -else +else ifeq ($(PCB), TARANIS) build: stamp_header tra lbm bootloader.lbm allsrc.cpp elf remallsrc bin +else + build: stamp_header tra lbm allsrc.cpp elf remallsrc bin endif # build bootloader .PHONY bootloader.lbm: @echo "Building bootloader..." - $(MAKE) -C bootloader PCB=TARANIS + $(MAKE) -C bootloader PCB=$(PCB) PCBREV=$(PCBREV) $(BIN2LBM) bootloader.lbm bootloader/bootloader_ramBoot.bin tra: translations/en.h translations/cz.h translations/de.h translations/es.h translations/fi.h translations/fr.h translations/it.h translations/pl.h translations/pt.h translations/se.h diff --git a/radio/src/bootloader/Makefile b/radio/src/bootloader/Makefile index 71f882a6e..1e98fe3d9 100644 --- a/radio/src/bootloader/Makefile +++ b/radio/src/bootloader/Makefile @@ -70,6 +70,9 @@ RUN_FROM_FLASH = 0 endif endif +# PCB revision +PCBREV = + EXTRAINCDIRS = # @@ -90,6 +93,14 @@ ifeq ($(RUN_FROM_FLASH), 1) TRGT = arm-none-eabi- CPPDEFS += -DPCBSKY UDEFS = -Dat91sam3s8 + + # If REVX board + ifeq ($(REVX), 1) + CPPDEFS += -DREVX + endif + + CPPDEFS += -DREVB + else ifeq ($(PCB), TARANIS) ARCH = ARM @@ -105,6 +116,15 @@ else EXTRAINCDIRS += ../targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_Device_Library/Class/msc/inc EXTRAINCDIRS += ../targets/taranis EXTRAINCDIRS += ../fonts/std + + ifeq ($(PCBREV), REV3) + CPPDEFS += -DREV3 + else ifeq ($(PCBREV), REV4a) + CPPDEFS += -DREV4a + else + CPPDEFS += -DREV4 + endif + endif endif @@ -240,16 +260,9 @@ COBJS = $(patsubst %,$(OBJDIR)/%,$(notdir $(CXOBJS) )) CPPOBJS = $(patsubst %,$(OBJDIR)/%,$(notdir $(CPPXOBJS) )) DIRS = $(sort $(dir $(AXOBJS) $(CXOBJS) $(CPPXOBJS) ) ) -# If REVX board -ifeq ($(REVX), 1) - CPPDEFS += -DREVX - EXT_MOD=REVB-X -endif CPPDEFS += -DCPUARM -CPPDEFS += -DREVB - # If serial Debug required ifeq ($(DEBUG), 1) CPPDEFS += -DDEBUG diff --git a/radio/src/bootloader/boot.cpp b/radio/src/bootloader/boot.cpp index cf137f00a..312034e8e 100644 --- a/radio/src/bootloader/boot.cpp +++ b/radio/src/bootloader/boot.cpp @@ -49,7 +49,7 @@ /*---------------------------------------------------------------------------- * Headers *----------------------------------------------------------------------------*/ - + #include #include #include @@ -111,7 +111,6 @@ volatile uint8_t Tenms ; uint8_t EE_timer ; TCHAR FlashFilename[60] ; -FATFS g_FATFS ; FIL FlashFile ; DIR Dj ; FILINFO Finfo ; @@ -194,7 +193,7 @@ uint32_t isFirmwareStart( uint32_t *block ) { return 0 ; } - return 1 ; + return 1 ; } #endif @@ -213,7 +212,7 @@ uint32_t isFirmwareStart( uint32_t *block ) { return 0 ; } - return 1 ; + return 1 ; } #endif @@ -253,16 +252,16 @@ uint32_t program( uint32_t *address, uint32_t *buffer ) // size is 256 bytes FlashSectorNum = (uint32_t) address ; FlashSectorNum >>= 8 ; // page size is 256 bytes FlashSectorNum &= 2047 ; // max page number - + /* Send data to the sector here */ for ( i = 0 ; i < 64 ; i += 1 ) { - *address++ = *buffer++ ; + *address++ = *buffer++ ; } /* build the command to send to EEFC */ flash_cmd = (0x5A << 24) | (FlashSectorNum << 8) | 0x03 ; //AT91C_MC_FCMD_EWP ; - + __disable_irq() ; /* Call the IAP function with appropriate command */ i = IAP_Function( 0, flash_cmd ) ; @@ -275,7 +274,7 @@ uint32_t readLockBits() { // Always initialise this here, setting a default doesn't seem to work IAP_Function = (uint32_t (*)(uint32_t, uint32_t)) *(( uint32_t *)0x00800008) ; - + uint32_t flash_cmd = (0x5A << 24) | 0x0A ; //AT91C_MC_FCMD_GLB ; __disable_irq() ; (void) IAP_Function( 0, flash_cmd ) ; @@ -298,7 +297,7 @@ void clearLockBits() /* Call the IAP function with appropriate command */ (void) IAP_Function( 0, flash_cmd ) ; __enable_irq() ; - } + } } #endif @@ -335,7 +334,7 @@ void init10msTimer() ptc->TC_CHANNEL[2].TC_CMR = 0x0009C003 ; // 0000 0000 0000 1001 1100 0000 0000 0011 // MCK/128, set @ RA, Clear @ RC waveform ptc->TC_CHANNEL[2].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) - + NVIC_EnableIRQ(TC2_IRQn) ; TC0->TC_CHANNEL[2].TC_IER = TC_IER0_CPCS ; } @@ -349,7 +348,7 @@ extern "C" void TC2_IRQHandler() (void) dummy ; // Discard value - prevents compiler warning interrupt10ms() ; - + } #endif @@ -360,7 +359,7 @@ void init10msTimer() RCC->APB1ENR |= RCC_APB1ENR_TIM14EN ; // Enable clock TIM14->ARR = 9999 ; // 10mS TIM14->PSC = (PERI1_FREQUENCY * TIMER_MULT_APB1) / 1000000 - 1 ; // 1uS from 12MHz - TIM14->CCER = 0 ; + TIM14->CCER = 0 ; TIM14->CCMR1 = 0 ; TIM14->EGR = 0 ; TIM14->CR1 = 5 ; @@ -380,7 +379,7 @@ void init_hw_timer() RCC->APB1ENR |= RCC_APB1ENR_TIM13EN ; // Enable clock TIM13->ARR = 65535 ; TIM13->PSC = (PERI1_FREQUENCY * TIMER_MULT_APB1) / 10000000 - 1 ; // 0.1uS from 12MHz - TIM13->CCER = 0 ; + TIM13->CCER = 0 ; TIM13->CCMR1 = 0 ; TIM13->EGR = 0 ; TIM13->CR1 = 1 ; @@ -432,13 +431,13 @@ void eraseSector( uint32_t sector ) FLASH->CR &= SECTOR_MASK; FLASH->CR |= FLASH_CR_SER | (sector<<3) ; FLASH->CR |= FLASH_CR_STRT; - + /* Wait for operation to be completed */ waitFlashIdle() ; - + /* if the erase operation is completed, disable the SER Bit */ FLASH->CR &= (~FLASH_CR_SER); - FLASH->CR &= SECTOR_MASK; + FLASH->CR &= SECTOR_MASK; } uint32_t program( uint32_t *address, uint32_t *buffer ) // size is 256 bytes @@ -488,25 +487,25 @@ uint32_t program( uint32_t *address, uint32_t *buffer ) // size is 256 bytes } // Now program the 256 bytes - + for (i = 0 ; i < 64 ; i += 1 ) { /* Device voltage range supposed to be [2.7V to 3.6V], the operation will - be done by word */ - + be done by word */ + // Wait for last operation to be completed waitFlashIdle() ; - + FLASH->CR &= CR_PSIZE_MASK; FLASH->CR |= FLASH_PSIZE_WORD; FLASH->CR |= FLASH_CR_PG; - + *address = *buffer ; - + /* Wait for operation to be completed */ waitFlashIdle() ; FLASH->CR &= (~FLASH_CR_PG); - + /* Check the written value */ if ( *address != *buffer ) { @@ -530,7 +529,7 @@ uint8_t *cpystr( uint8_t *dest, uint8_t *source ) return dest - 1 ; } - + FRESULT readBinDir( DIR *dj, FILINFO *fno ) { FRESULT fr ; @@ -621,7 +620,7 @@ FRESULT openFirmwareFile( uint32_t index ) uint8_t flashFile( uint32_t index ) { FRESULT fr ; - + lcd_clear() ; lcd_putsLeft( 0, "\005Flash File" ) ; if ( Valid == 0 ) @@ -630,7 +629,7 @@ uint8_t flashFile( uint32_t index ) // return 3 if invalid fr = openFirmwareFile( index ) ; fr = f_close( &FlashFile ) ; - + Valid = 1 ; if ( isFirmwareStart( Block_buffer ) == 0 ) { @@ -650,7 +649,7 @@ uint8_t flashFile( uint32_t index ) { return 3 ; } - return 4 ; // + return 4 ; // } lcd_putsnAtt( 0, 2*FH, Filenames[index], DISPLAY_CHAR_WIDTH, 0 ) ; @@ -661,13 +660,13 @@ uint8_t flashFile( uint32_t index ) lcd_putsLeft( 6*FH,"\003[MENU]\013[EXIT]") ; lcd_putsLeft( 5*FH,"\003YES\013NO") ; #endif - + uint8_t event = getEvent() ; if ( event == EVT_KEY_FIRST(BOOT_KEY_MENU) ) { fr = openFirmwareFile( index ) ; - FirmwareSize = FileSize[index] ; + FirmwareSize = FileSize[index] ; if ( fr != FR_OK ) { return 4 ; // File open error @@ -756,7 +755,7 @@ extern uint8_t OptrexDisplay ; #ifdef PCBSKY uint32_t chip_id = CHIPID->CHIPID_CIDR ; - FlashSize = ( (chip_id >> 8 ) & 0x000F ) == 9 ? 256 : 512 ; + FlashSize = ( (chip_id >> 8 ) & 0x000F ) == 9 ? 256 : 512 ; #endif #ifdef PCBTARANIS @@ -774,7 +773,6 @@ extern uint8_t OptrexDisplay ; #ifdef PCBTARANIS // SD card detect pin // configure_pins( SD_PRESENT_GPIO_Pin, PIN_PORTD | PIN_INPUT | PIN_PULLUP ) ; - disk_initialize( 0 ) ; sdInit() ; unlockFlash() ; @@ -787,7 +785,7 @@ extern uint8_t OptrexDisplay ; #ifdef PCBSKY usbMassStorage() ; #endif - + wdt_reset() ; if ( Tenms ) @@ -804,29 +802,18 @@ extern uint8_t OptrexDisplay ; } } - Tenms = 0 ; - lcd_clear() ; -#ifdef PCBSKY - lcd_putsLeft( 0, "Boot Loader" ) ; -#endif -#ifdef PCBTARANIS - lcd_putsLeft( 0, "\006Boot Loader" ) ; -#endif + Tenms = 0; + lcd_clear(); + lcd_putsLeft(0, CENTER "Boot Loader"); + lcd_invert_line(0); - if ( sdMounted() ) { -#ifdef PCBSKY - lcd_putsLeft( 0, "\014Ready" ) ; -#endif -#ifdef PCBTARANIS - lcd_putsLeft( 0, "\022Ready" ) ; -#endif if ( usbPlugged() ) { state = ST_USB ; } - + if ( state == ST_USB ) { #ifdef PCBSKY @@ -849,11 +836,12 @@ extern uint8_t OptrexDisplay ; if ( state == ST_START ) { - fr = f_mount(0, &g_FATFS) ; + sdInit(); + fr = FR_OK; } else { - fr = FR_OK ; + fr = FR_OK ; } if ( fr == FR_OK) @@ -865,7 +853,7 @@ extern uint8_t OptrexDisplay ; } if ( state == ST_DIR_CHECK ) { - fr = f_chdir( (TCHAR *)"\\firmware" ) ; + fr = f_chdir("/firmware") ; if ( fr == FR_OK ) { state = ST_OPEN_DIR ; @@ -875,15 +863,15 @@ extern uint8_t OptrexDisplay ; if ( state == ST_DIR_CHECK ) { #ifdef PCBSKY - lcd_putsLeft( 16, "\005No Firmware" ) ; + lcd_putsLeft( 2*FH, "\005No Firmware" ) ; #endif #ifdef PCBTARANIS - lcd_putsLeft( 16, "\013No Firmware" ) ; + lcd_putsLeft( 2*FH, "\013No Firmware" ) ; #endif } if ( state == ST_OPEN_DIR ) { - fr = f_opendir( &Dj, (TCHAR *) "." ) ; + fr = f_opendir(&Dj, ".") ; if ( fr == FR_OK ) { state = ST_FILE_LIST ; @@ -898,7 +886,7 @@ extern uint8_t OptrexDisplay ; uint32_t limit = 6 ; if ( nameCount < limit ) { - limit = nameCount ; + limit = nameCount ; } maxhsize = 0 ; for ( i = 0 ; i < limit ; i += 1 ) @@ -907,7 +895,7 @@ extern uint8_t OptrexDisplay ; x = strlen( Filenames[i] ) ; if ( x > maxhsize ) { - maxhsize = x ; + maxhsize = x ; } if ( x > DISPLAY_CHAR_WIDTH ) { @@ -963,14 +951,14 @@ extern uint8_t OptrexDisplay ; { if ( hpos + DISPLAY_CHAR_WIDTH < maxhsize ) { - hpos += 1 ; + hpos += 1 ; } } if ( ( event == EVT_KEY_REPT(BOOT_KEY_LEFT)) || ( event == EVT_KEY_FIRST(BOOT_KEY_LEFT) ) ) { if ( hpos ) { - hpos -= 1 ; + hpos -= 1 ; } } if ( event == EVT_KEY_LONG(BOOT_KEY_MENU) ) @@ -984,7 +972,7 @@ extern uint8_t OptrexDisplay ; state = ST_REBOOT ; } } - lcd_invert_line(2*FH+FH*vpos); + lcd_invert_line(2+vpos); // lcd_char_inverse( 0, 2*FH+FH*vpos, DISPLAY_CHAR_WIDTH*FW, 0 ) ; } if ( state == ST_FLASH_CHECK ) @@ -993,7 +981,7 @@ extern uint8_t OptrexDisplay ; FirmwareSize = FileSize[vpos] - 32768 ; if ( i == 1 ) { - state = ST_FILE_LIST ; // Canceled + state = ST_FILE_LIST ; // Canceled } if ( i == 2 ) { @@ -1009,7 +997,7 @@ extern uint8_t OptrexDisplay ; if ( i == 3 ) { // Invalid file - state = ST_FILE_LIST ; // Canceled + state = ST_FILE_LIST ; // Canceled } } if ( state == ST_FLASHING ) @@ -1024,7 +1012,7 @@ extern uint8_t OptrexDisplay ; firmwareAddress += 256 ; if ( BlockCount > 256 ) { - BlockCount -= 256 ; + BlockCount -= 256 ; } else { @@ -1061,37 +1049,29 @@ extern uint8_t OptrexDisplay ; } } -#ifdef PCBTARANIS - if ( --TenCount == 0 ) - { - TenCount = 2 ; -#endif - lcdRefresh() ; -#ifdef PCBTARANIS + if ( --TenCount == 0 ) { + TenCount = 2 ; + lcdRefresh() ; } -#endif + if ( PowerUpDelay < 20 ) // 200 mS { PowerUpDelay += 1 ; } else { -#ifdef PCBSKY - sd_poll_10mS() ; -#endif -#ifdef PCBTARANIS sdPoll10ms() ; -#endif + } } if ((state < ST_FLASH_CHECK) || (state == ST_FLASH_DONE)) { if (pwrCheck() == e_power_off ) { - pwrOff() ; - for(;;) - { + pwrOff() ; + for(;;) + { // Wait for power to go off - } + } } } if ( state < ST_FILE_LIST ) @@ -1105,12 +1085,11 @@ extern uint8_t OptrexDisplay ; { if ( (~readKeys() & 0x7E) == 0 ) { - NVIC_SystemReset() ; + NVIC_SystemReset() ; } } } -// stop_timer0() ; return 0; } diff --git a/radio/src/gui/menu_general.cpp b/radio/src/gui/menu_general.cpp index 5f2ade988..f83806fec 100644 --- a/radio/src/gui/menu_general.cpp +++ b/radio/src/gui/menu_general.cpp @@ -432,12 +432,8 @@ void menuGeneralSetup(uint8_t event) case ITEM_SETUP_CONTRAST: lcd_putsLeft(y, STR_CONTRAST); lcd_outdezAtt(RADIO_SETUP_2ND_COLUMN, y, g_eeGeneral.contrast, attr|LEFT); - if(attr) { -#if defined(PCBTARANIS) - CHECK_INCDEC_GENVAR(event, g_eeGeneral.contrast, 0, 45); -#else - CHECK_INCDEC_GENVAR(event, g_eeGeneral.contrast, 10, 45); -#endif + if (attr) { + CHECK_INCDEC_GENVAR(event, g_eeGeneral.contrast, CONTRAST_MIN, CONTRAST_MAX); lcdSetContrast(); } break; @@ -601,24 +597,16 @@ void menuGeneralSetup(uint8_t event) #endif #if defined(MAVLINK) - case ITEM_MAVLINK_BAUD: - g_eeGeneral.mavbaud = selectMenuItem(RADIO_SETUP_2ND_COLUMN, //Y - y, // Y - STR_MAVLINK_BAUD_LABEL, // pm_char *label - STR_MAVLINK_BAUDS, // pm_char *values -// PSTR("4800""9600""14400""19200""38400""57600""76800""115200"), - g_eeGeneral.mavbaud, // value - 0, // min - 7, // max - attr, // attr - event); // event - break; + case ITEM_MAVLINK_BAUD: + g_eeGeneral.mavbaud = selectMenuItem(RADIO_SETUP_2ND_COLUMN, y, STR_MAVLINK_BAUD_LABEL, STR_MAVLINK_BAUDS, PSTR("4800""9600""14400""19200""38400""57600""76800""115200"), g_eeGeneral.mavbaud, 0, 7, attr, event); + break; #endif case ITEM_SETUP_RX_CHANNEL_ORD: lcd_putsLeft(y, STR_RXCHANNELORD); // RAET->AETR - for (uint8_t i=1; i<=4; i++) + for (uint8_t i=1; i<=4; i++) { putsChnLetter(RADIO_SETUP_2ND_COLUMN - FW + i*FW, y, channel_order(i), attr); + } if (attr) CHECK_INCDEC_GENVAR(event, g_eeGeneral.templateSetup, 0, 23); break; @@ -629,7 +617,9 @@ void menuGeneralSetup(uint8_t event) case ITEM_SETUP_STICK_MODE: lcd_putcAtt(2*FW, y, '1'+g_eeGeneral.stickMode, attr); - for (uint8_t i=0; i<4; i++) putsMixerSource((6+4*i)*FW, y, MIXSRC_Rud + pgm_read_byte(modn12x3 + 4*g_eeGeneral.stickMode + i), 0); + for (uint8_t i=0; i<4; i++) { + putsMixerSource((6+4*i)*FW, y, MIXSRC_Rud + pgm_read_byte(modn12x3 + 4*g_eeGeneral.stickMode + i), 0); + } if (attr && s_editMode>0) { CHECK_INCDEC_GENVAR(event, g_eeGeneral.stickMode, 0, 3); } diff --git a/radio/src/lcd.h b/radio/src/lcd.h index 29dcf4b16..18e405a76 100644 --- a/radio/src/lcd.h +++ b/radio/src/lcd.h @@ -43,12 +43,16 @@ #define xcoord_t uint16_t #define CENTER "\015" #define CENTER_OFS (7*FW-FW/2) + #define CONTRAST_MIN 0 + #define CONTRAST_MAX 45 #else #define LCD_W 128 #define LCD_H 64 #define xcoord_t uint8_t #define CENTER #define CENTER_OFS 0 + #define CONTRAST_MIN 10 + #define CONTRAST_MAX 45 #endif #if defined(CPUARM) diff --git a/radio/src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c b/radio/src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c index 552410e8a..367091dd2 100644 --- a/radio/src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c +++ b/radio/src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c @@ -232,7 +232,7 @@ void SystemInit(void) #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else - #if defined(BOOTLOADER) + #if defined(BOOTLOADER) || defined(BOOT) extern uint32_t g_pfnVectors ; SCB->VTOR = (uint32_t) &g_pfnVectors ; /* Vector Table Relocation in Internal FLASH */ #else diff --git a/radio/src/targets/taranis/diskio.cpp b/radio/src/targets/taranis/diskio.cpp index 8f80c8841..91ebf76b9 100644 --- a/radio/src/targets/taranis/diskio.cpp +++ b/radio/src/targets/taranis/diskio.cpp @@ -670,14 +670,23 @@ int8_t SD_ReadSectors(uint8_t *buff, uint32_t sector, uint32_t count) { if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert to byte address if needed */ - if (send_cmd(CMD18, sector) == 0) { /* READ_MULTIPLE_BLOCK */ - do { - if (!rcvr_datablock(buff, 512)) { - break; + if (count == 1) { /* Single block read */ + if (send_cmd(CMD17, sector) == 0) { /* READ_SINGLE_BLOCK */ + if (rcvr_datablock(buff, 512)) { + count = 0; } - buff += 512; - } while (--count); - send_cmd(CMD12, 0); /* STOP_TRANSMISSION */ + } + } + else { /* Multiple block read */ + if (send_cmd(CMD18, sector) == 0) { /* READ_MULTIPLE_BLOCK */ + do { + if (!rcvr_datablock(buff, 512)) { + break; + } + buff += 512; + } while (--count); + send_cmd(CMD12, 0); /* STOP_TRANSMISSION */ + } } release_spi(); @@ -695,29 +704,9 @@ DRESULT disk_read ( if (drv || !count) return RES_PARERR; if (Stat & STA_NOINIT) return RES_NOTRDY; - if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert to byte address if needed */ + SD_ReadSectors(buff, sector, count); - if (count == 1) { /* Single block read */ - if (send_cmd(CMD17, sector) == 0) { /* READ_SINGLE_BLOCK */ - if (rcvr_datablock(buff, 512)) { - count = 0; - } - } - } - else { /* Multiple block read */ - if (send_cmd(CMD18, sector) == 0) { /* READ_MULTIPLE_BLOCK */ - do { - if (!rcvr_datablock(buff, 512)) { - break; - } - buff += 512; - } while (--count); - send_cmd(CMD12, 0); /* STOP_TRANSMISSION */ - } - } - release_spi(); - - return count ? RES_ERROR : RES_OK; + return RES_OK; } diff --git a/radio/src/targets/taranis/lcd_driver.cpp b/radio/src/targets/taranis/lcd_driver.cpp index 5b8c2a6bd..e9e3c1129 100644 --- a/radio/src/targets/taranis/lcd_driver.cpp +++ b/radio/src/targets/taranis/lcd_driver.cpp @@ -13,7 +13,7 @@ #define WriteData(x) AspiData(x) #define WriteCommand(x) AspiCmd(x) -#define CONTRAST_OFS 5 +#define CONTRAST_OFS 5 static void LCD_Init() { @@ -22,9 +22,9 @@ static void LCD_Init() AspiCmd(0xEA); //set bias=1/10 :Command table NO.27 AspiCmd(0x81); //Set Vop #if defined(BOOT) - AspiCmd(CONTRAST_OFS); + AspiCmd(CONTRAST_OFS+25); #else - AspiCmd(g_eeGeneral.contrast+CONTRAST_OFS); //0--255 + AspiCmd(CONTRAST_OFS+g_eeGeneral.contrast); #endif AspiCmd(0xA6); //inverse display off AspiCmd(0xD1); //SET RGB:Command table NO.21 .SET RGB or BGR. D1=RGB diff --git a/radio/src/targets/taranis/usbd_storage_msd.cpp b/radio/src/targets/taranis/usbd_storage_msd.cpp index 1e838c078..79ddf8619 100644 --- a/radio/src/targets/taranis/usbd_storage_msd.cpp +++ b/radio/src/targets/taranis/usbd_storage_msd.cpp @@ -203,14 +203,11 @@ int8_t STORAGE_Read (uint8_t lun, uint16_t blk_len) { if (lun == 1) { - if (fat12Read(buf, blk_addr, blk_len) != 0) { + if (fat12Read(buf, blk_addr, blk_len) != 0) return -1; - } } else { - if (SD_ReadSectors(buf, - blk_addr, - blk_len) != 0) { + if (SD_ReadSectors(buf, blk_addr, blk_len) != 0) { return -1; } } @@ -238,9 +235,7 @@ int8_t STORAGE_Write (uint8_t lun, return -1; } else { - if (SD_WriteSectors(buf, - blk_addr, - blk_len) != 0) + if (SD_WriteSectors(buf, blk_addr, blk_len) != 0) return -1; } From 278218e7a032471f334dada339adff4bf861479b Mon Sep 17 00:00:00 2001 From: bsongis Date: Wed, 12 Mar 2014 16:18:30 +0100 Subject: [PATCH 061/285] Reindentation of boot.cpp --- radio/src/bootloader/boot.cpp | 1419 +++++++++++++++------------------ 1 file changed, 653 insertions(+), 766 deletions(-) diff --git a/radio/src/bootloader/boot.cpp b/radio/src/bootloader/boot.cpp index 312034e8e..583130c7d 100644 --- a/radio/src/bootloader/boot.cpp +++ b/radio/src/bootloader/boot.cpp @@ -1,34 +1,34 @@ /**************************************************************************** -* Copyright (c) 2014 by Michael Blandford. All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* 1. Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* 3. Neither the name of the author nor the names of its contributors may -* be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL -* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -* SUCH DAMAGE. -* -**************************************************************************** -* Other Authors: + * Copyright (c) 2014 by Michael Blandford. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the author nor the names of its contributors may + * be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF + * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + **************************************************************************** + * Other Authors: * - Andre Bernet * - Bertrand Songis * - Bryan J. Rentoul (Gruvin) @@ -42,9 +42,8 @@ * - Rob Thomson * - Romolo Manfredini * - Thomas Husterer -* -****************************************************************************/ - + * + ****************************************************************************/ /*---------------------------------------------------------------------------- * Headers @@ -55,88 +54,75 @@ #include #ifdef PCBTARANIS -#include "stm32f2xx.h" #include "stm32f2xx_flash.h" -#include "../targets/taranis/i2c.h" -#include "hal.h" - -extern "C" { -#include "usb_dcd_int.h" -#include "usb_bsp.h" -#include "../targets/taranis/usbd_desc.h" -#include "usbd_msc_core.h" -#include "usbd_usr.h" -} - #endif #include "board_taranis.h" #include "../pwr.h" #include "../lcd.h" #include "../keys.h" - #include "../FatFs/ff.h" #include "../FatFs/diskio.h" -#ifdef PCBTARANIS -#define BOOT_KEY_UP KEY_PLUS -#define BOOT_KEY_DOWN KEY_MINUS -#define BOOT_KEY_LEFT KEY_MENU -#define BOOT_KEY_RIGHT KEY_PAGE -#define BOOT_KEY_MENU KEY_ENTER -#define BOOT_KEY_EXIT KEY_EXIT -#define DISPLAY_CHAR_WIDTH 35 +#if defined(PCBTARANIS) + #define BOOT_KEY_UP KEY_PLUS + #define BOOT_KEY_DOWN KEY_MINUS + #define BOOT_KEY_LEFT KEY_MENU + #define BOOT_KEY_RIGHT KEY_PAGE + #define BOOT_KEY_MENU KEY_ENTER + #define BOOT_KEY_EXIT KEY_EXIT + #define DISPLAY_CHAR_WIDTH 35 #endif // states -#define ST_START 0 -#define ST_DIR_CHECK 1 -#define ST_OPEN_DIR 2 -#define ST_FILE_LIST 3 -#define ST_FLASH_CHECK 4 -#define ST_FLASHING 5 -#define ST_FLASH_DONE 6 -#define ST_USB 10 -#define ST_REBOOT 11 - +enum BootLoaderStates { + ST_START, + ST_DIR_CHECK, + ST_OPEN_DIR, + ST_FILE_LIST, + ST_FLASH_CHECK, + ST_FLASHING, + ST_FLASH_DONE, + ST_USB = 10, + ST_REBOOT = 11, +}; /*---------------------------------------------------------------------------- * Local variables *----------------------------------------------------------------------------*/ -uint32_t FirmwareSize ; +uint32_t FirmwareSize; -uint32_t Master_frequency ; -volatile uint8_t Tenms ; -uint8_t EE_timer ; +uint32_t Master_frequency; +volatile uint8_t Tenms; +uint8_t EE_timer; -TCHAR FlashFilename[60] ; -FIL FlashFile ; -DIR Dj ; -FILINFO Finfo ; +TCHAR FlashFilename[60]; +FIL FlashFile; +DIR Dj; +FILINFO Finfo; -TCHAR Filenames[20][50] ; -uint32_t FileSize[20] ; -uint32_t FnStartIndex ; -uint32_t Valid ; +TCHAR Filenames[20][50]; +uint32_t FileSize[20]; +uint32_t FnStartIndex; +uint32_t Valid; -uint32_t FlashSize ; +uint32_t FlashSize; +uint32_t FlashBlocked = 1; +uint32_t LockBits; -uint32_t FlashBlocked = 1 ; -uint32_t LockBits ; - -uint32_t Block_buffer[1024] ; -UINT BlockCount ; +uint32_t Block_buffer[1024]; +UINT BlockCount; #ifdef PCBSKY -extern int32_t EblockAddress ; + extern int32_t EblockAddress; #endif -extern uint32_t EepromBlocked ; -extern void init_spi( void ) ; -extern void writeBlock( void ) ; +extern uint32_t EepromBlocked; +extern void init_spi(void); +extern void writeBlock(void); /*---------------------------------------------------------------------------- * Global functions @@ -148,169 +134,162 @@ extern void writeBlock( void ) ; // This was 6 MHz, we may need to slow it to TIMER_CLOCK2 (MCK/8=4.5 MHz) void start_timer0() { - register Tc *ptc ; + register Tc *ptc; - PMC->PMC_PCER0 |= 0x00800000L ; // Enable peripheral clock to TC0 + PMC->PMC_PCER0 |= 0x00800000L; // Enable peripheral clock to TC0 - ptc = TC0 ; // Tc block 0 (TC0-2) - ptc->TC_BCR = 0 ; // No sync - ptc->TC_BMR = 2 ; - ptc->TC_CHANNEL[0].TC_CMR = 0x00008001 ; // Waveform mode MCK/8 for 36MHz osc.(Upset be write below) - ptc->TC_CHANNEL[0].TC_RC = 0xFFF0 ; - ptc->TC_CHANNEL[0].TC_RA = 0 ; - ptc->TC_CHANNEL[0].TC_CMR = 0x00008040 ; // 0000 0000 0000 0000 1000 0000 0100 0000, stop at regC, 18MHz - ptc->TC_CHANNEL[0].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) + ptc = TC0;// Tc block 0 (TC0-2) + ptc->TC_BCR = 0;// No sync + ptc->TC_BMR = 2; + ptc->TC_CHANNEL[0].TC_CMR = 0x00008001;// Waveform mode MCK/8 for 36MHz osc.(Upset be write below) + ptc->TC_CHANNEL[0].TC_RC = 0xFFF0; + ptc->TC_CHANNEL[0].TC_RA = 0; + ptc->TC_CHANNEL[0].TC_CMR = 0x00008040;// 0000 0000 0000 0000 1000 0000 0100 0000, stop at regC, 18MHz + ptc->TC_CHANNEL[0].TC_CCR = 5;// Enable clock and trigger it (may only need trigger) } void stop_timer0( void ) { - TC0->TC_CHANNEL[0].TC_CCR = TC_CCR0_CLKDIS ; // Disable clock + TC0->TC_CHANNEL[0].TC_CCR = TC_CCR0_CLKDIS; // Disable clock } void delay2ms() { - TC0->TC_CHANNEL[0].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) - while ( TC0->TC_CHANNEL[0].TC_CV < 36000 ) // 2mS, Value depends on MCK/2 (used 18MHz) - { - // Wait - } + TC0->TC_CHANNEL[0].TC_CCR = 5;// Enable clock and trigger it (may only need trigger) + while ( TC0->TC_CHANNEL[0].TC_CV < 36000 )// 2mS, Value depends on MCK/2 (used 18MHz) + { + // Wait + } } #endif #ifdef PCBTARANIS -uint32_t isFirmwareStart( uint32_t *block ) +uint32_t isFirmwareStart(uint32_t *block) { - if ( ( block[0] & 0xFFFC0000 ) != 0x20000000 ) - { - return 0 ; - } - if ( ( block[1] & 0xFFF00000 ) != 0x08000000 ) - { - return 0 ; - } - if ( ( block[2] & 0xFFF00000 ) != 0x08000000 ) - { - return 0 ; - } - return 1 ; + if ((block[0] & 0xFFFC0000) != 0x20000000) { + return 0; + } + if ((block[1] & 0xFFF00000) != 0x08000000) { + return 0; + } + if ((block[2] & 0xFFF00000) != 0x08000000) { + return 0; + } + return 1; } #endif #ifdef PCBSKY uint32_t isFirmwareStart( uint32_t *block ) { - if ( ( block[0] & 0xFFFE3000 ) != 0x20000000 ) - { - return 0 ; - } - if ( ( block[1] & 0xFFF80000 ) != 0x00400000 ) - { - return 0 ; - } - if ( ( block[2] & 0xFFF80000 ) != 0x00400000 ) - { - return 0 ; - } - return 1 ; + if ( ( block[0] & 0xFFFE3000 ) != 0x20000000 ) + { + return 0; + } + if ( ( block[1] & 0xFFF80000 ) != 0x00400000 ) + { + return 0; + } + if ( ( block[2] & 0xFFF80000 ) != 0x00400000 ) + { + return 0; + } + return 1; } #endif - #ifdef PCBSKY -uint32_t (*IAP_Function)(uint32_t, uint32_t) ; - +uint32_t (*IAP_Function)(uint32_t, uint32_t); uint32_t program( uint32_t *address, uint32_t *buffer ) // size is 256 bytes { - uint32_t FlashSectorNum ; - uint32_t flash_cmd = 0 ; - uint32_t i ; + uint32_t FlashSectorNum; + uint32_t flash_cmd = 0; + uint32_t i; // uint32_t flash_status = 0; - // uint32_t EFCIndex = 0; // 0:EEFC0, 1: EEFC1 - /* Initialize the function pointer (retrieve function address from NMI vector) */ + // uint32_t EFCIndex = 0; // 0:EEFC0, 1: EEFC1 + /* Initialize the function pointer (retrieve function address from NMI vector) */ - if ( (uint32_t) address == 0x00408000 ) - { - if ( isFirmwareStart( buffer) ) - { - FlashBlocked = 0 ; - } - else - { - FlashBlocked = 1 ; - } - } + if ( (uint32_t) address == 0x00408000 ) + { + if ( isFirmwareStart( buffer) ) + { + FlashBlocked = 0; + } + else + { + FlashBlocked = 1; + } + } - if ( FlashBlocked ) - { - return 1 ; - } - // Always initialise this here, setting a default doesn't seem to work - IAP_Function = (uint32_t (*)(uint32_t, uint32_t)) *(( uint32_t *)0x00800008) ; - FlashSectorNum = (uint32_t) address ; - FlashSectorNum >>= 8 ; // page size is 256 bytes - FlashSectorNum &= 2047 ; // max page number + if ( FlashBlocked ) + { + return 1; + } + // Always initialise this here, setting a default doesn't seem to work + IAP_Function = (uint32_t (*)(uint32_t, uint32_t)) *(( uint32_t *)0x00800008); + FlashSectorNum = (uint32_t) address; + FlashSectorNum >>= 8;// page size is 256 bytes + FlashSectorNum &= 2047;// max page number - /* Send data to the sector here */ - for ( i = 0 ; i < 64 ; i += 1 ) - { - *address++ = *buffer++ ; - } + /* Send data to the sector here */ + for ( i = 0; i < 64; i += 1 ) + { + *address++ = *buffer++; + } - /* build the command to send to EEFC */ - flash_cmd = (0x5A << 24) | (FlashSectorNum << 8) | 0x03 ; //AT91C_MC_FCMD_EWP ; + /* build the command to send to EEFC */ + flash_cmd = (0x5A << 24) | (FlashSectorNum << 8) | 0x03; //AT91C_MC_FCMD_EWP ; - __disable_irq() ; - /* Call the IAP function with appropriate command */ - i = IAP_Function( 0, flash_cmd ) ; - __enable_irq() ; - return i ; + __disable_irq(); + /* Call the IAP function with appropriate command */ + i = IAP_Function( 0, flash_cmd ); + __enable_irq(); + return i; } - uint32_t readLockBits() { - // Always initialise this here, setting a default doesn't seem to work - IAP_Function = (uint32_t (*)(uint32_t, uint32_t)) *(( uint32_t *)0x00800008) ; + // Always initialise this here, setting a default doesn't seem to work + IAP_Function = (uint32_t (*)(uint32_t, uint32_t)) *(( uint32_t *)0x00800008); - uint32_t flash_cmd = (0x5A << 24) | 0x0A ; //AT91C_MC_FCMD_GLB ; - __disable_irq() ; - (void) IAP_Function( 0, flash_cmd ) ; - __enable_irq() ; - return EFC->EEFC_FRR ; + uint32_t flash_cmd = (0x5A << 24) | 0x0A;//AT91C_MC_FCMD_GLB ; + __disable_irq(); + (void) IAP_Function( 0, flash_cmd ); + __enable_irq(); + return EFC->EEFC_FRR; } - void clearLockBits() { - uint32_t i ; - uint32_t flash_cmd = 0 ; + uint32_t i; + uint32_t flash_cmd = 0; - // Always initialise this here, setting a default doesn't seem to work - IAP_Function = (uint32_t (*)(uint32_t, uint32_t)) *(( uint32_t *)0x00800008) ; - for ( i = 0 ; i < 16 ; i += 1 ) - { - flash_cmd = (0x5A << 24) | ((128*i) << 8) | 0x09 ; //AT91C_MC_FCMD_CLB ; - __disable_irq() ; - /* Call the IAP function with appropriate command */ - (void) IAP_Function( 0, flash_cmd ) ; - __enable_irq() ; - } + // Always initialise this here, setting a default doesn't seem to work + IAP_Function = (uint32_t (*)(uint32_t, uint32_t)) *(( uint32_t *)0x00800008); + for ( i = 0; i < 16; i += 1 ) + { + flash_cmd = (0x5A << 24) | ((128*i) << 8) | 0x09; //AT91C_MC_FCMD_CLB ; + __disable_irq(); + /* Call the IAP function with appropriate command */ + (void) IAP_Function( 0, flash_cmd ); + __enable_irq(); + } } #endif void interrupt10ms(void) { - Tenms |= 1 ; // 10 mS has passed + Tenms |= 1; // 10 mS has passed uint8_t enuk = KEY_MENU; uint8_t in = ~readKeys(); - for (int i=1; i<7; i++) { - uint8_t value = in & (1<PMC_PCER0 |= 0x02000000L ; // Enable peripheral clock to TC2 + PMC->PMC_PCER0 |= 0x02000000L; // Enable peripheral clock to TC2 - timer = Master_frequency / 12800 ; // MCK/128 and 100 Hz + timer = Master_frequency / 12800;// MCK/128 and 100 Hz - ptc = TC0 ; // Tc block 0 (TC0-2) - ptc->TC_BCR = 0 ; // No sync - ptc->TC_BMR = 0 ; - ptc->TC_CHANNEL[2].TC_CMR = 0x00008000 ; // Waveform mode - ptc->TC_CHANNEL[2].TC_RC = timer ; // 10 Hz - ptc->TC_CHANNEL[2].TC_RA = timer >> 1 ; - ptc->TC_CHANNEL[2].TC_CMR = 0x0009C003 ; // 0000 0000 0000 1001 1100 0000 0000 0011 - // MCK/128, set @ RA, Clear @ RC waveform - ptc->TC_CHANNEL[2].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) + ptc = TC0;// Tc block 0 (TC0-2) + ptc->TC_BCR = 0;// No sync + ptc->TC_BMR = 0; + ptc->TC_CHANNEL[2].TC_CMR = 0x00008000;// Waveform mode + ptc->TC_CHANNEL[2].TC_RC = timer;// 10 Hz + ptc->TC_CHANNEL[2].TC_RA = timer >> 1; + ptc->TC_CHANNEL[2].TC_CMR = 0x0009C003;// 0000 0000 0000 1001 1100 0000 0000 0011 + // MCK/128, set @ RA, Clear @ RC waveform + ptc->TC_CHANNEL[2].TC_CCR = 5;// Enable clock and trigger it (may only need trigger) - NVIC_EnableIRQ(TC2_IRQn) ; - TC0->TC_CHANNEL[2].TC_IER = TC_IER0_CPCS ; + NVIC_EnableIRQ(TC2_IRQn); + TC0->TC_CHANNEL[2].TC_IER = TC_IER0_CPCS; } extern "C" void TC2_IRQHandler() @@ -345,9 +324,9 @@ extern "C" void TC2_IRQHandler() /* Clear status bit to acknowledge interrupt */ dummy = TC0->TC_CHANNEL[2].TC_SR; - (void) dummy ; // Discard value - prevents compiler warning + (void) dummy; // Discard value - prevents compiler warning - interrupt10ms() ; + interrupt10ms(); } #endif @@ -355,46 +334,44 @@ extern "C" void TC2_IRQHandler() #ifdef PCBTARANIS void init10msTimer() { - // Timer14 - RCC->APB1ENR |= RCC_APB1ENR_TIM14EN ; // Enable clock - TIM14->ARR = 9999 ; // 10mS - TIM14->PSC = (PERI1_FREQUENCY * TIMER_MULT_APB1) / 1000000 - 1 ; // 1uS from 12MHz - TIM14->CCER = 0 ; - TIM14->CCMR1 = 0 ; - TIM14->EGR = 0 ; - TIM14->CR1 = 5 ; - TIM14->DIER |= 1 ; - NVIC_EnableIRQ(TIM8_TRG_COM_TIM14_IRQn) ; + // Timer14 + RCC->APB1ENR |= RCC_APB1ENR_TIM14EN; // Enable clock + TIM14->ARR = 9999; // 10mS + TIM14->PSC = (PERI1_FREQUENCY * TIMER_MULT_APB1) / 1000000 - 1; // 1uS from 12MHz + TIM14->CCER = 0; + TIM14->CCMR1 = 0; + TIM14->EGR = 0; + TIM14->CR1 = 5; + TIM14->DIER |= 1; + NVIC_EnableIRQ(TIM8_TRG_COM_TIM14_IRQn); } extern "C" void TIM8_TRG_COM_TIM14_IRQHandler() { - TIM14->SR &= ~TIM_SR_UIF ; - interrupt10ms() ; + TIM14->SR &= ~TIM_SR_UIF; + interrupt10ms(); } void init_hw_timer() { - // Timer13 - RCC->APB1ENR |= RCC_APB1ENR_TIM13EN ; // Enable clock - TIM13->ARR = 65535 ; - TIM13->PSC = (PERI1_FREQUENCY * TIMER_MULT_APB1) / 10000000 - 1 ; // 0.1uS from 12MHz - TIM13->CCER = 0 ; - TIM13->CCMR1 = 0 ; - TIM13->EGR = 0 ; - TIM13->CR1 = 1 ; + // Timer13 + RCC->APB1ENR |= RCC_APB1ENR_TIM13EN; // Enable clock + TIM13->ARR = 65535; + TIM13->PSC = (PERI1_FREQUENCY * TIMER_MULT_APB1) / 10000000 - 1;// 0.1uS from 12MHz + TIM13->CCER = 0; + TIM13->CCMR1 = 0; + TIM13->EGR = 0; + TIM13->CR1 = 1; } - // delay in units of 0.1 uS up to 6.5535 mS -void hw_delay( uint16_t time ) +void hw_delay(uint16_t time) { - TIM13->CNT = 0 ; - TIM13->EGR = 1 ; // Re-start counter - while ( TIM13->CNT < time ) - { - // wait - } + TIM13->CNT = 0; + TIM13->EGR = 1; // Re-start counter + while ( TIM13->CNT < time) { + // wait + } } //After reset, write is not allowed in the Flash control register (FLASH_CR) to protect the @@ -408,690 +385,600 @@ void hw_delay( uint16_t time ) //FLASH_CR register. void unlockFlash() { - FLASH->KEYR = 0x45670123 ; - FLASH->KEYR = 0xCDEF89AB ; + FLASH->KEYR = 0x45670123; + FLASH->KEYR = 0xCDEF89AB; } void waitFlashIdle() { - while (FLASH->SR & FLASH_FLAG_BSY) - { - wdt_reset() ; - } + while (FLASH->SR & FLASH_FLAG_BSY) { + wdt_reset(); + } } #define SECTOR_MASK ((uint32_t)0xFFFFFF07) -void eraseSector( uint32_t sector ) +void eraseSector(uint32_t sector) { - waitFlashIdle() ; + waitFlashIdle(); FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_WORD ; + FLASH->CR |= FLASH_PSIZE_WORD; FLASH->CR &= SECTOR_MASK; - FLASH->CR |= FLASH_CR_SER | (sector<<3) ; + FLASH->CR |= FLASH_CR_SER | (sector << 3); FLASH->CR |= FLASH_CR_STRT; /* Wait for operation to be completed */ - waitFlashIdle() ; + waitFlashIdle(); /* if the erase operation is completed, disable the SER Bit */ FLASH->CR &= (~FLASH_CR_SER); FLASH->CR &= SECTOR_MASK; } -uint32_t program( uint32_t *address, uint32_t *buffer ) // size is 256 bytes +uint32_t program(uint32_t *address, uint32_t *buffer) // size is 256 bytes { - uint32_t i ; + uint32_t i; - if ( (uint32_t) address == 0x08008000 ) - { - if ( isFirmwareStart( buffer) ) - { - FlashBlocked = 0 ; - } - else - { - FlashBlocked = 1 ; - } - } + if ((uint32_t) address == 0x08008000) { + if (isFirmwareStart(buffer)) { + FlashBlocked = 0; + } + else { + FlashBlocked = 1; + } + } - if ( FlashBlocked ) - { - return 1 ; - } + if (FlashBlocked) { + return 1; + } - if ( (uint32_t) address == 0x08008000 ) - { - eraseSector( 2 ) ; - } - if ( (uint32_t) address == 0x0800C000 ) - { - eraseSector( 3 ) ; - } - if ( (uint32_t) address == 0x08010000 ) - { - eraseSector( 4 ) ; - } - if ( (uint32_t) address == 0x08020000 ) - { - eraseSector( 5 ) ; - } - if ( (uint32_t) address == 0x08040000 ) - { - eraseSector( 6 ) ; - } - if ( (uint32_t) address == 0x08060000 ) - { - eraseSector( 7 ) ; - } + if ((uint32_t) address == 0x08008000) { + eraseSector(2); + } + if ((uint32_t) address == 0x0800C000) { + eraseSector(3); + } + if ((uint32_t) address == 0x08010000) { + eraseSector(4); + } + if ((uint32_t) address == 0x08020000) { + eraseSector(5); + } + if ((uint32_t) address == 0x08040000) { + eraseSector(6); + } + if ((uint32_t) address == 0x08060000) { + eraseSector(7); + } - // Now program the 256 bytes + // Now program the 256 bytes - for (i = 0 ; i < 64 ; i += 1 ) - { + for (i = 0; i < 64; i += 1) { /* Device voltage range supposed to be [2.7V to 3.6V], the operation will - be done by word */ + be done by word */ - // Wait for last operation to be completed - waitFlashIdle() ; + // Wait for last operation to be completed + waitFlashIdle(); FLASH->CR &= CR_PSIZE_MASK; FLASH->CR |= FLASH_PSIZE_WORD; FLASH->CR |= FLASH_CR_PG; - *address = *buffer ; + *address = *buffer; /* Wait for operation to be completed */ - waitFlashIdle() ; + waitFlashIdle(); FLASH->CR &= (~FLASH_CR_PG); - /* Check the written value */ - if ( *address != *buffer ) - { + /* Check the written value */ + if (*address != *buffer) { /* Flash content doesn't match SRAM content */ - return 2 ; + return 2; } /* Increment FLASH destination address */ - address += 1 ; - buffer += 1 ; + address += 1; + buffer += 1; } - return 0 ; + return 0; } #endif - -uint8_t *cpystr( uint8_t *dest, uint8_t *source ) +uint8_t *cpystr(uint8_t *dest, uint8_t *source) { - while ( (*dest++ = *source++) ) + while ((*dest++ = *source++)) ; - return dest - 1 ; + return dest - 1; } - -FRESULT readBinDir( DIR *dj, FILINFO *fno ) +FRESULT readBinDir(DIR *dj, FILINFO *fno) { - FRESULT fr ; - uint32_t loop ; - do - { - loop = 0 ; - fr = f_readdir ( dj, fno ) ; // First entry + FRESULT fr; + uint32_t loop; + do { + loop = 0; + fr = f_readdir(dj, fno); // First entry - if ( fr != FR_OK || fno->fname[0] == 0 ) - { - break ; - } - if ( *fno->lfname == 0 ) - { - cpystr( (uint8_t *)fno->lfname, (uint8_t *)fno->fname ) ; // Copy 8.3 name - } - int32_t len = strlen(fno->lfname) - 4 ; - if ( len < 0 ) - { - loop = 1 ; - } - if ( fno->lfname[len] != '.' ) - { - loop = 1 ; - } - if ( ( fno->lfname[len+1] != 'b' ) && ( fno->lfname[len+1] != 'B' ) ) - { - loop = 1 ; - } - if ( ( fno->lfname[len+2] != 'i' ) && ( fno->lfname[len+2] != 'I' ) ) - { - loop = 1 ; - } - if ( ( fno->lfname[len+3] != 'n' ) && ( fno->lfname[len+3] != 'N' ) ) - { - loop = 1 ; - } + if (fr != FR_OK || fno->fname[0] == 0) { + break; + } + if (*fno->lfname == 0) { + cpystr((uint8_t *) fno->lfname, (uint8_t *) fno->fname); // Copy 8.3 name + } + int32_t len = strlen(fno->lfname) - 4; + if (len < 0) { + loop = 1; + } + if (fno->lfname[len] != '.') { + loop = 1; + } + if ((fno->lfname[len + 1] != 'b') && (fno->lfname[len + 1] != 'B')) { + loop = 1; + } + if ((fno->lfname[len + 2] != 'i') && (fno->lfname[len + 2] != 'I')) { + loop = 1; + } + if ((fno->lfname[len + 3] != 'n') && (fno->lfname[len + 3] != 'N')) { + loop = 1; + } - } while ( loop ) ; - return fr ; + } while (loop); + return fr; } - -uint32_t fillNames( uint32_t index ) +uint32_t fillNames(uint32_t index) { - uint32_t i ; - FRESULT fr ; - Finfo.lfname = Filenames[0] ; - Finfo.lfsize = 48 ; - fr = f_readdir ( &Dj, 0 ) ; // rewind - fr = f_readdir ( &Dj, &Finfo ) ; // Skip . - fr = f_readdir ( &Dj, &Finfo ) ; // Skip .. - i = 0 ; - while ( i <= index ) - { - fr = readBinDir( &Dj, &Finfo ) ; // First entry - FileSize[0] = Finfo.fsize ; - i += 1 ; - if ( fr == FR_NO_FILE) - { - return 0 ; - } - } - for ( i = 1 ; i < 7 ; i += 1 ) - { - Finfo.lfname = Filenames[i] ; - fr = readBinDir( &Dj, &Finfo ) ; // First entry - FileSize[i] = Finfo.fsize ; - if ( fr != FR_OK || Finfo.fname[0] == 0 ) - { - break ; - } - } - return i ; + uint32_t i; + FRESULT fr; + Finfo.lfname = Filenames[0]; + Finfo.lfsize = 48; + fr = f_readdir(&Dj, 0); // rewind + fr = f_readdir(&Dj, &Finfo); // Skip . + fr = f_readdir(&Dj, &Finfo); // Skip .. + i = 0; + while (i <= index) { + fr = readBinDir(&Dj, &Finfo); // First entry + FileSize[0] = Finfo.fsize; + i += 1; + if (fr == FR_NO_FILE) { + return 0; + } + } + for (i = 1; i < 7; i += 1) { + Finfo.lfname = Filenames[i]; + fr = readBinDir(&Dj, &Finfo); // First entry + FileSize[i] = Finfo.fsize; + if (fr != FR_OK || Finfo.fname[0] == 0) { + break; + } + } + return i; } -FRESULT openFirmwareFile( uint32_t index ) +FRESULT openFirmwareFile(uint32_t index) { - cpystr( cpystr( (uint8_t *)FlashFilename, (uint8_t *)"\\firmware\\" ), (uint8_t *)Filenames[index] ) ; - f_open( &FlashFile, FlashFilename, FA_READ ) ; - f_lseek ( &FlashFile, 32768 ) ; - return f_read( &FlashFile, (BYTE *)Block_buffer, 4096, &BlockCount ) ; + cpystr(cpystr((uint8_t *) FlashFilename, (uint8_t *) "\\firmware\\"), + (uint8_t *) Filenames[index]); + f_open(&FlashFile, FlashFilename, FA_READ); + f_lseek(&FlashFile, 32768); + return f_read(&FlashFile, (BYTE *) Block_buffer, 4096, &BlockCount); } - - -uint8_t flashFile( uint32_t index ) +uint8_t flashFile(uint32_t index) { - FRESULT fr ; + FRESULT fr; - lcd_clear() ; - lcd_putsLeft( 0, "\005Flash File" ) ; - if ( Valid == 0 ) - { - // Validate file here - // return 3 if invalid - fr = openFirmwareFile( index ) ; - fr = f_close( &FlashFile ) ; + lcd_clear(); + lcd_putsLeft(0, "\005Flash File"); + if (Valid == 0) { + // Validate file here + // return 3 if invalid + fr = openFirmwareFile(index); + fr = f_close(&FlashFile); - Valid = 1 ; - if ( isFirmwareStart( Block_buffer ) == 0 ) - { - Valid = 2 ; - } - } - if ( Valid == 2 ) - { - lcd_putsLeft( 3*FH,"NOT A VALID FIRMWARE") ; + Valid = 1; + if (isFirmwareStart(Block_buffer) == 0) { + Valid = 2; + } + } + if (Valid == 2) { + lcd_putsLeft(3 * FH, "NOT A VALID FIRMWARE"); #ifdef PCBTARANIS - lcd_putsLeft( 6*FH,"\015[EXIT]") ; + lcd_putsLeft(6 * FH, "\015[EXIT]"); #else - lcd_putsLeft( 6*FH,"\007[EXIT]") ; + lcd_putsLeft( 6*FH,"\007[EXIT]"); #endif - uint8_t event = getEvent() ; - if ( event == EVT_KEY_FIRST(BOOT_KEY_EXIT) ) - { - return 3 ; - } - return 4 ; // - } - lcd_putsnAtt( 0, 2*FH, Filenames[index], DISPLAY_CHAR_WIDTH, 0 ) ; + uint8_t event = getEvent(); + if (event == EVT_KEY_FIRST(BOOT_KEY_EXIT)) { + return 3; + } + return 4; // + } + lcd_putsnAtt(0, 2 * FH, Filenames[index], DISPLAY_CHAR_WIDTH, 0); #ifdef PCBTARANIS - lcd_putsLeft( 6*FH,"\010[ENTER]\021[EXIT]") ; - lcd_putsLeft( 5*FH,"\010YES\021NO") ; + lcd_putsLeft(6 * FH, "\010[ENTER]\021[EXIT]"); + lcd_putsLeft(5 * FH, "\010YES\021NO"); #else - lcd_putsLeft( 6*FH,"\003[MENU]\013[EXIT]") ; - lcd_putsLeft( 5*FH,"\003YES\013NO") ; + lcd_putsLeft( 6*FH,"\003[MENU]\013[EXIT]"); + lcd_putsLeft( 5*FH,"\003YES\013NO"); #endif - uint8_t event = getEvent() ; + uint8_t event = getEvent(); - if ( event == EVT_KEY_FIRST(BOOT_KEY_MENU) ) - { - fr = openFirmwareFile( index ) ; - FirmwareSize = FileSize[index] ; - if ( fr != FR_OK ) - { - return 4 ; // File open error - } - return 2 ; - } - if ( event == EVT_KEY_FIRST(BOOT_KEY_EXIT) ) - { - return 1 ; - } - return 0 ; + if (event == EVT_KEY_FIRST(BOOT_KEY_MENU)) { + fr = openFirmwareFile(index); + FirmwareSize = FileSize[index]; + if (fr != FR_OK) { + return 4; // File open error + } + return 2; + } + if (event == EVT_KEY_FIRST(BOOT_KEY_EXIT)) { + return 1; + } + return 0; } +extern Key keys[]; -extern Key keys[] ; - -static uint32_t PowerUpDelay ; +static uint32_t PowerUpDelay; int main() { - uint32_t i ; - uint8_t index = 0 ; + uint32_t i; + uint8_t index = 0; #ifdef PCBTARANIS - uint8_t TenCount = 2 ; + uint8_t TenCount = 2; #endif - uint8_t maxhsize = DISPLAY_CHAR_WIDTH ; - FRESULT fr ; - uint32_t state = ST_START ; - uint32_t nameCount = 0 ; - uint32_t vpos = 0 ; - uint32_t hpos = 0 ; + uint8_t maxhsize = DISPLAY_CHAR_WIDTH; + FRESULT fr; + uint32_t state = ST_START; + uint32_t nameCount = 0; + uint32_t vpos = 0; + uint32_t hpos = 0; #ifdef PCBTARANIS - uint32_t firmwareAddress = 0x08000000 ; + uint32_t firmwareAddress = 0x08000000; #endif #ifdef PCBSKY - uint32_t firmwareAddress = 0x00400000 ; + uint32_t firmwareAddress = 0x00400000; #endif - uint32_t firmwareWritten = 0 ; + uint32_t firmwareWritten = 0; #ifdef PCBTARANIS - wdt_reset() ; - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ; // Enable portA clock + wdt_reset(); + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN; // Enable portA clock #endif - pwrInit() ; + pwrInit(); #ifdef PCBSKY - MATRIX->CCFG_SYSIO |= 0x000000F0L ; // Disable syspins, enable B4,5,6,7 + MATRIX->CCFG_SYSIO |= 0x000000F0L; // Disable syspins, enable B4,5,6,7 #endif #ifdef PCBSKY - init_SDcard() ; - PIOC->PIO_PER = PIO_PC25 ; // Enable bit C25 (USB-detect) - start_timer0() ; + init_SDcard(); + PIOC->PIO_PER = PIO_PC25; // Enable bit C25 (USB-detect) + start_timer0(); #endif - lcdInit() ; + lcdInit(); #ifdef PCBSKY -extern uint8_t OptrexDisplay ; - OptrexDisplay = 1 ; + extern uint8_t OptrexDisplay; + OptrexDisplay = 1; #endif - lcd_clear() ; + lcd_clear(); #ifdef PCBTARANIS - lcd_putsLeft( 0, "\006Boot Loader" ) ; + lcd_putsLeft(0, "\006Boot Loader"); #endif - lcdRefresh() ; + lcdRefresh(); #ifdef PCBSKY - OptrexDisplay = 0 ; - lcdRefresh() ; + OptrexDisplay = 0; + lcdRefresh(); #endif #ifdef PCBTARANIS - keysInit() ; - I2C_EE_Init() ; - init_hw_timer() ; + keysInit(); + I2C_EE_Init(); + init_hw_timer(); #endif - __enable_irq() ; - init10msTimer() ; + __enable_irq(); + init10msTimer(); #ifdef PCBSKY - EblockAddress = -1 ; - init_spi() ; + EblockAddress = -1; + init_spi(); #endif #ifdef PCBSKY - uint32_t chip_id = CHIPID->CHIPID_CIDR ; + uint32_t chip_id = CHIPID->CHIPID_CIDR; - FlashSize = ( (chip_id >> 8 ) & 0x000F ) == 9 ? 256 : 512 ; + FlashSize = ( (chip_id >> 8 ) & 0x000F ) == 9 ? 256 : 512; #endif #ifdef PCBTARANIS - FlashSize = 512 ; + FlashSize = 512; #endif #ifdef PCBSKY - LockBits = readLockBits() ; - if ( LockBits ) - { - clearLockBits() ; - } + LockBits = readLockBits(); + if ( LockBits ) + { + clearLockBits(); + } #endif #ifdef PCBTARANIS - // SD card detect pin - // configure_pins( SD_PRESENT_GPIO_Pin, PIN_PORTD | PIN_INPUT | PIN_PULLUP ) ; - sdInit() ; - unlockFlash() ; + // SD card detect pin + // configure_pins( SD_PRESENT_GPIO_Pin, PIN_PORTD | PIN_INPUT | PIN_PULLUP ) ; + sdInit(); + unlockFlash(); - usbInit() ; - usbStart() ; + usbInit(); + usbStart(); #endif - for(;;) - { + for (;;) { #ifdef PCBSKY - usbMassStorage() ; + usbMassStorage(); #endif - wdt_reset() ; + wdt_reset(); - if ( Tenms ) - { - wdt_reset() ; // Retrigger hardware watchdog + if (Tenms) { + wdt_reset(); // Retrigger hardware watchdog - if ( EE_timer ) - { - if ( --EE_timer == 0) - { + if (EE_timer) { + if (--EE_timer == 0) { #ifdef PCBSKY - writeBlock() ; + writeBlock(); #endif - } - } + } + } - Tenms = 0; - lcd_clear(); - lcd_putsLeft(0, CENTER "Boot Loader"); - lcd_invert_line(0); + Tenms = 0; + lcd_clear(); + lcd_putsLeft(0, CENTER "Boot Loader"); + lcd_invert_line(0); - { + { - if ( usbPlugged() ) - { - state = ST_USB ; - } + if (usbPlugged()) { + state = ST_USB; + } - if ( state == ST_USB ) - { + if (state == ST_USB) { #ifdef PCBSKY - lcd_putsLeft( 3*FH, "\010BUSY" ) ; + lcd_putsLeft( 3*FH, "\010BUSY" ); #endif #ifdef PCBTARANIS - lcd_putsLeft( 3*FH, "\016BUSY" ) ; + lcd_putsLeft(3 * FH, "\016BUSY"); #endif - if ( usbPlugged() == 0 ) - { - state = ST_START ; - } + if (usbPlugged() == 0) { + state = ST_START; + } #ifdef PCBSKY - lcd_putc( 0, 6*FH, 'F' ) ; - lcd_putc( 6, 6*FH, '0' + FlashBlocked ) ; - lcd_putc( 0, 7*FH, 'E' ) ; - lcd_putc( 6, 7*FH, '0' + EepromBlocked ) ; + lcd_putc( 0, 6*FH, 'F' ); + lcd_putc( 6, 6*FH, '0' + FlashBlocked ); + lcd_putc( 0, 7*FH, 'E' ); + lcd_putc( 6, 7*FH, '0' + EepromBlocked ); #endif - } + } - if ( state == ST_START ) - { - sdInit(); - fr = FR_OK; - } - else - { - fr = FR_OK ; - } + if (state == ST_START) { + sdInit(); + fr = FR_OK; + } + else { + fr = FR_OK; + } - if ( fr == FR_OK) - { - if ( state == ST_START ) - { - state = ST_DIR_CHECK ; - } - } - if ( state == ST_DIR_CHECK ) - { - fr = f_chdir("/firmware") ; - if ( fr == FR_OK ) - { - state = ST_OPEN_DIR ; - index = 0 ; - } - } - if ( state == ST_DIR_CHECK ) - { + if (fr == FR_OK) { + if (state == ST_START) { + state = ST_DIR_CHECK; + } + } + if (state == ST_DIR_CHECK) { + fr = f_chdir("/firmware"); + if (fr == FR_OK) { + state = ST_OPEN_DIR; + index = 0; + } + } + if (state == ST_DIR_CHECK) { #ifdef PCBSKY - lcd_putsLeft( 2*FH, "\005No Firmware" ) ; + lcd_putsLeft( 2*FH, "\005No Firmware" ); #endif #ifdef PCBTARANIS - lcd_putsLeft( 2*FH, "\013No Firmware" ) ; + lcd_putsLeft(2 * FH, "\013No Firmware"); #endif - } - if ( state == ST_OPEN_DIR ) - { - fr = f_opendir(&Dj, ".") ; - if ( fr == FR_OK ) - { - state = ST_FILE_LIST ; - index = 0 ; - nameCount = fillNames( 0 ) ; - hpos = 0 ; - vpos = 0 ; - } - } - if ( state == ST_FILE_LIST ) - { - uint32_t limit = 6 ; - if ( nameCount < limit ) - { - limit = nameCount ; - } - maxhsize = 0 ; - for ( i = 0 ; i < limit ; i += 1 ) - { - uint32_t x ; - x = strlen( Filenames[i] ) ; - if ( x > maxhsize ) - { - maxhsize = x ; - } - if ( x > DISPLAY_CHAR_WIDTH ) - { - if ( ( hpos + DISPLAY_CHAR_WIDTH ) > x ) - { - x = x - DISPLAY_CHAR_WIDTH ; - } - else - { - x = hpos ; - } - } - else - { - x = 0 ; - } - lcd_putsnAtt( 0, 16+FH*i, &Filenames[i][x], DISPLAY_CHAR_WIDTH, 0 ) ; - } - { - uint8_t event = getEvent() ; + } + if (state == ST_OPEN_DIR) { + fr = f_opendir(&Dj, "."); + if (fr == FR_OK) { + state = ST_FILE_LIST; + index = 0; + nameCount = fillNames(0); + hpos = 0; + vpos = 0; + } + } + if (state == ST_FILE_LIST) { + uint32_t limit = 6; + if (nameCount < limit) { + limit = nameCount; + } + maxhsize = 0; + for (i = 0; i < limit; i += 1) { + uint32_t x; + x = strlen(Filenames[i]); + if (x > maxhsize) { + maxhsize = x; + } + if (x > DISPLAY_CHAR_WIDTH) { + if ((hpos + DISPLAY_CHAR_WIDTH) > x) { + x = x - DISPLAY_CHAR_WIDTH; + } + else { + x = hpos; + } + } + else { + x = 0; + } + lcd_putsnAtt(0, 16 + FH * i, &Filenames[i][x], DISPLAY_CHAR_WIDTH, + 0); + } + { + uint8_t event = getEvent(); - if ( ( event == EVT_KEY_REPT(BOOT_KEY_DOWN) ) || event == EVT_KEY_FIRST(BOOT_KEY_DOWN) ) - { - if ( vpos < limit-1 ) - { - vpos += 1 ; - } - else - { - if ( nameCount > limit ) - { - index += 1 ; - nameCount = fillNames( index ) ; - } - } - } - if ( ( event == EVT_KEY_REPT(BOOT_KEY_UP)) || ( event == EVT_KEY_FIRST(BOOT_KEY_UP) ) ) - { - if ( vpos > 0 ) - { - vpos -= 1 ; - } - else - { - if ( index ) - { - index -= 1 ; - nameCount = fillNames( index ) ; - } - } - } - if ( ( event == EVT_KEY_REPT(BOOT_KEY_RIGHT)) || ( event == EVT_KEY_FIRST(BOOT_KEY_RIGHT) ) ) - { - if ( hpos + DISPLAY_CHAR_WIDTH < maxhsize ) - { - hpos += 1 ; - } - } - if ( ( event == EVT_KEY_REPT(BOOT_KEY_LEFT)) || ( event == EVT_KEY_FIRST(BOOT_KEY_LEFT) ) ) - { - if ( hpos ) - { - hpos -= 1 ; - } - } - if ( event == EVT_KEY_LONG(BOOT_KEY_MENU) ) - { - // Select file to flash - state = ST_FLASH_CHECK ; - Valid = 0 ; - } - if ( event == EVT_KEY_LONG(BOOT_KEY_EXIT) ) - { - state = ST_REBOOT ; - } - } - lcd_invert_line(2+vpos); - // lcd_char_inverse( 0, 2*FH+FH*vpos, DISPLAY_CHAR_WIDTH*FW, 0 ) ; - } - if ( state == ST_FLASH_CHECK ) - { - i = flashFile( vpos ) ; - FirmwareSize = FileSize[vpos] - 32768 ; - if ( i == 1 ) - { - state = ST_FILE_LIST ; // Canceled - } - if ( i == 2 ) - { + if ((event == EVT_KEY_REPT(BOOT_KEY_DOWN)) + || event == EVT_KEY_FIRST(BOOT_KEY_DOWN)) { + if (vpos < limit - 1) { + vpos += 1; + } + else { + if (nameCount > limit) { + index += 1; + nameCount = fillNames(index); + } + } + } + if ((event == EVT_KEY_REPT(BOOT_KEY_UP)) + || (event == EVT_KEY_FIRST(BOOT_KEY_UP))) { + if (vpos > 0) { + vpos -= 1; + } + else { + if (index) { + index -= 1; + nameCount = fillNames(index); + } + } + } + if ((event == EVT_KEY_REPT(BOOT_KEY_RIGHT)) + || (event == EVT_KEY_FIRST(BOOT_KEY_RIGHT))) { + if (hpos + DISPLAY_CHAR_WIDTH < maxhsize) { + hpos += 1; + } + } + if ((event == EVT_KEY_REPT(BOOT_KEY_LEFT)) + || (event == EVT_KEY_FIRST(BOOT_KEY_LEFT))) { + if (hpos) { + hpos -= 1; + } + } + if (event == EVT_KEY_LONG(BOOT_KEY_MENU)) { + // Select file to flash + state = ST_FLASH_CHECK; + Valid = 0; + } + if (event == EVT_KEY_LONG(BOOT_KEY_EXIT)) { + state = ST_REBOOT; + } + } + lcd_invert_line(2 + vpos); + // lcd_char_inverse( 0, 2*FH+FH*vpos, DISPLAY_CHAR_WIDTH*FW, 0 ) ; + } + if (state == ST_FLASH_CHECK) { + i = flashFile(vpos); + FirmwareSize = FileSize[vpos] - 32768; + if (i == 1) { + state = ST_FILE_LIST; // Canceled + } + if (i == 2) { #ifdef PCBSKY - firmwareAddress = 0x00408000 ; + firmwareAddress = 0x00408000; #endif #ifdef PCBTARANIS - firmwareAddress = 0x08008000 ; + firmwareAddress = 0x08008000; #endif - firmwareWritten = 0 ; - state = ST_FLASHING ; // confirmed - } - if ( i == 3 ) - { - // Invalid file - state = ST_FILE_LIST ; // Canceled - } - } - if ( state == ST_FLASHING ) - { - // Commit to flashing - uint32_t blockOffset = 0 ; - lcd_putsLeft( 3*FH, "Flashing" ) ; - while ( BlockCount ) - { - program( (uint32_t *)firmwareAddress, &Block_buffer[blockOffset] ) ; // size is 256 bytes - blockOffset += 64 ; // 32-bit words (256 bytes) - firmwareAddress += 256 ; - if ( BlockCount > 256 ) - { - BlockCount -= 256 ; - } - else - { - BlockCount = 0 ; - } - } - firmwareWritten += 1 ; - uint32_t width = FirmwareSize / 4096 ; - lcd_hline( 0, 5*FH-1, width+1 ) ; - lcd_hline( 0, 6*FH, width+1 ) ; - lcd_vline( width, 5*FH, 8 ) ; - for ( i = 0 ; i < firmwareWritten ; i += 1 ) - { - lcd_vline( i, 5*FH, 8 ) ; - } - fr = f_read( &FlashFile, (BYTE *)Block_buffer, 4096, &BlockCount ) ; - if ( BlockCount == 0 ) - { - state = ST_FLASH_DONE ; - } - if ( firmwareWritten > FlashSize/4 - 9 ) // (127-8, or 63-8) 4K blocks - { - state = ST_FLASH_DONE ; // Backstop - } - } - if ( state == ST_FLASH_DONE ) - { - uint8_t event = getEvent() ; - lcd_putsLeft( 3*FH, "Flashing Complete" ) ; - if ( event == EVT_KEY_FIRST(BOOT_KEY_EXIT) ) - { - state = ST_FILE_LIST ; - } - } - } + firmwareWritten = 0; + state = ST_FLASHING; // confirmed + } + if (i == 3) { + // Invalid file + state = ST_FILE_LIST; // Canceled + } + } + if (state == ST_FLASHING) { + // Commit to flashing + uint32_t blockOffset = 0; + lcd_putsLeft(3 * FH, "Flashing"); + while (BlockCount) { + program((uint32_t *) firmwareAddress, &Block_buffer[blockOffset]);// size is 256 bytes + blockOffset += 64; // 32-bit words (256 bytes) + firmwareAddress += 256; + if (BlockCount > 256) { + BlockCount -= 256; + } + else { + BlockCount = 0; + } + } + firmwareWritten += 1; + uint32_t width = FirmwareSize / 4096; + lcd_hline(0, 5 * FH - 1, width + 1); + lcd_hline(0, 6 * FH, width + 1); + lcd_vline(width, 5 * FH, 8); + for (i = 0; i < firmwareWritten; i += 1) { + lcd_vline(i, 5 * FH, 8); + } + fr = f_read(&FlashFile, (BYTE *) Block_buffer, 4096, &BlockCount); + if (BlockCount == 0) { + state = ST_FLASH_DONE; + } + if (firmwareWritten > FlashSize / 4 - 9)// (127-8, or 63-8) 4K blocks + { + state = ST_FLASH_DONE; // Backstop + } + } + if (state == ST_FLASH_DONE) { + uint8_t event = getEvent(); + lcd_putsLeft(3 * FH, "Flashing Complete"); + if (event == EVT_KEY_FIRST(BOOT_KEY_EXIT)) { + state = ST_FILE_LIST; + } + } + } - if ( --TenCount == 0 ) { - TenCount = 2 ; - lcdRefresh() ; - } + if (--TenCount == 0) { + TenCount = 2; + lcdRefresh(); + } - if ( PowerUpDelay < 20 ) // 200 mS - { - PowerUpDelay += 1 ; - } - else - { - sdPoll10ms() ; + if (PowerUpDelay < 20) // 200 mS + { + PowerUpDelay += 1; + } + else { + sdPoll10ms(); - } - } - if ((state < ST_FLASH_CHECK) || (state == ST_FLASH_DONE)) - { - if (pwrCheck() == e_power_off ) { - pwrOff() ; - for(;;) - { - // Wait for power to go off - } - } - } - if ( state < ST_FILE_LIST ) - { - if ( getEvent() == EVT_KEY_LONG(BOOT_KEY_EXIT) ) - { - state = ST_REBOOT ; - } - } - if ( state == ST_REBOOT ) - { - if ( (~readKeys() & 0x7E) == 0 ) - { - NVIC_SystemReset() ; - } - } + } + } + if ((state < ST_FLASH_CHECK) || (state == ST_FLASH_DONE)) { + if (pwrCheck() == e_power_off) { + pwrOff(); + for (;;) { + // Wait for power to go off + } + } + } + if (state < ST_FILE_LIST) { + if (getEvent() == EVT_KEY_LONG(BOOT_KEY_EXIT)) { + state = ST_REBOOT; + } + } + if (state == ST_REBOOT) { + if ((~readKeys() & 0x7E) == 0) { + NVIC_SystemReset(); + } + } - } + } return 0; } - From 7738aa27bd57da992cabd55c4b7c8822d22303ca Mon Sep 17 00:00:00 2001 From: bsongis Date: Wed, 12 Mar 2014 16:19:34 +0100 Subject: [PATCH 062/285] Reindentation of loadboot.cpp --- radio/src/loadboot.cpp | 186 +++++++++++++++++++++-------------------- 1 file changed, 94 insertions(+), 92 deletions(-) diff --git a/radio/src/loadboot.cpp b/radio/src/loadboot.cpp index b06241019..867103916 100644 --- a/radio/src/loadboot.cpp +++ b/radio/src/loadboot.cpp @@ -1,34 +1,34 @@ /**************************************************************************** -* Copyright (c) 2014 by Michael Blandford. All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* 1. Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* 3. Neither the name of the author nor the names of its contributors may -* be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL -* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -* SUCH DAMAGE. -* -**************************************************************************** -* Other Authors: + * Copyright (c) 2014 by Michael Blandford. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the author nor the names of its contributors may + * be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF + * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + **************************************************************************** + * Other Authors: * - Andre Bernet * - Bertrand Songis * - Bryan J. Rentoul (Gruvin) @@ -42,37 +42,35 @@ * - Rob Thomson * - Romolo Manfredini * - Thomas Husterer -* -****************************************************************************/ - + * + ****************************************************************************/ #include + #ifdef PCBSKY #include "AT91SAM3S4.h" #endif #ifdef PCBTARANIS - #include "stm32f2xx.h" - #include "stm32f2xx_gpio.h" +#include "stm32f2xx.h" +#include "stm32f2xx_gpio.h" #endif #if defined(PCBTARANIS) void bwdt_reset() { - IWDG->KR = 0xAAAA ; // reload + IWDG->KR = 0xAAAA; // reload } #endif #if defined(PCBTARANIS) __attribute__ ((section(".bootrodata"), used)) -void _bootStart( void ) ; +void _bootStart(void); __attribute__ ((section(".isr_boot_vector"), used)) -const uint32_t BootVectors[] = { - (uint32_t)&_estack, - (uint32_t)(void (*)(void))((unsigned long)&_bootStart) -} ; +const uint32_t BootVectors[] = { (uint32_t) &_estack, + (uint32_t) (void (*)(void)) ((unsigned long) &_bootStart) }; #endif #if defined(PCBTARANIS) @@ -85,8 +83,7 @@ __attribute__ ((section(".bootrodata"), used)) const uint8_t BootCode[] = { #include "bootloader.lbm" -} ; - +}; #if defined(PCBTARANIS) @@ -94,61 +91,66 @@ __attribute__ ((section(".bootrodata"), used)) void _bootStart() { - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN ; // Enable portC clock - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOEEN ; // Enable portE clock - - GPIOC->PUPDR = 0x00000004 ; - GPIOE->PUPDR = 0x00000040 ; + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN; // Enable portC clock + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOEEN; // Enable portE clock - uint32_t i ; - for ( i = 0 ; i < 50000 ; i += 1 ) - { - bwdt_reset() ; - } + GPIOC->PUPDR = 0x00000004; + GPIOE->PUPDR = 0x00000040; - if ( (GPIOE->IDR & 0x00000008 ) == 0 ) - { - if ( (GPIOC->IDR & 0x00000002 ) == 0 ) - { - // Bootloader needed - const uint8_t *src ; - uint8_t *dest ; - uint32_t size ; + uint32_t i; + for (i = 0; i < 50000; i += 1) { + bwdt_reset(); + } - bwdt_reset() ; - size = sizeof(BootCode) ; - src = BootCode ; - dest = (uint8_t *)0x20000000 ; + if ((GPIOE->IDR & 0x00000008) == 0) { + if ((GPIOC->IDR & 0x00000002) == 0) { + // Bootloader needed + const uint8_t *src; + uint8_t *dest; + uint32_t size; - for ( ; size ; size -= 1 ) - { - *dest++ = *src++ ; - } - // Could check for a valid copy to RAM here - // Go execute bootloader - bwdt_reset() ; - - uint32_t address = *(uint32_t *)0x20000004 ; - - ((void (*)(void)) (address))() ; // Go execute the loaded application - - } - } + bwdt_reset(); + size = sizeof(BootCode); + src = BootCode; + dest = (uint8_t *) 0x20000000; + + for (; size; size -= 1) { + *dest++ = *src++; + } + // Could check for a valid copy to RAM here + // Go execute bootloader + bwdt_reset(); + + uint32_t address = *(uint32_t *) 0x20000004; + + ((void (*)(void)) (address))(); // Go execute the loaded application + + } + } // run_application() ; - asm(" mov.w r1, #134217728"); // 0x8000000 - asm(" add.w r1, #32768"); // 0x8000 - - asm(" movw r0, #60680"); // 0xED08 - asm(" movt r0, #57344"); // 0xE000 - asm(" str r1, [r0, #0]"); // Set the VTOR - - asm("ldr r0, [r1, #0]"); // Stack pointer value - asm("msr msp, r0"); // Set it - asm("ldr r0, [r1, #4]"); // Reset address + asm(" mov.w r1, #134217728"); + // 0x8000000 + asm(" add.w r1, #32768"); + // 0x8000 + + asm(" movw r0, #60680"); + // 0xED08 + asm(" movt r0, #57344"); + // 0xE000 + asm(" str r1, [r0, #0]"); + // Set the VTOR + + asm("ldr r0, [r1, #0]"); + // Stack pointer value + asm("msr msp, r0"); + // Set it + asm("ldr r0, [r1, #4]"); + // Reset address asm("mov.w r1, #1"); - asm("orr r0, r1"); // Set lsbit - asm("bx r0"); // Execute application + asm("orr r0, r1"); + // Set lsbit + asm("bx r0"); + // Execute application } #endif - From ef05cdd782c7530d2dc7d03ba03e7d2b2a708dd7 Mon Sep 17 00:00:00 2001 From: bsongis Date: Wed, 12 Mar 2014 17:30:45 +0100 Subject: [PATCH 063/285] Cosmetics --- radio/src/myeeprom.h | 18 ++++++++++++------ radio/src/telemetry/frsky.cpp | 2 +- radio/src/telemetry/frsky_sport.cpp | 2 +- radio/src/translations/en.h.txt | 4 ++-- 4 files changed, 16 insertions(+), 10 deletions(-) diff --git a/radio/src/myeeprom.h b/radio/src/myeeprom.h index ba722512f..c87086de5 100644 --- a/radio/src/myeeprom.h +++ b/radio/src/myeeprom.h @@ -1112,12 +1112,18 @@ enum FrskyUsrProtocols { USR_PROTO_LAST = USR_PROTO_WS_HOW_HIGH, }; -enum FrskySource { - FRSKY_SOURCE_NONE, - FRSKY_SOURCE_A1, - FRSKY_SOURCE_A2, - FRSKY_SOURCE_FAS, - FRSKY_SOURCE_CELLS, +enum FrskyCurrentSource { + FRSKY_CURRENT_SOURCE_NONE, + FRSKY_CURRENT_SOURCE_A1, + FRSKY_CURRENT_SOURCE_A2, + FRSKY_CURRENT_SOURCE_FAS, +}; + +enum FrskyVoltsSource { + FRSKY_VOLTS_SOURCE_A1, + FRSKY_VOLTS_SOURCE_A2, + FRSKY_VOLTS_SOURCE_FAS, + FRSKY_VOLTS_SOURCE_CELLS, }; #if defined(CPUARM) diff --git a/radio/src/telemetry/frsky.cpp b/radio/src/telemetry/frsky.cpp index 408fa43cd..45394bff0 100644 --- a/radio/src/telemetry/frsky.cpp +++ b/radio/src/telemetry/frsky.cpp @@ -723,7 +723,7 @@ void telemetryInterrupt10ms() uint16_t current = 0; #endif - channel = g_model.frsky.currentSource - FRSKY_SOURCE_A1; + channel = g_model.frsky.currentSource - FRSKY_CURRENT_SOURCE_A1; if (channel <= 1) { current = applyChannelRatio(channel, frskyData.analog[channel].value) / 10; } diff --git a/radio/src/telemetry/frsky_sport.cpp b/radio/src/telemetry/frsky_sport.cpp index 8ac5a0801..84f71cc88 100644 --- a/radio/src/telemetry/frsky_sport.cpp +++ b/radio/src/telemetry/frsky_sport.cpp @@ -595,7 +595,7 @@ void telemetryInterrupt10ms() uint16_t current = 0; #endif - channel = g_model.frsky.currentSource - FRSKY_SOURCE_A1; + channel = g_model.frsky.currentSource - FRSKY_CURRENT_SOURCE_A1; if (channel <= 1) { current = applyChannelRatio(channel, frskyData.analog[channel].value) / 10; } diff --git a/radio/src/translations/en.h.txt b/radio/src/translations/en.h.txt index 7f26756f8..d2cced3eb 100644 --- a/radio/src/translations/en.h.txt +++ b/radio/src/translations/en.h.txt @@ -319,8 +319,8 @@ #define LEN_VTELPROTO "\007" #define TR_VTELPROTO "None\0 ""Hub\0 ""WSHHigh" -#define LEN_VOLTSRC "\003" -#define TR_VOLTSRC "---""A1\0""A2\0""FAS""Cel" +#define LEN_VOLTSRC TR("\003", "\007") +#define TR_VOLTSRC TR("---""A1\0""A2\0""FAS""Cel", "---\0 ""A1\0 ""A2\0 ""FAS\0 ""Cells\0 ") #define LEN_VARIOSRC "\004" #if defined(FRSKY_SPORT) From c913aa337401e8f1aaf48bb68e09dffe2319093a Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Wed, 12 Mar 2014 18:22:02 +0100 Subject: [PATCH 064/285] Update DONATIONS.txt --- DONATIONS.txt | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/DONATIONS.txt b/DONATIONS.txt index f12ab0c37..323f2e19c 100644 --- a/DONATIONS.txt +++ b/DONATIONS.txt @@ -335,3 +335,12 @@ David Finger FrSky - www.frsky-rc.com Jean-Marie Oddo Mike Matheny +Glen Roe (Showmaster) +Arron Bates +Tim Spurr +Daniel Morgan +Trent Ready +Mark Maskiell +Robert Crockford +Mark Illum + From 0ae5d055197f4415cf21798577b4407695549eab Mon Sep 17 00:00:00 2001 From: Kjell Kernen Date: Fri, 14 Mar 2014 15:58:32 +0100 Subject: [PATCH 065/285] v 0.4 --- speaker/.gitignore | 1 + speaker/App.xaml | 8 + speaker/App.xaml.cs | 16 + speaker/MainWindow.xaml | 118 ++++ speaker/MainWindow.xaml.cs | 198 +++++++ speaker/OpenTXspeak.csproj | 117 ++++ speaker/OpenTXspeak.sln | 20 + speaker/Properties/AssemblyInfo.cs | 55 ++ speaker/Properties/Resources.Designer.cs | 71 +++ speaker/Properties/Resources.resx | 117 ++++ speaker/Properties/Settings.Designer.cs | 30 + speaker/Properties/Settings.settings | 7 + speaker/aboutWindow.xaml | 27 + speaker/aboutWindow.xaml.cs | 39 ++ speaker/icon.ico | Bin 0 -> 79774 bytes speaker/sentencetables.cs | 698 +++++++++++++++++++++++ 16 files changed, 1522 insertions(+) create mode 100644 speaker/.gitignore create mode 100644 speaker/App.xaml create mode 100644 speaker/App.xaml.cs create mode 100644 speaker/MainWindow.xaml create mode 100644 speaker/MainWindow.xaml.cs create mode 100644 speaker/OpenTXspeak.csproj create mode 100644 speaker/OpenTXspeak.sln create mode 100644 speaker/Properties/AssemblyInfo.cs create mode 100644 speaker/Properties/Resources.Designer.cs create mode 100644 speaker/Properties/Resources.resx create mode 100644 speaker/Properties/Settings.Designer.cs create mode 100644 speaker/Properties/Settings.settings create mode 100644 speaker/aboutWindow.xaml create mode 100644 speaker/aboutWindow.xaml.cs create mode 100644 speaker/icon.ico create mode 100644 speaker/sentencetables.cs diff --git a/speaker/.gitignore b/speaker/.gitignore new file mode 100644 index 000000000..3e3980000 --- /dev/null +++ b/speaker/.gitignore @@ -0,0 +1 @@ +/OpenTXspeak.suo diff --git a/speaker/App.xaml b/speaker/App.xaml new file mode 100644 index 000000000..c38764331 --- /dev/null +++ b/speaker/App.xaml @@ -0,0 +1,8 @@ + + + + + diff --git a/speaker/App.xaml.cs b/speaker/App.xaml.cs new file mode 100644 index 000000000..b6053db6e --- /dev/null +++ b/speaker/App.xaml.cs @@ -0,0 +1,16 @@ +using System; +using System.Collections.Generic; +using System.Configuration; +using System.Data; +using System.Linq; +using System.Windows; + +namespace OpenTXspeak +{ + /// + /// Interaction logic for App.xaml + /// + public partial class App : Application + { + } +} diff --git a/speaker/MainWindow.xaml b/speaker/MainWindow.xaml new file mode 100644 index 000000000..ca5ce1fbc --- /dev/null +++ b/speaker/MainWindow.xaml @@ -0,0 +1,118 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/sound/recorder/MainWindow.xaml.cs b/sound/recorder/MainWindow.xaml.cs new file mode 100644 index 000000000..8578fd9e2 --- /dev/null +++ b/sound/recorder/MainWindow.xaml.cs @@ -0,0 +1,244 @@ +/* This file is part of OpenTX Recorder. + * OpenTX Recorder is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + + * OpenTX Recorder is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see . + * + * Copyright 2014 Kjell Kernen */ + + +using System; +using System.IO; +using System.Collections.Generic; +using System.Linq; +using System.Media; +using System.Threading; +using System.Windows; +using System.Windows.Controls; +using System.Windows.Input; +using System.Windows.Navigation; +using System.Runtime.InteropServices; + +namespace OpenTXrecorder +{ + public partial class MainWindow : Window + { + [DllImport("winmm.dll", EntryPoint = "mciSendStringA", CharSet = CharSet.Ansi, SetLastError = true, ExactSpelling = true)] + private static extern int mciSendString(string lpstrCommand, string lpstrReturnString, int uReturnLength, int hwndCallback); + + SentenceTables tables = new SentenceTables(); + Languages languages = new Languages(); + Language curLang; + Sentences sentences = new Sentences(); + int added_files = 0; + bool isRecording = false; + + public MainWindow() + { + SplashScreen splash = new SplashScreen("recorder_logo.png"); + splash.Show(true); + Thread.Sleep(1500); + + InitializeComponent(); + + lvSentences.ItemsSource = sentences; + cbLanguages.ItemsSource = languages; + languages.Add("English", "en"); + languages.Add("Czech", "cz"); + languages.Add("German", "de"); + languages.Add("French", "fr"); + languages.Add("Italian", "it"); + languages.Add("Polish", "pl"); + languages.Add("Portuguese", "pt"); + languages.Add("Swedish", "se"); + languages.Add("Slovak", "sk"); + languages.Add("Spanish", "es"); + curLang = languages[0]; + cbLanguages.SelectedIndex = 0; // Note: Sets current langugage -> triggers loadlanguage() + } + + private void loadLanguage() + { + string[] system_strings; + string[] other_strings; + + try + { + system_strings = System.IO.File.ReadAllLines(@"SOUNDS\" + curLang.sName + @"\SYSTEM\system_sounds.txt"); + other_strings = System.IO.File.ReadAllLines(@"SOUNDS\" + curLang.sName + @"\other_sounds.txt"); + } + catch (IOException) + { + system_strings = tables.default_system_strings[tables.toInt(curLang.sName)]; + other_strings = tables.default_other_strings[tables.toInt(curLang.sName)]; + } + sentences.RemoveRange(0, sentences.Count); + + foreach (string str in system_strings) + sentences.Add(str, @"SOUNDS\" + curLang.sName + @"\SYSTEM\"); + + sentences.Add(@";^ System Sounds ^;", ""); + + foreach (string str in other_strings) + sentences.Add(str, @"SOUNDS\" + curLang.sName + @"\"); + + lvSentences.Items.Refresh(); // Workaround - Two way binding is better + } + + private void saveLanguage() + { + System.IO.Directory.CreateDirectory(@"SOUNDS\" + curLang.sName + @"\SYSTEM"); + StreamWriter sw = File.CreateText(@"SOUNDS\" + curLang.sName + @"\SYSTEM\system_sounds.txt"); + int i; + for (i = 0; sentences[i].fileName != ""; i++) + { + sw.WriteLine(sentences[i].toRaw()); + } + sw.Close(); + sw = File.CreateText(@"SOUNDS\" + curLang.sName + @"\other_sounds.txt"); + for (i++; i < sentences.Count; i++) + { + sw.WriteLine(sentences[i].toRaw()); + } + sw.Close(); + } + + private void cbLanguages_SelectionChanged(object sender, SelectionChangedEventArgs e) + { + curLang = (Language)e.AddedItems[0]; + loadLanguage(); + } + + private void lvSentences_MouseDoubleClick(object sender, MouseButtonEventArgs e) + { + if (this.lvSentences.SelectedItems.Count < 1) return; + + Sentence sentence = (Sentence)this.lvSentences.SelectedItem; + if (sentence.fileExists) + { + try + { + SoundPlayer player = new SoundPlayer(sentence.fullPath()); + player.Play(); + } + catch (Exception) { }; // Catch and disregard all media exceptions + } + } + + private void openTXLogo_MouseLeftButtonDown(object sender, MouseButtonEventArgs e) + { + AboutWindow aboutWindow = new AboutWindow(); + aboutWindow.ShowDialog(); + } + + private void buttonAddItem_Click(object sender, RoutedEventArgs e) + { + added_files++; + sentences.Add(new Sentence("new_file_" + added_files.ToString() + ";New Description;New Voice Message", @"SOUNDS\" + curLang.sName + @"\")); + this.lvSentences.Items.Refresh(); + this.lvSentences.SelectedIndex = this.lvSentences.Items.Count - 1; + this.lvSentences.ScrollIntoView(this.lvSentences.SelectedItem); + } + + private void btnRecord_Click(object sender, RoutedEventArgs e) + { + if (this.lvSentences.SelectedItems.Count < 1) return; + + if (isRecording) + btnStop_Click(sender, e); + else + { + saveLanguage(); + isRecording = true; + lblRecording.Visibility = System.Windows.Visibility.Visible; + Sentence sentence = (Sentence)this.lvSentences.SelectedItem; + string path = sentence.fullPath(); + Directory.CreateDirectory(Path.GetDirectoryName(path)); // Create directory if it doesn't exist + System.IO.File.WriteAllText(path, ""); // Creates and flushes a file if it does not exist + + mciSendString("open new Type waveaudio Alias recsound", "", 0, 0); + mciSendString("record recsound", "", 0, 0); + } + } + + private void btnStop_Click(object sender, RoutedEventArgs e) + { + if (this.lvSentences.SelectedItems.Count < 1) return; + + int index = this.lvSentences.SelectedIndex; + lblRecording.Visibility = System.Windows.Visibility.Hidden; + isRecording = false; + Sentence sentence = (Sentence)this.lvSentences.SelectedItem; + mciSendString("save recsound " + sentence.fullPath(), "", 0, 0); + mciSendString("close recsound ", "", 0, 0); + + loadLanguage(); // Called to refresh the sentence data of the current langugae + this.lvSentences.SelectedIndex = index; + } + + private void btnPlay_Click(object sender, RoutedEventArgs e) + { + lblRecording.Visibility = System.Windows.Visibility.Hidden; + lvSentences_MouseDoubleClick(sender, null); + } + } + + public class Language + { + public string lName { get; set; } + public string sName { get; set; } + } + + public class Languages : List + { + public void Add(string longer, string shorter) + { + this.Add(new Language { lName = longer, sName = shorter }); + } + } + + public class Sentence + { + public string fileName { get; set; } + public string description { get; set; } + public string voiceString { get; set; } + public string path { get; set; } + public bool fileExists { get; set; } + + public Sentence(string rawString, string dirPath) + { + string[] words = rawString.Split(';'); + fileName = words[0].TrimStart(' ', '\"'); + description = words[1]; + voiceString = words[2].TrimEnd('\"', ',', ' '); + path = dirPath; + fileExists = File.Exists(fullPath()); + } + + public string fullPath() + { + return System.AppDomain.CurrentDomain.BaseDirectory + path + fileName + ".wav"; + } + + public string toRaw() + { + return "\"" + fileName + ";" + description + ";" + voiceString + "\","; + } + } + + public class Sentences : List + { + public void Add(string rawString, string dirPath) + { + this.Add(new Sentence(rawString, dirPath)); + } + } +} diff --git a/sound/recorder/OpenTXRecorder.csproj b/sound/recorder/OpenTXRecorder.csproj new file mode 100644 index 000000000..74a04e914 --- /dev/null +++ b/sound/recorder/OpenTXRecorder.csproj @@ -0,0 +1,169 @@ + + + + Debug + x86 + 8.0.30703 + 2.0 + {8143D08D-1861-42DD-A861-56B15DE42A69} + WinExe + Properties + OpenTXrecorder + OpenTXrecorder + v4.0 + Client + 512 + {60dc8134-eba5-43b8-bcc9-bb4bc16c2548};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + 4 + false + publish\ + true + Disk + false + Foreground + 7 + Days + false + false + true + 0 + 1.0.0.%2a + false + true + + + x86 + true + full + false + bin\Debug\ + DEBUG;TRACE + prompt + 4 + + + x86 + pdbonly + true + bin\Release\ + TRACE + prompt + 4 + + + icon.ico + + + + + + + + + + + + 4.0 + + + + + + + + MSBuild:Compile + Designer + + + AboutWindow.xaml + + + App.xaml + + + + MSBuild:Compile + Designer + + + MainWindow.xaml + Code + + + Designer + MSBuild:Compile + + + + + Code + + + True + True + Resources.resx + + + True + Settings.settings + True + + + ResXFileCodeGenerator + Resources.Designer.cs + + + SettingsSingleFileGenerator + Settings.Designer.cs + + + + + + + + + + + + False + Microsoft .NET Framework 4 Client Profile %28x86 and x64%29 + true + + + False + .NET Framework 3.5 SP1 Client Profile + false + + + False + .NET Framework 3.5 SP1 + false + + + False + Windows Installer 3.1 + true + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/sound/recorder/Properties/AssemblyInfo.cs b/sound/recorder/Properties/AssemblyInfo.cs new file mode 100644 index 000000000..d01499fd5 --- /dev/null +++ b/sound/recorder/Properties/AssemblyInfo.cs @@ -0,0 +1,71 @@ +/* This file is part of OpenTX Recorder. +* OpenTX Recorder is free software: you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation, either version 3 of the License, or +* (at your option) any later version. + +* OpenTX Recorder is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. + +* You should have received a copy of the GNU General Public License +* along with Foobar. If not, see . +* +* Copyright 2014 Kjell Kernen */ + +using System.Reflection; +using System.Resources; +using System.Runtime.CompilerServices; +using System.Runtime.InteropServices; +using System.Windows; + +// General Information about an assembly is controlled through the following +// set of attributes. Change these attribute values to modify the information +// associated with an assembly. +[assembly: AssemblyTitle("OpenTX Recorder")] +[assembly: AssemblyDescription("")] +[assembly: AssemblyConfiguration("")] +[assembly: AssemblyCompany("OpenTX Team")] +[assembly: AssemblyProduct("OpenTX Recorder")] +[assembly: AssemblyCopyright("Copyright © Kjell Kernen 2014")] +[assembly: AssemblyTrademark("")] +[assembly: AssemblyCulture("")] + +// Setting ComVisible to false makes the types in this assembly not visible +// to COM components. If you need to access a type in this assembly from +// COM, set the ComVisible attribute to true on that type. +[assembly: ComVisible(false)] + +//In order to begin building localizable applications, set +//CultureYouAreCodingWith in your .csproj file +//inside a . For example, if you are using US english +//in your source files, set the to en-US. Then uncomment +//the NeutralResourceLanguage attribute below. Update the "en-US" in +//the line below to match the UICulture setting in the project file. + +//[assembly: NeutralResourcesLanguage("en-US", UltimateResourceFallbackLocation.Satellite)] + + +[assembly: ThemeInfo( + ResourceDictionaryLocation.None, //where theme specific resource dictionaries are located + //(used if a resource is not found in the page, + // or application resource dictionaries) + ResourceDictionaryLocation.SourceAssembly //where the generic resource dictionary is located + //(used if a resource is not found in the page, + // app, or any theme specific resource dictionaries) +)] + + +// Version information for an assembly consists of the following four values: +// +// Major Version +// Minor Version +// Build Number +// Revision +// +// You can specify all the values or you can default the Build and Revision Numbers +// by using the '*' as shown below: +// [assembly: AssemblyVersion("1.0.*")] +[assembly: AssemblyVersion("0.1")] +[assembly: AssemblyFileVersion("0.1")] diff --git a/sound/recorder/Properties/Resources.Designer.cs b/sound/recorder/Properties/Resources.Designer.cs new file mode 100644 index 000000000..04f945574 --- /dev/null +++ b/sound/recorder/Properties/Resources.Designer.cs @@ -0,0 +1,63 @@ +//------------------------------------------------------------------------------ +// +// This code was generated by a tool. +// Runtime Version:4.0.30319.18444 +// +// Changes to this file may cause incorrect behavior and will be lost if +// the code is regenerated. +// +//------------------------------------------------------------------------------ + +namespace OpenTXrecorder.Properties { + using System; + + + /// + /// A strongly-typed resource class, for looking up localized strings, etc. + /// + // This class was auto-generated by the StronglyTypedResourceBuilder + // class via a tool like ResGen or Visual Studio. + // To add or remove a member, edit your .ResX file then rerun ResGen + // with the /str option, or rebuild your VS project. + [global::System.CodeDom.Compiler.GeneratedCodeAttribute("System.Resources.Tools.StronglyTypedResourceBuilder", "4.0.0.0")] + [global::System.Diagnostics.DebuggerNonUserCodeAttribute()] + [global::System.Runtime.CompilerServices.CompilerGeneratedAttribute()] + internal class Resources { + + private static global::System.Resources.ResourceManager resourceMan; + + private static global::System.Globalization.CultureInfo resourceCulture; + + [global::System.Diagnostics.CodeAnalysis.SuppressMessageAttribute("Microsoft.Performance", "CA1811:AvoidUncalledPrivateCode")] + internal Resources() { + } + + /// + /// Returns the cached ResourceManager instance used by this class. + /// + [global::System.ComponentModel.EditorBrowsableAttribute(global::System.ComponentModel.EditorBrowsableState.Advanced)] + internal static global::System.Resources.ResourceManager ResourceManager { + get { + if (object.ReferenceEquals(resourceMan, null)) { + global::System.Resources.ResourceManager temp = new global::System.Resources.ResourceManager("OpenTXrecorder.Properties.Resources", typeof(Resources).Assembly); + resourceMan = temp; + } + return resourceMan; + } + } + + /// + /// Overrides the current thread's CurrentUICulture property for all + /// resource lookups using this strongly typed resource class. + /// + [global::System.ComponentModel.EditorBrowsableAttribute(global::System.ComponentModel.EditorBrowsableState.Advanced)] + internal static global::System.Globalization.CultureInfo Culture { + get { + return resourceCulture; + } + set { + resourceCulture = value; + } + } + } +} diff --git a/speaker/Properties/Resources.resx b/sound/recorder/Properties/Resources.resx similarity index 100% rename from speaker/Properties/Resources.resx rename to sound/recorder/Properties/Resources.resx diff --git a/sound/recorder/Properties/Settings.Designer.cs b/sound/recorder/Properties/Settings.Designer.cs new file mode 100644 index 000000000..ffa4c812a --- /dev/null +++ b/sound/recorder/Properties/Settings.Designer.cs @@ -0,0 +1,26 @@ +//------------------------------------------------------------------------------ +// +// This code was generated by a tool. +// Runtime Version:4.0.30319.18444 +// +// Changes to this file may cause incorrect behavior and will be lost if +// the code is regenerated. +// +//------------------------------------------------------------------------------ + +namespace OpenTXrecorder.Properties { + + + [global::System.Runtime.CompilerServices.CompilerGeneratedAttribute()] + [global::System.CodeDom.Compiler.GeneratedCodeAttribute("Microsoft.VisualStudio.Editors.SettingsDesigner.SettingsSingleFileGenerator", "10.0.0.0")] + internal sealed partial class Settings : global::System.Configuration.ApplicationSettingsBase { + + private static Settings defaultInstance = ((Settings)(global::System.Configuration.ApplicationSettingsBase.Synchronized(new Settings()))); + + public static Settings Default { + get { + return defaultInstance; + } + } + } +} diff --git a/speaker/Properties/Settings.settings b/sound/recorder/Properties/Settings.settings similarity index 100% rename from speaker/Properties/Settings.settings rename to sound/recorder/Properties/Settings.settings diff --git a/sound/recorder/aboutWindow.xaml b/sound/recorder/aboutWindow.xaml new file mode 100644 index 000000000..95e440614 --- /dev/null +++ b/sound/recorder/aboutWindow.xaml @@ -0,0 +1,49 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/sound/recorder/aboutWindow.xaml.cs b/sound/recorder/aboutWindow.xaml.cs new file mode 100644 index 000000000..8e09efc76 --- /dev/null +++ b/sound/recorder/aboutWindow.xaml.cs @@ -0,0 +1,62 @@ +/* This file is part of OpenTX Recorder. + * OpenTX Recorder is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + + * OpenTX Recorder is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see . + * + * Copyright 2014 Kjell Kernen */ + +using System; +using System.Collections.Generic; +using System.Diagnostics; +using System.Linq; +using System.Reflection; +using System.Text; +using System.Windows; +using System.Windows.Controls; +using System.Windows.Data; +using System.Windows.Documents; +using System.Windows.Input; +using System.Windows.Media; +using System.Windows.Media.Imaging; +using System.Windows.Shapes; +using System.Windows.Navigation; + + +namespace OpenTXrecorder +{ + public partial class AboutWindow : Window + { + public AboutWindow() + { + InitializeComponent(); + Assembly app = Assembly.GetExecutingAssembly(); + + AssemblyTitleAttribute title = (AssemblyTitleAttribute)app.GetCustomAttributes(typeof(AssemblyTitleAttribute), false)[0]; + AssemblyProductAttribute product = (AssemblyProductAttribute)app.GetCustomAttributes(typeof(AssemblyProductAttribute), false)[0]; + AssemblyCopyrightAttribute copyright = (AssemblyCopyrightAttribute)app.GetCustomAttributes(typeof(AssemblyCopyrightAttribute), false)[0]; + AssemblyCompanyAttribute company = (AssemblyCompanyAttribute)app.GetCustomAttributes(typeof(AssemblyCompanyAttribute), false)[0]; + Version version = app.GetName().Version; + + this.Title = String.Format("About {0}", title.Title); + this.lblProductName.Content = product.Product; + this.lblVersion.Content = String.Format("Version {0}", version.ToString()); + this.lblCopyright.Content = copyright.Copyright.ToString(); + this.lblCompanyName.Content = company.Company; + } + + private void Hyperlink_RequestNavigate(object sender, RequestNavigateEventArgs e) + { + Process.Start(new ProcessStartInfo(e.Uri.AbsoluteUri)); + e.Handled = true; + } + } +} diff --git a/speaker/icon.ico b/sound/recorder/icon.ico similarity index 100% rename from speaker/icon.ico rename to sound/recorder/icon.ico diff --git a/sound/recorder/play.png b/sound/recorder/play.png new file mode 100644 index 0000000000000000000000000000000000000000..15f2da559cf813ff5d2183dfbf77f0860acde253 GIT binary patch literal 4270 zcmV;f5K-@mP)KLZ*U+IBfRsybQWXdwQbLP>6pAqfylh#{fb6;Z(vMMVS~$e@S=j*ftg6;Uhf59&ghTmgWD0l;*T zI709Y^p6lP1rIRMx#05C~cW=H_Aw*bJ-5DT&Z2n+x)QHX^p z00esgV8|mQcmRZ%02D^@S3L16t`O%c004NIvOKvYIYoh62rY33S640`D9%Y2D-rV&neh&#Q1i z007~1e$oCcFS8neI|hJl{-P!B1ZZ9hpmq0)X0i`JwE&>$+E?>%_LC6RbVIkUx0b+_+BaR3cnT7Zv!AJxW zizFb)h!jyGOOZ85F;a?DAXP{m@;!0_IfqH8(HlgRxt7s3}k3K`kFu>>-2Q$QMFfPW!La{h336o>X zu_CMttHv6zR;&ZNiS=X8v3CR#fknUxHUxJ0uoBa_M6WNWeqIg~6QE69c9o#eyhGvpiOA@W-aonk<7r1(?fC{oI5N*U!4 zfg=2N-7=cNnjjOr{yriy6mMFgG#l znCF=fnQv8CDz++o6_Lscl}eQ+l^ZHARH>?_s@|##Rr6KLRFA1%Q+=*RRWnoLsR`7U zt5vFIcfW3@?wFpwUVxrVZ>QdQz32KIeJ}k~{cZZE^+ya? z2D1z#2HOnI7(B%_ac?{wFUQ;QQA1tBKtrWrm0_3Rgps+?Jfqb{jYbcQX~taRB;#$y zZN{S}1|}gUOHJxc?wV3fxuz+mJ4`!F$IZ;mqRrNsHJd##*D~ju=bP7?-?v~|cv>vB zsJ6IeNwVZxrdjT`yl#bBIa#GxRa#xMMy;K#CDyyGyQdMSxlWT#tDe?p!?5wT$+oGt z8L;Kp2HUQ-ZMJ=3XJQv;x5ci*?vuTfeY$;({XGW_huIFR9a(?@3)XSs8O^N5RyOM=TTmp(3=8^+zpz2r)C z^>JO{deZfso3oq3?Wo(Y?l$ge?uXo;%ru`Vo>?<<(8I_>;8Eq#KMS9gFl*neeosSB zfoHYnBQIkwkyowPu(zdms`p{<7e4kra-ZWq<2*OsGTvEV%s0Td$hXT+!*8Bnh2KMe zBmZRodjHV?r+_5^X9J0WL4jKW`}lf%A-|44I@@LTvf1rHjG(ze6+w@Jt%Bvjts!X0 z?2xS?_ve_-kiKB_KiJlZ$9G`c^=E@oNG)mWWaNo-3TIW8)$Hg0Ub-~8?KhvJ>$ z3*&nim@mj(aCxE5!t{lw7O5^0EIO7zOo&c6l<+|iDySBWCGrz@C5{St!X3hAA}`T4 z(TLbXTq+(;@<=L8dXnssyft|w#WSTW<++3>sgS%(4NTpeI-VAqb|7ssJvzNHgOZVu zaYCvgO_R1~>SyL=cFU|~g|hy|Zi}}s9+d~lYqOB71z9Z$wnC=pR9Yz4DhIM>Wmjgu z&56o6maCpC&F##y%G;1PobR9i?GnNg;gYtchD%p19a!eQtZF&3JaKv33gZ<8D~47E ztUS1iwkmDaPpj=$m#%)jCVEY4fnLGNg2A-`YwHVD3gv};>)hAvT~AmqS>Lr``i7kw zJ{5_It`yrBmlc25DBO7E8;5VoznR>Ww5hAaxn$2~(q`%A-YuS64wkBy=9dm`4cXeX z4c}I@?e+FW+b@^RDBHV(wnMq2zdX3SWv9u`%{xC-q*U}&`cyXV(%rRT*Z6MH?i+i& z_B8C(+grT%{XWUQ+f@NoP1R=AW&26{v-dx)iK^-Nmiuj8txj!m?Z*Ss1N{dh4z}01 z)YTo*JycSU)+_5r4#yw9{+;i4Ee$peRgIj+;v;ZGdF1K$3E%e~4LaI(jC-u%2h$&R z9cLXcYC@Xwnns&bn)_Q~Te?roKGD|d-g^8;+aC{{G(1^(O7m37Y1-+6)01cN&y1aw zoqc{T`P^XJqPBbIW6s}d4{z_f5Om?vMgNQEJG?v2T=KYd^0M3I6IZxbny)%vZR&LD zJpPl@Psh8QyPB@KTx+@RdcC!KX7}kEo;S|j^u2lU7XQ}Oo;f|;z4Ll+_r>@1-xl3| zawq-H%e&ckC+@AhPrP6BKT#_XdT7&;F71j}Joy zkC~6lh7E@6o;W@^IpRNZ{ptLtL(gQ-CY~4mqW;US7Zxvm_|@yz&e53Bp_lTPlfP|z zrTyx_>lv@x#=^!PzR7qqF<$gm`|ZJZ+;<)Cqu&ot2z=0000WV@Og>004R=004l4008;_004mL004C`008P>0026e000+nl3&F} z000HqNkl)V`@hWPaDrMAl{!JwQj?7Ip~e_xGRE3uoRS!^ln_cE z`%;QR^B{#j*n)y0f)C!nzVt#xTG}@&tvW55)`}&j)EJo78<{FCX3m-O@BiO>t>wdi z&dJPVX3m+A4GaFuzI=OqYkh0c*|YCq`7p+SnPH3p5y6lF2vEfps&c!kP7%>05nWA0 zV*sFvj;fqf)zd`uXCj&d@IL?$5kLV^hB2;wUp8nE03y0xM7~F$<4Kxa>zwO-hpN__ z5TSQij1i#<=S1aK#@MG-ftgVh z#iEElZmoGlgv+4-SYr`6P6*4-vOK#Z&vTSziPD$#V(Kmg^`D`DLi^8T2w9dP%Q93| z1z-5TkfHBd=jMe603f0ptE&3_`1tq^B0{^}hKTgtJnT?a7-KL#J`PnyyWRdzk|ak| zacaeR^Yiol7iRuqS^8HRjm8bkjHRWe+P&D^;e8OOX&M_FgR>5ct;P4#G&^9e=^tu( zT&ikPmj36XqoX&(7}09A`Zp1kOR`>!v|24xp~C3s=tNoiUjmdFV_=M_0RRf`ixbY; zDOK$sE+Uu30HED&LsgL^$t`8+f7GXmh#(>pF~kRxG)1e`sy!krt(VVfngSq*$VGED zwC=@{BtZz_hgDha5EhsaDs(!X?yD6t;c1WCiw7!5AfVGPva{$?!?UOEOvb9%ZM=`hB#Du zR%Hb;bVUf&9WI2h-&%uEg_`@GpsWU<0@hk;jj8Ly>32@y%)9@>*KXc}ZycJzHP>E) z(wAUnted$CRH1^i4pmj{cPu;!0%DB)32Uwsg)-Nhcjec)T3Y8`dlmn9`)%x>p2qZn z186q4z+rYTBauIW{d3=!Gpn0ZX-f@rJ@pc~CSPpys>0+6K{{=2Y%=bw8Pe|-55IDF4h z?3%m@%ooRovO-lyoQl$VysxG}M8N9+=zatP<}n_uW|oAczWl;n8R` zF#FBJxa-g%TzTbH@V-D%bT-`6l3j2LeMdyTKB(NPD1;R;)+t6Hl%n5d zYhQE5nmJYdRH0uOggA1<;^JqxZely`x%WQo-M0_UITW1^h6&`ASwo*W>t1oH_`gfs zFG^qDzYz_QBb;;i_Oau*>);HU%_fSXK&Zmz8x>WgS^8^H`Go#@@+6q~`t#?{p8_zp zk%STvvOGtqs(v>3nYjCB_INIpL@GV&-hZ&=So1VyK_qAT81PtaA; zEX$rqv+Rs922Mr6%Ez#9NHJix5rucAb?`ML)-xJ z0K&W0x*s^>e#*krF~%tXyH$0Ys*ZIFQ-_Ea0Q}QhJ7=wZRaF;;$)?W-0J~u?sZXP= Q6#xJL07*qoM6N<$f@usCxc~qF literal 0 HcmV?d00001 diff --git a/sound/recorder/record.png b/sound/recorder/record.png new file mode 100644 index 0000000000000000000000000000000000000000..7ee74f7fc2abed31e8a5f4fbe3a390a8d5ffa6f1 GIT binary patch literal 4301 zcmV;;5HjzHP)KLZ*U+IBfRsybQWXdwQbLP>6pAqfylh#{fb6;Z(vMMVS~$e@S=j*ftg6;Uhf59&ghTmgWD0l;*T zI709Y^p6lP1rIRMx#05C~cW=H_Aw*bJ-5DT&Z2n+x)QHX^p z00esgV8|mQcmRZ%02D^@S3L16t`O%c004NIvOKvYIYoh62rY33S640`D9%Y2D-rV&neh&#Q1i z007~1e$oCcFS8neI|hJl{-P!B1ZZ9hpmq0)X0i`JwE&>$+E?>%_LC6RbVIkUx0b+_+BaR3cnT7Zv!AJxW zizFb)h!jyGOOZ85F;a?DAXP{m@;!0_IfqH8(HlgRxt7s3}k3K`kFu>>-2Q$QMFfPW!La{h336o>X zu_CMttHv6zR;&ZNiS=X8v3CR#fknUxHUxJ0uoBa_M6WNWeqIg~6QE69c9o#eyhGvpiOA@W-aonk<7r1(?fC{oI5N*U!4 zfg=2N-7=cNnjjOr{yriy6mMFgG#l znCF=fnQv8CDz++o6_Lscl}eQ+l^ZHARH>?_s@|##Rr6KLRFA1%Q+=*RRWnoLsR`7U zt5vFIcfW3@?wFpwUVxrVZ>QdQz32KIeJ}k~{cZZE^+ya? z2D1z#2HOnI7(B%_ac?{wFUQ;QQA1tBKtrWrm0_3Rgps+?Jfqb{jYbcQX~taRB;#$y zZN{S}1|}gUOHJxc?wV3fxuz+mJ4`!F$IZ;mqRrNsHJd##*D~ju=bP7?-?v~|cv>vB zsJ6IeNwVZxrdjT`yl#bBIa#GxRa#xMMy;K#CDyyGyQdMSxlWT#tDe?p!?5wT$+oGt z8L;Kp2HUQ-ZMJ=3XJQv;x5ci*?vuTfeY$;({XGW_huIFR9a(?@3)XSs8O^N5RyOM=TTmp(3=8^+zpz2r)C z^>JO{deZfso3oq3?Wo(Y?l$ge?uXo;%ru`Vo>?<<(8I_>;8Eq#KMS9gFl*neeosSB zfoHYnBQIkwkyowPu(zdms`p{<7e4kra-ZWq<2*OsGTvEV%s0Td$hXT+!*8Bnh2KMe zBmZRodjHV?r+_5^X9J0WL4jKW`}lf%A-|44I@@LTvf1rHjG(ze6+w@Jt%Bvjts!X0 z?2xS?_ve_-kiKB_KiJlZ$9G`c^=E@oNG)mWWaNo-3TIW8)$Hg0Ub-~8?KhvJ>$ z3*&nim@mj(aCxE5!t{lw7O5^0EIO7zOo&c6l<+|iDySBWCGrz@C5{St!X3hAA}`T4 z(TLbXTq+(;@<=L8dXnssyft|w#WSTW<++3>sgS%(4NTpeI-VAqb|7ssJvzNHgOZVu zaYCvgO_R1~>SyL=cFU|~g|hy|Zi}}s9+d~lYqOB71z9Z$wnC=pR9Yz4DhIM>Wmjgu z&56o6maCpC&F##y%G;1PobR9i?GnNg;gYtchD%p19a!eQtZF&3JaKv33gZ<8D~47E ztUS1iwkmDaPpj=$m#%)jCVEY4fnLGNg2A-`YwHVD3gv};>)hAvT~AmqS>Lr``i7kw zJ{5_It`yrBmlc25DBO7E8;5VoznR>Ww5hAaxn$2~(q`%A-YuS64wkBy=9dm`4cXeX z4c}I@?e+FW+b@^RDBHV(wnMq2zdX3SWv9u`%{xC-q*U}&`cyXV(%rRT*Z6MH?i+i& z_B8C(+grT%{XWUQ+f@NoP1R=AW&26{v-dx)iK^-Nmiuj8txj!m?Z*Ss1N{dh4z}01 z)YTo*JycSU)+_5r4#yw9{+;i4Ee$peRgIj+;v;ZGdF1K$3E%e~4LaI(jC-u%2h$&R z9cLXcYC@Xwnns&bn)_Q~Te?roKGD|d-g^8;+aC{{G(1^(O7m37Y1-+6)01cN&y1aw zoqc{T`P^XJqPBbIW6s}d4{z_f5Om?vMgNQEJG?v2T=KYd^0M3I6IZxbny)%vZR&LD zJpPl@Psh8QyPB@KTx+@RdcC!KX7}kEo;S|j^u2lU7XQ}Oo;f|;z4Ll+_r>@1-xl3| zawq-H%e&ckC+@AhPrP6BKT#_XdT7&;F71j}Joy zkC~6lh7E@6o;W@^IpRNZ{ptLtL(gQ-CY~4mqW;US7Zxvm_|@yz&e53Bp_lTPlfP|z zrTyx_>lv@x#=^!PzR7qqF<$gm`|ZJZ+;<)Cqu&ot2z=0000WV@Og>004R=004l4008;_004mL004C`008P>0026e000+nl3&F} z000H}Nkl=bG7CV04GIX!LLfvIAa*QJ2qcbhlr=#PNC7Du$CeX}#}UZmWNZiQe%wdjQ^lgE z+hem6G@uf5keUKj+qUOh%h>= zu4@L>U{Otf=bZnwnV!B`070XESDbujrZF?;gQu?Rv6|U607L}uJxP)fLLkOSp66Fo z?PuP*!>X}b7Xa@(b*y)2)Zb){?2$&JL0OiRMLFCo%NvpLGX{o@pT!ATmXT!{RaH^s z#b3n9SA7Tz8rJ|IBD<@qdU1Ak_I)Bkx7$Tk$6;Qtm>JGFW@l$HGrHaGTS<}}G~@U+ z=PfKOj9+4mca>%Fa=YEWC&oyx*BgeH|L^cI2!?5DwORxpxYD`uR+?rX^WL2ur+k!4 zGfT>{_-(VvaGqtP zP*q5*Vah(k5E0t#Hr;MFZ)A=8z4!kNgF!`EmfuK{q@CwEF~(t!kE;5r1#kj0P2}B6 zxKk&Q#dE_?+qR>-??pGxL*56qi8xf1JkLpzWTq&JLur|NQUKEFHNqz4;prLz|^kr%uv8e;#Qx)@GlOU`tDcldqFKv=b=v5&x(TV{kzc3TPQDG#3jk<;je4_{3fzp zA0U<`X43(9@oziBPUv!|CaKmnVZ#PC95_h7C@54Z%qFWEy?&n!`woz7oJR+P>2{-H z*a??}B=eu%Pu=gYYSYZ{ z-X9CjyJKdyWZ35EbpT?p^J`C%ZoiX%y>yiRg$q~tK!nD|d3Jo^%iOtdKN=$zw7Uj2An|e%Zh><(?e};_@euV$LafYPuwUd-YXfjCWtYeEB%gT6OptIqW??O|Me28F5fybsV|3mW`s_Zhy#o z|7P&PlcdQ)RaHOfcDqkG=hh~gx<*ITy$aBYEvibh+5CB$WpA1)!PJNrX*3##^CEw& zuImSHb_QI}pz1?-?Y6nwe&m;jnNSqP=>I^~$Qn;{2Aw~d+0I*z!9YaLwOY+DI&t}k z{6atPuUvMv(P$jZ`}t9foww3+5&3t!-TrK=**aaXNZ-n-c+{K6LkN!of4zl6>EC?_ zk2>#PyPo#llmc1^!wo-F)6Uq~dPnlB>wC_*!y$x^3Y?xaN32%zWeDL1X_7wRynEWr zmNe?{8jX{wb^P7zf{6Swgz$h5;d?+nb$nPOc_6&ueK-_c_;J*@x325GzP&54&k~Qu^NjoIRaqCX#>U00000NkvXXu0mjfh@m4F literal 0 HcmV?d00001 diff --git a/sound/recorder/recorder_logo.png b/sound/recorder/recorder_logo.png new file mode 100644 index 0000000000000000000000000000000000000000..5998c34d3041ffa1029d6f9ebdfe20bf3b832692 GIT binary patch literal 14657 zcma*OWmH>D7ch#ul~SNME$&j>S}4%s?oM%ccXuchDefNJT?!QU;BLi&JLDdo_q#vt zpS!+fB_}y+&di?eHW3PPl9*^jXfQA^nBTvBRf2(mYXg2)p&$X@&u#cLzy--jTJkFl z^!1(7QJe_eLAC#;=>$9he*M6T(xtltH<6vc%Zekf!Q*0c@TT~t{eyv_fcgIQi;DZw z$*Nl_o_H_PS(BydM`9fg6cpTK3W{$EUsNW=o?#FXU=?u`XW`k+y6q))#$mQ{zv05? z&<1{>AdIhY-=Rhc3^p+gh^eldQC%lLI)?2H{dby{m3Dh8DCic~wmhS&tNZLK>+%bx z8u@Fk_%?Y-$k%2Kysuxss^IeY^D`l#^)ySr{$u$2f#L)33e|o6{=c{wEl|G>{J*&T zf2TBaLf#THGB#GMF%qYurOg+Q!Y|RRqxqSb=y0*~okYMDBb~=?;N|(z;pxr+_&a(r z5f>SG@o0yRj;<*k4!j6mcdFxu*mFkh%PYNaqOSAaf=`Kh% zvph6B+?&DY#O89SV!coeySTVm)TrKIsj5<@f~sXTGNOkPaI)Og#}>^2mE9hQk$xtv z0!L*ExFuWZ6MZs=X?k3lJD$uHYZTnTdGqECtUru_#nMkDqtR4$LLtxk_2o$|F_ZwY zFsxjYkz`)ygZNUPS`LMWo0EkaGB1Oq{l*!?0Fr$8 zc-&~WPL@b3&*C@esF3@`aKSFSGEWV`Bq{R)_S*lKVv zLWNdC*=)`cao2K}pWkeS=37w|06{2}H~@VcZI+ErS6YgnPh0BEr{Gw-o@xt2;u8~t zj;gxIggme4Ufi~0c#IAvbBkjLSZvlot%nS=rOJapeK;PKGUtSj%^r3V<^NkPVLR=& z=O_WcG`gC;&-FXc+f$!;`ffooY~PoAvlZtV+2)7C@*3xV)3|+g^F-JpPi$G<7vD$F za;vLx*1a#sH2t_eE`DGTeL^uFjQ#U5PEg6R+V5&glHI5uW#*A8`19@QYC?MY5qRCy z#AH#+fkCCjf7!MTlhbr`Lluy&ubTv}C0&6&&G=TE}7NaJ!+aJ$lejEjUFOq3J7d8xB z{hN938WA2oH1$L_U=QiIO@0s%4R?$?(P?$2-y6@=KCBK0Fon=w4Qk$sREleI+#PT;@mB9V%Q0b;v$#Vs_8*S%2^xLVDY1Q2mqCfx~$qR6Ckk3mQQZZ|3I z+6E76b0dmm+v^yJq6CP%+-+Atb**B|vVD@(aRH$UkzZgwIr7eqj>hP6JC5O5qvLXR z{Wnd$fvBd%TBJO<@cVkjX(E#oMdbNv=9|>kQU|c!j-am(bfwkhNXd-)OqP1DYC5^_ z+NUvTx{A;1`Bg@~(Mw}&0OFqPqc>9|n~<2OeA*=~Egb|tYPed!CgJrb(D!~L4@{{U z_t*f|V{|b`2VhbB7QBki(wsBC{x=mlhUn~7Nk zozfnx>lWe@a_%npXA^220PVP4+g23^Hjzu}dU<&%{nRqwI$Qd8_=B);=j=MY4MX*3 z4}eM8?AF==Dc{$+0`#I>CV#GMI(K{RE9lOBr!~fdQco>7a1EAo934*79T|JUIY*CA zfIw^m`mf1kS*{?7fB(u!%StAVBSak^AP8TeejWSqVqNhpd&O$2OJ9nUt6xf=+OO_7PBVljv=Lpw$Zvd?%+P2cM`AoA#hD$)z>?O zP|?tQ;Nx3_RJ%f-Z&U7^C=mcR&lgXKxG24T2+km}jyxIt@ zjUndwz{&ac7o+;iNK2`96APf8|A+!6_7zm^Mr*z!^#!xTg_`_zWrtrT^akYvfAR70 zjn23JRABm=&lF+0Le_ld*H!^k17`6p6BY0%8qq%pxm+4Y;jG@={pEfNzwF|o;PtF> ziAK#9pC70p6nymO>Hg9KDaaZy2@4%wxB4$_0J8MlDT%nPhyLHy?Yf>_OSfGc<^jv+ z+|sC>D~cFR#8uW$aYEetd3+L(#jQ)(S1!jlbOTJOMyIz&X|D6t!Ib-15AsO;SbzW5 zSHsTE&c2T^-8s>AH7)INL-K)<5&dYsvd-t9>FX~2Lv>M<#aSCq^o-ebZ{YA3r z@u{gO^w5U{2M33P)i$2my1Gr*Hfao5QIw~v8F^pXzwaz{SW?!Z<7(rs7tB;WYp?DL zT6%Sx)4m)AF?WTGkSD-~;;ydT7=53$w1`Z{eut3z-o1JQLlYB&fPWC#XZ<}E(30bb zn7tA6L}_VhXPzCt&)QwSKHax&Q+eXYtFMlZq(k~@cft2W`{!%$HlY5P8YJgwxwzhy zmX_{fDT|^2mWTF(T=e3kIiW=NZHpBcbiDZAb2U3{r&&T?MlVnIjfkZBlS0s^%Y>Aa z!MZ&IKsy;z{$~tdR{Rhp8+ZW#wH+797#!8*gI}+PGitjS+q_ z$3em*3RbJs%JsP1GheKw2If>ORidV%qUr`52U=R>HaCa_fY$j+?J!JY?hU|SNd{C(7f2jaq+%seX(Roj`~Aseu7(Nri(a%0Im1IPV9Zk#0@6qj(SVO1!8j8fxJ? z44ZCacLf8yjRJ@1^FiGGSTRu*I3g;ZZq){mXnL8=uRY%d+GV_UD*Bl4+YgRxH^)lmjtUdDNzt_~k3>XTR_5k(q<54& zxVS9;&^-Bwhy6u2;?|j0&Gl;d$ZVh4kP5Kq9I&j{KScJ&3tmwb)G3w zsHyslWWdv6i;Xq7tIf>_%B+ofgRI>SOqL zF0}lj8Eq-Ra8SOz3hjF)>@xK37Pd2=$#uUR=6Q1z$*kx5ILfBI6n*q!4JV% zNNPdlY#Qqa_9&iA%UH1do3p9yxSPW}^@g&jST;=3Bhd4t{LMIuv+7!T;AkRsR~IfM zR&ve91Ga;fgwF#Z`{W5Dkz2OcFYYPj-rq2V(DlS39R3}GPwwAak5G;cRlWA}b)K{S zNLuUrQTCI8jYa8fOiw;+s4p*#b*jOUS#vNt<736wa)!zc*A`~<;7+G~^fAOWxC%M_ znA6L)kIRWR%jYVQmBF%2wxV;*W${W`jo7Yh!67(wXZQvS(}tqUm;7#Rf7!J3NgF+$g8kw!XKklLk6Eq!Zo2OId~JuLUhSIeh4~z3I)n~ou_KO< zRbDrei_luHyO1m2&3JdLNf#%^q!*9d=GXmgwbr zo;xhOclO!ceXKB7|5Ws1!{7+{D_;CNvlrBvp~;h{JJnpUM9s^4Md3^SBv3Y>iuup@ zk~A9!jvYi;U$%s%ZMz(}-50yvax+oWV{a}L?I=!3&yT9_42AQ!-P;^5a;uFebdBi! z2=hqP0#HBROP+Xt|0?%i>U~q1p__GtVg%u;?$Lbx)kB4 zb!2Gl0DX)Nt28a*i-LeU=D3yrikH(=g%KwZiK1nvC(IKWR}n@@YH^-rjdjlk47Jjt z6Hw{dFUeA>%t@Dp8M~1)cBb)N50Gp}_F(fs{lm0{NZx=cVd_h!;g)Te@f!!#X=|_= z*Bam1xp+olMv0+P;!x*T8+Ido60D-^V|f#zzTs2ZXLX>E50Acsx6L2h7Y*XH_S0lk zSW>fzT1R>g4K6_#B#*1o>-7C|bO(M1jZEbSQ?$T#o}RlbAko7RI-H|a95s#K{97Md z>H8ZBOAOG8uH9Bt%gTHG$ZKZVu@@Y!c6Ze(f39#8CTH~|CUgMmG~ueBr*snR^t}IE zj(m3W%T7{evbpp0`arcyU4z_gWSBX@O`fc5P~8mvc+!*bDE3d0HV^wTuA)1at!)ai z$juA;)`*d9Q_I0jwfq8!{AzzIC4utR??$bTIT8zHy#N0Qux=%pH-nH>no3NGD5eQR$VH{g^*2 z{A8!kV>Jt5%1FqB2$V!Rg+=HQaaDP#sUQ#bfR*&@#sVI;-rr^P%Ogt2oVHF0%fa!#AF9cPVjfpvlePMbd-qniQl z+&)HIYf-4}4}FSXUEfQ_dTc1J3^1vd)GwnGFj`^akNygEm=_SUgHoYme=K_#^Z;i; zwjzq|z3SfeYTuWAt;}rpkNcS6dBQK4hCYSYN+-AVw-TK8ST;4&}Mr=(xneXH- ze5fu%VV=xnw}|2=oc=>Q39g(|#qMwlZk1Ikm0CFK;pGc-)ZN_~VHm1TuN&IPkuv>I z2lZ&N(x0Rc!deV)%@{ma$9$({sKfC14z8y(g^A#zl zgfpMqR=im2%Wn{8u5}NQOCog&fr-YkB`$! zDQ7Fc>#7uZ*jy+ETuGuB98@VnKIvi?#@nM3V359$%44*dvh3JVskjlt<-+8^@O=}N zMVF&cQD^L~rW}IzCs2rb?<`%%;X}=m?ZbzFkbJ8ddo#C`-iaD>#5-P9ZB?Wwo0b&V z-rL@tqM!Y%aV014J=!hyqJDc)&D=e(~UPcS5A zk!O_K=lIt)W4=TP5pSv+n*q2lbA2ts!eZv7{ZIJT1uot1pzERsp3U4Sa?wYk6K0Vv zH(h6ffhzJi%rxRBVUZX9crTcSqFJ;EZhb4=t?TE_M(lIoqsZ6Dfwk&_GPyS_Ar;Xh zi)4I}{C6`OOh_+-&?}C%6<%#7Q;sxCjrI*ow2+V`iY&5|6x{&?hd zmfR#LHjplxl_~KUPj4j+#z7fqnpU4}hfA4no}H$j@m_v-xUEXy7kcOLc5B0T8S^}u z_ayt#hG&bmKmWP-q=wt)#KO-?qHia(L@_sXccwe@EUSAiTR-ODe5!=4298YQ1_u8` zH&~1otEaqUhE`reO7C+caZE9f#9oAq^mtWO#hy#{;K0fU zNjb7FqrrskzreFXurQ~VuIgWt-uHntXJ8i2PeSR?!W>l$3|iwb?{`=xHw zZG?H#3h_40lXy0ESnQX(4U6TA!HH+zP@LXcV~(T%Y2i+Ub4dSo*t1BI2UAn1gq$H3 z5)+Ake?&xTgK@G84;8&4S0}@gs@48NYXhwrwnP<)&7mL=eHIwKl_bl~#k3aa#8h3Y z3XBqICDgK-36Mew;Q#J&CX;UVdH#%n)zU{{WVXpi>u4*>8&Co*wND^Qzs4%UU)o>v zNV;dPs3JpIHS`o<@N!;yHqlK#WiPI%$Vbf+v2)PagC%kB^AGf@1jgkB*K4Z`_D{0H z&>$+^kLl}!sE`OpsE?i@*_sZN2A7rw|28z4M^GiI{MDq544VTy7M_I@;}Ql=TavRi zWO?wJ!9EeTFk8G=lQQ(Zy^rn0(${!|i_JRo+e4v5_^oDrcz0v^oNyiPLyKQNt)3>_ zBtbYo;r;LL2UIo_ zyt=SMCKa}(Cqqkyf2C13t(Eq_7um&jc9GYc#i~n11Ro$oTkz22Jd#_o7AH4FlWX0?-&@HALp##` z_2muI3%|MfRfHT5eTXS@S<=yY@V+vJb-pUqF4J!!akxC+djzyDRGhTt^c zh=7eemz+m#9bO=p4)+x!BZ8-#1Mh-D=`orAtsXwQ=*ukf|4FVDalAk=qU{&8F!|29 z@zy4zqjo89oglT$EVuEeR#lakq3i?E3rpA-~;j3Q< z58_~s6Dz<3WOLy>zUkQAd0_7>LPJiXBdW()QaF8?s+SexFa zDflJR7?gqQ{A@uYMopow{iro#{F~M;D_T>)Y_YQ{3aSyU&mooVvC%OONh9jbN$M^7 zn9g*G`Q(+S5~S*9d+O*0=94KGF)hBuagFjDGu`66^~wL)1iNnw9kpX5AMv zKSDZI#-b0=!5*&fT`Mtgy*}-rSu8K;p3KLCHT;Hmlxy!ej~DE&S%p2c{#eVW;J}gX zqD~Ma_FFJc+#jt$PF+UXsl{n?MeCvZZjbmV=Fi`c{7-N5I-;tdx*ccwzI*ZQF`bg1dVdC+?RDwFA6h}__yc5il?*HP@@?1b{Bg8Oz|=J zbF=`B0qX&x)&0NEX-<74PSK~VE zY)6;ojdO`Po^(-9ROFj{h_IQxhHiXhBfj@M>aOv4l;br+9v?|~#vi5+Q+|`lT|#7` zrT`jCvfuTO!STNUc4I(QlcUxQ-hum*$~noR#N`;}cK6CBgHxR$G3HsFabNwpd0J^Xpwu z0dCBdAC|;6WsN;sBKQJ(8G=A0USDo&JB40|ce8hlx$2dnmRju#cWUL3t&eT2WwkQ3 z6YC$mdROAUvUn_~3{;V}U&tYDDhoF8D=>_YAi$fUwNAx(bE|-5Ts?9GbNst_5&i&{ z#?D~MzjL`LJqKxr2DKxGwNP_2Pl_Pdz#SGyi1;Gwt}}dl%Oi&|5i0Y|JXM?BX7rFf zmcK|tz2aYrJfPg%6ygjor^fz_j6aOfN3nh#F@IWus7G7afwIgiN!7tm?5ALdqE7Me z(Q?t@^i{`f?SJf#3G4fug{~M_+n0#nm<(j;rXPGH0#&jQ#$afBy18V89<$~O-&DD& z-^44>{t{v>6o<7$3S+%<`GUrCNHyQH%f&LdK@;TQQdu5V{J`E;@;RAy1d=k7AS zH$5Apj1mCvflT5e^OyZ^(aV~Z`}uWNRgf=f#1 zHF?$^dZ5&X4v>KSka{jix|OLkEMGk)Hp7c?JH#j24Rb>lkGadLFI8hs@yjT|B;T&p zj<^ZzoH#6ZM-rSvmN`e>&%O1kVWv0cq9iE7aroxvU4b9~V) zm*!$TGR1u0?km}KWHW}w1@B0DN>YEB0p7H58QYPLcXA!?>0I%l^c&N3=t$x^miWnj zGMI6>9Hgv&^GO>UJsPgP^;9)<_2PH;7jYmHvh?(oY+8Nw$ zVlmU5mad~fyn6N-m^0bf#Y#gQP}>3w6O`Z>N$#!u6LRrccI0csh68i2Wa6lZ2nRKK z5lEYn%|atAVaM<}*CfsYH>7ffGC;`sTLzwU2#z^h$Cs}pRg3InvFK+sUL6@6T_ua9 zr^7_y8B5X!>2RlixLA#**2Jw-=}KJA?OzP*?@Gk`Nd?S|QNALMOvOJI*f1th62*U% z7WtJ|?(e$n4DSqYiKZ{*q%~=C?ZEhy@F>|&;>61?kX%ziIc58IYEQ5Jk}xa23rk=B zmOo4L8iTk<86qhf{2YiaSI6o`J`UY@3Kw(@UH#1EY5Z;@M5v>UNP&PMJlLs6i})`L z3}NqUFF>)yCjKOk<+8B8FGB!HmKm*J3w-x@MP>#gT!a$WTF z=mUHGEn9$`-miHpZ{t;>d{i^nYiTLAqd^z6cZqCo^o^+5!@E~~F8$i-ynJD46dfd^DMZySWfh>T#tb1a1GnQQ*x{BW%e zEQgwn+j*YjMP$Yd4eW14yA_ap|K1@&tlg1kri;X#`)v0hiFt|f$_E)$w2ne8MK8ij zq$lBpuF4bATn%^KSs9ZaZ#Hg^*J}(W-~=ybKE|dGk6ZrQW=QvRkP#EuqaL5m4_4dO?3gJ|WCA`E*DF z=4yzk&$o!}!iNss!@CsCMwHy_2Skydi5yt!ev%36pqgKcE9|Ex*AE2zMv4i6&Ka|>X1J@L~sg#P;n6>jo|K$@BWIdGSFK3 zBpt@2K{_PqEz)~M(rATU$$agGmCYM%c|P~FHUXs1))WoFu zV79#l{WkC<4j^(nP3P*#))ca&ogcV7$sRnIOQ`!Wcb42I+kigPB!@jJX58Z-c$0X~ zK7+W{J=$kO*9S4_ZJ5`Xc0yI6Df9>6CU>W0*vR$^RVMb-j^Ri8DhuoLS?v1m@((X@ zGE;ICl?r7aXpt>7Av>V#T=m&@#dW0{h4 z%T`}6s0}8q*H_N4weQ+@k%f9QLR>&|@1<{V8t6SQ75?4K6Xnnrn>S7~@*!Z&k7{2+_z`9k+E&l~g^Awqt z5&_6Lo|zW&uwM)&wD)8MvX&rH!@@WQARK#YYQehW*{^QG85vGUS?IxDzY7ArJCv)` zc3yf)<(EbYaCZ|FKDhYOpR(QTvMnRx&eU#^n;&b@i{vDfFGbJvuYrn=lk=%=TOF}3y?apU^K09XPhH@0%*P`nEKP<53xrRE{3w8d%FlXEoxvFyR@&-%E7QU>J z6ovhyW2c{?5;s1&HhYNqpZQMtY#+)8mLeJ)#8!z(lzDFUPk2;AJNdal+s*!v$04@jYG`9~|DB2WUII^JvU)qXx#0(n*%WM)YmCP#v%A%H72lYYO( z=f0bw9-olCdE3cYcs3@xo}(tpyk_v;mDGR;rp*)?*X*h4SGq7oj^BP1q8icDi9x}B z;Ug(ll2YoT3(X-dIPSnvWZq@ug=; zbqpxQ!YRb###$H({ITHDt-NB3S;HMX|2QuWy(-6Obv^i0oLD*_YZcSbR1tH)aeV1Q zuH5li6ve!<#%WTnzxi0#RnXWRX>0Yo@I`MO(MR?+-mDL7WRrq z_k4F-&LCWU`P%r;%a@%<+8{N%s%)>0(p;bc#e43#yxKBbxaIV%j@mYd@-mL-MrI6z zx0BQ%GC?G^zca(92=x3?`pjOxs1T|v5ls;m0Efw^yi_+7TquARZVk&7#ag%sfcPBm z@nJ?~d;X-?*1cp-?2UG)a+4gFkeUV%6PF+qV9QFbBl$2dH<4X?b_=XT4WIuSdE(LA z{gX7NEQ5)9Myd>uFF*i0$7ZfEIpuL!m~rYl5R^PtDd?ttuNR0*Lp-HSF4#!69O+ka zA6AMyVea7GJ0x*@oKD{H!#-Izmh8oF?~kigC&;wG>_=WD6pW9`!^^xSucU@!gUP+tl) z#eQ>!SoqIYI)1*Zs7+VX+-qk3=$drTH5;9N*v}TC<4BvNROHp{9pEP0#r2xMuPta7 z03Sx@yOE2xS)N1|3vhbXb(#GW`l4@dFk7ZL#5&5Oy4Ud5%6MSiH2An-wo}WCr2Uct z)Ulx@ExKRc)sDuHovA5s{!(-+`>So9i1Fd;&E%URg5sUOJPkg|32C;4Fg3E>3%xF* z@SAPV>xT0;n!f8ld}5Z%I?F#aVyx>y8~@${y7Z)S9%@Ubv+s za{cmOH0HhDyJ9Q_$Z-k0%g(+Kv9laq&MOGTFSV+c2j&I@HlWtCqdqobw3GxZ_n!JINpSOh5 z&L|9j)M}}M?_-}^(LsHf*O5gu%NZ^2%V*S$fdG5x<_A0sFhVr{k|tFkb6)WF=sG$HA-o@Sfk9 z-$KgL*vn@QedK|Ov*Fq5P$%e7do8YMzANNgU-c2ifDF7l{O5qW8);waTtSj@;%`!n zS1+wRoyRYQr6+)tW5qRk;u-sq61O9_JXYTGKTKtl{W&_)W4(kx*HfTjb4?YE))@cN zcwSy>HJXK{MYaaJTszB@scUnsCTc!|AA`HcFl{BWLw$y?H;he&RHY34)_lFM+v@a= ziEdWeFl;#%Af7wv^d{@^KHpy494BLq=P~P~yxoN^yEGS-MI8FRKHU!a1v#z&jIKS6 zWKpSj@@&cLy=AWuyImY4VmQ1<-<-clS`@n(BWJfE()CPB$C-)1HOQvMJM{f?CnTq) zjVS&e*HSphmTh!d2pfpPKMC0#TdB8)@<+IkfRz>XXxnLruOF>A=Z$(pQ7LZ&rM{b5 zryE-SVr3lvMY>y>6qtk?Q^ez_ljik{fLYj5aYg#bZjt6IwE>V2jO8t=%M=qBFP|r} zkesn!zr784YM>4FpYG`(z|!PE(Cf1*BeSebaMjl8UzG<;nZ$DiMUt59xFSr^Wd?#W zUh_e1^+1UTPN!vYqe{a+v1* zH{`S8?aY~cqHkK(q%0ND#?s1Yl8~&IB+oCCIV^U?yX5v*lWvquiBRwERU*k1-8qUgh znhRVdS3#1--J_^?%_F)b#Hx6LzsJg5){Yi8+2LBK`%~5wq239irrF<4>br??XzH3= zqLl2}#vg2sVK;^>Je`v#9m~q)=i$a*>8$7>j*17p zxvi?R-ky15Z3oD-ml*%q!$3IMkdXgTXFChk&3)MfhylyVG}deIM4(srfIEAUq^;Ji z2DYiETO2;>=x3Veo#!B!In5@>Fy+a#{eGXg;7cpdh$b$7m?4-R^mHsGy~pZP+9zF- zuFjfbYRC!x9n$^}YjpX5t%%m6( z){qvZ6vVm=ZY3TGqqeyYgO%3}wBW6WSAHzIW=_5!^Lh7t=a4ten*jSTX>z!NH*~|@1|@ag?|EIm;S@$1 zM2`&{a|iE(1>?-r1mFJ5JphV^CA_6ZLnmJO?_)OD1&fX*0o&9QUnJJM_n;*81tmZV z3JPAY^)=47se|15#c}5i z9Fxv^X8XRG`oqX%z96u|2mE7A9B!d@)|aObNX$ek-rH!1#BtVNuW!r4tkc#Tc37nM zvVFQn9?gGFQ|*WW-8SeqO#VPQCKjK>#F&)AFa426I$5GBMF%^7Db{GAaN`a1q3#3n z7FiK27?$8lk4CrHk~crMls?`&W*PB2!A9YTUgUz~F?SU)5;In%zsAph7Bf?)iLOOQ zp{uzlFt2qeAhgGLaO^f6UEqdaj2dPN-pwWbP|)9?uM=f^*}B;1AM_TaNQ<>Q zeDh;_z=KCiNq9p4Mv$e<`Ar`S;yTnY|xgHX%q~4(A-s6= z-MM0l-Dt#7VhLk5TZ{bB={8LKKsUVx|NGm-Y7U>mk3k?DIPlXxQS_Z*u#jQ@kB^#b zXRBNJ_-sjrWozH)6L8Z50dE1Vw6&;##S_`!L^_;|Jcinj$#9#bzyP{?%38x?Rz;oN z22}8=B&c5nB8#RR~RQ6%!Q)W!|I?e~%@(WQhnCM}F!1eWrp zF}dql*N>*#RD2 zfqcX<|4g0p8`T%aKJN@+52!Sq>bpvYM7*>1vwEJ|jT3FBKD$^-ktYTjN}dV1q+hyD zh#g+3=-l7`TJUyu`g|C+_%HEE*YIqK6~yI3`tag=**ykZx=+ogXHTNd*<`f27UF)A z0-iKfLmq0PZXG)cm3Q+ds<8phx5|i_jA9hO5xrYo>wGyn8XB6Y-q9epyX3X4a5L7( z6bYc{bkhgA>yB63z!xVp)YO!;w6s?fP~BM$m|6|BPVq4?(g<%msMhu%)o4=vZjM|i)K{3Z)se(VT$2xRR;#^w~_*iPSq2* zei6hgmN0G*MjIa0Nm)Z*;T)@YUF4X8Kn?fL{KUEn z=>1b zQy7*$Zz3!q50T(&Bm3)pXWHX5OPTERE;SsO6@Tx@x&OgaTHg!#n5)BmeJBABa!$Ek zp7$>UQ5@ABzMc%}W63PvVEkTEo@5in73BaoFoG1UuCd-$4(n32_5HOAH&mBjz^93Y zsMA2K3N)HD+4YWEr$qtIwOtt>vH5g+#PWZuo7ua#egW6#N~;rum|YJ;J#}Nmk-mmj zcOq-TOO(MnknOL%c9a6Mg-ngX9H-8HhH-2}5Hx$*zeU6`el~-J$@*eGO7-Qxz5fsa z+pAAi!@cH_a1=&f_>gA@@$u$lpa2 z^_YF{5e#(9U?K#&{u@L*b!Cr9=QWBO8mC#d z2O2gb?M++3{=fA+Bh?u3euUN+x~Wq$4!Ksy{cj$RJQzFLs_TwcB7gLF$gk&5hqqif zHWP+rxo97Ja1b?pOUBp8^brZ0~~RjYIcCPUw+9x*pvKaz7A^{%^&M zoaJuBk5fR>JD4(uCaJ4!;Vurg*>J)>G!!il5uWuw_6il@F^K+jtckmT7|!P#D#c1M zDDAa3s0womi$J^nA2L_jCR&@?qI$DQSqqROQMXzZ#8$?uUyny& zv>8fMp}Vu*EY+QBz(9VlN1wMEPN@8VQ4v5~Or4ARj|uxYk7My~MoS;}e|A33)kk&YHi2w#|>a4%-}yn&LsSgI_CI0W4H{%0NQoZ zbtb)z$A$?Jg(QRKW-Y3WUvK?2Ux+kH=DN{_I0A>bSt+CjbvPn}^4NWfpyB zh_KDIx@?U^up%@IXvVu9LKB4D)cV}bhrcG; zCv4+96yi}f$zeS1eC0d(EHd6VE1$j|mk zK!6xH1`wt+Kc+}bOdJIq*jQ>^=a(1rHS2QT3$d(J*vcoC z#_z_-x#v)lYQ0z8;Bh!7jeH!Cjl5{qg^T*0GyS4j3vfysd3cYx(-)k5{<&G5#_+}1 zF{sCRSqrl-o^{a4od%59=$ozB8s6N|Qel2U@i0U4}&+1uL`MKE_&N@e0Yx=xJ+0)O-p1v^aB5l2M zrq7#wK00Prr-c{vT{ugAaK`k7v-+Nqy9jWHh=49jA&=2*(r271Sad+}XO`kwB z#=VCAay81WDEFYOMOjz(bBUADg5RV2^fV^pEZ8r)PUB86-&bL#GmL3nX-sB`G40Mb zrlV_2=h4RWxC^Dsm_EIY={wSxf%h0Q1UTeR#*Elx%*gG=jLAX4=f?d8WwtQ~gDDQ( zXv`5P6K^%`q`%-K&HGaudLfI&CwdZYaG_1`Rf$ zk&{j6Ae3?aO=!Y!6FU4iCiL5U6Pnn_gkW}|DP2tH)F~!(Ml+Oh6PnY4-8A1)qBZ*YU=CC|{V+o7b4oTWIsQ zq9*iq3QB7f{Lb4WQI15Jijs|T5z5slx1&6SvJT}Plr1RVp+rsSofMSTC_Pa|q8y1b z6(t+xB9yC9Zbx|tWgW^pC|gjzLy4l_rJ%G%>4`EDeJTeY=;F;_0Vju4Bha%}5jPgV@#q+GzTj47_xlsOfE*;FW8c9;UfxyH2I)YFf$}+jKT<V^~Lc>Z?RH=3CqKnH`fo{CLOZ_jlx zXzL@;$n+IxX!?2hOor(%&;TI6nQjIEBPPuZ1a8DoVUT=SK&~al3=FleAow@+L=DnSk2Du3?$ZffxMrmKd~;6MF+rW(BMJaGsO z{-e_qXz*X07Dt2May$+Gg`R5gcI=uI8vLfAYVfwTB#s9EQga&o*F!Pug26{7`vyPX zsKH-NgI`L6zk&w8m=$^o4L&-S2EV5h4SszB4SuO_@JG?$cV*Jx^FlQEnKby_&1mo| ze1jiDga0_520w!a|3y3vemV{Q^LSeN>4eQ{@Fif#0rkA(Bm`IaQ?=3lQkQuqCw06& z;QtX0_R{c3tlvc*sP+9C<@$o_{Av49PU_1BgNQN4v0O9S*pBPriREl_y^seicfGJT z!Z^0Zaa}LT8*H3h*Gu*W87I&6QoMo2+30$yAZz)VG_SvL z3SBSV>t~#N*K6SQHO^|+%K+l*4ZS`BjlAB*b-c!2FZ~;hy`K6vn|M8pQ{j3|z2G{3 zhWczO?LK6ywEL`xwtMmlwtI`W*zUc)V!KZ$X1kwZvEBc~b`Racc8|M@?Vhlj?VkK3 z+db(ywtM^|Z1?agw)<^t_iNbh=ds<7mi9-x_b>Cb-CKPv?H>P}i55p~^f)un*ab1i z4Z8{GJ9eSvxFI)9zEN!BRU@yfiRI#?beB%XDzx#crPsk&+vHUnubr_iylCgOF?KmR zaF*A~*fE^xT9=di{uc@&&;;rspWBdWU=;<}YTX@mi%g~lMR;eZ7q2IVdtqa5!-)}INPG1t&o=nNXiS6f+_*Hj$6r%B zHtc!msTbaaz8Xm!I4x(@JKw`_`kH9csJSaXh`~B~npmTwu6!*53qXGj4f(?xHv4PR z#FabQUy~=TDrJ8iep@m7Yx9L0*M>oJ=> z?XRQWWPfdWkKbS8=NGfTj@aO7e@$8Hu)mHi@U*`sFZ26r-%mX0uk#|(U!U^(Yp!YP zh8)|Dhwb#8!?@5;FY}x(~Ew1+i}E&Fi0F3 zQOq5N@4>7hCTkU0nht*3?IOE2^c-#L7#}hgA6JXy&=ZIr;>npH~H7{ z2WChWo#03n9Uj#x8dbsX!)L}cHunjiw2^)TbRkV~BOaMD2JGy$Fiun+n9Yp68^6*G zPfi&W_P~SFsdT+wUL!r$$0i1meZ2kaf$^!y+^Mdka0y+j=? z4#h*%DRsSJ@(jfv8t%pEvvdTWrE&oy1pHoOP z8~eE9shP!{xZYDUOPTv6%`D-pB2UdMeCn4pvtvJ{ne}{;W|n?!jAl0FTbfzsvoy0) zzUR}v#UnJcV|IFKW(haY%-X(5GdpxAp7}7dOB|Y6(tWI=Ca==Wx@@7DjoO8gD$MLR zl{B-75jC?DEsOx1Q|;PjmSXIJh~m>c*`o!l; zO&`-p&cqC!=<>p@UMO0v!vR@=>0(-AX}~s}OeWBR_qZLfLY>F>jXVfFWVy(K_qY>q zx4&9sSFaWo`Kv{izgpzLc`U0$yK&3CfKhmjdjlQ1jU9Cx%SsSeh>Cx(LKO8q#W8Owyn8sQ;FVFNf|V^v1;z8@NCh7qL@KyFomBAUIIbhPH>8jX zHV-8gM9(G_JdjQ*__QafpnNi^;18sNyAwzSFEt_+Y?7G<7K@8|k_vYACl%}+N-8KB zO)4lKODZTCL@LV)ZaGzwY3e@DqgBp=!g_2UPM_ep!Wz%Tbwy}&Ow<1g^b&2WKV zZpM-Ye&LKyc{54S8)EP`##k5z+wh^p$>?sQ62A`7hMFV{d2H~1ijKGjsa6Qeo&hEu zCuBg_K!$&Lrmty;6Xp6ekT-gp#yEELp&;1PG{fJ}M+2a{X(315pee$8T}>;2E&%yz zXB{|3@U&=yGipsDn~@onEwUN4Cdg*gnjo7I zYf{;aS`%b5VofTWQEP&1My6Q~WHV|_kj=z^ny#ibEu}SGL2Ft}YdVG21lf#Q z6J#@LO_0r~H7)h6=_pzgWHV|_kj;o0xie`^kjbSBP99P7Ri`2s*6(^)9LB2CYBS6v%2E`bu!Gcr;y7ihxC@Kp;g zc&JvXapHvqbCjo<4f~VFmkmp+7S?vfaa5;A_~2gE*WovEeIH3oCq{T@8>U2k@lnfP z_QErd0@^6&M0ohgs6n3KRLoY--W|+^L>s%&cZXE??hwm&huFS5#PQuBaD-rd;dnXW zaXMHE>IBUZ)Cu}5-Ddx=pR@|WcB;IpjcYEO+$*fM6Dxo1hRLnfc&viIPHjrLsDy9>v_5bt!Epa^ddBmOsDnS zl0fTuwI!|Rn<2EGvO`%b(GzGr&K&J2i)lR#^58NMMxo0fB*R+q)1p7g*a9Fbe!vKT zjIm{)Ato-oR_-NX zJ?b>2o|oV%f4Vl>U+VIoi*M5*vuRz=OS(ROL3RaP6-yNg62dc~>lp~>kp|er21sgaFtk8auXy_qaEuW~IR<259dY! zi$Pr@`L=+>oppel5uX;2A8W7vk$m_on#!jH#J$&6oR5xz9A+Y>5r+ycASbxD{kPqQ zqED*NO#38!X4)s=Gt)i^pBek)d`ub8C$DCoT*^Lq1^eV;_Q_M&C*d>GJ_(m;{_iut*zYeer%01$qQ3tK1 z4j|~x^xBIm-1XXucvzxqI!N8+L#8ZsC-qvmx2)2y*Bo<;7gRSoLQvg5W3T`3_wLeA za>Eww`W-s$+-slw+=h%7CXqDw+_gJMC!tX{eoHzD9hFBq8S)}b38po*h;-8US<*@P z3d9J(5*Lt8&L^E*PdbTvo^;Y=JL%+@{~n#3N;+w^n{<-!I_YFNE);Zf2`(Equ?RN- zItgEndjg$gJV847-B!{`?7+E2l+i4+_rWKgbLHPY zjd?ldW=vpxmp5i7^n4>}m8it39pE^EZZuX~JxUE}F&9vD>dX0W=w-}ta8_av@Exo$ z$^TLO9}*JBTv?b?p%M_5lcQ>Z!y}szB~%c06Y>aq36+Ex!T+BBE46+ae>Pg@ugkSK zSpKfLNN};nLoDVE=w0wXM?T~h>;KhtAadF&tt3&^`gJu5THC!iMCujRB-YMCl88kz zumHqsfGjO8oCrakOLYcy&Tjjw?&sr_RNPhMma4|Im$`%u0Ca?2`v3X*f1dttH4<)_ zEdQ;P{|Yhg0k^CXZs{s96^>b<|98j#uF8s3#2pa$nmZ;?-*U10G+A6%pO3DU+Tgo#O-8)&KgUBr}kXsHTx2y-Z{JRN7;G2?cTA(Kdhv4pmh8}25 zbUxrS1)Jay-1-3iwfI*S!6k_^E?*Iht9Ryue}n$*mgsx`Zk_!npAYK$mrYC*)b}r3 z-_2-lM-Ubh9wmGO0Fh*nGx`vIOPE8rl5ij4Wx{&GCxkBv+X*EEi{Mj06^}{@dk9+z z8wjrvo*>*oSVEXhID*g_06vMuE4o{FFAoteBKWu4Sdab_e#i;W^$@F4k4sKm9&{hU zRsIxhwExuQKTmg+lbVi{mks~lCHM>fO6_$wPLcRS;TLe}7Z6`*S9K?v+d!ul@AHxu!ARS zt4OT^Z~>X}m5u@u(%VLk#NmshPEb+flbr=50Rj>sAj^dy4!a;(v9ptiE9r_uob3uX zk1Ijj07;S1TphlG_}T6Pl4+=!COiX=wi8IUuaj)Yl5E$KY_n{V z?R6yEwC@$&vq-idk!<^sY_B8P#uX{LN04mqC)p;IDdMcM?5%{a0btnyWZ6Fu-Xz(k z2nC}74<^gz5MEG{brQ-+w!=uT*@Qn6-Xz(E$`sws%VKu+8x8s}gkg@>rWis3dHBCo7GNQ?&RxdO<(`irPb0uEFfR)Og3-g2fA z>gwu*4%O+vB|Ufv^w<*KU_+qY1sH)SLc$&jAl#NP2npY-&LAP-5mAUKBoTQ88VgA^ zQ3dHmTRrZep@T6fG$f+Xf^ega2!J|4lLu+_VXsA1+ zL?TlX#Fh2HiV=RIr+^J;B1aOXg`bCf93L%E#94{q!nO4l0h6ndUHD8Nl{Hl=;;cG? ze2|%!xLXQ1J^E31OBC}W(Mjbi;s^ShpfQ5R2rL6+@S~Oyvp4*8&JggFwP)3oM#@vx z&ZP&%DNkAMi<1+Tr|gRByC_fDRX4O$p0Xo1wmEJoO=Y>Ll{i z&P4LmRphBoEoth`Bt3vvP-gb9zy zNqiY>9NguvsV%ohK6(1j7fm~8K)1F{Q^KiDGrJ6*bk-m5USEzuo|}j}jfOfN{ijzW zI-<0a4qCE--L~_hx7lrb-?&>f6n4_o_b}E)xBX2XyY0wV*lj0mX19$$`+MXmMz?MG zAiM4Hd)RH;yv%MJcOCK_quWlYVz(W&lijvUA-iqc&Fr=D zJ9gVaW!i0zvZdS3)owdjChRF<8|c%TOdCnFQ(-eO!!$7=n26@oE|8qs{pHgQyeDx_>OA7@COBPDAF(a`?VxsVv@Cd zG@@@)4TtZmfzLsFHn^IW0=~y4suhkSaok82@EQjW{5bUAh)Js-$HCNM--I!OHuJqY z0N<%oiFpQmI}U*^9%pwgR}VZs;_2}L4j-9&033o4S&bLSEyaWcP9U2gz98QvFCq05gG~pyR=q-dz0I+KtlI$sjy9fmU&}tKs z>=A?pxh)OVtDGika7B&d^J&TPy@WY@C@!p{2vOE4vo zYz~EpNACm7#mq!fVXj90JMpCCVTK~9GV>A0E*_PgoT! zfTU&;cT9mI&UUEr%CwaaNtix9l%+nJ3PqgNG&K%^4jZ{Gb=D({5ID#OVtPm)!JkX4=}s|+Qpyvja4m8=4{g|LfzmCq`j6x}z-Dsz2S zX+>69Pdd4jFjU#ZDTyPiJVhS4gzy_eQ(=|xjqq-Vu)j+zT3K4Ox^Pcfbwo}la62}g zD8-H2+cXD$Yn+j7Ca~d4sRW=%a%9ITf|G{fI>_%O>63dK3tPR&Rs%xr2w;>X_~LW0 z_rM7u&IWrY&WM*GR*4ttUcj77+zSQpEMUK+;IjVR+Sad^KjnN3o{Ne!B{ zA9(2GMYlY;Nv27$Z&xiiqzT$Fnmp+A+c1x8M0n5WrnE+{2Cp2zVMMI}~8)$#b!N3R0>A z2g^}-Jd2g*(dn41oe4TJFg{;~rC{!Bk?B!u~BKUqVU<#H_c;M21DE)(vW zCHm@Re6023bj{K~c3CL%cQCw@Td9uT8-FHvw3KGJ1mXP`yvzCpohR>Jk@#kB6U?X>P}S~sSAYTY>sPOBKL z`+mYmTK6aDg|P0+2!q%s3%QtnBVjzP8w=ZN-T8!D2qzP|0$|;xplIZblC5kc@kA6! zqa^XfMr4gbA}m)y=2gsuRjk>gaC*3e{M&v$tR0$v6K9#!*3zWrGItuxyc7bmyMScn z#HR#g#wB|n;7~yRu%zn5A@kqHG-D?YWnTp7_-hH`W%;?*YA!;ZxRfGGzWxF*mV<4s zws3J+CW19f$NoYxmX#x1wUHFM{#r9uo}*aN(VP|vl3PQTrAx5fqp2+vB+V|4{A{}s ztPEkHND^=O>)JkG5vc-?HGoZU{|=Czw_Fp7qKYL;FMdVA{YQXx^)jqe0b&H%HXKI| zLDt-Z<_wxMu+DmHol{A+>rz$w#rju;{M6#{QBH7+UvUPfrY#;W?b|A_2Ns?_plI^_;j@6E2dxL^g)`%=C z>((IKO#qPXc#`dd3Qn{I$#x#$Edc1XBU$!h!p8uxYNWAv}QjQ!`^WCYcK$Vmx_40^+XRSh|z@$e$l$u!doDpWtyj7;3= zx{^VM2{m*3Rw=9m3UdW5$8jj>i7smOUPDp{z^PzDd3@Kfs_l9X{NbE zTG)Vnd1$bI|EP&M+`RU7RkUqkS&{WWD}x<3c_we9$_z`k`N>K z-}8T^)=%T_Me+Cc{dIqx%-VOIf2UBu9g8ACd>+jud<3o#l_dCD1gQ_uu|$tlR~9M{ z9-U07ObCHxM?##bIx!vjr57bPp zD)H;78-75lt)>?7P0=cdSFJ{~;8(x2#$MEaP2-@dY6J|>G1y#bbg{x1G~@r#UxH=~ ztWkLCm$XLi@QE}=N~%a>q@+5Ruz{r7i==u!Ay2`v8j(gP6IK!m0brSCe6=mxS$v5`snWd9aE{rG!0%t%MDP*9cD#?jS57 z%qAQ`=nMdD{9zx+37-g6 zN#({J#pRKhjR>wdx3jp4b|6!6$d#!~Y@;SE7V)pOLu5}fRj~{Fc&+9b`0wu}sDqvm zqy_zebx@L!+NgQfz(bCkefd2veZ_3u(bU1GT>E;ZiqvBXLl!+B!9*4Ikb2Zz-_srv zCq9gM?*4BJV#_&k<1vtg>cy^vgIF@t+8cd2o1KRjqGQv*O%<>qAZ&;T*FXp=Tq_pg z8U$ zXv~cxu4>V!$lIDw#{tyH%jAz~3Lc4`g3cc?Y?_}(!msv4Xi3;afnSAN;OH ze>n=y4tmH@9U3=g)2ow9e>u)-yn{s_k9yDj_%nbXjaEs=kA$efckF|>kZ~kI6o3kV zpPa~tpa~Eg5;Q?z1&B@&B5M7IZ6uf?{gzn%_qvI{F(DQNxEx zL}y1xM1#H|5oLZrB1(UTM3ndli75Ud%IV@BBN3&%Mj~qb35lrFUP|T;_p@_dsC?vv zUm+1?m6C{Nl87Ex37pfqj6`%Xi75Fi6441HqE{KWG@eBCjxvyYEQu(*g+z1)i72&< z40Jc)U=mSiD;el=!VnTscsDo)4D=vjIw6xp^cgwlLBfTE-w;{?z(7Ut#sXdkBw>QN zyYJ=NomFBSEHnpy`ZYMoX@MRp%Z^$jciW#f{IbY z;crB5QMBPJg46Za%{AvQR+3N~nS$=dDL0q!fvq(J23bFwfj${L@AB9dHGV|!p-WEY3z;IF^Xj5rgX{Va# zwV+J{JKbll^~X-%OC|TN_O*AHQhVnfOYSZ1K(*cLlHwfF=3J`n>`|(=bG~Xw?!6xX z?mdzEx*~*~im>h$1;-gmN!|N#sy?2m%tD2B>=Mg?4_YNcX-mc)3q|r`KB|M?vL^4RaClUTe z?yXE?D;`hy3*jpO+O!KvcMf5Vg0m+~w(U(gjc_yJEd{4ac6bBL4j{-zZ#eoBVKw1H zLOB35+lFjAmN1zx7f|1KKn||&r`rKJsLP-(f7l0d!iOUXRYE;3%)T95+{{qwFNa0)WCmM1397jh(3>U=Ti8|8X;xPueHd1 zstnt^6#DDnzGDYodvjCGU;lk`i%ae2%Mi*sRj1eWpqI1$M_!8j4gHKB1Ll3haL zMEb}Y9oF(B4ZW<%=^7nYx_Zdw6Ou6kJ5xAtjQiVFU=s^0AnYdO5%v-)2{D5IJ^xqy-xR=~ zjnXM!D>);s%-VOIZ8WGuH}mj!@sQO;U2H9!LJPyWe6|}B31(($X#_&u(d1-N}vJ2AxLNlGPGkEq$P7*C`f1sBD4iGO<@ZG z+0p_aK@GZISOZuu+zW{=AV#nW5dYw@ovf-93|Wtp@@ zQR~9563q$HvZmTlnXE;vQ`wHA3YF?txL^I!8hgrg8>M8{X@gB;ia|s&&Ab?(E)AI>=Bvr(FD2+}gtRxhY zRGYCGk02~2JWBWm0OHJ`A@m{qmN18KCE-58%Y^lWPY7QUwi8MSl0_Fk?ekz2k0ci) zPVOOWC2SzPMtFj72Vn_eHsJ_DX8=eQ@g9PR_t1X&5aA+%+^&#nV@1S!Xay}NoB+VH z2=N|*5Z35}Y5_n0U%Yxdnl>i$u=59Qhfnz3Q|3cq`DrY+7i(vK?&+0 z=mQ64AIM2L9-}MCXb9iM7|$^d{tt=gLUi7;SXK(_eQB&KlMNSZ^O)@+CH z@MtbmcrYZFDZX4Mr765dlF}5XHM1!s)SB7U7l`Au>crs=kp!pEK#N=)XEn_!Qj>~m z9Dk|5WI3&?9miSmNaJiPFSwC<*&=JDYqi>|UF$S{{d5r`+4wwKBG`YaPX|wTfM<>38f} zC$eijN;Pon@6o4_NOuOi)^q4uBV||+XGX|0Bwlm<#}sjxpeg^074e}&GgLm5q#FPf z`x^jQNYy=9riUqJki46U#NCqZGF5j2DDig#sPuOOi1@n!RQbCBl>55@>_Oh{p0fME zYHnDDzor|OA)_QWR+QK zsun!c1-l$F*>!hhzYM#My&JkO*|CtBFXe)36uLFJE+wU=B)N3lZTpnDHJL0$peso$ zB@bs!o=Tnfi56F`P!glb6q~x+T#CM^yOp;o%PgnB3pZXzRZBUo+^xz*lQB$?b2BBDZfkf!zMa??TG$ zc5KZUa{I>%nk%>4Tdp1gmPNjM>#d7>fsHe~n7#h$BhyLlyV_C${AL2l{dxe%{TM2M zi#wCt-%lpF-vI!*pTd-x6}?IBo6VCpHLOx*&;VZ(ogk6LZ zLKUHIZIk%0laP|)ZbA{Ekl_FH`#gGq@F3w7d@$f>UqE+_nk)Y`x%nZ8T-BVib+HMCvH)V-51k<^-6 zNoswVFp<=nuoGkoIqovT5K`+##CnDBkUn;Bdo3ig>^ns$|L{l{)SBcPuKl>b+3g-k~cwfOGF7a z!L1GAC)S;uEP`7bWX~pba@X3|NwQH?aj%i;jh!~CTLeyI-QURtV6PFojsx7Lj|6{A z9N_pU{os{#{NUW7Nq(Mw@H~b>OBxDQTS@wfeQxlm?*^};iv-`2tPQbqp)=ku@O|A8-`6ernCf)B`&!el&$^WyG-}YO9*jzjIk43KvZX%Cc34JOM3_Q2 zj4+tciO`hLfRIcG*MX!uA8Ep)4g`OTrU^Vcfp8w-2Etmx`wC7~m`vN1a17x}LY{(C z5l_M$LC7V%qu@9#NWW(jUQ=+~_N3p-=#?%?An%??c$f718(QjXbWtBo`rQ;y`aPTU zTilxTyOy5n&1D)^?W>b7nW3a3EohR%1QKwXdp=vfVQoTppQoV!9w0gUI$LekK6|1-9CRT5YjjZ0xPqEc6s<-o3tlr@} zum>=z_xMU=ze4qf|KwM1%jZ3<-rwzF^|n}rQ4;j;OfrZ@s2$i;pN{+s^y3Nqz@|#Q zT=5KOYQ!G}KO)NJM}9Oc%a6$M!>b|)6WEthQ8vQCkwb_9kk!x6uUI$DBD%chSMQZhPFa)_z7XCrM?CpKlSgBBMNl zR{Ys*IIzWk!4?;@8Ez!pOL&^_4&gJxH-w#p5<(TBE-y=@DahK-$GDeA-x0PEHWS_^ zJWF_h@Mppmgt>%c2*U_%6r4DVbXiDPM_5KUi!g!Uhj01etLtclR}hXPbO3-uzaxh} zOgNj+8vsV#$wZM46J{`9WJ{k)-zJq_Lg-IMEg+*VA#^9BzQ;6?3l*H!78!Ld;cx{f z^f?*z0y1i|D&4@ym0f(WU0P?GjJg`2K?$1bi)j|&P0%BM6Ja0xorV2Y1a0{$Hks$gFwm4Od@7+S=?UCpnwVa|jnJC(2IfP2(g&D_WstsloPitGtEH4q36Mj#aMi@`% zOK3~TAS4s~iE@0M_aLtoHt0g=PZ&u!mavd;E8%IvCIzP|j?_Dla2DZS!sh@`uSnVe zClS_?fh$r;y~h$(k%5sTQpLiv2_KVz$CH8AaO!S%q^+(b10$oQ3W%R11CQZ6{;d!h z_#85D8I;qaBVI?T+3B3z@9n_J{kutI;5*2`r$cH62Cf`H2Hx754E#X@GVrsk;CjtQ8?f=4x?9TP#>ED_gR1Fem- z(@&`(X+p3PA&b1otbwE%f>a1V(wM}&(Y4tq+dIb05SCot%3b;WomD z05EWxt?2%S4160II4ns?z`&!)z)O{RozRzL;3LSuPb%{|okh5VmFJ~o;56AO0SQ?y zrmZ$DCIc@e1GkTmf$t^*kM|ik^$Rlajbz|aB2EGWr*0+#KR^aPj|@D{0)l}vcaVY8 z){}wbpC$v}O$J^@2EGZ=VqoCVG6a!{^W;%6e zv;WouvI5==S5dBrH+x7ZfkTje9I%A$?ptleQ4~i_cK`REWC|z6a^w({R zH**enFX0KoYlKe-TM7QmbvKVn2)=)?u7l4%S;~+2U)av0uL++L-X!=F(ffGh&rUDr z(b)T9HxLkWmjMqka}5 zqb?$&Rx~A}-b_Zdv&g6qfKgq82=D#$zfm6Mb)Lb~-NJ&SBJv*yBJ~08NwG>W&W!%a z3(_hCb@%_Q*P!nH|NU{lue-Ir%_6M?ZT7Tkn|;=|+4eu5&E_O6W}*bl8JH#^q$we) z5H>slW6zC@q$#=xKV!i~60qPe4U+sTOv56+EJ?tEvjZgmig>nyTX!T2$pP5v8a<9% z_hZMk$0K%Jdpu&twZ~u29)ApbJYvVS$0K%Jd;A^j@uz5yujnlueN(B79L|=PNd6*y z9=Tt%&tJekkK8YsbqKj%w9jA0KA*UesbP@&Mf?0x_Ic!f(LN9Vf%f^^+2@h_Mf?0w z?DMObAO^W#w9lW&KL04Z1n}D;_lx%V8SL}Vq0eLQCdnO&C0W^8Px7hAhI{^Qe3Evg z7|R9NOUlL~0@iqCakrhGZI68cMU34+_6L-00m1ybA|It#WjW|Mhu1fw*`(IUGjHUL&)K$Zry5aOPq z=LcbTKh6Cz*u={(SZ0_BGxy5~qsKX6+aN*9L9lWB=O6{t7-P!{^k@^pPZUFu7zXA- zkr*d;A|QWZ1b$F1aX5Cb5#{|blPGs6AdAF9bz8wof2+uR-KPw14>qY%S%Uy_`2+QG z3w4_^ygNYR3#dVtiWV`yBxg~QF4EV_38XKiH&OaRdK0BDq&Lwt^d?GQNN=L_h4dy$Ur2AF^d;#{guXPriPD#(HyL3x zxrx$Oy3p7CN?+MZUr0Zq^o8^zN?%AnqV#n>=?m#cl)jLDMCl9ZN0h#nkiMM5NMA@l zGQ=c%4$_Yd2A{guk-jF8zL0)I=?m#cbhE|VNM9#W43G39N?%AnqV%dNw`BqO_gcu=8s3epUiU_L- zI|yZjDuVw#|5yCqWZ(;YI<^0L-D{Df&c>~x%$tETxZK*&G;)N9n<(|+4#5R6jNIBPOSViugPwtK1s_33f?)`|| zD?3Jkdqe9L-Ba17soyBNxm1+3tswV4L($l5s>M2%k$c0hkb8emVb}yw>VkVa>>~GO zd_e9^e39H6dXU^3zMI?|w~E}G{4lw<`5TaZfqQ#?LGC@doIYBYD((6NjM;&|QbKps zi42f*)RLAuk4_o!Df_PFeINQ$mX1 zq7|341o+grrs1J>d=GWGB7Cl@lb1*(@mEW75%{Ya$Ar&{+gkKgHSTM8v2EXrovVls zby8<`nIgWbaR3s6wNGXyVwQbUGSQIfeorbMgWJDaCx!~DPc7(QOVE%(Lmt2u`9~7i z?Sw}NZxB8v6cD~9d`BoDFadwHUCZWfu<{B*F<}>BD`5lSHNsN_*<%XdyNp@TBBx$L7(r?+jVHCP z1($+aPbalPktK_OP-H2!F7&At3@z093b+)IO=^ucBegyRE(Nt7Mr!>kL~6Z+)LPYy z)OshWwKu7C9XJ(+IgZr&8aNdUdjzR(1^C}nurozaf;tHLz=7EZa+2Rf zDxrj5xCDRo=dSVOdgKdFM|PxNz63Q8)Id-JIVtloc@`}lloZXtc0q>^CCV-A+a1a$` z3bqCmk!7-O8JLT0rLcpbqabf5>i&Y|*n?^~KDJsFxA+lC&1F-Zyr|Qcp}w zwR&P=+=xs}%omfZjX_MVS*aiPonLMC%=avjYg0*)@8s#bn$U8gnPDn1R zKR%DQ`bnH&a6_oNdfh@3*yWzruI51St6gpxyBq|+()F-~o_4vF>~dQhvCBd5t6gp` zyWCyqYUpwh{A!nj;8(jG1i#wlAo$fT2f?p)IS78W%R%rfT}}nR+T|el)h-9YuXH)+ zebMEh_SG(Tl5{z!Wu?nOEUR5^6}#MQbh!g{WAYr68{9k6XB}wmf1tN}Q;}RjnpJB< zDoOq&TTqGOO1GJE6ePV?4-s%7CbHJXQcj`hx>{(?F4;W_gI?W43i-7(b(jtC^NJzY z4K!$)d`wc_)TGstOzWBiThwOIpfRVlghbZludYd4E!V1|Hs+|7YZc|2Tx%OqYET|0 zS-wOZKHT8&)nl2(W#lKH#8eox{ zE?01pJ|#6FnUzx0jijbDNuq_+S`$c3cS1S^YHIi`sc9mqiFv1;=DSEuQ%OyaLz>kN zd9R8|O|t-?rWcv>xl;wH>0AXT{1&OHr?1>ytPJHOd`M~< zGL(~ENNPHq)U<-s)ToHmbPTC!HL0n^&qPhN(;63RQcX-!nj)()CMisAY%#SaluLBd ztkwx6-e!(tTj!B7>!Ft>UuTf`5vDq}bs{Ml`j`(OS0|8uJ^<3?ko9mYsQvphnQO5$--J1>CdnndO^JZ@^|1t?-(069IlR$>6` z@u)%4cAdlkrG8=n8$r@CSP2?K9`c%`A!v-iGLSN(mSsc+G57Bm4M|gvkfs)rrmWGV zscp?jQ|rQ{sY^*y&IHobcWp>huf~(6uJLJVB5CUTj-;vlB+}G!($rMaR9O$w)F-K= zsgzV8JG0Ex>p{X5Sj?mO@d400d z)Ki+up=}9iY7Q+Ult-HCQc0RxNSca!hcwkYN}9@HDu;v(Oyw}dCQV(#R1PVhX(|V2 ztWQ(RnaiQU*QBW0^0tWL#GNSGN4Y*#;E5&{`L7*KgDuzB z%5=fIMVbH`Uv3GHr92ga>JF+K{X!Cy1ic%3ux0!t#cfS8c_ofya+QMP9u5C0$Yif1 zR6upFPb8V#0sxszCYh9WCz*VlN;0_{05X}WT2ZH}Kgr~?43f#iB$Ih?{UTLOY&gke zYZH>mQz4Sc#UvAZJjrBxE0W2}aU_!~6dd=rB$GYuNha?kl1!G7Oimz~ly)PTe3U{m zSy4kKec=50cS=rru9DEd^Bwu@f9rcWaR$r4X}^M!W3Ds7-PF&v{PndB@|f50+v2Dr z0@mQOQtz!@$9oGut$J?>vfVfmEUCew*4&RmUKcIYX=gif5ea#{nR9Y9T_uLKUO z^A?kAb>2DvIBn^>m8~MwYYVTjcx`1WF8*2xKW+?XE#{1ky*~2kMqXcmh5+#%XUI;S zaBVm6ut-+udg*v_IGCZQ$&Q`{F1DN;q%p}U-e3)jPR16X_vJc16;H`NpE z9!48~l{P+}HvTBxpq(PL@yivQv~9HUsQ}pc3v`2KmC?qtY2%?6Y2!GpHa?p+{xH3u z8K2X}2S#Y)b73Q0C%G0#*#5J_>xO+Uc@z8Si%PVN(vn<;9p~bZEUSHA1Tf9vhPhLSApB+&fANsY} zIQANbjmtK0j(Q+uWG+G*DBmj7*?<@2>Se%-i24;o3s;~%1iZ5H)L$Uy_Ns3H`Zy%R z%t_9ni_(^DYSae?$`Oa8T?9^27bLhyT#)uooX{+!@G?q9MtdW^BK}2LR~smsH{g@~ z5!|c4)fam`=qF?y(B6TM%F3U;4KHM^Pv1hAwXrSytgPVKRd^w^Z{^x}CERZ9b?{0E zoUeqetpa%$#2i#bP!-xge$Xp+OrwFU>#PQ1M{a7R24Yt(ZJ`EYmtWgS4a9PvKOs>K z#M*h?m^d{MYxl|%GSom~)`xeVIgl3e3>;&2=)4Fmr2nV1kd#|}3pwOVT1eV5-$KTG zN()Iizl;`=`5-N1+`F`p(3CF_2M-HLnD?D7N7<_k3;qRaIR31?>=F|DbiVe}1b z>uvGL?JFy+I?4(>v{YH)57n`lrqT+3#Ex-(&4?YwfH8U_Sce#cjM>r6b?A->g$&&> ziq62u9cOg_U*ZqoVKFj*$LTubc>G~`#$z&&f-UCpZnEq&k5PUSMxv6|C{c#>__7S^ z@u>ui>hUQZ+~YcQa1XJF4(>6?4|$`F6_Gs+u-!fGV&5R&hS+XgPz^yf=#;Of8ivp) zp5vPSa2mzqGCnd+f8Qt`Mln;t3Fp%&hB-8f8)+12g*1vIXcYI- zC>n3$i1!fRD6aJfz8`Yn+pB^`aWaiUhQBb1#Pu|a_Pc2mhj1M1&Z1E)rBQ?*r%|N8 zPorq@8I7XDH#CZ#yE!T@lTq=(Y7|2-6s+{u@*Q0rlVeeV<2h8whq>$I`YZKzt}JyS zkRtJA4t<3OBzZZY_5fJs-kPExW~k#}q}kWp{Fu@YtIo-vtW$PbbC-|nU>IbhgJC>J zWiTwi-Va&FboksyBv~K>854^dte0$HiDOa0>4;c$Zx~L?b6?)*EL*+-MZ#mR#!re^ zL?7!iA(D48_dUJwJTKShd3TPgg%PbiGK3bo-&q9uNGd`K+u6Ix;gUOQt;)e=X1PfHxMn~TnUcF+>Ld`3%b`YJ6k z={{QG<(QYk5>Kh*dUC(dXo(qXXo(9fTH?q8T4LIANdyQ>JZu{+vEepDki5Ag8yX-IESR1j9V{MZuax09hZ99^SJ&f(VsDt5qM-1QhI<^(7EZ(^>w_tZk zWz6RIy+NzsV*an1IZ>La?c>@^$rqKfnL<+v@rXh*g{ORiXP0wEiZoN&oXuz^d(SmJ zq?!8MSS-zye{Nf8rjEb=2+v;YgFlW;kY-9AclAazQ?xSg@?$!O&`!~~9w%J$W)yS0 zqO$c5U7bDYpx&(;r6q(C(;H{@8-LuqrEA}>@^TtLF`zNR@(@dKUfwue)0h+%% zjl@l^hM`G(;clov1j}K8vc*jmL?RN77=>vL1IiR_DA0z<%HzR;2}@L?g>kva=VB0~ z3{*@t1AyXR>JKb|js^Q%Lt4-Pfng92G{n44JXDP!<&&>9*6_>S5X*?j%)zvw8_>e7 zc9EW3gl)DvHFQfTId2h+^&Y(O*rcr4Al|~z|3DAO*4P*NSgU3j2P6+KR79l zX8z0sC?OhocI2+!P)NYcH_Vp}4%0llNj^1HLp66O zf}VzfUvPG~Zn0AgWZdQm*@4H!!(PHS3xKjgPZT>`AWBn)0w8ml@#C#A$lz>pQV@(D zTsDMnzhG?-WG8u+on#0*$=}#XoZjpttJq1RofX}y*h#iGU?(}9on*aidV)@34`nA= z%1-iSDm%$x>?C)ylYHHXox~Z3jZM%=u4X5BKariJyeB)!H0>m}NGEwaQ94OG?IiBc zwO!uNv2Es0`I|ZBkFp8p&$GYhPkEs~$8QBUe;~I!TuX2ii)#sPWdZSP%bJozF3R*4 zr*)PKDT?}=;GmKqOiULv787nPS&sd3u{WWhulN zDFYwpGqA+;#Qdm-;vbFavHX~xGL_*=RxeG~>`;e~*&l;?DpiLs>H9UIKJ)6+cO`qs zM*OIrLRH{nR+uF@rzMZSc)X&1P|uEiK|M9Q2FUd>rpM2}{ezeu%a7?PQyIR*4Yh#Z z4L>a)7tmbYag~^-i;60bk!=!yi)lRGW&|$vWil6)2wYrWBk}Q72jE8i0NfoaslmGq z;4;9wjK39yhd2!PYG51QO@%)Z?=o4MxE00CSn99Y<-#8^Ox|X)G#hRT@lICg!hu|$ zZci)$xZ=dD-jTZs-VWK3yMU_+E`SbD{Ew}Tu(IHKWA&LDv}n+xfsNLC8%3zC20tOx zRwF4NVer#J20tOxRwF49YAcbH4nl2}buT6BBGgt{7ooP2Ro_9Vt+MVl3XVIG;ZF#) z)mTb|+G;H2asGbrAq2s$K~IQ`WtOtUFm1j1B_8 zBz>NP05C~=;NDHvok`Y30GP5a0>C8ef%`C7cOF?60bt6yTbqz|5dfyFdofwp9#7Uq z0GQ^cL;#qw?iD`k{#F-n9Rz?W>mmS5UC_(Ox+f_2mUa`?{m5tC18sBE+99-E^|=$& zKu`k*Tn*HU{iGHA-y5BFgE#>yre;X3MLBy5h>&A>F;OkG7R~cEybQVRp`@zJE81ID zrILj>Hz$3Gmjb!5ZJA5|$$qlGnm-YD=sm2c#0krHVrqqoit9J`$#SizXmbClSH4_^ zNn8U{5|@(Ew0-|^lV&Yh@qB^fNmy)YtfF}5S0Cm*vf@u?{cbQS4RIR?N*gHBH8j8= zDBA43sPw@S>X8Sn$xts2QWU&3+zU~PGSah4@dmP|))5})gFsR=%jn$U8l;ZWMQUK- z`5}Y(h%YtRiN}nL{Ut-PNDORWVo;8!)BvvNr>eF<@-9n0XN>O~VE!S$gmD3v`Wxv) zrP7xbSa_m#a!0!xEolmEMb09@j&sMDMG@s*S|onU{k44C=GK_s^6& zY476-Xzv*i!l}K-&DlwN4^8}p_8va*BiOUuWMP5WJ5)y^G`d}8*w?DPFQ&aaXVcy* zen-v0j-j;ok2=uaA4;RW+ZWK@w@;wGuWLbjkNrLb!-2@)qXBB~wtcy%3}El?4WYf4 z&X2#1Mw?Z6FJ{xu@E@ z<-R&IUG3d2Skg)D-QINh0JV23`qBlx)!t*y2RBWG<^cvD+qv%YBQjv|5pVC?D=+z< zwqo!I#)H8(Q&Q?KIh9@ffT)imia6}4$)a~Cg6n!o#$Fe{Ev^VjsexqC4g?F5EIJ=3 z$)aP>i)pfG(I|*hsh?(xj&K3msjE)diG^p8CB(SmOj!c{f~XP1V=_eL2*p@wPQY;l zOU)3dfkG)naJa_o=o&M=rTPQ6mi{1DmX>o(PV%L}UH;12atNl+=&=v6$5wS{RyH6_iSB!qilH zY*}yi*b`JE;aWWIY3bn356s>!l1TVdbfZVxKoF_X$B-UM`W;9QH7z*An;L`+ zL6`&~!}F@K$PjO8EHX5P!@NW}Eg(73G%dKK-A$IWlBY)kjWsK{4M>%<8mA0F z#2=DyWt<%#DSRN_l&EE#?Jvqw3QXlnMc0J0DsRHIsYE_m6n&FO>U5hAUtx-i)ong-RU&M{ovOYGE^$$qiYm7DHXjgginbIN z+tNcS3Mxz;h&O9?`H)d~(4s+$1~yvHZ4{DCVcog-A5yY6$hr`0D(hZE)`ehGSr>v$ zW!=lkx)5wC>q4-pta~F_7lKV?-3esfJIT5bY%1$cBv$W!)<&DurNESr>v$W!;+wYy$fh4Khja%__CfT-u)er5~;JlgJgquASkNd zHc}P{iXkP^^@6roa>TotB4xt$wLv0hxxUt#4n7xBqE_;@fLuUJje4$xlt`4Ld06+z zlnW4$x0`7`_z0v#A{{NjIth|Axd5btcOWS0fU{AoqDXA@4lJv5ly@5<W>xLA_J4ao3n#<4caxZ*Zs?0 zA>mXWhJ;gj_!08(Lh>*qoXW$Ha4HW&!l^ubDR~$YPUT@pIF*MX;Zz>JMnNQ;%EORw zDi1@#sXV-#JUo>=3<;<5FeIGH!z%&c;aTKiNI2WcLMmXWhJ;gj_!jc;Wb!a1oXW$Ha4HYq zO&*>}9)^Tdc^DE-<>80P!}G|)kZ>vwZ*4*zhJ;gj_+s)fB%I2_kZ>vwL&B*%e1*@$ zza_v5k5smniR0AQ@~QGfW`S9&#(M&o8LeSC9Fla@u| zGKWq&>+;+6dOAZmWII+qdPRHag={C9tKBJ1^g@;Bj!lt66N!29O-{pZcMwz0A*1fak+g-&KF*jDW``a%*ee3bRUb*1p zLp#Uo<^8bj`x|SABo|6W&O-~SLYd#t&Q+0KSdtfRvmCa|&-T&OV{ZGL7mzh;HFL>D zL%nC*_P)hTaml0R|3zEkQj8-oa1XmNCn|IHf!Z8a0qnu9K>vwDy3KfLt5TS#T@bOH zkkiTyLsM9V#>u$J)Qcb3j$5dTymRv@-OL+%aSze&Ub*e8p^3POs+QxkZ+bNUJBhcg za=v|M&2?vtZh~9+EV0wrX>%{V{;o&!J}lT;w5z1jaz*|3ZQ*AhytMYO*DXH##L?~1 zzPQ7%sNC#Atg=Hbhb_b#zVI)fvNqj(bdr2=)#=y>8ejZjU)k@E8-Vv}mqaLHf>M9$ zAmIp;Q>z#gH_aHc76t!8f+y-rV?G7;_Ftb3Z0^4v3QXne)GLe$uf*#RN}KuT&YHLA z!qaBXpL_1~dD-*lop#Rr+4K9IJ8!mp7_ks|wBosmlI*{hZ>9LJ0T^fSGxA#gf_z^7 zrJ+>6POtSE{jTPGL%f#Xt^SvU7uDZs=D$V`Apc+J-7ER3<__Xb=-nqwT=PGp+>7!E z%JV31p?qBDv!RbWo6sloQI??GjB+2!Gbrz%6rk)u@k|Ii$%j7u8l}{PHic1|pmahR zgmMVVu_!Z87NA^)vJ7P<%Ht@nqHI9<8l}{PHiuD~pmahRgmMVVu_!Z87NA^)vJ7P< z%Ht@nqHI9<+JwGl+ioK1<>FEE7&$X~K<9H{qt(zP{-g zl%r8jMmYy%G0Jr)e?eJ;@&Zae%I7G%QEU@#mX6XEr4Py&l%r8jMmYy%G0Jr)e?eJ; z@&Zae%I7G%QEU@#o{rKMrH=`>dDVooE;ZrqWhUJ3F%uqu8StOhCu}m|$#YG3%0nhR^(_<}Pupg~ zCncEh$#A)xa;FKO7H`6*e~40uQf$K04N4=FER+E#<54D|oQ`rXN-oNcD0ibgijs%& zAxa@iu?f#GD2-6EPzIokN123jI?A~yxhOZH+>P=mN*>CGCY(J9YJ2`<)3d z#J&CgJrlkd`?W4!V8Xd*i_6|d*^IISC1S#VOh##i(gS4#$`L42Q0Aaqh;kLmZ72_- zJd5%+%4U=uC=nCBJQ<}GN)MC~C`X`7L79VcA<9)Kx1l_U@+`{RCVa&UCVcHhC|8^C zjpI>DP59P7ned-+Uw5uI;k$>SoC@OUg)#~SaaSv+p`3+sG0HV4cc83Bc@AYg%4aA$ zQDP>1Zz@U~lwK&KP=1Rt4dpD9i&3sYxdUZ2%5x~|Q9eW2i4rs6RjDX#PEngdb~a!cTr`!cX07!t3rpS#844<8#knfwCOsew3$C-bBIYo-abF zG~pK#QCgsMLm7s0ILe7AXQEtyas|qAl>1ShMtKwEQveqQb$sTXX((rzaQ<~B{66mE!yFUd*b!x*34eidYf)ZAc@O0alszbp32$zI(hj9B%0VdqgK`SWT$DecEJgV%%372c zQQkxO0%Z@1W5S;uX~JLOGhg8|-@xX-1vh+mmkIAZ)PzgFG2!w86Rvu|grf^l{)mFQ zj^2y%1j=hDAOCNAX98bWRj&Pga*~szY1%YxI?wY&=ea=33?+p!3&@NS2tuI@1sakv zw@sRCaKNkgDxdfPS4I8!)O&FN#Q_x&P`S>4Tm_Utrb3&u_PPJ(UFYPSrY)D2DQS0p zzn%9zd%t^Ld+oK?^FGgF;#u7MYEZN#$<&u=4AX3;1DK9sI*Vx))3r>uFnxjP9;OGF ze#P`O)2l&Idy=Uy(-@}NOb0L>!*mwYs-P%MeU!PI>5(8=^q)bpQ^m35wlVIw@G>YlJn4V#xqp`Y_X#mp%ruj^VFrC2k z(IDCP45n2~*E4;J=`JSThkbv+^aK;z?Fap_UkwxM_glzxIMXRi7c#A7x`pYBOy6Sq zDbpXAUSP`bPUU!N#xSwp8unYmerwoo&E-t?ZZ2#YN4MO(&&_D*@LDdp zxv}^CnXWhoIQqtLc!+6=O*gy*DpSL6j$X+$_I@H)z`|@ni+}qL!rk|JB>3=8G=)sE z=#^)J=v2`TM!pOMAzkzX8?NJWWT6)Y?c+9^jlM!})S@6-Y{M8tKfx>vqT?CdU_szY z{$w^f(Yg<#A7P*s&G3VSd=|r)A$>NPjV`v)5~81B7*S-Pdfdw))z7F~F5VvC9S^KRq_6d7yp0(K0Mfxn1AsdeHKgi@@Opyb= zs`R>Q1~mK)X(0@GF!MgLMi`A`$mf;A*OSWYve(HrsR-QA`v80(g&(UYy3nxBBdP_;*7CcYZOL5?8UndzR8MtGVBU2Q(ecm8vCK0$vFOox(4hBC( zW{vCh2x&Iamoh6eZ>InD@b?~lPT7WUzV!Li51Bro2psCo|o=WU0l zK*ORkjyV0zOWTv`i4mSpAH1VU_AQ=Dgf(9Xn3d>;2jALzaa?% zz{UM(Fc2SU5Puy7TLC0xl$%;_(u*(Lr3`L7C`VK#Q2; zF(h8RQf@Z-9Ka*#7zbjI-v3*X*{B6razG}Ug&}w2<%HSj0kBKP)xoDj~`e<21f5p`%AYUT|%}+bte5x(;)II`eo8v?%bRD zhZ^kRgQ&q6M&lcksP!Pnw|~4Zl_GWJOLf$h)S+J`fkAcZUk{{C9Z6DFbBfBA%J+dj zRKDbi{dy=V5md^5nM|cjCH>-JuX43%DNqU-VlPc07lPEVzYL}lhr9nsC9ou^VfU7p zyj9ffRj#7_NroUb?CCz#`{@ze^f11sY$z33K!0*Xpq(&YPxZ!`1yHM`$l!v%n#r0M9sIT-c zOq@(t#mdnuDY!GJp}U7chw3X;ReBlBAY(qdlh2medneZ*pffHm2yr1IgC#Bqacx44 zN?3DW^v|b$^}xT>&Guh1n>YXbQ)kUkX6%Ga`x_6g zB}ts`lXmy5ql@_z*^95H8%Z)ZV#;?;NRqL|Fo-|ji;S+>d`C5wkZ8?7YLCt)^=n=x zoxZV*mNaUIzm@tKDu}Ox@CS=%o}UnyTCO{bSW1)T*){cxqLj-*`^duvd&z z6|MEus$S1~YSk6qjK_=#qCXkID*CuLCwp^rh=}nC{1loMo-?Z-pAVuD6Z=e@5=0OBG2q`TLmDPyEotk~H@ycJ=XAQGmkTw@;=+i=}v%b$ActJeRJf zAD_ka)}P$r-I4R$OL{}Fm@fY64sT+Ix1_^6uEVSE@YZ&Cw|01UcX&VS@E+^%zSrU1 z+2P&X;jQWL>N>n5JG_M*-k1)r(tDiTletrhKGESF<~WsKhsAA366!r?aKUgxcF?B>Hx?<(@l?Y^q& zGAagD zEVOO@14Gi*63a`7evBEGiH;;Yfy}O77m?Y8z|E;<+!HBFR){|4a~7WKX*ml~gBka7 zUwTFX*PG3_H->_KgXw?Pj7v`dk0CKYxW43X<^c7RJ#a4u`5WmyV19}r>EI}z;_$ds zA0}j?Gt9WBN-fhNTImxW{$6Pb4^gAfdw8Xv^(#iLKKYgrtglq}+a$6Oj6Sfx)RH2N{>6`~yR_)(G8m=g zdQ^>T*RoaFU%{uf@Ocdk)-Tgu6%5&=rPt(s2J5x>RgKBeFSCVg?&^PPd1$|BEF^;H zN=0lQ2@jQ{&>UCstYU7<%_$0^dd0XYbdFjKIf3Lk6Z5s)oTL&D$gf*Kzo~_gK3Mda zLU=LwImoA}uQ56Ve!JcmaY@l|aB)eAOG;d)Q186+I>p{VKVuA+iNhvF19)ddO#l+n zt+5whgSSx*`tnwaOHcf?>{^Wxm!7z;-SzhkrAKcsQBh+aakst%x`(-YiQRpfv%5Pp zcxTVA6O$N{?IWH)`Fn4k_U3tSUiU_Fdo$H-SRqsCO|i)kM(sZ26>pyP<_T{e_vRsQ z?)B!g-ZXl1hBpU#Gv1qW%Ps z{?Yf4kosWpFCkw;$)55?M*QrR_CN8RV4olw8Z;JV7CIi<{LYMXm83$Es&I-o|6#_Z2aw%E=jw&t{0u|S zDw?x0YkmLwGfE$#|GnAwzi*l7```c5_rI_3yud$~S7|t@*^=Klw{0^CEe&?ifEx&Lt4Z>4y&ecnw8g@&h%L{=g5^Q1v4} zLPPo2{0I%nTOp~J22q0z$>2_V-Ns^YlOC~A7}BM!8t#U>5Z`CRS>pSgiQ?zk18Cj% zdDa(IO%NR+ZtK^?a$PF#UU{?RJs@wayocoVm-ica5tY_uDD(?lBx+0A$ z75%pYdnxb_@)*=46Fnwxvb+c7Es%Ggyo2R^Q{J)izAW!ddH*7Br930{Hp@Fh^S&eR zAbJ0gH&Hw>MoP&@OayqC1}N_h{?HW_};f zxzT{6(T7Br{)R}_6;I1OOfx@;=l+=B6#zp4to34fm*TnC`tUx8&Jkbx8a#JOq`A)t zLQN+wNNfIiB7IN%A*0l|-xZ4(Ub5y*F~E<)cXJ+POq=N2;HB-OE_qPn+_)Eq0Gmb+ zp>Yx&$NZ_%{iqUx_UB404D>e_vL=l5=mg$Cu+1-F2N2C~2EJwWyNj@p&A(C3@vzT- zE#_c3jB7bj&LVvdmxi-_X*rjji}r)zl$7D{I<8Lg4vdRlT=e3i7uR}wR;{O(F7Kcn zahlWjA9|?XC*6vt{k^42{W0_2k9pef?KMDLKQ29SDci*-EiOI!Hi_$~UAqPzgc}s3 zt1o?$ubBQp`@kbVyNQpG-iN+<_=)GNzVWUnGmS-jWBiiNC-=9Z;&8t{C!p)8{f%W% zx}kc%vXop%>SyMYoC(wX!LxhP1vWX8ej(h8ZBv(hsDtYQ7sYP9s=(^KKR<=6YTTQbv)J$mObrFxt9Tyj6 zuywU!78e)YlXs_1$!{gDUEbHa2Od8!B%^PZX#5j6pARSK>&VU7NA%4Tax+pv^bLjl zzL*qR24lfuIfc*r9YmV(<6v3*NiQrvmuOlQT|uvxZATcDg;UM z+wJAI!O$4Re_%#*kN@3MI5z~{DtNap@kK%s=XnoU|84>JRl@ow z8P;#gwf`p6U!EKOrjiP()Ol|*=JH(4E9#AeUMx~w)^nAAN9d24LzVcD^<3#wB7#(j zbazJ1bIHe%2xKOy{YQCkL=gQH`9S93?eD#jL3A$)gUmx+aCW59RzIgbr%D1(%{kBYeOb~rRqC)=lk;4~bLz3FQa8=Va-K^);fp-oG^fOc zpQ{rW{*PV$?Nq2gJ`GZ1vM+mH|KI7pF6iBv97K z&q!pV6Fbdte=MQ(mJcb)MCW#z;r`Zx##=sw@6FYnX1JI7(00p*(3yH;ry1_`K{Va+ zAtjmUQ=MjPVSJY$d$s!psZ9I--TG%VBfqqiQN!}T$}(=BjurXwqmCctY^) z^}bt~xO9Tl#-+21mg=~4#-+3C*0}}+LFw(*-17L~V>-R3rSEwIlXs%m^E^vt!KOUD zGxm0c9!r1Eq0eTfXDWkq&8=zrI_b)s@-6x|A>thJYdSKkgLLxLpVLoS6Qt*VVKY6B zjAqjRswe1C92}%)u6>ja!(lLWF1l|MoqHpL&BfEt{`A9J=!+W{yiqpyxK(X;KlEIt z7u1|*f~moaW&KA^nzi>qM;>>?fs1EO98r@B8Y=_!I>kqky%u^~A&2?IBHmX+GU?45 zdeKXYhUS+?(;Z3&_Cx#7+1Wpn{^9WnIyn1g(wjazgN(91ne^{3f%_En%A_A!GnH%I zgD&%LpFa$cyd<;v&7Xea^r=PYB)s|4FKt|T^h{(JD_2W)bGO=$uH9SYo$qQ!?YIX= zJP28=vGV(GmDS$mx2~&`t2eW@Qv%#OPt2+w*k_=g=y$%Qt&^1A>+RaLDY`$i#E!mk zdmdM>?0tsh$_7FdofP!2gW7X9j|9Pop5yUAZe}V3gpgp5!;s zEjO-9v-Ou(^kdL`fz^&aryHw7Qw3Xte#L;?+O6?}L{&U0hi1sdKe`0&=8=LRcf zo|)i>H+6U=1IG-EdU4VEb?Ri>-FIshMEnui6b=u&^`|KJG1h3yHw5;akLpezktl|p zl-%K4=Kr5J?7)@Dp#)-LxyXgQ|xzSf2it0N~5 zFqQMk1Wb|bVDrfZWbKsyK{jA2?`!Q6zkrOuRL&<6FhyE}tv$xpPWm4t1Exr3umxke zYQ>~2*bfo{Q#qeJz!bR(Hh(<2qeUc`LeD&u4z_fvz-Mhge`4TLS$7ia`k8pe-ka<< zwVRl1fh%oV-)FsDA_`n>*e5if0@oB)<$O1(HSFzwP~htGzU#Rm?By3w;A(R|1+FQq z^z$ijtliW9pupAVeXU*L7f|48bH0Xq2z&VX6gbu{_dh6b^?6@wm-z)0xZ0dgfolp& z{d@`>Yp47V3S52O*V-k10R^r$=TqRC!eT$40>|1(|APWopZB$PkzYW8tIhcoxTY}S z=TqQVJM1WM^#wj_cNDnVtV=O#>L_rNcH;sU*KlzS$FPc4&Ag|^Ubd;mvLJ|xBrcue zpWYPa?wkG1OQDM_ni4Eo&%uUKYq(EHWwTGHT4wLi1-1NF4qmtzqdI9(NY-Ax8O1CN z$@8nlC?hajfKkx=kQ~B#GYXm)l4DqlQ6^$I7o(s#A*79ZGYXm=lKfMPfr8N#&cY~Y zW(eP+-i(4~gwQK$F%T-6!s!?VO$*^t)SFSzULk~vS_~A5rf@1oK~usd-RXv?1eK^M_)oSI?BX-g9Jm=tWKUIyjgc zl!k6Yc`zp^3sIAlajlbr*+F@T1oG^lM~D*hER1XJ6U+=MLi8zRT-%&rM$j{K*C$0D z4x*`X+f`$bXOVIwiH%t@6g>;3XWP8MjtWbTE~EE^$8iWYf4ZZqB2Zn#9>qd z(ew=wPL^@4(*#9??%D*6#+ooX-i&MMj}}P(5bBeRYg-5rWkBd|EC$3K7)Ga?aT|wA zzd4Mq!VC^k4n@T|bnD6`-yD*!E8|)xO20XTnacQyp&vidPL%NzLxwDrac#4u`^t$H zOUF4x6I8~v41&fpDvT~SCvk5*jtr`hDCWPp ziKIQE%%fIfUP*3&Dxh3Am0Q-e<*H@2S-sd+*Vg?m@~dyPi^c4`W9=R6!yjTt)K=@~ zj>BT|`%wLBiv|RCzEgF+YnkPig&Itve7%{o!!TGBv=7~AHd;+vBollE@e&EKpnvJgJV_;qo9l*!JTs{bIG8>)7N5!1L4Qw$RUBdUq z?7+=zGaFsYcL}}ENAle=GjJ6f%tq((Ni!pGqgu^ISMljHJ#hQ9VW&}Z-@rH0v>-Z} z&!)WsSKVSZx`@xKspReGlWVG8o>d|E`(b>UO%7b?In<4R*I&Mm1dR0f-;*g zjXN&!F4^(G=&|Zl=99jpQb3D>#)^H#aGkJj{jBxuu#vVEEv|!TanS&yY{^Ea(;kCz zJ8+}f=u%o~C04d%DO>Z^vRgsRjuAE~Te6g`g|q@ywqz+=i_|!zY%L1YLGg{W69#;tcZ4C39* z8@&!xf2=hu2Izg?b}%n`UjGfe{%H-gjy6lwVA=|5exQqOQA5;}&=}0LEQpdNYM2@v zL=B@kqHPUVv!sDey`dH*OVmiUU5FZ~CJj-e)WT_?g)_*aWQn5XVNqk$IwEQ;mZ))R zG_glnqQ=v*(zeE{r9~8Db|`A1HNZxjC2EqIXGBe+(Wa=$YP>bjc&oB)$r3eHEj^;9 zTFdWXT7EPH8)yhtT9hnN)75GuYPz)|52h7Kqq2cUC2dTOOO~ivG(Z(KOAS)?I9u)0 z2HK}ISBa7(YHpCSsJTIjMa{z!H9sh}C|RNw1WAip5ENO|LM%~>f`moM62*%wWQW{+ zcDHvBKQ!BE!~E}$#rOoUR*l0WAnjYg2woUbgfbt-;gd=EvO3HdGNkUeWATT+LV8_Q?UO#UsFenXkQn{ z{|%<;(isZdJ;D;{A=ZQJ!!ZW;pBz>T_n#cXSZWFdh!{KL8C*G%j(T2XjDi_SuJL$f<|H#G$I_PAQ=T2 z$)y%Uo>)^j45Of-A*o{ZW)w6eBtfheLv~J6I2fa#K_MAo^=1?_FeDGG7DLuo6YvRW z3PJq=SqPF*P>rCMS`1RdO<_L)GX(V&PE&72LDir+1XT;$X#&%kVnJ0xeCk1b0DuVU z4K74bZ=pm@phJL0Y^f3ui69vT^#o!fs3*V^K^4NE2`E=!!)EwBn48^B$1;Z4Z7j&bTo*6Q1wTx>cJ0qACy6co2JUc|LOh)+$Wx<>gZwdy?O~kVGgm%1?~Ly6F?Q}nMTblFR-qCg6BXBaULiRF;*_YHWb z`XcAra^-L}$`SPdwHSFjq;YXLAkSn0k>HgQHN1?1qQj>OOO{Ce0sNnOs}z?2>Z&pd zM+33%It?^0kY1dztY12s2D6oY=I092S)#D+lb zIT8}$Qo+Jt3y%Q%UKFIuD9ZHnCmC(2_#TiZw|^Tow6ex;qQa&cKaFafTD^aZSrGie zRQW>iWut4T`gtK7!3%-+L-_`?(K);>h6iqBtJ&yEULw3xKv{?DRRe-QLT{cEdGicm z6y6rI(MsM&q&-h=HA_`GTJNyKc!#0Xn_6c!I*T_OgYXX7Xg0c>_a3i75PaF_I^K%B zBah)784c6D0K><j z#i``#Ma#Jtx&+gChI{L7tRk;3xxs?`|1a&2e== zjcpAxk{G%*c)tB~AR%|}-V&(`gfWgW%@NQWYwuAV}g3?mm z7?#VRa)#v=={?oJQ^9MCC|RP4d8Y|IF4jAaO_k`C*T5@}XNV|SqDpx`DymfPOQOp3 z`fT9A6in26>I-iC>)KE)!JlOIOh*J82qAU%e&Zi*|WoZZpTN(mE z%05t#Wg*o0EChnMtMTKZG?IK{V#m!4mb}H|p}K|_E;S7e#NOZIbt8YY_Y3ALj)~jF zd#{_T3+&0~pnI6Rm)Jc=S-_w7o_oHX5cX_2P+16Kyn0vg>iktB^SGtz}&0dN_By;Fe<+sgIyY1U-Th;bH~Jv=d}(zU3IY zHJj}JB=e9wF4f> zkstgFu)o|g&=!_~4(4WXQVQ0JJ~+3b89`$bWrFoW)Ryzl1x<95rUUMqGzqwGCQZP7 zGiie57%+k+&;S@~1WA*CAd@B_$fOCDV~`|hGGzh?hU2r_8`f=rrVIR=!Z$&?8cBuxT>OqzfoB`|PqQ@zzD4;|zhlJ` z-@m`TBFwX3Sa<#z&VuQUMUAjDmxR$e_58OTqW^2GPjK#`?3&BAtvvF_x$QD4bKVq1SLbTgyh24b zF`?7T#^rM%RLjj5zp(8P;~A1aAbO$Wt{Kg+&eIHm0mg}6NR)VnM2TLgD5DwHd72?n z6U8qiN<2fNL@!j7(G2T6&5)=m;ujJno*_}97b?nVhIO81NYpg(3yBiXkSNg$6=gKT zIxuf&hD6O2zmO>L42crGP*FxRtn)NOqUMNSNR)VnM2TLgD5DwHd72?n^TjVDN<2fN zL@!j7(G2T6&5$Ty@{k}Z`EU(oO%as1I=xfN{cSiL-)*SY!tfIQ6Tc7fuoP`|NQ>vO z6*k^FosF|kBqqKtDzWrIFae4STgJk`_~ z-S8H#%6O$$Wjv$}3k#*^Ixoj4C3+}y)1*!hvo3Lsmt*{pmt!2%?By6QGZ{v=qzwzh zg~KyF#yYRZIANpLV{G&~j4QkjW8V#C;Z{h7(Jg4j!VN6G-s>=)?sXVPwRj!IHPBQb zM=TRvWlt+EbbMC;Qh6XMUtD+M0okU|=Sz0yXDJ)XL&89TJ-!R-=^%L>*jZMpai~c(ULi=KE#wHpp!tKmI#!=m94?|2 zDdZ(&ej}|4C94#>g#k1`4tZcv$uuq&ST9TsV82rOrdfpx0oDl76s=5XL=YV`m#fBV zv*bcK;>OP)Ii1U1io-l^1S|10l8s)Wxd@}ON0G`>^tlrOTE<#Pp|W29v{I4L*e}=` zcmRxBh8NLXJVpeu)g}P%94_z@#PWKoB5^sU2Ipe8oEroP$3oj!XN0mtxo@s*u}-3a zJBsQtCoyIt_gu=;oWw_PqgtH=LaZ<|8gvo|s02yu8KCkiT-2F44S+w`7}wiroC&(; z*e9ofhQb9EZ9$Y5a5t?VQHo7Jx){&1sw>k0D?<+3NutISrj(H@_D= z@>U#jNV+GZ7W9*MhSs;je6~jDvk+cxQ&b!OOP4z@yIcgt#oXM=Z+RS^ZCkMN+c=Iw zeyzb++b830|2X{0c2)fK@GBP_hs~hnkUI(eP89c+`eY**3}DgGJcwXNEd#)gkgB}g zjMTYJVI2W*Q&_*yjBB0CQwc5wdynRg#KUDIPi_+Hpq?hN{vk82Whf6R%9>YU0K%5> zoPvvO=)*IL4Cg8{D$i0_cQ=(w@j<2DB-YVXH*NLn^t__g#%XQT30RajkQB!l?;zqUvXPQT5jG)CMrOIC!b4 zbMPjr&cXNc_37IxxGEp<1Eh!KZ9hQUZN|qiT(_rlabIIflhR~j7_Q?Jy%VYw|J+Hq zt_${T$A=UnU@-y~BVgTvYME_o#xPtAtHiL%4q%nIXv9ThXNrc^slCa?H(8Q$`b$Y} z28#moYSipW`jKeV|6_zpxqcf$Td{Zz=_o{3tx($^aTaTN(9NRfwj&1TrFUOW>@^Wm)dO5cK8@wFbDlf;jxDAVl zXz2}JkL@h4$42+QblCuFq{jvW$aL7M)_Wbc3r&a3&2Gi^qX=E+IX~){hw}r#D2wcw zC_nC?HY}WfU`bm}4-PRz|~#WJ24D1pIKr+Ij4WQ$oq2^&xBur@4!M&&vW zPo3}KsTrbY0Z$cO>*1-BJUlhH*=%%~B(MTdGEl0ro4`FE2{vYKcF(pWo3RZi$?tjRS5`6E!JchVw&3g-)9su~k;Qn~YGIkPZFRuG zsD$3=_?Nz$K#U>@ya8&Mz?-l^(8A_wv*;=o z>bq?m;q~24@%nCT()8UxK1|>3T(9p2^alxuP3~&~Z^$W1*UdHe_4;l{cwM&!uj>ZF zAbq#!6q9vx;19h_*A4tdx^Cxn(skPx5CL7cOMwdmT46X`{)VYAi3ExQ!-H&tp ziEiqF70qiYxKaH4@Z`Ri&yOmp8gQjNJ1>V~f;J@zP)lpHBQ5+ud>-Z@ zc~PMRGcBr)v$4JVV=iZIg3Jak?t(T`MyGvX0_kYBnn3!AX4FuUK)SL>B#qAao~Dpq zy}>J_AA>;|eJxF%A(rAKY4qp<8bm{Bdu{Lv=|^COi|s6(KIwr=8a+DCjO)3cwibf8 z%P`2}Hqa2GeMUN#q|u`~GfJ9~Lb^M!%}b+SX-2sZ(ngQYG@~YsX`|D`F>UnKX55e# z6Gumv)-=*-yhtP6Eo}4R=$Dvr1Dj199ZIx`q$jTP>gc3=nL7H#W*p}&d2~j+HI;PB zYS9)~=GJj0n;4Cvbag#UT#7*Adax-pNOBkT;8$Ui&7M-7wcjxg@ z{X}W7N3nCg;;V>)Cwd!s^juxWb8IUY)I5cCTmG5P0_--Upt95Nj;cvHXXQ)u2EURw zH+rpy@jjOda}}?7l7=oebs8h4sE#DFDXM?ijB6P|!vY=I z1`PR1N7Cv*Y?k+^394Ue#*ublit4;|O;P=PGp==(S5znMfVN>6ooS}Mb)2WUH+h=- zah~QrSZ)4XVp{nUJ!)O>;@X#gswsQh3X0a-z32IJdROjw?p2t7bM4ZBj0+ldQio8S z-1^>XF^4Pp4>fxspWaZjDJ=C2|ksY+gX9q3!*+Con z`Rt%eve`jPe0C6p#j=Cyv)Ms2eRdFRZ_5rk-Dd}F9P6`#C@hv8bZj;|XpqkiT5U$O zbW0E7*eyM1Wi~x%zE2OjvDBvr)n(Izrug)rYl?h&&`H_!py56}Nc?@$gO&%D9z-iN zdv$j8G4HasoGOg+OhY;Qf{snMyb`*HRxj;oSr>cy`Nrh$nEd^23I3k=aPr~C(xtrC z_b>(FJ^sY))lt@zSz`CUaeE#Og*^-+eVCl>#?p)TG+1;GKW#k<^lN%F^DO{W3n+l4 zI-{A15_;YWu}p(4Y(^H#l;43F=iIW+yG-RVTU)uRE_iPw#vAW z?TcEmupdiq@MOp{JsA>EQlv#S-^8z=g70bwd#n*Z=957^a7VM%bg;zkFV%Fo#Lf;cH;>ZGh+ft!PtOFUO0NICEgLsql<24uyq+(k zdCG0!%2w>Q#peCWwkM0o1NqyQZ$k**;<<69#nift0VG(-MD#ZFHw)cmV$fH;P}0tm z1e|H;oyPY(>>mJ|$&i9Hu-FulgX;PEhbshNGgabwZToxiyi4gTsHE?zzgaeE+IbE1 zFTg@-$!h1FMz;eTB{pf=d30f!cAh#Z(9XN50$XaEoFl^1Wpru4e`1rSop+Si%xj?g zqu9jpWTVsR96`p8O)fB5yIDMrbfuh6SBiR8DzJ34?5~>;UdkPF7s7JZRoE@=Wk;Rb zf!k1ZS@p<2Zg;QyR9T%yB?W(*9(rAX#chhXRR0EMBPdKe-he$DiJW?=kF>5*-v?_m ze6MMF2XsP3oIMI97??|Mtc7l~$a-*Wkq1@GCAWqn;(^F*=4~!Zl%=NlXPExas9D{f zC-G029}>JJ)4~LAFE*phArrhk&WtGJrg&>96)4_bKxPFA7bKII;_V6yinooVVZb1z z2Hr~Xb{)AJFpUq#KqPJOinpYHnBuKi$&gBc9i({cpt8@9Fs$gN>$ZoQJeRY$n0t}ZdkL4-J(ounztqAt(@ZPsP1=fs7uM!u|h=6$c^49jwB_iaMgV8 ztO0mgSjHl(SQfx`+1~uz1`2za?Jx>a1*2-_kw}e=NmO#FHB7 zb2U=qd1h2$8maO6EUEEyPimyk)kuwvSyJOMSyJObx(b2VSDSHd2YFWG`d*&Zcwv^+ zIN!4x>2oz!<43Zr#>t-5NS~{*8c)o!8i#vU<5iy3SnFAh^tp=8$kBUNdV}>(?ywwD`=jq-19Xv!n{6nNto6Q74$pJx- gI4ZEeqT4WcdOxuOd#v|u-sG&Wc{N#I^LohtA5vB&#{d8T literal 0 HcmV?d00001 diff --git a/sound/recorder/recorder_logo_small.png b/sound/recorder/recorder_logo_small.png new file mode 100644 index 0000000000000000000000000000000000000000..b505a2f3ce2e561ce178c07de4d22685410e7861 GIT binary patch literal 4748 zcmV;75_9c|P)RncLU0t=55YbXe)4&U+W?~#g6al$k=JvdQ;B02k-ZMjqy;1wS)+}b8 z{oMBR{O-SJZv;?7ON9Vl!9pzt4E!Pl0v2N#4E#}HGM2!A!2kvf{DDm%ujt*oH*MOq zp`xOKyu3Wkb+g$_XlSUath&0Iy1F`JWev1k4KQZR7^IY(Jb99woE%P_I)#*yn{K*E zRd3?Ni4+$Xt3I{0wdCdH5fv4s)U#MDNGWwc8#iuL>Lny3DCL=%nM!$RXsA*?V88%l z*9=@e2ADm2HW?Wi0GvE|lGM~xE?l?(z@9yOm@{XNQrF>d03f9#H#e8u+*|;9_Uy^I zbLUh{P+eV(lu|PR_cHhXMvWRpe0;oe&1$s*;B-2TT{Cd?7+}MO4FGK2x|P0t`?6%o z5;}M8%!v~x0Ql!W|EcN3X0tJ5$Pfk%8pPnigO&23Lx-yB2_bmmi6;mO3Q|6E=g!si zCxigt`RAWEcF4f5#{i>8k5<0lci(-gii;L40-#&BZUhDfdL>$yq;@ZJNB8dCNlZ*6 zF)@)5BSz4!T{}%3tJTWs)2A6Za-?cb1`J$P2DtXxYXPv^?bOz)vr9QSIm-8b{ragr z>A*m~_~Hw`{PIhV9zCkt#%0>vfB*etW@eI^nMp=Q28oG@x@J*QQW5~Esj1j(He;s@ zT>U6ed3kvQSC~v1>D{?=XXSfwaj}|auu21rj&R|xvP`|e}Snl;L`C!c&$ac0k- zKdw@&tJ$z& z19RrgAvHCX>gs9^9y~}wLITOj$pEUbr8~}^JxfJJh2H_AqoWx+cC7Ndq@;xG>}*{# zsHCKX)vH&tWXTd^rwm*b2tZ?796o%Q0RskLGBvsg4u^xSTemW4(j=v9^5n^U`st_G z?RGkJ=-`zBEEWsJ#l?h#glMj1WMn7|F?8rq_V3@1)oLXoB7(}wN;-Awq|!M3`}gPA zv15(1e+7)ga0Z%11Go?y8%ub2I1?sJpj)?YKt{{JL+}Y$AraT5+>dD020Z?+KUv`7U^CO5CKG5BAGvEK8alt2@VM6 zNbwOi9NR$l#cXU&?@oSLP#BBi7BQ{QGzN4SfRvJgssgs;Z(+rO735dsBk}GZ^$+il zNhjaw#7R+25mmM->Kyu+`|fSK)7IQp_gYDP376_Fd2Q=LRO=`@1aL>V2-+6>ESNrN5e>0XkVaQ8=$qH!SNyMSTTn`Dx5Zo1wW@ zv!I6HfMB2PpW62nPwaa_Q$DuaSl%A@HjyEbNGVl)xPFVZ+I|B~f#l50Ato$_08@aj zi714isHTWJw%oz)bG!AKbCK`ut+myXTbfJ4`w5zB>66nL+kLFpvFq*i6x9}SZ~DFL zEZC{r|0|Mx{v zDW4kl6pvj0h_a#nj)AzFJV$07QO5Px)?_jvrDW~MwIp;(@VgF`)=DbsD>U~VVTs^h z!~f-7h+IC4O)Tw2LK*1aj?_TWnR(=6}7}XpRWMnh|Rl^v)pNjT1t!_TXAxJoKWf&(iu*l>|?@Aw}ua>1>pO z@Bi>Vrz=jA)Fp|eE=d}qcxT)@Dk1 zluBEr*LxrF;RuctAE8(KUVMM|_n4$f33fbo!(%M{W~r_Q5JGU^!U3jknM#k)9xNEN zfa!gwtL8ec`#7fdp2~+meyD3Q2_ZODc8Xg*zJ=g`;6@GWX3x8i=@L|7{|*D->0wWk zl8~azCqM)+D|(h@FMcrt1O){V8XBrO;@niY+R3A`q30kS(_l8>OLGkX870Bt)>Z;$ zkgxu7;&(xV6WvsyWv=>KO9w5RP3srj&0!y_qGum#}x*UV69h ztq>Q$yaDrg?%;D?*T5kg?)zlfNuK`pX`USRq>72cgTfVN_H_Dd?X~1r=96EU&sPOs z@o3hg9J=ceZOm<0j<`x!tS(dw1kurtJBKasUN#WH*T()-^4-R^e4wgoz zdPJ8ISHu8U#{`nVIv_yjS|1RxK5V?ZQ4{}V`&wiR$ZsAKNaFxoE41n!>9wt|2t=QD zedrn5Q`I&tKaJ)4m#c^$pt!DB<$R_lrD_;<)JLOK#IIEYS)t5{4msDEhZ-f8V zoc?OOs{+3l+K?ev^>Z6oL{xA`ZwwW{0GR@ zDYt^WSAtpRS~AdDM{C$XzR|qFsz6g9W|Nu0k%O7iYl_MqK3;a*=cX*XVHw2_6f2*y z|1MK}fMHR?v^<@DxAze7Wo8lx61ya-HvM?%arRx<=kq?+A6~Ee-L*|uTA5mTtsfu) z2oM281V^wsX|>9iusLm%Tg!jeI;Q_8ogd58+HmwW-VZQFhedO7-bK~=Jv!u3ze3Aw zGIMj+n~AhUs2Ll9v_(UM> z&Bp*Cfg$`f=O;|UM7vh)G>+=@Ez^BUq7ZWkA?6U>h)GmPl*ZpEtt<5}iG+!ezz~(0 zw*JWaCJ~^^E_Su++rBTkrMbHMvpsn`PU)m=tF{CM2C43C!lns7J9-9?U6f7l_Pv!c z+%=#(y+|n=m@gzkbv-yR*z1^~L7|+VcOJ7a6K)At=IeAiaYzSg`Dx9^09jdCOqnu8 zc`yYaCMJeet5#_ja{G2xuU@T6ZWR<1Xe2l90(WRlB$*`PE8yJavc;G6k@PU73PJ9? za^iPqT9e5{WJsijz=aUp{pH;%hqfuElsgdxm;zLFtPX3FL$#iL*V_H3xa%GD8iAyj zH*mq-es;f~=W?DS<4lH6lcyadbunXd{P`_hn3=|mt@OtdC@4Ug=8qdp+l3j)q~@-Lj5_I~V%w*NKzD>O!JgH=0o6dyJ_{nR#KM(w~YP@P| zwTd}Ck(Qsv_#Wex-*J&~O_ua}=oi+HfgJ{_x9!|6ul4iF^N86P(`2n(R8vG@bs>X0 zHa=;1L#G>>jTU~LL|8F!R)@&#z+@U;&E;wO1OcBmBOgk2e0j+GL#VbjJg4k*I+0TH z(QO|!DH`Dm2Z|18A`=e|dXVY8r|Z^#_tr)gm-0=DYAmPINoI1U*RejC@Ch;DF{*jK zc-VJH@Zql?=4i=LRZ=VSPnllLGJn{fyj_zgdGq+2KDCcOQ_$TcwFFw2_2n#8oun>F zJe&Az3t|9hi2d6<2wiw+1oyD#tD;$7+UPDNO~QoTX=iEHQiKr713=?@jAwEDV!tL( zr;tv>MZ^&s5ld`DEb$TXDm!&%+Dui}5()3$_CA{?ZsMMP_b~ao$^0euFPyyhBs2QV zP)X+>%YRfwW_pD7pz^^=<`0_Bjh$}f`pD~<(PswxXY6N6uPI9S(lyq)!|Qws0ZV{| znQ1c>r&I{RHEpip^GTok4SR-|Lx>5BAu%eEhvOcmZb2PUt)rA=AHd?T7gJ;RzHvbT zLG)?gM_Ierh*+ZAN2|tk&l^Z7IdKmN2yA&=z0Tn^HqJVIIx10ZyKU8 zn@?}%(8WWWWs;G#kZ!$Z5Hd)iNRQ^e8b8B86^|G#3avg;bLa=bh zLZ9}x%hbv($t5*ARdrNjLeB}@+Wl6qQ57jA*LS?0@9+6uH@agonaHom=Y@kW_#FSb z_SbRZo)fD3{^8OOM86g7v)$5fma-^*k!sAWX<3B*JM4;b0l(^5Ah|_CIo{8o%7(Bf zYx&jAsCr6kDJ2JI9`tGgd5dJYXFdUjyf=iy#fN=HL-hLk=KMF@zWH`dbjqJo|KZ6G zdHKl8O}_7?Sxd1wY^rp@%y!1G|-sq)kHhJEMXJ1yQ)$f=!_8Q{e ziBt7q4luKS`u-MT0=ee~yhZ6;8Q+V|JETCUUd9z@YE*oA6?y#i>%Xe<03Aa*vg1!X zlsaaUS*4OaKQ6P%Q_{x28_#1|k9qY&ykYa{&5ZtdwBn=qJ4mHCyAu65G8U)T4t`ZDJ4m`}{c7~L$gD_J3D^#I4_sv>&cpc%v;VMEm z2@_pgccq}ZfM>pYhM<5TpJVJiyHmG(<##Jd%}HhXu;q;GI+6%W1SVmktiFsBmrn4~ z;g|ILE7(cf|7pwO_{H4W_fERB?m}p*P=pZF*lRdneV(rhzT)qD{_gcb9)RWFE^o|# z2ops$jmMs|FJ`lF$3nWc>8cVIW4etY<4gu`9e;~&&wr~c)i2dwVpqW~znSXKPk&BH zU5U>l5a(+epZMExb_XV5Que3Lt`19&{CFg*5?85?qqGlde+9zPkFha)_;9kavNYuz zHf+#+sg+->0$O5(5T)Hw+L8 z@R8P87JX7V}lI*4j4dOFQC1S)R(|Z zz?*0iVc3EDjSVu;(ixx)$azwG)WHPe4bkxM%eO$4j@D=k%rrL1KuczTX$_98M#5hJ znRA&doIontpsW+Pslk6RV4&qOz#t$&$MkUmp0EBd1-{eK0#0BFVEDuaS{wsR13Ysy zfgpAW&^x~Irkiizj&>jt4Gu8Sf*3&DDIiQoau. + * + * Copyright 2014 Kjell Kernen */ + +using System; +using System.Collections.Generic; +using System.Configuration; +using System.Data; +using System.Linq; +using System.Windows; + +namespace OpenTXrecorder +{ + public class SentenceTables + { + private static string[] default_pl_system_strings = + { + "0000;0;0", + "0001;1;1", + "0002;2;2", + "0003;3;3", + "0004;4;4", + "0005;5;5", + "0006;6;6", + "0007;7;7", + "0008;8;8", + "0009;9;9", + "0010;10;10", + "0011;11;11", + "0012;12;12", + "0013;13;13", + "0014;14;14", + "0015;15;15", + "0016;16;16", + "0017;17;17", + "0018;18;18", + "0019;19;19", + "0020;20;20", + "0021;21;21", + "0022;22;22", + "0023;23;23", + "0024;24;24", + "0025;25;25", + "0026;26;26", + "0027;27;27", + "0028;28;28", + "0029;29;29", + "0030;30;30", + "0031;31;31", + "0032;32;32", + "0033;33;33", + "0034;34;34", + "0035;35;35", + "0036;36;36", + "0037;37;37", + "0038;38;38", + "0039;39;39", + "0040;40;40", + "0041;41;41", + "0042;42;42", + "0043;43;43", + "0044;44;44", + "0045;45;45", + "0046;46;46", + "0047;47;47", + "0048;48;48", + "0049;49;49", + "0050;50;50", + "0051;51;51", + "0052;52;52", + "0053;53;53", + "0054;54;54", + "0055;55;55", + "0056;56;56", + "0057;57;57", + "0058;58;58", + "0059;59;59", + "0060;60;60", + "0061;61;61", + "0062;62;62", + "0063;63;63", + "0064;64;64", + "0065;65;65", + "0066;66;66", + "0067;67;67", + "0068;68;68", + "0069;69;69", + "0070;70;70", + "0071;71;71", + "0072;72;72", + "0073;73;73", + "0074;74;74", + "0075;75;75", + "0076;76;76", + "0077;77;77", + "0078;78;78", + "0079;79;79", + "0080;80;80", + "0081;81;81", + "0082;82;82", + "0083;83;83", + "0084;84;84", + "0085;85;85", + "0086;86;86", + "0087;87;87", + "0088;88;88", + "0089;89;89", + "0090;90;90", + "0091;91;91", + "0092;92;92", + "0093;93;93", + "0094;94;94", + "0095;95;95", + "0096;96;96", + "0097;97;97", + "0098;98;98", + "0099;99;99", + "0100;100;100", + "0101;200;200", + "0102;300;300", + "0103;400;400", + "0104;500;500", + "0105;600;600", + "0106;700;700", + "0107;800;800", + "0108;900;900", + "0109;;1000", + "0110;TISIACE;tisiace", + "0111;JEDNA;jedna", + "0112;JEDNO;jedno", + "0113;DWIE;dwie", + "0114;CALA;cela", + "0115;CALE;cale", + "0116;CALYCH;calych", + "0117;MINUS;minus", + + "0120;Female number;", + "0121;Female number;", + "0122;Female number;", + "0123;Female number;", + "0124;Female number;", + "0125;Female number;", + "0126;Female number;", + "0127;Female number;", + "0128;Female number;", + "0129;Female number;", + + "0160;volt 1;wolt", + "0161;volt 2;wolty", + "0162;volt 3;", + "0163;volt 4;", + "0164;amps 1;", + "0165;amps 2;", + "0166;amps 3;", + "0167;amps 4;", + "0168;mps 1;", + "0169;mps 2;", + "0170;mps 3;", + "0171;mps 4;", + "0172;spare 1;", + "0173;spare 2;", + "0174;spare 3;", + "0175;spare 4;", + "0176;kmh 1;", + "0177;kmh 2;", + "0178;kmh 3;", + "0179;kmh 4;", + "0180;meter 1;", + "0181;meter 2;", + "0182;meter 3;", + "0183;meter 4;", + "0184;degrees 1;", + "0185;degrees 2;", + "0186;degrees 3;", + "0187;degrees 4;", + "0188;percent 1;", + "0189;percent 2;", + "0190;percent 3;", + "0191;percent 4;", + "0192;milliamps 1;", + "0193;milliamps 2;", + "0194;milliamps 3;", + "0195;milliamps 4;", + "0196;mAh 1;", + "0197;mAh 2;", + "0198;mAh 3;", + "0199;mAh 4;", + "0200;watt 1;", + "0201;watt 2;", + "0202;watt 3;", + "0203;watt 4;", + "0204;db 1;", + "0205;db 2;", + "0206;db 3;", + "0207;db 4;", + "0208;feet 1;", + "0209;feet 2;", + "0210;feet 3;", + "0211;feet 4;", + "0212;knot 1;", + "0213;knot 2;", + "0214;knot 3;", + "0215;knot 4;", + "0216;hours 1;", + "0217;hours 2;", + "0218;hours 3;", + "0219;hours 4;", + "0220;minutes 1;", + "0221;minutes 2;", + "0222;minutes 3;", + "0223;minutes 4;", + "0224;secondds 1;", + "0225;secondds 2;", + "0226;secondds 3;", + "0227;secondds 4;", + "0228;rpm 1;", + "0229;rpm 2;", + "0230;rpm 3;", + "0231;rpm 4;", + "0232;g 1;", + "0233;g 2;", + "0234;g 3;", + "0235;g 4;", + "0250;Timer1;", + "0251;Timer2;", + "0252;RSSI Tx;", + "0253;RSSI Rx;", + "0254;A1;", + "0255;A2;", + "0256;Altitude;", + "0257;RPM;", + "0258;Fuel;", + "0259;T1;", + "0260;T2;", + "0261;Speed;", + "0262;Distance;", + "0263;GPS Altitude;", + "0264;LiPo Elements;", + "0265;LiPo Total;", + "0266;VFAS;", + "0267;Current;", + "0268;Consumption;", + "0269;Telemetry Power;", + "0270;Accel X;", + "0271;Accel Y;", + "0272;Accel Z;", + "0217;HDG;", + "0218;Vario;", + }; + + private static string[] default_pl_other_strings = + { + "atti;attitude;", + "batcrit;battery critical;", + "batlow;low battery;", + "camcenter;camera center;", + "camfix;camera fixed;", + "cammanual;camera manual;", + "flapsdn;flaps down;", + "flapsup;flaps up;", + "fltmode1;flight mode 1;", + "fltmode2;flight mode 2;", + "fltmode3;flight mode 3;", + "fltmode4;flight mode 4;", + "fltmode5;flight mode 5;", + "fltmode6;flight mode 6;", + "fltmode7;flight mode 7;", + "fltmode8;flight mode 8;", + "fltmode9;flight mode 9;", + "fsoff;failsafe off;", + "fson;failsafe on;", + "geardn;gear down;", + "gearup;gear upp;", + "gps;gps;", + "hirates;hi rates;", + "htoff;head tracker off;", + "hton;head tracker on;", + "ioc;ioc;", + "iocoff;ioc off;", + "lowrates;lowrates;", + "manual;manual;", + "normal;normal;", + "nrmmod;normal mode;", + "thrhold;throttle locked;", + "thrrel;throttle released;", + }; + + private static string[] default_sk_system_strings = + { + "0000;0;0", + "0001;1;jedna", + "0002;2;dva", + "0003;3;3", + "0004;4;4", + "0005;5;5", + "0006;6;6", + "0007;7;7", + "0008;8;8", + "0009;9;9", + "0010;10;10", + "0011;11;11", + "0012;12;12", + "0013;13;13", + "0014;14;14", + "0015;15;15", + "0016;16;16", + "0017;17;17", + "0018;18;18", + "0019;19;19", + "0020;20;20", + "0021;21;21", + "0022;22;22", + "0023;23;23", + "0024;24;24", + "0025;25;25", + "0026;26;26", + "0027;27;27", + "0028;28;28", + "0029;29;29", + "0030;30;30", + "0031;31;31", + "0032;32;32", + "0033;33;33", + "0034;34;34", + "0035;35;35", + "0036;36;36", + "0037;37;37", + "0038;38;38", + "0039;39;39", + "0040;40;40", + "0041;41;41", + "0042;42;42", + "0043;43;43", + "0044;44;44", + "0045;45;45", + "0046;46;46", + "0047;47;47", + "0048;48;48", + "0049;49;49", + "0050;50;50", + "0051;51;51", + "0052;52;52", + "0053;53;53", + "0054;54;54", + "0055;55;55", + "0056;56;56", + "0057;57;57", + "0058;58;58", + "0059;59;59", + "0060;60;60", + "0061;61;61", + "0062;62;62", + "0063;63;63", + "0064;64;64", + "0065;65;65", + "0066;66;66", + "0067;67;67", + "0068;68;68", + "0069;69;69", + "0070;70;70", + "0071;71;71", + "0072;72;72", + "0073;73;73", + "0074;74;74", + "0075;75;75", + "0076;76;76", + "0077;77;77", + "0078;78;78", + "0079;79;79", + "0080;80;80", + "0081;81;81", + "0082;82;82", + "0083;83;83", + "0084;84;84", + "0085;85;85", + "0086;86;86", + "0087;87;87", + "0088;88;88", + "0089;89;89", + "0090;90;90", + "0091;91;91", + "0092;92;92", + "0093;93;93", + "0094;94;94", + "0095;95;95", + "0096;96;96", + "0097;97;97", + "0098;98;98", + "0099;99;99", + "0100;100;100", + "0101;200;200", + "0102;300;300", + "0103;400;400", + "0104;500;500", + "0105;600;600", + "0106;700;700", + "0107;800;800", + "0108;900;900", + "0109;1000;1000", + "0110;2000;dvetisíc;", + "0111;JEDEN;jeden", + "0112;JEDNO;jedno", + "0113;DVE;dve", + "0114;CELA;celá", + "0115;CELE;celá", + "0116;CELYCH;celýnch", + "0117;MINUS;minus", + "0118;volt 1;volt", + "0119;volt 2;volty", + "0120;volt 3;voltov", + "0121;volt 4;volta", + "0122;amps 1;ampér", + "0123;amps 2;ampére", + "0124;amps 3;ampérov", + "0125;amps 4;ampéra", + "0126;mps 1;meter za sekundu", + "0127;mps 2;metre za sekundu", + "0128;mps 3;metrov za sekundu", + "0129;mps 4;metra za sekundu", + "0130;spare 1;jednotka", + "0131;spare 2;jednotky", + "0132;spare 3;jednotiek", + "0133;spare 4;jednotky", + "0134;kmh 1;kilometer za hodinu", + "0135;kmh 2;kilometre za hodinu", + "0136;kmh 3;kilometrov za hodinu", + "0137;kmh 4;kilometra za hodinu", + "0138;meter 1;meter", + "0139;meter 2;metre", + "0140;meter 3;metrov", + "0141;meter 4;metra", + "0142;degrees 1;stupeň", + "0143;degrees 2;stupně", + "0144;degrees 3;stupňov", + "0145;degrees 4;stupňa", + "0146;percent 1;percento", + "0147;percent 2;percentá", + "0148;percent 3;percent", + "0149;percent 4;percenta", + "0150;milliamps 1;miliampér", + "0151;milliamps 2;miliampére", + "0152;milliamps 3;miliampérov", + "0153;milliamps 4;miliampéra", + "0154;mAh 1;miliampérhodina", + "0155;mAh 2;miliampérhodiny", + "0156;mAh 3;miliampérhodín", + "0157;mAh 4;miliampérhodiny", + "0158;watt 1;vat", + "0159;watt 2;vaty", + "0160;watt 3;vatov", + "0161;watt 4;vatu", + "0162;db 1;decibel", + "0163;db 2;decibely", + "0164;db 3;decibelov", + "0165;db 4;decibela", + "0166;feet 1;stopa", + "0167;feet 2;stopy", + "0168;feet 3;stuop", + "0169;feet 4;stopy", + "0170;knot 1;uzol", + "0171;knot 2;uzly", + "0172;knot 3;uzlov", + "0173;knot 4;uzla", + "0174;hours 1;hodina", + "0175;hours 2;hodiny", + "0176;hours 3;hodín", + "0177;hours 4;hodiny", + "0178;minutes 1;minůta", + "0179;minutes 2;minůty", + "0180;minutes 3;minůt", + "0181;minutes 4;minůty", + "0182;secondds 1;sekunda", + "0183;secondds 2;sekundy", + "0184;secondds 3;sekund", + "0185;secondds 4;sekundy", + "0186;rpm 1;otáčka za minůtu", + "0187;rpm 2;otáčky za minůtu", + "0188;rpm 3;otáčok za minůtu", + "0189;rpm 4;otáčky za minůtu", + "0190;g 1;gé", + "0191;g 2;gé", + "0192;g 3;gé", + "0193;g 4;gé", + "a1_org;a1 low;", + "a1_red;a1 critical;", + "a2_org;a2 low;", + "a2_red;a2 critical;", + "endtrim;maximum trim reached;", + "inactiv;inactivity alarm;", + "lowbatt;radio battery low;", + "midtrim;trim center;", + "rssi_org;rf signal low;", + "rssi_red;rf signal critical;", + "swalert;switch warning;", + "swr_red;radio antenna defective;", + "tada;Start Sound;", + "telemko;telemetry lost;", + "telemok;telemetry recover;", + "thralert;throttle warning;", + "timer10;10 seconds;", + "timer20;20 seconds;", + "timer30;30 seconds;", + "timerlt3;timer sound;" + }; + + private static string[] default_sk_other_strings = + { + "atti;attitude;", + "batcrit;battery critical;", + "batlow;low battery;", + "camcenter;camera center;", + "camfix;camera fixed;", + "cammanual;camera manual;", + "flapsdn;flaps down;", + "flapsup;flaps up;", + "fltmode1;flight mode 1;", + "fltmode2;flight mode 2;", + "fltmode3;flight mode 3;", + "fltmode4;flight mode 4;", + "fltmode5;flight mode 5;", + "fltmode6;flight mode 6;", + "fltmode7;flight mode 7;", + "fltmode8;flight mode 8;", + "fltmode9;flight mode 9;", + "fsoff;failsafe off;", + "fson;failsafe on;", + "geardn;gear down;", + "gearup;gear upp;", + "gps;gps;", + "hirates;hi rates;", + "htoff;head tracker off;", + "hton;head tracker on;", + "ioc;ioc;", + "iocoff;ioc off;", + "lowrates;lowrates;", + "manual;manual;", + "normal;normal;", + "nrmmod;normal mode;", + "thrhold;throttle locked;", + "thrrel;throttle released;" + }; + + private static string[] default_es_system_strings = + { + "0000;0;0", + "0001;1;1", + "0002;2;2", + "0003;3;3", + "0004;4;4", + "0005;5;5", + "0006;6;6", + "0007;7;7", + "0008;8;8", + "0009;9;9", + "0010;10;10", + "0011;11;11", + "0012;12;12", + "0013;13;13", + "0014;14;14", + "0015;15;15", + "0016;16;16", + "0017;17;17", + "0018;18;18", + "0019;19;19", + "0020;20;20", + "0021;21;21", + "0022;22;22", + "0023;23;23", + "0024;24;24", + "0025;25;25", + "0026;26;26", + "0027;27;27", + "0028;28;28", + "0029;29;29", + "0030;30;30", + "0031;31;31", + "0032;32;32", + "0033;33;33", + "0034;34;34", + "0035;35;35", + "0036;36;36", + "0037;37;37", + "0038;38;38", + "0039;39;39", + "0040;40;40", + "0041;41;41", + "0042;42;42", + "0043;43;43", + "0044;44;44", + "0045;45;45", + "0046;46;46", + "0047;47;47", + "0048;48;48", + "0049;49;49", + "0050;50;50", + "0051;51;51", + "0052;52;52", + "0053;53;53", + "0054;54;54", + "0055;55;55", + "0056;56;56", + "0057;57;57", + "0058;58;58", + "0059;59;59", + "0060;60;60", + "0061;61;61", + "0062;62;62", + "0063;63;63", + "0064;64;64", + "0065;65;65", + "0066;66;66", + "0067;67;67", + "0068;68;68", + "0069;69;69", + "0070;70;70", + "0071;71;71", + "0072;72;72", + "0073;73;73", + "0074;74;74", + "0075;75;75", + "0076;76;76", + "0077;77;77", + "0078;78;78", + "0079;79;79", + "0080;80;80", + "0081;81;81", + "0082;82;82", + "0083;83;83", + "0084;84;84", + "0085;85;85", + "0086;86;86", + "0087;87;87", + "0088;88;88", + "0089;89;89", + "0090;90;90", + "0091;91;91", + "0092;92;92", + "0093;93;93", + "0094;94;94", + "0095;95;95", + "0096;96;96", + "0097;97;97", + "0098;98;98", + "0099;99;99", + "0100;100;100", + "0101;;ciento", + "0102;;doscientos", + "0103;;trescientos", + "0104;;cuatrocientos", + "0105;;quinientos", + "0106;;sescientos", + "0107;;setecientos", + "0108;;ochocientos", + "0109;;nuevecientos", + "0110;;mil", + "0111;;coma", + "0112;;un", + "0113;;una", + "0114;;y", + "0115;;meno", + "0116;;hora", + "0117;;horas", + "0118;;minuto", + "0119;;minutos", + "0120;;segundo", + "0121;;segundos", + "0122;;Voltio", + "0123;;ampério", + "0124;;metros por segundo", + "0125;;", + "0126;;kilómetro por hora", + "0127;;metros", + "0128;;grados", + "0129;;por ciento", + "0130;;miliamperios", + "0131;;miliamperios por hora", + "0132;;vatio", + "0133;;db", + "0134;;pés", + "0135;;nós", + "0136;;horas", + "0137;;minutos", + "0138;;segundos", + "0139;;RPM", + "0140;;g", + "0141;;cronómetro", + "0142;;cronómetro", + "0143;;transmisión", + "0144;;recepción", + "0145;;A1", + "0146;;A2", + "0147;;altitud", + "0148;;motor", + "0149;;combustible", + "0150;;temperatura", + "0151;;temperatura", + "0152;;velocidad", + "0153;;distancia", + "0154;;altitude", + "0155;;célula lipo", + "0156;;Total lipo", + "0157;;voltaje", + "0158;;corriente", + "0159;;consumo", + "0160;;potencia", + "0161;;aceleración X", + "0162;;aceleración Y", + "0163;;aceleración Z", + "0164;;dirección", + "0165;;variómetro", + "0166;;minimo", + "0167;;máximo", + "a1_org;;Alarma A1", + "a1_red;;A1 crítica", + "a2_org;;Alarma A2", + "a2_red;;A2 crítica", + "eebad;;eeprom corrompida", + "eeformat;;Formateo de eeprom en curso", + "endtrim;;trim al máximo", + "error;;error", + "highmah;;assorbimiento elevado", + "hightemp;;temperatura elevada", + "inactiv;;me tienes abandonada", + "lowbatt;;batería del transmisor baja", + "midpot;;potenciómetro centrado", + "midtrim;;trim centrado", + "rssi_org;;recepcion de señal baja", + "rssi_red;;recepción de señal crítica", + "swr_red;;Problemas con la antena del transmisor", + "swalert;;Los interruptores no están en la posición correcta, por favor corrijalo", + "tada;OpenTX Welcome sound;Bienvenida a OpenTX", + "telemko;;Sin telemetría", + "telemok;;Telemetría disponible", + "thralert;;El acelerador está activado, por favor, corrijalo", + "timer10;;10 segundos", + "timer20;;20 segundos", + "timer30;;30 segundos", + "timerlt3;;3 segundos" + }; + + private static string[] default_es_other_strings = + { + "attero;;aterrizaje", + "crowof;;crou, desligado", + "crowon;;crou, activo", + "engoff;;motor apagado", + "flapdn;;flaps abajo", + "flapup;;flaps arriba", + "fltmd1;;fase de vuelo 1", + "fltmd2;;fase de vuelo 2", + "fltmd3;;fase de vuelo 3", + "fltmd4;;fase de vuelo 4", + "fltmd5;;fase de vuelo 5", + "fltmd6;;fase de vuelo 6", + "fltmd7;;fase de vuelo 7", + "fltmd8;;fase de vuelo 8", + "fltmd9;;fase de vuelo 9", + "geardn;;tren abajo.", + "gearup;;tren arriba.", + "lowbat;;bateria baja", + "nrmmod;;modo de vuelo normal", + "spdmod;;modo de velocidad", + "thmmod;;modo de térmica", + "trnoff;;modo de entrenamiento deshabilitado", + "trnon;;modo de entrenamiento activado", + "tohigh;;muy alto", + "tolow;;muy bajo" + }; + + private static string[] default_pt_system_strings = + { + "0000;0;0", + "0001;1;1", + "0002;2;2", + "0003;3;3", + "0004;4;4", + "0005;5;5", + "0006;6;6", + "0007;7;7", + "0008;8;8", + "0009;9;9", + "0010;10;10", + "0011;11;11", + "0012;12;12", + "0013;13;13", + "0014;14;14", + "0015;15;15", + "0016;16;16", + "0017;17;17", + "0018;18;18", + "0019;19;19", + "0020;20;20", + "0021;21;21", + "0022;22;22", + "0023;23;23", + "0024;24;24", + "0025;25;25", + "0026;26;26", + "0027;27;27", + "0028;28;28", + "0029;29;29", + "0030;30;30", + "0031;31;31", + "0032;32;32", + "0033;33;33", + "0034;34;34", + "0035;35;35", + "0036;36;36", + "0037;37;37", + "0038;38;38", + "0039;39;39", + "0040;40;40", + "0041;41;41", + "0042;42;42", + "0043;43;43", + "0044;44;44", + "0045;45;45", + "0046;46;46", + "0047;47;47", + "0048;48;48", + "0049;49;49", + "0050;50;50", + "0051;51;51", + "0052;52;52", + "0053;53;53", + "0054;54;54", + "0055;55;55", + "0056;56;56", + "0057;57;57", + "0058;58;58", + "0059;59;59", + "0060;60;60", + "0061;61;61", + "0062;62;62", + "0063;63;63", + "0064;64;64", + "0065;65;65", + "0066;66;66", + "0067;67;67", + "0068;68;68", + "0069;69;69", + "0070;70;70", + "0071;71;71", + "0072;72;72", + "0073;73;73", + "0074;74;74", + "0075;75;75", + "0076;76;76", + "0077;77;77", + "0078;78;78", + "0079;79;79", + "0080;80;80", + "0081;81;81", + "0082;82;82", + "0083;83;83", + "0084;84;84", + "0085;85;85", + "0086;86;86", + "0087;87;87", + "0088;88;88", + "0089;89;89", + "0090;90;90", + "0091;91;91", + "0092;92;92", + "0093;93;93", + "0094;94;94", + "0095;95;95", + "0096;96;96", + "0097;97;97", + "0098;98;98", + "0099;99;99", + "0100;100;100", + "0101;;cento", + "0102;;duzentos", + "0103;;trezentos", + "0104;;quatrocentos", + "0105;;quinhentos", + "0106;;seiscentos", + "0107;;setecentos", + "0108;;oitocentos", + "0109;;novecentos", + "0110;;mil", + "0111;;virgula", + "0112;;uma", + "0113;;duas", + "0114;;e", + "0115;;menos", + "0116;;hora", + "0117;;horas", + "0118;;minuto", + "0119;;minutos", + "0120;;segundo", + "0121;;segundos", + "0122;;Volt", + "0123;;ampére", + "0124;;metros por segundo", + "0125;;", + "0126;;quilômetros por hora", + "0127;;metros", + "0128;;graus", + "0129;;cento", + "0130;;miliamperes", + "0131;;miliamperes por hora", + "0132;;watt", + "0133;;db", + "0134;;pés", + "0135;;nós", + "0136;;horas", + "0137;;minutos", + "0138;;segundos", + "0139;;RPM", + "0140;;g", + "0141;;cronómetro", + "0142;;cronómetro", + "0143;;transmissão", + "0144;;recepção", + "0145;;A1", + "0146;;A2", + "0147;;altitude", + "0148;;motor", + "0149;;combustível", + "0150;;temperatura", + "0151;;temperatura", + "0152;;velocidade", + "0153;;distância", + "0154;;altitude", + "0155;;célula lipo", + "0156;;Total lipo", + "0157;;tensão", + "0158;;corrente", + "0159;;consumo", + "0160;;potência", + "0161;;aceleração X", + "0162;;aceleração Y", + "0163;;aceleração Z", + "0164;;Direcção", + "0165;;variómetro", + "0166;;mínimo", + "0167;;máximo", + "a1_org;;Alarme A1", + "a1_red;;A1 critica", + "a2_org;;Alarme A2", + "a2_red;;A2 critica", + "eebad;;eeprom corrompida", + "eeformat;;formatação da eeprom em curso", + "endtrim;;trim no máximo", + "error;;erro", + "highmah;;assorbimento elevato", + "hightemp;;temperatura elevata", + "inactiv;;atenção, o rádio foi esquecido ligado, por favor desligue-o", + "midtrim;;trim centrado", + "midpot;;potenciómetro centrado", + "lowbatt;;bateria do rádio fraca", + "rssi_org;;recepção de sinal muito baixa", + "rssi_red;;recepção de sinal crítica", + "swalert;;atenção, certifique-se que os interruptores estão na posição certa", + "swr_red;;Problema com a antena do transmissor", + "tada;;Bem-vindo ao OpenTX", + "thralert;;atenção,acelerador não está no mínimo", + "timer10;;10 segundos", + "timer20;;20 segundos", + "timer30;;30 segundos", + "timerlt3;;três segundo" + }; + + private static string[] default_pt_other_strings = + { + "attero;;aterragem", + "crowof;;crou, desligado", + "crowon;;crou, activo", + "engoff;;motor desligado", + "flapdn;;flaps estendidos", + "flapup;;flaps recolhidos", + "fltmd1;;fase de voo 1", + "fltmd2;;fase de voo 2", + "fltmd3;;fase de voo 3", + "fltmd4;;fase de voo 4", + "fltmd5;;fase de voo 5", + "fltmd6;;fase de vôo 6", + "fltmd7;;fase de voo 7", + "fltmd8;;fase de voo 8", + "fltmd9;;fase de voo 9", + "geardn;;trem, em baixo.", + "gearup;;trem, em cima.", + "lowbat;;bateria fraca", + "nrmmod;;modo de voo normal", + "sigcrt;;sinal crítico", + "siglow;;sinal baixo", + "spdmod;;modo de velocidade", + "thmmod;;modo de térmica", + "trnoff;;modo de treino desligado", + "trnon;;modo de treino ligado", + "tohigh;;muito alto", + "tolow;;muito baixo" + }; + + private static string[] default_cz_system_strings = + { + "0000;0;nula", + "0001;1;jedna", + "0002;2;dva", + "0003;3;3", + "0004;4;4", + "0005;5;5", + "0006;6;6", + "0007;7;7", + "0008;8;8", + "0009;9;9", + "0010;10;10", + "0011;11;11", + "0012;12;12", + "0013;13;13", + "0014;14;14", + "0015;15;15", + "0016;16;16", + "0017;17;17", + "0018;18;18", + "0019;19;19", + "0020;20;20", + "0021;21;21", + "0022;22;22", + "0023;23;23", + "0024;24;24", + "0025;25;25", + "0026;26;26", + "0027;27;27", + "0028;28;28", + "0029;29;29", + "0030;30;30", + "0031;31;31", + "0032;32;32", + "0033;33;33", + "0034;34;34", + "0035;35;35", + "0036;36;36", + "0037;37;37", + "0038;38;38", + "0039;39;39", + "0040;40;40", + "0041;41;41", + "0042;42;42", + "0043;43;43", + "0044;44;44", + "0045;45;45", + "0046;46;46", + "0047;47;47", + "0048;48;48", + "0049;49;49", + "0050;50;50", + "0051;51;51", + "0052;52;52", + "0053;53;53", + "0054;54;54", + "0055;55;55", + "0056;56;56", + "0057;57;57", + "0058;58;58", + "0059;59;59", + "0060;60;60", + "0061;61;61", + "0062;62;62", + "0063;63;63", + "0064;64;64", + "0065;65;65", + "0066;66;66", + "0067;67;67", + "0068;68;68", + "0069;69;69", + "0070;70;70", + "0071;71;71", + "0072;72;72", + "0073;73;73", + "0074;74;74", + "0075;75;75", + "0076;76;76", + "0077;77;77", + "0078;78;78", + "0079;79;79", + "0080;80;80", + "0081;81;81", + "0082;82;82", + "0083;83;83", + "0084;84;84", + "0085;85;85", + "0086;86;86", + "0087;87;87", + "0088;88;88", + "0089;89;89", + "0090;90;90", + "0091;91;91", + "0092;92;92", + "0093;93;93", + "0094;94;94", + "0095;95;95", + "0096;96;96", + "0097;97;97", + "0098;98;98", + "0099;99;99", + "0100;;sto", + "0101;;dvěsta", + "0102;;třista", + "0103;;čtyřista", + "0104;;pětset", + "0105;;šestset", + "0106;;sedmset", + "0107;;osmset", + "0108;;devětset", + "0109;;tisíc", + "0110;;tisíce", + "0111;;jeden", + "0112;;jedno", + "0113;;dvě", + "0114;;celá", + "0115;;celé", + "0116;;celých", + "0117;;mínus", + "0118;;volt", + "0119;;volty", + "0120;;voltů", + "0121;;voltu", + "0122;;ampér", + "0123;;ampéry", + "0124;;ampérů", + "0125;;ampéru", + "0126;;metr za sekundu", + "0127;;metry za sekundu", + "0128;;metrů za sekundu", + "0129;;metru za sekundu", + "0130;;jednotka", + "0131;;jednotky", + "0132;;jednotek", + "0133;;jednotky", + "0134;;kilometr za hodinu", + "0135;;kilometry za hodinu", + "0136;;kilometrů za hodinu", + "0137;;kilometru za hodinu", + "0138;;metr", + "0139;;metry", + "0140;;metrů", + "0141;;metru", + "0142;;stupeň", + "0143;;stupně", + "0144;;stupňů", + "0145;;stupně", + "0146;;procento", + "0147;;procenta", + "0148;;procento", + "0149;;procenta", + "0150;;miliampér", + "0151;;miliampéry", + "0152;;miliampérů", + "0153;;miliampéru", + "0154;;miliampérhodina", + "0155;;miliampérhodiny", + "0156;;miliampérhodin", + "0157;;miliampérhodiny", + "0158;;vat", + "0159;;vaty", + "0160;;vatů", + "0161;;vatu", + "0162;;decibel", + "0163;;decibely", + "0164;;decibelů", + "0165;;decibelu", + "0166;;stopa", + "0167;;stopy", + "0168;;stop", + "0169;;stopy", + "0170;;uzel", + "0171;;uzly", + "0172;;uzlů", + "0173;;uzlu", + "0174;;hodina", + "0175;;hodiny", + "0176;;hodin", + "0177;;hodiny", + "0178;;minuta", + "0179;;minuty", + "0180;;minut", + "0181;;minuty", + "0182;;sekunda", + "0183;;sekundy", + "0184;;sekund", + "0185;;sekundy", + "0186;;otáčka za minutu", + "0187;;otáčky za minutu", + "0188;;otáček za minutu", + "0189;;otáčky za minutu", + "0190;;gé", + "0191;;gé", + "0192;;gé", + "0193;;gé", + "a1_org;;A1,nízká", + "a1_red;;A1,kritická", + "a2_org;;A2,nízká", + "a2_red;;A2,kritická", + "eebad;;neplatná eeprom", + "endtrim;;maximum trimu", + "inactiv;;zapoměl jsi na mě!", + "lowbatt;;baterie rádia je vybitá", + "midtrim;;střed trimu", + "rssi_org;;nízký RF signál", + "rssi_red;;kritický RF signál", + "swalert;;přepínače nejsou ve výchozí poloze", + "swr_red;;problém s anténou rádia", + "tada;;Oupn najn iks", + "telemko;;telemetrie ztracena", + "telemok;;telemetrie je funkční", + "thralert;;plyn není na nule", + "timer10;;deset sekund", + "timer20;;dvacet sekund", + "timer30;;třicet sekund", + "timerlt3;;tři sekund!" + }; + + private static string[] default_cz_other_strings = + { + "bytvybita;;baterie modelu je vybitá", + "klapky0;;klapky jsou vypnuty", + "klapky1;;klapky jsou zapnuty", + "ksignal;;kritický signál!", + "motor0;;motor je vypnut", + "motor1;;motor je aktivován", + "nizko;;jsi příliš nízko", + "nsignal;;nízký signál!", + "palivo;;dochází palivo", + "podvozek0;;podvozek je zasunut", + "podvozek1;;podvozek je vysunut", + "r_norm;;normální režim aktivován", + "r_pristani;;režim přistání aktivován", + "r_rychly;;rychlý režim aktivován", + "r_start;;režim start aktivován", + "r_termik;;termický režim aktivován", + "stpovolen;;start povolen", + "trener0;;trenér je vypnutý", + "trener1;;trenér je zapnut", + "vario0;;vario je zapnuto", + "vario1;;vario je vypnuto", + "vysoko;;jsi příliš vysoko" + }; + + private static string[] default_en_system_strings = + { + "0000;0;0", + "0001;1;1", + "0002;2;2", + "0003;3;3", + "0004;4;4", + "0005;5;5", + "0006;6;6", + "0007;7;7", + "0008;8;8", + "0009;9;9", + "0010;10;10", + "0011;11;11", + "0012;12;12", + "0013;13;13", + "0014;14;14", + "0015;15;15", + "0016;16;16", + "0017;17;17", + "0018;18;18", + "0019;19;19", + "0020;20;20", + "0021;21;21", + "0022;22;22", + "0023;23;23", + "0024;24;24", + "0025;25;25", + "0026;26;26", + "0027;27;27", + "0028;28;28", + "0029;29;29", + "0030;30;30", + "0031;31;31", + "0032;32;32", + "0033;33;33", + "0034;34;34", + "0035;35;35", + "0036;36;36", + "0037;37;37", + "0038;38;38", + "0039;39;39", + "0040;40;40", + "0041;41;41", + "0042;42;42", + "0043;43;43", + "0044;44;44", + "0045;45;45", + "0046;46;46", + "0047;47;47", + "0048;48;48", + "0049;49;49", + "0050;50;50", + "0051;51;51", + "0052;52;52", + "0053;53;53", + "0054;54;54", + "0055;55;55", + "0056;56;56", + "0057;57;57", + "0058;58;58", + "0059;59;59", + "0060;60;60", + "0061;61;61", + "0062;62;62", + "0063;63;63", + "0064;64;64", + "0065;65;65", + "0066;66;66", + "0067;67;67", + "0068;68;68", + "0069;69;69", + "0070;70;70", + "0071;71;71", + "0072;72;72", + "0073;73;73", + "0074;74;74", + "0075;75;75", + "0076;76;76", + "0077;77;77", + "0078;78;78", + "0079;79;79", + "0080;80;80", + "0081;81;81", + "0082;82;82", + "0083;83;83", + "0084;84;84", + "0085;85;85", + "0086;86;86", + "0087;87;87", + "0088;88;88", + "0089;89;89", + "0090;90;90", + "0091;91;91", + "0092;92;92", + "0093;93;93", + "0094;94;94", + "0095;95;95", + "0096;96;96", + "0097;97;97", + "0098;98;98", + "0099;99;99", + "0100;100;100", + "0101;200;200", + "0102;300;300", + "0103;400;400", + "0104;500;500", + "0105;600;600", + "0106;700;700", + "0107;800;800", + "0108;900;900", + "0109;thousand;thousand", + "0111;minus;minus", + "0112;point;point", + "0115;volt;volt", + "0116;volts;volts", + "0117;amp;ampere", + "0118;amps;ampere", + "0119;meter per second;meter per second", + "0120;meters per second;meters per second", + "0123;kmh;k-m-h", + "0124;kmh;k-m-h", + "0125;meter;meter", + "0126;meters;meters", + "0127;degree;degree", + "0128;degrees;degrees", + "0129;percent;percent", + "0130;percent;percent", + "0131;milliamp;milliamp", + "0132;milliamps;milliamps", + "0133;mah;m-a-h", + "0134;mah;m-a-h", + "0135;watt;watt", + "0136;watts;watts", + "0137;db;db", + "0138;db;db", + "0140;feet;feet", + "0141;knot;knot", + "0142;knots;knots", + "0143;hour;hour", + "0144;hours;hours", + "0145;minute;minute", + "0146;minutes;minutes", + "0147;second;second", + "0148;seconds;seconds", + "0149;rpm;r-p-m", + "0150;rpm;r-p-m", + "0151;g;gee", + "0152;g;gees", + "0160;point zero;point zero", + "0161;point one;point one", + "0162;point two;point two", + "0163;point three;point three", + "0164;point four;point four", + "0165;point five;point five", + "0166;point six;point six", + "0167;point seven;point seven", + "0168;point eight;point eight", + "0169;point nine;point nine", + "a1_org;a1 low;a1 low", + "a1_red;a1 critical;a1 critical", + "a2_org;a2 low;a2 low", + "a2_red;a2 critical;a2 critical", + "endtrim;maximum trim reached;maximum trim reached", + "inactiv;inactivity alarm;inactivity alarm", + "lowbatt;radio battery low;radio battery low", + "midtrim;trim center;center", + "rssi_org;rf signal low;rf signal low", + "rssi_red;rf signal critical;rf signal critical", + "swalert;switch warning;switch warning", + "swr_red;radio antenna defective;radio antenna defective", + "tada;Start Sound;welcome to open T-X", + "telemko;telemetry lost;telemetry lost", + "telemok;telemetry recover;telemetry recover", + "thralert;throttle warning;throttle warning", + "timer10;10 seconds;10 seconds", + "timer20;20 seconds;20 seconds", + "timer30;30 seconds;30 seconds", + "timerlt3;timer sound;3 seconds" + }; + + private static string[] default_en_other_strings = + { + "atti;attitude;attitude", + "batcrit;battery critical;battery critical", + "batlow;low battery;low battery", + "camcenter;camera center;camera center", + "camfix;camera fixed;camera fixed", + "cammanual;camera manual;camera manual", + "capacity;capacity;capacity", + "engdis;engine disabled;engine disabled", + "engoff;engine off;engine off", + "engon;engine on;engine on", + "flaps1;flaps 1;flaps 1", + "flaps2;flaps 2;flaps 2", + "flapsdn;flaps down;flaps down", + "flapsup;flaps up;flaps up", + "fltmode1;flight mode one;flight mode one", + "fltmode2;flight mode two;flight mode two", + "fltmode3;flight mode three;flight mode three", + "fltmode4;flight mode four;flight mode four", + "fltmode5;flight mode five;flight mode five", + "fltmode6;flight mode six;flight mode six", + "fltmode7;flight mode seven;flight mode seven", + "fltmode8;flight mode eight;flight mode eight", + "fsoff;failsafe off;failsafe off", + "fson;failsafe on;failsafe on", + "geardn;gear down;gear down", + "gearup;gear upp;gear upp", + "gps;gps;G-P-S", + "horn;horn sound;eeeeeeeee", + "hirates;hi rates;hi rates", + "htoff;head tracker off;head tracker off", + "hton;head tracker on;head tracker on", + "ioc;ioc;ioc", + "iocoff;ioc off;ioc off", + "lowrates;lowrates;lowrates", + "manual;manual;manual", + "normal;normal;normal", + "nrmmod;normal mode;normal mode", + "pouet;small horn;ee , ee", + "shutter;camera shutter sound;klick", + "thrhold;throttle locked;throttle locked", + "thrrel;throttle released;throttle released", + "wizz;wizzing sound;shiss" + }; + + private static string[] default_se_system_strings = + { + "0000;0;0", + "0001;1;en", + "0002;2;2", + "0003;3;3", + "0004;4;4", + "0005;5;5", + "0006;6;6", + "0007;7;7", + "0008;8;8", + "0009;9;9", + "0010;10;10", + "0011;11;11", + "0012;12;12", + "0013;13;13", + "0014;14;14", + "0015;15;15", + "0016;16;16", + "0017;17;17", + "0018;18;18", + "0019;19;19", + "0020;20;20", + "0021;21;tjugoen", + "0022;22;22", + "0023;23;23", + "0024;24;24", + "0025;25;25", + "0026;26;26", + "0027;27;27", + "0028;28;28", + "0029;29;29", + "0030;30;30", + "0031;31;trettioen", + "0032;32;32", + "0033;33;33", + "0034;34;34", + "0035;35;35", + "0036;36;36", + "0037;37;37", + "0038;38;38", + "0039;39;39", + "0040;40;40", + "0041;41;fyrtioen", + "0042;42;42", + "0043;43;43", + "0044;44;44", + "0045;45;45", + "0046;46;46", + "0047;47;47", + "0048;48;48", + "0049;49;49", + "0050;50;50", + "0051;51;femtioen", + "0052;52;52", + "0053;53;53", + "0054;54;54", + "0055;55;55", + "0056;56;56", + "0057;57;57", + "0058;58;58", + "0059;59;59", + "0060;60;60", + "0061;61;sextioen", + "0062;62;62", + "0063;63;63", + "0064;64;64", + "0065;65;65", + "0066;66;66", + "0067;67;67", + "0068;68;68", + "0069;69;69", + "0070;70;70", + "0071;71;sjuttioen", + "0072;72;72", + "0073;73;73", + "0074;74;74", + "0075;75;75", + "0076;76;76", + "0077;77;77", + "0078;78;78", + "0079;79;79", + "0080;80;80", + "0081;81;åttioen", + "0082;82;82", + "0083;83;83", + "0084;84;84", + "0085;85;85", + "0086;86;86", + "0087;87;87", + "0088;88;88", + "0089;89;89", + "0090;90;90", + "0091;91;nittioen", + "0092;92;92", + "0093;93;93", + "0094;94;94", + "0095;95;95", + "0096;96;96", + "0097;97;97", + "0098;98;98", + "0099;99;99", + "0100;100;100", + "0101;200;200", + "0102;300;300", + "0103;400;400", + "0104;500;500", + "0105;600;600", + "0106;700;700", + "0107;800;800", + "0108;900;900", + "0109;thousand;tusen", + "0111;minus;minus", + "0112;point;komma", + "0115;volt;volt", + "0116;volts;volt", + "0117;amp;ampere", + "0118;amps;ampere", + "0119;meter per second;meter per sekund", + "0120;meters per second;meter per sekund", + "0123;kmh;kilometer i timmen", + "0124;kmh;kilometer i timmen", + "0125;meter;meter", + "0126;meters;meter", + "0127;degree;grad", + "0128;degrees;grader", + "0129;percent;procent", + "0130;percent;procent", + "0131;milliamp;milliampere", + "0132;milliamps;milliampere", + "0133;mah;milliampere-timme", + "0134;mah;milliampere-timmar", + "0135;watt;watt", + "0136;watts;watt", + "0137;db;dessibell", + "0138;db;dessibell", + "0140;feet;fot", + "0141;knot;knop", + "0142;knots;knop", + "0143;hour;timme", + "0144;hours;timmar", + "0145;minute;minut", + "0146;minutes;minuter", + "0147;second;sekund", + "0148;seconds;sekunder", + "0149;rpm;varv i minuten", + "0150;rpm;varv i minuten", + "0151;g;g", + "0152;g;g", + "0160;point zero;komma noll", + "0161;point one;komma en", + "0162;point two;komma två", + "0163;point three;komma tre", + "0164;point four;komma fyra", + "0165;point five;komma fem", + "0166;point six;komma sex", + "0167;point seven;komma sju", + "0168;point eight;komma åtta", + "0169;point nine;komma nio", + "a1_org;a1 low;a1 låg", + "a1_red;a1 critical;a1 kritisk", + "a2_org;a2 low;a2 låg", + "a2_red;a2 critical;a2 kritisk", + "endtrim;maximum trim reached;maximum trim", + "inact;inactivity alarm;inaktivitets-larm", + "lowbat;radio battery low;Låg radiobatterispänning", + "midtrim;trim center;center", + "rssi_org;rf signal low;Svag radio-signal", + "rssi_red;rf signal critical;Kritisk radio-signal", + "swalert;switch warning;brytar-varning", + "swr_red;;radio-antennen är defekt", + "tada;;Välkommen till open Te Ex", + "telemko;;telemetri förlorad", + "telemok;;telemetri åter", + "thralert;;gas-varning", + "timer10;;10 sekunder", + "timer20;;20 sekunder", + "timer30;;30 sekunder", + "timerlt3;timer sound;3 sekunder" + }; + + private static string[] default_se_other_strings = + { + "atti;;lutning", + "batcrit;;kritisk batteri-nivå", + "batlow;;låg batteri-nivå", + "camcenter;;kamera centrerad", + "cammanual;;manuell kamera-kontroll", + "capacity;;kapacitet", + "engdis;;motor säkrad", + "engoff;;motor avslagen", + "engon;;motor på", + "flaps1;;flaps läge, ett", + "flaps2;;flaps läge två", + "flapsdn;;flaps ned", + "flapsup;;flaps upp", + "fltmode1;;flyg-läge, ett", + "fltmode2;;flyg-läge två", + "fltmode3;;flyg-läge tre", + "fltmode4;;flyg-läge fyra", + "fltmode5;;flyg-läge fem", + "fltmode6;;flyg-läge sex", + "fltmode7;;flyg-läge sju", + "fltmode8;;flyg-läge åtta", + "fsoff;;fäjlsäif avslagen", + "fson;;fäjlsäif på", + "geardn;;landningsställ ned", + "gearup;;landningsställ upp", + "gps;;GPS", + "hirates;;höga nivåer", + "htoff;;head tracker avslagen", + "hton;;head tracker på", + "horn;horn sound;eeeeeeeee", + "ioc;;i o c", + "iocoff;;i o c avslagen", + "lowrates;;låga nivåer", + "manual;;manuell", + "normal;;normal", + "nrmmod;;normalt läge", + "pouet;small horn;ee , ee", + "shutter;camera shutter sound;klick", + "thrhold;;gas säkrad", + "thrrel;;gas osäkrad", + "speed;;hastighet", + "start;;start", + "thermal;;termik", + "wizz;wizzing sound;shiss" + }; + + private static string[] default_it_system_strings = + { + "0000;0;0", + "0001;1;1", + "0002;2;2", + "0003;3;3", + "0004;4;4", + "0005;5;5", + "0006;6;6", + "0007;7;7", + "0008;8;8", + "0009;9;9", + "0010;10;10", + "0011;11;11", + "0012;12;12", + "0013;13;13", + "0014;14;14", + "0015;15;15", + "0016;16;16", + "0017;17;17", + "0018;18;18", + "0019;19;19", + "0020;20;20", + "0021;21;21", + "0022;22;22", + "0023;23;23", + "0024;24;24", + "0025;25;25", + "0026;26;26", + "0027;27;27", + "0028;28;28", + "0029;29;29", + "0030;30;30", + "0031;31;31", + "0032;32;32", + "0033;33;33", + "0034;34;34", + "0035;35;35", + "0036;36;36", + "0037;37;37", + "0038;38;38", + "0039;39;39", + "0040;40;40", + "0041;41;41", + "0042;42;42", + "0043;43;43", + "0044;44;44", + "0045;45;45", + "0046;46;46", + "0047;47;47", + "0048;48;48", + "0049;49;49", + "0050;50;50", + "0051;51;51", + "0052;52;52", + "0053;53;53", + "0054;54;54", + "0055;55;55", + "0056;56;56", + "0057;57;57", + "0058;58;58", + "0059;59;59", + "0060;60;60", + "0061;61;61", + "0062;62;62", + "0063;63;63", + "0064;64;64", + "0065;65;65", + "0066;66;66", + "0067;67;67", + "0068;68;68", + "0069;69;69", + "0070;70;70", + "0071;71;71", + "0072;72;72", + "0073;73;73", + "0074;74;74", + "0075;75;75", + "0076;76;76", + "0077;77;77", + "0078;78;78", + "0079;79;79", + "0080;80;80", + "0081;81;81", + "0082;82;82", + "0083;83;83", + "0084;84;84", + "0085;85;85", + "0086;86;86", + "0087;87;87", + "0088;88;88", + "0089;89;89", + "0090;90;90", + "0091;91;91", + "0092;92;92", + "0093;93;93", + "0094;94;94", + "0095;95;95", + "0096;96;96", + "0097;97;97", + "0098;98;98", + "0099;99;99", + "0100;100;100", + "0101;mila;mila", + "0102;mille;mille", + "0103;virgola;virgola", + "0104;un;un", + "0105;e;e", + "0106;meno;meno", + "0107;ora;ora", + "0108;ore;ore", + "0109;minuto;minuto", + "0110;minuti;minuti", + "0111;secondo;secondo", + "0112;secondi;secondi", + "0113;;volt", + "0114;;ampere", + "0115;;metri per secondo", + "0116;;", + "0117;;chilometri/ora", + "0118;;metri", + "0119;;gradi", + "0120;;percento", + "0121;;milliampere", + "0122;;milliampere/ora", + "0123;;watt", + "0124;;db", + "0125;;piedi", + "0126;;nodi", + "0127;;ore", + "0128;;minuti", + "0129;;secondi", + "0130;;R P M", + "0131;;g", + "0132;;timer", + "0133;;timer", + "0134;;trasmissione", + "0135;;ricezione", + "0136;;A1", + "0137;;A2", + "0138;;altitudine", + "0139;;motore", + "0140;;carburante", + "0141;;temperatura", + "0142;;temperatura", + "0143;;velocità", + "0144;;distanza", + "0145;;altitudine", + "0146;;cella lipo", + "0147;;totale lipo", + "0148;;tensione", + "0149;;corrente", + "0150;;consumo", + "0151;;potenza", + "0152;;accellerazione X", + "0153;;accellerazione Y", + "0154;;accellerazione Z", + "0155;;direzione", + "0156;;variometro", + "0157;;minimo", + "0158;;massimo", + "a1_org;A1 in allarme;A1 in allarme", + "a1_red;A1 critico;A1 critico", + "a2_org;A2 in allarme;A2 in allarme", + "a2_red;A2 critico;A2 critico", + "eebad;eeprom corrotta;eeprom corrotta", + "eeformat;formattazone eeprom in corso;formattazone eeprom in corso", + "endtrim;massimo trim raggiunto;massimo trim raggiunto", + "error;errore;errore", + "highmah;assorbimento elevato;assorbimento elevato", + "hightemp;temperatura elevata;temperatura elevata", + "inactiv;radio inattiva controllare;radio inattiva controllare", + "lowbatt;batteria della radio scarica;batteria della radio scarica", + "midpot;potenziometro centrato;potenziometro centrato", + "midtrim;trim centrato;trim centrato", + "rssi_org;Segnale radio basso;Segnale radio basso", + "rssi_red;Segnale radio critico;Segnale radio critico", + "swalert;interruttori non in posizione, verificare;interruttori non in posizione, verificare", + "swr_red;Problema all'antenna della radio;Problema all'antenna della radio", + "tada;;Benvenuto", + "telemko;Telemetria assente;Telemetria assente", + "telemok;Telemetria disponibile;Telemetria disponibile", + "thralert;controllo motore non in posizione, verificare;controllo motore non in posizione, verificare", + "timer10;dieci secondi;dieci secondi", + "timer20;venti secondi;venti secondi", + "timer30;trenta secondi;trenta secondi", + "timerlt3;timer sound;3 secondi" + }; + + private static string[] default_it_other_strings = + { + "attero;;atterraggiio", + "crowof;;crow off", + "crowon;;crow on", + "engoff;;motore spento", + "flapdn;;flap estesi", + "flapup;;flap rientrati", + "fltmd1;;fase di volo 1", + "fltmd2;;fase di volo 2", + "fltmd3;;fase di volo 3", + "fltmd4;;fase di volo 4", + "fltmd5;;fase di volo 5", + "fltmd6;;fase di volo 6", + "fltmd7;;fase di volo 7", + "fltmd8;;fase di volo 8", + "fltmd9;;fase di volo 9", + "geardn;;carrello aperto", + "gearup;;carrello chiuso", + "gps;;GPS", + "lowbat;;batteria scarica", + "nrmmod;;modo volo normale", + "spdmod;;modo velocità", + "thmmod;;modo termica", + "tohigh;;troppo alto", + "tolow;;troppo basso", + "trnoff;;modalità maestro disattiva", + "trnon;;modalità maestro attiva" + }; + + private static string[] default_de_system_strings = + { + "0000;0;0", + "0001;1;ein", + "0002;2;2", + "0003;3;3", + "0004;4;4", + "0005;5;5", + "0006;6;6", + "0007;7;7", + "0008;8;8", + "0009;9;9", + "0010;10;10", + "0011;11;11", + "0012;12;12", + "0013;13;13", + "0014;14;14", + "0015;15;15", + "0016;16;16", + "0017;17;17", + "0018;18;18", + "0019;19;19", + "0020;20;20", + "0021;21;21", + "0022;22;22", + "0023;23;23", + "0024;24;24", + "0025;25;25", + "0026;26;26", + "0027;27;27", + "0028;28;28", + "0029;29;29", + "0030;30;30", + "0031;31;31", + "0032;32;32", + "0033;33;33", + "0034;34;34", + "0035;35;35", + "0036;36;36", + "0037;37;37", + "0038;38;38", + "0039;39;39", + "0040;40;40", + "0041;41;41", + "0042;42;42", + "0043;43;43", + "0044;44;44", + "0045;45;45", + "0046;46;46", + "0047;47;47", + "0048;48;48", + "0049;49;49", + "0050;50;50", + "0051;51;51", + "0052;52;52", + "0053;53;53", + "0054;54;54", + "0055;55;55", + "0056;56;56", + "0057;57;57", + "0058;58;58", + "0059;59;59", + "0060;60;60", + "0061;61;61", + "0062;62;62", + "0063;63;63", + "0064;64;64", + "0065;65;65", + "0066;66;66", + "0067;67;67", + "0068;68;68", + "0069;69;69", + "0070;70;70", + "0071;71;71", + "0072;72;72", + "0073;73;73", + "0074;74;74", + "0075;75;75", + "0076;76;76", + "0077;77;77", + "0078;78;78", + "0079;79;79", + "0080;80;80", + "0081;81;81", + "0082;82;82", + "0083;83;83", + "0084;84;84", + "0085;85;85", + "0086;86;86", + "0087;87;87", + "0088;88;88", + "0089;89;89", + "0090;90;90", + "0091;91;91", + "0092;92;92", + "0093;93;93", + "0094;94;94", + "0095;95;95", + "0096;96;96", + "0097;97;97", + "0098;98;98", + "0099;99;99", + "0100;100;100", + "0101;1000;tausend", + "0102;;comma;comma", + "0103;;und", + "0104;;minus", + "0105;;uhr", + "0106;;minute", + "0107;;minuten", + "0108;;sekunde", + "0109;;sekunden", + "0110;;Volt", + "0111;;Ampere", + "0112;;Meter pro sekunde", + "0113;;", + "0114;;kilometer pro stunde", + "0115;;Meter", + "0116;;Grad", + "0117;;Prozent", + "0118;;Milliampere", + "0119;;Milliampere pro stunde", + "0120;;Watt", + "0121;;db", + "0122;;Fuesse", + "0123;;Knoten", + "0124;;Uhr", + "0125;;Minuten", + "0126;;Secunden", + "0127;;R P M", + "0128;;g", + "0129;;Timer", + "0130;;Timer", + "0131;;Sendung", + "0132;;Empfang", + "0133;;A1", + "0134;;A2", + "0135;;Hoehe", + "0136;;Motor", + "0137;;Treibstoff", + "0138;;Temperatur", + "0139;;Temperatur", + "0140;;Geschwindigkeit", + "0141;;Ferne", + "0142;;Hoehe", + "0143;;Lipo-Zelle", + "0144;;Zellen gesamt", + "0145;;Spannung", + "0146;;Strom", + "0147;;Verbrauch", + "0148;;Power", + "0149;;Beschleunigung X", + "0150;;Beschleunigung Y", + "0151;;Beschleunigung Z", + "0152;;Richtung", + "0153;;Variometer", + "0154;;Minimum", + "0155;;Maximum", + "a1_org;;A1 schlecht!", + "a1_red;;A1 kritisch!", + "a2_org;;A2 schlecht!", + "a2_red;;A2 kritisch!", + "eebad;;Das EEPROM ist fehlerhaft", + "eeformat;;Das EEPROM ist immer formatiert", + "endtrim;;Maximale trimmung erreicht", + "error;;fehler", + "highmah;;Senderstrom ist zu hoch!", + "hightemp;;Sendertemperatur ist zu hoch!", + "inactiv;;Sender ist inaktiv,bitte Ueberpruefen Sie", + "lowbatt;;Senderakku niedrig", + "midtrim;;Trim zentriert", + "midpot;;Poti zentriert", + "rssi_org;;Funksignal schlecht!", + "rssi_red;;Funksignal kritisch!", + "swr_red;;Problem mit der sender Antenna", + "swalert;;Schalten fehlpositioniert, bitte pruefen", + "tada;Welcome sound;Willkommen", + "thralert;;Gaskanal nicht Null, bitte pruefen", + "timer10;;10 sekunden", + "timer20;;20 sekunden", + "timer30;;30 sekunden", + "timerlt3;;Noch drei Sekunden" }; + + private static string[] default_de_other_strings = + { + "attero;;Landung", + "crowof;;crow aus", + "crowon;;crow ein", + "engoff;;Motor aus", + "flapdn;;Klappen ausgefahren", + "flapup;;Klappen eingefahren", + "fltmd1;;Regime 1", + "fltmd2;;Regime 2", + "fltmd3;;Regime 3", + "fltmd4;;Regime 4", + "fltmd5;;Regime 5", + "fltmd6;;Regime 6", + "fltmd7;;Regime 7", + "fltmd8;;Regime 8", + "fltmd9;;Regime 9", + "geardn;;Fahrwerk ausgefahren", + "gearup;;Fahrwerk eingezogen", + "horn;horn sound;eeeeeeeee", + "lowbat;;Batterie schwach", + "nrmmod;;Normal-Modus ist aktiviert", + "pouet;small horn;ee , ee", + "shutter;camera shutter sound;klick", + "spdmod;;Schnell-Modus ist aktiviert", + "thmmod;;Thermik-Modus ist aktiviert", + "trnon;;Trainer-Modus ein", + "trnoff;;Trainer-Modus aus", + "tohigh;;zu hoch", + "tolow;;zu niedrig", + "wizz;wizzing sound;shiss" + }; + + private static string[] default_fr_system_strings = + { + "0000;0;0", + "0001;1;1", + "0002;2;2", + "0003;3;3", + "0004;4;4", + "0005;5;5", + "0006;6;6", + "0007;7;7", + "0008;8;8", + "0009;9;9", + "0010;10;10", + "0011;11;11", + "0012;12;12", + "0013;13;13", + "0014;14;14", + "0015;15;15", + "0016;16;16", + "0017;17;17", + "0018;18;18", + "0019;19;19", + "0020;20;20", + "0021;21;21", + "0022;22;22", + "0023;23;23", + "0024;24;24", + "0025;25;25", + "0026;26;26", + "0027;27;27", + "0028;28;28", + "0029;29;29", + "0030;30;30", + "0031;31;31", + "0032;32;32", + "0033;33;33", + "0034;34;34", + "0035;35;35", + "0036;36;36", + "0037;37;37", + "0038;38;38", + "0039;39;39", + "0040;40;40", + "0041;41;41", + "0042;42;42", + "0043;43;43", + "0044;44;44", + "0045;45;45", + "0046;46;46", + "0047;47;47", + "0048;48;48", + "0049;49;49", + "0050;50;50", + "0051;51;51", + "0052;52;52", + "0053;53;53", + "0054;54;54", + "0055;55;55", + "0056;56;56", + "0057;57;57", + "0058;58;58", + "0059;59;59", + "0060;60;60", + "0061;61;61", + "0062;62;62", + "0063;63;63", + "0064;64;64", + "0065;65;65", + "0066;66;66", + "0067;67;67", + "0068;68;68", + "0069;69;69", + "0070;70;70", + "0071;71;71", + "0072;72;72", + "0073;73;73", + "0074;74;74", + "0075;75;75", + "0076;76;76", + "0077;77;77", + "0078;78;78", + "0079;79;79", + "0080;80;80", + "0081;81;81", + "0082;82;82", + "0083;83;83", + "0084;84;84", + "0085;85;85", + "0086;86;86", + "0087;87;87", + "0088;88;88", + "0089;89;89", + "0090;90;90", + "0091;91;91", + "0092;92;92", + "0093;93;93", + "0094;94;94", + "0095;95;95", + "0096;96;96", + "0097;97;97", + "0098;98;98", + "0099;99;99", + "0100;100;100", + "0101;200;200", + "0102;300;300", + "0103;400;400", + "0104;500;500", + "0105;600;600", + "0106;700;700", + "0107;800;800", + "0108;900;900", + "0109;1000;Mille", + "0110;;une", + "0111;11;onze", + "0112;21;21", + "0113;31;31", + "0114;41;41", + "0115;51;51", + "0116;61;61", + "0117;71;71", + "0118;81;81", + "0119;.;virgule", + "0120;&;et", + "0121;-;moins", + "0122;<>;bip", + "0123;<>;bip", + "0124;<>;bip", + "0125;V;volts", + "0126;A;ampères", + "0127;ms;mètres par seconde", + "0128;<>;bip", + "0129;kmh;kilomètre heure", + "0130;m;mètres", + "0131;;degrés", + "0132;%;pourcent", + "0133;mA;milliampère", + "0134;mAH;milliampères heure", + "0135;W;watt", + "0136;dB;db", + "0137;;pied", + "0138;;noeud", + "0139;h;heure", + "0140;min;minute", + "0141;sec;secondes", + "0142;;taux par minute", + "0143;G;g", + "0144;<>;bip", + "0144;<>;bip", + "0146;timer;chrono", + "0147;<>;bip", + "0148;;tension", + "0149;;tension", + "0150;;émission", + "0151;;réception", + "0152;;altitude", + "0153;;moteur", + "0154;;carburant", + "0155;;temperature", + "0156;;temperature", + "0157;;vitesse", + "0158;;distance", + "0159;;attitude", + "0160;;élément lipo", + "0161;;total lipo", + "0162;;tension", + "0163;;courant", + "0164;;consomation", + "0165;;puissance", + "0166;;accelération x", + "0167;;accelération y", + "0168;;accelération z", + "0169;;orientation", + "0170;;vario", + "0171;<>;bip", + "0172;<>;bip", + "0173;<>;bip", + "0174;<>;bip", + "0175;<>;bip", + "0176;<>;bip", + "0177;<>;bip", + "0178;<>;bip", + "0179;<>;bip", + "0180;.0;virgule 0", + "0181;.1;virgule 1", + "0182;.2;virgule 2", + "0183;.3;virgule 3", + "0184;.4;virgule 4", + "0185;.5;virgule 5", + "0186;.6;virgule 6", + "0187;.7;virgule 7", + "0188;.8;virgule 8", + "0189;.9;virgule 9", + "190;<>;bip", + "a1_org;a1 low;a1 bas", + "a1_red;a1 critical;a1 critique", + "a2_org;a2 low;a2 bas", + "a2_red;a2 critical;a2 critique", + "eebad;memoire basse;niveau mémoire bas", + "endtrim;trim maximum atteint;trim maximum atteint", + "inact;inactivity alarm;alarme d'innactivité", + "lowbat;radio battery low;batterie transmetteur faible", + "midtrim;trim center;trim centré", + "rssi_org;rf signal low;signal recepteur faible", + "rssi_red;rf signal critical;signal recepteur critique", + "swalert;switch warning;interupteur mal positionné", + "swr_red;radio antenna defective;antenne emeteur defectueuse", + "tada;welcome to opentx;Bienvenue sur Open tx", + "telemko;telemetry lost;télémétrie perdue", + "telemok;telemetry recover;télémétrie retrouvée", + "thralert;throttle warning;mettre les gaz a 0", + "timer10;10 seconds;10 secondes", + "timer20;20 seconds;20 secondes", + "timer30;30 seconds;30 secondes", + "timerlt3;3 seconds;3 secondes" + }; + + private static string[] default_fr_other_strings = + { + "attero;;atterrissage", + "atti;attitude;attitude", + "batcrit;battery critical;niveau batterie critique", + "batlow;low battery;niveau batterie bas", + "camcenter;camera center;caméra centrée", + "cammanual;camera manual;caméra manuelle", + "capacity;capacity;capacité", + "engdis;engine disabled;moteur calé", + "engoff;engine off;moteur coupé", + "engon;engine on;moteur démarré", + "flaps1;flaps 1;volets 1", + "flaps2;flaps 2;volets 2", + "flapsdn;flaps down;volets sortis", + "flapsup;flaps up;volets rentrés", + "fltmode0;phase de vol 0;phase de vol 0", + "fltmode1;phase de vol 1;phase de vol 1", + "fltmode2;phase de vol 2;phase de vol 2", + "fltmode3;phase de vol 3;phase de vol 3", + "fltmode4;phase de vol 4;phase de vol 4", + "fltmode5;phase de vol 5;phase de vol 5", + "fltmode6;phase de vol 6;phase de vol 6", + "fltmode7;phase de vol 7;phase de vol 7", + "fltmode8;phase de vol 8;phase de vol 8", + "fsoff;failsafe off;failsafe coupé", + "fson;failsafe on;failsafe activé", + "geardn;gear down;train sorti", + "gearup;gear upp;train rentré", + "gps;gps;gps", + "hirates;hi rates;taux élevé", + "htoff;head tracker off;suivi tète désactivé", + "hton;head tracker on;suivi tète activé", + "ioc;ioc;i o c", + "iocoff;ioc off;i o c coupé", + "lowrates;lowrates;taux faible", + "manual;manual;manuel", + "normal;normal;normal", + "nrmmod;normal mode;mode normal", + "thrhold;throttle locked;gaz bloqués","thrrel;throttle released;gaz relachés", + "trnoff;;fin écolage", + "trnon;;écolage", + }; + + public string[][] default_system_strings = new string[10][]; + public string[][] default_other_strings = new string[10][]; + + public int toInt(string langStr) + { + if (langStr == "cz") return 1; + if (langStr == "de") return 2; + if (langStr == "es") return 3; + if (langStr == "fr") return 4; + if (langStr == "it") return 5; + if (langStr == "pl") return 6; + if (langStr == "pt") return 7; + if (langStr == "se") return 8; + if (langStr == "sk") return 9; + else return 0; //English default + } + + public SentenceTables() + { + default_other_strings[toInt("cz")] = default_cz_other_strings; + default_system_strings[toInt("cz")] = default_cz_system_strings; + + default_other_strings[toInt("de")] = default_de_other_strings; + default_system_strings[toInt("de")] = default_de_system_strings; + + default_other_strings[toInt("en")] = default_en_other_strings; + default_system_strings[toInt("en")] = default_en_system_strings; + + default_other_strings[toInt("es")] = default_es_other_strings; + default_system_strings[toInt("es")] = default_es_system_strings; + + default_other_strings[toInt("fr")] = default_fr_other_strings; + default_system_strings[toInt("fr")] = default_fr_system_strings; + + default_other_strings[toInt("it")] = default_it_other_strings; + default_system_strings[toInt("it")] = default_it_system_strings; + + default_other_strings[toInt("pl")] = default_pl_other_strings; + default_system_strings[toInt("pl")] = default_pl_system_strings; + + default_other_strings[toInt("pt")] = default_pt_other_strings; + default_system_strings[toInt("pt")] = default_pt_system_strings; + + default_other_strings[toInt("se")] = default_se_other_strings; + default_system_strings[toInt("se")] = default_se_system_strings; + + default_other_strings[toInt("sk")] = default_sk_other_strings; + default_system_strings[toInt("sk")] = default_sk_system_strings; + } + } +} diff --git a/sound/recorder/stop.png b/sound/recorder/stop.png new file mode 100644 index 0000000000000000000000000000000000000000..d931243bd3a4975df7733abe714b91dfe5cc9ea3 GIT binary patch literal 4065 zcmV<74<7J|P)KLZ*U+IBfRsybQWXdwQbLP>6pAqfylh#{fb6;Z(vMMVS~$e@S=j*ftg6;Uhf59&ghTmgWD0l;*T zI709Y^p6lP1rIRMx#05C~cW=H_Aw*bJ-5DT&Z2n+x)QHX^p z00esgV8|mQcmRZ%02D^@S3L16t`O%c004NIvOKvYIYoh62rY33S640`D9%Y2D-rV&neh&#Q1i z007~1e$oCcFS8neI|hJl{-P!B1ZZ9hpmq0)X0i`JwE&>$+E?>%_LC6RbVIkUx0b+_+BaR3cnT7Zv!AJxW zizFb)h!jyGOOZ85F;a?DAXP{m@;!0_IfqH8(HlgRxt7s3}k3K`kFu>>-2Q$QMFfPW!La{h336o>X zu_CMttHv6zR;&ZNiS=X8v3CR#fknUxHUxJ0uoBa_M6WNWeqIg~6QE69c9o#eyhGvpiOA@W-aonk<7r1(?fC{oI5N*U!4 zfg=2N-7=cNnjjOr{yriy6mMFgG#l znCF=fnQv8CDz++o6_Lscl}eQ+l^ZHARH>?_s@|##Rr6KLRFA1%Q+=*RRWnoLsR`7U zt5vFIcfW3@?wFpwUVxrVZ>QdQz32KIeJ}k~{cZZE^+ya? z2D1z#2HOnI7(B%_ac?{wFUQ;QQA1tBKtrWrm0_3Rgps+?Jfqb{jYbcQX~taRB;#$y zZN{S}1|}gUOHJxc?wV3fxuz+mJ4`!F$IZ;mqRrNsHJd##*D~ju=bP7?-?v~|cv>vB zsJ6IeNwVZxrdjT`yl#bBIa#GxRa#xMMy;K#CDyyGyQdMSxlWT#tDe?p!?5wT$+oGt z8L;Kp2HUQ-ZMJ=3XJQv;x5ci*?vuTfeY$;({XGW_huIFR9a(?@3)XSs8O^N5RyOM=TTmp(3=8^+zpz2r)C z^>JO{deZfso3oq3?Wo(Y?l$ge?uXo;%ru`Vo>?<<(8I_>;8Eq#KMS9gFl*neeosSB zfoHYnBQIkwkyowPu(zdms`p{<7e4kra-ZWq<2*OsGTvEV%s0Td$hXT+!*8Bnh2KMe zBmZRodjHV?r+_5^X9J0WL4jKW`}lf%A-|44I@@LTvf1rHjG(ze6+w@Jt%Bvjts!X0 z?2xS?_ve_-kiKB_KiJlZ$9G`c^=E@oNG)mWWaNo-3TIW8)$Hg0Ub-~8?KhvJ>$ z3*&nim@mj(aCxE5!t{lw7O5^0EIO7zOo&c6l<+|iDySBWCGrz@C5{St!X3hAA}`T4 z(TLbXTq+(;@<=L8dXnssyft|w#WSTW<++3>sgS%(4NTpeI-VAqb|7ssJvzNHgOZVu zaYCvgO_R1~>SyL=cFU|~g|hy|Zi}}s9+d~lYqOB71z9Z$wnC=pR9Yz4DhIM>Wmjgu z&56o6maCpC&F##y%G;1PobR9i?GnNg;gYtchD%p19a!eQtZF&3JaKv33gZ<8D~47E ztUS1iwkmDaPpj=$m#%)jCVEY4fnLGNg2A-`YwHVD3gv};>)hAvT~AmqS>Lr``i7kw zJ{5_It`yrBmlc25DBO7E8;5VoznR>Ww5hAaxn$2~(q`%A-YuS64wkBy=9dm`4cXeX z4c}I@?e+FW+b@^RDBHV(wnMq2zdX3SWv9u`%{xC-q*U}&`cyXV(%rRT*Z6MH?i+i& z_B8C(+grT%{XWUQ+f@NoP1R=AW&26{v-dx)iK^-Nmiuj8txj!m?Z*Ss1N{dh4z}01 z)YTo*JycSU)+_5r4#yw9{+;i4Ee$peRgIj+;v;ZGdF1K$3E%e~4LaI(jC-u%2h$&R z9cLXcYC@Xwnns&bn)_Q~Te?roKGD|d-g^8;+aC{{G(1^(O7m37Y1-+6)01cN&y1aw zoqc{T`P^XJqPBbIW6s}d4{z_f5Om?vMgNQEJG?v2T=KYd^0M3I6IZxbny)%vZR&LD zJpPl@Psh8QyPB@KTx+@RdcC!KX7}kEo;S|j^u2lU7XQ}Oo;f|;z4Ll+_r>@1-xl3| zawq-H%e&ckC+@AhPrP6BKT#_XdT7&;F71j}Joy zkC~6lh7E@6o;W@^IpRNZ{ptLtL(gQ-CY~4mqW;US7Zxvm_|@yz&e53Bp_lTPlfP|z zrTyx_>lv@x#=^!PzR7qqF<$gm`|ZJZ+;<)Cqu&ot2z=0000WV@Og>004R=004l4008;_004mL004C`008P>0026e000+nl3&F} z000FHNkl#MJ-E-ftlh?T<_17?OX21Eoy1|UEcSE$OIs?HJ79Yk~u5%mB-6-%n}tE!$MqLV~) z62PATAR>SQq6}l)_WS5jUw_mfevSRcCB-6@;g*@ya^E|hozJdL%bj=?-^s? zR+WXz1>l6`88Y;Ar|j&s&LX8WHC0^&fQVqNMV4i7&ViXx*Yzb4ebriXRD{Ep09a#@ zI9)F+?-XTmpe#!?O@qca)fL7CIE=& z))2x+{eJ&uBEoPugosStyw#zqFvg(Y??Y8F91hQCS$0Sjr&pb~xVSidVdm?a#(y#x z3~pj(EG;dK-HZQr_!I=jH1&EtIO}k!x^zCzi+ij!=cbfTxK!1wY5cq0Zuh2?5~`}2 z-b7R`%O){WRTV-E=ytn%n#Laks4&LB7&8U{D7>$qa@Ouw)#>3PvMmMx!{HFBiY&|S zY#RUE{*EL4Wp&eH~m3>P*v6V!)3a?jSeEhU@*XNIIPQ}+-t4<$;22i8jYUF zvTRV-HJEw5+eOA37}}C4bbR|YbSz5~S(bIY_eWxiaLl}u6F-vYIsB5J^1enHXnX@- z*T80KP(@jGkQX^rblqp~J$k(!nE7Ewyb3}Ai2m!(y%PlW+e0Ay+J~)0HWm&eK z@4d(UhaSM({C+gP*-)OL2_QqeVhjgdjB(ytgBapi4bY7jg@CH6kYa2FQ2QDoG*AUZ zWuss~hyl(zgb?N(3-1L1DW&Ozb!%jqQ(>@hD*$0$=3h6Y001~KhzKHjyAzS!P^`<* zt2SK@pcDe4wXFbRjNp`j6%w2ULPT~uX6^~ey1-jafqWRPGbVG{2~}+`D9bl7#$sBb>> zLxfRXV^~$2HYTcye!q`Sx7(^L0{uN03~q6%_{(MPSmT=~XKl_zb`7kJ41vbFW&UEe@s<-vw~4r08ZOcmjS@%S^heKV63w!JLO`h(|LuN zr~3WBjG0js#cO#{{9ufMQ&F%o%CbCK`})3=(p}r#jI4CMb?)mOJ9oTfm(}FF_mlqv zp)AV7RjfW%)jiveK>;HArPu2|WXRN$0Cl5!v~t?HvMdkPqxwTA_H5_PiRkCSVDMnC z+gq4c-ZfqEM4P9ba|Z!@zKu=kDeK%pW9`>#rD7pAicu`cUl?iD}_V4^9W6V+K z+}#8$V1vA1+On#1?)f~+_Ze&6P}SdsWn4yieRK;8rr%ZnAfmUNbNj4w&jP4t9pW}? zFhTgn#sx1-GZveiv)}FA|eyXY$$7*U%T>lIJk|epy Tk|C|n00000NkvXXu0mjfL1&l? literal 0 HcmV?d00001 diff --git a/sound/speaker/.gitignore b/sound/speaker/.gitignore new file mode 100644 index 000000000..ebd53ae98 --- /dev/null +++ b/sound/speaker/.gitignore @@ -0,0 +1,3 @@ +/OpenTXspeaker.suo +/bin/* +/obj/* diff --git a/speaker/App.xaml b/sound/speaker/App.xaml similarity index 100% rename from speaker/App.xaml rename to sound/speaker/App.xaml diff --git a/speaker/App.xaml.cs b/sound/speaker/App.xaml.cs similarity index 100% rename from speaker/App.xaml.cs rename to sound/speaker/App.xaml.cs diff --git a/sound/speaker/GPLv3_Logo.png b/sound/speaker/GPLv3_Logo.png new file mode 100644 index 0000000000000000000000000000000000000000..ba78d4c4941dabf2fcac5409a92ac4c57920c69f GIT binary patch literal 2666 zcmV-w3YGPVP)Px#32;bRa{vGVivR!tivi)#(!2lw00(qQO+^RT0uvMpF24YJ`L;(K) z{{a7>y{D4^014_zL_t(&-tC%skW|$b#(x5`77PlZ01Xf|tXfvU1+9P)Nl;9MMIeIW zf~A;|yxWx-F&@d<9Z!mSGK`{-NXD*+V< z1U?qnFHjo71r>243NtglEQV7Q5|M$wwPW#3mU1Xa75(4)}+D^1dj!r-wg;N!7wPTlz6cv~* zaG8PJ%ocdxi%_r(8VF2J2gJd((|x~-stE3f0*?zktgtfz_z{7D0<}|XS^^CmbayaJ zV6ea`S+E+%|4L05^x|!{8+(dT?jEM~Js`$27+y6h2%>GgYF0wJYE0l-O z)7o925Tv&W;2eAZgu;B5;j^dJ8-bz3oKpjkZt1g)zX^66mI| z)j_Xp5wNzxdh2k6HU6=}>lr5fjzC|47oe%aZiQ_MKeNs1Wz;5au`^ddqYxT8_`O0| z2+eKGVG3K)+k_Uu1%|7S@cDv!RA5U0Jp{%pe3tfppM%?rytQ5}8P;njwoMwi^#raG z_|!q~0P19O58V`YC~Ow^rGefh%fweYXuAOFEA&%1pirdH-T=NSi#0u9by^9`QxJv5 zHjl?NEpVEPINjb~s%aLOrIZQ$Er2cpYhwES(!o;>ZWd4fj>h!yt-vP^&Rzf~rSJ-% zg@aKFTLZW-2{m&$=#dIvD=Zf1XvcR*1&`sq0ThV$zmI09^NGMv1M6&ojS7EJsBiOF z8n;M=9{?nvrNFcK_*#Yg1^TDhK}Ke?#C57YX(PO#~hmZ&YIfXpm0?Of77b zcz4lUy){(?;9j;d=Zg=NarIQ8n^{2*frBCRE`gImI7i`?I3Q90+X5fTF_*Oh*9+WO z1x|lZpeTTXIJ}Zj$9dYg#Asf_jNm>ECo6nxzAm326$kDY0%zN14N};eq2A;GS}N34 z_?^POB%Ep+b3>f}wIrZv1mNKjYL#A=I=IZiomF5OUkN;%%t28n`n7hnwKmOUxi!^C z?!7sJ)RYjqCgH3A+6T}!^hf+gd!G=mbKa5;2^2Z#5Q*l| zfdhdl0@EDyF+dtC++#s#w6j4H&?112wh__NE(zy`FhF3r<@t|C0A7{B|L)KTzz$ld zr)$xAGn~&v$ExqQqQD+9qd48hXc$805H1yOr8Q%W^E8V!qcoEr7HA|sO)M9(j7va) zLPO)u<>K8*eH(mXo|E4b6{n4!WlMoas%ZhvALqY1(?UYejX$qum2H*6CFz(2o?R^x zDEv(hmVvj&jg=p^uDHvkZKlwQXnG#Q_KXL#Ubbsr9Nn7x7-IFOx}g0W@Fj z20>x8!ootY1Jtn~{dF~g`?~m)`Q!|iyHa6%kmfQnQM3*U9~p3ePDSc@Q2%*2Wf?S% zmJ%okp_W5IHRG)GOwilcdW(Gu*4g{T~>dyLTd*<7nqH5>P4bO#m15lF^bQk0@fXG4I;>Zi8G4~)h=aS0UnUjaR`^J~?z=+$ zHTWKdViR&!n`TiY-;I@$Nas4sHq*3$R%RqSBP!U};>Y>BK#9N@@vNzKHf)UY&9JQQ zCMxp?bTg|ev(NnmCWO%6!B~MAp&w|lz>EMc4xx`RjCHn%FPzVQekwkb8YeK{!Gi*~ zsNb|P0)6c!`IJklP`iK9vb6vc-7RoHJ0Nq5dRwk5m+UDA)gAo?O?LN0*eFN#QW*D#LIwjzkygL(4{)S zRcNGevoWb@0%ujrt~sxh79Qi@G*o92@TaP*zZ6=F7pc}Mlq8{3Nv<1-3c80vD-#)#iR!fAg3`3i=|n0Ep+VCB*yVN$x?2_YiZ5k$@3&Tcz#W!=Gm9%=?NxpL Y19h*OP%`Tk_W%F@07*qoM6N<$g8#_jNdN!< literal 0 HcmV?d00001 diff --git a/speaker/MainWindow.xaml b/sound/speaker/MainWindow.xaml similarity index 72% rename from speaker/MainWindow.xaml rename to sound/speaker/MainWindow.xaml index 9ed94b625..312a13593 100644 --- a/speaker/MainWindow.xaml +++ b/sound/speaker/MainWindow.xaml @@ -2,10 +2,10 @@ xmlns="http://schemas.microsoft.com/winfx/2006/xaml/presentation" xmlns:x="http://schemas.microsoft.com/winfx/2006/xaml" Title="OpenTX Speaker" - Height="460" + Height="514" MinWidth="840" MaxWidth="840" - ResizeMode="CanResizeWithGrip" MinHeight="460" SizeToContent="Width"> + ResizeMode="CanResizeWithGrip" MinHeight="514" SizeToContent="Width" Icon="/OpenTXspeaker;component/icon.ico"> @@ -71,7 +71,7 @@ - + + + + + + + + @@ -91,7 +106,7 @@ - + + + + + + + + - - + + - -