Many details commited

This commit is contained in:
bsongis
2011-09-21 20:31:44 +00:00
parent c1e7fba8d9
commit 807e76f112
4 changed files with 19 additions and 27 deletions
+3 -18
View File
@@ -308,10 +308,9 @@ ISR(USART0_RX_vect)
}
/*
USART0 (transmit) Data Register Emtpy ISR
Usef to transmit FrSky data packets, which are buffered in frskyTXBuffer.
USART0 Transmit Data Register Emtpy ISR
Used to transmit FrSky data packets
*/
ISR(USART0_UDRE_vect)
{
if (frskyTxBufferCount > 0) {
@@ -395,24 +394,10 @@ inline void FRSKY_EnableTXD(void)
inline void FRSKY_EnableRXD(void)
{
UCSR0B |= (1 << RXEN0); // enable RX
UCSR0B |= (1 << RXCIE0); // enable Interrupt
}
#if 0
void FRSKY_DisableTXD(void)
{
UCSR0B &= ~((1 << TXEN0) | (1 << UDRIE0)); // disable TX pin and interrupt
}
void FRSKY_DisableRXD(void)
{
UCSR0B &= ~(1 << RXEN0); // disable RX
UCSR0B &= ~(1 << RXCIE0); // disable Interrupt
}
#endif
void FRSKY_Init(void)
{
// clear frsky variables
@@ -431,7 +416,7 @@ void FRSKY_Init(void)
UBRR0L = UBRRL_VALUE;
UCSR0A &= ~(1 << U2X0); // disable double speed operation.
// set 8 N1
// set 8N1
UCSR0B = 0 | (0 << RXCIE0) | (0 << TXCIE0) | (0 << UDRIE0) | (0 << RXEN0) | (0 << TXEN0) | (0 << UCSZ02);
UCSR0C = 0 | (1 << UCSZ01) | (1 << UCSZ00);