diff --git a/src/Makefile b/src/Makefile index 9aa83ad17..c2d1628ca 100644 --- a/src/Makefile +++ b/src/Makefile @@ -126,13 +126,12 @@ COPY = cp WINSHELL = cmd IMG2LBM = python ../util/img2lbm.py -AREV = $(shell sh -c "cat .svn/entries | sed -n '4p'") -REV = $(shell echo $$(( $(AREV) + 1 ))) +REV = $(shell sh -c "svnversion | egrep -o '[[:digit:]]+[[:alpha:]]*$$'") # MCU name ifeq ($(PCB), ARM) - MCU = cortex-m3 - BOARDSRC = board_arm.cpp + MCU = cortex-m3 + BOARDSRC = board_arm.cpp endif ifeq ($(PCB), STD) MCU = atmega64 @@ -156,7 +155,7 @@ TARGET = open9x OBJDIR = obj # List C++ source files here. (C dependencies are automatically generated.) -CPPSRC = open9x.cpp pulses.cpp stamp.cpp menus.cpp model_menus.cpp general_menus.cpp main_views.cpp statistics_views.cpp pers.cpp file.cpp lcd.cpp drivers.cpp o9xstrings.cpp +CPPSRC = open9x.cpp pulses.cpp stamp.cpp menus.cpp model_menus.cpp general_menus.cpp main_views.cpp statistics_views.cpp eeprom_avr.cpp lcd.cpp drivers.cpp o9xstrings.cpp ifeq ($(EXT), JETI) CPPSRC += jeti.cpp @@ -172,10 +171,10 @@ endif # Disk IO support (PCB V2+ only) ifneq ($(PCB), STD) - CPPSRC += gtime.cpp - CPPSRC += rtc.cpp - CPPSRC += ff.cpp - CPPSRC += diskio.cpp + CPPSRC += gruvin9x/gtime.cpp + CPPSRC += gruvin9x/rtc.cpp + CPPSRC += gruvin9x/ff.cpp + CPPSRC += gruvin9x/diskio.cpp endif # List Assembler source files here. @@ -205,7 +204,7 @@ DBGFMT = dwarf-2 # Each directory must be seperated by a space. # Use forward slashes for directory separators. # For a directory that has spaces, enclose it in quotes. -EXTRAINCDIRS = translations +EXTRAINCDIRS = . translations # Compiler flag to set the C Standard level. @@ -297,6 +296,7 @@ endif ifeq ($(PCB), V4) # V4 PCB, so ... CPPDEFS += -DPCBV4 -DAUDIO + EXTRAINCDIRS += gruvin9x CPPSRC += audio.cpp ifeq ($(NAVIGATION), RE1) @@ -304,13 +304,13 @@ ifeq ($(PCB), V4) endif ifeq ($(LOGS), YES) - CPPSRC += logs.cpp + CPPSRC += gruvin9x/logs.cpp CPPDEFS += -DLOGS MODS:=${MODS}L endif ifeq ($(SOMO), YES) - CPPSRC += somo14d.cpp + CPPSRC += gruvin9x/somo14d.cpp CPPDEFS += -DSOMO endif else @@ -691,8 +691,8 @@ FOXLIB=-L/usr/local/lib \ -lFOX-1.6 \ -Wl,-rpath,$(FOXPATH)/src/.libs -simu: $(CPPSRC) Makefile simu.cpp $(CPPSRC) simpgmspace.cpp *.h *.lbm eeprom.bin - g++ simu.cpp $(CPPFLAGS) $(CPPSRC) simpgmspace.cpp $(ARCH) -MD -DSIMU -o simu $(FOXINC) $(FOXLIB) -pthread +simu: $(BOARDSRC) $(CPPSRC) Makefile simu.cpp simpgmspace.cpp *.h *.lbm eeprom.bin + g++ simu.cpp $(BOARDSRC) $(CPPFLAGS) $(CPPSRC) simpgmspace.cpp $(ARCH) -MD -DSIMU -o simu $(FOXINC) $(FOXLIB) -pthread eeprom.bin: dd if=/dev/zero of=$@ bs=1 count=2048 diff --git a/src/beeper.h b/src/beeper.h index 329a4b5ef..eff644460 100644 --- a/src/beeper.h +++ b/src/beeper.h @@ -68,7 +68,7 @@ extern void beep(uint8_t val); #define IS_AUDIO_BUSY() (g_beepCnt || beepAgain || beepOn) -#if not defined(PCBARM) +#if !defined(PCBARM) FORCEINLINE void AUDIO_HEARTBEAT() { if(g_beepCnt) { diff --git a/src/board_gruvin9x.cpp b/src/board_gruvin9x.cpp index 40dbf3406..10a26ea68 100644 --- a/src/board_gruvin9x.cpp +++ b/src/board_gruvin9x.cpp @@ -69,7 +69,10 @@ inline void board_init() } #endif -FORCEINLINE uint8_t keyDown() +#ifndef SIMU +FORCEINLINE +#endif +uint8_t keyDown() { return (~PINL) & 0x3F; } @@ -128,7 +131,9 @@ bool keyState(EnumKeys enuk) return result; } - +#ifndef SIMU +FORCEINLINE +#endif void readKeysAndTrims() { /* Original keys were connected to PORTB as follows: diff --git a/src/board_stock.cpp b/src/board_stock.cpp index 6da398cbe..05db3c352 100644 --- a/src/board_stock.cpp +++ b/src/board_stock.cpp @@ -68,7 +68,10 @@ inline void board_init() } #endif -FORCEINLINE uint8_t keyDown() +#ifndef SIMU +FORCEINLINE +#endif +uint8_t keyDown() { return (~PINB) & 0x7E; } @@ -142,7 +145,10 @@ bool keyState(EnumKeys enuk) return result; } -inline void readKeysAndTrims() +#ifndef SIMU +FORCEINLINE +#endif +void readKeysAndTrims() { uint8_t enuk = KEY_MENU; diff --git a/src/drivers.cpp b/src/drivers.cpp index 45a2b25f5..3e27cc530 100644 --- a/src/drivers.cpp +++ b/src/drivers.cpp @@ -33,66 +33,6 @@ #include "open9x.h" -uint16_t eeprom_pointer; -const char* eeprom_buffer_data; -volatile int8_t eeprom_buffer_size = 0; - -#if not defined(SIMU) and not defined(PCBARM) - -inline void eeprom_write_byte() -{ - EEAR = eeprom_pointer; - EEDR = *eeprom_buffer_data; -#if defined (PCBV4) - EECR |= 1< 0) { - eeprom_write_byte(); - } - else { -#if defined (PCBV4) - EECR &= ~(1< 0) wdt_reset(); - } -} - static uint8_t s_evt; void putEvent(uint8_t evt) { @@ -251,7 +191,7 @@ void per10ms() if(mixWarning & 2) if(((g_tmr10ms&0xFF)== 64) || ((g_tmr10ms&0xFF)== 72)) AUDIO_MIX_WARNING_2(); if(mixWarning & 4) if(((g_tmr10ms&0xFF)==128) || ((g_tmr10ms&0xFF)==136) || ((g_tmr10ms&0xFF)==144)) AUDIO_MIX_WARNING_3(); -#if defined(FRSKY_HUB) or defined(WS_HOW_HIGH) +#if defined(FRSKY_HUB) || defined(WS_HOW_HIGH) static uint16_t s_varioTmr = 0; if (isFunctionActive(FUNC_VARIO)) { diff --git a/src/eeprom_arm.cpp b/src/eeprom_arm.cpp new file mode 100644 index 000000000..edb687f12 --- /dev/null +++ b/src/eeprom_arm.cpp @@ -0,0 +1,1462 @@ +/* + * Author - Erez Raviv + * + * Based on th9x -> http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + + +#include +#include "open9x.h" +#include "stdio.h" +#include "inttypes.h" +#include "string.h" + +extern PROGMEM s9xsplash[] ; + + + +// Logic for storing to EERPOM/loading from EEPROM +// If main needs to wait for the eeprom, call mainsequence without actioning menus +// General configuration +// 'main' set flag STORE_GENERAL +// 'eeCheck' sees flag STORE_GENERAL, copies data, starts 2 second timer, clears flag STORE_GENERAL +// 'eeCheck' sees 2 second timer expire, locks copy, initiates write, enters WRITE_GENERAL mode +// 'eeCheck' completes write, unlocks copy, exits WRITE_GENERAL mode + +// 'main' set flag STORE_MODEL(n) + +// 'main' set flag STORE_MODEL_TRIM(n) + + +// 'main' needs to load a model + + + + + +// These may not be needed, or might just be smaller +uint8_t Spi_tx_buf[24] ; +uint8_t Spi_rx_buf[24] ; + + +struct t_file_entry File_system[MAX_MODELS+1] ; + +unsigned char ModelNames[MAX_MODELS+1][sizeof(g_model.name)] ; // Allow for general + + +//static uint32_t Eeprom_image_updated ; // Ram image changed +//static uint32_t Eeprom_sequence_no ; // Ram image changed +//static uint8_t Current_eeprom_block ; // 0 or 1 is active block +//static uint8_t Other_eeprom_block_blank ; +//static uint8_t Eeprom_process_state ; +//static uint8_t Eeprom_process_sub_no ; // Used to manage writes +//static uint8_t Eeprom_write_pending ; +//static uint8_t Eeprom_writing_block_no ; + + +uint8_t Eeprom32_process_state ; +uint8_t Eeprom32_state_after_erase ; +uint8_t Eeprom32_write_pending ; +uint8_t Eeprom32_file_index ; +uint8_t *Eeprom32_buffer_address ; +uint8_t *Eeprom32_source_address ; +uint32_t Eeprom32_address ; +uint32_t Eeprom32_data_size ; + + +uint16_t General_timer ; +uint16_t Model_timer ; +uint32_t Update_timer ; +uint8_t General_dirty ; +uint8_t Model_dirty ; + +uint8_t Ee32_general_write_pending ; +uint8_t Ee32_model_write_pending ; +uint8_t Ee32_model_delete_pending ; + + + +// States in Eeprom_process_state +#define E_IDLE 1 +//#define E_ERASESENDING 2 +//#define E_ERASEWAITING 3 +//#define E_WRITESENDING 4 +//#define E_WRITEWAITING 5 +//#define E_32ACTIVE 6 + +#define EE_WAIT 0 +#define EE_NO_WAIT 1 + + +// States in Eeprom32_process_state +#define E32_IDLE 1 +#define E32_ERASESENDING 2 +#define E32_ERASEWAITING 3 +#define E32_WRITESENDING 4 +#define E32_WRITEWAITING 5 +#define E32_READSENDING 6 +#define E32_READWAITING 7 +#define E32_BLANKCHECK 8 +#define E32_WRITESTART 9 + +//#define E32_READING 10 // Set elsewhere as a lock + + +void handle_serial( void ) ; +//void hello( void ) ; +//void dbl9x( void ) ; +//uint32_t read_switch( enum EnumKeys enuk ) ; +//uint32_t read_eeprom_block( uint32_t block_no, uint32_t immediate ) ; +//uint32_t write_eeprom_block( uint32_t block_no, uint32_t sub_no, uint32_t size, uint32_t immediate ) ; +//uint32_t eeprom_image_blank( uint32_t image_index ) ; + +bool ee32ModelExists(uint8_t id) ; +uint32_t get_current_block_number( uint32_t block_no, uint16_t *p_size, uint32_t *p_seq ) ; +uint32_t read32_eeprom_data( uint32_t eeAddress, register uint8_t *buffer, uint32_t size, uint32_t immediate ) ; +uint32_t write32_eeprom_block( uint32_t eeAddress, register uint8_t *buffer, uint32_t size, uint32_t immediate ) ; +void ee32_read_model_names( void ) ; +void ee32LoadModelName(uint8_t id, unsigned char*buf,uint8_t len) ; +void ee32_update_name( uint32_t id, uint8_t *source ) ; + + + +void eeprom_process( void ) ; +uint32_t ee32_process( void ) ; + +// New file system + +// Start with 16 model memories, initial test uses 34 and 35 for these +// Blocks 0 and 1, general +// Blocks 2 and 3, model 1 +// Blocks 4 and 5, model 2 etc +// Blocks 32 and 33, model 16 + +uint8_t Current_general_block ; // 0 or 1 is active block +uint8_t Other_general_block_blank ; + +struct t_eeprom_header +{ + uint32_t sequence_no ; // sequence # to decide which block is most recent + uint16_t data_size ; // # bytes in data area + uint8_t flags ; + uint8_t hcsum ; +} ; + +// Structure of data in a block +struct t_eeprom_block +{ + struct t_eeprom_header header ; + union + { + uint8_t bytes[4088] ; + uint32_t words[1022] ; + } data ; +} ; + +//struct t_gen_buf +//{ +// struct t_eeprom_header header ; +// EEGeneral data ; +//} ; + +//struct t_model_buf +//{ +// struct t_eeprom_header header ; +// ModelData data ; +//} ; + +#define EEPROM_BUFFER_SIZE ((sizeof(ModelData) + sizeof( struct t_eeprom_header ) + 3)/4) + + +struct t_eeprom_buffer +{ + struct t_eeprom_header header ; + union t_eeprom_data + { + EEGeneral general_data ; + ModelData model_data ; + uint32_t words[ EEPROM_BUFFER_SIZE ] ; + } data ; +} Eeprom_buffer ; + + +//union t_eeprom_buffer +//{ +// struct t_gen_buf eeGeneral_buffer ; +// struct t_model_buf eeModel_buffer ; +// uint32_t words[ EEPROM_BUFFER_SIZE ] ; +//} Eeprom_buffer ; + + + +//struct t_eeprom_block E_images[2] ; + +// Check all 4096 bytes of an image to see if they are blank +//uint32_t eeprom_image_blank( uint32_t image_index ) +//{ +// register uint32_t x ; +// register uint32_t *p ; + +// p = &E_images[image_index].sequence_no ; + +// for ( x = 0 ; x < 1024 ; x += 1 ) +// { +// if ( *p++ != 0xFFFFFFFF ) +// { +// return 0 ; +// } +// } +// return 1 ; +//} + +// genaral data needs to be written to EEPROM +void ee32StoreGeneral() +{ + General_dirty = 1 ; + General_timer = 500 ; // 5 seconds timeout before writing +} + + +// Store model to EEPROM, trim is non-zero if this is the result of a trim change +void ee32StoreModel( uint8_t modelNumber, uint8_t trim ) +{ + Model_dirty = modelNumber + 1 ; + Model_timer = 500 ; + ee32_update_name( Model_dirty, (uint8_t *)&g_model ) ; // In case it's changed +} + +void ee32_delete_model( uint8_t id ) +{ + uint8_t buffer[sizeof(g_model.name)] ; + memset( buffer, ' ', sizeof(g_model.name) ) ; + ee32_update_name( id + 1, buffer ) ; + Ee32_model_delete_pending = id + 1 ; +} + +void ee32_read_model_names() +{ + uint32_t i ; + + for ( i = 1 ; i <= MAX_MODELS ; i += 1 ) + { + ee32LoadModelName( i, ModelNames[i], sizeof(g_model.name) ) ; + } +} + +void ee32_update_name( uint32_t id, uint8_t *source ) +{ + uint8_t * p ; + uint32_t i ; + + p = ModelNames[id] ; + for ( i = 0 ; i < sizeof(g_model.name) ; i += 1 ) + { + *p++ = *source++ ; + } +} + + +// Read eeprom data starting at random address +uint32_t read32_eeprom_data( uint32_t eeAddress, register uint8_t *buffer, uint32_t size, uint32_t immediate ) +{ + register uint8_t *p ; + register uint32_t x ; + + p = Spi_tx_buf ; + *p = 3 ; // Read command + *(p+1) = eeAddress >> 16 ; + *(p+2) = eeAddress >> 8 ; + *(p+3) = eeAddress ; // 3 bytes address + spi_PDC_action( p, 0, buffer, 4, size ) ; + + if ( immediate ) + { + return 0 ; + } + for ( x = 0 ; x < 100000 ; x += 1 ) + { + if ( Spi_complete ) + { + break ; + } + } + return x ; +} + + +uint32_t write32_eeprom_block( uint32_t eeAddress, register uint8_t *buffer, uint32_t size, uint32_t immediate ) +{ + register uint8_t *p ; + register uint32_t x ; + + eeprom_write_enable() ; + + p = Spi_tx_buf ; + *p = 2 ; // Write command + *(p+1) = eeAddress >> 16 ; + *(p+2) = eeAddress >> 8 ; + *(p+3) = eeAddress ; // 3 bytes address + spi_PDC_action( p, buffer, 0, 4, size ) ; + + if ( immediate ) + { + return 0 ; + } + for ( x = 0 ; x < 100000 ; x += 1 ) + { + if ( Spi_complete ) + { + break ; + } + } + return x ; +} + +uint8_t byte_checksum( uint8_t *p, uint32_t size ) +{ + uint32_t csum ; + + csum = 0 ; + while( size ) + { + csum += *p++ ; + size -= 1 ; + } + return csum ; +} + +uint32_t ee32_check_header( struct t_eeprom_header *hptr ) +{ + uint8_t csum ; + + csum = byte_checksum( ( uint8_t *) hptr, 7 ) ; + if ( csum == hptr->hcsum ) + { + return 1 ; + } + return 0 ; +} + +// Pass in an even block number, this and the next block will be checked +// to see which is the most recent, the block_no of the most recent +// is returned, with the corresponding data size if required +// and the sequence number if required +uint32_t get_current_block_number( uint32_t block_no, uint16_t *p_size, uint32_t *p_seq ) +{ + struct t_eeprom_header b0 ; + struct t_eeprom_header b1 ; + uint32_t sequence_no ; + uint16_t size ; + read32_eeprom_data( block_no << 12, ( uint8_t *)&b0, sizeof(b0), EE_WAIT ) ; // Sequence # 0 + read32_eeprom_data( (block_no+1) << 12, ( uint8_t *)&b1, sizeof(b1), EE_WAIT ) ; // Sequence # 1 + + if ( ee32_check_header( &b0 ) == 0 ) + { + b0.sequence_no = 0 ; + b0.data_size = 0 ; + b0.flags = 0 ; + } + + size = b0.data_size ; + sequence_no = b0.sequence_no ; + if ( ee32_check_header( &b0 ) == 0 ) + { + if ( ee32_check_header( &b1 ) != 0 ) + { + size = b1.data_size ; + sequence_no = b1.sequence_no ; + block_no += 1 ; + } + else + { + size = 0 ; + sequence_no = 1 ; + } + } + else + { + if ( ee32_check_header( &b1 ) != 0 ) + { + if ( b1.sequence_no > b0.sequence_no ) + { + size = b1.data_size ; + sequence_no = b1.sequence_no ; + block_no += 1 ; + } + } + } + + if ( size == 0xFFFF ) + { + size = 0 ; + } + if ( p_size ) + { + *p_size = size ; + } + if ( sequence_no == 0xFFFFFFFF ) + { + sequence_no = 0 ; + } + if ( p_seq ) + { + *p_seq = sequence_no ; + } +// Block_needs_erasing = erase ; + + return block_no ; +} + +bool ee32LoadGeneral() +{ + uint16_t size ; + + size = File_system[0].size ; + + memset(&g_eeGeneral, 0, sizeof(EEGeneral)); + + if ( size > sizeof(EEGeneral) ) + { + size = sizeof(EEGeneral) ; + } + + if ( size ) + { + read32_eeprom_data( ( File_system[0].block_no << 12) + sizeof( struct t_eeprom_header), ( uint8_t *)&g_eeGeneral, size, 0 ) ; + } + + for(uint8_t i=0; i(sizeof(EEGeneral)-20)) for(uint8_t i=0; i<12;i++) sum+=g_eeGeneral.calibMid[i]; + return g_eeGeneral.chkSum == sum; +} + +void ee32WaitLoadModel(uint8_t id) +{ + // Wait for EEPROM to be idle + if ( General_timer ) + { + General_timer = 1 ; // Make these happen soon + } + if ( Model_timer ) + { + Model_timer = 1 ; + } + + while( ( Eeprom32_process_state != E32_IDLE ) + || ( General_timer ) + || ( Model_timer ) ) + { + mainSequence( NO_MENU ) ; // Wait for EERPOM to be IDLE + } + + ee32LoadModel( id ) ; // Now get the model +} + + +void ee32LoadModel(uint8_t id) +{ + uint16_t size ; + + if(id sizeof(g_model) ) + { + size = sizeof(g_model) ; + } + + if(size<256) // if not loaded a fair amount + { + modelDefault(id) ; + } + else + { + read32_eeprom_data( ( File_system[id+1].block_no << 12) + sizeof( struct t_eeprom_header), ( uint8_t *)&g_model, size, 0 ) ; + } + + for(uint8_t i=0; i 0 ) ; +} + +void ee32LoadModelName( uint8_t id, unsigned char*buf, uint8_t len ) +{ + if(id<=MAX_MODELS) + { + memset(buf,' ',len); + if ( File_system[id].size > sizeof(g_model.name) ) + { + read32_eeprom_data( ( File_system[id].block_no << 12) + 8, ( uint8_t *)buf, sizeof(g_model.name), 0 ) ; + } + } +} + + +void fill_file_index() +{ + uint32_t i ; + for ( i = 0 ; i < MAX_MODELS + 1 ; i += 1 ) + { + File_system[i].block_no = get_current_block_number( i * 2, &File_system[i].size, &File_system[i].sequence_no ) ; + } +} + +void init_ee32() +{ + fill_file_index() ; + ee32_read_model_names() ; + Eeprom32_process_state = E32_IDLE ; +} + +uint32_t ee32_check_finished() +{ + if ( ( Eeprom32_process_state != E32_IDLE ) + || ( General_timer ) + || ( Model_timer ) ) + { + ee32_process() ; + return 0 ; + } + return 1 ; +} + + +uint32_t ee32_process() +{ + register uint8_t *p ; + register uint8_t *q ; + register uint32_t x ; + register uint32_t eeAddress ; + +// return 0 ; + + if ( General_timer ) + { + if ( --General_timer == 0 ) + { + + // Time to write g_eeGeneral + Ee32_general_write_pending = 1 ; + } + } + if ( Model_timer ) + { + if ( --Model_timer == 0 ) + { + + // Time to write model + Ee32_model_write_pending = 1 ; + } + } + + if ( Eeprom32_process_state == E32_IDLE ) + { + if ( Ee32_general_write_pending ) + { + Ee32_general_write_pending = 0 ; // clear flag + + // Check we can write, == block is blank + + Eeprom32_source_address = (uint8_t *)&g_eeGeneral ; // Get data fromm here + Eeprom32_data_size = sizeof(g_eeGeneral) ; // This much + Eeprom32_file_index = 0 ; // This file system entry + Eeprom32_process_state = E32_BLANKCHECK ; +// Writing_model = 0 ; + } + else if ( Ee32_model_write_pending ) + { + Ee32_model_write_pending = 0 ; // clear flag + + // Check we can write, == block is blank + + Eeprom32_source_address = (uint8_t *)&g_model ; // Get data from here + Eeprom32_data_size = sizeof(g_model) ; // This much + Eeprom32_file_index = Model_dirty ; // This file system entry + Eeprom32_process_state = E32_BLANKCHECK ; +// Writing_model = Model_dirty ; + } + else if ( Ee32_model_delete_pending ) + { + Eeprom32_source_address = (uint8_t *)&g_model ; // Get data from here + Eeprom32_data_size = 0 ; // This much + Eeprom32_file_index = Ee32_model_delete_pending ; // This file system entry + Ee32_model_delete_pending = 0 ; + Eeprom32_process_state = E32_BLANKCHECK ; + } + } + + if ( Eeprom32_process_state == E32_BLANKCHECK ) + { + eeAddress = File_system[Eeprom32_file_index].block_no ^ 1 ; + eeAddress <<= 12 ; // Block start address + Eeprom32_address = eeAddress ; // Where to put new data + x = Eeprom32_data_size + sizeof( struct t_eeprom_header ) ; // Size needing to be checked + p = (uint8_t *) &Eeprom_buffer ; + read32_eeprom_data( eeAddress, p, x, 1 ) ; + Eeprom32_process_state = E32_READSENDING ; + } + + if ( Eeprom32_process_state == E32_READSENDING ) + { + if ( Spi_complete ) + { + uint32_t blank = 1 ; + x = Eeprom32_data_size + sizeof( struct t_eeprom_header ) ; // Size needing to be checked + p = (uint8_t *) &Eeprom_buffer ; + while ( x ) + { + if ( *p++ != 0xFF ) + { + blank = 0 ; + break ; + } + x -= 1 ; + } + // If not blank, sort erasing here + if ( blank ) + { + Eeprom32_state_after_erase = E32_IDLE ; + Eeprom32_process_state = E32_WRITESTART ; + } + else + { + eeAddress = Eeprom32_address ; + eeprom_write_enable() ; + p = Spi_tx_buf ; + *p = 0x20 ; // Block Erase command + *(p+1) = eeAddress >> 16 ; + *(p+2) = eeAddress >> 8 ; + *(p+3) = eeAddress ; // 3 bytes address + spi_PDC_action( p, 0, 0, 4, 0 ) ; + Eeprom32_process_state = E32_ERASESENDING ; + Eeprom32_state_after_erase = E32_WRITESTART ; + } + } + } + + if ( Eeprom32_process_state == E32_WRITESTART ) + { + uint32_t total_size ; + p = Eeprom32_source_address ; + q = (uint8_t *)&Eeprom_buffer.data ; + for ( x = 0 ; x < Eeprom32_data_size ; x += 1 ) + { + *q++ = *p++ ; // Copy the data to temp buffer + } + Eeprom_buffer.header.sequence_no = ++File_system[Eeprom32_file_index].sequence_no ; + File_system[Eeprom32_file_index].size = Eeprom_buffer.header.data_size = Eeprom32_data_size ; + Eeprom_buffer.header.flags = 0 ; + Eeprom_buffer.header.hcsum = byte_checksum( (uint8_t *)&Eeprom_buffer, 7 ) ; + total_size = Eeprom32_data_size + sizeof( struct t_eeprom_header ) ; + eeAddress = Eeprom32_address ; // Block start address + x = total_size / 256 ; // # sub blocks + x <<= 8 ; // to offset address + eeAddress += x ; // Add it in + p = (uint8_t *) &Eeprom_buffer ; + p += x ; // Add offset + x = total_size % 256 ; // Size of last bit + if ( x == 0 ) // Last bit empty + { + x = 256 ; + p -= x ; + eeAddress -= x ; + } + Eeprom32_buffer_address = p ; + Eeprom32_address = eeAddress ; + write32_eeprom_block( eeAddress, p, x, 1 ) ; + Eeprom32_process_state = E32_WRITESENDING ; + } + + if ( Eeprom32_process_state == E32_WRITESENDING ) + { + if ( Spi_complete ) + { + Eeprom32_process_state = E32_WRITEWAITING ; + } + } + + if ( Eeprom32_process_state == E32_WRITEWAITING ) + { + x = eeprom_read_status() ; + if ( ( x & 1 ) == 0 ) + { + if ( ( Eeprom32_address & 0x0FFF ) != 0 ) // More to write + { + Eeprom32_address -= 256 ; + Eeprom32_buffer_address -= 256 ; + write32_eeprom_block( Eeprom32_address, Eeprom32_buffer_address, 256, 1 ) ; + Eeprom32_process_state = E32_WRITESENDING ; + } + else + { + // now erase the other block + File_system[Eeprom32_file_index].block_no ^= 1 ; // This is now the current block + eeAddress = Eeprom32_address ^ 0x00001000 ; // Address of block to erase + eeprom_write_enable() ; + p = Spi_tx_buf ; + *p = 0x20 ; // Block Erase command + *(p+1) = eeAddress >> 16 ; + *(p+2) = eeAddress >> 8 ; + *(p+3) = eeAddress ; // 3 bytes address + spi_PDC_action( p, 0, 0, 4, 0 ) ; + Eeprom32_process_state = E32_ERASESENDING ; + Eeprom32_state_after_erase = E32_IDLE ; + } + } + } + + if ( Eeprom32_process_state == E32_ERASESENDING ) + { + if ( Spi_complete ) + { + Eeprom32_process_state = E32_ERASEWAITING ; + } + } + + if ( Eeprom32_process_state == E32_ERASEWAITING ) + { + x = eeprom_read_status() ; + if ( ( x & 1 ) == 0 ) + { // Command finished + Eeprom32_process_state = Eeprom32_state_after_erase ; + } + } + + if ( Eeprom32_process_state == E32_IDLE ) + { + return 0 ; // inactive + } + else + { + return 1 ; + } +} + + +// Temporary eeprom handling - hence it's here + +// storage defination +//struct t_eeprom_image +//{ +// uint8_t spi_command[4] ; +// union +// { +// uint8_t bytes[2048] ; +// uint32_t words[512] ; +// } image ; +// uint32_t sequence_no ; +// uint32_t filler[3] ; +// union +// { +// uint8_t bytes[2016] ; +// uint32_t words[504] ; +// } imagex ; +//} ; + +// storage declaration +//struct t_eeprom_image E_images[2] ; + + +//void eeprom_process() +//{ +// register uint8_t *p ; +// register uint8_t *q ; +// register uint32_t block_no ; +// register uint32_t x ; + +// if ( Eeprom_image_updated ) +// { +// Eeprom_image_updated = 0 ; +// Update_timer = 100 ; // 1 second +// } +// if ( Update_timer ) +// { +// if ( --Update_timer == 0 ) +// { +// // Changed, but no changes for 2 seconds +// // Time to write changes to eeprom +// Eeprom_write_pending = 1 ; +// } +// } + +// ee32_process() ; + + +// if ( ( Eeprom_process_state == E_32ACTIVE ) || ( Eeprom_process_state == E_IDLE ) ) +// { +// if ( ee32_process() ) +// { +// Eeprom_process_state = E_32ACTIVE ; +// return ; +// } +// else +// { +// Eeprom_process_state = E_IDLE ; +// } +// } + + +// if ( Eeprom_process_state == E_IDLE ) +// { +// if ( Other_eeprom_block_blank == 0 ) +// { +// // Need to erase it +// Eeprom_process_state = E_ERASESENDING ; +// block_no = 0 ; +// if ( Current_eeprom_block == 0 ) +// { +// block_no = 1 ; +// } +// eeprom_write_enable() ; +// p = E_images[block_no].spi_command ; +// *p = 0x20 ; // Block Erase command +// *(p+1) = 0 ; +// *(p+2) = block_no << 4 ; +// *(p+3) = 0 ; // 3 bytes address +// spi_PDC_action( p, 0, 0, 4, 0 ) ; +// } +// else if ( Eeprom_write_pending ) +// { +// Eeprom_write_pending = 0 ; +// block_no = 0 ; +// if ( Current_eeprom_block == 0 ) +// { +// block_no = 1 ; +// } +// // Copy data from RAM based eeprom image + +// p = E_images[block_no].image.bytes ; +// q = eeprom ; +// for ( x = 0 ; x < 2048 ; x += 1 ) +// { +// *p++ = *q++ ; +// } +// E_images[block_no].sequence_no = Eeprom_sequence_no + 1 ; +// Eeprom_process_sub_no = 0 ; +// write_eeprom_block( block_no, Eeprom_process_sub_no, 256, 1 ) ; +// Eeprom_process_state = E_WRITESENDING ; +// Eeprom_writing_block_no = block_no ; +// } +// } + +// if ( Eeprom_process_state == E_ERASESENDING ) +// { +// if ( Spi_complete ) +// { +// Eeprom_process_state = E_ERASEWAITING ; +// } +// } + +// if ( Eeprom_process_state == E_ERASEWAITING ) +// { +// x = eeprom_read_status() ; +// if ( ( x & 1 ) == 0 ) +// { // Command finished +// Eeprom_process_state = E_IDLE ; +// Other_eeprom_block_blank = 1 ; +// } +// } + +// if ( Eeprom_process_state == E_WRITESENDING ) +// { +// if ( Spi_complete ) +// { +// Eeprom_process_state = E_WRITEWAITING ; +// } +// } + +// if ( Eeprom_process_state == E_WRITEWAITING ) +// { +// x = eeprom_read_status() ; +// if ( ( x & 1 ) == 0 ) +// { +// register uint32_t size ; +// Eeprom_process_sub_no += 1 ; +// size = 256 ; +// if ( Eeprom_process_sub_no == 8) +// { +// size = 4 ; +// } +// if ( Eeprom_process_sub_no > 8) +// { +// size = 0 ; +// } +// if ( size > 0 ) +// { +// write_eeprom_block( Eeprom_writing_block_no, Eeprom_process_sub_no, size, 1 ) ; +// Eeprom_process_state = E_WRITESENDING ; +// } +// else +// { +// Eeprom_process_state = E_IDLE ; +// Current_eeprom_block = Eeprom_writing_block_no ; +// Other_eeprom_block_blank = 0 ; +// } +// } +// } +//} + + +void init_eeprom() +{ +// register uint32_t x ; +// register uint32_t y ; +// register uint8_t *p ; +// register uint8_t *q ; +// register uint32_t valid ; + +// read_eeprom_block( 0, 0 ) ; +// read_eeprom_block( 1, 0 ) ; + + // Here we should find which block is the most recent +// x = eeprom_image_blank( 0 ) ; +// y = eeprom_image_blank( 1 ) ; + +// Eeprom_process_state = E_IDLE ; +// Eeprom_process_sub_no = 0 ; +// Eeprom_write_pending = 0 ; +// if ( x ) +// { +// if ( y ) +// { // Both blank +// Other_eeprom_block_blank = 1 ; +// Current_eeprom_block = 1 ; +// Eeprom_sequence_no = 0 ; +// } +// else +// { // Block 1 is active, 0 is blank +// Other_eeprom_block_blank = 1 ; +// Current_eeprom_block = 1 ; +// Eeprom_sequence_no = E_images[1].sequence_no ; +// } +// } +// else +// { +// if ( y ) +// { // Block 0 is active, 1 is blank +// Other_eeprom_block_blank = 1 ; +// Current_eeprom_block = 0 ; +// Eeprom_sequence_no = E_images[0].sequence_no ; + +// } +// else +// { // Check sequence number and erase other block +// Other_eeprom_block_blank = 0 ; +// x = E_images[0].sequence_no ; +// y = E_images[1].sequence_no ; +// if ( y == 0xFFFFFFFF ) +// { +// y = 0 ; +// } +// if ( x == 0xFFFFFFFF ) +// { +// x = 0 ; +// } +// if ( x > y ) // Simple test, assumes no 32 bit overflow +// { +// Current_eeprom_block = 0 ; +// Eeprom_sequence_no = x ; +// } +// else +// { +// Current_eeprom_block = 1 ; +// Eeprom_sequence_no = y ; +// } +// } +// } + +// // Copy valid block to RAM eeprom image +// p = E_images[Current_eeprom_block].image.bytes ; +// q = eeprom ; +// for ( x = 0 ; x < 2048 ; x += 1 ) +// { +// *q++ = *p++ ; +// } +// disp_256( (uint32_t)eeprom, 6 ) ; +// Eeprom_process_state = E_IDLE ; + + init_ee32() ; +} + + +//uint32_t eeprom_image_blank( uint32_t image_index ) +//{ +// register uint32_t x ; +// register uint32_t *p ; +// register uint32_t result ; + +// result = 1 ; +// p = E_images[image_index].image.words ; + +// for ( x = 0 ; x < 512 ; x += 1 ) +// { +// if ( *p++ != 0xFFFFFFFF ) +// { +// result = 0 ; +// } +// } +// if ( result ) +// { +// x = E_images[image_index].sequence_no ; +// if ( x != 0xFFFFFFFF ) +// { +// result = 0 ; +// } +// } +// return result ; +//} + + +//uint32_t read_eeprom_block( uint32_t block_no, uint32_t immediate ) +//{ +// register uint8_t *p ; +// register uint32_t x ; + +// p = E_images[block_no].spi_command ; +// *p = 3 ; // Read command +// *(p+1) = 0 ; +// *(p+2) = block_no << 4 ; +// *(p+3) = 0 ; // 3 bytes address +// spi_PDC_action( p, 0, E_images[block_no].image.bytes, 4, 2048 + 4 ) ; + +// if ( immediate ) +// { +// return 0 ; +// } +// for ( x = 0 ; x < 100000 ; x += 1 ) +// { +// if ( Spi_complete ) +// { +// break ; +// } +// } +// return x ; + +//// return spi_action( p, E_images[block_no].image, E_images[block_no].image, 4, 2048 + 4 ) ; +//} + +//uint32_t write_eeprom_block( uint32_t block_no, uint32_t sub_no, uint32_t size, uint32_t immediate ) +//{ +// register uint8_t *p ; +// register uint32_t x ; + +// eeprom_write_enable() ; + +// p = E_images[block_no].spi_command ; +// *p = 2 ; // Write command +// *(p+1) = 0 ; +// *(p+2) = (block_no << 4) + sub_no ; +// *(p+3) = 0 ; // 3 bytes address +// spi_PDC_action( p, &E_images[block_no].image.bytes[sub_no << 8], 0, 4, size ) ; + +// if ( immediate ) +// { +// return 0 ; +// } +// for ( x = 0 ; x < 100000 ; x += 1 ) +// { +// if ( Spi_complete ) +// { +// break ; +// } +// } +// return x ; +//// return spi_action( p, E_images[block_no].image[sub_no << 8], 0, 4, size ) ; +//} + + + +//uint32_t write_eeprom_status( uint8_t value ) +//{ +// register uint8_t *p ; + +// eeprom_write_enable() ; + +// p = Spi_tx_buf ; +// *p = 1 ; // Write status register command +// *(p+1) = value ; + +// return spi_operation( p, Spi_rx_buf, 2 ) ; +//} + +uint32_t unprotect_eeprom() +{ + register uint8_t *p ; + + eeprom_write_enable() ; + + p = Spi_tx_buf ; + *p = 0x39 ; // Unprotect sector command + *(p+1) = 0 ; + *(p+2) = 0 ; + *(p+3) = 0 ; // 3 bytes address + + return spi_operation( p, Spi_rx_buf, 4 ) ; +} + +// +// bs=16 128 blocks verlust link:128 16files:16*8 128 sum 256 +// bs=32 64 blocks verlust link: 64 16files:16*16 256 sum 320 +// +//# define EESIZE 2048 +//# define BS 16 +//# define RESV 64 //reserv for eeprom header with directory (eeFs) + +//#define FIRSTBLK (RESV/BS) +//#define BLOCKS (EESIZE/BS) + +//#define EEFS_VERS 4 +//struct DirEnt{ +// uint8_t startBlk; +// uint16_t size:12; +// uint16_t typ:4; +//}__attribute__((packed)); +//#define MAXFILES (1+MAX_MODELS+3) +//struct EeFs{ +// uint8_t version; +// uint8_t mySize; +// uint8_t freeList; +// uint8_t bs; +// DirEnt files[MAXFILES]; +//}__attribute__((packed)) eeFs; + + +//static uint8_t EeFsRead(uint8_t blk,uint8_t ofs){ +// uint8_t ret; +// eeprom_read_block(&ret,(const void*)(blk*BS+ofs),1); +// return ret; +//} +//static void EeFsWrite(uint8_t blk,uint8_t ofs,uint8_t val){ +// eeWriteBlockCmp(&val, (void*)(blk*BS+ofs), 1); +//} + +//static uint8_t EeFsGetLink(uint8_t blk){ +// return EeFsRead( blk,0); +//} +//static void EeFsSetLink(uint8_t blk,uint8_t val){ +// EeFsWrite( blk,0,val); +//} +//static uint8_t EeFsGetDat(uint8_t blk,uint8_t ofs){ +// return EeFsRead( blk,ofs+1); +//} +//static void EeFsSetDat(uint8_t blk,uint8_t ofs,uint8_t*buf,uint8_t len){ +// //EeFsWrite( blk,ofs+1,val); +// eeWriteBlockCmp(buf, (void*)(blk*BS+ofs+1), len); +//} +//static void EeFsFlushFreelist() +//{ +// eeWriteBlockCmp(&eeFs.freeList,&((EeFs*)0)->freeList ,sizeof(eeFs.freeList)); +//} +//static void EeFsFlush() +//{ +// eeWriteBlockCmp(&eeFs, 0,sizeof(eeFs)); +//} + +//uint16_t EeFsGetFree() +//{ +// uint16_t ret = 0; +// uint8_t i = eeFs.freeList; +// while( i ){ +// ret += BS-1; +// i = EeFsGetLink(i); +// } +// return ret; +//} +//static void EeFsFree(uint8_t blk){///free one or more blocks +// uint8_t i = blk; +// while( EeFsGetLink(i)) i = EeFsGetLink(i); +// EeFsSetLink(i,eeFs.freeList); +// eeFs.freeList = blk; //chain in front +// EeFsFlushFreelist(); +//} +//static uint8_t EeFsAlloc(){ ///alloc one block from freelist +// uint8_t ret=eeFs.freeList; +// if(ret){ +// eeFs.freeList = EeFsGetLink(ret); +// EeFsFlushFreelist(); +// EeFsSetLink(ret,0); +// } +// return ret; +//} + +//int8_t EeFsck() +//{ +// uint8_t *bufp; +// static uint8_t buffer[BLOCKS]; +// bufp = buffer; +// memset(bufp,0,BLOCKS); +// uint8_t blk ; +// int8_t ret=0; +// for(uint8_t i = 0; i <= MAXFILES; i++){ +// uint8_t *startP = i==MAXFILES ? &eeFs.freeList : &eeFs.files[i].startBlk; +// uint8_t lastBlk = 0; +// blk = *startP; +// //if(i == MAXFILES) blk = eeFs.freeList; +// // else blk = eeFs.files[i].startBlk; +// while(blk){ +// // if(blk < FIRSTBLK ) goto err_1; //bad blk index +// // if(blk >= BLOCKS ) goto err_2; //bad blk index +// // if(bufp[blk]) goto err_3; //blk double usage +// if( ( blk < FIRSTBLK ) //goto err_1; //bad blk index +// || (blk >= BLOCKS ) //goto err_2; //bad blk index +// || (bufp[blk] ))//goto err_3; //blk double usage +// { +// if(lastBlk){ +// EeFsSetLink(lastBlk,0); +// }else{ +// *startP = 0; //interrupt chain at startpos +// EeFsFlush(); +// } +// blk=0; //abort +// }else{ +// bufp[blk] = i+1; +// lastBlk = blk; +// blk = EeFsGetLink(blk); +// } +// } +// } +// for(blk = FIRSTBLK; blk < BLOCKS; blk++){ +// if(bufp[blk]==0) { //goto err_4; //unused block +// EeFsSetLink(blk,eeFs.freeList); +// eeFs.freeList = blk; //chain in front +// EeFsFlushFreelist(); +// } +// } +// // if(0){ +// //err_4: ret--; +// //err_3: ret--; +// // err_2: ret--; +// // err_1: ret--; +// // } +// return ret; +//} +//void EeFsFormat() +//{ +// if(sizeof(eeFs) != RESV){ +// extern void eeprom_RESV_mismatch(); +// eeprom_RESV_mismatch(); +// } +// memset(&eeFs,0, sizeof(eeFs)); +// eeFs.version = EEFS_VERS; +// eeFs.mySize = sizeof(eeFs); +// eeFs.freeList = 0; +// eeFs.bs = BS; +// for(uint8_t i = FIRSTBLK; i < BLOCKS; i++) EeFsSetLink(i,i+1); +// EeFsSetLink(BLOCKS-1, 0); +// eeFs.freeList = FIRSTBLK; +// EeFsFlush(); +//} +//bool EeFsOpen() +//{ +// eeprom_read_block(&eeFs,0,sizeof(eeFs)); + +// return eeFs.version == EEFS_VERS && eeFs.mySize == sizeof(eeFs); +//} + +//bool EFile::exists(uint8_t i_fileId) +//{ +// return eeFs.files[i_fileId].startBlk; +//} + +//void EFile::swap(uint8_t i_fileId1,uint8_t i_fileId2) +//{ +// DirEnt tmp = eeFs.files[i_fileId1]; +// eeFs.files[i_fileId1] = eeFs.files[i_fileId2]; +// eeFs.files[i_fileId2] = tmp;; +// EeFsFlush(); +//} + +//void EFile::rm(uint8_t i_fileId){ +// uint8_t i = eeFs.files[i_fileId].startBlk; +// memset(&eeFs.files[i_fileId], 0, sizeof(eeFs.files[i_fileId])); +// EeFsFlush(); //chained out + +// if(i) EeFsFree( i ); //chain in +//} + +//uint16_t EFile::size(){ +// return eeFs.files[m_fileId].size; +//} + + +//uint8_t EFile::openRd(uint8_t i_fileId){ +// m_fileId = i_fileId; +// m_pos = 0; +// m_currBlk = eeFs.files[m_fileId].startBlk; +// m_ofs = 0; +// m_bRlc = 0; +// m_err = ERR_NONE; //error reasons +// return eeFs.files[m_fileId].typ; +//} +//uint8_t EFile::read(uint8_t*buf,uint16_t i_len){ +// uint16_t len = eeFs.files[m_fileId].size - m_pos; +// if(len < i_len) i_len = len; +// len = i_len; +// while(len) +// { +// if(!m_currBlk) break; +// *buf++ = EeFsGetDat(m_currBlk, m_ofs++); +// if(m_ofs>=(BS-1)){ +// m_ofs=0; +// m_currBlk=EeFsGetLink(m_currBlk); +// } +// len--; +// } +// m_pos += i_len - len; +// return i_len - len; +//} +//uint16_t EFile::readRlc(uint8_t*buf,uint16_t i_len){ +// uint16_t i; +// for( i=0; i(i_len-i)) l = (uint8_t)(i_len-i); +// if(m_bRlc&0x80){ // if contains high byte +// memset(&buf[i],0,l); // write l zeros +// }else{ +// uint8_t lr = read(&buf[i],l); // read and write l bytes +// if(lr!=l) return i+lr; +// } +// i += l; +// m_bRlc -= l; +// } +// return i; +//} +//uint8_t EFile::write(uint8_t*buf,uint8_t i_len){ +// uint8_t len=i_len; +// if(!m_currBlk && m_pos==0) +// { +// eeFs.files[m_fileId].startBlk = m_currBlk = EeFsAlloc(); +// } +// while(len) +// { +// if( (int16_t)(m_stopTime10ms - get_tmr10ms()) < 0) +// { +// m_err = ERR_TMO; +// break; +// } +// if(!m_currBlk) { +// m_err = ERR_FULL; +// break; +// } +// if(m_ofs>=(BS-1)){ +// m_ofs=0; +// if( ! EeFsGetLink(m_currBlk) ){ +// EeFsSetLink(m_currBlk, EeFsAlloc()); +// } +// m_currBlk = EeFsGetLink(m_currBlk); +// } +// if(!m_currBlk) { +// m_err = ERR_FULL; +// break; +// } +// uint8_t l = BS-1-m_ofs; if(l>len) l=len; +// EeFsSetDat(m_currBlk, m_ofs, buf, l); +// buf +=l; +// m_ofs +=l; +// len -=l; +// } +// m_pos += i_len - len; +// return i_len - len; +//} +//void EFile::create(uint8_t i_fileId, uint8_t typ, uint16_t maxTme10ms){ +// openRd(i_fileId); //internal use +// eeFs.files[i_fileId].typ = typ; +// eeFs.files[i_fileId].size = 0; +// m_stopTime10ms = get_tmr10ms() + maxTme10ms; +//} +//void EFile::closeTrunc() +//{ +// uint8_t fri=0; +// eeFs.files[m_fileId].size = m_pos; +// if(m_currBlk && ( fri = EeFsGetLink(m_currBlk))) EeFsSetLink(m_currBlk, 0); +// EeFsFlush(); //chained out + +// if(fri) EeFsFree( fri ); //chain in +//} + +//uint16_t EFile::writeRlc(uint8_t i_fileId, uint8_t typ,uint8_t*buf,uint16_t i_len, uint8_t maxTme10ms){ +// create(i_fileId,typ,maxTme10ms); +// bool state0 = true; +// uint8_t cnt = 0; +// uint16_t i; + +// //RLE compression: +// //rb = read byte +// //if (rb | 0x80) write rb & 0x7F zeros +// //else write rb bytes +// for( i=0; i<=i_len; i++) +// { +// bool nst0 = buf[i] == 0; +// if( nst0 && !state0 && buf[i+1]!=0) nst0 = false ; +// if(nst0 != state0 || cnt>=0x7f || i==i_len){ +// if(state0){ +// if(cnt>0){ +// cnt|=0x80; +// if( write(&cnt,1)!=1) goto error; +// cnt=0; +// } +// }else{ +// if(cnt>0) { +// if( write(&cnt,1) !=1) goto error; +// uint8_t ret=write(&buf[i-cnt],cnt); +// if( ret !=cnt) { cnt-=ret; goto error;} +// cnt=0; +// } +// } +// state0 = nst0; +// } +// cnt++; +// } +// if(0){ +// error: +// i_len = i - (cnt & 0x7f); +// } +// closeTrunc(); +// return i_len; +//} + + + + diff --git a/src/eeprom_arm.h b/src/eeprom_arm.h new file mode 100644 index 000000000..40678c2e3 --- /dev/null +++ b/src/eeprom_arm.h @@ -0,0 +1,115 @@ +/* + * Author - Erez Raviv + * + * Based on th9x -> http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef eeprom_arm_h +#define eeprom_arm_h + +#include +#include + + +extern void init_eeprom( void ) ; + +extern uint32_t ee32_check_finished( void ) ; +extern void ee32StoreGeneral( void ) ; +extern void ee32StoreModel( uint8_t modelNumber, uint8_t trim ) ; +extern bool ee32LoadGeneral( void ) ; +extern void ee32LoadModel(uint8_t id) ; +extern void ee32WaitLoadModel(uint8_t id) ; +extern void ee32_delete_model( uint8_t id ) ; +extern bool ee32ModelExists(uint8_t id) ; +extern uint32_t ee32_process( void ) ; + +#define DISPLAY_PROGRESS_BAR(x) + +struct t_file_entry +{ + uint32_t block_no ; + uint32_t sequence_no ; + uint16_t size ; + uint8_t flags ; +} ; + +extern struct t_file_entry File_system[] ; +extern unsigned char ModelNames[][sizeof(g_model.name)] ; // Allow for general + +extern EEGeneral g_eeGeneral; +extern ModelData g_model; + +extern uint8_t Spi_tx_buf[] ; +extern uint8_t Spi_rx_buf[] ; + +/// fileId of general file +//#define FILE_GENERAL 0 +/// convert model number 0..MAX_MODELS-1 int fileId +//#define FILE_MODEL(n) (1+n) +//#define FILE_TMP (1+16) + +//bool EeFsOpen(); +//int8_t EeFsck(); +//void EeFsFormat(); +//uint16_t EeFsGetFree(); +//#define ERR_NONE 0 +//#define ERR_FULL 1 +//#define ERR_TMO 2 +//class EFile +//{ +// uint8_t m_fileId; //index of file in directory = filename +// uint16_t m_pos; //over all filepos +// uint8_t m_currBlk; //current block.id +// uint8_t m_ofs; //offset inside of the current block +// uint8_t m_bRlc; //control byte for run length decoder +// uint8_t m_err; //error reasons +// uint16_t m_stopTime10ms; //maximum point of time for writing +//public: + ///remove contents of given file +// static void rm(uint8_t i_fileId); + + ///swap contents of file1 with them of file2 +// static void swap(uint8_t i_fileId1,uint8_t i_fileId2); + + ///return true if the file with given fileid exists +// static bool exists(uint8_t i_fileId); + + ///open file for reading, no close necessary + ///for writing use writeRlc() or create() +// uint8_t openRd(uint8_t i_fileId); + /// create a new file with given fileId, + /// !!! if this file already exists, then all blocks are reused + /// and all contents will be overwritten. + /// after writing closeTrunc has to be called +// void create(uint8_t i_fileId, uint8_t typ, uint16_t maxTme10ms); + /// close file and truncate the blockchain if to long. +// void closeTrunc(); + + ///open file, write to file and close it. + ///If file existed before, then contents is overwritten. + ///If file was larger before, then unused blocks are freed +// uint16_t writeRlc(uint8_t i_fileId, uint8_t typ,uint8_t*buf,uint16_t i_len, uint8_t maxTme10ms); + +// uint8_t read(uint8_t*buf,uint16_t i_len); +// uint8_t write(uint8_t*buf,uint8_t i_len); + + ///return size of compressed file without block overhead +// uint16_t size(); + ///read from opened file and decode rlc-coded data +// uint16_t readRlc(uint8_t*buf,uint16_t i_len); + ///deliver current errno, this is reset in open +// uint8_t errno(){return m_err;} +//}; + +#endif +/*eof*/ diff --git a/src/file.cpp b/src/eeprom_avr.cpp similarity index 78% rename from src/file.cpp rename to src/eeprom_avr.cpp index d19cec614..b4dca2edd 100644 --- a/src/file.cpp +++ b/src/eeprom_avr.cpp @@ -38,6 +38,9 @@ uint8_t s_write_err = 0; // error reasons uint8_t s_sync_write = false; +uint8_t s_eeDirtyMsk; + +RlcFile theFile; //used for any file operation #define EEFS_VERS 4 PACK(struct DirEnt{ @@ -54,6 +57,70 @@ PACK(struct EeFs{ DirEnt files[MAXFILES]; }) eeFs; +void eeDirty(uint8_t msk) +{ + s_eeDirtyMsk |= msk; +} + +uint16_t eeprom_pointer; +const char* eeprom_buffer_data; +volatile int8_t eeprom_buffer_size = 0; + +#if !defined(SIMU) + +inline void eeprom_write_byte() +{ + EEAR = eeprom_pointer; + EEDR = *eeprom_buffer_data; +#if defined (PCBV4) + EECR |= 1< 0) { + eeprom_write_byte(); + } + else { +#if defined (PCBV4) + EECR &= ~(1< 0) wdt_reset(); + } +} static uint8_t EeFsRead(uint8_t blk, uint8_t ofs) { @@ -596,3 +663,117 @@ void RlcFile::DisplayProgressBar(uint8_t x) } } #endif + +bool eeLoadGeneral() +{ + theFile.openRlc(FILE_GENERAL); + if (theFile.readRlc((uint8_t*)&g_eeGeneral, 1) == 1 && g_eeGeneral.myVers == EEPROM_VER) { + theFile.openRlc(FILE_GENERAL); // TODO include this openRlc inside readRlc + if (theFile.readRlc((uint8_t*)&g_eeGeneral, sizeof(g_eeGeneral)) <= sizeof(EEGeneral)) { + uint16_t sum = evalChkSum(); + if (g_eeGeneral.chkSum == sum) { + return true; + } + } + } + return false; +} + + +uint16_t eeLoadModelName(uint8_t id, char *name) +{ + memset(name, 0, sizeof(g_model.name)); + if (id 0 && sz != sizeof(g_model)) { + printf("Model data read=%d bytes vs %d bytes\n", sz, (int)sizeof(ModelData)); + } +#endif + + if (sz == 0) { + // alert("Error Loading Model"); + modelDefault(id); + eeCheck(true); + } + + resetProto(); + resetAll(); + +#ifdef LOGS + initLogs(); +#endif + } +} + +int8_t eeFindEmptyModel(uint8_t id, bool down) +{ + int8_t i = id; + for (;;) { + i = (MAX_MODELS + (down ? i+1 : i-1)) % MAX_MODELS; + if (!EFile::exists(FILE_MODEL(i))) break; + if (i == id) return -1; // no free space in directory left + } + return i; +} + +void eeReadAll() +{ + if(!EeFsOpen() || + EeFsck() < 0 || + !eeLoadGeneral()) + { + alert(STR_BADEEPROMDATA, true); + message(STR_EEPROMFORMATTING); + EeFsFormat(); + //alert(PSTR("format ok")); + generalDefault(); + //alert(PSTR("default ok")); + + theFile.writeRlc(FILE_GENERAL, FILE_TYP_GENERAL,(uint8_t*)&g_eeGeneral,sizeof(EEGeneral), true); + + modelDefault(0); + //alert(PSTR("modef ok")); + theFile.writeRlc(FILE_MODEL(0), FILE_TYP_MODEL, (uint8_t*)&g_model, sizeof(g_model), true); + //alert(PSTR("modwrite ok")); + } + + stickMode = g_eeGeneral.stickMode; + eeLoadModel(g_eeGeneral.currModel); +} + +void eeCheck(bool immediately) +{ + if (immediately) { + eeFlush(); + } + if (s_eeDirtyMsk & EE_GENERAL) { + s_eeDirtyMsk -= EE_GENERAL; + theFile.writeRlc(FILE_GENERAL, FILE_TYP_GENERAL, (uint8_t*)&g_eeGeneral, sizeof(EEGeneral), immediately); + if (!immediately) return; + } + if (s_eeDirtyMsk & EE_MODEL) { + s_eeDirtyMsk = 0; + theFile.writeRlc(FILE_MODEL(g_eeGeneral.currModel), FILE_TYP_MODEL, (uint8_t*)&g_model, sizeof(g_model), immediately); + } +} + diff --git a/src/file.h b/src/eeprom_avr.h similarity index 97% rename from src/file.h rename to src/eeprom_avr.h index b61852059..d83c82725 100644 --- a/src/file.h +++ b/src/eeprom_avr.h @@ -167,6 +167,10 @@ public: #endif }; +extern RlcFile theFile; //used for any file operation + +inline void eeFlush() { theFile.flush(); } + #if defined (EEPROM_PROGRESS_BAR) #define DISPLAY_PROGRESS_BAR(x) theFile.DisplayProgressBar(x) #else diff --git a/src/AT91SAM3S2.h b/src/ersky9x/AT91SAM3S2.h similarity index 100% rename from src/AT91SAM3S2.h rename to src/ersky9x/AT91SAM3S2.h diff --git a/src/AT91SAM3S4.h b/src/ersky9x/AT91SAM3S4.h similarity index 100% rename from src/AT91SAM3S4.h rename to src/ersky9x/AT91SAM3S4.h diff --git a/src/ersky9x/board.h b/src/ersky9x/board.h new file mode 100644 index 000000000..deadd628a --- /dev/null +++ b/src/ersky9x/board.h @@ -0,0 +1,667 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2009, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/** + * \page sam3s_ek_board_desc "SAM3S-EK - Board Description" + * + * \section + * A file is dedicated to descibe the AT91SAM3S-EK board. + * + * \section Contents + * - The code for booting the board is provided by board_cstartup.S and + * board_lowlevel.c. + * - For using board PIOs, board characteristics (clock, etc.) and external + * components, see board.h. + * - For manipulating memories (remapping, SDRAM, etc.), see board_memories.h. + * + * To get more software details and the full list of parameters related to the + * SAM3S-EK board configuration, please have a look at the source file: \n + * \ref board.h\n + * + * This file can be used as a template and modified to fit a custom board, with + * specific PIOs usage or memory connections. + **/ +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +/// \file board.h +/// +/// \par Purpose +/// +/// Definition of AT91SAM3S-EK characteristics, AT91SAM3S-dependant PIOs and +/// external components interfacing. +/// +/// \par Usage +/// -# For operating frequency information, see "SAM3S-EK - Operating frequencies". +/// -# For using portable PIO definitions, see "SAM3S-EK - PIO definitions". +/// -# Several USB definitions are included here (see "SAM3S-EK - USB device"). +//------------------------------------------------------------------------------ + +#ifndef BOARD_H +#define BOARD_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +/* These headers were introduced in C99 by working group ISO/IEC JTC1/SC22/WG14. */ +#include +#include + +#if defined(at91sam3s4) + #include "chip.h" + #include "AT91SAM3S4.h" +#else + #error Board does not support the specified chip. +#endif + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \par +/// This page lists several definition related to the board description. +/// +/// Definitions +/// - BOARD_NAME + +/// Name of the board. +#define BOARD_NAME "AT91SAM3S-EK" +/// Board definition. +#define at91sam3sek +/// Family definition (already defined). +#define at91sam3s +/// Core definition +#define cortexm3 + +//#define BOARD_REV_A +#define BOARD_REV_B + +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \par sam3s_ek_opfreq "SAM3S-EK - Operating frequencies" +/// This page lists several definition related to the board operating frequency +/// (when using the initialization done by board_lowlevel.c). +/// +/// !Definitions +/// - BOARD_MAINOSC +/// - BOARD_MCK + +/// Frequency of the board main oscillator. +#define BOARD_MAINOSC 12000000 + +/// Master clock frequency (when using board_lowlevel.c). +//#define BOARD_MCK 48000000 +#define BOARD_MCK 64000000 + +//------------------------------------------------------------------------------ +// ADC +//------------------------------------------------------------------------------ + +/// Startup time max, return from Idle mode (in µs) +#define ADC_STARTUP_TIME_MAX 15 +/// Track and hold Acquisition Time min (in ns) +#define ADC_TRACK_HOLD_TIME_MIN 1200 + +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// USB attributes configuration descriptor (bus or self powered, remote wakeup) +//#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_RWAKEUP +#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \par sam3s_ek_piodef "SAM3S-EK - PIO definitions" +/// This pages lists all the pio definitions contained in board.h. The constants +/// are named using the following convention: PIN_* for a constant which defines +/// a single Pin instance (but may include several PIOs sharing the same +/// controller), and PINS_* for a list of Pin instances. +/// +/// !ADC +/// - PIN_ADC0_AD0 +/// - PIN_ADC0_AD1 +/// - PIN_ADC0_AD2 +/// - PIN_ADC0_AD3 +/// - PIN_ADC0_AD4 +/// - PIN_ADC0_AD5 +/// - PIN_ADC0_AD6 +/// - PIN_ADC0_AD7 +/// - PINS_ADC0 +/// +/// !UART +/// - PINS_UART +/// +/// !EBI +/// - PIN_EBI_DATA_BUS +/// - PIN_EBI_NCS0 +/// - PIN_EBI_NRD +/// - PIN_EBI_NWE +/// - PIN_EBI_ADDR_BUS +/// - PIN_EBI_PSRAM_NBS +/// - PIN_EBI_A1 +/// - PIN_EBI_LCD_RS +/// +/// !LEDs +/// - PIN_LED_0 +/// - PIN_LED_1 +/// - PIN_LED_2 +/// - PINS_LEDS +/// +/// !MCI +/// - PINS_MCI +/// +/// !Push buttons +/// - PIN_PUSHBUTTON_1 +/// - PIN_PUSHBUTTON_2 +/// - PINS_PUSHBUTTONS +/// - PUSHBUTTON_BP1 +/// - PUSHBUTTON_BP2 +/// +/// !PWMC +/// - PIN_PWMC_PWMH0 +/// - PIN_PWMC_PWML0 +/// - PIN_PWMC_PWMH1 +/// - PIN_PWMC_PWML1 +/// - PIN_PWMC_PWMH2 +/// - PIN_PWMC_PWML2 +/// - PIN_PWMC_PWMH3 +/// - PIN_PWMC_PWML3 +/// - PIN_PWM_LED0 +/// - PIN_PWM_LED1 +/// - PIN_PWM_LED2 +/// - CHANNEL_PWM_LED0 +/// - CHANNEL_PWM_LED1 +/// - CHANNEL_PWM_LED2 +/// +/// !SPI +/// - PIN_SPI_MISO +/// - PIN_SPI_MOSI +/// - PIN_SPI_SPCK +/// - PINS_SPI +/// - PIN_SPI_NPCS0_PA11 +/// +/// ! SSC +/// - PIN_SSC_TD +/// - PIN_SSC_TK +/// - PIN_SSC_TF +/// - PINS_SSC_CODEC +/// +/// ! PCK0 +/// - PIN_PCK0 +/// +/// !TWI +/// - PIN_TWI_TWD0 +/// - PIN_TWI_TWCK0 +/// - PINS_TWI +/// +/// !USART0 +/// - PIN_USART0_RXD +/// - PIN_USART0_TXD +/// - PIN_USART0_CTS +/// - PIN_USART0_RTS +/// - PIN_USART0_SCK +/// +/// !USB +/// - PIN_USB_PULLUP +/// + +/// ADC_AD0 pin definition. +#define PIN_ADC0_AD0 {1 << 21, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT} +/// ADC_AD1 pin definition. +#define PIN_ADC0_AD1 {1 << 30, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT} +/// ADC_AD2 pin definition. +#define PIN_ADC0_AD2 {1 << 3, PIOB, ID_PIOB, PIO_INPUT, PIO_DEFAULT} +/// ADC_AD3 pin definition. +#define PIN_ADC0_AD3 {1 << 4, PIOB, ID_PIOB, PIO_INPUT, PIO_DEFAULT} +/// ADC_AD4 pin definition. +#define PIN_ADC0_AD4 {1 << 15, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} +/// ADC_AD5 pin definition. +#define PIN_ADC0_AD5 {1 << 16, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} +/// ADC_AD6 pin definition. +#define PIN_ADC0_AD6 {1 << 17, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} +/// ADC_AD7 pin definition. +#define PIN_ADC0_AD7 {1 << 18, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} + +/// Pins ADC +#define PINS_ADC PIN_ADC0_AD0, PIN_ADC0_AD1, PIN_ADC0_AD2, PIN_ADC0_AD3, PIN_ADC0_AD4, PIN_ADC0_AD5, PIN_ADC0_AD6, PIN_ADC0_AD7 + +/** UART pins (UTXD0 and URXD0) definitions, PA9,10. */ +#define PINS_UART {0x00000600, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} + +/// EBI +#define PIN_EBI_DATA_BUS {0xFF, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_NRD {1 << 11, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_NWE {1 << 8, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} + +#define PIN_EBI_NCS0 {1 << 20, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_PSRAM_ADDR_BUS {0x3f00fff, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_PSRAM_NBS {1 << 7, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_PULLUP}, \ + {1 << 15, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_A1 {1 << 19, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} + +#define PIN_EBI_NCS1 {1 << 15, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} /* LCD CS pin */ +#define PIN_EBI_LCD_RS {1 << 19, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} /* LCD RS pin */ + +#ifdef BOARD_REV_A +/** LED #0 pin definition. */ +#define PIN_LED_0 {1 << 20, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +/** LED #1 pin definition. */ +#define PIN_LED_1 {1 << 21, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +/** LED #2 pin definition. */ +#define PIN_LED_2 {1 << 22, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +#endif +#ifdef BOARD_REV_B +/** LED #0 pin definition. */ +#define PIN_LED_0 {1 << 19, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} +/** LED #1 pin definition. */ +#define PIN_LED_1 {1 << 20, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} +/** LED #2 pin definition. */ +#define PIN_LED_2 {1 << 20, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +#endif + +/** List of all LEDs definitions. */ +#define PINS_LEDS PIN_LED_0, PIN_LED_1, PIN_LED_2 + +/// MCI pins definition. +#define PINS_MCI {0x1f8, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_PULLUP}, \ + {1 << 3, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} + +/// MCI pin Card Detect +#define PIN_MCI_CD \ + {AT91C_PIO_PA25, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP} + +/** Push button #0 definition. Attributes = pull-up + debounce + interrupt on rising edge. */ +#define PIN_PUSHBUTTON_1 {1 << 3, PIOB, ID_PIOB, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE} +/** Push button #1 definition. Attributes = pull-up + debounce + interrupt on falling edge. */ +#define PIN_PUSHBUTTON_2 {1 << 12, PIOC, ID_PIOC, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE} +/** List of all push button definitions. */ +#define PINS_PUSHBUTTONS PIN_PUSHBUTTON_1, PIN_PUSHBUTTON_2 + +/** Push button #1 index. */ +#define PUSHBUTTON_BP1 0 +/** Push button #2 index. */ +#define PUSHBUTTON_BP2 1 + +/// Simulated joystick LEFT index. +#define JOYSTICK_LEFT 0 +/// Simulated joystick RIGHT index. +#define JOYSTICK_RIGHT 1 + +/** PWMC PWM0 pin definition. */ +#define PIN_PWMC_PWMH0 {1 << 18, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} +#define PIN_PWMC_PWML0 {1 << 19, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} +/** PWMC PWM1 pin definition. */ +#define PIN_PWMC_PWMH1 {1 << 19, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} +#define PIN_PWMC_PWML1 {1 << 20, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} +/** PWMC PWM2 pin definition. */ +#define PIN_PWMC_PWMH2 {1 << 20, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} +#define PIN_PWMC_PWML2 {1 << 16, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT} +/** PWMC PWM3 pin definition. */ +#define PIN_PWMC_PWMH3 {1 << 21, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} +#define PIN_PWMC_PWML3 {1 << 15, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT} +/** PWM pin definition for LED0 */ +#define PIN_PWM_LED0 PIN_PWMC_PWMH0, PIN_PWMC_PWML0 +/** PWM pin definition for LED1 */ +#define PIN_PWM_LED1 PIN_PWMC_PWMH2, PIN_PWMC_PWML2 +/** PWM pin definition for LED2 */ +#define PIN_PWM_LED2 PIN_PWMC_PWMH3, PIN_PWMC_PWML3 +/** PWM channel for LED0 */ +#define CHANNEL_PWM_LED0 0 +/** PWM channel for LED1 */ +#define CHANNEL_PWM_LED1 2 +/** PWM channel for LED2 */ +#define CHANNEL_PWM_LED2 3 + +/** SPI MISO pin definition. */ +#define PIN_SPI_MISO {1 << 12, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** SPI MOSI pin definition. */ +#define PIN_SPI_MOSI {1 << 13, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** SPI SPCK pin definition. */ +#define PIN_SPI_SPCK {1 << 14, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** SPI chip select pin definition. */ +#define PIN_SPI_NPCS0_PA11 {1 << 11, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** List of SPI pin definitions (MISO, MOSI & SPCK). */ +#define PINS_SPI PIN_SPI_MISO, PIN_SPI_MOSI, PIN_SPI_SPCK + +/// SSC pins definition. +#define PIN_SSC_TD {0x1 << 26, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_SSC_TK {0x1 << 28, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_SSC_TF {0x1 << 30, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PINS_SSC_CODEC PIN_SSC_TD, PIN_SSC_TK, PIN_SSC_TF + +/// PCK0 +#define PIN_PCK0 {0x1 << 21, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} + +/// TWI pins definition. +#define TWI_V3XX +#define PIN_TWI_TWD0 {0x1 << 9, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_TWI_TWCK0 {0x1 << 10, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PINS_TWI0 PIN_TWI_TWD0, PIN_TWI_TWCK0 +#define PIN_TWI_TWD1 {0x1 << 24, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_TWI_TWCK1 {0x1 << 25, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PINS_TWI1 PIN_TWI_TWD1, PIN_TWI_TWCK1 + +/// USART0 +#define PIN_USART0_RXD {0x1 << 19, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART0_TXD {0x1 << 18, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART0_CTS {0x1 << 8, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART0_RTS {0x1 << 7, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART0_SCK {0x1 << 17, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} + +/// USART1 +#define PIN_USART1_RXD {0x1 << 21, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART1_TXD {0x1 << 22, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART1_CTS {0x1 << 25, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART1_RTS {0x1 << 24, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART1_EN {0x1 << 23, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT} + + + +/// USB VBus monitoring pin definition. +#ifdef BOARD_REV_A +#define PIN_USB_VBUS {1 << 23, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} +#endif +#ifdef BOARD_REV_B +#define PIN_USB_VBUS {1 << 21, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} +#endif + +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \par sam3s_ek_extcomp "SAM3S-EK - External components" +/// This page lists the definitions related to external on-board components +/// located in the board.h file for the AT91SAM3S-EK. +/// +/// !AT45 Dataflash Card +/// - BOARD_AT45_A_SPI_BASE +/// - BOARD_AT45_A_SPI_ID +/// - BOARD_AT45_A_SPI_PINS +/// - BOARD_AT45_A_SPI +/// - BOARD_AT45_A_NPCS +/// - BOARD_AT45_A_NPCS_PIN +/// +/// !AT45 Dataflash (serial onboard DataFlash) +/// - BOARD_AT45_B_SPI_BASE +/// - BOARD_AT45_B_SPI_ID +/// - BOARD_AT45_B_SPI_PINS +/// - BOARD_AT45_B_SPI +/// - BOARD_AT45_B_NPCS +/// - BOARD_AT45_B_NPCS_PIN +/// +/// !AT26 Serial Flash +/// - BOARD_AT26_A_SPI_BASE +/// - BOARD_AT26_A_SPI_ID +/// - BOARD_AT26_A_SPI_PINS +/// - BOARD_AT26_A_SPI +/// - BOARD_AT26_A_NPCS +/// - BOARD_AT26_A_NPCS_PIN +/// +/// !SD Card +/// - MCI2_INTERFACE +/// - BOARD_SD_MCI_BASE +/// - BOARD_SD_MCI_ID +/// - BOARD_SD_PINS +/// - BOARD_SD_SLOT +/// +/// !PSRAM +/// - BOARD_PSRAM_PINS +/// +/// !LCD +/// - BOARD_LCD_ILI9325 +/// - BOARD_LCD_PINS +/// - BOARD_BACKLIGHT_PIN +/// - BOARD_LCD_BASE +/// - BOARD_LCD_RS +/// - BOARD_LCD_WIDTH +/// - BOARD_LCD_HEIGHT +/// +/// !TouchScreen +/// - BOARD_TSC_ADS7843 +/// - PIN_TCS_IRQ +/// - PIN_TCS_BUSY +/// - BOARD_TSC_SPI_BASE +/// - BOARD_TSC_SPI_ID +/// - BOARD_TSC_SPI_PINS +/// - BOARD_TSC_NPCS +/// - BOARD_TSC_NPCS_PIN +/// +/// Base address of SPI peripheral connected to the dataflash. +//#define BOARD_AT45_A_SPI_BASE SPI0 +///// Identifier of SPI peripheral connected to the dataflash. +//#define BOARD_AT45_A_SPI_ID ID_SPI0 +///// Pins of the SPI peripheral connected to the dataflash. +//#define BOARD_AT45_A_SPI_PINS PINS_SPI0 +///// Dataflahs SPI number. +//#define BOARD_AT45_A_SPI 0 +///// Chip select connected to the dataflash. +//#define BOARD_AT45_A_NPCS 3 +///// Chip select pin connected to the dataflash. +//#define BOARD_AT45_A_NPCS_PIN PIN_SPI0_NPCS3 + +/// Base address of SPI peripheral connected to the dataflash. +//#define BOARD_AT45_B_SPI_BASE SPI1 +///// Identifier of SPI peripheral connected to the dataflash. +//#define BOARD_AT45_B_SPI_ID ID_SPI1 +///// Pins of the SPI peripheral connected to the dataflash. +//#define BOARD_AT45_B_SPI_PINS PINS_SPI1 +///// Dataflahs SPI number. +//#define BOARD_AT45_B_SPI 1 +///// Chip select connected to the dataflash. +//#define BOARD_AT45_B_NPCS 3 +///// Chip select pin connected to the dataflash. +//#define BOARD_AT45_B_NPCS_PIN PIN_SPI1_NPCS3 + +/// Base address of SPI peripheral connected to the serialflash. +//#define BOARD_AT26_A_SPI_BASE SPI0 +///// Identifier of SPI peripheral connected to the serialflash. +//#define BOARD_AT26_A_SPI_ID ID_SPI0 +///// Pins of the SPI peripheral connected to the serialflash. +//#define BOARD_AT26_A_SPI_PINS PINS_SPI0 +///// Serialflash SPI number. +//#define BOARD_AT26_A_SPI 0 +///// Chip select connected to the serialflash. +//#define BOARD_AT26_A_NPCS 3 +///// Chip select pin connected to the serialflash. +//#define BOARD_AT26_A_NPCS_PIN PIN_SPI0_NPCS3 + +/// ISO7816 +/// - PIN_SMARTCARD_CONNECT +/// - PIN_ISO7816_RSTMC +/// - PINS_ISO7816 + +/// Smartcard detection pin +//#define PIN_SMARTCARD_CONNECT {1 << 5, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT} +/// PIN used for reset the smartcard +//#define PIN_ISO7816_RSTMC {1 << 7, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT} +/// Pins used for connect the smartcard +//#define PINS_ISO7816 PIN_USART0_TXD, PIN_USART0_SCK, PIN_ISO7816_RSTMC + +/// Dma channel number +#define BOARD_MCI_DMA_CHANNEL 0 +/// MCI0 DMA hardware handshaking ID +#define DMA_HW_SRC_REQ_ID_MCI0 AT91C_HDMA_SRC_PER_0 +#define DMA_HW_DEST_REQ_ID_MCI0 AT91C_HDMA_DST_PER_0 +/// MCI1 DMA hardware handshaking ID +#define DMA_HW_SRC_REQ_ID_MCI1 AT91C_HDMA_SRC_PER_13 +#define DMA_HW_DEST_REQ_ID_MCI1 AT91C_HDMA_DST_PER_13 +/// SD DMA hardware handshaking ID +#define BOARD_SD_DMA_HW_SRC_REQ_ID DMA_HW_SRC_REQ_ID_MCI0 +#define BOARD_SD_DMA_HW_DEST_REQ_ID DMA_HW_DEST_REQ_ID_MCI0 + + +/// HS MCI interface +#define MCI2_INTERFACE +/// Base address of the MCI peripheral connected to the SD card. +#define BOARD_SD_MCI_BASE MCI0//MCI +///// Peripheral identifier of the MCI connected to the SD card. +#define BOARD_SD_MCI_ID ID_MCI0 //ID_MCI +///// MCI pins that shall be configured to access the SD card. +#define BOARD_SD_PINS PINS_MCI +///// MCI slot to which the SD card is connected to. +#define BOARD_SD_SLOT MCI_SD_SLOTA +///// MCI Card Detect pin. +#define BOARD_SD_PIN_CD PIN_MCI_CD + +/* +#define BOARD_PSRAM_PINS PIN_EBI_DATA_BUS, PIN_EBI_NCS0, PIN_EBI_NRD, PIN_EBI_NWE, \ + PIN_EBI_PSRAM_ADDR_BUS, PIN_EBI_PSRAM_NBS, PIN_EBI_A1 +*/ + +/** Indicates board has an ILI9325 external component to manage LCD. */ +#define BOARD_LCD_ILI9325 + +/** LCD pins definition. */ +#define BOARD_LCD_PINS PIN_EBI_DATA_BUS, PIN_EBI_NRD, PIN_EBI_NWE, \ + PIN_EBI_NCS1, PIN_EBI_LCD_RS +/** Backlight pin definition. */ +#define BOARD_BACKLIGHT_PIN {1 << 13, PIOC, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT} +/** Define ILI9325 base address. */ +#define BOARD_LCD_BASE 0x61000000 +/** Define ILI9325 register select signal. */ +#define BOARD_LCD_RS (1 << 1) +/** Display width in pixels. */ +#define BOARD_LCD_WIDTH 240 +/** Display height in pixels. */ +#define BOARD_LCD_HEIGHT 320 + +/** Indicates board has an ADS7843 external component to manage Touch Screen */ +#define BOARD_TSC_ADS7843 + +#ifdef BOARD_REV_A +/** Touchscreen controller IRQ pin definition. */ +#define PIN_TCS_IRQ {PIO_PA4, PIOA, ID_PIOA, PIO_INPUT, PIO_DEBOUNCE | PIO_IT_AIME | PIO_IT_EDGE} +#define PIN_TCS_IRQ_WUP_ID (1 << 3) +/** Touchscreen controller Busy pin definition. */ +#define PIN_TCS_BUSY {PIO_PA5, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP} +#endif +#ifdef BOARD_REV_B +/** Touchscreen controller IRQ pin definition. */ +#define PIN_TCS_IRQ {PIO_PA16, PIOA, ID_PIOA, PIO_INPUT, PIO_DEBOUNCE | PIO_IT_AIME | PIO_IT_EDGE} +#define PIN_TCS_IRQ_WUP_ID (1 << 15) +/** Touchscreen controller Busy pin definition. */ +#define PIN_TCS_BUSY {PIO_PA17, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP} +#endif + +/** Base address of SPI peripheral connected to the touchscreen controller. */ +#define BOARD_TSC_SPI_BASE SPI +/** Identifier of SPI peripheral connected to the touchscreen controller. */ +#define BOARD_TSC_SPI_ID ID_SPI +/** Pins of the SPI peripheral connected to the touchscreen controller. */ +#define BOARD_TSC_SPI_PINS PINS_SPI +/** Chip select connected to the touchscreen controller. */ +#define BOARD_TSC_NPCS 0 +/** Chip select pin connected to the touchscreen controller. */ +#define BOARD_TSC_NPCS_PIN PIN_SPI_NPCS0_PA11 + +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \par sam3s_ek_mem "SAM3S-EK - Memories" +/// This page lists definitions related to internal & external on-board memories. +/// +/// !Embedded Flash +/// - BOARD_FLASH_EFC + +/// Internal SRAM address +#define AT91C_ISRAM AT91C_IRAM +#define AT91C_ISRAM_SIZE 0x00008000 + +#define AT91C_IFLASH_SIZE (0x40000) +#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH 0 Page Size: 256 bytes +#define AT91C_IFLASH_NB_OF_PAGES (1024) // Internal FLASH 0 Number of Pages: 512 +#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH 0 Lock Region Size: 16 Kbytes +#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH 0 Number of Lock Bits: 16 + +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +/// \section sam3s_ek_extcomp "SAM3S-EK - External components" +/// This page lists the definitions related to external on-board components +/// located in the board.h file for the SAM3S-EK. +/// +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \par sam3s_ek_chipdef "SAM3S-EK - Individual chip definition" +/// This page lists the definitions related to different chip's definition +/// located in the board.h file for the SAM3S-EK. + +/// DBGU +#define BOARD_DBGU_ID ID_DBGU + +/// Rtc +#define BOARD_RTC_ID ID_RTC + +/// Twi eeprom +#define BOARD_ID_TWI_EEPROM ID_TWI1 +#define BOARD_BASE_TWI_EEPROM TWI1 +#define BOARD_PINS_TWI_EEPROM PINS_TWI1 + +/// USART +#define BOARD_PIN_USART_RXD PIN_USART1_RXD +#define BOARD_PIN_USART_TXD PIN_USART1_TXD +#define BOARD_PIN_USART_CTS PIN_USART1_CTS +#define BOARD_PIN_USART_RTS PIN_USART1_RTS +#define BOARD_PIN_USART_EN PIN_USART1_EN +#define BOARD_USART_BASE USART1 +#define BOARD_ID_USART ID_USART1 + +//------------------------------------------------------------------------------ + + +#define PIN_EBI_NANDOE {1 << 9, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_NANDWE {1 << 10, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_NANDCLE {1 << 17, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_NANDALE {1 << 16, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_NANDIO {0x000000FF, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} + +/// Nandflash chip enable pin definition. +#define BOARD_NF_CE_PIN {1 << 14, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +/// Nandflash ready/busy pin definition. +#define BOARD_NF_RB_PIN {1 << 18, PIOC, ID_PIOC, PIO_INPUT, PIO_PULLUP} + +/// Nandflash controller peripheral pins definition. +#define PINS_NANDFLASH PIN_EBI_NANDIO, BOARD_NF_CE_PIN, BOARD_NF_RB_PIN, PIN_EBI_NANDOE, \ + PIN_EBI_NANDWE, PIN_EBI_NANDCLE, PIN_EBI_NANDALE + +/// Address for transferring command bytes to the nandflash. +#define BOARD_NF_COMMAND_ADDR 0x60400000 +/// Address for transferring address bytes to the nandflash. +#define BOARD_NF_ADDRESS_ADDR 0x60200000 +/// Address for transferring data bytes to the nandflash. +#define BOARD_NF_DATA_ADDR 0x60000000 + +#endif //#ifndef BOARD_H + diff --git a/src/ersky9x/board_lowlevel.c b/src/ersky9x/board_lowlevel.c new file mode 100644 index 000000000..a97fde941 --- /dev/null +++ b/src/ersky9x/board_lowlevel.c @@ -0,0 +1,229 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \par Purpose + * + * Provides the low-level initialization function that gets called on chip startup. + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +/*---------------------------------------------------------------------------- + * Local definitions + *----------------------------------------------------------------------------*/ +/** Define clock timeout */ +#define CLOCK_TIMEOUT 5000 +/** Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.*/ +#define PMC_PLLA_SET_BIT29 (0x1 << 29) +/** Specifies the number of Slow Clock cycles x8 before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.*/ +#define PMC_PLLA_COUNT (0xBF << 8) +/** The PLLA Clock frequency is the PLLA input frequency multiplied by 8*/ +#define PMC_PLLA_MULTIPIER (0x07 << 16) +/** PLLA Divider is bypassed.*/ +#define PMC_PLLA_DIV (0x01) + +void revert_osc( void ) ; + + +/*---------------------------------------------------------------------------- + * Local functions + * returns master_frequency + *----------------------------------------------------------------------------*/ + +// *** WARNING, this is called BEFORE .data and .bss have been initialised +// *** GLOBAL variables are NOT useable + +static uint32_t BOARD_ConfigurePmc(void) +{ +/* TODO: configurate PLL in new way */ +//#if 0 +// uint32_t timeout = 0; +// /** 1: Checking the Main Oscillator Frequency (Optional) and Initialize main oscillator */ +// /** 1.1 Initialize main oscillator */ +// // TODO: + +// /** 2. Setting PLL and Divider*/ +// /** 2.1 Initialize PLLA*/ +// PMC->CKGR_PLLAR = ( PMC_PLLA_SET_BIT29 | +// PMC_PLLA_MULTIPIER | +// PMC_PLLA_COUNT | +// PMC_PLLA_DIV +// ); +// timeout = 0; +// /** 2.2 Wait for the LOCKA bit to be set by polling the status register.*/ +// while (!(PMC->PMC_SR & PMC_SR_LOCKA) && (timeout++ < CLOCK_TIMEOUT)); +// /** 2.3 wait for the MCKRDY bit to be set by polling the status register*/ +// timeout = 0; +// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); + +// /** 3. Selection of Master Clock and Processor Clock*/ +// PMC->PMC_MCKR |= PMC_MCKR_PRES_CLK_2; + +// /** 3.1 wait for the MCKRDY bit to be set by polling the status register*/ +// timeout = 0; +// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); + +// /** 3.2 PLLA Clock is selected */ +// PMC->PMC_MCKR = PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK; + +// /** 3.3 wait for the MCKRDY bit to be set by polling the status register*/ +// timeout = 0; +// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); +//#endif + +#if 1 // old as sam3u +#define AT91C_CKGR_MUL_SHIFT 16 +//#define AT91C_CKGR_OUT_SHIFT 14 +#define AT91C_CKGR_PLLCOUNT_SHIFT 8 +#define AT91C_CKGR_DIV_SHIFT 0 + +// Settings at 72MHz/2 = 36MHz +#define BOARD_OSCOUNT (CKGR_MOR_MOSCXTST & (0x8 << 8)) +#define BOARD_PLLR ((1 << 29) | (0x5 << AT91C_CKGR_MUL_SHIFT) \ + | (0x1 << AT91C_CKGR_PLLCOUNT_SHIFT) | (0x2 << AT91C_CKGR_DIV_SHIFT)) +#define BOARD_MCKR (PMC_MCKR_CSS_PLLA_CLK) + +// Define clock timeout +#undef CLOCK_TIMEOUT +#define CLOCK_TIMEOUT 0xFFFFFFFF + + register uint32_t timeout = 0 ; + register Pmc *pmcptr ; + + pmcptr = PMC ; + + /* Enable NRST reset + ************************************/ + //AT91C_BASE_RSTC->RSTC_RMR |= AT91C_RSTC_URSTEN; + + /* Select external slow clock + ****************************/ + + +// if ((SUPC->SUPC_SR & SUPC_SR_OSCSEL) != SUPC_SR_OSCSEL_CRYST) { +// SUPC->SUPC_CR = SUPC_CR_XTALSEL_CRYSTAL_SEL | ((uint32_t)0xA5 << 24); +// timeout = 0; +// while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL_CRYST) ); +// } + + + /* Initialize main oscillator + ****************************/ + if(!(pmcptr->CKGR_MOR & CKGR_MOR_MOSCSEL)) + { + + pmcptr->CKGR_MOR = (0x37 << 16) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN; + timeout = 0; + while (!(pmcptr->PMC_SR & PMC_SR_MOSCXTS) && (++timeout < CLOCK_TIMEOUT)); + + } + + /* Switch to 3-20MHz Xtal oscillator */ + pmcptr->CKGR_MOR = (0x37 << 16) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL; + timeout = 0; + while (!(pmcptr->PMC_SR & PMC_SR_MOSCSELS) && (++timeout < CLOCK_TIMEOUT)); + + pmcptr->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS) | PMC_MCKR_CSS_MAIN_CLK; + timeout = 0; + while (!(pmcptr->PMC_SR & PMC_SR_MCKRDY) && (++timeout < CLOCK_TIMEOUT)); + + /* Initialize PLLA 72 MHz */ + pmcptr->CKGR_PLLAR = BOARD_PLLR; + timeout = 0; + while (!(pmcptr->PMC_SR & PMC_SR_LOCKA) && (++timeout < CLOCK_TIMEOUT)); + + + /* Initialize UTMI for USB usage, can be disabled if not using USB for the sake of saving power*/ + //AT91C_BASE_CKGR->CKGR_UCKR |= (AT91C_CKGR_UPLLCOUNT & (3 << 20)) | AT91C_CKGR_UPLLEN; + //timeout = 0; + //while (!(PMC->PMC_SR & AT91C_PMC_LOCKU) && (timeout++ < CLOCK_TIMEOUT)); + + /* Switch to fast clock + **********************/ +// PMC->PMC_MCKR = (BOARD_MCKR & ~PMC_MCKR_CSS) | PMC_MCKR_CSS_MAIN_CLK; +// timeout = 0; +// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); + + // Switch to PLLA as main clock 36MHz + PMC->PMC_MCKR = BOARD_MCKR; + timeout = 0; + while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); + +#endif + return 36000000L ; // Master_frequency +} + +void revert_osc() +{ + register uint32_t timeout = 0 ; + register Pmc *pmcptr ; + + pmcptr = PMC ; + + + // Switch back to the internal oscillator + pmcptr->CKGR_MOR = (0x37 << 16) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN ; + timeout = 0; + while (!(pmcptr->PMC_SR & PMC_SR_MOSCSELS) && (++timeout < CLOCK_TIMEOUT)); + + pmcptr->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS) | PMC_MCKR_CSS_SLOW_CLK; + timeout = 0; + while (!(pmcptr->PMC_SR & PMC_SR_MCKRDY) && (++timeout < CLOCK_TIMEOUT)); + + + pmcptr->CKGR_PLLAR = 1 << 29 ; // Stop PLLA + +} + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------*/ +/** + * \brief Performs the low-level initialization of the chip. This includes EFC, + * master clock and watchdog configuration. + */ +/*----------------------------------------------------------------------------*/ +uint32_t SystemInit (void) +{ + /** Set 2 cycle (1 WS) for Embedded Flash Access */ + // Max clock is 38 MHz (1.8V VVDCORE) + EFC->EEFC_FMR = (1 << 8) ; + + /** Configure PMC */ + return BOARD_ConfigurePmc(); +} diff --git a/src/ersky9x/chip.h b/src/ersky9x/chip.h new file mode 100644 index 000000000..d216db6d1 --- /dev/null +++ b/src/ersky9x/chip.h @@ -0,0 +1,130 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// !Purpose +/// +/// Definition of AT91SAM3S4 characteristics and features +/// +/// !Usage +/// -# For ARM core feature, see "AT91SAM3S4 - ARM core features". +/// -# For IP features, see "AT91SAM3S4 - IP features". +/// -# For misc, see "AT91SAM3S4 - Misc". +//------------------------------------------------------------------------------ + +#ifndef CHIP_H +#define CHIP_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "AT91SAM3S4 - ARM core features" +/// This page lists several characteristics related to the ARM core +/// + +//ARM core features + +/// ARM core definition. +#define cortexm3 + +/// family definition. +#define at91sam3s + +//------------------------------------------------------------------------------ +/// \page "AT91SAM3S4 - IP features" +/// This page lists several characteristics related to the embedded IP +/// + +//IP FEATURES + +// EFC GPNVM number +#define CHIP_EFC_NUM_GPNVMS 3 + +/// Indicates chip has an Enhanced EFC. +#define CHIP_FLASH_EEFC + +// DMA channels number +#define CHIP_DMA_CHANNEL_NUM 4 + +// Indicate chip's MCI interface. +#define MCI2_INTERFACE + +// Indicate chip SSC has DMA interface. +#define CHIP_SSC_DMA + +// Indicate chip SPI has DMA interface. +#define CHIP_SPI_DMA + +/// Indicates chip has an UDP Full Speed. +#define CHIP_USB_UDP + +/// Indicates chip has an internal pull-up. +#define CHIP_USB_PULLUP_INTERNAL + +/// Number of USB endpoints +#define CHIP_USB_NUMENDPOINTS 8 + +/// Endpoints max paxcket size +#define CHIP_USB_ENDPOINTS_MAXPACKETSIZE(i) \ + ((i == 0) ? 64 : \ + ((i == 1) ? 64 : \ + ((i == 2) ? 64 : \ + ((i == 3) ? 64 : \ + ((i == 4) ? 512 : \ + ((i == 5) ? 512 : \ + ((i == 6) ? 64 : \ + ((i == 7) ? 64 : 0 )))))))) + +/// Endpoints Number of Bank +#define CHIP_USB_ENDPOINTS_BANKS(i) \ + ((i == 0) ? 1 : \ + ((i == 1) ? 2 : \ + ((i == 2) ? 2 : \ + ((i == 3) ? 1 : \ + ((i == 4) ? 2 : \ + ((i == 5) ? 2 : \ + ((i == 6) ? 2 : \ + ((i == 7) ? 2 : 0 )))))))) + +//------------------------------------------------------------------------------ +/// \page "AT91SAM3S4 - Misc " +/// This page lists misc features +/// + +//Misc + +#endif //#ifndef CHIP_H + diff --git a/src/ersky9x/core_cm3.c b/src/ersky9x/core_cm3.c new file mode 100644 index 000000000..eac95e9b5 --- /dev/null +++ b/src/ersky9x/core_cm3.c @@ -0,0 +1,831 @@ +/**************************************************************************//** + * @file core_cm3.c + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File + * @version V1.30 + * @date 30. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + +uint32_t __get_PSP(void) ; +void __set_PSP(uint32_t topOfProcStack) ; +uint32_t __get_MSP(void) ; +void __set_MSP(uint32_t mainStackPointer) ; +uint32_t __REV16(uint16_t value) ; +int32_t __REVSH(int16_t value) ; +uint32_t __RBIT(uint32_t value) ; +uint8_t __LDREXB(uint8_t *addr) ; +uint16_t __LDREXH(uint16_t *addr) ; +uint32_t __LDREXW(uint32_t *addr) ; +uint32_t __STREXB(uint8_t value, uint8_t *addr) ; +uint32_t __STREXH(uint16_t value, uint16_t *addr) ; +uint32_t __STREXW(uint32_t value, uint32_t *addr) ; + +uint32_t __get_BASEPRI(void) ; +void __set_BASEPRI(uint32_t basePri) ; +uint32_t __get_PRIMASK(void) ; +void __set_PRIMASK(uint32_t priMask) ; +uint32_t __get_FAULTMASK(void) ; +void __set_FAULTMASK(uint32_t faultMask) ; +uint32_t __get_CONTROL(void) ; +void __set_CONTROL(uint32_t control) ; +uint32_t __REV(uint32_t value) ; + +void revert_osc( void ) ; +void sam_boot( void ) ; + + +/* ################### Compiler specific Intrinsics ########################### */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +__ASM uint32_t __get_PSP(void) +{ + mrs r0, psp + bx lr +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +__ASM void __set_PSP(uint32_t topOfProcStack) +{ + msr psp, r0 + bx lr +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +__ASM uint32_t __get_MSP(void) +{ + mrs r0, msp + bx lr +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +__ASM void __set_MSP(uint32_t mainStackPointer) +{ + msr msp, r0 + bx lr +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +__ASM uint32_t __REV16(uint16_t value) +{ + rev16 r0, r0 + bx lr +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +__ASM int32_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} + + +#if (__ARMCC_VERSION < 400000) + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +__ASM void __CLREX(void) +{ + clrex +} + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +__ASM uint32_t __get_BASEPRI(void) +{ + mrs r0, basepri + bx lr +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +__ASM void __set_BASEPRI(uint32_t basePri) +{ + msr basepri, r0 + bx lr +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +__ASM uint32_t __get_PRIMASK(void) +{ + mrs r0, primask + bx lr +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +__ASM void __set_PRIMASK(uint32_t priMask) +{ + msr primask, r0 + bx lr +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +__ASM uint32_t __get_FAULTMASK(void) +{ + mrs r0, faultmask + bx lr +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +__ASM void __set_FAULTMASK(uint32_t faultMask) +{ + msr faultmask, r0 + bx lr +} + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +__ASM uint32_t __get_CONTROL(void) +{ + mrs r0, control + bx lr +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +__ASM void __set_CONTROL(uint32_t control) +{ + msr control, r0 + bx lr +} + +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#pragma diag_suppress=Pe940 + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +uint32_t __get_PSP(void) +{ + __ASM("mrs r0, psp"); + __ASM("bx lr"); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM("msr psp, r0"); + __ASM("bx lr"); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +uint32_t __get_MSP(void) +{ + __ASM("mrs r0, msp"); + __ASM("bx lr"); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM("msr msp, r0"); + __ASM("bx lr"); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + __ASM("rev16 r0, r0"); + __ASM("bx lr"); +} + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +uint32_t __RBIT(uint32_t value) +{ + __ASM("rbit r0, r0"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit values) + */ +uint8_t __LDREXB(uint8_t *addr) +{ + __ASM("ldrexb r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +uint16_t __LDREXH(uint16_t *addr) +{ + __ASM("ldrexh r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +uint32_t __LDREXW(uint32_t *addr) +{ + __ASM("ldrex r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + __ASM("strexb r0, r0, [r1]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + __ASM("strexh r0, r0, [r1]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + __ASM("strex r0, r0, [r1]"); + __ASM("bx lr"); +} + +#pragma diag_default=Pe940 + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +/*extern uint32_t __get_PSP(void) __attribute__( ( naked ) ); */ +uint32_t __get_PSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, psp\n\t" + "MOV r0, %0 \n\t" + "BX lr \n\t" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +/*void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); */ +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n\t" + "BX lr \n\t" : : "r" (topOfProcStack) ); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +/*uint32_t __get_MSP(void) __attribute__( ( naked ) ); */ +uint32_t __get_MSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, msp\n\t" + "MOV r0, %0 \n\t" + "BX lr \n\t" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +/*void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); */ +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n\t" + "BX lr \n\t" : : "r" (topOfMainStack) ); +} + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +uint32_t __get_BASEPRI(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +uint32_t __get_PRIMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +uint32_t __get_FAULTMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +uint32_t __get_CONTROL(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + + +/** + * @brief Reverse byte order in integer value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +uint32_t __REV(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +int32_t __REVSH(int16_t value) +{ + uint32_t result=0; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +uint32_t __RBIT(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +uint8_t __LDREXB(uint8_t *addr) +{ + uint8_t result=0; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +uint16_t __LDREXH(uint16_t *addr) +{ + uint16_t result=0; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +uint32_t __LDREXW(uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +void sam_boot() +{ + revert_osc() ; + + __ASM(" mov.w r1, #8388608"); + __ASM(" movw r0, #60680"); + __ASM(" movt r0, #57344"); + __ASM(" str r1, [r0, #0]"); // Set the VTOR + + __ASM("mov.w r3, #0"); + __ASM("movt r3, #128"); + __ASM("ldr r0, [r3, #0]"); + __ASM("msr msp, r0"); + __ASM("ldr r0, [r3, #4]"); + __ASM("mov.w r3, #1"); + __ASM("orr r0, r3"); + __ASM("bx r0"); +} + + + +#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif diff --git a/src/ersky9x/core_cm3.h b/src/ersky9x/core_cm3.h new file mode 100644 index 000000000..1c07effab --- /dev/null +++ b/src/ersky9x/core_cm3.h @@ -0,0 +1,1818 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V1.30 + * @date 30. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CM3_CORE_H__ +#define __CM3_CORE_H__ + +/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration + * + * List of Lint messages which will be suppressed and not shown: + * - Error 10: \n + * register uint32_t __regBasePri __asm("basepri"); \n + * Error 10: Expecting ';' + * . + * - Error 530: \n + * return(__regBasePri); \n + * Warning 530: Symbol '__regBasePri' (line 264) not initialized + * . + * - Error 550: \n + * __regBasePri = (basePri & 0x1ff); \n + * Warning 550: Symbol '__regBasePri' (line 271) not accessed + * . + * - Error 754: \n + * uint32_t RESERVED0[24]; \n + * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced + * . + * - Error 750: \n + * #define __CM3_CORE_H__ \n + * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced + * . + * - Error 528: \n + * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n + * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced + * . + * - Error 751: \n + * } InterruptType_Type; \n + * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced + * . + * Note: To re-enable a Message, insert a space before 'lint' * + * + */ + +/*lint -save */ +/*lint -e10 */ +/*lint -e530 */ +/*lint -e550 */ +/*lint -e754 */ +/*lint -e750 */ +/*lint -e528 */ +/*lint -e751 */ + + +/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core registers and bitfields + - Cortex-M core peripheral base address + @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex core */ + +#include /* Include standard types */ + +#if defined (__ICCARM__) + #include /* IAR Intrinsics */ +#endif + + +#ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ +#endif + + + + +/** + * IO definitions + * + * define access restrictions to peripheral registers + */ + +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register + @{ +*/ + + +/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC + memory mapped structure for Nested Vectored Interrupt Controller (NVIC) + @{ + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ +} NVIC_Type; +/*@}*/ /* end of group CMSIS_CM3_NVIC */ + + +/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB + memory mapped structure for System Control Block (SCB) + @{ + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (0x1ul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +/*@}*/ /* end of group CMSIS_CM3_SCB */ + + +/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick + memory mapped structure for SysTick + @{ + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ +/*@}*/ /* end of group CMSIS_CM3_SysTick */ + + +/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM + memory mapped structure for Instrumentation Trace Macrocell (ITM) + @{ + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ + __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ + __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +/*@}*/ /* end of group CMSIS_CM3_ITM */ + + +/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type + memory mapped structure for Interrupt Type + @{ + */ +typedef struct +{ + uint32_t RESERVED0; + __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ +#else + uint32_t RESERVED1; +#endif +} InterruptType_Type; + +/* Interrupt Controller Type Register Definitions */ +#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ +#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ +#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ + +#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ +#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ + +#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ +#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ +/*@}*/ /* end of group CMSIS_CM3_InterruptType */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) +/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU + memory mapped structure for Memory Protection Unit (MPU) + @{ + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ +#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ +#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ +#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ +#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ +#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ +#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@}*/ /* end of group CMSIS_CM3_MPU */ +#endif + + +/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug + memory mapped structure for Core Debug Register + @{ + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ + + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ + +#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ +#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_register */ + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#define __enable_fault_irq __enable_fiq +#define __disable_fault_irq __disable_fiq + +#define __NOP __nop +#define __WFI __wfi +#define __WFE __wfe +#define __SEV __sev +#define __ISB() __isb(0) +#define __DSB() __dsb(0) +#define __DMB() __dmb(0) +#define __REV __rev +#define __RBIT __rbit +#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) +#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) +#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) +#define __STREXB(value, ptr) __strex(value, ptr) +#define __STREXH(value, ptr) __strex(value, ptr) +#define __STREXW(value, ptr) __strex(value, ptr) + + +/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ +/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +extern int32_t __REVSH(int16_t value); + + +#if (__ARMCC_VERSION < 400000) + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +extern void __CLREX(void); + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +extern uint32_t __get_BASEPRI(void); + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +extern void __set_BASEPRI(uint32_t basePri); + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +extern uint32_t __get_PRIMASK(void); + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +extern void __set_PRIMASK(uint32_t priMask); + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +extern uint32_t __get_FAULTMASK(void); + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +extern void __set_FAULTMASK(uint32_t faultMask); + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +extern uint32_t __get_CONTROL(void); + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +extern void __set_CONTROL(uint32_t control); + +#else /* (__ARMCC_VERSION >= 400000) */ + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +#define __CLREX __clrex + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +static __INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & 1); +} + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +static __INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ +#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ + +static __INLINE void __enable_fault_irq( void ) { __ASM ("cpsie f"); } +static __INLINE void __disable_fault_irq( void ) { __ASM ("cpsid f"); } + +#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ +static __INLINE void __WFI( void ) { __ASM ("wfi"); } +static __INLINE void __WFE( void ) { __ASM ("wfe"); } +static __INLINE void __SEV( void ) { __ASM ("sev"); } +static __INLINE void __CLREX( void ) { __ASM ("clrex"); } + +/* intrinsic void __ISB(void) */ +/* intrinsic void __DSB(void) */ +/* intrinsic void __DMB(void) */ +/* intrinsic void __set_PRIMASK(); */ +/* intrinsic void __get_PRIMASK(); */ +/* intrinsic void __set_FAULTMASK(); */ +/* intrinsic void __get_FAULTMASK(); */ +/* intrinsic uint32_t __REV(uint32_t value); */ +/* intrinsic uint32_t __REVSH(uint32_t value); */ +/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ +/* intrinsic unsigned long __LDREX(unsigned long *); */ + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +extern uint32_t __RBIT(uint32_t value); + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit values) + */ +extern uint8_t __LDREXB(uint8_t *addr); + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +extern uint16_t __LDREXH(uint16_t *addr); + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +extern uint32_t __LDREXW(uint32_t *addr); + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +extern uint32_t __STREXB(uint8_t value, uint8_t *addr); + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +extern uint32_t __STREXH(uint16_t value, uint16_t *addr); + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +extern uint32_t __STREXW(uint32_t value, uint32_t *addr); + + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +static __INLINE void __enable_irq(void) { __ASM volatile ("cpsie i"); } +static __INLINE void __disable_irq(void) { __ASM volatile ("cpsid i"); } + +static __INLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f"); } +static __INLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f"); } + +static __INLINE void __NOP(void) { __ASM volatile ("nop"); } +static __INLINE void __WFI(void) { __ASM volatile ("wfi"); } +static __INLINE void __WFE(void) { __ASM volatile ("wfe"); } +static __INLINE void __SEV(void) { __ASM volatile ("sev"); } +static __INLINE void __ISB(void) { __ASM volatile ("isb"); } +static __INLINE void __DSB(void) { __ASM volatile ("dsb"); } +static __INLINE void __DMB(void) { __ASM volatile ("dmb"); } +static __INLINE void __CLREX(void) { __ASM volatile ("clrex"); } + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +extern uint32_t __get_BASEPRI(void); + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +extern void __set_BASEPRI(uint32_t basePri); + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +extern uint32_t __get_PRIMASK(void); + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +extern void __set_PRIMASK(uint32_t priMask); + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +extern uint32_t __get_FAULTMASK(void); + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +extern void __set_FAULTMASK(uint32_t faultMask); + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +extern uint32_t __get_CONTROL(void); + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +extern void __set_CONTROL(uint32_t control); + +/** + * @brief Reverse byte order in integer value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +extern uint32_t __REV(uint32_t value); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +extern int32_t __REVSH(int16_t value); + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +extern uint32_t __RBIT(uint32_t value); + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +extern uint8_t __LDREXB(uint8_t *addr); + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +extern uint16_t __LDREXH(uint16_t *addr); + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +extern uint32_t __LDREXW(uint32_t *addr); + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +extern uint32_t __STREXB(uint8_t value, uint8_t *addr); + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +extern uint32_t __STREXH(uint16_t value, uint16_t *addr); + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +extern uint32_t __STREXW(uint32_t value, uint32_t *addr); + + +#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + + +/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface + Core Function Interface containing: + - Core NVIC Functions + - Core SysTick Functions + - Core Reset Functions +*/ +/*@{*/ + +/* ########################## NVIC functions #################################### */ + +/** + * @brief Set the Priority Grouping in NVIC Interrupt Controller + * + * @param PriorityGroup is priority grouping field + * + * Set the priority grouping field using the required unlock sequence. + * The parameter priority_grouping is assigned to the field + * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + (0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + +/** + * @brief Get the Priority Grouping from NVIC Interrupt Controller + * + * @return priority grouping field + * + * Get the priority grouping from NVIC Interrupt Controller. + * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + +/** + * @brief Enable Interrupt in NVIC Interrupt Controller + * + * @param IRQn The positive number of the external interrupt to enable + * + * Enable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + +/** + * @brief Disable the interrupt line for external interrupt specified + * + * @param IRQn The positive number of the external interrupt to disable + * + * Disable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + +/** + * @brief Read the interrupt pending bit for a device specific interrupt source + * + * @param IRQn The number of the device specifc interrupt + * @return 1 = interrupt pending, 0 = interrupt not pending + * + * Read the pending register in NVIC and return 1 if its status is pending, + * otherwise it returns 0 + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + +/** + * @brief Set the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for set pending + * + * Set the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + +/** + * @brief Clear the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for clear pending + * + * Clear the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + +/** + * @brief Read the active bit for an external interrupt + * + * @param IRQn The number of the interrupt for read active bit + * @return 1 = interrupt active, 0 = interrupt not active + * + * Read the active register in NVIC and returns 1 if its status is active, + * otherwise it returns 0. + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + +/** + * @brief Set the priority for an interrupt + * + * @param IRQn The number of the interrupt for set priority + * @param priority The priority to set + * + * Set the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + +/** + * @brief Read the priority for an interrupt + * + * @param IRQn The number of the interrupt for get priority + * @return The priority for the interrupt + * + * Read the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * The returned priority value is automatically aligned to the implemented + * priority bits of the microcontroller. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** + * @brief Encode the priority for an interrupt + * + * @param PriorityGroup The used priority group + * @param PreemptPriority The preemptive priority value (starting from 0) + * @param SubPriority The sub priority value (starting from 0) + * @return The encoded priority for the interrupt + * + * Encode the priority for an interrupt with the given priority group, + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The returned priority value can be used for NVIC_SetPriority(...) function + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** + * @brief Decode the priority of an interrupt + * + * @param Priority The priority for the interrupt + * @param PriorityGroup The used priority group + * @param pPreemptPriority The preemptive priority value (starting from 0) + * @param pSubPriority The sub priority value (starting from 0) + * + * Decode an interrupt priority value with the given priority group to + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The priority value can be retrieved with NVIC_GetPriority(...) function + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + + +/* ################################## SysTick function ############################################ */ + +#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) + +/** + * @brief Initialize and start the SysTick counter and its interrupt. + * + * @param ticks number of ticks between two interrupts + * @return 1 = failed, 0 = successful + * + * Initialise the system tick timer and its interrupt and start the + * system tick timer / counter in free running mode to generate + * periodical interrupts. + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + + + + +/* ################################## Reset function ############################################ */ + +/** + * @brief Initiate a system reset request. + * + * Initiate a system reset request to reset the MCU + */ +static __INLINE void NVIC_SystemReset(void) +{ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ + + + +/* ##################################### Debug In/Output function ########################################### */ + +/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface + Core Debug Interface containing: + - Core Debug Receive / Transmit Functions + - Core Debug Defines + - Core Debug Variables +*/ +/*@{*/ + +extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ + + +/** + * @brief Outputs a character via the ITM channel 0 + * + * @param ch character to output + * @return character to output + * + * The function outputs a character via the ITM channel 0. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ + (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** + * @brief Inputs a character via variable ITM_RxBuffer + * + * @return received character, -1 = no character received + * + * The function inputs a character via variable ITM_RxBuffer. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE int ITM_ReceiveChar (void) { + int ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + * @brief Check if a character via variable ITM_RxBuffer is available + * + * @return 1 = character available, 0 = no character available + * + * The function checks variable ITM_RxBuffer whether a character is available or not. + * The function returns '1' if a character is available and '0' if no character is available. + */ +static __INLINE int ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_definitions */ + +#endif /* __CM3_CORE_H__ */ + +/*lint -restore */ diff --git a/src/ersky9x/crt.c b/src/ersky9x/crt.c new file mode 100644 index 000000000..d370eb281 --- /dev/null +++ b/src/ersky9x/crt.c @@ -0,0 +1,147 @@ +/**************************************************************************** +* Copyright (c) 2011 by Michael Fischer. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. Neither the name of the author nor the names of its contributors may +* be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +* SUCH DAMAGE. +* +**************************************************************************** +* History: +* +* 09.04.2011 mifi First Version +* 29.04.2011 mifi Call SystemInit, and set the Vector Table Offset +* before copy of data and bss segment. +****************************************************************************/ +#define __CRT_C__ + +#include + +/*=========================================================================*/ +/* DEFINE: All extern Data */ +/*=========================================================================*/ +/* + * The next data are defined by the linker script. + */ +extern unsigned long _stext; +extern unsigned long _etext; +extern unsigned long _sdata; +extern unsigned long _edata; +extern unsigned long _sbss; +extern unsigned long _ebss; +extern unsigned long _estack; + +/* This is the main */ +extern int main (void); + +/*=========================================================================*/ +/* DEFINE: Prototypes */ +/*=========================================================================*/ +extern uint32_t SystemInit (void) ; // __attribute__((weak)); + +/*=========================================================================*/ +/* DEFINE: All code exported */ +/*=========================================================================*/ + +/***************************************************************************/ +/* SystemInit */ +/* */ +/* SystemInit is a function which is provided by the CMSIS interface. */ +/* If this function is not available, we need a function here to prevent */ +/* an error of the linker. Therefore this function is declared as weak. */ +/***************************************************************************/ +//uint32_t SystemInit (void) +//{ + +//} /* SystemInit */ + +extern uint32_t Master_frequency ; + +/***************************************************************************/ +/* ResetHandler */ +/* */ +/* This function is used for the C runtime initialisation, */ +/* for handling the .data and .bss segments. */ +/***************************************************************************/ +void ResetHandler (void) +{ + { + register uint32_t *pSrc; + register uint32_t *pDest; + register uint32_t m_freq ; + + /* + * Call the SystemInit code from CMSIS interface if available. + * SystemInit is a week function which can be override + * by an external function. + */ + m_freq = SystemInit(); + + /* + * Set the "Vector Table Offset Register". From the ARM + * documentation, we got the following information: + * + * Use the Vector Table Offset Register to determine: + * - if the vector table is in RAM or code memory + * - the vector table offset. + */ + *((uint32_t*)0xE000ED08) = (uint32_t)&_stext; + + /* + * Copy the initialized data of the ".data" segment + * from the flash to the are in the ram. + */ + pSrc = &_etext; + pDest = &_sdata; + while(pDest < &_edata) + { + *pDest++ = *pSrc++; + } + + /* + * Clear the ".bss" segment. + */ + pDest = &_sbss; + while(pDest < &_ebss) + { + *pDest++ = 0; + } + Master_frequency = m_freq ; + } + + /* + * And now the main function can be called. + * Scotty, energie... + */ + main(); + + /* + * In case there are problems with the + * "warp drive", stop here. + */ + while(1) {}; + +} /* ResetHandler */ + +/*** EOF ***/ diff --git a/src/ersky9x/sound.cpp b/src/ersky9x/sound.cpp new file mode 100644 index 000000000..32c371fca --- /dev/null +++ b/src/ersky9x/sound.cpp @@ -0,0 +1,344 @@ +/**************************************************************************** +* Copyright (c) 2011 by Michael Blandford. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. Neither the name of the author nor the names of its contributors may +* be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +* SUCH DAMAGE. +* +**************************************************************************** +* History: +* +****************************************************************************/ + + + +#include + +#include "AT91SAM3S2.h" +#include "core_cm3.h" + +#include "sound.h" + +void start_sound( void ) ; +void buzzer_on( void ) ; +void buzzer_off( void ) ; +void buzzer_sound( uint8_t time ) ; +void start_timer1( void ) ; +void init_dac( void ) ; +extern "C" void DAC_IRQHandler( void ) ; +void disp_mem( register uint32_t address ) ; +void end_sound( void ) ; +void tone_start( register uint32_t time ) ; +void tone_stop( void ) ; +void init_twi( void ) ; +void set_volume( register uint8_t volume ) ; +extern "C" void TWI0_IRQHandler (void) ; +void audioDefevent( uint8_t e ) ; + + +extern uint32_t Master_frequency ; + +volatile uint32_t Tone_timer ; // Modified in interrupt routine +volatile uint8_t Buzzer_count ; + +// Must NOT be in flash, PDC needs a RAM source. +uint16_t Sine_values[] = +{ +2048,2173,2298,2422,2545,2666,2784,2899,3011,3119, +3223,3322,3417,3505,3589,3666,3736,3800,3857,3907, +3950,3985,4012,4032,4044,4048,4044,4032,4012,3985, +3950,3907,3857,3800,3736,3666,3589,3505,3417,3322, +3223,3119,3011,2899,2784,2666,2545,2422,2298,2173, +2048,1922,1797,1673,1550,1429,1311,1196,1084, 976, + 872, 773, 678, 590, 506, 429, 359, 295, 238, 188, + 145, 110, 83, 63, 51, 48, 51, 63, 83, 110, + 145, 188, 238, 295, 359, 429, 506, 590, 678, 773, + 872, 976,1084,1196,1311,1429,1550,1673,1797,1922 +} ; + +// Must NOT be in flash, PDC needs a RAM source. +uint16_t Sine_values64[] = +{ +2048,2244,2438,2628,2813,2990,3159,3316, +3462,3594,3710,3811,3895,3961,4009,4038, +4048,4038,4009,3961,3895,3811,3710,3594, +3462,3316,3159,2990,2813,2628,2438,2244, +2048,1851,1657,1467,1282,1105, 936, 779, + 633, 501, 385, 284, 200, 134, 86, 57, + 48, 57, 86, 134, 200, 284, 385, 501, + 633, 779, 936,1105,1282,1467,1657,1851 +} ; + +// Sound routines + +void start_sound() +{ + register Pio *pioptr ; + + start_timer1() ; + init_dac() ; + init_twi() ; + + pioptr = PIOA ; +#ifdef REVB + pioptr->PIO_CODR = 0x02000000L ; // Set bit A25 OFF + pioptr->PIO_PER = 0x02000000L ; // Enable bit A25 (Stock buzzer) + pioptr->PIO_OER = 0x02000000L ; // Set bit A25 as output +#else + pioptr->PIO_CODR = 0x00010000L ; // Set bit A16 OFF + pioptr->PIO_PER = 0x00010000L ; // Enable bit A16 (Stock buzzer) + pioptr->PIO_OER = 0x00010000L ; // Set bit A16 as output +#endif +} + +#ifdef REVB +void buzzer_on() +{ + PIOA->PIO_SODR = 0x02000000L ; // Set bit A25 ON +} + +void buzzer_off() +{ + PIOA->PIO_CODR = 0x02000000L ; // Set bit A25 ON +} +#else +void buzzer_on() +{ + PIOA->PIO_SODR = 0x00010000L ; // Set bit A16 ON +} + +void buzzer_off() +{ + PIOA->PIO_CODR = 0x00010000L ; // Set bit A16 ON +} +#endif + +void buzzer_sound( uint8_t time ) +{ + buzzer_on() ; + Buzzer_count = time ; +} + + +static uint32_t Frequency ; + +void set_frequency( uint32_t frequency ) +{ + register Tc *ptc ; + register uint32_t timer ; + + Frequency = frequency ; + timer = Master_frequency / (800 * frequency) ; // MCK/8 and 100 000 Hz + if ( timer > 65535 ) + { + timer = 65535 ; + } + if ( timer < 2 ) + { + timer = 2 ; + } + ptc = TC0 ; // Tc block 0 (TC0-2) + ptc->TC_CHANNEL[1].TC_CCR = TC_CCR0_CLKDIS ; // Stop clock + ptc->TC_CHANNEL[1].TC_RC = timer ; // 100 000 Hz + ptc->TC_CHANNEL[1].TC_RA = timer >> 1 ; + ptc->TC_CHANNEL[1].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) +} + + +// Start TIMER1 at 100000Hz, used for DACC trigger +void start_timer1() +{ + register Tc *ptc ; + register uint32_t timer ; + + // Enable peripheral clock TC0 = bit 23 thru TC5 = bit 28 + PMC->PMC_PCER0 |= 0x01000000L ; // Enable peripheral clock to TC1 + + timer = Master_frequency / 800000 ; // MCK/8 and 100 000 Hz + ptc = TC0 ; // Tc block 0 (TC0-2) + ptc->TC_BCR = 0 ; // No sync + ptc->TC_BMR = 0 ; + ptc->TC_CHANNEL[1].TC_CMR = 0x00008000 ; // Waveform mode + ptc->TC_CHANNEL[1].TC_RC = timer ; // 100 000 Hz + ptc->TC_CHANNEL[1].TC_RA = timer >> 1 ; + ptc->TC_CHANNEL[1].TC_CMR = 0x0009C001 ; // 0000 0000 0000 1001 1100 0000 0000 0001 + // MCK/8, set @ RA, Clear @ RC waveform + ptc->TC_CHANNEL[1].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) + Frequency = 1000 ; +} + + + +// Configure DAC1 (or DAC0 for REVB) +// Not sure why PB14 has not be allocated to the DAC, although it is an EXTRA function +// So maybe it is automatically done +void init_dac() +{ + register Dacc *dacptr ; + + PMC->PMC_PCER0 |= 0x40000000L ; // Enable peripheral clock to DAC + dacptr = DACC ; +#ifdef REVB + dacptr->DACC_MR = 0x0B000215L ; // 0000 1011 0000 0001 0000 0010 0001 0101 +#else + dacptr->DACC_MR = 0x0B010215L ; // 0000 1011 0000 0001 0000 0010 0001 0101 +#endif +#ifdef REVB + dacptr->DACC_CHER = 1 ; // Enable channel 0 +#else + dacptr->DACC_CHER = 2 ; // Enable channel 1 +#endif + dacptr->DACC_CDR = 2048 ; // Half amplitude +// Data for PDC must NOT be in flash, PDC needs a RAM source. + dacptr->DACC_TPR = (uint32_t) Sine_values ; + dacptr->DACC_TNPR = (uint32_t) Sine_values ; + dacptr->DACC_TCR = 50 ; // words, 100 16 bit values + dacptr->DACC_TNCR = 50 ; // words, 100 16 bit values + dacptr->DACC_PTCR = DACC_PTCR_TXTEN ; + NVIC_EnableIRQ(DACC_IRQn) ; +} + +extern "C" void DAC_IRQHandler() +{ +// Data for PDC must NOT be in flash, PDC needs a RAM source. + DACC->DACC_TNPR = (uint32_t) Sine_values ; + DACC->DACC_TNCR = 50 ; // words, 100 16 bit values + if ( Tone_timer ) + { + if ( --Tone_timer == 0 ) + { + DACC->DACC_IDR = DACC_IDR_ENDTX ; + } + } +} + +void end_sound() +{ + DACC->DACC_IDR = DACC_IDR_ENDTX ; + NVIC_DisableIRQ(DACC_IRQn) ; + TWI0->TWI_IDR = TWI_IDR_TXCOMP ; + NVIC_DisableIRQ(TWI0_IRQn) ; + PMC->PMC_PCER0 &= ~0x00080000L ; // Disable peripheral clock to TWI0 + PMC->PMC_PCER0 &= ~0x40000000L ; // Disable peripheral clock to DAC +} + +// Time is in milliseconds +void tone_start( register uint32_t time ) +{ + PMC->PMC_PCER0 |= 0x40000000L ; // Enable peripheral clock to DAC + Tone_timer = Frequency * time / 1000 ; + DACC->DACC_IER = DACC_IER_ENDTX ; +} + +void tone_stop() +{ + DACC->DACC_IDR = DACC_IDR_ENDTX ; // Disable interrupt + Tone_timer = 0 ; +} + + +// Set up for volume control (TWI0) +// Need PA3 and PA4 set to peripheral A +void init_twi() +{ + register Pio *pioptr ; + register uint32_t timing ; + + PMC->PMC_PCER0 |= 0x00080000L ; // Enable peripheral clock to TWI0 + + /* Configure PIO */ + pioptr = PIOA ; + pioptr->PIO_ABCDSR[0] &= ~0x00000018 ; // Peripheral A + pioptr->PIO_ABCDSR[1] &= ~0x00000018 ; // Peripheral A + pioptr->PIO_PDR = 0x00000018 ; // Assign to peripheral + + timing = Master_frequency * 5 / 1000000 ; // 5uS high and low + timing += 15 - 4 ; + timing /= 16 ; + timing |= timing << 8 ; + + TWI0->TWI_CWGR = 0x00040000 | timing ; // TWI clock set + TWI0->TWI_CR = TWI_CR_MSEN | TWI_CR_SVDIS ; // Master mode enable + TWI0->TWI_MMR = 0x002F0000 ; // Device 5E (>>1) and master is writing + NVIC_EnableIRQ(TWI0_IRQn) ; + +} + +static int16_t Volume_required ; +static const uint8_t Volume_scale[NUM_VOL_LEVELS] = +{ + 0, 2, 4, 6, 8, 10, 13, 17, 22, 27, 33, 40, + 64, 82, 96, 105, 112, 117, 120, 122, 124, 125, 126, 127 +} ; + +void set_volume( register uint8_t volume ) +{ + PMC->PMC_PCER0 |= 0x00080000L ; // Enable peripheral clock to TWI0 + + if ( volume >= NUM_VOL_LEVELS ) + { + volume = NUM_VOL_LEVELS - 1 ; + } + volume = Volume_scale[volume] ; + + __disable_irq() ; + if ( TWI0->TWI_IMR & TWI_IMR_TXCOMP ) + { + Volume_required = volume ; + } + else + { + TWI0->TWI_THR = volume ; // Send data + TWI0->TWI_CR = TWI_CR_STOP ; // Stop Tx + TWI0->TWI_IER = TWI_IER_TXCOMP ; + + } + __enable_irq() ; +} + +extern "C" void TWI0_IRQHandler() +{ + if ( Volume_required >= 0 ) + { + TWI0->TWI_THR = Volume_required ; // Send data + Volume_required = -1 ; + TWI0->TWI_CR = TWI_CR_STOP ; // Stop Tx + } + else + { + TWI0->TWI_IDR = TWI_IDR_TXCOMP ; + } +} + + +void audioDefevent(uint8_t e) +{ + buzzer_sound( 4 ) ; +// audio.event(e,BEEP_DEFAULT_FREQ); +} + + + + diff --git a/src/ersky9x/sound.h b/src/ersky9x/sound.h new file mode 100644 index 000000000..3e6207122 --- /dev/null +++ b/src/ersky9x/sound.h @@ -0,0 +1,83 @@ +/**************************************************************************** +* Copyright (c) 2011 by Michael Blandford. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. Neither the name of the author nor the names of its contributors may +* be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +* SUCH DAMAGE. +* +**************************************************************************** +* History: +* +****************************************************************************/ + + + + +/* make sure the defines below always go in numeric order */ +#define AUDIO_TADA (0) +#define AUDIO_WARNING1 (1) +#define AUDIO_WARNING2 (2) +#define AUDIO_WARNING3 (3) +#define AUDIO_ERROR (4) +#define AUDIO_KEYPAD_UP (5) +#define AUDIO_KEYPAD_DOWN (6) +#define AUDIO_TRIM_MOVE (7) +#define AUDIO_TRIM_MIDDLE (8) +#define AUDIO_MENUS (9) +#define AUDIO_POT_STICK_MIDDLE (10) +#define AUDIO_MIX_WARNING_1 (11) +#define AUDIO_MIX_WARNING_2 (12) +#define AUDIO_MIX_WARNING_3 (13) +#define AUDIO_TIMER_30 (14) +#define AUDIO_TIMER_20 (15) +#define AUDIO_TIMER_10 (16) +#define AUDIO_TIMER_LT3 (17) +#define AUDIO_INACTIVITY (18) +#define AUDIO_TX_BATTERY_LOW (19) + + +#define NUM_VOL_LEVELS 24 + +extern volatile uint8_t Buzzer_count ; + + +extern void start_sound( void ) ; +extern void buzzer_on( void ) ; +extern void buzzer_off( void ) ; +extern void buzzer_sound( uint8_t time ) ; +extern void set_frequency( uint32_t frequency ) ; +extern void start_timer1( void ) ; +extern void init_dac( void ) ; +extern "C" void DAC_IRQHandler( void ) ; +extern void end_sound( void ) ; +extern void tone_start( register uint32_t time ) ; +extern void tone_stop( void ) ; +extern void init_twi( void ) ; +extern void set_volume( register uint8_t volume ) ; +extern "C" void TWI0_IRQHandler (void) ; +extern void audioDefevent( uint8_t e ) ; + + + diff --git a/src/ersky9x/vectors_sam3s.c b/src/ersky9x/vectors_sam3s.c new file mode 100644 index 000000000..56c700acd --- /dev/null +++ b/src/ersky9x/vectors_sam3s.c @@ -0,0 +1,197 @@ +/**************************************************************************** +* Copyright (c) 2011 by Michael Fischer. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. Neither the name of the author nor the names of its contributors may +* be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +* SUCH DAMAGE. +* +**************************************************************************** +* History: +* +* 22.05.2011 mifi First Version for the SAM3S4C +****************************************************************************/ +#define __VECTORS_SAM3S_C__ + +/*=========================================================================*/ +/* DEFINE: All extern Data */ +/*=========================================================================*/ +extern unsigned long _estack; + +/*=========================================================================*/ +/* DEFINE: Prototypes */ +/*=========================================================================*/ +void ResetHandler(void); + +void NMI_Handler (void) __attribute__((weak)); +void HardFault_Handler (void) __attribute__((weak)); +void MemManage_Handler (void) __attribute__((weak)); +void BusFault_Handler (void) __attribute__((weak)); +void UsageFault_Handler (void) __attribute__((weak)); +void SVC_Handler (void) __attribute__((weak)); +void DebugMon_Handler (void) __attribute__((weak)); +void PendSV_Handler (void) __attribute__((weak)); +void SysTick_Handler (void) __attribute__((weak)); + +void SUPC_IRQHandler (void) __attribute__((weak)); +void RSTC_IRQHandler (void) __attribute__((weak)); +void RTC_IRQHandler (void) __attribute__((weak)); +void RTT_IRQHandler (void) __attribute__((weak)); +void WDT_IRQHandler (void) __attribute__((weak)); +void PMC_IRQHandler (void) __attribute__((weak)); +void EEFC_IRQHandler (void) __attribute__((weak)); +void UART0_IRQHandler (void) __attribute__((weak)); +void UART1_IRQHandler (void) __attribute__((weak)); +void SMC_IRQHandler (void) __attribute__((weak)); +void PIOA_IRQHandler (void) __attribute__((weak)); +void PIOB_IRQHandler (void) __attribute__((weak)); +void PIOC_IRQHandler (void) __attribute__((weak)); +void USART0_IRQHandler (void) __attribute__((weak)); +void USART1_IRQHandler (void) __attribute__((weak)); +void MCI_IRQHandler (void) __attribute__((weak)); +void TWI0_IRQHandler (void) __attribute__((weak)); +void TWI1_IRQHandler (void) __attribute__((weak)); +void SPI_IRQHandler (void) __attribute__((weak)); +void SSC_IRQHandler (void) __attribute__((weak)); +void TC0_IRQHandler (void) __attribute__((weak)); +void TC1_IRQHandler (void) __attribute__((weak)); +void TC2_IRQHandler (void) __attribute__((weak)); +void TC3_IRQHandler (void) __attribute__((weak)); +void TC4_IRQHandler (void) __attribute__((weak)); +void TC5_IRQHandler (void) __attribute__((weak)); +void ADC_IRQHandler (void) __attribute__((weak)); +void DAC_IRQHandler (void) __attribute__((weak)); +void PWM_IRQHandler (void) __attribute__((weak)); +void CRCCU_IRQHandler (void) __attribute__((weak)); +void ACC_IRQHandler (void) __attribute__((weak)); +void USBD_IRQHandler (void) __attribute__((weak)); + +/*=========================================================================*/ +/* DEFINE: All code exported */ +/*=========================================================================*/ +/* + * This is our vector table. + */ +__attribute__ ((section(".vectors"), used)) +void (* const gVectors[])(void) = +{ + (void (*)(void))((unsigned long)&_estack), + ResetHandler, + NMI_Handler, + HardFault_Handler, + MemManage_Handler, + BusFault_Handler, + UsageFault_Handler, + 0, 0, 0, 0, + SVC_Handler, + DebugMon_Handler, + 0, + PendSV_Handler, + SysTick_Handler, + + SUPC_IRQHandler, /* 0 SUPPLY CONTROLLER */ + RSTC_IRQHandler, /* 1 RESET CONTROLLER */ + RTC_IRQHandler, /* 2 REAL TIME CLOCK */ + RTT_IRQHandler, /* 3 REAL TIME TIMER */ + WDT_IRQHandler, /* 4 WATCHDOG TIMER */ + PMC_IRQHandler, /* 5 PMC */ + EEFC_IRQHandler, /* 6 EEFC */ + 0, /* 7 Reserved */ + UART0_IRQHandler, /* 8 UART0 */ + UART1_IRQHandler, /* 9 UART1 */ + SMC_IRQHandler, /* 10 SMC */ + PIOA_IRQHandler, /* 11 Parallel IO Controller A */ + PIOB_IRQHandler, /* 12 Parallel IO Controller B */ + PIOC_IRQHandler, /* 13 Parallel IO Controller C */ + USART0_IRQHandler, /* 14 USART 0 */ + USART1_IRQHandler, /* 15 USART 1 */ + 0, /* 16 Reserved */ + 0, /* 17 Reserved */ + MCI_IRQHandler, /* 18 MCI */ + TWI0_IRQHandler, /* 19 TWI 0 */ + TWI1_IRQHandler, /* 20 TWI 1 */ + SPI_IRQHandler, /* 21 SPI */ + SSC_IRQHandler, /* 22 SSC */ + TC0_IRQHandler, /* 23 Timer Counter 0 */ + TC1_IRQHandler, /* 24 Timer Counter 1 */ + TC2_IRQHandler, /* 25 Timer Counter 2 */ + TC3_IRQHandler, /* 26 Timer Counter 3 */ + TC4_IRQHandler, /* 27 Timer Counter 4 */ + TC5_IRQHandler, /* 28 Timer Counter 5 */ + ADC_IRQHandler, /* 29 ADC controller */ + DAC_IRQHandler, /* 30 DAC controller */ + PWM_IRQHandler, /* 31 PWM */ + CRCCU_IRQHandler, /* 32 CRC Calculation Unit */ + ACC_IRQHandler, /* 33 Analog Comparator */ + USBD_IRQHandler, /* 34 USB Device Port */ + 0 /* 35 not used */ +}; /* gVectors */ + +/* + * And here are the weak interrupt handlers. + */ +void NMI_Handler (void) { while(1); } +void HardFault_Handler (void) { while(1); } +void MemManage_Handler (void) { while(1); } +void BusFault_Handler (void) { while(1); } +void UsageFault_Handler (void) { while(1); } +void SVC_Handler (void) { while(1); } +void DebugMon_Handler (void) { while(1); } +void PendSV_Handler (void) { while(1); } +void SysTick_Handler (void) { while(1); } + +void SUPC_IRQHandler (void) { while(1); } +void RSTC_IRQHandler (void) { while(1); } +void RTC_IRQHandler (void) { while(1); } +void RTT_IRQHandler (void) { while(1); } +void WDT_IRQHandler (void) { while(1); } +void PMC_IRQHandler (void) { while(1); } +void EEFC_IRQHandler (void) { while(1); } +void UART0_IRQHandler (void) { while(1); } +void UART1_IRQHandler (void) { while(1); } +void SMC_IRQHandler (void) { while(1); } +void PIOA_IRQHandler (void) { while(1); } +void PIOB_IRQHandler (void) { while(1); } +void PIOC_IRQHandler (void) { while(1); } +void USART0_IRQHandler (void) { while(1); } +void USART1_IRQHandler (void) { while(1); } +void MCI_IRQHandler (void) { while(1); } +void TWI0_IRQHandler (void) { while(1); } +void TWI1_IRQHandler (void) { while(1); } +void SPI_IRQHandler (void) { while(1); } +void SSC_IRQHandler (void) { while(1); } +void TC0_IRQHandler (void) { while(1); } +void TC1_IRQHandler (void) { while(1); } +void TC2_IRQHandler (void) { while(1); } +void TC3_IRQHandler (void) { while(1); } +void TC4_IRQHandler (void) { while(1); } +void TC5_IRQHandler (void) { while(1); } +void ADC_IRQHandler (void) { while(1); } +void DAC_IRQHandler (void) { while(1); } +void PWM_IRQHandler (void) { while(1); } +void CRCCU_IRQHandler (void) { while(1); } +void ACC_IRQHandler (void) { while(1); } +void USBD_IRQHandler (void) { while(1); } + +/*** EOF ***/ diff --git a/src/general_menus.cpp b/src/general_menus.cpp index a0bccabb0..b730dbf4f 100644 --- a/src/general_menus.cpp +++ b/src/general_menus.cpp @@ -31,7 +31,7 @@ * */ -#include "menus.h" +#include "open9x.h" const pm_uchar sticks[] PROGMEM = { #include "sticks.lbm" diff --git a/src/diskio-test.cpp b/src/gruvin9x/diskio-test.cpp similarity index 100% rename from src/diskio-test.cpp rename to src/gruvin9x/diskio-test.cpp diff --git a/src/diskio.cpp b/src/gruvin9x/diskio.cpp similarity index 100% rename from src/diskio.cpp rename to src/gruvin9x/diskio.cpp diff --git a/src/diskio.h b/src/gruvin9x/diskio.h similarity index 100% rename from src/diskio.h rename to src/gruvin9x/diskio.h diff --git a/src/ff.cpp b/src/gruvin9x/ff.cpp similarity index 100% rename from src/ff.cpp rename to src/gruvin9x/ff.cpp diff --git a/src/ff.h b/src/gruvin9x/ff.h similarity index 100% rename from src/ff.h rename to src/gruvin9x/ff.h diff --git a/src/ffconf.h b/src/gruvin9x/ffconf.h similarity index 100% rename from src/ffconf.h rename to src/gruvin9x/ffconf.h diff --git a/src/gtime.cpp b/src/gruvin9x/gtime.cpp similarity index 100% rename from src/gtime.cpp rename to src/gruvin9x/gtime.cpp diff --git a/src/gtime.h b/src/gruvin9x/gtime.h similarity index 100% rename from src/gtime.h rename to src/gruvin9x/gtime.h diff --git a/src/integer.h b/src/gruvin9x/integer.h similarity index 100% rename from src/integer.h rename to src/gruvin9x/integer.h diff --git a/src/logs.cpp b/src/gruvin9x/logs.cpp similarity index 100% rename from src/logs.cpp rename to src/gruvin9x/logs.cpp diff --git a/src/logs.h b/src/gruvin9x/logs.h similarity index 100% rename from src/logs.h rename to src/gruvin9x/logs.h diff --git a/src/rtc.cpp b/src/gruvin9x/rtc.cpp similarity index 100% rename from src/rtc.cpp rename to src/gruvin9x/rtc.cpp diff --git a/src/rtc.h b/src/gruvin9x/rtc.h similarity index 100% rename from src/rtc.h rename to src/gruvin9x/rtc.h diff --git a/src/main_views.cpp b/src/main_views.cpp index 14edac1fd..55ab9f6e3 100644 --- a/src/main_views.cpp +++ b/src/main_views.cpp @@ -31,7 +31,7 @@ * */ -#include "menus.h" +#include "open9x.h" #define BOX_WIDTH 23 #define BAR_HEIGHT (BOX_WIDTH-1l) diff --git a/src/menus.cpp b/src/menus.cpp index 3a7bf7cd2..64daad904 100644 --- a/src/menus.cpp +++ b/src/menus.cpp @@ -31,10 +31,7 @@ * */ - #include "open9x.h" -#include "templates.h" -#include "menus.h" int16_t calibratedStick[NUM_STICKS+NUM_POTS]; uint8_t s_pgOfs; diff --git a/src/menus.h b/src/menus.h index 036791d7d..5961dac59 100644 --- a/src/menus.h +++ b/src/menus.h @@ -34,8 +34,6 @@ #ifndef menus_h #define menus_h -#include "open9x.h" - #define NO_HI_LEN 25 #define RESX 1024 diff --git a/src/model_menus.cpp b/src/model_menus.cpp index d0659b352..fe951bf69 100644 --- a/src/model_menus.cpp +++ b/src/model_menus.cpp @@ -31,8 +31,7 @@ * */ -#include "menus.h" -#include "templates.h" +#include "open9x.h" #define WCHART 32 #define X0 (128-WCHART-2) @@ -153,15 +152,20 @@ static uint8_t s_copyMode = 0; static int8_t s_copySrcRow; static int8_t s_copyTgtOfs; +// TODO add ARM code here... void menuProcModelSelect(uint8_t event) { TITLE(STR_MENUMODELSEL); +#if !defined(PCBARM) // flush eeprom write eeFlush(); +#endif if (s_confirmation) { +#if !defined(PCBARM) EFile::rm(FILE_MODEL(m_posVert)); // delete file +#endif s_confirmation = 0; s_copyMode = 0; } @@ -169,10 +173,12 @@ void menuProcModelSelect(uint8_t event) uint8_t _event = (s_warning ? 0 : event); uint8_t _event_ = (IS_RE1_EVT(_event) ? 0 : _event); +#if !defined(PCBARM) if (s_copyMode || !EFile::exists(FILE_MODEL(g_eeGeneral.currModel))) { if ((_event & 0x1f) == KEY_EXIT) _event_ -= KEY_EXIT; } +#endif int8_t oldSub = m_posVert; if (!check_submenu_simple(_event_, MAX_MODELS-1)) return; @@ -199,11 +205,13 @@ void menuProcModelSelect(uint8_t event) s_editMode = -1; break; case EVT_KEY_LONG(KEY_EXIT): +#if !defined(PCBARM) if (s_copyMode && s_copyTgtOfs == 0 && g_eeGeneral.currModel != sub && EFile::exists(FILE_MODEL(sub))) { s_warning = STR_DELETEMODEL; killEvents(_event); break; } +#endif // no break case EVT_KEY_BREAK(KEY_EXIT): if (s_copyMode) { @@ -229,15 +237,19 @@ void menuProcModelSelect(uint8_t event) uint8_t cur = (16 + sub + s_copyTgtOfs) % 16; if (s_copyMode == COPY_MODE) { +#if !defined(PCBARM) if (!theFile.copy(FILE_MODEL(cur), FILE_MODEL(s_copySrcRow))) cur = sub; +#endif } s_copySrcRow = g_eeGeneral.currModel; // to update the currModel value while (sub != cur) { uint8_t src = cur; cur = (s_copyTgtOfs > 0 ? cur+15 : cur+1) % 16; +#if !defined(PCBARM) EFile::swap(FILE_MODEL(src), FILE_MODEL(cur)); +#endif if (src == s_copySrcRow) s_copySrcRow = cur; else if (cur == s_copySrcRow) @@ -269,9 +281,11 @@ void menuProcModelSelect(uint8_t event) killEvents(event); return; } +#if !defined(PCBARM) else if (EFile::exists(FILE_MODEL(sub))) { s_copyMode = (s_copyMode == COPY_MODE ? MOVE_MODE : COPY_MODE); } +#endif break; case EVT_KEY_FIRST(KEY_LEFT): case EVT_KEY_FIRST(KEY_RIGHT): @@ -309,7 +323,9 @@ void menuProcModelSelect(uint8_t event) } lcd_puts(9*FW-(LEN_FREE-4)*FW, 0, STR_FREE); +#if !defined(PCBARM) lcd_outdezAtt( 17*FW, 0, EeFsGetFree(),0); +#endif DisplayScreenIndex(e_ModelSelect, DIM(menuTabModel), (sub == g_eeGeneral.currModel) ? INVERS : 0); @@ -341,12 +357,14 @@ void menuProcModelSelect(uint8_t event) k %= 16; +#if !defined(PCBARM) if (EFile::exists(FILE_MODEL(k))) { uint16_t size = eeLoadModelName(k, reusableBuffer.model_name); putsModelName(4*FW, y, reusableBuffer.model_name, k, 0); lcd_outdezAtt(20*FW, y, size, 0); if (k==g_eeGeneral.currModel && (s_copySrcRow<0 || i+s_pgOfs!=sub)) lcd_putc(1, y, '*'); } +#endif if (s_copyMode && sub==i+s_pgOfs) { lcd_filled_rect(9, y, DISPLAY_W-1-9, 7); diff --git a/src/myeeprom.h b/src/myeeprom.h index 327ec7495..e51eb1884 100644 --- a/src/myeeprom.h +++ b/src/myeeprom.h @@ -229,7 +229,7 @@ enum Functions { FUNC_PLAY_SOMO, #endif FUNC_RESET, -#if defined(FRSKY_HUB) or defined(WS_HOW_HIGH) +#if defined(FRSKY_HUB) || defined(WS_HOW_HIGH) FUNC_VARIO, #endif #ifdef LOGS @@ -409,6 +409,12 @@ enum Dsm2Variants { DSM2_DSMX }; +#ifdef MAVLINK +#define EXTDATA MavlinkData mavlink +#else +#define EXTDATA FrSkyData frsky +#endif + PACK(typedef struct t_ModelData { char name[10]; // 10 must be first for eeLoadModelName TimerData timers[MAX_TIMERS]; @@ -432,11 +438,9 @@ PACK(typedef struct t_ModelData { FuncSwData funcSw[NUM_FSW]; SwashRingData swashR; PhaseData phaseData[MAX_PHASES]; -#ifdef MAVLINK - MavlinkData mavlink; -#else - FrSkyData frsky; -#endif + + EXTDATA; + int8_t ppmFrameLength; // 0=22.5ms (10ms-30ms) 0.5msec increments uint8_t thrTraceSrc; uint8_t modelId; diff --git a/src/open9x.cpp b/src/open9x.cpp index 1dcaf3c1e..e1699de06 100644 --- a/src/open9x.cpp +++ b/src/open9x.cpp @@ -129,6 +129,75 @@ LimitData *limitaddress(uint8_t idx) return &g_model.limitData[idx]; } +void generalDefault() +{ + memset(&g_eeGeneral,0,sizeof(g_eeGeneral)); + g_eeGeneral.myVers = EEPROM_VER; + g_eeGeneral.contrast = 25; + g_eeGeneral.vBatWarn = 90; + for (int i = 0; i < 7; ++i) { + g_eeGeneral.calibMid[i] = 0x200; + g_eeGeneral.calibSpanNeg[i] = 0x180; + g_eeGeneral.calibSpanPos[i] = 0x180; + } + g_eeGeneral.chkSum = (0x200 * 7) + (0x180 * 5); +} + +uint16_t evalChkSum() +{ + uint16_t sum=0; + for (int i=0; i<12;i++) + sum += g_eeGeneral.calibMid[i]; + return sum; +} + +#ifndef TEMPLATES +inline void applyDefaultTemplate() +{ + for (int i=0; idestCh = i; + md->weight = 100; + md->srcRaw = channel_order(i+1); + } + + STORE_MODELVARS; +} +#endif + +void modelDefault(uint8_t id) +{ + memset(&g_model, 0, sizeof(g_model)); + applyDefaultTemplate(); +} + +void resetProto() +{ +#if defined(DSM2_SERIAL) + if (g_model.protocol == PROTO_DSM2) { + cli(); +#if defined(FRSKY) + DSM2_Init(); +#endif + sei(); + } + else { + cli(); +#if defined(FRSKY) + FRSKY_Init(); +#else + DSM2_Done(); +#endif + sei(); +#if defined(FRSKY) + FRSKY_setModelAlarms(); +#endif + } +#elif defined(FRSKY) + FRSKY_setModelAlarms(); +#endif +} + int16_t intpol(int16_t x, uint8_t idx) // -100, -75, -50, -25, 0 ,25 ,50, 75, 100 { #define D9 (RESX * 2 / 8) @@ -572,6 +641,7 @@ void doSplash() } #endif +#if !defined(PCBARM) void checkLowEEPROM() { if(g_eeGeneral.disableMemoryWarning) return; @@ -580,6 +650,7 @@ void checkLowEEPROM() alert(STR_EEPROMLOWMEM); } } +#endif void alertMessages( const pm_char * s, const pm_char * t ) { @@ -949,7 +1020,7 @@ uint16_t g_vbat100mV = 0; volatile uint8_t tick10ms = 0; uint16_t g_LightOffCounter; -#if not defined(PCBARM) +#if !defined(PCBARM) FORCEINLINE bool checkSlaveMode() { // no power -> only phone jack = slave mode @@ -1531,12 +1602,14 @@ void perMain() sei(); } +#if !defined(PCBARM) if (!eeprom_buffer_size) { if (theFile.isWriting()) theFile.nextWriteStep(); else if (s_eeDirtyMsk) eeCheck(); } +#endif if (!tick10ms) return; //make sure the rest happen only every 10ms. @@ -1824,7 +1897,7 @@ void perMain() int16_t g_ppmIns[8]; uint8_t ppmInState = 0; //0=unsync 1..8= wait for value i-1 -#if not defined(SIMU) and not defined(PCBARM) +#if !defined(SIMU) && !defined(PCBARM) volatile uint8_t g_tmr16KHz; //continuous timer 16ms (16MHz/1024/256) -- 8-bit counter overflow #if defined (PCBV4) diff --git a/src/open9x.h b/src/open9x.h index 74cca21e3..7af5c195e 100644 --- a/src/open9x.h +++ b/src/open9x.h @@ -31,8 +31,8 @@ * */ -#ifndef gruvin9x_h -#define gruvin9x_h +#ifndef open9x_h +#define open9x_h #define MAJ_VERS 2 #define MIN_VERS 00 @@ -78,17 +78,25 @@ extern void board_init(); #include #endif -#include "file.h" -#include "lcd.h" #include "myeeprom.h" -#if not defined(SIMU) +#if defined(PCBARM) +#include "eeprom_arm.h" +#else +#include "eeprom_avr.h" +#endif + +#include "lcd.h" +#include "menus.h" +#ifdef TEMPLATES +#include "templates.h" +#endif + +#if !defined(SIMU) #define assert(x) #define printf printf_not_allowed #endif -extern RlcFile theFile; //used for any file operation - // G: The following comments relate to the original stock PCB only // // elev thr @@ -456,6 +464,8 @@ uint8_t keyDown(); bool keyState(EnumKeys enuk); void readKeysAndTrims(); +uint16_t evalChkSum(); + /// Gibt Alarm Maske auf lcd aus. /// Die Maske wird so lange angezeigt bis eine beliebige Taste gedrueckt wird. void alert(const pm_char * s, bool defaults=false); @@ -603,13 +613,15 @@ uint16_t isqrt32(uint32_t n); /// eeCheck ins EEPROM zurueckgeschrieben. void eeWriteBlockCmp(const void *i_pointer_ram, uint16_t i_pointer_eeprom, size_t size); void eeDirty(uint8_t msk); -inline void eeFlush() { theFile.flush(); } void eeCheck(bool immediately=false); void eeReadAll(); bool eeModelExists(uint8_t id); uint16_t eeLoadModelName(uint8_t id, char *name); void eeLoadModel(uint8_t id); int8_t eeFindEmptyModel(uint8_t id, bool down); +void generalDefault(); +void modelDefault(uint8_t id); +void resetProto(); extern inline int16_t calc100toRESX(int8_t x) { @@ -771,7 +783,9 @@ extern uint16_t jeti_keys; // Re-useable byte array to save having multiple buffers union ReusableBuffer { +#if !defined(PCBARM) uint8_t eefs_buffer[BLOCKS]; // used by EeFsck +#endif char model_name[sizeof(g_model.name)]; // used by menuProcModelSelect diff --git a/src/pers.cpp b/src/pers.cpp deleted file mode 100644 index 19bd80fe5..000000000 --- a/src/pers.cpp +++ /dev/null @@ -1,225 +0,0 @@ -/* - * Authors (alphabetical order) - * - Bertrand Songis - * - Bryan J. Rentoul (Gruvin) - * - Cameron Weeks - * - Erez Raviv - * - Jean-Pierre Parisy - * - Karl Szmutny - * - Michael Blandford - * - Michal Hlavinka - * - Pat Mackenzie - * - Philip Moss - * - Rob Thomson - * - Romolo Manfredini - * - Thomas Husterer - * - * open9x is based on code named - * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, - * er9x by Erez Raviv: http://code.google.com/p/er9x/, - * and the original (and ongoing) project by - * Thomas Husterer, th9x: http://code.google.com/p/th9x/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include "open9x.h" -#include "templates.h" - -RlcFile theFile; //used for any file operation - -void generalDefault() -{ - memset(&g_eeGeneral,0,sizeof(g_eeGeneral)); - g_eeGeneral.myVers = EEPROM_VER; - g_eeGeneral.contrast = 25; - g_eeGeneral.vBatWarn = 90; - for (int i = 0; i < 7; ++i) { - g_eeGeneral.calibMid[i] = 0x200; - g_eeGeneral.calibSpanNeg[i] = 0x180; - g_eeGeneral.calibSpanPos[i] = 0x180; - } - g_eeGeneral.chkSum = (0x200 * 7) + (0x180 * 5); -} - -uint16_t evalChkSum() -{ - uint16_t sum=0; - for (int i=0; i<12;i++) - sum += g_eeGeneral.calibMid[i]; - return sum; -} - -bool eeLoadGeneral() -{ - theFile.openRlc(FILE_GENERAL); - if (theFile.readRlc((uint8_t*)&g_eeGeneral, 1) == 1 && g_eeGeneral.myVers == EEPROM_VER) { - theFile.openRlc(FILE_GENERAL); // TODO include this openRlc inside readRlc - if (theFile.readRlc((uint8_t*)&g_eeGeneral, sizeof(g_eeGeneral)) <= sizeof(EEGeneral)) { - uint16_t sum = evalChkSum(); - if (g_eeGeneral.chkSum == sum) { - return true; - } - } - } - return false; -} - -#ifndef TEMPLATES -inline void applyDefaultTemplate() -{ - for (int i=0; idestCh = i; - md->weight = 100; - md->srcRaw = channel_order(i+1); - } - - STORE_MODELVARS; -} -#endif - -void modelDefault(uint8_t id) -{ - memset(&g_model, 0, sizeof(g_model)); - applyDefaultTemplate(); -} - -uint16_t eeLoadModelName(uint8_t id, char *name) -{ - memset(name, 0, sizeof(g_model.name)); - if (id 0 && sz != sizeof(g_model)) { - printf("Model data read=%d bytes vs %d bytes\n", sz, (int)sizeof(ModelData)); - } -#endif - - if (sz == 0) { - // alert("Error Loading Model"); - modelDefault(id); - eeCheck(true); - } - - resetProto(); - resetAll(); - -#ifdef LOGS - initLogs(); -#endif - } -} - -int8_t eeFindEmptyModel(uint8_t id, bool down) -{ - int8_t i = id; - for (;;) { - i = (MAX_MODELS + (down ? i+1 : i-1)) % MAX_MODELS; - if (!EFile::exists(FILE_MODEL(i))) break; - if (i == id) return -1; // no free space in directory left - } - return i; -} - -void eeReadAll() -{ - if(!EeFsOpen() || - EeFsck() < 0 || - !eeLoadGeneral()) - { - alert(STR_BADEEPROMDATA, true); - message(STR_EEPROMFORMATTING); - EeFsFormat(); - //alert(PSTR("format ok")); - generalDefault(); - //alert(PSTR("default ok")); - - theFile.writeRlc(FILE_GENERAL, FILE_TYP_GENERAL,(uint8_t*)&g_eeGeneral,sizeof(EEGeneral), true); - - modelDefault(0); - //alert(PSTR("modef ok")); - theFile.writeRlc(FILE_MODEL(0), FILE_TYP_MODEL, (uint8_t*)&g_model, sizeof(g_model), true); - //alert(PSTR("modwrite ok")); - } - - stickMode = g_eeGeneral.stickMode; - eeLoadModel(g_eeGeneral.currModel); -} - - -uint8_t s_eeDirtyMsk; -void eeDirty(uint8_t msk) -{ - s_eeDirtyMsk |= msk; -} - -void eeCheck(bool immediately) -{ - if (immediately) { - eeFlush(); - } - if (s_eeDirtyMsk & EE_GENERAL) { - s_eeDirtyMsk -= EE_GENERAL; - theFile.writeRlc(FILE_GENERAL, FILE_TYP_GENERAL, (uint8_t*)&g_eeGeneral, sizeof(EEGeneral), immediately); - if (!immediately) return; - } - if (s_eeDirtyMsk & EE_MODEL) { - s_eeDirtyMsk = 0; - theFile.writeRlc(FILE_MODEL(g_eeGeneral.currModel), FILE_TYP_MODEL, (uint8_t*)&g_model, sizeof(g_model), immediately); - } -} diff --git a/src/statistics_views.cpp b/src/statistics_views.cpp index b63307829..113372d40 100644 --- a/src/statistics_views.cpp +++ b/src/statistics_views.cpp @@ -31,7 +31,7 @@ * */ -#include "menus.h" +#include "open9x.h" void menuProcStatistic(uint8_t event) { diff --git a/src/templates.cpp b/src/templates.cpp index 0216518eb..ec83d05fb 100644 --- a/src/templates.cpp +++ b/src/templates.cpp @@ -52,7 +52,6 @@ */ #include "open9x.h" -#include "templates.h" MixData* setDest(uint8_t dch, bool clear=false) { diff --git a/src/translations/en.h b/src/translations/en.h index ddffea57b..b1e9d58f3 100644 --- a/src/translations/en.h +++ b/src/translations/en.h @@ -63,7 +63,7 @@ #define TR_VCSWFUNC "----\0 ""v>ofs ""vofs""|v|v2 ""v1=v2 ""v1<=v2 " #define LEN_VFSWFUNC "\015" -#if defined(FRSKY_HUB) or defined(WS_HOW_HIGH) +#if defined(FRSKY_HUB) || defined(WS_HOW_HIGH) #define TR_VARIO "Vario " #else #define TR_VARIO diff --git a/src/translations/fr.h b/src/translations/fr.h index e379a6439..160903521 100644 --- a/src/translations/fr.h +++ b/src/translations/fr.h @@ -63,7 +63,7 @@ #define TR_VCSWFUNC "----\0 ""v>ofs ""vofs""|v|v2 ""v1=v2 ""v1<=v2 " #define LEN_VFSWFUNC "\015" -#if defined(FRSKY_HUB) or defined(WS_HOW_HIGH) +#if defined(FRSKY_HUB) || defined(WS_HOW_HIGH) #define TR_VARIO "Vario " #else #define TR_VARIO diff --git a/src/translations/se.h b/src/translations/se.h index 2c17aac16..ff3623213 100644 --- a/src/translations/se.h +++ b/src/translations/se.h @@ -63,7 +63,7 @@ #define TR_VCSWFUNC "----\0 ""v>ofs ""vofs""(v)v2 ""v1=v2 ""v1<=v2 " #define LEN_VFSWFUNC "\015" -#if defined(FRSKY_HUB) or defined(WS_HOW_HIGH) +#if defined(FRSKY_HUB) || defined(WS_HOW_HIGH) #define TR_VARIO "Vario " #else #define TR_VARIO