[all] DSM2 changes (variants are now chosen in Protocol field)
[sky9x] PPM Port2 support added [all] Negative GVARS bug fixed
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@@ -35,7 +35,7 @@
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#include "../open9x.h"
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// TODO illogical in the driver :(
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void setupPulsesPPM();
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void setupPulsesPPM(uint32_t ppmPort=0);
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void init_main_ppm( uint32_t period, uint32_t out_enable )
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{
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@@ -62,9 +62,26 @@ void init_main_ppm( uint32_t period, uint32_t out_enable )
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pwmptr->PWM_CH_NUM[3].PWM_CDTY = g_model.ppmDelay*100+600; // Duty in half uS
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pwmptr->PWM_CH_NUM[3].PWM_CDTYUPD = g_model.ppmDelay*100+600; // Duty in half uS
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pwmptr->PWM_ENA = PWM_ENA_CHID3 ; // Enable channel 3
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NVIC_EnableIRQ(PWM_IRQn) ;
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pwmptr->PWM_IER1 = PWM_IER1_CHID3 ;
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#if !defined(REVA)
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configure_pins( PIO_PC15, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_B | PIN_PORTC | PIN_NO_PULLUP ) ;
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#endif
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#if !defined(REVA)
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// PWM1 for PPM2
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pwmptr->PWM_CH_NUM[1].PWM_CMR = 0x0000000B ; // CLKB
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if (g_model.pulsePol)
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pwmptr->PWM_CH_NUM[1].PWM_CMR |= 0x00000200 ; // CPOL
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pwmptr->PWM_CH_NUM[1].PWM_CPDR = period ; // Period
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pwmptr->PWM_CH_NUM[1].PWM_CPDRUPD = period ; // Period
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pwmptr->PWM_CH_NUM[1].PWM_CDTY = g_model.ppmDelay*100+600 ; // Duty
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pwmptr->PWM_CH_NUM[1].PWM_CDTYUPD = g_model.ppmDelay*100+600 ; // Duty
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pwmptr->PWM_ENA = PWM_ENA_CHID1 ; // Enable channel 1
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#endif
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pwmptr->PWM_IER1 = PWM_IER1_CHID1 ;
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NVIC_EnableIRQ(PWM_IRQn) ;
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}
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void disable_main_ppm()
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@@ -75,6 +92,16 @@ void disable_main_ppm()
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pioptr->PIO_PER = PIO_PA17 ; // Assign A17 to PIO
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PWM->PWM_IDR1 = PWM_IDR1_CHID3 ;
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}
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void disable_ppm2()
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{
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register Pio *pioptr ;
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pioptr = PIOC ;
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pioptr->PIO_PER = PIO_PC17 ; // Assign A17 to PIO
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PWM->PWM_IDR1 = PWM_IDR1_CHID1 ;
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NVIC_DisableIRQ(PWM_IRQn) ;
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}
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