diff --git a/radio/src/targets/horus/system_stm32f4xx.c b/radio/src/targets/horus/system_stm32f4xx.c
index 393603fc2..5c609ffac 100644
--- a/radio/src/targets/horus/system_stm32f4xx.c
+++ b/radio/src/targets/horus/system_stm32f4xx.c
@@ -23,7 +23,7 @@
   * @file    system_stm32f4xx.c
   * @author  MCD Application Team
   * @version V1.1.0
-  * @date    21-March-2015
+  * @date    25-March-2016
   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   *          This file contains the system clock configuration for STM32F4xx devices,
   *          and is generated by the clock configuration tool
@@ -199,7 +199,7 @@
   * @{
   */
 
-  uint32_t SystemCoreClock = 180000000;
+  uint32_t SystemCoreClock = 168000000;
 
   __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 
@@ -426,7 +426,7 @@ static void SetSysClock(void)
     }
    
     /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
-    FLASH->ACR = FLASH_ACR_PRFTEN |FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
+    FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
 
     /* Select the main PLL as system clock source */
     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));