diff --git a/radio/bootloader/Makefile b/radio/bootloader/Makefile
index 22b73105f..9971b9d5b 100644
--- a/radio/bootloader/Makefile
+++ b/radio/bootloader/Makefile
@@ -99,7 +99,8 @@ else
CPPDEFS += -DPCBTARANIS
FULL_PRJ = $(PROJECT)_ramBoot
EXTRAINCDIRS += include
-# EXTRAINCDIRS += ../targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include
+ EXTRAINCDIRS += ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc
+ EXTRAINCDIRS += ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include
endif
endif
@@ -111,9 +112,9 @@ UADEFS =
ifeq ($(PCB), TARANIS)
SRC = system_stm32f2xx.c \
- stm32f2xx_rcc.c \
- stm32f2xx_gpio.c \
- stm32f2xx_spi.c \
+ ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rcc.c \
+ ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_gpio.c \
+ ../src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_spi.c \
misc.c \
ccsbcs.c \
../src/targets/taranis/STM32_USB-Host-Device_Lib_V2.1.0/Libraries/STM32_USB_OTG_Driver/src/usb_core.c \
diff --git a/radio/bootloader/include/stm32f2xx_gpio.h b/radio/bootloader/include/stm32f2xx_gpio.h
deleted file mode 100644
index b0c6b5f7c..000000000
--- a/radio/bootloader/include/stm32f2xx_gpio.h
+++ /dev/null
@@ -1,411 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_gpio.h
- * @author MCD Application Team
- * @version V1.1.2
- * @date 05-March-2012
- * @brief This file contains all the functions prototypes for the GPIO firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2012 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_GPIO_H
-#define __STM32F2xx_GPIO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx.h"
-
-/** @addtogroup STM32F2xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup GPIO
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
- ((PERIPH) == GPIOB) || \
- ((PERIPH) == GPIOC) || \
- ((PERIPH) == GPIOD) || \
- ((PERIPH) == GPIOE) || \
- ((PERIPH) == GPIOF) || \
- ((PERIPH) == GPIOG) || \
- ((PERIPH) == GPIOH) || \
- ((PERIPH) == GPIOI))
-
-/**
- * @brief GPIO Configuration Mode enumeration
- */
-typedef enum
-{
- GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
- GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
- GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */
- GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */
-}GPIOMode_TypeDef;
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \
- ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
-
-/**
- * @brief GPIO Output type enumeration
- */
-typedef enum
-{
- GPIO_OType_PP = 0x00,
- GPIO_OType_OD = 0x01
-}GPIOOType_TypeDef;
-#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
-
-
-/**
- * @brief GPIO Output Maximum frequency enumeration
- */
-typedef enum
-{
- GPIO_Speed_2MHz = 0x00, /*!< Low speed */
- GPIO_Speed_25MHz = 0x01, /*!< Medium speed */
- GPIO_Speed_50MHz = 0x02, /*!< Fast speed */
- GPIO_Speed_100MHz = 0x03 /*!< High speed on 30 pF (80 MHz Output max speed on 15 pF) */
-}GPIOSpeed_TypeDef;
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_2MHz) || ((SPEED) == GPIO_Speed_25MHz) || \
- ((SPEED) == GPIO_Speed_50MHz)|| ((SPEED) == GPIO_Speed_100MHz))
-
-/**
- * @brief GPIO Configuration PullUp PullDown enumeration
- */
-typedef enum
-{
- GPIO_PuPd_NOPULL = 0x00,
- GPIO_PuPd_UP = 0x01,
- GPIO_PuPd_DOWN = 0x02
-}GPIOPuPd_TypeDef;
-#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
- ((PUPD) == GPIO_PuPd_DOWN))
-
-/**
- * @brief GPIO Bit SET and Bit RESET enumeration
- */
-typedef enum
-{
- Bit_RESET = 0,
- Bit_SET
-}BitAction;
-#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
-
-
-/**
- * @brief GPIO Init structure definition
- */
-typedef struct
-{
- uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
- This parameter can be any value of @ref GPIO_pins_define */
-
- GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
- This parameter can be a value of @ref GPIOMode_TypeDef */
-
- GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
- This parameter can be a value of @ref GPIOSpeed_TypeDef */
-
- GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.
- This parameter can be a value of @ref GPIOOType_TypeDef */
-
- GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
- This parameter can be a value of @ref GPIOPuPd_TypeDef */
-}GPIO_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Constants
- * @{
- */
-
-/** @defgroup GPIO_pins_define
- * @{
- */
-#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */
-#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */
-#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */
-#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */
-#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */
-#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */
-#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */
-#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */
-#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */
-#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */
-#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */
-#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */
-#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */
-#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */
-#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */
-#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */
-#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */
-
-#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
-#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
- ((PIN) == GPIO_Pin_1) || \
- ((PIN) == GPIO_Pin_2) || \
- ((PIN) == GPIO_Pin_3) || \
- ((PIN) == GPIO_Pin_4) || \
- ((PIN) == GPIO_Pin_5) || \
- ((PIN) == GPIO_Pin_6) || \
- ((PIN) == GPIO_Pin_7) || \
- ((PIN) == GPIO_Pin_8) || \
- ((PIN) == GPIO_Pin_9) || \
- ((PIN) == GPIO_Pin_10) || \
- ((PIN) == GPIO_Pin_11) || \
- ((PIN) == GPIO_Pin_12) || \
- ((PIN) == GPIO_Pin_13) || \
- ((PIN) == GPIO_Pin_14) || \
- ((PIN) == GPIO_Pin_15))
-/**
- * @}
- */
-
-
-/** @defgroup GPIO_Pin_sources
- * @{
- */
-#define GPIO_PinSource0 ((uint8_t)0x00)
-#define GPIO_PinSource1 ((uint8_t)0x01)
-#define GPIO_PinSource2 ((uint8_t)0x02)
-#define GPIO_PinSource3 ((uint8_t)0x03)
-#define GPIO_PinSource4 ((uint8_t)0x04)
-#define GPIO_PinSource5 ((uint8_t)0x05)
-#define GPIO_PinSource6 ((uint8_t)0x06)
-#define GPIO_PinSource7 ((uint8_t)0x07)
-#define GPIO_PinSource8 ((uint8_t)0x08)
-#define GPIO_PinSource9 ((uint8_t)0x09)
-#define GPIO_PinSource10 ((uint8_t)0x0A)
-#define GPIO_PinSource11 ((uint8_t)0x0B)
-#define GPIO_PinSource12 ((uint8_t)0x0C)
-#define GPIO_PinSource13 ((uint8_t)0x0D)
-#define GPIO_PinSource14 ((uint8_t)0x0E)
-#define GPIO_PinSource15 ((uint8_t)0x0F)
-
-#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
- ((PINSOURCE) == GPIO_PinSource1) || \
- ((PINSOURCE) == GPIO_PinSource2) || \
- ((PINSOURCE) == GPIO_PinSource3) || \
- ((PINSOURCE) == GPIO_PinSource4) || \
- ((PINSOURCE) == GPIO_PinSource5) || \
- ((PINSOURCE) == GPIO_PinSource6) || \
- ((PINSOURCE) == GPIO_PinSource7) || \
- ((PINSOURCE) == GPIO_PinSource8) || \
- ((PINSOURCE) == GPIO_PinSource9) || \
- ((PINSOURCE) == GPIO_PinSource10) || \
- ((PINSOURCE) == GPIO_PinSource11) || \
- ((PINSOURCE) == GPIO_PinSource12) || \
- ((PINSOURCE) == GPIO_PinSource13) || \
- ((PINSOURCE) == GPIO_PinSource14) || \
- ((PINSOURCE) == GPIO_PinSource15))
-/**
- * @}
- */
-
-/** @defgroup GPIO_Alternat_function_selection_define
- * @{
- */
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
-
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
-#define GPIO_AF_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
-
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
-#define GPIO_AF_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
-#define GPIO_AF_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
-
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
-#define GPIO_AF_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
-#define GPIO_AF_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
-#define GPIO_AF_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
-
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
-#define GPIO_AF_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
-#define GPIO_AF_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
-#define GPIO_AF_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
-
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
-
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
-#define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
-#define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
-
-/**
- * @brief AF 8 selection
- */
-#define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
-#define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
-#define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
-
-/**
- * @brief AF 9 selection
- */
-#define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
-#define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
-#define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
-#define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
-#define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
-
-/**
- * @brief AF 10 selection
- */
-#define GPIO_AF_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
-#define GPIO_AF_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */
-
-/**
- * @brief AF 11 selection
- */
-#define GPIO_AF_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
-
-/**
- * @brief AF 12 selection
- */
-#define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */
-#define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
-#define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
-
-/**
- * @brief AF 13 selection
- */
-#define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
-
-/**
- * @brief AF 15 selection
- */
-#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
- ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
- ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
- ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \
- ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \
- ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \
- ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
- ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \
- ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \
- ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \
- ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
- ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \
- ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \
- ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \
- ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \
- ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_FSMC) || \
- ((AF) == GPIO_AF_OTG_HS_FS) || ((AF) == GPIO_AF_SDIO) || \
- ((AF) == GPIO_AF_DCMI) || ((AF) == GPIO_AF_EVENTOUT))
-/**
- * @}
- */
-
-/** @defgroup GPIO_Legacy
- * @{
- */
-
-#define GPIO_Mode_AIN GPIO_Mode_AN
-
-#define GPIO_AF_OTG1_FS GPIO_AF_OTG_FS
-#define GPIO_AF_OTG2_HS GPIO_AF_OTG_HS
-#define GPIO_AF_OTG2_FS GPIO_AF_OTG_HS_FS
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the GPIO configuration to the default reset state ****/
-void GPIO_DeInit(GPIO_TypeDef* GPIOx);
-
-/* Initialization and Configuration functions *********************************/
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-
-/* GPIO Read and Write functions **********************************************/
-//uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
-//void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-//void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
-void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-
-/* GPIO Alternate functions configuration function ****************************/
-void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F2xx_GPIO_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/radio/bootloader/include/stm32f2xx_rcc.h b/radio/bootloader/include/stm32f2xx_rcc.h
deleted file mode 100644
index b87733e32..000000000
--- a/radio/bootloader/include/stm32f2xx_rcc.h
+++ /dev/null
@@ -1,515 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_rcc.h
- * @author MCD Application Team
- * @version V1.1.2
- * @date 05-March-2012
- * @brief This file contains all the functions prototypes for the RCC firmware library.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2012 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_RCC_H
-#define __STM32F2xx_RCC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx.h"
-
-/** @addtogroup STM32F2xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup RCC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-typedef struct
-{
- uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */
- uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */
- uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */
- uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */
-}RCC_ClocksTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Constants
- * @{
- */
-
-/** @defgroup RCC_HSE_configuration
- * @{
- */
-#define RCC_HSE_OFF ((uint8_t)0x00)
-#define RCC_HSE_ON ((uint8_t)0x01)
-#define RCC_HSE_Bypass ((uint8_t)0x05)
-#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
- ((HSE) == RCC_HSE_Bypass))
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_Clock_Source
- * @{
- */
-#define RCC_PLLSource_HSI ((uint32_t)0x00000000)
-#define RCC_PLLSource_HSE ((uint32_t)0x00400000)
-#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
- ((SOURCE) == RCC_PLLSource_HSE))
-#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
-#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
-#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
-#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
-
-#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
-#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Source
- * @{
- */
-#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
-#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
-#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
-#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
- ((SOURCE) == RCC_SYSCLKSource_HSE) || \
- ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB_Clock_Source
- * @{
- */
-#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
-#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
-#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
-#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
-#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
-#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
-#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
-#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
-#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
-#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
- ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
- ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
- ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
- ((HCLK) == RCC_SYSCLK_Div512))
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_APB2_Clock_Source
- * @{
- */
-#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
-#define RCC_HCLK_Div2 ((uint32_t)0x00001000)
-#define RCC_HCLK_Div4 ((uint32_t)0x00001400)
-#define RCC_HCLK_Div8 ((uint32_t)0x00001800)
-#define RCC_HCLK_Div16 ((uint32_t)0x00001C00)
-#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
- ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
- ((PCLK) == RCC_HCLK_Div16))
-/**
- * @}
- */
-
-/** @defgroup RCC_Interrupt_Source
- * @{
- */
-#define RCC_IT_LSIRDY ((uint8_t)0x01)
-#define RCC_IT_LSERDY ((uint8_t)0x02)
-#define RCC_IT_HSIRDY ((uint8_t)0x04)
-#define RCC_IT_HSERDY ((uint8_t)0x08)
-#define RCC_IT_PLLRDY ((uint8_t)0x10)
-#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
-#define RCC_IT_CSS ((uint8_t)0x80)
-#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
-#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
- ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
- ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
- ((IT) == RCC_IT_PLLI2SRDY))
-#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup RCC_LSE_Configuration
- * @{
- */
-#define RCC_LSE_OFF ((uint8_t)0x00)
-#define RCC_LSE_ON ((uint8_t)0x01)
-#define RCC_LSE_Bypass ((uint8_t)0x04)
-#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
- ((LSE) == RCC_LSE_Bypass))
-/**
- * @}
- */
-
-/** @defgroup RCC_RTC_Clock_Source
- * @{
- */
-#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
-#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
-#define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300)
-#define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300)
-#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300)
-#define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300)
-#define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300)
-#define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300)
-#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300)
-#define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300)
-#define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300)
-#define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300)
-#define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300)
-#define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300)
-#define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300)
-#define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300)
-#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300)
-#define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300)
-#define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300)
-#define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300)
-#define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300)
-#define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300)
-#define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300)
-#define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300)
-#define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300)
-#define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300)
-#define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300)
-#define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300)
-#define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300)
-#define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300)
-#define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300)
-#define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300)
-#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
- ((SOURCE) == RCC_RTCCLKSource_LSI) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div31))
-/**
- * @}
- */
-
-/** @defgroup RCC_I2S_Clock_Source
- * @{
- */
-#define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00)
-#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01)
-
-#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB1_Peripherals
- * @{
- */
-#define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001)
-#define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002)
-#define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004)
-#define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008)
-#define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010)
-#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020)
-#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040)
-#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080)
-#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100)
-#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000)
-#define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000)
-#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000)
-#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000)
-#define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000)
-#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000)
-#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000)
-#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000)
-#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000)
-#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000)
-#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000)
-#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000)
-#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000)
-#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x819BEE00) == 0x00) && ((PERIPH) != 0x00))
-#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00))
-#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81986E00) == 0x00) && ((PERIPH) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB2_Peripherals
- * @{
- */
-#define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001)
-#define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010)
-#define RCC_AHB2Periph_HASH ((uint32_t)0x00000020)
-#define RCC_AHB2Periph_RNG ((uint32_t)0x00000040)
-#define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080)
-#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB3_Peripherals
- * @{
- */
-#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
-#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Peripherals
- * @{
- */
-#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
-#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
-#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
-#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
-#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
-#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
-#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
-#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
-#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
-#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
-#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
-#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
-#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
-#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
-#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
-#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
-#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
-#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
-#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000)
-#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
-#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
-#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
-#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
-#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC9013600) == 0x00) && ((PERIPH) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_Peripherals
- * @{
- */
-#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001)
-#define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002)
-#define RCC_APB2Periph_USART1 ((uint32_t)0x00000010)
-#define RCC_APB2Periph_USART6 ((uint32_t)0x00000020)
-#define RCC_APB2Periph_ADC ((uint32_t)0x00000100)
-#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100)
-#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200)
-#define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400)
-#define RCC_APB2Periph_SDIO ((uint32_t)0x00000800)
-#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
-#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000)
-#define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000)
-#define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000)
-#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000)
-#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A0CC) == 0x00) && ((PERIPH) != 0x00))
-#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A6CC) == 0x00) && ((PERIPH) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup RCC_MCO1_Clock_Source_Prescaler
- * @{
- */
-#define RCC_MCO1Source_HSI ((uint32_t)0x00000000)
-#define RCC_MCO1Source_LSE ((uint32_t)0x00200000)
-#define RCC_MCO1Source_HSE ((uint32_t)0x00400000)
-#define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000)
-#define RCC_MCO1Div_1 ((uint32_t)0x00000000)
-#define RCC_MCO1Div_2 ((uint32_t)0x04000000)
-#define RCC_MCO1Div_3 ((uint32_t)0x05000000)
-#define RCC_MCO1Div_4 ((uint32_t)0x06000000)
-#define RCC_MCO1Div_5 ((uint32_t)0x07000000)
-#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \
- ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))
-
-#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \
- ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \
- ((DIV) == RCC_MCO1Div_5))
-/**
- * @}
- */
-
-/** @defgroup RCC_MCO2_Clock_Source_Prescaler
- * @{
- */
-#define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000)
-#define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000)
-#define RCC_MCO2Source_HSE ((uint32_t)0x80000000)
-#define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000)
-#define RCC_MCO2Div_1 ((uint32_t)0x00000000)
-#define RCC_MCO2Div_2 ((uint32_t)0x20000000)
-#define RCC_MCO2Div_3 ((uint32_t)0x28000000)
-#define RCC_MCO2Div_4 ((uint32_t)0x30000000)
-#define RCC_MCO2Div_5 ((uint32_t)0x38000000)
-#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \
- ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK))
-
-#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \
- ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \
- ((DIV) == RCC_MCO2Div_5))
-/**
- * @}
- */
-
-/** @defgroup RCC_Flag
- * @{
- */
-#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
-#define RCC_FLAG_HSERDY ((uint8_t)0x31)
-#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
-#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
-#define RCC_FLAG_LSERDY ((uint8_t)0x41)
-#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
-#define RCC_FLAG_BORRST ((uint8_t)0x79)
-#define RCC_FLAG_PINRST ((uint8_t)0x7A)
-#define RCC_FLAG_PORRST ((uint8_t)0x7B)
-#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
-#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
-#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
-#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
-#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
- ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
- ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \
- ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
- ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
- ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
- ((FLAG) == RCC_FLAG_PLLI2SRDY))
-#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the RCC clock configuration to the default reset state */
-void RCC_DeInit(void);
-
-/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
-void RCC_HSEConfig(uint8_t RCC_HSE);
-ErrorStatus RCC_WaitForHSEStartUp(void);
-void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
-void RCC_HSICmd(FunctionalState NewState);
-void RCC_LSEConfig(uint8_t RCC_LSE);
-void RCC_LSICmd(FunctionalState NewState);
-
-void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
-void RCC_PLLCmd(FunctionalState NewState);
-void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
-void RCC_PLLI2SCmd(FunctionalState NewState);
-
-void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
-void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
-void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
-
-/* System, AHB and APB busses clocks configuration functions ******************/
-void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
-uint8_t RCC_GetSYSCLKSource(void);
-void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
-void RCC_PCLK1Config(uint32_t RCC_HCLK);
-void RCC_PCLK2Config(uint32_t RCC_HCLK);
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
-
-/* Peripheral clocks configuration functions **********************************/
-void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
-void RCC_RTCCLKCmd(FunctionalState NewState);
-void RCC_BackupResetCmd(FunctionalState NewState);
-void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
-
-void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
-void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
-void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
-void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
-void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
-
-void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
-void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
-void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
-void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
-void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
-
-void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
-void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
-void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
-void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
-void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
-FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
-void RCC_ClearFlag(void);
-ITStatus RCC_GetITStatus(uint8_t RCC_IT);
-void RCC_ClearITPendingBit(uint8_t RCC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_RCC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/radio/bootloader/include/stm32f2xx_rtc.h b/radio/bootloader/include/stm32f2xx_rtc.h
deleted file mode 100644
index 677f9783b..000000000
--- a/radio/bootloader/include/stm32f2xx_rtc.h
+++ /dev/null
@@ -1,650 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_rtc.h
- * @author MCD Application Team
- * @version V1.1.2
- * @date 05-March-2012
- * @brief This file contains all the functions prototypes for the RTC firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2012 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_RTC_H
-#define __STM32F2xx_RTC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-//#include "X9D/stm32f2xx.h"
-
-/** @addtogroup STM32F2xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup RTC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief RTC Init structures definition
- */
-typedef struct
-{
- uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format.
- This parameter can be a value of @ref RTC_Hour_Formats */
-
- uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
- This parameter must be set to a value lower than 0x7F */
-
- uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
- This parameter must be set to a value lower than 0x1FFF */
-}RTC_InitTypeDef;
-
-/**
- * @brief RTC Time structure definition
- */
-typedef struct
-{
- uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour.
- This parameter must be set to a value in the 0-12 range
- if the RTC_HourFormat_12 is selected or 0-23 range if
- the RTC_HourFormat_24 is selected. */
-
- uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes.
- This parameter must be set to a value in the 0-59 range. */
-
- uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds.
- This parameter must be set to a value in the 0-59 range. */
-
- uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time.
- This parameter can be a value of @ref RTC_AM_PM_Definitions */
-}RTC_TimeTypeDef;
-
-/**
- * @brief RTC Date structure definition
- */
-typedef struct
-{
- uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.
- This parameter can be a value of @ref RTC_WeekDay_Definitions */
-
- uint8_t RTC_Month; /*!< Specifies the RTC Date Month (in BCD format).
- This parameter can be a value of @ref RTC_Month_Date_Definitions */
-
- uint8_t RTC_Date; /*!< Specifies the RTC Date.
- This parameter must be set to a value in the 1-31 range. */
-
- uint8_t RTC_Year; /*!< Specifies the RTC Date Year.
- This parameter must be set to a value in the 0-99 range. */
-}RTC_DateTypeDef;
-
-/**
- * @brief RTC Alarm structure definition
- */
-typedef struct
-{
- RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */
-
- uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks.
- This parameter can be a value of @ref RTC_AlarmMask_Definitions */
-
- uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
- This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
-
- uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
- If the Alarm Date is selected, this parameter
- must be set to a value in the 1-31 range.
- If the Alarm WeekDay is selected, this
- parameter can be a value of @ref RTC_WeekDay_Definitions */
-}RTC_AlarmTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup RTC_Exported_Constants
- * @{
- */
-
-
-/** @defgroup RTC_Hour_Formats
- * @{
- */
-#define RTC_HourFormat_24 ((uint32_t)0x00000000)
-#define RTC_HourFormat_12 ((uint32_t)0x00000040)
-#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \
- ((FORMAT) == RTC_HourFormat_24))
-/**
- * @}
- */
-
-/** @defgroup RTC_Asynchronous_Predivider
- * @{
- */
-#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F)
-
-/**
- * @}
- */
-
-
-/** @defgroup RTC_Synchronous_Predivider
- * @{
- */
-#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x1FFF)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Time_Definitions
- * @{
- */
-#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))
-#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)
-#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)
-#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_AM_PM_Definitions
- * @{
- */
-#define RTC_H12_AM ((uint8_t)0x00)
-#define RTC_H12_PM ((uint8_t)0x40)
-#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Year_Date_Definitions
- * @{
- */
-#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Month_Date_Definitions
- * @{
- */
-
-/* Coded in BCD format */
-#define RTC_Month_January ((uint8_t)0x01)
-#define RTC_Month_February ((uint8_t)0x02)
-#define RTC_Month_March ((uint8_t)0x03)
-#define RTC_Month_April ((uint8_t)0x04)
-#define RTC_Month_May ((uint8_t)0x05)
-#define RTC_Month_June ((uint8_t)0x06)
-#define RTC_Month_July ((uint8_t)0x07)
-#define RTC_Month_August ((uint8_t)0x08)
-#define RTC_Month_September ((uint8_t)0x09)
-#define RTC_Month_October ((uint8_t)0x10)
-#define RTC_Month_November ((uint8_t)0x11)
-#define RTC_Month_December ((uint8_t)0x12)
-#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))
-#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_WeekDay_Definitions
- * @{
- */
-
-#define RTC_Weekday_Monday ((uint8_t)0x01)
-#define RTC_Weekday_Tuesday ((uint8_t)0x02)
-#define RTC_Weekday_Wednesday ((uint8_t)0x03)
-#define RTC_Weekday_Thursday ((uint8_t)0x04)
-#define RTC_Weekday_Friday ((uint8_t)0x05)
-#define RTC_Weekday_Saturday ((uint8_t)0x06)
-#define RTC_Weekday_Sunday ((uint8_t)0x07)
-#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
- ((WEEKDAY) == RTC_Weekday_Tuesday) || \
- ((WEEKDAY) == RTC_Weekday_Wednesday) || \
- ((WEEKDAY) == RTC_Weekday_Thursday) || \
- ((WEEKDAY) == RTC_Weekday_Friday) || \
- ((WEEKDAY) == RTC_Weekday_Saturday) || \
- ((WEEKDAY) == RTC_Weekday_Sunday))
-/**
- * @}
- */
-
-
-/** @defgroup RTC_Alarm_Definitions
- * @{
- */
-#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
-#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
- ((WEEKDAY) == RTC_Weekday_Tuesday) || \
- ((WEEKDAY) == RTC_Weekday_Wednesday) || \
- ((WEEKDAY) == RTC_Weekday_Thursday) || \
- ((WEEKDAY) == RTC_Weekday_Friday) || \
- ((WEEKDAY) == RTC_Weekday_Saturday) || \
- ((WEEKDAY) == RTC_Weekday_Sunday))
-
-/**
- * @}
- */
-
-
-/** @defgroup RTC_AlarmDateWeekDay_Definitions
- * @{
- */
-#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000)
-#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000)
-
-#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
- ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
-
-/**
- * @}
- */
-
-
-/** @defgroup RTC_AlarmMask_Definitions
- * @{
- */
-#define RTC_AlarmMask_None ((uint32_t)0x00000000)
-#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000)
-#define RTC_AlarmMask_Hours ((uint32_t)0x00800000)
-#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000)
-#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080)
-#define RTC_AlarmMask_All ((uint32_t)0x80808080)
-#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Alarms_Definitions
- * @{
- */
-#define RTC_Alarm_A ((uint32_t)0x00000100)
-#define RTC_Alarm_B ((uint32_t)0x00000200)
-#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))
-#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Wakeup_Timer_Definitions
- * @{
- */
-#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000)
-#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001)
-#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002)
-#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003)
-#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004)
-#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006)
-#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \
- ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \
- ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \
- ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \
- ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \
- ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))
-#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
-/**
- * @}
- */
-
-/** @defgroup RTC_Time_Stamp_Edges_definitions
- * @{
- */
-#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000)
-#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008)
-#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \
- ((EDGE) == RTC_TimeStampEdge_Falling))
-/**
- * @}
- */
-
-/** @defgroup RTC_Output_selection_Definitions
- * @{
- */
-#define RTC_Output_Disable ((uint32_t)0x00000000)
-#define RTC_Output_AlarmA ((uint32_t)0x00200000)
-#define RTC_Output_AlarmB ((uint32_t)0x00400000)
-#define RTC_Output_WakeUp ((uint32_t)0x00600000)
-
-#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \
- ((OUTPUT) == RTC_Output_AlarmA) || \
- ((OUTPUT) == RTC_Output_AlarmB) || \
- ((OUTPUT) == RTC_Output_WakeUp))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Output_Polarity_Definitions
- * @{
- */
-#define RTC_OutputPolarity_High ((uint32_t)0x00000000)
-#define RTC_OutputPolarity_Low ((uint32_t)0x00100000)
-#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \
- ((POL) == RTC_OutputPolarity_Low))
-/**
- * @}
- */
-
-
-/** @defgroup RTC_Digital_Calibration_Definitions
- * @{
- */
-#define RTC_CalibSign_Positive ((uint32_t)0x00000000)
-#define RTC_CalibSign_Negative ((uint32_t)0x00000080)
-#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \
- ((SIGN) == RTC_CalibSign_Negative))
-#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
-
-/**
- * @}
- */
-
-
-/** @defgroup RTC_DayLightSaving_Definitions
- * @{
- */
-#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000)
-#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000)
-#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \
- ((SAVE) == RTC_DayLightSaving_ADD1H))
-
-#define RTC_StoreOperation_Reset ((uint32_t)0x00000000)
-#define RTC_StoreOperation_Set ((uint32_t)0x00040000)
-#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \
- ((OPERATION) == RTC_StoreOperation_Set))
-/**
- * @}
- */
-
-/** @defgroup RTC_Tamper_Trigger_Definitions
- * @{
- */
-#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000)
-#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001)
-#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
- ((TRIGGER) == RTC_TamperTrigger_FallingEdge))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Tamper_Pins_Definitions
- * @{
- */
-#define RTC_Tamper_1 RTC_TAFCR_TAMP1E
-#define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Tamper_Pin_Selection
- * @{
- */
-#define RTC_TamperPin_PC13 ((uint32_t)0x00000000)
-#define RTC_TamperPin_PI8 ((uint32_t)0x00010000)
-#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TamperPin_PC13) || \
- ((PIN) == RTC_TamperPin_PI8))
-/**
- * @}
- */
-
-/** @defgroup RTC_TimeStamp_Pin_Selection
- * @{
- */
-#define RTC_TimeStampPin_PC13 ((uint32_t)0x00000000)
-#define RTC_TimeStampPin_PI8 ((uint32_t)0x00020000)
-#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TimeStampPin_PC13) || \
- ((PIN) == RTC_TimeStampPin_PI8))
-/**
- * @}
- */
-
-/** @defgroup RTC_Output_Type_ALARM_OUT
- * @{
- */
-#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000)
-#define RTC_OutputType_PushPull ((uint32_t)0x00040000)
-#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \
- ((TYPE) == RTC_OutputType_PushPull))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Backup_Registers_Definitions
- * @{
- */
-
-#define RTC_BKP_DR0 ((uint32_t)0x00000000)
-#define RTC_BKP_DR1 ((uint32_t)0x00000001)
-#define RTC_BKP_DR2 ((uint32_t)0x00000002)
-#define RTC_BKP_DR3 ((uint32_t)0x00000003)
-#define RTC_BKP_DR4 ((uint32_t)0x00000004)
-#define RTC_BKP_DR5 ((uint32_t)0x00000005)
-#define RTC_BKP_DR6 ((uint32_t)0x00000006)
-#define RTC_BKP_DR7 ((uint32_t)0x00000007)
-#define RTC_BKP_DR8 ((uint32_t)0x00000008)
-#define RTC_BKP_DR9 ((uint32_t)0x00000009)
-#define RTC_BKP_DR10 ((uint32_t)0x0000000A)
-#define RTC_BKP_DR11 ((uint32_t)0x0000000B)
-#define RTC_BKP_DR12 ((uint32_t)0x0000000C)
-#define RTC_BKP_DR13 ((uint32_t)0x0000000D)
-#define RTC_BKP_DR14 ((uint32_t)0x0000000E)
-#define RTC_BKP_DR15 ((uint32_t)0x0000000F)
-#define RTC_BKP_DR16 ((uint32_t)0x00000010)
-#define RTC_BKP_DR17 ((uint32_t)0x00000011)
-#define RTC_BKP_DR18 ((uint32_t)0x00000012)
-#define RTC_BKP_DR19 ((uint32_t)0x00000013)
-#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \
- ((BKP) == RTC_BKP_DR1) || \
- ((BKP) == RTC_BKP_DR2) || \
- ((BKP) == RTC_BKP_DR3) || \
- ((BKP) == RTC_BKP_DR4) || \
- ((BKP) == RTC_BKP_DR5) || \
- ((BKP) == RTC_BKP_DR6) || \
- ((BKP) == RTC_BKP_DR7) || \
- ((BKP) == RTC_BKP_DR8) || \
- ((BKP) == RTC_BKP_DR9) || \
- ((BKP) == RTC_BKP_DR10) || \
- ((BKP) == RTC_BKP_DR11) || \
- ((BKP) == RTC_BKP_DR12) || \
- ((BKP) == RTC_BKP_DR13) || \
- ((BKP) == RTC_BKP_DR14) || \
- ((BKP) == RTC_BKP_DR15) || \
- ((BKP) == RTC_BKP_DR16) || \
- ((BKP) == RTC_BKP_DR17) || \
- ((BKP) == RTC_BKP_DR18) || \
- ((BKP) == RTC_BKP_DR19))
-/**
- * @}
- */
-
-/** @defgroup RTC_Input_parameter_format_definitions
- * @{
- */
-#define RTC_Format_BIN ((uint32_t)0x000000000)
-#define RTC_Format_BCD ((uint32_t)0x000000001)
-#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Flags_Definitions
- * @{
- */
-#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)
-#define RTC_FLAG_TSOVF ((uint32_t)0x00001000)
-#define RTC_FLAG_TSF ((uint32_t)0x00000800)
-#define RTC_FLAG_WUTF ((uint32_t)0x00000400)
-#define RTC_FLAG_ALRBF ((uint32_t)0x00000200)
-#define RTC_FLAG_ALRAF ((uint32_t)0x00000100)
-#define RTC_FLAG_INITF ((uint32_t)0x00000040)
-#define RTC_FLAG_RSF ((uint32_t)0x00000020)
-#define RTC_FLAG_INITS ((uint32_t)0x00000010)
-#define RTC_FLAG_WUTWF ((uint32_t)0x00000004)
-#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002)
-#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001)
-#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \
- ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \
- ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \
- ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \
- ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \
- ((FLAG) == RTC_FLAG_TAMP1F))
-#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFFC0DF) == (uint32_t)RESET))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Interrupts_Definitions
- * @{
- */
-#define RTC_IT_TS ((uint32_t)0x00008000)
-#define RTC_IT_WUT ((uint32_t)0x00004000)
-#define RTC_IT_ALRB ((uint32_t)0x00002000)
-#define RTC_IT_ALRA ((uint32_t)0x00001000)
-#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
-#define RTC_IT_TAMP1 ((uint32_t)0x00020000)
-
-#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))
-#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \
- ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \
- ((IT) == RTC_IT_TAMP1))
-#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFD0FFF) == (uint32_t)RESET))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Legacy
- * @{
- */
-#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig
-#define RTC_DigitalCalibCmd RTC_CoarseCalibCmd
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the RTC configuration to the default reset state *****/
-ErrorStatus RTC_DeInit(void);
-
-/* Initialization and Configuration functions *********************************/
-ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
-void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
-void RTC_WriteProtectionCmd(FunctionalState NewState);
-ErrorStatus RTC_EnterInitMode(void);
-void RTC_ExitInitMode(void);
-ErrorStatus RTC_WaitForSynchro(void);
-ErrorStatus RTC_RefClockCmd(FunctionalState NewState);
-
-/* Time and Date configuration functions **************************************/
-ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
-void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
-void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
-ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
-void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
-void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
-
-/* Alarms (Alarm A and Alarm B) configuration functions **********************/
-void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
-void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
-void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
-ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);
-
-/* WakeUp Timer configuration functions ***************************************/
-void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock);
-void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);
-uint32_t RTC_GetWakeUpCounter(void);
-ErrorStatus RTC_WakeUpCmd(FunctionalState NewState);
-
-/* Daylight Saving configuration functions ************************************/
-void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
-uint32_t RTC_GetStoreOperation(void);
-
-/* Output pin Configuration function ******************************************/
-void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
-
-/* Coarse Calibration configuration functions *********************************/
-ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value);
-ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState);
-void RTC_CalibOutputCmd(FunctionalState NewState);
-
-/* TimeStamp configuration functions ******************************************/
-void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);
-void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct,
- RTC_DateTypeDef* RTC_StampDateStruct);
-
-/* Tampers configuration functions ********************************************/
-void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
-void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
-
-/* Backup Data Registers configuration functions ******************************/
-void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);
-uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);
-
-/* RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration
- functions ******************************************************************/
-void RTC_TamperPinSelection(uint32_t RTC_TamperPin);
-void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin);
-void RTC_OutputTypeConfig(uint32_t RTC_OutputType);
-
-/* Interrupts and flags management functions **********************************/
-void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);
-FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
-void RTC_ClearFlag(uint32_t RTC_FLAG);
-ITStatus RTC_GetITStatus(uint32_t RTC_IT);
-void RTC_ClearITPendingBit(uint32_t RTC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F2xx_RTC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/radio/bootloader/include/stm32f2xx_spi.h b/radio/bootloader/include/stm32f2xx_spi.h
deleted file mode 100644
index 7a56a23f9..000000000
--- a/radio/bootloader/include/stm32f2xx_spi.h
+++ /dev/null
@@ -1,526 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_spi.h
- * @author MCD Application Team
- * @version V1.1.2
- * @date 05-March-2012
- * @brief This file contains all the functions prototypes for the SPI
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2012 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_SPI_H
-#define __STM32F2xx_SPI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-//#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h"
-
-/** @addtogroup STM32F2xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup SPI
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief SPI Init structure definition
- */
-
-typedef struct
-{
- uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
- This parameter can be a value of @ref SPI_data_direction */
-
- uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.
- This parameter can be a value of @ref SPI_mode */
-
- uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
- This parameter can be a value of @ref SPI_data_size */
-
- uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
- This parameter can be a value of @ref SPI_Clock_Polarity */
-
- uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
- This parameter can be a value of @ref SPI_Clock_Phase */
-
- uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
- hardware (NSS pin) or by software using the SSI bit.
- This parameter can be a value of @ref SPI_Slave_Select_management */
-
- uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
- used to configure the transmit and receive SCK clock.
- This parameter can be a value of @ref SPI_BaudRate_Prescaler
- @note The communication clock is derived from the master
- clock. The slave clock does not need to be set. */
-
- uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
- This parameter can be a value of @ref SPI_MSB_LSB_transmission */
-
- uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
-}SPI_InitTypeDef;
-
-/**
- * @brief I2S Init structure definition
- */
-
-typedef struct
-{
-
- uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
- This parameter can be a value of @ref I2S_Mode */
-
- uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
- This parameter can be a value of @ref I2S_Standard */
-
- uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
- This parameter can be a value of @ref I2S_Data_Format */
-
- uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
- This parameter can be a value of @ref I2S_MCLK_Output */
-
- uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
- This parameter can be a value of @ref I2S_Audio_Frequency */
-
- uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
- This parameter can be a value of @ref I2S_Clock_Polarity */
-}I2S_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SPI_Exported_Constants
- * @{
- */
-
-#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
- ((PERIPH) == SPI2) || \
- ((PERIPH) == SPI3))
-
-#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
- ((PERIPH) == SPI3))
-
-/** @defgroup SPI_data_direction
- * @{
- */
-
-#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
-#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
-#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
-#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
-#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
- ((MODE) == SPI_Direction_2Lines_RxOnly) || \
- ((MODE) == SPI_Direction_1Line_Rx) || \
- ((MODE) == SPI_Direction_1Line_Tx))
-/**
- * @}
- */
-
-/** @defgroup SPI_mode
- * @{
- */
-
-#define SPI_Mode_Master ((uint16_t)0x0104)
-#define SPI_Mode_Slave ((uint16_t)0x0000)
-#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
- ((MODE) == SPI_Mode_Slave))
-/**
- * @}
- */
-
-/** @defgroup SPI_data_size
- * @{
- */
-
-#define SPI_DataSize_16b ((uint16_t)0x0800)
-#define SPI_DataSize_8b ((uint16_t)0x0000)
-#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
- ((DATASIZE) == SPI_DataSize_8b))
-/**
- * @}
- */
-
-/** @defgroup SPI_Clock_Polarity
- * @{
- */
-
-#define SPI_CPOL_Low ((uint16_t)0x0000)
-#define SPI_CPOL_High ((uint16_t)0x0002)
-#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
- ((CPOL) == SPI_CPOL_High))
-/**
- * @}
- */
-
-/** @defgroup SPI_Clock_Phase
- * @{
- */
-
-#define SPI_CPHA_1Edge ((uint16_t)0x0000)
-#define SPI_CPHA_2Edge ((uint16_t)0x0001)
-#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
- ((CPHA) == SPI_CPHA_2Edge))
-/**
- * @}
- */
-
-/** @defgroup SPI_Slave_Select_management
- * @{
- */
-
-#define SPI_NSS_Soft ((uint16_t)0x0200)
-#define SPI_NSS_Hard ((uint16_t)0x0000)
-#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
- ((NSS) == SPI_NSS_Hard))
-/**
- * @}
- */
-
-/** @defgroup SPI_BaudRate_Prescaler
- * @{
- */
-
-#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
-#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
-#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
-#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
-#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
-#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
-#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
-#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_256))
-/**
- * @}
- */
-
-/** @defgroup SPI_MSB_LSB_transmission
- * @{
- */
-
-#define SPI_FirstBit_MSB ((uint16_t)0x0000)
-#define SPI_FirstBit_LSB ((uint16_t)0x0080)
-#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
- ((BIT) == SPI_FirstBit_LSB))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_Mode
- * @{
- */
-
-#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
-#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
-#define I2S_Mode_MasterTx ((uint16_t)0x0200)
-#define I2S_Mode_MasterRx ((uint16_t)0x0300)
-#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
- ((MODE) == I2S_Mode_SlaveRx) || \
- ((MODE) == I2S_Mode_MasterTx)|| \
- ((MODE) == I2S_Mode_MasterRx))
-/**
- * @}
- */
-
-
-/** @defgroup SPI_I2S_Standard
- * @{
- */
-
-#define I2S_Standard_Phillips ((uint16_t)0x0000)
-#define I2S_Standard_MSB ((uint16_t)0x0010)
-#define I2S_Standard_LSB ((uint16_t)0x0020)
-#define I2S_Standard_PCMShort ((uint16_t)0x0030)
-#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
-#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
- ((STANDARD) == I2S_Standard_MSB) || \
- ((STANDARD) == I2S_Standard_LSB) || \
- ((STANDARD) == I2S_Standard_PCMShort) || \
- ((STANDARD) == I2S_Standard_PCMLong))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_Data_Format
- * @{
- */
-
-#define I2S_DataFormat_16b ((uint16_t)0x0000)
-#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
-#define I2S_DataFormat_24b ((uint16_t)0x0003)
-#define I2S_DataFormat_32b ((uint16_t)0x0005)
-#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
- ((FORMAT) == I2S_DataFormat_16bextended) || \
- ((FORMAT) == I2S_DataFormat_24b) || \
- ((FORMAT) == I2S_DataFormat_32b))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_MCLK_Output
- * @{
- */
-
-#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
-#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
-#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
- ((OUTPUT) == I2S_MCLKOutput_Disable))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_Audio_Frequency
- * @{
- */
-
-#define I2S_AudioFreq_192k ((uint32_t)192000)
-#define I2S_AudioFreq_96k ((uint32_t)96000)
-#define I2S_AudioFreq_48k ((uint32_t)48000)
-#define I2S_AudioFreq_44k ((uint32_t)44100)
-#define I2S_AudioFreq_32k ((uint32_t)32000)
-#define I2S_AudioFreq_22k ((uint32_t)22050)
-#define I2S_AudioFreq_16k ((uint32_t)16000)
-#define I2S_AudioFreq_11k ((uint32_t)11025)
-#define I2S_AudioFreq_8k ((uint32_t)8000)
-#define I2S_AudioFreq_Default ((uint32_t)2)
-
-#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
- ((FREQ) <= I2S_AudioFreq_192k)) || \
- ((FREQ) == I2S_AudioFreq_Default))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_Clock_Polarity
- * @{
- */
-
-#define I2S_CPOL_Low ((uint16_t)0x0000)
-#define I2S_CPOL_High ((uint16_t)0x0008)
-#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
- ((CPOL) == I2S_CPOL_High))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_DMA_transfer_requests
- * @{
- */
-
-#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
-#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
-#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup SPI_NSS_internal_software_management
- * @{
- */
-
-#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
-#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
-#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
- ((INTERNAL) == SPI_NSSInternalSoft_Reset))
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_Transmit_Receive
- * @{
- */
-
-#define SPI_CRC_Tx ((uint8_t)0x00)
-#define SPI_CRC_Rx ((uint8_t)0x01)
-#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
-/**
- * @}
- */
-
-/** @defgroup SPI_direction_transmit_receive
- * @{
- */
-
-#define SPI_Direction_Rx ((uint16_t)0xBFFF)
-#define SPI_Direction_Tx ((uint16_t)0x4000)
-#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
- ((DIRECTION) == SPI_Direction_Tx))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_interrupts_definition
- * @{
- */
-
-#define SPI_I2S_IT_TXE ((uint8_t)0x71)
-#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
-#define SPI_I2S_IT_ERR ((uint8_t)0x50)
-#define I2S_IT_UDR ((uint8_t)0x53)
-#define SPI_I2S_IT_TIFRFE ((uint8_t)0x58)
-
-#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
- ((IT) == SPI_I2S_IT_RXNE) || \
- ((IT) == SPI_I2S_IT_ERR))
-
-#define SPI_I2S_IT_OVR ((uint8_t)0x56)
-#define SPI_IT_MODF ((uint8_t)0x55)
-#define SPI_IT_CRCERR ((uint8_t)0x54)
-
-#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
-
-#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE)|| ((IT) == SPI_I2S_IT_TXE) || \
- ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \
- ((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\
- ((IT) == SPI_I2S_IT_TIFRFE))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_flags_definition
- * @{
- */
-
-#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
-#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
-#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
-#define I2S_FLAG_UDR ((uint16_t)0x0008)
-#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
-#define SPI_FLAG_MODF ((uint16_t)0x0020)
-#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
-#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
-#define SPI_I2S_FLAG_TIFRFE ((uint16_t)0x0100)
-
-#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
-#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
- ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
- ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
- ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
- ((FLAG) == SPI_I2S_FLAG_TIFRFE))
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_polynomial
- * @{
- */
-
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_Legacy
- * @{
- */
-
-#define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx
-#define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx
-#define SPI_IT_TXE SPI_I2S_IT_TXE
-#define SPI_IT_RXNE SPI_I2S_IT_RXNE
-#define SPI_IT_ERR SPI_I2S_IT_ERR
-#define SPI_IT_OVR SPI_I2S_IT_OVR
-#define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE
-#define SPI_FLAG_TXE SPI_I2S_FLAG_TXE
-#define SPI_FLAG_OVR SPI_I2S_FLAG_OVR
-#define SPI_FLAG_BSY SPI_I2S_FLAG_BSY
-#define SPI_DeInit SPI_I2S_DeInit
-#define SPI_ITConfig SPI_I2S_ITConfig
-#define SPI_DMACmd SPI_I2S_DMACmd
-#define SPI_SendData SPI_I2S_SendData
-#define SPI_ReceiveData SPI_I2S_ReceiveData
-#define SPI_GetFlagStatus SPI_I2S_GetFlagStatus
-#define SPI_ClearFlag SPI_I2S_ClearFlag
-#define SPI_GetITStatus SPI_I2S_GetITStatus
-#define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the SPI configuration to the default reset state *****/
-void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
-
-/* Initialization and Configuration functions *********************************/
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
-void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
-void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-
-/* Data transfers functions ***************************************************/
-void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
-uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
-
-/* Hardware CRC Calculation functions *****************************************/
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_TransmitCRC(SPI_TypeDef* SPIx);
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
-
-/* DMA transfers management functions *****************************************/
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
-void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F2xx_SPI_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/radio/bootloader/stm32f2xx_gpio.c b/radio/bootloader/stm32f2xx_gpio.c
deleted file mode 100644
index c53371e3d..000000000
--- a/radio/bootloader/stm32f2xx_gpio.c
+++ /dev/null
@@ -1,566 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_gpio.c
- * @author MCD Application Team
- * @version V1.1.2
- * @date 05-March-2012
- * @brief This file provides firmware functions to manage the following
- * functionalities of the GPIO peripheral:
- * - Initialization and Configuration
- * - GPIO Read and Write
- * - GPIO Alternate functions configuration
- *
- * @verbatim
- *
- * ===================================================================
- * How to use this driver
- * ===================================================================
- * 1. Enable the GPIO AHB clock using the following function
- * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
- *
- * 2. Configure the GPIO pin(s) using GPIO_Init()
- * Four possible configuration are available for each pin:
- * - Input: Floating, Pull-up, Pull-down.
- * - Output: Push-Pull (Pull-up, Pull-down or no Pull)
- * Open Drain (Pull-up, Pull-down or no Pull).
- * In output mode, the speed is configurable: 2 MHz, 25 MHz,
- * 50 MHz or 100 MHz.
- * - Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull)
- * Open Drain (Pull-up, Pull-down or no Pull).
- * - Analog: required mode when a pin is to be used as ADC channel
- * or DAC output.
- *
- * 3- Peripherals alternate function:
- * - For ADC and DAC, configure the desired pin in analog mode using
- * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN;
- * - For other peripherals (TIM, USART...):
- * - Connect the pin to the desired peripherals' Alternate
- * Function (AF) using GPIO_PinAFConfig() function
- * - Configure the desired pin in alternate function mode using
- * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
- * - Select the type, pull-up/pull-down and output speed via
- * GPIO_PuPd, GPIO_OType and GPIO_Speed members
- * - Call GPIO_Init() function
- *
- * 4. To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
- *
- * 5. To set/reset the level of a pin configured in output mode use
- * GPIO_SetBits()/GPIO_ResetBits()
- *
- * 6. During and just after reset, the alternate functions are not
- * active and the GPIO pins are configured in input floating mode
- * (except JTAG pins).
- *
- * 7. The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as
- * general-purpose (PC14 and PC15, respectively) when the LSE
- * oscillator is off. The LSE has priority over the GPIO function.
- *
- * 8. The HSE oscillator pins OSC_IN/OSC_OUT can be used as
- * general-purpose PH0 and PH1, respectively, when the HSE
- * oscillator is off. The HSE has priority over the GPIO function.
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2012 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_gpio.h"
-#include "stm32f2xx_rcc.h"
-
-/** @addtogroup STM32F2xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup GPIO
- * @brief GPIO driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup GPIO_Private_Functions
- * @{
- */
-
-/** @defgroup GPIO_Group1 Initialization and Configuration
- * @brief Initialization and Configuration
- *
-@verbatim
- ===============================================================================
- Initialization and Configuration
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the GPIOx peripheral registers to their default reset values.
- * @note By default, The GPIO pins are configured in input floating mode (except JTAG pins).
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
- * @retval None
- */
-void GPIO_DeInit(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- if (GPIOx == GPIOA)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE);
- }
- else if (GPIOx == GPIOB)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE);
- }
- else if (GPIOx == GPIOC)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE);
- }
- else if (GPIOx == GPIOD)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE);
- }
- else if (GPIOx == GPIOE)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE);
- }
- else if (GPIOx == GPIOF)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE);
- }
- else if (GPIOx == GPIOG)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE);
- }
- else if (GPIOx == GPIOH)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE);
- }
- else
- {
- if (GPIOx == GPIOI)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
- * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains
- * the configuration information for the specified GPIO peripheral.
- * @retval None
- */
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
-{
- uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
- assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
- assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
-
- /* -------------------------Configure the port pins---------------- */
- /*-- GPIO Mode Configuration --*/
- for (pinpos = 0x00; pinpos < 0x10; pinpos++)
- {
- pos = ((uint32_t)0x01) << pinpos;
- /* Get the port pins position */
- currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
-
- if (currentpin == pos)
- {
- GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
- GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
-
- if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
- {
- /* Check Speed mode parameters */
- assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
-
- /* Speed mode configuration */
- GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
- GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
-
- /* Check Output mode parameters */
- assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
-
- /* Output mode configuration*/
- GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ;
- GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
- }
-
- /* Pull-up Pull down resistor configuration*/
- GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
- GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
- }
- }
-}
-
-/**
- * @brief Fills each GPIO_InitStruct member with its default value.
- * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
-{
- /* Reset GPIO init structure parameters values */
- GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
- GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
- GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
- GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
-}
-
-/**
- * @brief Locks GPIO Pins configuration registers.
- * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
- * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
- * @note The configuration of the locked GPIO pins can no longer be modified
- * until the next reset.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bit to be locked.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
- * @retval None
- */
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- __IO uint32_t tmp = 0x00010000;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- tmp |= GPIO_Pin;
- /* Set LCKK bit */
- GPIOx->LCKR = tmp;
- /* Reset LCKK bit */
- GPIOx->LCKR = GPIO_Pin;
- /* Set LCKK bit */
- GPIOx->LCKR = tmp;
- /* Read LCKK bit*/
- tmp = GPIOx->LCKR;
- /* Read LCKK bit*/
- tmp = GPIOx->LCKR;
-}
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Group2 GPIO Read and Write
- * @brief GPIO Read and Write
- *
-@verbatim
- ===============================================================================
- GPIO Read and Write
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Reads the specified input port pin.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bit to read.
- * This parameter can be GPIO_Pin_x where x can be (0..15).
- * @retval The input port pin value.
- */
-uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- uint8_t bitstatus = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-
- if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
- {
- bitstatus = (uint8_t)Bit_SET;
- }
- else
- {
- bitstatus = (uint8_t)Bit_RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Reads the specified GPIO input data port.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
- * @retval GPIO input data port value.
- */
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- return ((uint16_t)GPIOx->IDR);
-}
-
-/**
- * @brief Reads the specified output data port bit.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bit to read.
- * This parameter can be GPIO_Pin_x where x can be (0..15).
- * @retval The output port pin value.
- */
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- uint8_t bitstatus = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-
- if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
- {
- bitstatus = (uint8_t)Bit_SET;
- }
- else
- {
- bitstatus = (uint8_t)Bit_RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Reads the specified GPIO output data port.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
- * @retval GPIO output data port value.
- */
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- return ((uint16_t)GPIOx->ODR);
-}
-
-/**
- * @brief Sets the selected data port bits.
- * @note This functions uses GPIOx_BSRR register to allow atomic read/modify
- * accesses. In this way, there is no risk of an IRQ occurring between
- * the read and the modify access.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bits to be written.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
- * @retval None
- */
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- GPIOx->BSRRL = GPIO_Pin;
-}
-
-/**
- * @brief Clears the selected data port bits.
- * @note This functions uses GPIOx_BSRR register to allow atomic read/modify
- * accesses. In this way, there is no risk of an IRQ occurring between
- * the read and the modify access.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bits to be written.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
- * @retval None
- */
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- GPIOx->BSRRH = GPIO_Pin;
-}
-
-/**
- * @brief Sets or clears the selected data port bit.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bit to be written.
- * This parameter can be one of GPIO_Pin_x where x can be (0..15).
- * @param BitVal: specifies the value to be written to the selected bit.
- * This parameter can be one of the BitAction enum values:
- * @arg Bit_RESET: to clear the port pin
- * @arg Bit_SET: to set the port pin
- * @retval None
- */
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
- assert_param(IS_GPIO_BIT_ACTION(BitVal));
-
- if (BitVal != Bit_RESET)
- {
- GPIOx->BSRRL = GPIO_Pin;
- }
- else
- {
- GPIOx->BSRRH = GPIO_Pin ;
- }
-}
-
-/**
- * @brief Writes data to the specified GPIO data port.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
- * @param PortVal: specifies the value to be written to the port output data register.
- * @retval None
- */
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- GPIOx->ODR = PortVal;
-}
-
-/**
- * @brief Toggles the specified GPIO pins..
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
- * @param GPIO_Pin: Specifies the pins to be toggled.
- * @retval None
- */
-void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- GPIOx->ODR ^= GPIO_Pin;
-}
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Group3 GPIO Alternate functions configuration function
- * @brief GPIO Alternate functions configuration function
- *
-@verbatim
- ===============================================================================
- GPIO Alternate functions configuration function
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Changes the mapping of the specified pin.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
- * @param GPIO_PinSource: specifies the pin for the Alternate function.
- * This parameter can be GPIO_PinSourcex where x can be (0..15).
- * @param GPIO_AFSelection: selects the pin to used as Alternate function.
- * This parameter can be one of the following values:
- * @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset)
- * @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset)
- * @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset)
- * @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset)
- * @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset)
- * @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1
- * @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1
- * @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2
- * @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2
- * @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2
- * @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3
- * @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3
- * @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3
- * @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3
- * @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4
- * @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4
- * @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4
- * @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5
- * @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5
- * @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6
- * @arg GPIO_AF_USART1: Connect USART1 pins to AF7
- * @arg GPIO_AF_USART2: Connect USART2 pins to AF7
- * @arg GPIO_AF_USART3: Connect USART3 pins to AF7
- * @arg GPIO_AF_UART4: Connect UART4 pins to AF8
- * @arg GPIO_AF_UART5: Connect UART5 pins to AF8
- * @arg GPIO_AF_USART6: Connect USART6 pins to AF8
- * @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9
- * @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9
- * @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9
- * @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9
- * @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9
- * @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10
- * @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10
- * @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11
- * @arg GPIO_AF_FSMC: Connect FSMC pins to AF12
- * @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12
- * @arg GPIO_AF_SDIO: Connect SDIO pins to AF12
- * @arg GPIO_AF_DCMI: Connect DCMI pins to AF13
- * @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15
- * @retval None
- */
-void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
-{
- uint32_t temp = 0x00;
- uint32_t temp_2 = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
- assert_param(IS_GPIO_AF(GPIO_AF));
-
- temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
- GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
- temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
- GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/radio/bootloader/stm32f2xx_rcc.c b/radio/bootloader/stm32f2xx_rcc.c
deleted file mode 100644
index 0376f7f55..000000000
--- a/radio/bootloader/stm32f2xx_rcc.c
+++ /dev/null
@@ -1,1817 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_rcc.c
- * @author MCD Application Team
- * @version V1.1.2
- * @date 05-March-2012
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Reset and clock control (RCC) peripheral:
- * - Internal/external clocks, PLL, CSS and MCO configuration
- * - System, AHB and APB busses clocks configuration
- * - Peripheral clocks configuration
- * - Interrupts and flags management
- *
- * @verbatim
- *
- * ===================================================================
- * RCC specific features
- * ===================================================================
- *
- * After reset the device is running from Internal High Speed oscillator
- * (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
- * and I-Cache are disabled, and all peripherals are off except internal
- * SRAM, Flash and JTAG.
- * - There is no prescaler on High speed (AHB) and Low speed (APB) busses;
- * all peripherals mapped on these busses are running at HSI speed.
- * - The clock for all peripherals is switched off, except the SRAM and FLASH.
- * - All GPIOs are in input floating state, except the JTAG pins which
- * are assigned to be used for debug purpose.
- *
- * Once the device started from reset, the user application has to:
- * - Configure the clock source to be used to drive the System clock
- * (if the application needs higher frequency/performance)
- * - Configure the System clock frequency and Flash settings
- * - Configure the AHB and APB busses prescalers
- * - Enable the clock for the peripheral(s) to be used
- * - Configure the clock source(s) for peripherals which clocks are not
- * derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2012 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_rcc.h"
-
-/** @addtogroup STM32F2xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup RCC
- * @brief RCC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* ------------ RCC registers bit address in the alias region ----------- */
-#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
-/* --- CR Register ---*/
-/* Alias word address of HSION bit */
-#define CR_OFFSET (RCC_OFFSET + 0x00)
-#define HSION_BitNumber 0x00
-#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
-/* Alias word address of CSSON bit */
-#define CSSON_BitNumber 0x13
-#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
-/* Alias word address of PLLON bit */
-#define PLLON_BitNumber 0x18
-#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
-/* Alias word address of PLLI2SON bit */
-#define PLLI2SON_BitNumber 0x1A
-#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
-
-/* --- CFGR Register ---*/
-/* Alias word address of I2SSRC bit */
-#define CFGR_OFFSET (RCC_OFFSET + 0x08)
-#define I2SSRC_BitNumber 0x17
-#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
-
-/* --- BDCR Register ---*/
-/* Alias word address of RTCEN bit */
-#define BDCR_OFFSET (RCC_OFFSET + 0x70)
-#define RTCEN_BitNumber 0x0F
-#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
-/* Alias word address of BDRST bit */
-#define BDRST_BitNumber 0x10
-#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
-/* --- CSR Register ---*/
-/* Alias word address of LSION bit */
-#define CSR_OFFSET (RCC_OFFSET + 0x74)
-#define LSION_BitNumber 0x00
-#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
-/* ---------------------- RCC registers bit mask ------------------------ */
-/* CFGR register bit mask */
-#define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF)
-#define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF)
-
-/* RCC Flag Mask */
-#define FLAG_MASK ((uint8_t)0x1F)
-
-/* CR register byte 3 (Bits[23:16]) base address */
-#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802)
-
-/* CIR register byte 2 (Bits[15:8]) base address */
-#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
-
-/* CIR register byte 3 (Bits[23:16]) base address */
-#define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
-
-/* BDCR register base address */
-#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RCC_Private_Functions
- * @{
- */
-
-/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
- * @brief Internal and external clocks, PLL, CSS and MCO configuration functions
- *
-@verbatim
- ===============================================================================
- Internal/external clocks, PLL, CSS and MCO configuration functions
- ===============================================================================
-
- This section provide functions allowing to configure the internal/external clocks,
- PLLs, CSS and MCO pins.
-
- 1. HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
- the PLL as System clock source.
-
- 2. LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
- clock source.
-
- 3. HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
- through the PLL as System clock source. Can be used also as RTC clock source.
-
- 4. LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
-
- 5. PLL (clocked by HSI or HSE), featuring two different output clocks:
- - The first output is used to generate the high speed system clock (up to 120 MHz)
- - The second output is used to generate the clock for the USB OTG FS (48 MHz),
- the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
-
- 6. PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve
- high-quality audio performance on the I2S interface.
-
- 7. CSS (Clock security system), once enable and if a HSE clock failure occurs
- (HSE used directly or through PLL as System clock source), the System clock
- is automatically switched to HSI and an interrupt is generated if enabled.
- The interrupt is linked to the Cortex-M3 NMI (Non-Maskable Interrupt)
- exception vector.
-
- 8. MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
- clock (through a configurable prescaler) on PA8 pin.
-
- 9. MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
- clock (through a configurable prescaler) on PC9 pin.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Resets the RCC clock configuration to the default reset state.
- * @note The default reset state of the clock configuration is given below:
- * - HSI ON and used as system clock source
- * - HSE, PLL and PLLI2S OFF
- * - AHB, APB1 and APB2 prescaler set to 1.
- * - CSS, MCO1 and MCO2 OFF
- * - All interrupts disabled
- * @note This function doesn't modify the configuration of the
- * - Peripheral clocks
- * - LSI, LSE and RTC clocks
- * @param None
- * @retval None
- */
-void RCC_DeInit(void)
-{
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
-
- /* Reset CFGR register */
- RCC->CFGR = 0x00000000;
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
-
- /* Reset PLLCFGR register */
- RCC->PLLCFGR = 0x24003010;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
-}
-
-/**
- * @brief Configures the External High Speed oscillator (HSE).
- * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
- * software should wait on HSERDY flag to be set indicating that HSE clock
- * is stable and can be used to clock the PLL and/or system clock.
- * @note HSE state can not be changed if it is used directly or through the
- * PLL as system clock. In this case, you have to select another source
- * of the system clock then change the HSE state (ex. disable it).
- * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
- * @note This function reset the CSSON bit, so if the Clock security system(CSS)
- * was previously enabled you have to enable it again after calling this
- * function.
- * @param RCC_HSE: specifies the new state of the HSE.
- * This parameter can be one of the following values:
- * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
- * 6 HSE oscillator clock cycles.
- * @arg RCC_HSE_ON: turn ON the HSE oscillator
- * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
- * @retval None
- */
-void RCC_HSEConfig(uint8_t RCC_HSE)
-{
- /* Check the parameters */
- assert_param(IS_RCC_HSE(RCC_HSE));
-
- /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
- *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF;
-
- /* Set the new HSE configuration -------------------------------------------*/
- *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;
-}
-
-/**
- * @brief Waits for HSE start-up.
- * @note This functions waits on HSERDY flag to be set and return SUCCESS if
- * this flag is set, otherwise returns ERROR if the timeout is reached
- * and this flag is not set. The timeout value is defined by the constant
- * HSE_STARTUP_TIMEOUT in stm32f2xx.h file. You can tailor it depending
- * on the HSE crystal used in your application.
- * @param None
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: HSE oscillator is stable and ready to use
- * - ERROR: HSE oscillator not yet ready
- */
-ErrorStatus RCC_WaitForHSEStartUp(void)
-{
- __IO uint32_t startupcounter = 0;
- ErrorStatus status = ERROR;
- FlagStatus hsestatus = RESET;
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
- startupcounter++;
- } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET));
-
- if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
- {
- status = SUCCESS;
- }
- else
- {
- status = ERROR;
- }
- return (status);
-}
-
-/**
- * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
- * @note The calibration is used to compensate for the variations in voltage
- * and temperature that influence the frequency of the internal HSI RC.
- * @param HSICalibrationValue: specifies the calibration trimming value.
- * This parameter must be a number between 0 and 0x1F.
- * @retval None
- */
-void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
-
- tmpreg = RCC->CR;
-
- /* Clear HSITRIM[4:0] bits */
- tmpreg &= ~RCC_CR_HSITRIM;
-
- /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
- tmpreg |= (uint32_t)HSICalibrationValue << 3;
-
- /* Store the new value */
- RCC->CR = tmpreg;
-}
-
-/**
- * @brief Enables or disables the Internal High Speed oscillator (HSI).
- * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
- * It is used (enabled by hardware) as system clock source after startup
- * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
- * of the HSE used directly or indirectly as system clock (if the Clock
- * Security System CSS is enabled).
- * @note HSI can not be stopped if it is used as system clock source. In this case,
- * you have to select another source of the system clock then stop the HSI.
- * @note After enabling the HSI, the application software should wait on HSIRDY
- * flag to be set indicating that HSI clock is stable and can be used as
- * system clock source.
- * @param NewState: new state of the HSI.
- * This parameter can be: ENABLE or DISABLE.
- * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
- * clock cycles.
- * @retval None
- */
-void RCC_HSICmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the External Low Speed oscillator (LSE).
- * @note As the LSE is in the Backup domain and write access is denied to
- * this domain after reset, you have to enable write access using
- * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
- * (to be done once after reset).
- * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
- * software should wait on LSERDY flag to be set indicating that LSE clock
- * is stable and can be used to clock the RTC.
- * @param RCC_LSE: specifies the new state of the LSE.
- * This parameter can be one of the following values:
- * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
- * 6 LSE oscillator clock cycles.
- * @arg RCC_LSE_ON: turn ON the LSE oscillator
- * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
- * @retval None
- */
-void RCC_LSEConfig(uint8_t RCC_LSE)
-{
- /* Check the parameters */
- assert_param(IS_RCC_LSE(RCC_LSE));
-
- /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
- /* Reset LSEON bit */
- *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
-
- /* Reset LSEBYP bit */
- *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
-
- /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
- switch (RCC_LSE)
- {
- case RCC_LSE_ON:
- /* Set LSEON bit */
- *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
- break;
- case RCC_LSE_Bypass:
- /* Set LSEBYP and LSEON bits */
- *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Enables or disables the Internal Low Speed oscillator (LSI).
- * @note After enabling the LSI, the application software should wait on
- * LSIRDY flag to be set indicating that LSI clock is stable and can
- * be used to clock the IWDG and/or the RTC.
- * @note LSI can not be disabled if the IWDG is running.
- * @param NewState: new state of the LSI.
- * This parameter can be: ENABLE or DISABLE.
- * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
- * clock cycles.
- * @retval None
- */
-void RCC_LSICmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the main PLL clock source, multiplication and division factors.
- * @note This function must be used only when the main PLL is disabled.
- *
- * @param RCC_PLLSource: specifies the PLL entry clock source.
- * This parameter can be one of the following values:
- * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry
- * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry
- * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
- *
- * @param PLLM: specifies the division factor for PLL VCO input clock
- * This parameter must be a number between 0 and 63.
- * @note You have to set the PLLM parameter correctly to ensure that the VCO input
- * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
- * of 2 MHz to limit PLL jitter.
- *
- * @param PLLN: specifies the multiplication factor for PLL VCO output clock
- * This parameter must be a number between 192 and 432.
- * @note You have to set the PLLN parameter correctly to ensure that the VCO
- * output frequency is between 192 and 432 MHz.
- *
- * @param PLLP: specifies the division factor for main system clock (SYSCLK)
- * This parameter must be a number in the range {2, 4, 6, or 8}.
- * @note You have to set the PLLP parameter correctly to not exceed 120 MHz on
- * the System clock frequency.
- *
- * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks
- * This parameter must be a number between 4 and 15.
- * @note If the USB OTG FS is used in your application, you have to set the
- * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
- * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
- * correctly.
- *
- * @retval None
- */
-void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
-{
- /* Check the parameters */
- assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
- assert_param(IS_RCC_PLLM_VALUE(PLLM));
- assert_param(IS_RCC_PLLN_VALUE(PLLN));
- assert_param(IS_RCC_PLLP_VALUE(PLLP));
- assert_param(IS_RCC_PLLQ_VALUE(PLLQ));
-
- RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
- (PLLQ << 24);
-}
-
-/**
- * @brief Enables or disables the main PLL.
- * @note After enabling the main PLL, the application software should wait on
- * PLLRDY flag to be set indicating that PLL clock is stable and can
- * be used as system clock source.
- * @note The main PLL can not be disabled if it is used as system clock source
- * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
- * @param NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_PLLCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the PLLI2S clock multiplication and division factors.
- *
- * @note PLLI2S is available only in Silicon RevisionB and RevisionY.
- * @note This function must be used only when the PLLI2S is disabled.
- * @note PLLI2S clock source is common with the main PLL (configured in
- * RCC_PLLConfig function )
- *
- * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
- * This parameter must be a number between 192 and 432.
- * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
- * output frequency is between 192 and 432 MHz.
- *
- * @param PLLI2SR: specifies the division factor for I2S clock
- * This parameter must be a number between 2 and 7.
- * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
- * on the I2S clock frequency.
- *
- * @retval None
- */
-void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)
-{
- /* Check the parameters */
- assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
- assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR));
-
- RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28);
-}
-
-/**
- * @brief Enables or disables the PLLI2S.
- * @note PLLI2S is available only in RevisionB and RevisionY
- * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
- * @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_PLLI2SCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Enables or disables the Clock Security System.
- * @note If a failure is detected on the HSE oscillator clock, this oscillator
- * is automatically disabled and an interrupt is generated to inform the
- * software about the failure (Clock Security System Interrupt, CSSI),
- * allowing the MCU to perform rescue operations. The CSSI is linked to
- * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
- * @param NewState: new state of the Clock Security System.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Selects the clock source to output on MCO1 pin(PA8).
- * @note PA8 should be configured in alternate function mode.
- * @param RCC_MCO1Source: specifies the clock source to output.
- * This parameter can be one of the following values:
- * @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source
- * @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source
- * @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source
- * @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source
- * @param RCC_MCO1Div: specifies the MCO1 prescaler.
- * This parameter can be one of the following values:
- * @arg RCC_MCO1Div_1: no division applied to MCO1 clock
- * @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock
- * @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock
- * @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock
- * @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock
- * @retval None
- */
-void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source));
- assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div));
-
- tmpreg = RCC->CFGR;
-
- /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */
- tmpreg &= CFGR_MCO1_RESET_MASK;
-
- /* Select MCO1 clock source and prescaler */
- tmpreg |= RCC_MCO1Source | RCC_MCO1Div;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Selects the clock source to output on MCO2 pin(PC9).
- * @note PC9 should be configured in alternate function mode.
- * @param RCC_MCO2Source: specifies the clock source to output.
- * This parameter can be one of the following values:
- * @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source
- * @arg RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source
- * @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source
- * @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source
- * @param RCC_MCO2Div: specifies the MCO2 prescaler.
- * This parameter can be one of the following values:
- * @arg RCC_MCO2Div_1: no division applied to MCO2 clock
- * @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock
- * @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock
- * @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock
- * @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock
- * @retval None
- */
-void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source));
- assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div));
-
- tmpreg = RCC->CFGR;
-
- /* Clear MCO2 and MCO2PRE[2:0] bits */
- tmpreg &= CFGR_MCO2_RESET_MASK;
-
- /* Select MCO2 clock source and prescaler */
- tmpreg |= RCC_MCO2Source | RCC_MCO2Div;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions
- * @brief System, AHB and APB busses clocks configuration functions
- *
-@verbatim
- ===============================================================================
- System, AHB and APB busses clocks configuration functions
- ===============================================================================
-
- This section provide functions allowing to configure the System, AHB, APB1 and
- APB2 busses clocks.
-
- 1. Several clock sources can be used to drive the System clock (SYSCLK): HSI,
- HSE and PLL.
- The AHB clock (HCLK) is derived from System clock through configurable prescaler
- and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA, GPIO...).
- APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through
- configurable prescalers and used to clock the peripherals mapped on these busses.
- You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
-
-@note All the peripheral clocks are derived from the System clock (SYSCLK) except:
- - I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
- from an external clock mapped on the I2S_CKIN pin.
- You have to use RCC_I2SCLKConfig() function to configure this clock.
- - RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
- divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd()
- functions to configure this clock.
- - USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
- to work correctly, while the SDIO require a frequency equal or lower than
- to 48. This clock is derived of the main PLL through PLLQ divider.
- - IWDG clock which is always the LSI clock.
-
- 2. The maximum frequency of the SYSCLK and HCLK is 120 MHz, PCLK2 60 MHz and PCLK1 30 MHz.
- Depending on the device voltage range, the maximum frequency should be
- adapted accordingly:
- +-------------------------------------------------------------------------------------+
- | Latency | HCLK clock frequency (MHz) |
- | |---------------------------------------------------------------------|
- | | voltage range | voltage range | voltage range | voltage range |
- | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
- |---------------|----------------|----------------|-----------------|-----------------|
- |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |4WS(5CPU cycle)| NA |96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 108 |80 < HCLK <= 96 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |6WS(7CPU cycle)| NA | NA |108 < HCLK <= 120|96 < HCLK <= 112 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |7WS(8CPU cycle)| NA | NA | NA |112 < HCLK <= 120|
- +-------------------------------------------------------------------------------------+
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the system clock (SYSCLK).
- * @note The HSI is used (enabled by hardware) as system clock source after
- * startup from Reset, wake-up from STOP and STANDBY mode, or in case
- * of failure of the HSE used directly or indirectly as system clock
- * (if the Clock Security System CSS is enabled).
- * @note A switch from one clock source to another occurs only if the target
- * clock source is ready (clock stable after startup delay or PLL locked).
- * If a clock source which is not yet ready is selected, the switch will
- * occur when the clock source will be ready.
- * You can use RCC_GetSYSCLKSource() function to know which clock is
- * currently used as system clock source.
- * @param RCC_SYSCLKSource: specifies the clock source used as system clock.
- * This parameter can be one of the following values:
- * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source
- * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source
- * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
- * @retval None
- */
-void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
-
- tmpreg = RCC->CFGR;
-
- /* Clear SW[1:0] bits */
- tmpreg &= ~RCC_CFGR_SW;
-
- /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
- tmpreg |= RCC_SYSCLKSource;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Returns the clock source used as system clock.
- * @param None
- * @retval The clock source used as system clock. The returned value can be one
- * of the following:
- * - 0x00: HSI used as system clock
- * - 0x04: HSE used as system clock
- * - 0x08: PLL used as system clock
- */
-uint8_t RCC_GetSYSCLKSource(void)
-{
- return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
-}
-
-/**
- * @brief Configures the AHB clock (HCLK).
- * @note Depending on the device voltage range, the software has to set correctly
- * these bits to ensure that HCLK not exceed the maximum allowed frequency
- * (for more details refer to section above
- * "CPU, AHB and APB busses clocks configuration functions")
- * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
- * the system clock (SYSCLK).
- * This parameter can be one of the following values:
- * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
- * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
- * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
- * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
- * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
- * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
- * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
- * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
- * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
- * @retval None
- */
-void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_HCLK(RCC_SYSCLK));
-
- tmpreg = RCC->CFGR;
-
- /* Clear HPRE[3:0] bits */
- tmpreg &= ~RCC_CFGR_HPRE;
-
- /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
- tmpreg |= RCC_SYSCLK;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-
-/**
- * @brief Configures the Low Speed APB clock (PCLK1).
- * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
- * the AHB clock (HCLK).
- * This parameter can be one of the following values:
- * @arg RCC_HCLK_Div1: APB1 clock = HCLK
- * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
- * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
- * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
- * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
- * @retval None
- */
-void RCC_PCLK1Config(uint32_t RCC_HCLK)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PCLK(RCC_HCLK));
-
- tmpreg = RCC->CFGR;
-
- /* Clear PPRE1[2:0] bits */
- tmpreg &= ~RCC_CFGR_PPRE1;
-
- /* Set PPRE1[2:0] bits according to RCC_HCLK value */
- tmpreg |= RCC_HCLK;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Configures the High Speed APB clock (PCLK2).
- * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
- * the AHB clock (HCLK).
- * This parameter can be one of the following values:
- * @arg RCC_HCLK_Div1: APB2 clock = HCLK
- * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
- * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
- * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
- * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
- * @retval None
- */
-void RCC_PCLK2Config(uint32_t RCC_HCLK)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PCLK(RCC_HCLK));
-
- tmpreg = RCC->CFGR;
-
- /* Clear PPRE2[2:0] bits */
- tmpreg &= ~RCC_CFGR_PPRE2;
-
- /* Set PPRE2[2:0] bits according to RCC_HCLK value */
- tmpreg |= RCC_HCLK << 3;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK,
- * PCLK1 and PCLK2.
- *
- * @note The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
- * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
- * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.
- * @note (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value
- * 16 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- * @note (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value
- * 25 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * @note The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
- * the clocks frequencies.
- *
- * @note This function can be used by the user application to compute the
- * baudrate for the communication peripherals or configure other parameters.
- * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
- * must be called to update the structure's field. Otherwise, any
- * configuration based on this function will be incorrect.
- *
- * @retval None
- */
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
-{
- uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case 0x00: /* HSI used as system clock source */
- RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
- break;
- case 0x04: /* HSE used as system clock source */
- RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
- break;
- case 0x08: /* PLL used as system clock source */
-
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
- SYSCLK = PLL_VCO / PLLP
- */
- pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
- pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-
- if (pllsource != 0)
- {
- /* HSE used as PLL clock source */
- pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
- else
- {
- /* HSI used as PLL clock source */
- pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
-
- pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
- RCC_Clocks->SYSCLK_Frequency = pllvco/pllp;
- break;
- default:
- RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
- break;
- }
- /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/
-
- /* Get HCLK prescaler */
- tmp = RCC->CFGR & RCC_CFGR_HPRE;
- tmp = tmp >> 4;
- presc = APBAHBPrescTable[tmp];
- /* HCLK clock frequency */
- RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
-
- /* Get PCLK1 prescaler */
- tmp = RCC->CFGR & RCC_CFGR_PPRE1;
- tmp = tmp >> 10;
- presc = APBAHBPrescTable[tmp];
- /* PCLK1 clock frequency */
- RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
-
- /* Get PCLK2 prescaler */
- tmp = RCC->CFGR & RCC_CFGR_PPRE2;
- tmp = tmp >> 13;
- presc = APBAHBPrescTable[tmp];
- /* PCLK2 clock frequency */
- RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Group3 Peripheral clocks configuration functions
- * @brief Peripheral clocks configuration functions
- *
-@verbatim
- ===============================================================================
- Peripheral clocks configuration functions
- ===============================================================================
-
- This section provide functions allowing to configure the Peripheral clocks.
-
- 1. The RTC clock which is derived from the LSI, LSE or HSE clock divided by 2 to 31.
-
- 2. After restart from Reset or wakeup from STANDBY, all peripherals are off
- except internal SRAM, Flash and JTAG. Before to start using a peripheral you
- have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd()
- , RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.
-
- 3. To reset the peripherals configuration (to the default state after device reset)
- you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and
- RCC_APB1PeriphResetCmd() functions.
-
- 4. To further reduce power consumption in SLEEP mode the peripheral clocks can
- be disabled prior to executing the WFI or WFE instructions. You can do this
- using RCC_AHBPeriphClockLPModeCmd(), RCC_APB2PeriphClockLPModeCmd() and
- RCC_APB1PeriphClockLPModeCmd() functions.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the RTC clock (RTCCLK).
- * @note As the RTC clock configuration bits are in the Backup domain and write
- * access is denied to this domain after reset, you have to enable write
- * access using PWR_BackupAccessCmd(ENABLE) function before to configure
- * the RTC clock source (to be done once after reset).
- * @note Once the RTC clock is configured it can't be changed unless the
- * Backup domain is reset using RCC_BackupResetCmd() function, or by
- * a Power On Reset (POR).
- *
- * @param RCC_RTCCLKSource: specifies the RTC clock source.
- * This parameter can be one of the following values:
- * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
- * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
- * @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected
- * as RTC clock, where x:[2,31]
- *
- * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
- * work in STOP and STANDBY modes, and can be used as wakeup source.
- * However, when the HSE clock is used as RTC clock source, the RTC
- * cannot be used in STOP and STANDBY modes.
- * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
- * RTC clock source).
- *
- * @retval None
- */
-void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
-
- if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300)
- { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */
- tmpreg = RCC->CFGR;
-
- /* Clear RTCPRE[4:0] bits */
- tmpreg &= ~RCC_CFGR_RTCPRE;
-
- /* Configure HSE division factor for RTC clock */
- tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF);
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
- }
-
- /* Select the RTC clock source */
- RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF);
-}
-
-/**
- * @brief Enables or disables the RTC clock.
- * @note This function must be used only after the RTC clock source was selected
- * using the RCC_RTCCLKConfig function.
- * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_RTCCLKCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Forces or releases the Backup domain reset.
- * @note This function resets the RTC peripheral (including the backup registers)
- * and the RTC clock source selection in RCC_CSR register.
- * @note The BKPSRAM is not affected by this reset.
- * @param NewState: new state of the Backup domain reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_BackupResetCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the I2S clock source (I2SCLK).
- *
- * @note This function must be called before enabling the I2S APB clock.
- * @note This function applies only to Silicon RevisionB and RevisionY.
- *
- * @param RCC_I2SCLKSource: specifies the I2S clock source.
- * This parameter can be one of the following values:
- * @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source
- * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin
- * used as I2S clock source
- * @retval None
- */
-void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
-{
- /* Check the parameters */
- assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
-
- *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource;
-}
-
-/**
- * @brief Enables or disables the AHB1 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB1Periph_GPIOA: GPIOA clock
- * @arg RCC_AHB1Periph_GPIOB: GPIOB clock
- * @arg RCC_AHB1Periph_GPIOC: GPIOC clock
- * @arg RCC_AHB1Periph_GPIOD: GPIOD clock
- * @arg RCC_AHB1Periph_GPIOE: GPIOE clock
- * @arg RCC_AHB1Periph_GPIOF: GPIOF clock
- * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
- * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
- * @arg RCC_AHB1Periph_GPIOI: GPIOI clock
- * @arg RCC_AHB1Periph_CRC: CRC clock
- * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
- * @arg RCC_AHB1Periph_DMA1: DMA1 clock
- * @arg RCC_AHB1Periph_DMA2: DMA2 clock
- * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
- * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
- * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
- * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
- * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
- * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph));
-
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->AHB1ENR |= RCC_AHB1Periph;
- }
- else
- {
- RCC->AHB1ENR &= ~RCC_AHB1Periph;
- }
-}
-
-/**
- * @brief Enables or disables the AHB2 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB2Periph_DCMI: DCMI clock
- * @arg RCC_AHB2Periph_CRYP: CRYP clock
- * @arg RCC_AHB2Periph_HASH: HASH clock
- * @arg RCC_AHB2Periph_RNG: RNG clock
- * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHB2ENR |= RCC_AHB2Periph;
- }
- else
- {
- RCC->AHB2ENR &= ~RCC_AHB2Periph;
- }
-}
-
-/**
- * @brief Enables or disables the AHB3 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
- * This parameter must be: RCC_AHB3Periph_FSMC
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHB3ENR |= RCC_AHB3Periph;
- }
- else
- {
- RCC->AHB3ENR &= ~RCC_AHB3Periph;
- }
-}
-
-/**
- * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB1Periph_TIM2: TIM2 clock
- * @arg RCC_APB1Periph_TIM3: TIM3 clock
- * @arg RCC_APB1Periph_TIM4: TIM4 clock
- * @arg RCC_APB1Periph_TIM5: TIM5 clock
- * @arg RCC_APB1Periph_TIM6: TIM6 clock
- * @arg RCC_APB1Periph_TIM7: TIM7 clock
- * @arg RCC_APB1Periph_TIM12: TIM12 clock
- * @arg RCC_APB1Periph_TIM13: TIM13 clock
- * @arg RCC_APB1Periph_TIM14: TIM14 clock
- * @arg RCC_APB1Periph_WWDG: WWDG clock
- * @arg RCC_APB1Periph_SPI2: SPI2 clock
- * @arg RCC_APB1Periph_SPI3: SPI3 clock
- * @arg RCC_APB1Periph_USART2: USART2 clock
- * @arg RCC_APB1Periph_USART3: USART3 clock
- * @arg RCC_APB1Periph_UART4: UART4 clock
- * @arg RCC_APB1Periph_UART5: UART5 clock
- * @arg RCC_APB1Periph_I2C1: I2C1 clock
- * @arg RCC_APB1Periph_I2C2: I2C2 clock
- * @arg RCC_APB1Periph_I2C3: I2C3 clock
- * @arg RCC_APB1Periph_CAN1: CAN1 clock
- * @arg RCC_APB1Periph_CAN2: CAN2 clock
- * @arg RCC_APB1Periph_PWR: PWR clock
- * @arg RCC_APB1Periph_DAC: DAC clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB1ENR |= RCC_APB1Periph;
- }
- else
- {
- RCC->APB1ENR &= ~RCC_APB1Periph;
- }
-}
-
-/**
- * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB2Periph_TIM1: TIM1 clock
- * @arg RCC_APB2Periph_TIM8: TIM8 clock
- * @arg RCC_APB2Periph_USART1: USART1 clock
- * @arg RCC_APB2Periph_USART6: USART6 clock
- * @arg RCC_APB2Periph_ADC1: ADC1 clock
- * @arg RCC_APB2Periph_ADC2: ADC2 clock
- * @arg RCC_APB2Periph_ADC3: ADC3 clock
- * @arg RCC_APB2Periph_SDIO: SDIO clock
- * @arg RCC_APB2Periph_SPI1: SPI1 clock
- * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
- * @arg RCC_APB2Periph_TIM9: TIM9 clock
- * @arg RCC_APB2Periph_TIM10: TIM10 clock
- * @arg RCC_APB2Periph_TIM11: TIM11 clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB2ENR |= RCC_APB2Periph;
- }
- else
- {
- RCC->APB2ENR &= ~RCC_APB2Periph;
- }
-}
-
-/**
- * @brief Forces or releases AHB1 peripheral reset.
- * @param RCC_AHB1Periph: specifies the AHB1 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB1Periph_GPIOA: GPIOA clock
- * @arg RCC_AHB1Periph_GPIOB: GPIOB clock
- * @arg RCC_AHB1Periph_GPIOC: GPIOC clock
- * @arg RCC_AHB1Periph_GPIOD: GPIOD clock
- * @arg RCC_AHB1Periph_GPIOE: GPIOE clock
- * @arg RCC_AHB1Periph_GPIOF: GPIOF clock
- * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
- * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
- * @arg RCC_AHB1Periph_GPIOI: GPIOI clock
- * @arg RCC_AHB1Periph_CRC: CRC clock
- * @arg RCC_AHB1Periph_DMA1: DMA1 clock
- * @arg RCC_AHB1Periph_DMA2: DMA2 clock
- * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
- * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
- *
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHB1RSTR |= RCC_AHB1Periph;
- }
- else
- {
- RCC->AHB1RSTR &= ~RCC_AHB1Periph;
- }
-}
-
-/**
- * @brief Forces or releases AHB2 peripheral reset.
- * @param RCC_AHB2Periph: specifies the AHB2 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB2Periph_DCMI: DCMI clock
- * @arg RCC_AHB2Periph_CRYP: CRYP clock
- * @arg RCC_AHB2Periph_HASH: HASH clock
- * @arg RCC_AHB2Periph_RNG: RNG clock
- * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHB2RSTR |= RCC_AHB2Periph;
- }
- else
- {
- RCC->AHB2RSTR &= ~RCC_AHB2Periph;
- }
-}
-
-/**
- * @brief Forces or releases AHB3 peripheral reset.
- * @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset.
- * This parameter must be: RCC_AHB3Periph_FSMC
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHB3RSTR |= RCC_AHB3Periph;
- }
- else
- {
- RCC->AHB3RSTR &= ~RCC_AHB3Periph;
- }
-}
-
-/**
- * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
- * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB1Periph_TIM2: TIM2 clock
- * @arg RCC_APB1Periph_TIM3: TIM3 clock
- * @arg RCC_APB1Periph_TIM4: TIM4 clock
- * @arg RCC_APB1Periph_TIM5: TIM5 clock
- * @arg RCC_APB1Periph_TIM6: TIM6 clock
- * @arg RCC_APB1Periph_TIM7: TIM7 clock
- * @arg RCC_APB1Periph_TIM12: TIM12 clock
- * @arg RCC_APB1Periph_TIM13: TIM13 clock
- * @arg RCC_APB1Periph_TIM14: TIM14 clock
- * @arg RCC_APB1Periph_WWDG: WWDG clock
- * @arg RCC_APB1Periph_SPI2: SPI2 clock
- * @arg RCC_APB1Periph_SPI3: SPI3 clock
- * @arg RCC_APB1Periph_USART2: USART2 clock
- * @arg RCC_APB1Periph_USART3: USART3 clock
- * @arg RCC_APB1Periph_UART4: UART4 clock
- * @arg RCC_APB1Periph_UART5: UART5 clock
- * @arg RCC_APB1Periph_I2C1: I2C1 clock
- * @arg RCC_APB1Periph_I2C2: I2C2 clock
- * @arg RCC_APB1Periph_I2C3: I2C3 clock
- * @arg RCC_APB1Periph_CAN1: CAN1 clock
- * @arg RCC_APB1Periph_CAN2: CAN2 clock
- * @arg RCC_APB1Periph_PWR: PWR clock
- * @arg RCC_APB1Periph_DAC: DAC clock
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->APB1RSTR |= RCC_APB1Periph;
- }
- else
- {
- RCC->APB1RSTR &= ~RCC_APB1Periph;
- }
-}
-
-/**
- * @brief Forces or releases High Speed APB (APB2) peripheral reset.
- * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB2Periph_TIM1: TIM1 clock
- * @arg RCC_APB2Periph_TIM8: TIM8 clock
- * @arg RCC_APB2Periph_USART1: USART1 clock
- * @arg RCC_APB2Periph_USART6: USART6 clock
- * @arg RCC_APB2Periph_ADC1: ADC1 clock
- * @arg RCC_APB2Periph_ADC2: ADC2 clock
- * @arg RCC_APB2Periph_ADC3: ADC3 clock
- * @arg RCC_APB2Periph_SDIO: SDIO clock
- * @arg RCC_APB2Periph_SPI1: SPI1 clock
- * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
- * @arg RCC_APB2Periph_TIM9: TIM9 clock
- * @arg RCC_APB2Periph_TIM10: TIM10 clock
- * @arg RCC_APB2Periph_TIM11: TIM11 clock
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->APB2RSTR |= RCC_APB2Periph;
- }
- else
- {
- RCC->APB2RSTR &= ~RCC_APB2Periph;
- }
-}
-
-/**
- * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB1Periph_GPIOA: GPIOA clock
- * @arg RCC_AHB1Periph_GPIOB: GPIOB clock
- * @arg RCC_AHB1Periph_GPIOC: GPIOC clock
- * @arg RCC_AHB1Periph_GPIOD: GPIOD clock
- * @arg RCC_AHB1Periph_GPIOE: GPIOE clock
- * @arg RCC_AHB1Periph_GPIOF: GPIOF clock
- * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
- * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
- * @arg RCC_AHB1Periph_GPIOI: GPIOI clock
- * @arg RCC_AHB1Periph_CRC: CRC clock
- * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
- * @arg RCC_AHB1Periph_DMA1: DMA1 clock
- * @arg RCC_AHB1Periph_DMA2: DMA2 clock
- * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
- * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
- * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
- * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
- * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
- * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->AHB1LPENR |= RCC_AHB1Periph;
- }
- else
- {
- RCC->AHB1LPENR &= ~RCC_AHB1Periph;
- }
-}
-
-/**
- * @brief Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB2Periph_DCMI: DCMI clock
- * @arg RCC_AHB2Periph_CRYP: CRYP clock
- * @arg RCC_AHB2Periph_HASH: HASH clock
- * @arg RCC_AHB2Periph_RNG: RNG clock
- * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->AHB2LPENR |= RCC_AHB2Periph;
- }
- else
- {
- RCC->AHB2LPENR &= ~RCC_AHB2Periph;
- }
-}
-
-/**
- * @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
- * This parameter must be: RCC_AHB3Periph_FSMC
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->AHB3LPENR |= RCC_AHB3Periph;
- }
- else
- {
- RCC->AHB3LPENR &= ~RCC_AHB3Periph;
- }
-}
-
-/**
- * @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB1Periph_TIM2: TIM2 clock
- * @arg RCC_APB1Periph_TIM3: TIM3 clock
- * @arg RCC_APB1Periph_TIM4: TIM4 clock
- * @arg RCC_APB1Periph_TIM5: TIM5 clock
- * @arg RCC_APB1Periph_TIM6: TIM6 clock
- * @arg RCC_APB1Periph_TIM7: TIM7 clock
- * @arg RCC_APB1Periph_TIM12: TIM12 clock
- * @arg RCC_APB1Periph_TIM13: TIM13 clock
- * @arg RCC_APB1Periph_TIM14: TIM14 clock
- * @arg RCC_APB1Periph_WWDG: WWDG clock
- * @arg RCC_APB1Periph_SPI2: SPI2 clock
- * @arg RCC_APB1Periph_SPI3: SPI3 clock
- * @arg RCC_APB1Periph_USART2: USART2 clock
- * @arg RCC_APB1Periph_USART3: USART3 clock
- * @arg RCC_APB1Periph_UART4: UART4 clock
- * @arg RCC_APB1Periph_UART5: UART5 clock
- * @arg RCC_APB1Periph_I2C1: I2C1 clock
- * @arg RCC_APB1Periph_I2C2: I2C2 clock
- * @arg RCC_APB1Periph_I2C3: I2C3 clock
- * @arg RCC_APB1Periph_CAN1: CAN1 clock
- * @arg RCC_APB1Periph_CAN2: CAN2 clock
- * @arg RCC_APB1Periph_PWR: PWR clock
- * @arg RCC_APB1Periph_DAC: DAC clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->APB1LPENR |= RCC_APB1Periph;
- }
- else
- {
- RCC->APB1LPENR &= ~RCC_APB1Periph;
- }
-}
-
-/**
- * @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB2Periph_TIM1: TIM1 clock
- * @arg RCC_APB2Periph_TIM8: TIM8 clock
- * @arg RCC_APB2Periph_USART1: USART1 clock
- * @arg RCC_APB2Periph_USART6: USART6 clock
- * @arg RCC_APB2Periph_ADC1: ADC1 clock
- * @arg RCC_APB2Periph_ADC2: ADC2 clock
- * @arg RCC_APB2Periph_ADC3: ADC3 clock
- * @arg RCC_APB2Periph_SDIO: SDIO clock
- * @arg RCC_APB2Periph_SPI1: SPI1 clock
- * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
- * @arg RCC_APB2Periph_TIM9: TIM9 clock
- * @arg RCC_APB2Periph_TIM10: TIM10 clock
- * @arg RCC_APB2Periph_TIM11: TIM11 clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->APB2LPENR |= RCC_APB2Periph;
- }
- else
- {
- RCC->APB2LPENR &= ~RCC_APB2Periph;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Group4 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- Interrupts and flags management functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified RCC interrupts.
- * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_PLLRDY: main PLL ready interrupt
- * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
- * @param NewState: new state of the specified RCC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_IT(RCC_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */
- *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
- }
- else
- {
- /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */
- *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified RCC flag is set or not.
- * @param RCC_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
- * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
- * @arg RCC_FLAG_PLLRDY: main PLL clock ready
- * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready
- * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
- * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
- * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset
- * @arg RCC_FLAG_PINRST: Pin reset
- * @arg RCC_FLAG_PORRST: POR/PDR reset
- * @arg RCC_FLAG_SFTRST: Software reset
- * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
- * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
- * @arg RCC_FLAG_LPWRRST: Low Power reset
- * @retval The new state of RCC_FLAG (SET or RESET).
- */
-FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
-{
- uint32_t tmp = 0;
- uint32_t statusreg = 0;
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_RCC_FLAG(RCC_FLAG));
-
- /* Get the RCC register index */
- tmp = RCC_FLAG >> 5;
- if (tmp == 1) /* The flag to check is in CR register */
- {
- statusreg = RCC->CR;
- }
- else if (tmp == 2) /* The flag to check is in BDCR register */
- {
- statusreg = RCC->BDCR;
- }
- else /* The flag to check is in CSR register */
- {
- statusreg = RCC->CSR;
- }
-
- /* Get the flag position */
- tmp = RCC_FLAG & FLAG_MASK;
- if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the flag status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the RCC reset flags.
- * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
- * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
- * @param None
- * @retval None
- */
-void RCC_ClearFlag(void)
-{
- /* Set RMVF bit to clear the reset flags */
- RCC->CSR |= RCC_CSR_RMVF;
-}
-
-/**
- * @brief Checks whether the specified RCC interrupt has occurred or not.
- * @param RCC_IT: specifies the RCC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_PLLRDY: main PLL ready interrupt
- * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
- * @arg RCC_IT_CSS: Clock Security System interrupt
- * @retval The new state of RCC_IT (SET or RESET).
- */
-ITStatus RCC_GetITStatus(uint8_t RCC_IT)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_RCC_GET_IT(RCC_IT));
-
- /* Check the status of the specified RCC interrupt */
- if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the RCC_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the RCC's interrupt pending bits.
- * @param RCC_IT: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_PLLRDY: main PLL ready interrupt
- * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
- * @arg RCC_IT_CSS: Clock Security System interrupt
- * @retval None
- */
-void RCC_ClearITPendingBit(uint8_t RCC_IT)
-{
- /* Check the parameters */
- assert_param(IS_RCC_CLEAR_IT(RCC_IT));
-
- /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
- pending bits */
- *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/radio/bootloader/stm32f2xx_spi.c b/radio/bootloader/stm32f2xx_spi.c
deleted file mode 100644
index de0bc99a2..000000000
--- a/radio/bootloader/stm32f2xx_spi.c
+++ /dev/null
@@ -1,1185 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_spi.c
- * @author MCD Application Team
- * @version V1.1.2
- * @date 05-March-2012
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Serial peripheral interface (SPI):
- * - Initialization and Configuration
- * - Data transfers functions
- * - Hardware CRC Calculation
- * - DMA transfers management
- * - Interrupts and flags management
- *
- * @verbatim
- *
- *
- * ===================================================================
- * How to use this driver
- * ===================================================================
- * 1. Enable peripheral clock using the following functions
- * RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) for SPI1
- * RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) for SPI2
- * RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI3.
- *
- * 2. Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHB1PeriphClockCmd()
- * function.
- * In I2S mode, if an external clock source is used then the I2S CKIN pin GPIO
- * clock should also be enabled.
- *
- * 3. Peripherals alternate function:
- * - Connect the pin to the desired peripherals' Alternate
- * Function (AF) using GPIO_PinAFConfig() function
- * - Configure the desired pin in alternate function by:
- * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
- * - Select the type, pull-up/pull-down and output speed via
- * GPIO_PuPd, GPIO_OType and GPIO_Speed members
- * - Call GPIO_Init() function
- * In I2S mode, if an external clock source is used then the I2S CKIN pin
- * should be also configured in Alternate function Push-pull pull-up mode.
- *
- * 4. Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave
- * Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
- * function.
- * In I2S mode, program the Mode, Standard, Data Format, MCLK Output, Audio
- * frequency and Polarity using I2S_Init() function.
- * For I2S mode, make sure that either:
- * - I2S PLL is configured using the functions RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S),
- * RCC_PLLI2SCmd(ENABLE) and RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY).
- * or
- * - External clock source is configured using the function
- * RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly the define constant
- * I2S_EXTERNAL_CLOCK_VAL in the stm32f2xx_conf.h file.
- *
- * 5. Enable the NVIC and the corresponding interrupt using the function
- * SPI_ITConfig() if you need to use interrupt mode.
- *
- * 6. When using the DMA mode
- * - Configure the DMA using DMA_Init() function
- * - Active the needed channel Request using SPI_I2S_DMACmd() function
- *
- * 7. Enable the SPI using the SPI_Cmd() function or enable the I2S using
- * I2S_Cmd().
- *
- * 8. Enable the DMA using the DMA_Cmd() function when using DMA mode.
- *
- * 9. Optionally, you can enable/configure the following parameters without
- * re-initialization (i.e there is no need to call again SPI_Init() function):
- * - When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)
- * is programmed as Data direction parameter using the SPI_Init() function
- * it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx
- * using the SPI_BiDirectionalLineConfig() function.
- * - When SPI_NSS_Soft is selected as Slave Select Management parameter
- * using the SPI_Init() function it can be possible to manage the
- * NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.
- * - Reconfigure the data size using the SPI_DataSizeConfig() function
- * - Enable or disable the SS output using the SPI_SSOutputCmd() function
- *
- * 10. To use the CRC Hardware calculation feature refer to the Peripheral
- * CRC hardware Calculation subsection.
- *
- *
- * @note This driver supports only the I2S clock scheme available in Silicon
- * RevisionB and RevisionY.
- *
- * @note In I2S mode: if an external clock is used as source clock for the I2S,
- * then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f2xx_conf.h should
- * be enabled and set to the value of the source clock frequency (in Hz).
- *
- * @note In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd()
- * just after calling the function SPI_Init().
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2012 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include
-#include "stm32f2xx.h"
-#include "stm32f2xx_spi.h"
-#include "stm32f2xx_rcc.h"
-
-/** @addtogroup STM32F2xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup SPI
- * @brief SPI driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* SPI registers Masks */
-#define CR1_CLEAR_MASK ((uint16_t)0x3040)
-#define I2SCFGR_CLEAR_MASK ((uint16_t)0xF040)
-
-/* RCC PLLs masks */
-#define PLLCFGR_PPLR_MASK ((uint32_t)0x70000000)
-#define PLLCFGR_PPLN_MASK ((uint32_t)0x00007FC0)
-
-#define SPI_CR2_FRF ((uint16_t)0x0010)
-#define SPI_SR_TIFRFE ((uint16_t)0x0100)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SPI_Private_Functions
- * @{
- */
-
-/** @defgroup SPI_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- Initialization and Configuration functions
- ===============================================================================
-
- This section provides a set of functions allowing to initialize the SPI Direction,
- SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud
- Rate Prescaler, SPI First Bit and SPI CRC Polynomial.
-
- The SPI_Init() function follows the SPI configuration procedures for Master mode
- and Slave mode (details for these procedures are available in reference manual
- (RM0033)).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitialize the SPIx peripheral registers to their default reset values.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
- * in SPI mode or 2 or 3 in I2S mode.
- * @retval None
- */
-void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- if (SPIx == SPI1)
- {
- /* Enable SPI1 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
- /* Release SPI1 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
- }
- else if (SPIx == SPI2)
- {
- /* Enable SPI2 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
- /* Release SPI2 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
- }
- else
- {
- if (SPIx == SPI3)
- {
- /* Enable SPI3 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
- /* Release SPI3 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the SPIx peripheral according to the specified
- * parameters in the SPI_InitStruct.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
- * contains the configuration information for the specified SPI peripheral.
- * @retval None
- */
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
-{
- uint16_t tmpreg = 0;
-
- /* check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Check the SPI parameters */
- assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
- assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
- assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
- assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
- assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
- assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
- assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
- assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
- assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
-
-/*---------------------------- SPIx CR1 Configuration ------------------------*/
- /* Get the SPIx CR1 value */
- tmpreg = SPIx->CR1;
- /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
- tmpreg &= CR1_CLEAR_MASK;
- /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
- master/salve mode, CPOL and CPHA */
- /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
- /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
- /* Set LSBFirst bit according to SPI_FirstBit value */
- /* Set BR bits according to SPI_BaudRatePrescaler value */
- /* Set CPOL bit according to SPI_CPOL value */
- /* Set CPHA bit according to SPI_CPHA value */
- tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
- SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
- SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
- SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
- /* Write to SPIx CR1 */
- SPIx->CR1 = tmpreg;
-
- /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
- SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD);
-/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
- /* Write to SPIx CRCPOLY */
- SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
-}
-
-/**
- * @brief Initializes the SPIx peripheral according to the specified
- * parameters in the I2S_InitStruct.
- * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (configured in I2S mode).
- * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
- * contains the configuration information for the specified SPI peripheral
- * configured in I2S mode.
- *
- * @note The function calculates the optimal prescaler needed to obtain the most
- * accurate audio frequency (depending on the I2S clock source, the PLL values
- * and the product configuration). But in case the prescaler value is greater
- * than 511, the default value (0x02) will be configured instead.
- *
- * @note if an external clock is used as source clock for the I2S, then the define
- * I2S_EXTERNAL_CLOCK_VAL in file stm32f2xx_conf.h should be enabled and set
- * to the value of the the source clock frequency (in Hz).
- *
- * @retval None
- */
-void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
-{
- uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
- uint32_t tmp = 0, i2sclk = 0;
-#ifndef I2S_EXTERNAL_CLOCK_VAL
- uint32_t pllm = 0, plln = 0, pllr = 0;
-#endif /* I2S_EXTERNAL_CLOCK_VAL */
-
- /* Check the I2S parameters */
- assert_param(IS_SPI_23_PERIPH(SPIx));
- assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
- assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
- assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
- assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
- assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
- assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
-
-/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
- /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
- SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK;
- SPIx->I2SPR = 0x0002;
-
- /* Get the I2SCFGR register value */
- tmpreg = SPIx->I2SCFGR;
-
- /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
- if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
- {
- i2sodd = (uint16_t)0;
- i2sdiv = (uint16_t)2;
- }
- /* If the requested audio frequency is not the default, compute the prescaler */
- else
- {
- /* Check the frame length (For the Prescaler computing) *******************/
- if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
- {
- /* Packet length is 16 bits */
- packetlength = 1;
- }
- else
- {
- /* Packet length is 32 bits */
- packetlength = 2;
- }
-
- /* Get I2S source Clock frequency (only in Silicon RevisionB and RevisionY) */
-
- /* If an external I2S clock has to be used, this define should be set
- in the project configuration or in the stm32f2xx_conf.h file */
- #ifdef I2S_EXTERNAL_CLOCK_VAL
- /* Set external clock as I2S clock source */
- if ((RCC->CFGR & RCC_CFGR_I2SSRC) == 0)
- {
- RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC;
- }
-
- /* Set the I2S clock to the external clock value */
- i2sclk = I2S_EXTERNAL_CLOCK_VAL;
-
- #else /* There is no define for External I2S clock source */
- /* Set PLLI2S as I2S clock source */
- if ((RCC->CFGR & RCC_CFGR_I2SSRC) != 0)
- {
- RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC;
- }
-
- /* Get the PLLI2SN value */
- plln = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & \
- (RCC_PLLI2SCFGR_PLLI2SN >> 6));
-
- /* Get the PLLI2SR value */
- pllr = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & \
- (RCC_PLLI2SCFGR_PLLI2SR >> 28));
-
- /* Get the PLLM value */
- pllm = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
-
- /* Get the I2S source clock value */
- i2sclk = (uint32_t)(((HSE_VALUE / pllm) * plln) / pllr);
- #endif /* I2S_EXTERNAL_CLOCK_VAL */
-
- /* Compute the Real divider depending on the MCLK output state, with a floating point */
- if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
- {
- /* MCLK output is enabled */
- tmp = (uint16_t)(((((i2sclk / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
- }
- else
- {
- /* MCLK output is disabled */
- tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
- }
-
- /* Remove the flatting point */
- tmp = tmp / 10;
-
- /* Check the parity of the divider */
- i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
-
- /* Compute the i2sdiv prescaler */
- i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
-
- /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
- i2sodd = (uint16_t) (i2sodd << 8);
- }
-
- /* Test if the divider is 1 or 0 or greater than 0xFF */
- if ((i2sdiv < 2) || (i2sdiv > 0xFF))
- {
- /* Set the default values */
- i2sdiv = 2;
- i2sodd = 0;
- }
-
- /* Write to SPIx I2SPR register the computed value */
- SPIx->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
-
- /* Configure the I2S with the SPI_InitStruct values */
- tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \
- (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
- (uint16_t)I2S_InitStruct->I2S_CPOL))));
-
- /* Write to SPIx I2SCFGR */
- SPIx->I2SCFGR = tmpreg;
-}
-
-/**
- * @brief Fills each SPI_InitStruct member with its default value.
- * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
-{
-/*--------------- Reset SPI init structure parameters values -----------------*/
- /* Initialize the SPI_Direction member */
- SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
- /* initialize the SPI_Mode member */
- SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
- /* initialize the SPI_DataSize member */
- SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
- /* Initialize the SPI_CPOL member */
- SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
- /* Initialize the SPI_CPHA member */
- SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
- /* Initialize the SPI_NSS member */
- SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
- /* Initialize the SPI_BaudRatePrescaler member */
- SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
- /* Initialize the SPI_FirstBit member */
- SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
- /* Initialize the SPI_CRCPolynomial member */
- SPI_InitStruct->SPI_CRCPolynomial = 7;
-}
-
-/**
- * @brief Fills each I2S_InitStruct member with its default value.
- * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
-{
-/*--------------- Reset I2S init structure parameters values -----------------*/
- /* Initialize the I2S_Mode member */
- I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
-
- /* Initialize the I2S_Standard member */
- I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
-
- /* Initialize the I2S_DataFormat member */
- I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
-
- /* Initialize the I2S_MCLKOutput member */
- I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
-
- /* Initialize the I2S_AudioFreq member */
- I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
-
- /* Initialize the I2S_CPOL member */
- I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
-}
-
-/**
- * @brief Enables or disables the specified SPI peripheral.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param NewState: new state of the SPIx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI peripheral */
- SPIx->CR1 |= SPI_CR1_SPE;
- }
- else
- {
- /* Disable the selected SPI peripheral */
- SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);
- }
-}
-
-/**
- * @brief Enables or disables the specified SPI peripheral (in I2S mode).
- * @param SPIx: where x can be 2 or 3 to select the SPI peripheral.
- * @param NewState: new state of the SPIx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_23_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI peripheral (in I2S mode) */
- SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE;
- }
- else
- {
- /* Disable the selected SPI peripheral in I2S mode */
- SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE);
- }
-}
-
-/**
- * @brief Configures the data size for the selected SPI.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param SPI_DataSize: specifies the SPI data size.
- * This parameter can be one of the following values:
- * @arg SPI_DataSize_16b: Set data frame format to 16bit
- * @arg SPI_DataSize_8b: Set data frame format to 8bit
- * @retval None
- */
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_DATASIZE(SPI_DataSize));
- /* Clear DFF bit */
- SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;
- /* Set new DFF bit value */
- SPIx->CR1 |= SPI_DataSize;
-}
-
-/**
- * @brief Selects the data transfer direction in bidirectional mode for the specified SPI.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param SPI_Direction: specifies the data transfer direction in bidirectional mode.
- * This parameter can be one of the following values:
- * @arg SPI_Direction_Tx: Selects Tx transmission direction
- * @arg SPI_Direction_Rx: Selects Rx receive direction
- * @retval None
- */
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_DIRECTION(SPI_Direction));
- if (SPI_Direction == SPI_Direction_Tx)
- {
- /* Set the Tx only mode */
- SPIx->CR1 |= SPI_Direction_Tx;
- }
- else
- {
- /* Set the Rx only mode */
- SPIx->CR1 &= SPI_Direction_Rx;
- }
-}
-
-/**
- * @brief Configures internally by software the NSS pin for the selected SPI.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.
- * This parameter can be one of the following values:
- * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
- * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
- * @retval None
- */
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
- if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
- {
- /* Set NSS pin internally by software */
- SPIx->CR1 |= SPI_NSSInternalSoft_Set;
- }
- else
- {
- /* Reset NSS pin internally by software */
- SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the SS output for the selected SPI.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param NewState: new state of the SPIx SS output.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI SS output */
- SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE;
- }
- else
- {
- /* Disable the selected SPI SS output */
- SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);
- }
-}
-
-/**
- * @brief Enables or disables the SPIx/I2Sx DMA interface.
- *
- * @note This function can be called only after the SPI_Init() function has
- * been called.
- * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA
- * are not taken into consideration and are configured by hardware
- * respectively to the TI mode requirements.
- *
- * @param SPIx: where x can be 1, 2 or 3
- * @param NewState: new state of the selected SPI TI communication mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the TI mode for the selected SPI peripheral */
- SPIx->CR2 |= SPI_CR2_FRF;
- }
- else
- {
- /* Disable the TI mode for the selected SPI peripheral */
- SPIx->CR2 &= (uint16_t)~SPI_CR2_FRF;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Group2 Data transfers functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- Data transfers functions
- ===============================================================================
-
- This section provides a set of functions allowing to manage the SPI data transfers
-
- In reception, data are received and then stored into an internal Rx buffer while
- In transmission, data are first stored into an internal Tx buffer before being
- transmitted.
-
- The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData()
- function and returns the Rx buffered value. Whereas a write access to the SPI_DR
- can be done using SPI_I2S_SendData() function and stores the written data into
- Tx buffer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
- * in SPI mode or 2 or 3 in I2S mode.
- * @retval The value of the received data.
- */
-uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Return the data in the DR register */
- return SPIx->DR;
-}
-
-/**
- * @brief Transmits a Data through the SPIx/I2Sx peripheral.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
- * in SPI mode or 2 or 3 in I2S mode.
- * @param Data: Data to be transmitted.
- * @retval None
- */
-void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Write in the DR register the data to be sent */
- SPIx->DR = Data;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Group3 Hardware CRC Calculation functions
- * @brief Hardware CRC Calculation functions
- *
-@verbatim
- ===============================================================================
- Hardware CRC Calculation functions
- ===============================================================================
-
- This section provides a set of functions allowing to manage the SPI CRC hardware
- calculation
-
- SPI communication using CRC is possible through the following procedure:
- 1. Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler,
- Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
- function.
- 2. Enable the CRC calculation using the SPI_CalculateCRC() function.
- 3. Enable the SPI using the SPI_Cmd() function
- 4. Before writing the last data to the TX buffer, set the CRCNext bit using the
- SPI_TransmitCRC() function to indicate that after transmission of the last
- data, the CRC should be transmitted.
- 5. After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT
- bit is reset. The CRC is also received and compared against the SPI_RXCRCR
- value.
- If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt
- can be generated when the SPI_I2S_IT_ERR interrupt is enabled.
-
-@note It is advised not to read the calculated CRC values during the communication.
-
-@note When the SPI is in slave mode, be careful to enable CRC calculation only
- when the clock is stable, that is, when the clock is in the steady state.
- If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive
- to the SCK slave input clock as soon as CRCEN is set, and this, whatever
- the value of the SPE bit.
-
-@note With high bitrate frequencies, be careful when transmitting the CRC.
- As the number of used CPU cycles has to be as low as possible in the CRC
- transfer phase, it is forbidden to call software functions in the CRC
- transmission sequence to avoid errors in the last data and CRC reception.
- In fact, CRCNEXT bit has to be written before the end of the transmission/reception
- of the last data.
-
-@note For high bit rate frequencies, it is advised to use the DMA mode to avoid the
- degradation of the SPI speed performance due to CPU accesses impacting the
- SPI bandwidth.
-
-@note When the STM32F2xx is configured as slave and the NSS hardware mode is
- used, the NSS pin needs to be kept low between the data phase and the CRC
- phase.
-
-@note When the SPI is configured in slave mode with the CRC feature enabled, CRC
- calculation takes place even if a high level is applied on the NSS pin.
- This may happen for example in case of a multi-slave environment where the
- communication master addresses slaves alternately.
-
-@note Between a slave de-selection (high level on NSS) and a new slave selection
- (low level on NSS), the CRC value should be cleared on both master and slave
- sides in order to resynchronize the master and slave for their respective
- CRC calculation.
-
-@note To clear the CRC, follow the procedure below:
- 1. Disable SPI using the SPI_Cmd() function
- 2. Disable the CRC calculation using the SPI_CalculateCRC() function.
- 3. Enable the CRC calculation using the SPI_CalculateCRC() function.
- 4. Enable SPI using the SPI_Cmd() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the CRC value calculation of the transferred bytes.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param NewState: new state of the SPIx CRC value calculation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI CRC calculation */
- SPIx->CR1 |= SPI_CR1_CRCEN;
- }
- else
- {
- /* Disable the selected SPI CRC calculation */
- SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);
- }
-}
-
-/**
- * @brief Transmit the SPIx CRC value.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @retval None
- */
-void SPI_TransmitCRC(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Enable the selected SPI CRC transmission */
- SPIx->CR1 |= SPI_CR1_CRCNEXT;
-}
-
-/**
- * @brief Returns the transmit or the receive CRC register value for the specified SPI.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param SPI_CRC: specifies the CRC register to be read.
- * This parameter can be one of the following values:
- * @arg SPI_CRC_Tx: Selects Tx CRC register
- * @arg SPI_CRC_Rx: Selects Rx CRC register
- * @retval The selected CRC register value..
- */
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
-{
- uint16_t crcreg = 0;
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_CRC(SPI_CRC));
- if (SPI_CRC != SPI_CRC_Rx)
- {
- /* Get the Tx CRC register */
- crcreg = SPIx->TXCRCR;
- }
- else
- {
- /* Get the Rx CRC register */
- crcreg = SPIx->RXCRCR;
- }
- /* Return the selected CRC register */
- return crcreg;
-}
-
-/**
- * @brief Returns the CRC Polynomial register value for the specified SPI.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @retval The CRC Polynomial register value.
- */
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Return the CRC polynomial register */
- return SPIx->CRCPR;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Group4 DMA transfers management functions
- * @brief DMA transfers management functions
- *
-@verbatim
- ===============================================================================
- DMA transfers management functions
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the SPIx/I2Sx DMA interface.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
- * in SPI mode or 2 or 3 in I2S mode.
- * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
- * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
- * @param NewState: new state of the selected SPI DMA transfer request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI DMA requests */
- SPIx->CR2 |= SPI_I2S_DMAReq;
- }
- else
- {
- /* Disable the selected SPI DMA requests */
- SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Group5 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- Interrupts and flags management functions
- ===============================================================================
-
- This section provides a set of functions allowing to configure the SPI Interrupts
- sources and check or clear the flags or pending bits status.
- The user should identify which mode will be used in his application to manage
- the communication: Polling mode, Interrupt mode or DMA mode.
-
- Polling Mode
- =============
- In Polling Mode, the SPI/I2S communication can be managed by 9 flags:
- 1. SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register
- 2. SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register
- 3. SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI.
- 4. SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur
- 5. SPI_FLAG_MODF : to indicate if a Mode Fault error occur
- 6. SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur
- 7. I2S_FLAG_TIFRFE: to indicate a Frame Format error occurs.
- 8. I2S_FLAG_UDR: to indicate an Underrun error occurs.
- 9. I2S_FLAG_CHSIDE: to indicate Channel Side.
-
-@note Do not use the BSY flag to handle each data transmission or reception. It is
- better to use the TXE and RXNE flags instead.
-
- In this Mode it is advised to use the following functions:
- - FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
- - void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
-
- Interrupt Mode
- ===============
- In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources
- and 7 pending bits:
- Pending Bits:
- -------------
- 1. SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register
- 2. SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register
- 3. SPI_IT_CRCERR : to indicate if a CRC Calculation error occur (available in SPI mode only)
- 4. SPI_IT_MODF : to indicate if a Mode Fault error occur (available in SPI mode only)
- 5. SPI_I2S_IT_OVR : to indicate if an Overrun error occur
- 6. I2S_IT_UDR : to indicate an Underrun Error occurs (available in I2S mode only).
- 7. I2S_FLAG_TIFRFE : to indicate a Frame Format error occurs (available in TI mode only).
-
- Interrupt Source:
- -----------------
- 1. SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty
- interrupt.
- 2. SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not
- empty interrupt.
- 3. SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.
-
- In this Mode it is advised to use the following functions:
- - void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
- - ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
- - void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
-
- DMA Mode
- ========
- In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests:
- 1. SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request
- 2. SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request
-
- In this Mode it is advised to use the following function:
- - void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified SPI/I2S interrupts.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
- * in SPI mode or 2 or 3 in I2S mode.
- * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
- * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
- * @arg SPI_I2S_IT_ERR: Error interrupt mask
- * @param NewState: new state of the specified SPI interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
-{
- uint16_t itpos = 0, itmask = 0 ;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
-
- /* Get the SPI IT index */
- itpos = SPI_I2S_IT >> 4;
-
- /* Set the IT mask */
- itmask = (uint16_t)1 << (uint16_t)itpos;
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI interrupt */
- SPIx->CR2 |= itmask;
- }
- else
- {
- /* Disable the selected SPI interrupt */
- SPIx->CR2 &= (uint16_t)~itmask;
- }
-}
-
-/**
- * @brief Checks whether the specified SPIx/I2Sx flag is set or not.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
- * in SPI mode or 2 or 3 in I2S mode.
- * @param SPI_I2S_FLAG: specifies the SPI flag to check.
- * This parameter can be one of the following values:
- * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
- * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
- * @arg SPI_I2S_FLAG_BSY: Busy flag.
- * @arg SPI_I2S_FLAG_OVR: Overrun flag.
- * @arg SPI_FLAG_MODF: Mode Fault flag.
- * @arg SPI_FLAG_CRCERR: CRC Error flag.
- * @arg SPI_I2S_FLAG_TIFRFE: Format Error.
- * @arg I2S_FLAG_UDR: Underrun Error flag.
- * @arg I2S_FLAG_CHSIDE: Channel Side flag.
- * @retval The new state of SPI_I2S_FLAG (SET or RESET).
- */
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
-
- /* Check the status of the specified SPI flag */
- if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
- {
- /* SPI_I2S_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* SPI_I2S_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the SPI_I2S_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the SPIx CRC Error (CRCERR) flag.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
- * in SPI mode or 2 or 3 in I2S mode.
- * @param SPI_I2S_FLAG: specifies the SPI flag to clear.
- * This function clears only CRCERR flag.
- * @arg SPI_FLAG_CRCERR: CRC Error flag.
- *
- * @note OVR (OverRun error) flag is cleared by software sequence: a read
- * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read
- * operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
- * @note UDR (UnderRun error) flag is cleared by a read operation to
- * SPI_SR register (SPI_I2S_GetFlagStatus()).
- * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write
- * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a
- * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
- *
- * @retval None
- */
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
-
- /* Clear the selected SPI CRC Error (CRCERR) flag */
- SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
-}
-
-/**
- * @brief Checks whether the specified SPIx/I2Sx interrupt has occurred or not.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
- * in SPI mode or 2 or 3 in I2S mode.
- * @param SPI_I2S_IT: specifies the SPI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
- * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
- * @arg SPI_I2S_IT_OVR: Overrun interrupt.
- * @arg SPI_IT_MODF: Mode Fault interrupt.
- * @arg SPI_IT_CRCERR: CRC Error interrupt.
- * @arg I2S_IT_UDR: Underrun interrupt.
- * @arg SPI_I2S_IT_TIFRFE: Format Error interrupt.
- * @retval The new state of SPI_I2S_IT (SET or RESET).
- */
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
-{
- ITStatus bitstatus = RESET;
- uint16_t itpos = 0, itmask = 0, enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
-
- /* Get the SPI_I2S_IT index */
- itpos = 0x01 << (SPI_I2S_IT & 0x0F);
-
- /* Get the SPI_I2S_IT IT mask */
- itmask = SPI_I2S_IT >> 4;
-
- /* Set the IT mask */
- itmask = 0x01 << itmask;
-
- /* Get the SPI_I2S_IT enable bit status */
- enablestatus = (SPIx->CR2 & itmask) ;
-
- /* Check the status of the specified SPI interrupt */
- if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
- {
- /* SPI_I2S_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* SPI_I2S_IT is reset */
- bitstatus = RESET;
- }
- /* Return the SPI_I2S_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
- * in SPI mode or 2 or 3 in I2S mode.
- * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
- * This function clears only CRCERR interrupt pending bit.
- * @arg SPI_IT_CRCERR: CRC Error interrupt.
- *
- * @note OVR (OverRun Error) interrupt pending bit is cleared by software
- * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData())
- * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
- * @note UDR (UnderRun Error) interrupt pending bit is cleared by a read
- * operation to SPI_SR register (SPI_I2S_GetITStatus()).
- * @note MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
- * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus())
- * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable
- * the SPI).
- * @retval None
- */
-void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
-{
- uint16_t itpos = 0;
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));
-
- /* Get the SPI_I2S IT index */
- itpos = 0x01 << (SPI_I2S_IT & 0x0F);
-
- /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
- SPIx->SR = (uint16_t)~itpos;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/radio/src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_spi.c b/radio/src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_spi.c
index 033475e68..0a42a0f2c 100644
--- a/radio/src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_spi.c
+++ b/radio/src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_spi.c
@@ -113,8 +113,8 @@
*/
/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_spi.h"
-#include "stm32f2xx_rcc.h"
+#include "../inc/stm32f2xx_spi.h"
+#include "../inc/stm32f2xx_rcc.h"
/** @addtogroup STM32F2xx_StdPeriph_Driver
* @{