[sky9x] Issue 142 fixed
[sky9x] Tada was cut [sky9x] Issue 99 fixed [sky9x / gruvin9x] Menu popup has now a scrollbar on the right [sky9x] WDT was not working at all
This commit is contained in:
+43
-1
@@ -82,6 +82,49 @@ void dump(unsigned char *data, unsigned int size)
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debugPuts("\n\r");
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}
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/**
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* Configures a UART peripheral with the specified parameters.
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*
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* baudrate Baudrate at which the UART should operate (in Hz).
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* masterClock Frequency of the system master clock (in Hz).
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* uses PA9 and PA10, RXD2 and TXD2
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*/
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void DEBUG_UART_Configure( uint32_t baudrate, uint32_t masterClock)
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{
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register Uart *pUart = CONSOLE_USART;
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/* Configure PIO */
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configure_pins( (PIO_PA9 | PIO_PA10), PIN_PERIPHERAL | PIN_INPUT | PIN_PER_A | PIN_PORTA | PIN_NO_PULLUP ) ;
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/* Configure PMC */
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PMC->PMC_PCER0 = 1 << CONSOLE_ID;
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/* Reset and disable receiver & transmitter */
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pUart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX
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| UART_CR_RXDIS | UART_CR_TXDIS;
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/* Configure mode */
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pUart->UART_MR = 0x800 ; // NORMAL, No Parity
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/* Configure baudrate */
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/* Asynchronous, no oversampling */
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pUart->UART_BRGR = (masterClock / baudrate) / 16;
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/* Disable PDC channel */
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pUart->UART_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS;
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/* Enable receiver and transmitter */
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pUart->UART_CR = UART_CR_RXEN | UART_CR_TXEN;
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pUart->UART_IER = UART_IER_RXRDY ;
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NVIC_EnableIRQ(UART0_IRQn) ;
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}
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void DEBUG_UART_Stop()
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{
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CONSOLE_USART->UART_IDR = UART_IDR_RXRDY ;
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NVIC_DisableIRQ(UART0_IRQn) ;
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}
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Fifo32 debugFifo;
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extern "C" void UART0_IRQHandler()
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@@ -89,7 +132,6 @@ extern "C" void UART0_IRQHandler()
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debugFifo.push(CONSOLE_USART->UART_RHR);
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}
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void debugTask(void* pdata)
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{
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uint8_t rxchar ;
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@@ -34,6 +34,8 @@
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#ifndef debug_h
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#define debug_h
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#include <inttypes.h>
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#if defined(DEBUG)
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#ifdef __cplusplus
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@@ -57,6 +59,9 @@ void dump(unsigned char *data, unsigned int size);
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#define TRACE_ERROR(...) debugPuts("-E- " __VA_ARGS__)
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#define DUMP(data, size) dump(data, size)
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void DEBUG_UART_Configure( uint32_t baudrate, uint32_t masterClock);
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void DEBUG_UART_Stop();
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void debugTask(void* pdata);
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#else
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@@ -70,6 +75,9 @@ void debugTask(void* pdata);
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#define TRACE_ERROR(...) { }
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#define DUMP(...) { }
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#define DEBUG_UART_Configure(...)
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#define DEBUG_UART_Stop(...)
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#endif
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#endif
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+14
-66
@@ -86,9 +86,7 @@ uint32_t Card_SCR[2] ;
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uint32_t Card_CSD[4] ;
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int32_t Card_state = SD_ST_STARTUP ;
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volatile uint32_t Card_initialized = 0;
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uint32_t Sd_128_resp[4] ;
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uint32_t Sd_rca ;
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uint32_t Cmd_8_resp ;
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uint32_t Cmd_A41_resp ;
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uint8_t cardType;
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uint32_t transSpeed;
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@@ -1102,8 +1100,6 @@ uint32_t sd_card_mounted( void )
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uint32_t sd_read_block(uint32_t block_no, uint32_t *data)
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{
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uint32_t result = 0;
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// int32_t retry;
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unsigned int status = 0;
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// TRACE_ERROR("read block %d", block_no);
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@@ -1132,24 +1128,24 @@ uint32_t sd_read_block(uint32_t block_no, uint32_t *data)
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while (1) {
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if ((HSMCI->HSMCI_SR & (HSMCI_SR_ENDRX|HSMCI_SR_XFRDONE)) == (HSMCI_SR_ENDRX|HSMCI_SR_XFRDONE)) {
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result = 1;
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break;
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}
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}
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}
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/* Disable PDC */
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HSMCI->HSMCI_MR &= ~(uint32_t)HSMCI_MR_PDCMODE;
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HSMCI->HSMCI_PTCR = HSMCI_PTCR_RXTDIS | HSMCI_PTCR_TXTDIS;
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/* Disable PDC */
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HSMCI->HSMCI_MR &= ~(uint32_t)HSMCI_MR_PDCMODE;
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HSMCI->HSMCI_PTCR = HSMCI_PTCR_RXTDIS | HSMCI_PTCR_TXTDIS;
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return 1;
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}
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// TRACE_ERROR("ok %.2X %.4Xd\n\r", HSMCI->HSMCI_SR, HSMCI->HSMCI_RSPR[0]);
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return result;
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return 0;
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}
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uint32_t sd_write_block( uint32_t block_no, uint32_t *data )
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{
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uint32_t result = 0;
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unsigned int status = 0;
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if (sd_card_ready()) {
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@@ -1167,7 +1163,6 @@ uint32_t sd_write_block( uint32_t block_no, uint32_t *data )
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HSMCI->HSMCI_ARGR = (Cmd_A41_resp & OCR_SD_CCS ? block_no : (block_no << 9));
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HSMCI->HSMCI_TPR = (uint32_t)data;
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HSMCI->HSMCI_TCR = 512 / 4;
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// HSMCI->HSMCI_PTCR = HSMCI_PTCR_TXTEN;
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HSMCI->HSMCI_CMDR = SD_WRITE_SINGLE_BLOCK;
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while (!(HSMCI->HSMCI_SR & HSMCI_SR_CMDRDY));
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@@ -1178,17 +1173,18 @@ uint32_t sd_write_block( uint32_t block_no, uint32_t *data )
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while (1) {
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if ((HSMCI->HSMCI_SR & (HSMCI_SR_NOTBUSY|HSMCI_SR_XFRDONE)) == (HSMCI_SR_NOTBUSY|HSMCI_SR_XFRDONE)) {
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result = 1;
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break;
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}
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}
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/* Disable PDC */
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HSMCI->HSMCI_PTCR = HSMCI_PTCR_RXTDIS | HSMCI_PTCR_TXTDIS;
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HSMCI->HSMCI_MR &= ~(uint32_t)HSMCI_MR_PDCMODE;
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return 1;
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}
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/* Disable PDC */
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HSMCI->HSMCI_PTCR = HSMCI_PTCR_RXTDIS | HSMCI_PTCR_TXTDIS;
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HSMCI->HSMCI_MR &= ~(uint32_t)HSMCI_MR_PDCMODE;
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return result;
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return 0;
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}
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/*
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@@ -1237,54 +1233,6 @@ DSTATUS disk_initialize (
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if (drv) return STA_NOINIT; /* Supports only single drive */
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if ( sd_card_ready() == 0 ) return RES_NOTRDY;
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return RES_OK;
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#if 0
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BYTE n, cmd, ty, ocr[4];
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if (drv) return STA_NOINIT; /* Supports only single drive */
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if (Stat & STA_NODISK) return Stat; /* No card in the socket */
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power_on(); /* Force socket power on */
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FCLK_SLOW();
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for (n = 10; n; n--) rcvr_spi(); /* 80 dummy clocks */
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ty = 0;
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if (send_cmd(CMD0, 0) == 1) { /* Enter Idle state */
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Timer1 = 100; /* Initialization timeout of 1000 msec */
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if (send_cmd(CMD8, 0x1AA) == 1) { /* SDv2? */
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for (n = 0; n < 4; n++) ocr[n] = rcvr_spi(); /* Get trailing return value of R7 resp */
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if (ocr[2] == 0x01 && ocr[3] == 0xAA) { /* The card can work at vdd range of 2.7-3.6V */
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while (Timer1 && send_cmd(ACMD41, 1UL << 30)); /* Wait for leaving idle state (ACMD41 with HCS bit) */
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if (Timer1 && send_cmd(CMD58, 0) == 0) { /* Check CCS bit in the OCR */
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for (n = 0; n < 4; n++) ocr[n] = rcvr_spi();
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ty = (ocr[0] & 0x40) ? CT_SD2 | CT_BLOCK : CT_SD2; /* SDv2 */
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}
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}
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} else { /* SDv1 or MMCv3 */
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if (send_cmd(ACMD41, 0) <= 1) {
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ty = CT_SD1; cmd = ACMD41; /* SDv1 */
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} else {
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ty = CT_MMC; cmd = CMD1; /* MMCv3 */
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}
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while (Timer1 && send_cmd(cmd, 0)); /* Wait for leaving idle state */
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if (!Timer1 || send_cmd(CMD16, 512) != 0) /* Set R/W block length to 512 */
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ty = 0;
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}
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}
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CardType = ty;
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deselect();
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if (ty) { /* Initialization succeded */
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Stat &= ~STA_NOINIT; /* Clear STA_NOINIT */
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FCLK_FAST();
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} else { /* Initialization failed */
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power_off();
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}
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return Stat;
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#endif
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}
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/*-----------------------------------------------------------------------*/
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